mirror of
https://github.com/libretro/ppsspp.git
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534 lines
12 KiB
C++
534 lines
12 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <map>
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#include "../../Globals.h"
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#include "MIPS.h"
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#include "MIPSTables.h"
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#include "MIPSAnalyst.h"
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#include "MIPSCodeUtils.h"
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#include "../Debugger/SymbolMap.h"
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using namespace MIPSCodeUtils;
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using namespace std;
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namespace MIPSAnalyst
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{
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RegisterAnalysisResults regAnal[32];
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RegisterAnalysisResults total[32];
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int numAnalysisDone=0;
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int GetOutReg(u32 op)
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{
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u32 opinfo = MIPSGetInfo(op);
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if (opinfo & OUT_RT)
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return MIPS_GET_RT(op);
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if (opinfo & OUT_RD)
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return MIPS_GET_RD(op);
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if (opinfo & OUT_RA)
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return MIPS_REG_RA;
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return -1;
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}
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bool ReadsFromReg(u32 op, u32 reg)
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{
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u32 opinfo = MIPSGetInfo(op);
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if (opinfo & IN_RT)
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{
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if (MIPS_GET_RT(opinfo) == reg)
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return true;
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}
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if (opinfo & (IN_RS | IN_RS_ADDR | IN_RS_SHIFT))
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{
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if (MIPS_GET_RS(opinfo) == reg)
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return true;
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}
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return false; //TODO: there are more cases!
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}
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// TODO: Remove me?
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bool IsDelaySlotNice(u32 branch, u32 delayslot)
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{
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int outReg = GetOutReg(delayslot);
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if (outReg != -1)
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{
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if (ReadsFromReg(branch, outReg))
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{
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return false; //evil :(
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}
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else
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{
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return false; //aggh this should be true but doesn't work
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}
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}
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else
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{
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// Check for FPU flag
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if ((MIPSGetInfo(delayslot) & OUT_FPUFLAG) && (MIPSGetInfo(branch) & IN_FPUFLAG))
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return false;
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return true; //nice :)
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}
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}
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// Temporary, returns true for common ops which have proper flags in the table.
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bool IsDelaySlotInfoSafe(u32 op)
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{
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const char *safeOps[] = {
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"addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui",
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"lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr",
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"sb", "sh", "swl", "sw", "swr",
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"sll", "srl", "sra", "sllv", "srlv", "srav",
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"add", "addu", "sub", "subu", "and", "or", "xor", "nor",
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"slt", "sltu",
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};
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const char *opName = MIPSGetName(op);
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for (size_t i = 0; i < ARRAY_SIZE(safeOps); ++i)
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{
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if (!strcmp(safeOps[i], opName))
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return true;
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}
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return false;
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}
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bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2)
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{
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// NOOPs are always nice.
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if (op == 0)
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return true;
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// TODO: Once the flags are all correct on the tables, remove this safety.
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if (IsDelaySlotInfoSafe(op))
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{
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// $0 is never an out reg, it's always 0.
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if (reg1 != 0 && GetOutReg(op) == reg1)
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return false;
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if (reg2 != 0 && GetOutReg(op) == reg2)
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return false;
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return true;
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}
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return false;
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}
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bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op)
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{
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// NOOPs are always nice.
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if (op == 0)
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return true;
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// TODO: Once the flags are all correct on the tables, remove this safety.
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if (IsDelaySlotInfoSafe(op))
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{
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// TODO: There may be IS_VFPU cases which are safe...
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return (MIPSGetInfo(op) & IS_VFPU) == 0;
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}
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return false;
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}
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bool IsDelaySlotNiceFPU(u32 branchOp, u32 op)
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{
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// NOOPs are always nice.
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if (op == 0)
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return true;
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// TODO: Once the flags are all correct on the tables, remove this safety.
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if (IsDelaySlotInfoSafe(op))
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return (MIPSGetInfo(op) & OUT_FPUFLAG) == 0;
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return false;
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}
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bool IsSyscall(u32 op)
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{
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// Syscalls look like this: 0000 00-- ---- ---- ---- --00 1100
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return (op >> 26) == 0 && (op & 0x3f) == 12;
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}
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void Analyze(u32 address)
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{
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//set everything to -1 (FF)
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memset(regAnal, 255, sizeof(AnalysisResults)*32);
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for (int i=0; i<32; i++)
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{
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regAnal[i].used=false;
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regAnal[i].readCount=0;
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regAnal[i].writeCount=0;
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regAnal[i].readAsAddrCount=0;
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}
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u32 addr = address;
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bool exitFlag = false;
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while (true)
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{
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u32 op = Memory::Read_Instruction(addr);
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u32 info = MIPSGetInfo(op);
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for (int reg=0; reg < 32; reg++)
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{
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int rs = MIPS_GET_RS(op);
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int rt = MIPS_GET_RT(op);
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int rd = MIPS_GET_RD(op);
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if (
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((info & IN_RS) && (rs == reg)) ||
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((info & IN_RS_SHIFT) && (rs == reg)) ||
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((info & IN_RT) && (rt == reg)))
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{
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if (regAnal[reg].firstRead == -1)
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regAnal[reg].firstRead = addr;
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regAnal[reg].lastRead = addr;
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regAnal[reg].readCount++;
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regAnal[reg].used=true;
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}
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if (
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((info & IN_RS_ADDR) && (rs == reg))
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)
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{
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if (regAnal[reg].firstReadAsAddr == -1)
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regAnal[reg].firstReadAsAddr = addr;
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regAnal[reg].lastReadAsAddr = addr;
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regAnal[reg].readAsAddrCount++;
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regAnal[reg].used=true;
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}
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if (
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((info & OUT_RT) && (rt == reg)) ||
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((info & OUT_RD) && (rd == reg)) ||
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((info & OUT_RA) && (reg == MIPS_REG_RA))
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)
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{
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if (regAnal[reg].firstWrite == -1)
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regAnal[reg].firstWrite = addr;
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regAnal[reg].lastWrite = addr;
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regAnal[reg].writeCount++;
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regAnal[reg].used=true;
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}
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}
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if (exitFlag) //delay slot done, let's quit!
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break;
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if ((info & IS_JUMP) || (info & IS_CONDBRANCH))
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{
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exitFlag = true; // now do the delay slot
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}
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addr += 4;
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}
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int numUsedRegs=0;
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static int totalUsedRegs=0;
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static int numAnalyzings=0;
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for (int i=0; i<32; i++)
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{
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if (regAnal[i].used)
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numUsedRegs++;
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}
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totalUsedRegs+=numUsedRegs;
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numAnalyzings++;
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DEBUG_LOG(CPU,"[ %08x ] Used regs: %i Average: %f",address,numUsedRegs,(float)totalUsedRegs/(float)numAnalyzings);
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}
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struct Function
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{
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u32 start;
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u32 end;
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u32 hash;
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u32 size;
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bool isStraightLeaf;
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bool hasHash;
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bool usesVFPU;
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char name[64];
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};
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vector<Function> functions;
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map<u32, Function*> hashToFunction;
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void Shutdown()
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{
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functions.clear();
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hashToFunction.clear();
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}
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// hm pointless :P
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void UpdateHashToFunctionMap()
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{
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hashToFunction.clear();
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for (vector<Function>::iterator iter = functions.begin(); iter != functions.end(); iter++)
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{
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Function &f = *iter;
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if (f.hasHash)
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{
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hashToFunction[f.hash] = &f;
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}
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}
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}
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bool IsRegisterUsed(u32 reg, u32 addr)
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{
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while (true)
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{
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u32 op = Memory::Read_Instruction(addr);
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u32 info = MIPSGetInfo(op);
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if (
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((info & IN_RS) ||
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(info & IN_RS_SHIFT) ||
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(info & IN_RS_ADDR))
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&&
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(MIPS_GET_RS(op) == reg)
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)
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return true;
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if ((info & IN_RT) && (MIPS_GET_RT(op) == reg))
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return true;
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if ((info & IS_CONDBRANCH))
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return true; // could also follow both paths
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if ((info & IS_JUMP))
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return true; // could also follow the path
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if ((info & OUT_RT) && (MIPS_GET_RT(op) == reg))
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return false; //the reg got clobbed! yay!
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if ((info & OUT_RD) && (MIPS_GET_RD(op) == reg))
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return false; //the reg got clobbed! yay!
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if ((info & OUT_RA) && (reg == MIPS_REG_RA))
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return false; //the reg got clobbed! yay!
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addr+=4;
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}
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return true;
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}
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void HashFunctions()
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{
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for (vector<Function>::iterator iter = functions.begin(); iter!=functions.end(); iter++)
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{
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Function &f=*iter;
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u32 hash = 0x1337babe;
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for (u32 addr = f.start; addr <= f.end; addr += 4)
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{
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u32 validbits = 0xFFFFFFFF;
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u32 instr = Memory::Read_Instruction(addr);
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u32 flags = MIPSGetInfo(instr);
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if (flags & IN_IMM16)
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validbits&=~0xFFFF;
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if (flags & IN_IMM26)
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validbits&=~0x3FFFFFF;
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hash = __rotl(hash,13);
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hash ^= (instr&validbits);
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}
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f.hash=hash;
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f.hasHash=true;
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}
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}
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void ScanForFunctions(u32 startAddr, u32 endAddr /*, std::vector<u32> knownEntries*/)
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{
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Function currentFunction = {startAddr};
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u32 furthestBranch = 0;
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bool looking = false;
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bool end = false;
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bool isStraightLeaf=true;
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u32 addr;
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for (addr = startAddr; addr<=endAddr; addr+=4)
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{
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SymbolInfo syminfo;
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if (symbolMap.GetSymbolInfo(&syminfo, addr, ST_FUNCTION))
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{
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addr = syminfo.address + syminfo.size;
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continue;
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}
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u32 op = Memory::Read_Instruction(addr);
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u32 target = GetBranchTargetNoRA(addr);
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if (target != INVALIDTARGET)
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{
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isStraightLeaf = false;
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if (target > furthestBranch)
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{
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furthestBranch = target;
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}
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}
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if (op == MIPS_MAKE_JR_RA())
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{
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if (furthestBranch >= addr)
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{
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looking = true;
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addr+=4;
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}
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else
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{
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end = true;
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}
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}
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if (looking)
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{
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if (addr >= furthestBranch)
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{
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u32 sureTarget = GetSureBranchTarget(addr);
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if (sureTarget != INVALIDTARGET && sureTarget < addr)
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{
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end = true;
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}
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sureTarget = GetJumpTarget(addr);
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if (sureTarget != INVALIDTARGET && sureTarget < addr && ((op&0xFC000000)==0x08000000))
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{
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end = true;
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}
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//end = true;
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}
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}
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if (end)
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{
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currentFunction.end = addr + 4;
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currentFunction.isStraightLeaf = isStraightLeaf;
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functions.push_back(currentFunction);
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furthestBranch = 0;
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addr += 4;
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looking = false;
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end = false;
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isStraightLeaf=true;
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currentFunction.start = addr+4;
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}
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}
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currentFunction.end = addr + 4;
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functions.push_back(currentFunction);
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for (vector<Function>::iterator iter = functions.begin(); iter!=functions.end(); iter++)
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{
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(*iter).size = ((*iter).end-(*iter).start+4);
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char temp[256];
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sprintf(temp,"z_un_%08x",(*iter).start);
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symbolMap.AddSymbol(std::string(temp).c_str(), (*iter).start,(*iter).end-(*iter).start+4,ST_FUNCTION);
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}
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HashFunctions();
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}
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struct HashMapFunc
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{
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char name[64];
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u32 hash;
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u32 size; //number of bytes
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};
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void StoreHashMap(const char *filename)
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{
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FILE *file = fopen(filename,"wb");
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u32 num = 0;
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if(fwrite(&num,4,1,file) != 1) //fill in later
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WARN_LOG(CPU, "Could not store hash map %s", filename);
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for (vector<Function>::iterator iter = functions.begin(); iter!=functions.end(); iter++)
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{
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Function &f=*iter;
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if (f.hasHash && f.size>=12)
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{
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HashMapFunc temp;
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memset(&temp,0,sizeof(temp));
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strcpy(temp.name, f.name);
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temp.hash=f.hash;
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temp.size=f.size;
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if(fwrite((char*)&temp,sizeof(temp),1,file) != 1) {
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WARN_LOG(CPU, "Could not store hash map %s", filename);
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break;
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}
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num++;
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}
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}
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fseek(file,0,SEEK_SET);
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if(fwrite(&num,4,1,file) != 1) //fill in later
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WARN_LOG(CPU, "Could not store hash map %s", filename);
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fclose(file);
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}
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void LoadHashMap(const char *filename)
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{
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HashFunctions();
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UpdateHashToFunctionMap();
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FILE *file = fopen(filename, "rb");
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int num;
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if(fread(&num,4,1,file) == 1) {
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for (int i=0; i<num; i++)
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{
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HashMapFunc temp;
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if(fread(&temp,sizeof(temp),1,file) == 1) {
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map<u32,Function*>::iterator iter = hashToFunction.find(temp.hash);
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if (iter != hashToFunction.end())
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{
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//yay, found a function!
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Function &f = *(iter->second);
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if (f.size==temp.size)
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{
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strcpy(f.name, temp.name);
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f.hash=temp.hash;
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f.size=temp.size;
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}
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}
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}
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}
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}
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fclose(file);
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}
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void CompileLeafs()
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{
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/*
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int count=0;
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for (vector<Function>::iterator iter = functions.begin(); iter!=functions.end(); iter++)
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{
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Function &f = *iter;
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if (f.isStraightLeaf)
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{
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MIPSComp::CompileAt(f.start);
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count++;
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}
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}
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LOG(CPU,"Precompiled %i straight leaf functions",count);*/
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}
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std::vector<int> GetInputRegs(u32 op)
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{
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std::vector<int> vec;
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u32 info = MIPSGetInfo(op);
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if ((info & IS_VFPU) == 0)
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{
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if (info & IN_RS) vec.push_back(MIPS_GET_RS(op));
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if (info & IN_RT) vec.push_back(MIPS_GET_RT(op));
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}
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return vec;
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}
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std::vector<int> GetOutputRegs(u32 op)
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{
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std::vector<int> vec;
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u32 info = MIPSGetInfo(op);
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if ((info & IS_VFPU) == 0)
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{
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if (info & OUT_RD) vec.push_back(MIPS_GET_RD(op));
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if (info & OUT_RT) vec.push_back(MIPS_GET_RT(op));
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if (info & OUT_RA) vec.push_back(MIPS_REG_RA);
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}
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return vec;
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}
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}
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