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https://github.com/libretro/ppsspp.git
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eeff110c0f
Now the same logic on x86 and ARM, and handles HI/LO/etc. better.
128 lines
3.3 KiB
C++
128 lines
3.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Common/x64Emitter.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#ifdef _M_X64
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#define NUM_X_REGS 16
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#elif _M_IX86
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#define NUM_X_REGS 8
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#endif
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#define NUM_MIPS_GPRS 36
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#ifdef _M_X64
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#define CTXREG R14
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#else
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#define CTXREG EBP
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#endif
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// This must be one of EAX, EBX, ECX, EDX as they have 8-bit subregisters.
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#define TEMPREG EAX
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struct MIPSCachedReg {
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Gen::OpArg location;
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bool away; // value not in source register
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bool locked;
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};
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struct X64CachedReg {
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MIPSGPReg mipsReg;
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bool dirty;
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bool free;
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bool allocLocked;
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};
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struct GPRRegCacheState {
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MIPSCachedReg regs[NUM_MIPS_GPRS];
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X64CachedReg xregs[NUM_X_REGS];
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};
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namespace MIPSComp {
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struct JitOptions;
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struct JitState;
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}
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class GPRRegCache
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{
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public:
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GPRRegCache();
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~GPRRegCache() {}
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void Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats);
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void DiscardRegContentsIfCached(MIPSGPReg preg);
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void SetEmitter(Gen::XEmitter *emitter) {emit = emitter;}
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void FlushR(Gen::X64Reg reg);
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void FlushLockX(Gen::X64Reg reg) {
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FlushR(reg);
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LockX(reg);
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}
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void FlushLockX(Gen::X64Reg reg1, Gen::X64Reg reg2) {
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FlushR(reg1); FlushR(reg2);
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LockX(reg1); LockX(reg2);
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}
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void Flush();
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void FlushBeforeCall();
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int SanityCheck() const;
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void KillImmediate(MIPSGPReg preg, bool doLoad, bool makeDirty);
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void MapReg(MIPSGPReg preg, bool doLoad = true, bool makeDirty = true);
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void StoreFromRegister(MIPSGPReg preg);
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const Gen::OpArg &R(MIPSGPReg preg) const {return regs[preg].location;}
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Gen::X64Reg RX(MIPSGPReg preg) const
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{
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if (regs[preg].away && regs[preg].location.IsSimpleReg())
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return regs[preg].location.GetSimpleReg();
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PanicAlert("Not so simple - %i", preg);
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return (Gen::X64Reg)-1;
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}
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Gen::OpArg GetDefaultLocation(MIPSGPReg reg) const;
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// Register locking.
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void Lock(MIPSGPReg p1, MIPSGPReg p2 = MIPS_REG_INVALID, MIPSGPReg p3 = MIPS_REG_INVALID, MIPSGPReg p4 = MIPS_REG_INVALID);
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void LockX(int x1, int x2=0xff, int x3=0xff, int x4=0xff);
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void UnlockAll();
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void UnlockAllX();
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void SetImm(MIPSGPReg preg, u32 immValue);
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bool IsImm(MIPSGPReg preg) const;
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u32 GetImm(MIPSGPReg preg) const;
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void GetState(GPRRegCacheState &state) const;
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void RestoreState(const GPRRegCacheState state);
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MIPSState *mips;
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private:
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Gen::X64Reg GetFreeXReg();
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Gen::X64Reg FindBestToSpill(bool unusedOnly);
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const int *GetAllocationOrder(int &count);
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MIPSCachedReg regs[NUM_MIPS_GPRS];
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X64CachedReg xregs[NUM_X_REGS];
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Gen::XEmitter *emit;
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MIPSComp::JitState *js_;
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MIPSComp::JitOptions *jo_;
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};
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