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AUDIO: Support 96kHz audio rates in ARM assembler rate conversion.

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This should be the same changes as fuzzie's previous commit to the C++
version.
This commit is contained in:
D G Turner 2014-06-01 21:58:28 +01:00
parent 8f5a7cde2f
commit 9003ce517f
2 changed files with 33 additions and 22 deletions
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21
audio/rate_arm.cpp
View File

@ -68,6 +68,16 @@ namespace Audio {
*/
#define INTERMEDIATE_BUFFER_SIZE 512
/**
* The default fractional type in frac.h (with 16 fractional bits) limits
* the rate conversion code to 65536Hz audio: we need to able to handle
* 96kHz audio, so we use fewer fractional bits in this code.
*/
enum {
FRAC_BITS_LOW = 15,
FRAC_ONE_LOW = (1L << FRAC_BITS_LOW),
FRAC_HALF_LOW = (1L << (FRAC_BITS_LOW-1))
};
/**
* Audio rate converter based on simple resampling. Used when no
@ -287,17 +297,18 @@ LinearRateConverter<stereo, reverseStereo>::LinearRateConverter(st_rate_t inrate
error("Input and Output rates must be different to use rate effect");
}
if (inrate >= 65536 || outrate >= 65536) {
error("rate effect can only handle rates < 65536");
if (inrate >= 131072 || outrate >= 131072) {
error("rate effect can only handle rates < 131072");
}
lr.opos = FRAC_ONE;
lr.opos = FRAC_ONE_LOW;
/* increment */
incr = (inrate << FRAC_BITS) / outrate;
incr = (inrate << FRAC_BITS_LOW) / outrate;
lr.opos_inc = incr;
// FIXME: Does 32768 here need changing to 65536 or 0? Compare to rate.cpp code...
lr.ilast[0] = lr.ilast[1] = 32768;
lr.icur[0] = lr.icur[1] = 0;
@ -438,7 +449,7 @@ public:
*/
RateConverter *makeRateConverter(st_rate_t inrate, st_rate_t outrate, bool stereo, bool reverseStereo) {
if (inrate != outrate) {
if ((inrate % outrate) == 0) {
if ((inrate % outrate) == 0 && (inrate < 65536)) {
if (stereo) {
if (reverseStereo)
return new SimpleRateConverter<true, true>(inrate, outrate);

34
audio/rate_arm_asm.s
View File

@ -434,17 +434,17 @@ LinearRate_M_part2:
LDRSH r4, [r3] @ r4 = obuf[0]
LDRSH r5, [r3,#2] @ r5 = obuf[1]
MOV r6, r6, ASR #16 @ r6 = tmp0 = tmp1 >>= 16
MOV r6, r6, ASR #15 @ r6 = tmp0 = tmp1 >>= 15
MUL r7, r12,r6 @ r7 = tmp0*vol_l
MUL r6, r14,r6 @ r6 = tmp1*vol_r
ADDS r7, r7, r4, LSL #16 @ r7 = obuf[0]<<16 + tmp0*vol_l
ADDS r7, r7, r4, LSL #15 @ r7 = obuf[0]<<15 + tmp0*vol_l
RSCVS r7, r10, #0x80000000 @ Clamp r7
ADDS r6, r6, r5, LSL #16 @ r6 = obuf[1]<<16 + tmp1*vol_r
ADDS r6, r6, r5, LSL #15 @ r6 = obuf[1]<<15 + tmp1*vol_r
RSCVS r6, r10, #0x80000000 @ Clamp r6
MOV r7, r7, LSR #16 @ Shift back to halfword
MOV r6, r6, LSR #16 @ Shift back to halfword
MOV r7, r7, LSR #15 @ Shift back to halfword
MOV r6, r6, LSR #15 @ Shift back to halfword
LDR r5, [r2,#12] @ r5 = opos_inc
STRH r7, [r3],#2 @ Store output value
@ -530,23 +530,23 @@ LinearRate_S_part2:
LDR r7, [r2,#24] @ r7 = ilast[1]<<16 + 32768
LDRSH r5, [r2,#18] @ r5 = icur[1]
LDRSH r10,[r3] @ r10= obuf[0]
MOV r6, r6, ASR #16 @ r6 = tmp1 >>= 16
MOV r6, r6, ASR #15 @ r6 = tmp1 >>= 15
SUB r5, r5, r7, ASR #16 @ r5 = icur[1] - ilast[1]
MLA r7, r4, r5, r7 @ r7 = (icur[1]-ilast[1])*opos_frac+ilast[1]
LDRSH r5, [r3,#2] @ r5 = obuf[1]
MOV r7, r7, ASR #16 @ r7 = tmp0 >>= 16
MOV r7, r7, ASR #15 @ r7 = tmp0 >>= 15
MUL r7, r12,r7 @ r7 = tmp0*vol_l
MUL r6, r14,r6 @ r6 = tmp1*vol_r
ADDS r7, r7, r10, LSL #16 @ r7 = obuf[0]<<16 + tmp0*vol_l
ADDS r7, r7, r10, LSL #15 @ r7 = obuf[0]<<15 + tmp0*vol_l
MOV r4, #0
RSCVS r7, r4, #0x80000000 @ Clamp r7
ADDS r6, r6, r5, LSL #16 @ r6 = obuf[1]<<16 + tmp1*vol_r
ADDS r6, r6, r5, LSL #15 @ r6 = obuf[1]<<15 + tmp1*vol_r
RSCVS r6, r4, #0x80000000 @ Clamp r6
MOV r7, r7, LSR #16 @ Shift back to halfword
MOV r6, r6, LSR #16 @ Shift back to halfword
MOV r7, r7, LSR #15 @ Shift back to halfword
MOV r6, r6, LSR #15 @ Shift back to halfword
LDR r5, [r2,#12] @ r5 = opos_inc
STRH r7, [r3],#2 @ Store output value
@ -632,23 +632,23 @@ LinearRate_R_part2:
LDR r7, [r2,#24] @ r7 = ilast[1]<<16 + 32768
LDRSH r5, [r2,#18] @ r5 = icur[1]
LDRSH r10,[r3,#2] @ r10= obuf[1]
MOV r6, r6, ASR #16 @ r6 = tmp1 >>= 16
MOV r6, r6, ASR #15 @ r6 = tmp1 >>= 15
SUB r5, r5, r7, ASR #16 @ r5 = icur[1] - ilast[1]
MLA r7, r4, r5, r7 @ r7 = (icur[1]-ilast[1])*opos_frac+ilast[1]
LDRSH r5, [r3] @ r5 = obuf[0]
MOV r7, r7, ASR #16 @ r7 = tmp0 >>= 16
MOV r7, r7, ASR #15 @ r7 = tmp0 >>= 15
MUL r7, r12,r7 @ r7 = tmp0*vol_l
MUL r6, r14,r6 @ r6 = tmp1*vol_r
ADDS r7, r7, r10, LSL #16 @ r7 = obuf[1]<<16 + tmp0*vol_l
ADDS r7, r7, r10, LSL #15 @ r7 = obuf[1]<<15 + tmp0*vol_l
MOV r4, #0
RSCVS r7, r4, #0x80000000 @ Clamp r7
ADDS r6, r6, r5, LSL #16 @ r6 = obuf[0]<<16 + tmp1*vol_r
ADDS r6, r6, r5, LSL #15 @ r6 = obuf[0]<<15 + tmp1*vol_r
RSCVS r6, r4, #0x80000000 @ Clamp r6
MOV r7, r7, LSR #16 @ Shift back to halfword
MOV r6, r6, LSR #16 @ Shift back to halfword
MOV r7, r7, LSR #15 @ Shift back to halfword
MOV r6, r6, LSR #15 @ Shift back to halfword
LDR r5, [r2,#12] @ r5 = opos_inc
STRH r6, [r3],#2 @ Store output value