mirror of
https://github.com/libretro/snes9x.git
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816 lines
16 KiB
C++
816 lines
16 KiB
C++
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#include "snes9x.h"
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#include "memmap.h"
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#include "fxinst.h"
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#include "fxemu.h"
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static void FxReset (struct FxInfo_s *);
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static void fx_readRegisterSpace (void);
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static void fx_writeRegisterSpace (void);
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static void fx_updateRamBank (uint8);
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static void fx_dirtySCBR (void);
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static bool8 fx_checkStartAddress (void);
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static uint32 FxEmulate (uint32);
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static void FxCacheWriteAccess (uint16);
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static void FxFlushCache (void);
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void S9xInitSuperFX (void)
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{
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memset((uint8 *) &GSU, 0, sizeof(struct FxRegs_s));
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}
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void S9xResetSuperFX (void)
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{
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// FIXME: Snes9x only runs the SuperFX at the end of every line.
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// 5823405 is a magic number that seems to work for most games.
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SuperFX.speedPerLine = (uint32) (5823405 * ((1.0 / (float) Memory.ROMFramesPerSecond) / ((float) (Timings.V_Max))));
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SuperFX.oneLineDone = FALSE;
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SuperFX.vFlags = 0;
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CPU.IRQExternal = FALSE;
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FxReset(&SuperFX);
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}
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void S9xSetSuperFX (uint8 byte, uint16 address)
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{
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switch (address)
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{
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case 0x3030:
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if ((Memory.FillRAM[0x3030] ^ byte) & FLG_G)
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{
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Memory.FillRAM[0x3030] = byte;
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if (byte & FLG_G)
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{
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if (!SuperFX.oneLineDone)
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{
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S9xSuperFXExec();
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SuperFX.oneLineDone = TRUE;
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}
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}
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else
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FxFlushCache();
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}
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else
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Memory.FillRAM[0x3030] = byte;
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break;
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case 0x3031:
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Memory.FillRAM[0x3031] = byte;
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break;
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case 0x3033:
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Memory.FillRAM[0x3033] = byte;
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break;
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case 0x3034:
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Memory.FillRAM[0x3034] = byte & 0x7f;
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break;
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case 0x3036:
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Memory.FillRAM[0x3036] = byte & 0x7f;
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break;
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case 0x3037:
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Memory.FillRAM[0x3037] = byte;
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break;
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case 0x3038:
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Memory.FillRAM[0x3038] = byte;
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fx_dirtySCBR();
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break;
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case 0x3039:
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Memory.FillRAM[0x3039] = byte;
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break;
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case 0x303a:
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Memory.FillRAM[0x303a] = byte;
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break;
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case 0x303b:
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break;
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case 0x303c:
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Memory.FillRAM[0x303c] = byte;
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fx_updateRamBank(byte);
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break;
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case 0x303f:
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Memory.FillRAM[0x303f] = byte;
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break;
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case 0x301f:
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Memory.FillRAM[0x301f] = byte;
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Memory.FillRAM[0x3000 + GSU_SFR] |= FLG_G;
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if (!SuperFX.oneLineDone)
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{
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S9xSuperFXExec();
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SuperFX.oneLineDone = TRUE;
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}
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break;
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default:
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Memory.FillRAM[address] = byte;
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if (address >= 0x3100)
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FxCacheWriteAccess(address);
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break;
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}
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}
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uint8 S9xGetSuperFX (uint16 address)
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{
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uint8 byte;
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byte = Memory.FillRAM[address];
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if (address == 0x3031)
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{
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CPU.IRQExternal = FALSE;
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Memory.FillRAM[0x3031] = byte & 0x7f;
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}
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return (byte);
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}
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void S9xSuperFXExec (void)
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{
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if ((Memory.FillRAM[0x3000 + GSU_SFR] & FLG_G) && (Memory.FillRAM[0x3000 + GSU_SCMR] & 0x18) == 0x18)
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{
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FxEmulate(((Memory.FillRAM[0x3000 + GSU_CLSR] & 1) ? (SuperFX.speedPerLine * 5 / 2) : SuperFX.speedPerLine) * Settings.SuperFXClockMultiplier / 100);
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uint16 GSUStatus = Memory.FillRAM[0x3000 + GSU_SFR] | (Memory.FillRAM[0x3000 + GSU_SFR + 1] << 8);
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if ((GSUStatus & (FLG_G | FLG_IRQ)) == FLG_IRQ)
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CPU.IRQExternal = TRUE;
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}
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}
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static void FxReset (struct FxInfo_s *psFxInfo)
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{
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// Clear all internal variables
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memset((uint8 *) &GSU, 0, sizeof(struct FxRegs_s));
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// Set default registers
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GSU.pvSreg = GSU.pvDreg = &R0;
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// Set RAM and ROM pointers
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GSU.pvRegisters = psFxInfo->pvRegisters;
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GSU.nRamBanks = psFxInfo->nRamBanks;
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GSU.pvRam = psFxInfo->pvRam;
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GSU.nRomBanks = psFxInfo->nRomBanks;
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GSU.pvRom = psFxInfo->pvRom;
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GSU.vPrevScreenHeight = ~0;
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GSU.vPrevMode = ~0;
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// The GSU can't access more than 2mb (16mbits)
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if (GSU.nRomBanks > 0x20)
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GSU.nRomBanks = 0x20;
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// Clear FxChip register space
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memset(GSU.pvRegisters, 0, 0x300);
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// Set FxChip version Number
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GSU.pvRegisters[0x3b] = 0;
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// Make ROM bank table
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for (int i = 0; i < 256; i++)
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{
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uint32 b = i & 0x7f;
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if (b >= 0x40)
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{
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if (GSU.nRomBanks > 1)
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b %= GSU.nRomBanks;
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else
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b &= 1;
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GSU.apvRomBank[i] = &GSU.pvRom[b << 16];
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}
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else
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{
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b %= GSU.nRomBanks * 2;
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GSU.apvRomBank[i] = &GSU.pvRom[(b << 16) + 0x200000];
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}
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}
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// Make RAM bank table
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for (int i = 0; i < 4; i++)
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{
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GSU.apvRamBank[i] = &GSU.pvRam[(i % GSU.nRamBanks) << 16];
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GSU.apvRomBank[0x70 + i] = GSU.apvRamBank[i];
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}
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// Start with a nop in the pipe
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GSU.vPipe = 0x01;
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// Set pointer to GSU cache
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GSU.pvCache = &GSU.pvRegisters[0x100];
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fx_readRegisterSpace();
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}
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static void fx_readRegisterSpace (void)
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{
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static uint32 avHeight[] = { 128, 160, 192, 256 };
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static uint32 avMult[] = { 16, 32, 32, 64 };
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uint8 *p;
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int n;
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GSU.vErrorCode = 0;
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// Update R0-R15
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p = GSU.pvRegisters;
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for (int i = 0; i < 16; i++)
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{
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GSU.avReg[i] = *p++;
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GSU.avReg[i] += ((uint32) (*p++)) << 8;
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}
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// Update other registers
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p = GSU.pvRegisters;
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GSU.vStatusReg = (uint32) p[GSU_SFR];
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GSU.vStatusReg |= ((uint32) p[GSU_SFR + 1]) << 8;
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GSU.vPrgBankReg = (uint32) p[GSU_PBR];
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GSU.vRomBankReg = (uint32) p[GSU_ROMBR];
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GSU.vRamBankReg = ((uint32) p[GSU_RAMBR]) & (FX_RAM_BANKS - 1);
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GSU.vCacheBaseReg = (uint32) p[GSU_CBR];
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GSU.vCacheBaseReg |= ((uint32) p[GSU_CBR + 1]) << 8;
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// Update status register variables
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GSU.vZero = !(GSU.vStatusReg & FLG_Z);
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GSU.vSign = (GSU.vStatusReg & FLG_S) << 12;
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GSU.vOverflow = (GSU.vStatusReg & FLG_OV) << 16;
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GSU.vCarry = (GSU.vStatusReg & FLG_CY) >> 2;
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// Set bank pointers
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GSU.pvRamBank = GSU.apvRamBank[GSU.vRamBankReg & 0x3];
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GSU.pvRomBank = GSU.apvRomBank[GSU.vRomBankReg];
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GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg];
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// Set screen pointers
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GSU.pvScreenBase = &GSU.pvRam[USEX8(p[GSU_SCBR]) << 10];
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n = (int) (!!(p[GSU_SCMR] & 0x04));
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n |= ((int) (!!(p[GSU_SCMR] & 0x20))) << 1;
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GSU.vScreenHeight = GSU.vScreenRealHeight = avHeight[n];
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GSU.vMode = p[GSU_SCMR] & 0x03;
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if (n == 3)
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GSU.vScreenSize = (256 / 8) * (256 / 8) * 32;
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else
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GSU.vScreenSize = (GSU.vScreenHeight / 8) * (256 / 8) * avMult[GSU.vMode];
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if (GSU.vPlotOptionReg & 0x10) // OBJ Mode (for drawing into sprites)
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GSU.vScreenHeight = 256;
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if (GSU.pvScreenBase + GSU.vScreenSize > GSU.pvRam + (GSU.nRamBanks * 65536))
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GSU.pvScreenBase = GSU.pvRam + (GSU.nRamBanks * 65536) - GSU.vScreenSize;
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GSU.pfPlot = fx_PlotTable[GSU.vMode];
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GSU.pfRpix = fx_PlotTable[GSU.vMode + 5];
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fx_OpcodeTable[0x04c] = GSU.pfPlot;
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fx_OpcodeTable[0x14c] = GSU.pfRpix;
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fx_OpcodeTable[0x24c] = GSU.pfPlot;
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fx_OpcodeTable[0x34c] = GSU.pfRpix;
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fx_computeScreenPointers();
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//fx_backupCache();
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}
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static void fx_writeRegisterSpace (void)
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{
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uint8 *p;
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p = GSU.pvRegisters;
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for (int i = 0; i < 16; i++)
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{
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*p++ = (uint8) GSU.avReg[i];
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*p++ = (uint8) (GSU.avReg[i] >> 8);
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}
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// Update status register
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if (USEX16(GSU.vZero) == 0)
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SF(Z);
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else
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CF(Z);
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if (GSU.vSign & 0x8000)
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SF(S);
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else
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CF(S);
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if (GSU.vOverflow >= 0x8000 || GSU.vOverflow < -0x8000)
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SF(OV);
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else
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CF(OV);
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if (GSU.vCarry)
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SF(CY);
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else
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CF(CY);
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p = GSU.pvRegisters;
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p[GSU_SFR] = (uint8) GSU.vStatusReg;
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p[GSU_SFR + 1] = (uint8) (GSU.vStatusReg >> 8);
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p[GSU_PBR] = (uint8) GSU.vPrgBankReg;
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p[GSU_ROMBR] = (uint8) GSU.vRomBankReg;
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p[GSU_RAMBR] = (uint8) GSU.vRamBankReg;
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p[GSU_CBR] = (uint8) GSU.vCacheBaseReg;
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p[GSU_CBR + 1] = (uint8) (GSU.vCacheBaseReg >> 8);
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//fx_restoreCache();
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}
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// Update RamBankReg and RAM Bank pointer
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static void fx_updateRamBank (uint8 byte)
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{
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// Update BankReg and Bank pointer
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GSU.vRamBankReg = (uint32) byte & (FX_RAM_BANKS - 1);
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GSU.pvRamBank = GSU.apvRamBank[byte & 0x3];
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}
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// SCBR write seen. We need to update our cached screen pointers
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static void fx_dirtySCBR (void)
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{
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GSU.vSCBRDirty = TRUE;
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}
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static bool8 fx_checkStartAddress (void)
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{
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// Check if we start inside the cache
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if (GSU.bCacheActive && R15 >= GSU.vCacheBaseReg && R15 < (GSU.vCacheBaseReg + 512))
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return (TRUE);
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/*
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// Check if we're in an unused area
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if (GSU.vPrgBankReg < 0x40 && R15 < 0x8000)
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return (FALSE);
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*/
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if (GSU.vPrgBankReg >= 0x60 && GSU.vPrgBankReg <= 0x6f)
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return (FALSE);
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if (GSU.vPrgBankReg >= 0x74)
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return (FALSE);
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// Check if we're in RAM and the RAN flag is not set
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if (GSU.vPrgBankReg >= 0x70 && GSU.vPrgBankReg <= 0x73 && !(SCMR & (1 << 3)))
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return (FALSE);
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// If not, we're in ROM, so check if the RON flag is set
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if (!(SCMR & (1 << 4)))
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return (FALSE);
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return (TRUE);
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}
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// Execute until the next stop instruction
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static uint32 FxEmulate (uint32 nInstructions)
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{
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uint32 vCount;
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// Read registers and initialize GSU session
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fx_readRegisterSpace();
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// Check if the start address is valid
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if (!fx_checkStartAddress())
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{
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CF(G);
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fx_writeRegisterSpace();
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/*
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GSU.vIllegalAddress = (GSU.vPrgBankReg << 24) | R15;
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return (FX_ERROR_ILLEGAL_ADDRESS);
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*/
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return (0);
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}
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// Execute GSU session
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CF(IRQ);
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/*
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if (GSU.bBreakPoint)
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vCount = fx_run_to_breakpoint(nInstructions);
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else
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*/
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vCount = fx_run(nInstructions);
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// Store GSU registers
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fx_writeRegisterSpace();
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// Check for error code
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if (GSU.vErrorCode)
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return (GSU.vErrorCode);
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else
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return (vCount);
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}
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void fx_computeScreenPointers (void)
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{
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if (GSU.vMode != GSU.vPrevMode || GSU.vPrevScreenHeight != GSU.vScreenHeight || GSU.vSCBRDirty)
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{
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GSU.vSCBRDirty = FALSE;
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// Make a list of pointers to the start of each screen column
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switch (GSU.vScreenHeight)
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{
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case 128:
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switch (GSU.vMode)
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{
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case 0:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4);
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GSU.x[i] = i << 8;
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}
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break;
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case 1:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5);
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GSU.x[i] = i << 9;
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}
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break;
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case 2:
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case 3:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6);
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GSU.x[i] = i << 10;
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}
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break;
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}
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break;
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case 160:
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switch (GSU.vMode)
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{
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case 0:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4);
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GSU.x[i] = (i << 8) + (i << 6);
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}
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break;
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case 1:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5);
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GSU.x[i] = (i << 9) + (i << 7);
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}
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break;
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case 2:
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case 3:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6);
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GSU.x[i] = (i << 10) + (i << 8);
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}
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break;
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}
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break;
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case 192:
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switch (GSU.vMode)
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{
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case 0:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4);
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GSU.x[i] = (i << 8) + (i << 7);
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}
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break;
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case 1:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5);
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GSU.x[i] = (i << 9) + (i << 8);
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}
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break;
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case 2:
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case 3:
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for (int i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6);
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GSU.x[i] = (i << 10) + (i << 9);
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}
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break;
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}
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break;
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case 256:
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switch (GSU.vMode)
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{
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case 0:
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for (int i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + ((i & 0x10) << 9) + ((i & 0xf) << 8);
|
|
GSU.x[i] = ((i & 0x10) << 8) + ((i & 0xf) << 4);
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
for (int i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + ((i & 0x10) << 10) + ((i & 0xf) << 9);
|
|
GSU.x[i] = ((i & 0x10) << 9) + ((i & 0xf) << 5);
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
|
case 3:
|
|
for (int i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + ((i & 0x10) << 11) + ((i & 0xf) << 10);
|
|
GSU.x[i] = ((i & 0x10) << 10) + ((i & 0xf) << 6);
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
GSU.vPrevMode = GSU.vMode;
|
|
GSU.vPrevScreenHeight = GSU.vScreenHeight;
|
|
}
|
|
}
|
|
|
|
// Write access to the cache
|
|
static void FxCacheWriteAccess (uint16 vAddress)
|
|
{
|
|
/*
|
|
if (!GSU.bCacheActive)
|
|
{
|
|
uint8 v = GSU.pvCache[GSU.pvCache[vAddress & 0x1ff];
|
|
fx_setCache();
|
|
GSU.pvCache[GSU.pvCache[vAddress & 0x1ff] = v;
|
|
}
|
|
*/
|
|
|
|
if ((vAddress & 0x00f) == 0x00f)
|
|
GSU.vCacheFlags |= 1 << ((vAddress & 0x1f0) >> 4);
|
|
}
|
|
|
|
static void FxFlushCache (void)
|
|
{
|
|
GSU.vCacheFlags = 0;
|
|
GSU.vCacheBaseReg = 0;
|
|
GSU.bCacheActive = FALSE;
|
|
//GSU.vPipe = 0x1;
|
|
}
|
|
|
|
void fx_flushCache (void)
|
|
{
|
|
//fx_restoreCache();
|
|
GSU.vCacheFlags = 0;
|
|
GSU.bCacheActive = FALSE;
|
|
}
|
|
|
|
/*
|
|
static void fx_setCache (void)
|
|
{
|
|
uint32 c;
|
|
|
|
GSU.bCacheActive = TRUE;
|
|
GSU.pvRegisters[0x3e] &= 0xf0;
|
|
|
|
c = (uint32) GSU.pvRegisters[0x3e];
|
|
c |= ((uint32) GSU.pvRegisters[0x3f]) << 8;
|
|
if (c == GSU.vCacheBaseReg)
|
|
return;
|
|
|
|
GSU.vCacheBaseReg = c;
|
|
GSU.vCacheFlags = 0;
|
|
|
|
if (c < (0x10000 - 512))
|
|
{
|
|
const uint8 *t = &ROM(c);
|
|
memcpy(GSU.pvCache, t, 512);
|
|
}
|
|
else
|
|
{
|
|
const uint8 *t1, *t2;
|
|
uint32 i = 0x10000 - c;
|
|
|
|
t1 = &ROM(c);
|
|
t2 = &ROM(0);
|
|
memcpy(GSU.pvCache, t1, i);
|
|
memcpy(&GSU.pvCache[i], t2, 512 - i);
|
|
}
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static void fx_backupCache (void)
|
|
{
|
|
uint32 v = GSU.vCacheFlags;
|
|
uint32 c = USEX16(GSU.vCacheBaseReg);
|
|
|
|
if (v)
|
|
{
|
|
for (int i = 0; i < 32; i++)
|
|
{
|
|
if (v & 1)
|
|
{
|
|
if (c < (0x10000 - 16))
|
|
{
|
|
uint8 *t = &GSU.pvPrgBank[c];
|
|
memcpy(&GSU.avCacheBackup[i << 4], t, 16);
|
|
memcpy(t, &GSU.pvCache[i << 4], 16);
|
|
}
|
|
else
|
|
{
|
|
uint8 *t1, *t2;
|
|
uint32 a = 0x10000 - c;
|
|
|
|
t1 = &GSU.pvPrgBank[c];
|
|
t2 = &GSU.pvPrgBank[0];
|
|
memcpy(&GSU.avCacheBackup[i << 4], t1, a);
|
|
memcpy(t1, &GSU.pvCache[i << 4], a);
|
|
memcpy(&GSU.avCacheBackup[(i << 4) + a], t2, 16 - a);
|
|
memcpy(t2, &GSU.pvCache[(i << 4) + a], 16 - a);
|
|
}
|
|
}
|
|
|
|
c = USEX16(c + 16);
|
|
v >>= 1;
|
|
}
|
|
}
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static void fx_restoreCache()
|
|
{
|
|
uint32 v = GSU.vCacheFlags;
|
|
uint32 c = USEX16(GSU.vCacheBaseReg);
|
|
|
|
if (v)
|
|
{
|
|
for (int i = 0; i < 32; i++)
|
|
{
|
|
if (v & 1)
|
|
{
|
|
if (c < (0x10000 - 16))
|
|
{
|
|
uint8 *t = &GSU.pvPrgBank[c];
|
|
memcpy(t, &GSU.avCacheBackup[i << 4], 16);
|
|
memcpy(&GSU.pvCache[i << 4], t, 16);
|
|
}
|
|
else
|
|
{
|
|
uint8 *t1, *t2;
|
|
uint32 a = 0x10000 - c;
|
|
|
|
t1 = &GSU.pvPrgBank[c];
|
|
t2 = &GSU.pvPrgBank[0];
|
|
memcpy(t1, &GSU.avCacheBackup[i << 4], a);
|
|
memcpy(&GSU.pvCache[i << 4], t1, a);
|
|
memcpy(t2, &GSU.avCacheBackup[(i << 4) + a], 16 - a);
|
|
memcpy(&GSU.pvCache[(i << 4) + a], t2, 16 - a);
|
|
}
|
|
}
|
|
|
|
c = USEX16(c + 16);
|
|
v >>= 1;
|
|
}
|
|
}
|
|
}
|
|
*/
|
|
|
|
// Breakpoints
|
|
/*
|
|
static void FxBreakPointSet (uint32 vAddress)
|
|
{
|
|
GSU.bBreakPoint = TRUE;
|
|
GSU.vBreakPoint = USEX16(vAddress);
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static void FxBreakPointClear (void)
|
|
{
|
|
GSU.bBreakPoint = FALSE;
|
|
}
|
|
*/
|
|
|
|
// Step by step execution
|
|
/*
|
|
static uint32 FxStepOver (uint32 nInstructions)
|
|
{
|
|
uint32 vCount;
|
|
|
|
fx_readRegisterSpace();
|
|
|
|
if (!fx_checkStartAddress())
|
|
{
|
|
CF(G);
|
|
#if 0
|
|
GSU.vIllegalAddress = (GSU.vPrgBankReg << 24) | R15;
|
|
return (FX_ERROR_ILLEGAL_ADDRESS);
|
|
#else
|
|
return (0);
|
|
#endif
|
|
}
|
|
|
|
if (PIPE >= 0xf0)
|
|
GSU.vStepPoint = USEX16(R15 + 3);
|
|
else
|
|
if ((PIPE >= 0x05 && PIPE <= 0x0f) || (PIPE >= 0xa0 && PIPE <= 0xaf))
|
|
GSU.vStepPoint = USEX16(R15 + 2);
|
|
else
|
|
GSU.vStepPoint = USEX16(R15 + 1);
|
|
|
|
vCount = fx_step_over(nInstructions);
|
|
|
|
fx_writeRegisterSpace();
|
|
|
|
if (GSU.vErrorCode)
|
|
return (GSU.vErrorCode);
|
|
else
|
|
return (vCount);
|
|
}
|
|
*/
|
|
|
|
// Errors
|
|
/*
|
|
static int FxGetErrorCode (void)
|
|
{
|
|
return (GSU.vErrorCode);
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static int FxGetIllegalAddress (void)
|
|
{
|
|
return (GSU.vIllegalAddress);
|
|
}
|
|
*/
|
|
|
|
// Access to internal registers
|
|
/*
|
|
static uint32 FxGetColorRegister (void)
|
|
{
|
|
return (GSU.vColorReg & 0xff);
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static uint32 FxGetPlotOptionRegister (void)
|
|
{
|
|
return (GSU.vPlotOptionReg & 0x1f);
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static uint32 FxGetSourceRegisterIndex (void)
|
|
{
|
|
return (GSU.pvSreg - GSU.avReg);
|
|
}
|
|
*/
|
|
|
|
/*
|
|
static uint32 FxGetDestinationRegisterIndex (void)
|
|
{
|
|
return (GSU.pvDreg - GSU.avReg);
|
|
}
|
|
*/
|
|
|
|
// Get the byte currently in the pipe
|
|
/*
|
|
static uint8 FxPipe (void)
|
|
{
|
|
return (GSU.vPipe);
|
|
}
|
|
*/
|