2017-01-14 21:09:57 +00:00
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#include "../copyright"
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2014-10-29 23:23:30 +00:00
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2011-03-06 02:39:25 +00:00
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#include "seta.h"
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#include "memmap.h"
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ST011_Regs ST011;
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2017-08-16 03:20:50 +00:00
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uint8_t board[9][9]; /* shougi playboard */
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2011-03-06 02:39:25 +00:00
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2014-11-03 14:26:54 +00:00
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uint8_t S9xGetST011(uint32_t Address)
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2011-03-06 02:39:25 +00:00
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{
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2014-11-03 14:26:54 +00:00
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uint8_t t;
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uint16_t address = (uint16_t) Address & 0xFFFF;
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2014-10-29 23:23:30 +00:00
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2017-08-16 03:20:50 +00:00
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if (address == 0x01) /* status check */
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2014-10-29 23:23:30 +00:00
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t = 0xFF;
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2017-08-16 03:20:50 +00:00
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else /* read directly from s-ram */
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2014-10-29 23:23:30 +00:00
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t = Memory.SRAM[address];
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return t;
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2011-03-06 02:39:25 +00:00
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}
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2014-11-03 14:26:54 +00:00
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void S9xSetST011(uint32_t Address, uint8_t Byte)
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2011-03-06 02:39:25 +00:00
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{
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2014-11-03 14:26:54 +00:00
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uint16_t address = (uint16_t) Address & 0xFFFF;
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2014-10-29 23:23:30 +00:00
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static bool reset = false;
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2017-08-16 03:20:50 +00:00
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if (!reset) /* bootup values */
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2014-10-29 23:23:30 +00:00
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{
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ST011.waiting4command = true;
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reset = true;
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}
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Memory.SRAM[address] = Byte;
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2017-08-16 03:20:50 +00:00
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if (address == 0x00) /* op commands/data goes through this address */
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2014-10-29 23:23:30 +00:00
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{
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2017-08-16 03:20:50 +00:00
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if (ST011.waiting4command) /* check for new commands */
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2014-10-29 23:23:30 +00:00
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{
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ST011.waiting4command = false;
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ST011.command = Byte;
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ST011.in_index = 0;
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ST011.out_index = 0;
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switch (ST011.command)
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{
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case 0x01:
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ST011.in_count = 12 * 10 + 8;
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break;
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case 0x02:
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ST011.in_count = 4;
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break;
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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case 0x0E:
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ST011.in_count = 0;
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break;
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default:
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ST011.waiting4command = true;
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break;
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}
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}
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else
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{
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ST011.parameters [ST011.in_index] = Byte;
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ST011.in_index++;
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}
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}
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2017-08-16 03:20:50 +00:00
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if (ST011.in_count == ST011.in_index) /* Actually execute the command */
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2014-10-29 23:23:30 +00:00
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{
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ST011.waiting4command = true;
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ST011.out_index = 0;
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switch (ST011.command)
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{
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2017-08-16 03:20:50 +00:00
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case 0x01: /* unknown: download playboard */
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2014-10-29 23:23:30 +00:00
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{
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2017-08-16 03:20:50 +00:00
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/* 9x9 board data: top to bottom, left to right */
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/* Values represent piece types and ownership */
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2017-01-29 04:55:23 +00:00
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int32_t lcv;
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2014-10-29 23:23:30 +00:00
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for (lcv = 0; lcv < 9; lcv++)
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memcpy(board[lcv], ST011.parameters + lcv * 10, 9 * 1);
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2017-02-12 01:52:03 +00:00
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break;
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2014-10-29 23:23:30 +00:00
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}
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2017-08-16 03:20:50 +00:00
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case 0x04: /* unknown */
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2014-10-29 23:23:30 +00:00
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case 0x05:
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{
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2017-08-16 03:20:50 +00:00
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/* outputs */
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2014-10-29 23:23:30 +00:00
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Memory.SRAM[0x12C] = 0x00;
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Memory.SRAM[0x12E] = 0x00;
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2017-02-12 01:52:03 +00:00
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break;
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2014-10-29 23:23:30 +00:00
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}
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2017-08-16 03:20:50 +00:00
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case 0x0E: /* unknown */
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2014-10-29 23:23:30 +00:00
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{
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2017-08-16 03:20:50 +00:00
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/* outputs */
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2014-10-29 23:23:30 +00:00
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Memory.SRAM[0x12C] = 0x00;
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Memory.SRAM[0x12D] = 0x00;
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2017-08-14 05:03:05 +00:00
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break;
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2014-10-29 23:23:30 +00:00
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}
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}
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}
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2011-03-06 02:39:25 +00:00
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}
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