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Fully integrate BassAceGold's libraries, finally. The README still states that 1.2 is required to overwrite 0.13's stuff; really, 0.13 is needed only for gcc. So the sequence goes 0.13's gcc -> 1.2 -> BassAceGold's libraries -> make libds2a.a.

Browse Source 
DMA function names changed to match BassAceGold's.
This commit is contained in:
Nebuleon Fumika 2013-02-04 23:45:44 -05:00
parent b1c298ab50
commit d1a7bf5eb5
116 changed files with 555 additions and 6460 deletions
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4
Makefile
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@ -7,12 +7,14 @@ FS_DIR = $(DS2SDKPATH)/libsrc/fs
CONSOLE_DIR = $(DS2SDKPATH)/libsrc/console
KEY_DIR = $(DS2SDKPATH)/libsrc/key
ZLIB_DIR = $(DS2SDKPATH)/libsrc/zlib
CORE_DIR = $(DS2SDKPATH)/libsrc/core
LIBS := $(DS2SDKPATH)/lib/libds2b.a -lc -lm -lgcc
EXTLIBS := $(DS2SDKPATH)/lib/libds2a.a
INCLUDE := -Isource -Isource/unzip -Isource/nds -I$(DS2SDKPATH)/include \
-I$(FS_DIR) -I$(CONSOLE_DIR) -I$(KEY_DIR) -I$(ZLIB_DIR)
-I$(FS_DIR) -I$(CONSOLE_DIR) -I$(KEY_DIR) -I$(ZLIB_DIR) \
-I$(CORE_DIR)
LINK_SPEC := $(DS2SDKPATH)/specs/link.xn
START_ASM := $(DS2SDKPATH)/specs/start.S

8
README.md
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@ -31,10 +31,10 @@ Additionally, you will need to add the updated `zlib`, DMA
(Direct Memory Access) and filesystem access routines provided by BassAceGold
and recompile `libds2a.a`. To do this:
> sudo rm -r /opt/ds2sdk/libsrc/{console,dma,fs,key,zlib,Makefile} /opt/ds2sdk/include
> sudo cp -r sdk-modifications/{libsrc,include} /opt/ds2sdk
> sudo chmod -R 600 /opt/ds2sdk/{libsrc,include}
> sudo chmod -R a+rX /opt/ds2sdk/{libsrc,include}
> sudo rm -r /opt/ds2sdk/libsrc/{console,core,fs,key,zlib,Makefile}
> sudo cp -r sdk-modifications/libsrc /opt/ds2sdk
> sudo chmod -R 600 /opt/ds2sdk/libsrc
> sudo chmod -R a+rX /opt/ds2sdk/libsrc
> cd /opt/ds2sdk/libsrc
> sudo rm libds2a.a ../lib/libds2a.a
> sudo make

2356
sdk-modifications/include/archdefs.h
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58
sdk-modifications/include/bit_ops.h
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@ -1,58 +0,0 @@
/*
bit_ops.h
Functions for dealing with conversion of data between types
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _BIT_OPS_H
#define _BIT_OPS_H
/*-----------------------------------------------------------------
Functions to deal with little endian values stored in u8 arrays
-----------------------------------------------------------------*/
static inline u16 u8array_to_u16 (const u8* item, int offset) {
return ( item[offset] | (item[offset + 1] << 8));
}
static inline u32 u8array_to_u32 (const u8* item, int offset) {
return ( item[offset] | (item[offset + 1] << 8) | (item[offset + 2] << 16) | (item[offset + 3] << 24));
}
static inline void u16_to_u8array (u8* item, int offset, u16 value) {
item[offset] = (u8)value;
item[offset + 1] = (u8)(value >> 8);
}
static inline void u32_to_u8array (u8* item, int offset, u32 value) {
item[offset] = (u8)value;
item[offset + 1] = (u8)(value >> 8);
item[offset + 2] = (u8)(value >> 16);
item[offset + 3] = (u8)(value >> 24);
}
#endif // _BIT_OPS_H

9
sdk-modifications/include/console.h
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@ -1,9 +0,0 @@
#ifndef __CONSOLE_H__
#define __CONSOLE_H__
#include "ds2io.h"
extern int ConsoleInit(unsigned short front_color, unsigned short background_color, enum SCREEN_ID screen, unsigned int buf_size);
extern int cprintf(const char *format, ...);
#endif //__CONSOLE_H__

172
sdk-modifications/include/directory.h
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@ -1,172 +0,0 @@
/*
directory.h
Reading, writing and manipulation of the directory structure on
a FAT partition
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _DIRECTORY_H
#define _DIRECTORY_H
#include <sys/stat.h>
#include "fs_common.h"
#include "partition.h"
#define DIR_ENTRY_DATA_SIZE 0x20
#define MAX_FILENAME_LENGTH 256
#define MAX_ALIAS_LENGTH 13
#define LFN_ENTRY_LENGTH 13
#define FAT16_ROOT_DIR_CLUSTER 0
#define DIR_SEPARATOR '/'
// File attributes
#define ATTRIB_ARCH 0x20 // Archive
#define ATTRIB_DIR 0x10 // Directory
#define ATTRIB_LFN 0x0F // Long file name
#define ATTRIB_VOL 0x08 // Volume
#define ATTRIB_SYS 0x04 // System
#define ATTRIB_HID 0x02 // Hidden
#define ATTRIB_RO 0x01 // Read only
typedef enum {FT_DIRECTORY, FT_FILE} FILE_TYPE;
typedef struct {
u32 cluster;
u32 sector;
s32 offset;
} DIR_ENTRY_POSITION;
typedef struct {
u8 entryData[DIR_ENTRY_DATA_SIZE];
DIR_ENTRY_POSITION dataStart; // Points to the start of the LFN entries of a file, or the alias for no LFN
DIR_ENTRY_POSITION dataEnd; // Always points to the file/directory's alias entry
char d_name[MAX_FILENAME_LENGTH + MAX_FILENAME_LENGTH*2]; //Store name string using UTF8 coding
//u16 unicodeFilename[MAX_FILENAME_LENGTH];
} DIR_ENTRY;
// Directory entry offsets
enum DIR_ENTRY_offset {
DIR_ENTRY_name = 0x00,
DIR_ENTRY_extension = 0x08,
DIR_ENTRY_attributes = 0x0B,
DIR_ENTRY_reserved = 0x0C,
DIR_ENTRY_cTime_ms = 0x0D,
DIR_ENTRY_cTime = 0x0E,
DIR_ENTRY_cDate = 0x10,
DIR_ENTRY_aDate = 0x12,
DIR_ENTRY_clusterHigh = 0x14,
DIR_ENTRY_mTime = 0x16,
DIR_ENTRY_mDate = 0x18,
DIR_ENTRY_cluster = 0x1A,
DIR_ENTRY_fileSize = 0x1C
};
/*
Returns true if the file specified by entry is a directory
*/
static inline bool _FAT_directory_isDirectory (DIR_ENTRY* entry) {
return ((entry->entryData[DIR_ENTRY_attributes] & ATTRIB_DIR) != 0);
}
static inline bool _FAT_directory_isWritable (DIR_ENTRY* entry) {
return ((entry->entryData[DIR_ENTRY_attributes] & ATTRIB_RO) == 0);
}
static inline bool _FAT_directory_isDot (DIR_ENTRY* entry) {
return ((entry->d_name[0] == '.') && ((entry->d_name[1] == '\0') ||
((entry->d_name[1] == '.') && entry->d_name[2] == '\0')));
}
/*
Reads the first directory entry from the directory starting at dirCluster
Places result in entry
entry will be destroyed even if no directory entry is found
Returns true on success, false on failure
*/
bool _FAT_directory_getFirstEntry (PARTITION* partition, DIR_ENTRY* entry, u32 dirCluster);
/*
Reads the next directory entry after the one already pointed to by entry
Places result in entry
entry will be destroyed even if no directory entry is found
Returns true on success, false on failure
*/
bool _FAT_directory_getNextEntry (PARTITION* partition, DIR_ENTRY* entry);
/*
Gets the directory entry corrsponding to the supplied path
entry will be destroyed even if no directory entry is found
pathEnd specifies the end of the path string, for cutting strings short if needed
specify NULL to use the full length of path
pathEnd is only a suggestion, and the path string will be searched up until the next PATH_SEPARATOR
after pathEND.
Returns true on success, false on failure
*/
bool _FAT_directory_entryFromPath (PARTITION* partition, DIR_ENTRY* entry, const char* path, const char* pathEnd);
/*
Changes the current directory to the one specified by path
Returns true on success, false on failure
*/
bool _FAT_directory_chdir (PARTITION* partition, const char* path);
/*
Removes the directory entry specified by entry
Assumes that entry is valid
Returns true on success, false on failure
*/
bool _FAT_directory_removeEntry (PARTITION* partition, DIR_ENTRY* entry);
/*
Add a directory entry to the directory specified by dirCluster
The fileData, dataStart and dataEnd elements of the DIR_ENTRY struct are
updated with the new directory entry position and alias.
Returns true on success, false on failure
*/
bool _FAT_directory_addEntry (PARTITION* partition, DIR_ENTRY* entry, u32 dirCluster);
/*
Get the start cluster of a file from it's entry data
*/
u32 _FAT_directory_entryGetCluster (const u8* entryData);
/*
Fill in the file name and entry data of DIR_ENTRY* entry.
Assumes that the entry's dataStart and dataEnd are correct
Returns true on success, false on failure
*/
bool _FAT_directory_entryFromPosition (PARTITION* partition, DIR_ENTRY* entry);
/*
Fill in a stat struct based on a file entry
*/
void _FAT_directory_entryStat (PARTITION* partition, DIR_ENTRY* entry, struct stat *st);
#endif // _DIRECTORY_H

57
sdk-modifications/include/ds2_cpu.h
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@ -1,57 +0,0 @@
#ifndef __DS2_CPU_H__
#define __DS2_CPU_H__
#ifdef __cplusplus
extern "C" {
#endif
//exception handle
//cache operationr
//invalidate instruction cache
extern void __icache_invalidate_all(void);
//invalidate data cache
extern void __dcache_invalidate_all(void);
//data cache writeback
extern void __dcache_writeback_all(void);
//data cache writeback and invalidate
extern void _dcache_wback_inv(unsigned long addr, unsigned long size);
//interruption operation
//clear CPU's interrupt state and enable global interrupt
extern void sti(void);
//disable global interrupt
extern void cli(void);
//disable global interrupt and store the global interrupt state
//return: interrupt state
extern unsigned int spin_lock_irqsave(void);
//restore global interrupt state
extern void spin_unlock_irqrestore(unsigned int val);
//CPU frequence
//There are 14 levels, 0 to 13, 13 level have the highest clock frequence
extern int ds2_setCPUclocklevel(unsigned int num);
//print colock frequence CPU
extern void printf_clock(void);
//delay n us
extern void udelay(unsigned int usec);
//delay n ms
extern void mdelay(unsigned int msec);
#ifdef __cplusplus
}
#endif
#endif //__DS2_CPU_H__

54
sdk-modifications/include/ds2_dma.h
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@ -1,54 +0,0 @@
#ifndef __DMA_H__
#define __DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
//register a DMA transfer request
//ch: channel id request, there are 6 channles,
//irq_handler: the DMA interruption handle
//arg: argument to the handle
//mode: DMA mode, such as port width, address increased/fixed, and so on
//type: DMA request type
extern int dma_request(int ch, void (*irq_handler)(unsigned int), unsigned int arg,
unsigned int mode, unsigned int type);
//start DMA transfer, must request a DMA first
//ch: channel id
//srcAddr: DMA source address
//dstAddr: DMA destination address
//count: DMA transfer count, the total bytes due the mode in dma_request
extern void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count);
//Stop DMA transfer
extern void dma_stop(int ch);
//Wait DMA transfer over
extern int dma_wait_finish(int ch);
/*
* Copy 'size' bytes from src to dest, in blocks of 32 bytes.
* size is in bytes and must be a multiple of 32.
* Both src and dest must be aligned to 32 bytes.
* Returns 0 on failure, non-zero on success.
*/
extern int dma_copy32Byte(int ch, void *dest, void *src, unsigned int size);
// Blocks of 16 bytes, aligned to 16 bytes
extern int dma_copy16Byte(int ch, void *dest, void *src, unsigned int size);
// Blocks of 4 bytes, aligned to 4 bytes
extern int dma_copy32Bit(int ch, void *dest, void *src, unsigned int size);
// Blocks of 2 bytes, aligned to 2 bytes
extern int dma_copy16Bit(int ch, void *dest, void *src, unsigned int size);
extern int dma_isBusy(int ch);
extern int dma_isFree(int ch);
extern int dma_getFree(void);
#ifdef __cplusplus
}
#endif
#endif //__DMA_H__

55
sdk-modifications/include/ds2_excpt.h
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@ -1,55 +0,0 @@
#ifndef __DS2_EXCPT_H__
#define __DS2_EXCPT_H__
#include <mipsregs.h>
extern unsigned int Process_RA;
extern unsigned int Process_SP;
#define SAVE_PROCESS_REGISTER() \
do{ unsigned int sr ; \
sr = read_c0_status(); \
write_c0_status((sr&(~1))); \
__asm__ __volatile__( \
"sw $31,0x00(%0)\n\t" \
"sw $29,0x00(%1)\n\t" \
: \
: "r" (&Process_RA),"r" (&Process_SP)); \
write_c0_status(sr); \
}while(0)
#define RESTORE_PROCESS_REGISTER() \
__asm__ __volatile__( \
"lw $31,0x00(%0)\n\t" \
"lw $29,0x00(%1)\n\t" \
: \
: "r" (&Process_RA),"r" (&Process_SP))
inline static void excpt_exit(x) \
{
unsigned int sr;
sr = read_c0_status();
write_c0_status(sr & (~1));
__asm__ __volatile__("lw $2,0x00(%0)\n\t" :: "r" (&x));
RESTORE_PROCESS_REGISTER();
write_c0_status(sr);
__asm__ __volatile__(
"jr $31\n\t"
"nop\n\t"
);
}
typedef void (*PFun_Exception_Handler)(unsigned int);
//Setup handle to process the exception
//except_index: exception number
//except_handle: handle to process the exception
//arg: argument to the handle
extern int Setup_except_handle(unsigned int except_index, PFun_Exception_Handler except_handle, unsigned int arg);
//Add a write watched exception, if the CPU write the addr, a exception will
// generated, the watch exception's number is 23
//addr: address to be watched
extern void add_watch_point(unsigned int addr);
#endif //__DS2_EXCPT_H__

51
sdk-modifications/include/ds2_fcntl.h
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@ -1,51 +0,0 @@
#ifndef __libc_fcntl_h__
#define __libc_fcntl_h__
#ifdef __cplusplus
extern "C"
{
#endif
#define O_RDONLY (1 << 0)
#define O_WRONLY (2 << 0)
#define O_RDWR (3 << 0)
#define O_APPEND (1 << 2)
#define O_CREAT (1 << 3)
#define O_DSYNC (1 << 4)
#define O_EXCL (1 << 5)
#define O_NOCTTY (1 << 6)
#define O_NONBLOCK (1 << 7)
#define O_RSYNC (1 << 8)
#define O_SYNC (1 << 9)
#define O_TRUNC (1 << 10)
#define O_CREATE O_CREAT
#define O_ACCMODE 0x3
#define F_CLOEXEC (1 << 11)
#define F_DUPFD 1
#define F_GETFD 2
#define F_SETFD 3
#define F_GETFL 4
#define F_SETFL 5
#define F_GETLK 6
#define F_SETLK 7
#define F_SETLKW 8
#define F_GETOWN 9
#define F_SETOWN 10
#define _F_LAST F_SETOWN
#define _F_FILE_DESC (F_CLOEXEC)
#define _O_FILE_CREATE (O_CREAT | O_EXCL | O_NOCTTY | O_TRUNC)
#define _O_FILE_STATUS (O_APPEND | O_DSYNC | O_NONBLOCK | O_RSYNC | O_SYNC)
#define _O_UNSUPPORTED (0)
extern int open(const char* path, int oflag, ...);
extern int fcntl(int fildes, int cmd, ...);
#ifdef __cplusplus
}
#endif
#endif

32
sdk-modifications/include/ds2_malloc.h
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@ -1,32 +0,0 @@
#ifndef __DS2_MALLOC_H__
#define __DS2_MALLOC_H__
#ifdef __cplusplus
extern "C" {
#endif
extern void heapInit(unsigned int start, unsigned int end);
extern void* Drv_alloc(unsigned int nbytes);
extern void Drv_deAlloc(void* address);
extern void* Drv_realloc(void* address, unsigned int nbytes);
extern void* Drv_calloc(unsigned int nmem, unsigned int size);
#ifdef __cplusplus
}
#endif
#define malloc Drv_alloc
#define calloc Drv_calloc
#define realloc Drv_realloc
#define free Drv_deAlloc
#ifdef __cplusplus
#include <stdio.h>
inline void* operator new ( size_t s ) { return malloc( s ); }
inline void* operator new[] ( size_t s ) { return malloc( s ); }
inline void operator delete ( void* p ) { free( p ); }
inline void operator delete[] ( void* p ) { free( p ); }
#endif
#endif //__DS2_MALLOC_H__

56
sdk-modifications/include/ds2_mmc_api.h
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@ -1,56 +0,0 @@
#ifndef __MMC_API_H__
#define __MMC_API_H__
/* Error codes */
enum mmc_result_t {
MMC_NO_RESPONSE = -1,
MMC_NO_ERROR = 0,
MMC_ERROR_OUT_OF_RANGE,
MMC_ERROR_ADDRESS,
MMC_ERROR_BLOCK_LEN,
MMC_ERROR_ERASE_SEQ,
MMC_ERROR_ERASE_PARAM,
MMC_ERROR_WP_VIOLATION,
MMC_ERROR_CARD_IS_LOCKED,
MMC_ERROR_LOCK_UNLOCK_FAILED,
MMC_ERROR_COM_CRC,
MMC_ERROR_ILLEGAL_COMMAND,
MMC_ERROR_CARD_ECC_FAILED,
MMC_ERROR_CC,
MMC_ERROR_GENERAL,
MMC_ERROR_UNDERRUN,
MMC_ERROR_OVERRUN,
MMC_ERROR_CID_CSD_OVERWRITE,
MMC_ERROR_STATE_MISMATCH,
MMC_ERROR_HEADER_MISMATCH,
MMC_ERROR_TIMEOUT,
MMC_ERROR_CRC,
MMC_ERROR_DRIVER_FAILURE,
};
/* Get card's sectors*/
extern unsigned int MMC_GetSize(void);
/* initialize MMC/SD card */
extern int MMC_Initialize(void);
/* read a single block from MMC/SD card */
extern int MMC_ReadBlock(unsigned int blockaddr, unsigned char *recbuf);
/* read multi blocks from MMC/SD card */
extern int MMC_ReadMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf);
/* write a block to MMC/SD card */
extern int MMC_WriteBlock(unsigned int blockaddr, unsigned char *recbuf);
/* write multi blocks to MMC/SD card */
extern int MMC_WriteMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf);
/* detect MMC/SD card */
extern int MMC_DetectStatus(void);
#endif /* __MMC_API_H__ */

50
sdk-modifications/include/ds2_timer.h
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@ -1,50 +0,0 @@
#ifndef __DS2_TIMER_H__
#define __DS2_TIMER_H__
#ifdef __cplusplus
extern "C" {
#endif
/*
* Function: register a timer interruptting periodly
* channel: timer id, from 0 to 1
* period: interrupt period, unit is us, period < 2.5s
* handle: interrupt handle, if handle = NULL, the timer will not generate interrupt
* arg: argument to the interrupt handle
*/
extern int initTimer(unsigned int channel, unsigned int period, void (*handle)(unsigned int), int arg);
/*
* Function: set the timer run
*/
extern void runTimer(unsigned int channel);
/*
* Function: stop timer
*/
extern void stopTimer(unsigned int channel);
/*
* Function: reset timer
*/
extern void resetTimer(unsigned int channel);
/*
* Function: read value of timer
*/
extern unsigned int readTimer(unsigned int channel);
#define SYSTIME_UNIT 42667
/*
* Function: get the elapsed time since DS2 started
* it's uint is 42.667us, it will overflow after 50.9 horus since DS2 started
*/
extern unsigned int getSysTime(void);
#ifdef __cplusplus
}
#endif
#endif //__DS2_TIMER_H__

45
sdk-modifications/include/ds2_types.h
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@ -1,45 +0,0 @@
#ifndef __DS2_TYPES_H__
#define __DS2_TYPES_H__
#ifndef u8
#define u8 unsigned char
#endif
#ifndef s8
#define s8 char
#endif
#ifndef u16
#define u16 unsigned short
#endif
#ifndef s16
#define s16 short
#endif
#ifndef u32
#define u32 unsigned int
#endif
#ifndef s32
#define s32 int
#endif
#ifndef u64
#define u64 unsigned long long
#endif
#ifndef s64
#define s64 long long
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
#endif //__DS2_TYPES_H__

285
sdk-modifications/include/ds2io.h
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@ -1,285 +0,0 @@
#ifndef __DS2IO_H__
#define __DS2IO_H__
#ifndef BIT
#define BIT(a) (1<<a)
#endif
#define SCREEN_WIDTH 256
#define SCREEN_HEIGHT 192
#define AUDIO_BUFFER_COUNT 16
#ifdef __cplusplus
extern "C" {
#endif
typedef struct touchPosition {
signed short x;
signed short y;
} touchPosition;
typedef struct T_INPUT
{
unsigned int keysHeld;
unsigned int keysUp;
unsigned int keysDown;
unsigned int keysDownRepeat;
touchPosition touchPt;
touchPosition movedPt;
int touchDown;
int touchUp;
int touchHeld;
int touchMoved;
}INPUT;
typedef enum KEYPAD_BITS {
KEY_A = BIT(0), //!< Keypad A button.
KEY_B = BIT(1), //!< Keypad B button.
KEY_SELECT = BIT(2), //!< Keypad SELECT button.
KEY_START = BIT(3), //!< Keypad START button.
KEY_RIGHT = BIT(4), //!< Keypad RIGHT button.
KEY_LEFT = BIT(5), //!< Keypad LEFT button.
KEY_UP = BIT(6), //!< Keypad UP button.
KEY_DOWN = BIT(7), //!< Keypad DOWN button.
KEY_R = BIT(8), //!< Right shoulder button.
KEY_L = BIT(9), //!< Left shoulder button.
KEY_X = BIT(10), //!< Keypad X button.
KEY_Y = BIT(11), //!< Keypad Y button.
KEY_TOUCH = BIT(12), //!< Touchscreen pendown.
KEY_LID = BIT(13) //!< Lid state.
} KEYPAD_BITS;
struct rtc{
volatile unsigned char year; //add 2000 to get 4 digit year
volatile unsigned char month; //1 to 12
volatile unsigned char day; //1 to (days in month)
volatile unsigned char weekday; // day of week
volatile unsigned char hours; //0 to 11 for AM, 52 to 63 for PM
volatile unsigned char minutes; //0 to 59
volatile unsigned char seconds; //0 to 59
};
struct key_buf
{
unsigned short key;
unsigned short x;
unsigned short y;
};
typedef enum SCREEN_ID
{
UP_SCREEN = 1,
DOWN_SCREEN = 2,
DUAL_SCREEN = 3,
JOINTUSE_SCREEN = 3
} SCREEN_ID;
#define UP_MASK 0x1
#define DOWN_MASK 0x2
#define DUAL_MASK 0x3
//video buffer address of up screen
extern void* up_screen_addr;
//video buffer address of down screen
extern void* down_screen_addr;
//every time call ds2_updateAudio() function, the ds2io layer will transfer
//audio_samples_per_trans *4 bytes audio data to NDS
extern unsigned int audio_samples_per_trans;
/*
* Function: initialize ds2 I/O(DS2 Input and Output) layer
* audio_samples_lenght: ds2io layer's audio buffer length, it unit is sample
* which is fixed 4(ds2io use stereo and 16-bit audio) bytes,
* audio_samples_lenght sholud be 128*n, 128 <= audio_samples_lenght <= 4096
* NOTE: the audio sampling frequence be fixed to 44.1KHz, 2 channels 16-bit
*/
extern int ds2io_init(int audio_samples_lenght);
/*
* Function: initialize ds2 I/O(DS2 Input and Output) layer (b version)
* audio_samples_lenght: ds2io layer's audio buffer length, it unit is sample
* which is fixed 4(ds2io use stereo and 16-bit audio) bytes,
* audio_samples_lenght sholud be 128*n, 128 <= audio_samples_lenght <= 4096
* audio_samples_freq: audio samples frequence, it should be among 44100, 22050,
* 11025
* reserved1: reserved for future using
* reserved2: reserved for future using
* NOTE: the audio samples are 2 channels 16-bit
*/
extern int ds2io_initb(int audio_samples_lenght, int audio_samples_freq, int reserved1,
int reserved2);
/*
* Function: update video data from buffer to screen, the ds2io layer have 2 video
* buffers for up screen and 2 video buffers for down screen, everytime
* ds2_flipScreen is called, up_screen_addr and/or down_buffer_addr
* point to the other buffer, but not always do so, see below.
* screen_num: UP_SCREEN, only update up screen
* DOWN_SCREEN, only update down screen
* DUAL_SCREEN, update both up screen and down screen
* done: after updating video data, the up_screen_addr and/or down_buffer_addr
* are ready to point the other buffer, but if the other buffer is busy:
* when done = 0, ds2_flipScreen returns without change up_screen_addr
* and/or down_buffer_addr pointer. it will not sure the graphic just
* updated will appear on the screen
* when done = 1, it will WAIT untill the other buffer idle and change
* the pointers and returns. the graphic just updated will appear on
* the screen, but please noting the word "WAIT"
* when done = 2, it will WAIT untill the other buffer idle, then return
* without change the pointers, it is convenient for GUI drawing
*/
extern void ds2_flipScreen(enum SCREEN_ID screen_num, int done);
/*
* Function: set the video buffer to a single color
* screen_num: UP_SCREEN, only set up screen buffer
* DOWN_SCREEN, only set down screen buffer
* DUAL_SCREEN, set both up screen and down screen buffer
*/
extern void ds2_clearScreen(enum SCREEN_ID screen_num, unsigned short color);
/*
* Function: there are AUDIO_BUFFER_COUNT audio buffers on the ds2io layer, this function to
* check how many buffers are occupied
*/
extern int ds2_checkAudiobuff(void);
/*
* Function: get audio buffer address
* NOTE: ds2_getAudiobuff may return NULL, even if ds2_checkAudiobuff() < AUDIO_BUFFER_COUNT.
* The fact are that, AUDIO_BUFFER_COUNT audio buffers are on NDS, the ds2io layer using
* 2 other buffers transfering data to the AUDIO_BUFFER_COUNT audio buffers alternately,
* this function checks the 2 buffers in ds2io layers whether are occupied,
* it will return the address of the idle buffer, else it return NULL
*/
extern void* ds2_getAudiobuff(void);
/*
* Function: flush audio data from buffer to ds2io layer
NOTE: execution of the function ds2_updateAudio() only put audio data transfer request to wait queue,
it is not equal that the audio data reach NDS buffer.
*/
extern void ds2_updateAudio(void);
/*
* Function: set audio info
* audio_samples_freq: default freq 44100Hz
* audio_sample_bit: 16bit
* audio_samples_lenght: sholud be 128*n, 128 <= audio_samples_lenght <= 4096
* channels: 2
* data_format: 0: interleave(L R L R L R L R ...) 1: group(L L L L ...R R R R ...)
*/
void ds2_setAudio( unsigned int audio_samples_freq, int audio_sample_bit, unsigned int audio_samples_lenght, int channels, int data_format );
#ifndef RGB15
#define RGB15(r,g,b) (((r)|((g)<<5)|((b)<<10))|BIT(15))
#endif
/*
* Functin: get time
*/
extern void ds2_getTime(struct rtc *time);
/*
* Function: get brightness of the screens
* return: fours levels 0, 1, 2, 3
*/
extern int ds2_getBrightness(void);
/*
* Function: set brightness of the screens
* Input: level, there are 4 levels, 0, 1, 2 and 3
*/
extern void ds2_setBrightness(int level);
/*
* Function: get the swaping state of the screens
*/
extern int ds2_getSwap(void);
/*
* Funciotn: swap up screen and down screen
*/
extern void ds2_setSwap(int swap);
/*
* Function: get backlight status
* input bit0 = 0 set down screen's backlight off
* bit0 = 1 set down screen's backlight on
* bit1 = 0 set up screen's backlight off
* bit1 = 1 set up screen's backlight on
*/
extern void ds2_setBacklight(int backlight);
/*
* Function: get backlight status
* return bit0 = 0 the down screen's backlight is off
* bit0 = 1 the down screen's backlight is on
* bit1 = 0 the up screen's backlight is off
* bit1 = 1 the up screen's backlight is on
*/
extern int ds2_getBacklight(void);
/*
* Function: system suspend
*/
extern void ds2_setSupend(void);
/*
* Function: system wakeup
*/
extern void ds2_wakeup(void);
/*
* Function: NDS power offf
*/
extern void ds2_shutdown(void);
/*
* Function: set volume of NDS
* Input: volume 0- mute
* 1 - 127 hardware adjust the volume
* 128-255 software adjust the volume, when close to 255, the sound may
* be saturation distortion
*/
extern void ds2_setVolume(int volume);
/*
* Funciton: get key value and touch screen position value
*/
extern void ds2_getrawInput(struct key_buf *input);
/*
* Function: system exit, return to DSTWO Menu
*/
extern void ds2_plug_exit(void);
/*
* Function: return ds2sdk version string
*/
extern const char* ds2_getVersion(void);
/*
* Function: Register a function for debug purpos, such as CONSOLE. when keys
* pressed, function fun will be called in the interruption
*/
extern void regist_escape_key(void (*fun)(void), unsigned int keys);
/*
* Function: release the function fointer registered by regist_escape_key
*/
extern void release_escape_key(void);
#ifdef __cplusplus
}
#endif
#endif //__DS2IO_H__

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/*
fat.h
Simple functionality for startup, mounting and unmounting of FAT-based devices.
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
2006-07-14
* fatInitialise renamed to fatInit
2006-07-16 - Chishm
* Added fatInitDefault
*/
#ifndef _LIBFAT_H
#define _LIBFAT_H
#ifdef __cplusplus
extern "C" {
#endif
// When compiling for NDS, make sure NDS is defined
#ifndef NDS
#define NDS
#endif
#include <nds/jtypes.h>
#include "partition.h"
#include "directory.h"
#include "file_allocation_table.h"
//#include "unicode/unicode.h"
#include "fatdir_ex.h"
#include "fatfile_ex.h"
//typedef enum {PI_DEFAULT, PI_SLOT_1, PI_SLOT_2, PI_CUSTOM} PARTITION_INTERFACE;
struct IO_INTERFACE_STRUCT ;
/*
Initialise any inserted block-devices.
Add the fat device driver to the devoptab, making it available for standard file functions.
cacheSize: The number of pages to allocate for each inserted block-device
setAsDefaultDevice: if true, make this the default device driver for file operations
*/
bool fatInit (u32 cacheSize, bool setAsDefaultDevice);
/*
Calls fatInit with setAsDefaultDevice = true and cacheSize optimised for the host system.
*/
bool fatInitDefault (void);
/*
Special initialize for RPG card
*/
bool fatInitRPG (void);
/*
Mount the device specified by partitionNumber
PD_DEFAULT is not allowed, use _FAT_partition_setDefaultDevice
PD_CUSTOM is not allowed, use _FAT_partition_mountCustomDevice
*/
bool fatMountNormalInterface (PARTITION_INTERFACE partitionNumber, u32 cacheSize);
/*
Mount a partition on a custom device
*/
bool fatMountCustomInterface (struct IO_INTERFACE_STRUCT* device, u32 cacheSize);
/*
Unmount the partition specified by partitionNumber
If there are open files, it will fail
*/
bool fatUnmount (PARTITION_INTERFACE partitionNumber);
/*
Forcibly unmount the partition specified by partitionNumber
Any open files on the partition will become invalid
The cache will be invalidated, and any unflushed writes will be lost
*/
bool fatUnsafeUnmount (PARTITION_INTERFACE partitionNumber);
/*
Set the default device for access by fat: and fat0:
PD_DEFAULT is unallowed.
Doesn't do anything useful on GBA, since there is only one device
*/
bool fatSetDefaultInterface (PARTITION_INTERFACE partitionNumber);
#ifdef __cplusplus
}
#endif
#endif // _LIBFAT_H

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/*
fatdir.h
Functions used by the newlib disc stubs to interface with
this library
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-08-13 - Chishm
* Moved all externally visible directory related functions to fatdir
* Added _FAT_mkdir_r
2006-08-14 - Chishm
* Added directory iterator functions
2007-01-10 - Chishm
* Updated directory iterator functions for DevkitPro r20
*/
#ifndef _FATDIR_H
#define _FATDIR_H
//#include <sys/reent.h>
#include <sys/stat.h>
//#include <sys/iosupport.h>
#include "fs_common.h"
#include "directory.h"
typedef struct {
PARTITION* partition;
DIR_ENTRY currentEntry;
u32 startCluster;
u32 posEntry;
bool inUse;
bool validEntry;
} DIR_STATE_STRUCT;
extern int _FAT_stat_r (struct _reent *r, const char *path, struct stat *st);
extern int _FAT_link_r (struct _reent *r, const char *existing, const char *newLink);
extern int _FAT_unlink_r (struct _reent *r, const char *name);
extern int _FAT_chdir_r (struct _reent *r, const char *name);
extern int _FAT_rename_r (struct _reent *r, const char *oldName, const char *newName);
extern int _FAT_mkdir_r (struct _reent *r, const char *path, int mode);
/*
Directory iterator functions
*/
extern DIR_STATE_STRUCT* _FAT_diropen_r(struct _reent *r, DIR_STATE_STRUCT *dirState, const char *path);
extern int _FAT_dirreset_r (struct _reent *r, DIR_STATE_STRUCT *dirState);
extern int _FAT_dirnext_r (struct _reent *r, DIR_STATE_STRUCT *dirState, struct stat *filestat);
extern int _FAT_dirclose_r (struct _reent *r, DIR_STATE_STRUCT *dirState);
#endif // _FATDIR_H

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sdk-modifications/include/fatdir_ex.h
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#ifndef _FATDIR_EX_H_
#define _FATDIR_EX_H_
#include "fatdir.h"
#ifdef __cplusplus
extern "C" {
#endif
int dirnextl (DIR_ITER *dirState, char *filename, char *longFilename, struct stat *filestat);
int renamex( const char *oldName, const char *newName );
#ifdef __cplusplus
}
#endif
#endif//_FATDIR_EX_H_

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/*
fatfile.h
Functions used by the newlib disc stubs to interface with
this library
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
2006-07-17 - Chishm
* Made all path inputs const char*
* Added _FAT_rename_r
2006-07-24 - Chishm
* Removed padding workaround from FILE_STRUCT
2006-08-13 - Chishm
* Moved all externally visible directory related functions to fatdir
*/
#ifndef _FATFILE_H
#define _FATFILE_H
//#include <sys/reent.h>
#include <sys/stat.h>
#include "fs_common.h"
#include "partition.h"
#include "directory.h"
typedef struct {
u32 cluster;
u32 sector;
s32 byte;
} FILE_POSITION;
typedef struct {
int fd;
u32 filesize;
u32 startCluster;
u32 currentPosition;
FILE_POSITION rwPosition;
FILE_POSITION appendPosition;
bool read;
bool write;
bool append;
bool inUse;
PARTITION* partition;
DIR_ENTRY_POSITION dirEntryStart; // Points to the start of the LFN entries of a file, or the alias for no LFN
DIR_ENTRY_POSITION dirEntryEnd; // Always points to the file's alias entry
} FILE_STRUCT;
extern int _FAT_open_r (struct _reent *r, void *fileStruct, const char *path, int flags);
extern int _FAT_close_r (struct _reent *r, int fd);
extern int _FAT_write_r (struct _reent *r,int fd, const char *ptr, int len);
extern int _FAT_read_r (struct _reent *r, int fd, char *ptr, int len);
extern int _FAT_seek_r (struct _reent *r, int fd,int pos, int dir);
extern int _FAT_fstat_r (struct _reent *r, int fd, struct stat *st);
#endif // _FATFILE_H

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sdk-modifications/include/fatfile_ex.h
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#ifndef _FATFILE_EX_H_
#define _FATFILE_EX_H_
#include <stdio.h>
#include "fatfile.h"
#ifdef __cplusplus
extern "C" {
#endif
int freadex( void * buffer, int _size, int _n, FILE * f );
int fwritex( const void * buffer, int _size, int _n, FILE * f );
#ifdef __cplusplus
}
#endif
#endif//_FATFILE_EX_H_

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/*
file_allocation_table.h
Reading, writing and manipulation of the FAT structure on
a FAT partition
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
2006-10-01 - Chishm
* Added _FAT_fat_linkFreeClusterCleared to clear a cluster when it is allocated
*/
#ifndef _FAT_H
#define _FAT_H
#include "fs_common.h"
#include "partition.h"
#define CLUSTER_EOF_16 0xFFFF
#define CLUSTER_EOF 0x0FFFFFFF
#define CLUSTER_FREE 0x0000
#define CLUSTER_FIRST 0x0002
#define CLUSTERS_PER_FAT12 4085
#define CLUSTERS_PER_FAT16 65525
u32 _FAT_fat_nextCluster(PARTITION* partition, u32 cluster);
u32 _FAT_fat_linkFreeCluster(PARTITION* partition, u32 cluster);
u32 _FAT_fat_linkFreeClusterCleared (PARTITION* partition, u32 cluster);
bool _FAT_fat_clearLinks (PARTITION* partition, u32 cluster);
u32 _FAT_fat_lastCluster (PARTITION* partition, u32 cluster);
static inline u32 _FAT_fat_clusterToSector (PARTITION* partition, u32 cluster) {
return (cluster >= 2) ? ((cluster - 2) * partition->sectorsPerCluster) + partition->dataStart : partition->rootDirStart;
}
#endif // _FAT_H

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/*
filetime.h
Conversion of file time and date values to various other types
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _FILETIME_H
#define _FILETIME_H
#include "fs_common.h"
#include <sys/types.h>
u16 _FAT_filetime_getTimeFromRTC (void);
u16 _FAT_filetime_getDateFromRTC (void);
time_t _FAT_filetime_to_time_t (u16 time, u16 date);
#endif // _FILETIME_H

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#ifndef __FS_API_H__
#define __FS_API_H__
//v1.0
#ifdef __cplusplus
extern "C" {
#endif
#include "sys/stat.h"
#include "fatfile.h"
#include "fatdir.h"
#define mode_t unsigned int
#define size_t unsigned int
extern int fat_init(void);
extern FILE_STRUCT* fat_fopen(const char *file, const char *mode);
extern size_t fat_fread(void *buf, size_t size, size_t count, FILE_STRUCT *fp);
extern size_t fat_fwrite(const void *buf, size_t size, size_t count, FILE_STRUCT *fp);
extern int fat_fclose(FILE_STRUCT *fp);
extern int fat_fseek(FILE_STRUCT *fp, long offset, int whence);
extern long fat_ftell(FILE_STRUCT *fp);
extern int fat_feof(FILE_STRUCT *fp);
extern int fat_ferror(FILE_STRUCT *fp);
extern void fat_clearerr(FILE_STRUCT *fp);
extern int fat_fflush(FILE_STRUCT *fp);
extern int fat_fgetc(FILE_STRUCT *fp);
extern char* fat_fgets(char *buf, int n, FILE_STRUCT *fp);
extern int fat_fputc(int ch, FILE_STRUCT *fp);
extern int fat_fputs(const char *s, FILE_STRUCT *fp);
extern int fat_remove(const char *filename);
extern int fat_rename(const char *oldName, const char *newName);
extern int fat_setHidden(const char *name, unsigned char hide);
extern int fat_isHidden(struct stat *st);
extern int fat_getShortName(const char *fullName, char *outName);
extern void fat_rewind(FILE_STRUCT *fp);
extern int fat_fstat(int fildes, struct stat *buf);
extern int fat_fprintf(void* fp, const char *format, ...);
extern int fat_fscanf(FILE_STRUCT *fp, const char *format, ...);
extern DIR_STATE_STRUCT* fat_opendir(const char *name);
extern DIR_ENTRY* fat_readdir(DIR_STATE_STRUCT *dirp);
extern long fat_telldir(DIR_STATE_STRUCT *dirp);
extern void fat_seekdir(DIR_STATE_STRUCT *dirp, long int loc);
extern int fat_closedir(DIR_STATE_STRUCT *dirp);
extern int fat_chdir(const char *path);
extern char* fat_getcwd(char *buf, size_t size);
extern int fat_mkdir(const char *path, mode_t mode);
extern int fat_rmdir(const char *path);
extern int fat_lstat(const char *path, struct stat *buf);
extern DIR_ENTRY* fat_readdir_ex(DIR_STATE_STRUCT *dirp, struct stat *statbuf);
#ifndef SEEK_SET
#define SEEK_SET 0 /* Seek from beginning of file. */
#endif
#ifndef SEEK_CUR
#define SEEK_CUR 1 /* Seek from current position. */
#endif
#ifndef SEEK_END
#define SEEK_END 2 /* Seek from end of file. */
#endif
//#define S_ISDIR(st) (st.st_mode & S_IFDIR)
#define FILE FILE_STRUCT
#define fopen fat_fopen
#define fread fat_fread
#define fwrite fat_fwrite
#define fclose fat_fclose
#define fgets fat_fgets
#define fseek fat_fseek
#define ftell fat_ftell
#define feof fat_feof
#define ferror fat_ferror
#define fclearerr fat_clearerr
#define fflush fat_fflush
#define fgetc fat_fgetc
#define fgets fat_fgets
#define fputc fat_fputc
#define fputs fat_fputs
#define fprintf fat_fprintf
#define fscanf fat_fscanf
#define remove fat_remove
#define DIR DIR_STATE_STRUCT
#define dirent DIR_ENTRY
#define opendir fat_opendir
#define readdir fat_readdir
#define telldir fat_telldir
#define seekdir fat_seekdir
#define closedir fat_closedir
#define chdir fat_chdir
#define getcwd fat_getcwd
#define mkdir fat_mkdir
#define rmdir fat_rmdir
#define lstat fat_lstat
#define fstat fat_fstat
#define S_ISHID(st_mode) ((st_mode & S_IHIDDEN) != 0)
//the extended version of readdir_ex
#define readdir_ex fat_readdir_ex
#define MAX_PATH 512
#define MAX_FILE 512
//Misc function
extern bool fat_getDiskSpaceInfo( char * diskName, unsigned int *total, unsigned int *used, unsigned int *freeSpace );
#ifdef __cplusplus
}
#endif
#endif //__FS_API_H__

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/*
cache.h
The cache is not visible to the user. It should be flushed
when any file is closed or changes are made to the filesystem.
This cache implements a least-used-page replacement policy. This will
distribute sectors evenly over the pages, so if less than the maximum
pages are used at once, they should all eventually remain in the cache.
This also has the benefit of throwing out old sectors, so as not to keep
too many stale pages around.
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _CACHE_H
#define _CACHE_H
#include "fs_common.h"
#include "disc_io/disc_io.h"
#define CACHE_PAGE_SIZE BYTES_PER_READ
typedef struct {
u32 sector;
u32 count;
bool dirty;
} CACHE_ENTRY;
typedef struct {
const IO_INTERFACE* disc;
u32 numberOfPages;
CACHE_ENTRY* cacheEntries;
u8* pages;
} CACHE;
/*
Read data from a sector in the cache
If the sector is not in the cache, it will be swapped in
offset is the position to start reading from
size is the amount of data to read
Precondition: offset + size <= BYTES_PER_READ
*/
bool _FAT_cache_readPartialSector (CACHE* cache, void* buffer, u32 sector, u32 offset, u32 size);
/*
Write data to a sector in the cache
If the sector is not in the cache, it will be swapped in.
When the sector is swapped out, the data will be written to the disc
offset is the position to start reading from
size is the amount of data to read
Precondition: offset + size <= BYTES_PER_READ
*/
bool _FAT_cache_writePartialSector (CACHE* cache, const void* buffer, u32 sector, u32 offset, u32 size);
/*
Write data to a sector in the cache, zeroing the sector first
If the sector is not in the cache, it will be swapped in.
When the sector is swapped out, the data will be written to the disc
offset is the position to start reading from
size is the amount of data to read
Precondition: offset + size <= BYTES_PER_READ
*/
bool _FAT_cache_eraseWritePartialSector (CACHE* cache, const void* buffer, u32 sector, u32 offset, u32 size);
/*
Read a full sector from the cache
*/
static inline bool _FAT_cache_readSector (CACHE* cache, void* buffer, u32 sector) {
return _FAT_cache_readPartialSector (cache, buffer, sector, 0, BYTES_PER_READ);
}
/*
Write a full sector to the cache
*/
static inline bool _FAT_cache_writeSector (CACHE* cache, const void* buffer, u32 sector) {
return _FAT_cache_writePartialSector (cache, buffer, sector, 0, BYTES_PER_READ);
}
/*
Write any dirty sectors back to disc and clear out the contents of the cache
*/
bool _FAT_cache_flush (CACHE* cache);
/*
Clear out the contents of the cache without writing any dirty sectors first
*/
void _FAT_cache_invalidate (CACHE* cache);
CACHE* _FAT_cache_constructor (u32 numberOfPages, const IO_INTERFACE* discInterface);
void _FAT_cache_destructor (CACHE* cache);
#endif // _CACHE_H

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/*
common.h
Common definitions and included files for the FATlib
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _COMMON_H
#define _COMMON_H
// When compiling for NDS, make sure NDS is defined
#ifndef NDS
#if defined ARM9 || defined ARM7
#define NDS
#endif
#endif
#if 0
#ifdef NDS
#include <nds/jtypes.h>
#else
#include "gba_types.h"
#endif
#endif
#define BYTES_PER_READ 512
#ifndef NULL
#define NULL 0
#endif
#ifndef bool
#define bool int
#endif
#ifndef false
#define false 0
#endif
#ifndef true
#define true 1
#endif
#ifndef u8
#define u8 unsigned char
#endif
#ifndef u16
#define u16 unsigned short
#endif
#ifndef u32
#define u32 unsigned long
#endif
#ifndef s32
#define s32 long
#endif
struct _reent
{
/* FILE is a big struct and may change over time. To try to achieve binary
compatibility with future versions, put stdin,stdout,stderr here.
These are pointers into member __sf defined below. */
// __FILE *_stdin, *_stdout, *_stderr; /* XXX */
int _errno; /* local copy of errno */
// int _inc; /* used by tmpnam */
// char *_emergency;
// int __sdidinit; /* 1 means stdio has been init'd */
// int _current_category; /* unused */
// _CONST char *_current_locale; /* unused */
// struct _mprec *_mp;
// void _EXFNPTR(__cleanup, (struct _reent *));
// int _gamma_signgam;
/* used by some fp conversion routines */
// int _cvtlen; /* should be size_t */
// char *_cvtbuf;
// struct _rand48 *_r48;
// struct __tm *_localtime_buf;
// char *_asctime_buf;
/* signal info */
// void (**(_sig_func))(int);
/* atexit stuff */
// struct _atexit *_atexit;
// struct _atexit _atexit0;
// struct _glue __sglue; /* root of glue chain */
// __FILE *__sf; /* file descriptors */
// struct _misc_reent *_misc; /* strtok, multibyte states */
// char *_signal_buf; /* strsignal */
};
#endif // _COMMON_H

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#ifndef __FS_UNICODE_H__
#define __FS_UNICODE_H__
extern void _FAT_utf8_to_unicode16( const char* src, u16* dest );
extern void _FAT_unicode16_to_utf8( const u16* src, char* dest);
extern u32 _unistrnlen( const u16* unistr, u32 maxlen );
extern int _unistrncmp( const u16 * src, const u16 * dest, u32 maxlen );
extern const u16 * _unistrchr( const u16 * str, u16 unichar );
int _uniisalnum( u8 ch );
#endif //__FS_UNICODE_H__

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sdk-modifications/include/mem_allocate.h
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/*
mem_allocate.h
Memory allocation and destruction calls
Replace these calls with custom allocators if
malloc is unavailable
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _MEM_ALLOCATE_H
#define _MEM_ALLOCATE_H
#include "ds2_malloc.h"
static inline void* _FAT_mem_allocate (size_t size) {
return ((void*)malloc (size));
}
static inline void _FAT_mem_free (void* mem) {
return (free ((void*)mem));
}
#endif // _MEM_ALLOCATE_H

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/**************************************************************************
* *
* PROJECT : MIPS port for uC/OS-II *
* *
* MODULE : MIPS.h *
* *
* AUTHOR : Michael Anburaj *
* URL : http://geocities.com/michaelanburaj/ *
* EMAIL: michaelanburaj@hotmail.com *
* *
* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
* *
* TOOL-CHAIN : SDE & Cygnus *
* *
* DESCRIPTION : *
* MIPS processor definitions. *
* The basic CPU definitions are found in the file archdefs.h, which *
* is included by mips.h. *
* *
* mips.h implements aliases for some of the definitions in archdefs.h *
* and adds various definitions. *
* *
**************************************************************************/
#ifndef __MIPS_H__
#define __MIPS_H__
#include "archdefs.h"
/* ********************************************************************* */
/* Module configuration */
/* ********************************************************************* */
/* Interface macro & data definition */
#ifndef MSK
#define MSK(n) ((1 << (n)) - 1)
#endif
/* CPU registers */
#define SYS_CPUREG_ZERO 0
#define SYS_CPUREG_AT 1
#define SYS_CPUREG_V0 2
#define SYS_CPUREG_V1 3
#define SYS_CPUREG_A0 4
#define SYS_CPUREG_A1 5
#define SYS_CPUREG_A2 6
#define SYS_CPUREG_A3 7
#define SYS_CPUREG_T0 8
#define SYS_CPUREG_T1 9
#define SYS_CPUREG_T2 10
#define SYS_CPUREG_T3 11
#define SYS_CPUREG_T4 12
#define SYS_CPUREG_T5 13
#define SYS_CPUREG_T6 14
#define SYS_CPUREG_T7 15
#define SYS_CPUREG_S0 16
#define SYS_CPUREG_S1 17
#define SYS_CPUREG_S2 18
#define SYS_CPUREG_S3 19
#define SYS_CPUREG_S4 20
#define SYS_CPUREG_S5 21
#define SYS_CPUREG_S6 22
#define SYS_CPUREG_S7 23
#define SYS_CPUREG_T8 24
#define SYS_CPUREG_T9 25
#define SYS_CPUREG_K0 26
#define SYS_CPUREG_K1 27
#define SYS_CPUREG_GP 28
#define SYS_CPUREG_SP 29
#define SYS_CPUREG_S8 30
#define SYS_CPUREG_FP SYS_CPUREG_S8
#define SYS_CPUREG_RA 31
/* CPU register fp ($30) has an alias s8 */
#define s8 fp
/* Aliases for System Control Coprocessor (CP0) registers */
#define C0_INDEX C0_Index
#define C0_RANDOM C0_Random
#define C0_ENTRYLO0 C0_EntryLo0
#define C0_ENTRYLO1 C0_EntryLo1
#define C0_CONTEXT C0_Context
#define C0_PAGEMASK C0_PageMask
#define C0_WIRED C0_Wired
#define C0_BADVADDR C0_BadVAddr
#define C0_COUNT C0_Count
#define C0_ENTRYHI C0_EntryHi
#define C0_COMPARE C0_Compare
#define C0_STATUS C0_Status
#define C0_CAUSE C0_Cause
#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */
#undef C0_PRID
#endif
#define C0_PRID C0_PRId
#define C0_CONFIG C0_Config
#define C0_CONFIG1 C0_Config1
#define C0_LLADDR C0_LLAddr
#define C0_WATCHLO C0_WatchLo
#define C0_WATCHHI C0_WatchHi
#define C0_DEBUG C0_Debug
#define C0_PERFCNT C0_PerfCnt
#define C0_ERRCTL C0_ErrCtl
#define C0_CACHEERR C0_CacheErr
#define C0_TAGLO C0_TagLo
#define C0_DATALO C0_DataLo
#define C0_TAGHI C0_TagHi
#define C0_DATAHI C0_DataHi
#define C0_ERROREPC C0_ErrorEPC
#if 0
#define C0_DESAVE C0_DESAVE
#define C0_EPC C0_EPC
#define C0_DEPC C0_DEPC
#endif
/* System Control Coprocessor (CP0) registers select fields */
#define C0_INDEX_SEL 0 /* TLB Index */
#define C0_RANDOM_SEL 0 /* TLB Random */
#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */
#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */
#define C0_CONTEXT_SEL 0 /* Context */
#define C0_PAGEMASK_SEL 0 /* TLB PageMask */
#define C0_WIRED_SEL 0 /* TLB Wired */
#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */
#define C0_COUNT_SEL 0 /* Count */
#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */
#define C0_COMPARE_SEL 0 /* Compare */
#define C0_STATUS_SEL 0 /* Processor Status */
#define C0_CAUSE_SEL 0 /* Exception Cause */
#define C0_EPC_SEL 0 /* Exception PC */
#define C0_PRID_SEL 0 /* Processor Revision Indentifier */
#define C0_CONFIG_SEL 0 /* Config */
#define C0_CONFIG1_SEL 1 /* Config1 */
#define C0_LLADDR_SEL 0 /* LLAddr */
#define C0_WATCHLO_SEL 0 /* WatchpointLo */
#define C0_WATCHHI_SEL 0 /* WatchpointHi */
#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */
#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */
#define C0_PERFCNT_SEL 0 /* Performance counter interface */
#define C0_ERRCTL_SEL 0 /* ERRCTL */
#define C0_CACHEERR_SEL 0 /* CacheErr */
#define C0_TAGLO_SEL 0 /* TagLo */
#define C0_DATALO_SEL 1 /* DataLo */
#define C0_DTAGLO_SEL 2 /* DTagLo */
#define C0_TAGHI_SEL 0 /* TagHi */
#define C0_DATAHI_SEL 1 /* DataHi */
#define C0_DTAGHI_SEL 2 /* DTagHi */
#define C0_ERROREPC_SEL 0 /* ErrorEPC */
#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */
/* C0_CONFIG register encoding */
#define C0_CONFIG_M_SHF S_ConfigMore
#define C0_CONFIG_M_MSK M_ConfigMore
#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK
#define C0_CONFIG_BE_SHF S_ConfigBE
#define C0_CONFIG_BE_MSK M_ConfigBE
#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK
#define C0_CONFIG_AT_SHF S_ConfigAT
#define C0_CONFIG_AT_MSK M_ConfigAT
#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32
#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S
#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64
#define C0_CONFIG_AR_SHF S_ConfigAR
#define C0_CONFIG_AR_MSK M_ConfigAR
#define C0_CONFIG_MT_SHF S_ConfigMT
#define C0_CONFIG_MT_MSK M_ConfigMT
#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU
#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU
#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU
#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU
#define C0_CONFIG_K0_SHF S_ConfigK0
#define C0_CONFIG_K0_MSK M_ConfigK0
#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA
#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA
#define C0_CONFIG_K0_UNCACHED K_CacheAttrU
#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN
#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE
#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS
#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU
#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA
/* WC field.
*
* This feature is present specifically to support configuration
* testing of the core in a lead vehicle, and is not supported
* in any other environment. Attempting to use this feature
* outside of the scope of a lead vehicle is a violation of the
* MIPS Architecture, and may cause unpredictable operation of
* the processor.
*/
#define C0_CONFIG_WC_SHF 19
#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF)
#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK
/* C0_CONFIG1 register encoding */
#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize
#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize
#define C0_CONFIG1_IS_SHF S_Config1IS
#define C0_CONFIG1_IS_MSK M_Config1IS
#define C0_CONFIG1_IL_SHF S_Config1IL
#define C0_CONFIG1_IL_MSK M_Config1IL
#define C0_CONFIG1_IA_SHF S_Config1IA
#define C0_CONFIG1_IA_MSK M_Config1IA
#define C0_CONFIG1_DS_SHF S_Config1DS
#define C0_CONFIG1_DS_MSK M_Config1DS
#define C0_CONFIG1_DL_SHF S_Config1DL
#define C0_CONFIG1_DL_MSK M_Config1DL
#define C0_CONFIG1_DA_SHF S_Config1DA
#define C0_CONFIG1_DA_MSK M_Config1DA
#define C0_CONFIG1_WR_SHF S_Config1WR
#define C0_CONFIG1_WR_MSK M_Config1WR
#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK
#define C0_CONFIG1_CA_SHF S_Config1CA
#define C0_CONFIG1_CA_MSK M_Config1CA
#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK
#define C0_CONFIG1_EP_SHF S_Config1EP
#define C0_CONFIG1_EP_MSK M_Config1EP
#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK
#define C0_CONFIG1_FP_SHF S_Config1FP
#define C0_CONFIG1_FP_MSK M_Config1FP
#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK
/* C0_STATUS register encoding */
#define C0_STATUS_CU3_SHF S_StatusCU3
#define C0_STATUS_CU3_MSK M_StatusCU3
#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK
#define C0_STATUS_CU2_SHF S_StatusCU2
#define C0_STATUS_CU2_MSK M_StatusCU2
#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK
#define C0_STATUS_CU1_SHF S_StatusCU1
#define C0_STATUS_CU1_MSK M_StatusCU1
#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK
#define C0_STATUS_CU0_SHF S_StatusCU1
#define C0_STATUS_CU0_MSK M_StatusCU1
#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK
#define C0_STATUS_RP_SHF S_StatusRP
#define C0_STATUS_RP_MSK M_StatusRP
#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK
#define C0_STATUS_FR_SHF S_StatusFR
#define C0_STATUS_FR_MSK M_StatusFR
#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK
#define C0_STATUS_RE_SHF S_StatusRE
#define C0_STATUS_RE_MSK M_StatusRE
#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK
#define C0_STATUS_BEV_SHF S_StatusBEV
#define C0_STATUS_BEV_MSK M_StatusBEV
#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK
#define C0_STATUS_TS_SHF S_StatusTS
#define C0_STATUS_TS_MSK M_StatusTS
#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK
#define C0_STATUS_SR_SHF S_StatusSR
#define C0_STATUS_SR_MSK M_StatusSR
#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK
#define C0_STATUS_NMI_SHF S_StatusNMI
#define C0_STATUS_NMI_MSK M_StatusNMI
#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK
#define C0_STATUS_IM_SHF S_StatusIM
#define C0_STATUS_IM_MSK M_StatusIM
/* Note that the the definitions below indicate the interrupt number
* rather than the mask.
* (0..1 for SW interrupts and 2...7 for HW interrupts)
*/
#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM)
#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM)
#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM)
#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM)
#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM)
#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM)
#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM)
#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM)
/* Max interrupt code */
#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5
#define C0_STATUS_KSU_SHF S_StatusKSU
#define C0_STATUS_KSU_MSK M_StatusKSU
#define C0_STATUS_UM_SHF S_StatusUM
#define C0_STATUS_UM_MSK M_StatusUM
#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK
#define C0_STATUS_ERL_SHF S_StatusERL
#define C0_STATUS_ERL_MSK M_StatusERL
#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK
#define C0_STATUS_EXL_SHF S_StatusEXL
#define C0_STATUS_EXL_MSK M_StatusEXL
#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK
#define C0_STATUS_IE_SHF S_StatusIE
#define C0_STATUS_IE_MSK M_StatusIE
#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK
/* C0_PRID register encoding */
#define C0_PRID_OPT_SHF S_PRIdCoOpt
#define C0_PRID_OPT_MSK M_PRIdCoOpt
#define C0_PRID_COMP_SHF S_PRIdCoID
#define C0_PRID_COMP_MSK M_PRIdCoID
#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS
#define C0_PRID_COMP_NOT_MIPS32_64 0
#define C0_PRID_PRID_SHF S_PRIdImp
#define C0_PRID_PRID_MSK M_PRIdImp
/* Jade */
#define C0_PRID_PRID_4Kc K_PRIdImp_Jade
#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */
/* Emerald */
#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc
#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp
/* Coral */
#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc
/* Opal */
#define C0_PRID_PRID_5K K_PRIdImp_Opal
/* Ruby */
#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby
/* Other CPUs */
#define C0_PRID_PRID_R4000 K_PRIdImp_R4000
#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200
#define C0_PRID_PRID_RM70XX 0x27
#define C0_PRID_REV_SHF S_PRIdRev
#define C0_PRID_REV_MSK M_PRIdRev
#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_4Kc << \
C0_PRID_PRID_SHF) \
)
#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_4Kmp << \
C0_PRID_PRID_SHF) \
)
#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_4KEc << \
C0_PRID_PRID_SHF) \
)
#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_4KEmp << \
C0_PRID_PRID_SHF) \
)
#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_4KSc << \
C0_PRID_PRID_SHF) \
)
#define MIPS_5K ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_5K << \
C0_PRID_PRID_SHF) \
)
#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_20Kc << \
C0_PRID_PRID_SHF) \
)
#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_RM52XX << \
C0_PRID_PRID_SHF) \
)
#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
C0_PRID_COMP_SHF) | \
(C0_PRID_PRID_RM70XX << \
C0_PRID_PRID_SHF) \
)
/* C0_ENTRYHI register encoding */
#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2
#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2
#define C0_ENTRYHI_ASID_SHF S_EntryHiASID
#define C0_ENTRYHI_ASID_MSK M_EntryHiASID
/* C0_CAUSE register encoding */
#define C0_CAUSE_BD_SHF S_CauseBD
#define C0_CAUSE_BD_MSK M_CauseBD
#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK
#define C0_CAUSE_CE_SHF S_CauseCE
#define C0_CAUSE_CE_MSK M_CauseCE
#define C0_CAUSE_IV_SHF S_CauseIV
#define C0_CAUSE_IV_MSK M_CauseIV
#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK
#define C0_CAUSE_WP_SHF S_CauseWP
#define C0_CAUSE_WP_MSK M_CauseWP
#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK
#define C0_CAUSE_IP_SHF S_CauseIP
#define C0_CAUSE_IP_MSK M_CauseIP
#define C0_CAUSE_CODE_SHF S_CauseExcCode
#define C0_CAUSE_CODE_MSK M_CauseExcCode
#define C0_CAUSE_CODE_INT EX_INT
#define C0_CAUSE_CODE_MOD EX_MOD
#define C0_CAUSE_CODE_TLBL EX_TLBL
#define C0_CAUSE_CODE_TLBS EX_TLBS
#define C0_CAUSE_CODE_ADEL EX_ADEL
#define C0_CAUSE_CODE_ADES EX_ADES
#define C0_CAUSE_CODE_IBE EX_IBE
#define C0_CAUSE_CODE_DBE EX_DBE
#define C0_CAUSE_CODE_SYS EX_SYS
#define C0_CAUSE_CODE_BP EX_BP
#define C0_CAUSE_CODE_RI EX_RI
#define C0_CAUSE_CODE_CPU EX_CPU
#define C0_CAUSE_CODE_OV EX_OV
#define C0_CAUSE_CODE_TR EV_TR
#define C0_CAUSE_CODE_FPE EX_FPE
#define C0_CAUSE_CODE_WATCH EX_WATCH
#define C0_CAUSE_CODE_MCHECK EX_MCHECK
/* Max cause code */
#define C0_CAUSE_CODE_MAX EX_MCHECK
/* C0_PAGEMASK register encoding */
#define C0_PAGEMASK_MASK_SHF S_PageMaskMask
#define C0_PAGEMASK_MASK_MSK M_PageMaskMask
#define C0_PAGEMASK_MASK_4K K_PageMask4K
#define C0_PAGEMASK_MASK_16K K_PageMask16K
#define C0_PAGEMASK_MASK_64K K_PageMask64K
#define C0_PAGEMASK_MASK_256K K_PageMask256K
#define C0_PAGEMASK_MASK_1M K_PageMask1M
#define C0_PAGEMASK_MASK_4M K_PageMask4M
#define C0_PAGEMASK_MASK_16M K_PageMask16M
/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */
#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN
#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN
#define C0_ENTRYLO0_C_SHF S_EntryLoC
#define C0_ENTRYLO0_C_MSK M_EntryLoC
#define C0_ENTRYLO0_D_SHF S_EntryLoD
#define C0_ENTRYLO0_D_MSK M_EntryLoD
#define C0_ENTRYLO0_V_SHF S_EntryLoV
#define C0_ENTRYLO0_V_MSK M_EntryLoV
#define C0_ENTRYLO0_G_SHF S_EntryLoG
#define C0_ENTRYLO0_G_MSK M_EntryLoG
/* FPU (CP1) FIR register encoding */
#define C1_FIR_3D_SHF S_FIRConfig3D
#define C1_FIR_3D_MSK M_FIRConfig3D
#define C1_FIR_PS_SHF S_FIRConfigPS
#define C1_FIR_PS_MSK M_FIRConfigPS
#define C1_FIR_D_SHF S_FIRConfigD
#define C1_FIR_D_MSK M_FIRConfigD
#define C1_FIR_S_SHF S_FIRConfigS
#define C1_FIR_S_MSK M_FIRConfigS
#define C1_FIR_PRID_SHF S_FIRImp
#define C1_FIR_PRID_MSK M_FIRImp
#define C1_FIR_REV_SHF S_FIRRev
#define C1_FIR_REV_MSK M_FIRRev
/* FPU (CP1) FCSR control/status register */
#define C1_FCSR_FCC_SHF S_FCSRFCC7_1
#define C1_FCSR_FCC_MSK M_FCSRFCC7_1
#define C1_FCSR_FS_SHF S_FCSRFS
#define C1_FCSR_FS_MSK M_FCSRFS
#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK
#define C1_FCSR_CC_SHF S_FCSRCC
#define C1_FCSR_CC_MSK M_FCSRCC
#define C1_FCSR_IMPL_SHF S_FCSRImpl
#define C1_FCSR_IMPL_MSK M_FCSRImpl
#define C1_FCSR_EXC_SHF S_FCSRExc
#define C1_FCSR_EXC_MSK M_FCSRExc
#define C1_FCSR_ENA_SHF S_FCSREna
#define C1_FCSR_ENA_MSK M_FCSREna
#define C1_FCSR_FLG_SHF S_FCSRFlg
#define C1_FCSR_FLG_MSK M_FCSRFlg
#define C1_FCSR_RM_SHF S_FCSRRM
#define C1_FCSR_RM_MSK M_FCSRRM
#define C1_FCSR_RM_RN K_FCSRRM_RN
#define C1_FCSR_RM_RZ K_FCSRRM_RZ
#define C1_FCSR_RM_RP K_FCSRRM_RP
#define C1_FCSR_RM_RM K_FCSRRM_RM
/* cache operations */
#define CACHE_OP( code, type ) ( ((code) << 2) | (type) )
#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0)
#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0)
#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0)
#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1)
#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1)
#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1)
#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3)
#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0)
#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0)
#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0)
#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1)
#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1)
#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1)
#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1)
#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3)
/* Workaround for bug in early revisions of MIPS 4K family of
* processors. Only relevant in early engineering samples of test
* chips (RTL revision <= 3.0).
*
* The bug is described in :
*
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
* MIPS Document No: MD00003
*
* The bug is identified as : C16
*/
#ifndef SET_MIPS0
#define SET_MIPS0()
#define SET_PUSH()
#define SET_POP()
#endif
#define ICACHE_INVALIDATE_WORKAROUND(reg) \
SET_PUSH(); \
SET_MIPS0(); \
la reg, 999f; \
SET_POP(); \
cache ICACHE_ADDR_FILL, 0(reg); \
sync; \
nop; nop; nop; nop; \
999:
/* EMPTY_PIPELINE is used for the below cache invalidation operations.
* When $I is invalidated, there will still be operations in the
* pipeline. We make sure these are 'nop' operations.
*/
#define EMPTY_PIPELINE nop; nop; nop; nop
#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \
ICACHE_INVALIDATE_WORKAROUND(scratch); \
cache ICACHE_INDEX_INVALIDATE, 0(index); \
EMPTY_PIPELINE
#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \
ICACHE_INVALIDATE_WORKAROUND(scratch); \
cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \
EMPTY_PIPELINE
/* The sync used in the below macro is there in case we are installing
* a new instruction (flush $D, sync, invalidate $I sequence).
*/
#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \
cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \
sync; \
EMPTY_PIPELINE
/* Config1 cache field decoding */
#define CACHE_CALC_SPW(s) ( 64 << (s) )
#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 )
#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
#define CACHE_CALC_ASSOC(a) ( (a) + 1 )
/**** Move from/to Coprocessor operations ****/
/* We use ssnop instead of nop operations in order to handle
* superscalar CPUs.
* The "sll zero,zero,1" notation is compiler backwards compatible.
*/
#define SSNOP sll zero,zero,1
#define NOPS SSNOP; SSNOP; SSNOP; SSNOP
#define MFLO(dst) \
mflo dst;\
NOPS
/* Workaround for bug in early revisions of MIPS 4K family of
* processors.
*
* This concerns the nop instruction before mtc0 in the
* MTC0 macro below.
*
* The bug is described in :
*
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
* MIPS Document No: MD00003
*
* The bug is identified as : C27
*/
#define MTC0(src, dst) \
nop; \
mtc0 src,dst;\
NOPS
#define DMTC0(src, dst) \
nop; \
dmtc0 src,dst;\
NOPS
#define MFC0(dst, src) \
mfc0 dst,src;\
NOPS
#define DMFC0(dst, src) \
dmfc0 dst,src;\
NOPS
#define MFC0_SEL_OPCODE(dst, src, sel)\
.##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\
NOPS
#define MTC0_SEL_OPCODE(dst, src, sel)\
.##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\
NOPS
#define LDC1(dst, src, offs)\
.##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))
#define SDC1(src, dst, offs)\
.##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))
/* Instruction opcode fields */
#define OPC_SPECIAL 0x0
#define OPC_REGIM 0x1
#define OPC_J 0x2
#define OPC_JAL 0x3
#define OPC_BEQ 0x4
#define OPC_BNE 0x5
#define OPC_BLEZ 0x6
#define OPC_BGTZ 0x7
#define OPC_COP1 0x11
#define OPC_JALX 0x1D
#define OPC_BEQL 0x14
#define OPC_BNEL 0x15
#define OPC_BLEZL 0x16
#define OPC_BGTZL 0x17
/* Instruction function fields */
#define FUNC_JR 0x8
#define FUNC_JALR 0x9
/* Instruction rt fields */
#define RT_BLTZ 0x0
#define RT_BGEZ 0x1
#define RT_BLTZL 0x2
#define RT_BGEZL 0x3
#define RT_BLTZAL 0x10
#define RT_BGEZAL 0x11
#define RT_BLTZALL 0x12
#define RT_BGEZALL 0x13
/* Instruction rs fields */
#define RS_BC1 0x08
/* Access macros for instruction fields */
#define MIPS_OPCODE( instr) ((instr) >> 26)
#define MIPS_FUNCTION(instr) ((instr) & MSK(6))
#define MIPS_RT(instr) (((instr) >> 16) & MSK(5))
#define MIPS_RS(instr) (((instr) >> 21) & MSK(5))
#define MIPS_OFFSET(instr) ((instr) & 0xFFFF)
#define MIPS_TARGET(instr) ((instr) & MSK(26))
/* Instructions */
#define OPCODE_DERET 0x4200001f
#define OPCODE_BREAK 0x0005000d
#define OPCODE_NOP 0
#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )
#define DERET .##word OPCODE_DERET
/* MIPS16e opcodes and instruction field access macros */
#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f)
#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7)
#define MIPS16E_X(inst) (((inst) >> 26) & 0x1)
#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f)
#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3)
#define MIPS16E_OPC_EXTEND 0x1e
#define MIPS16E_OPC_JAL_X 0x03
#define MIPS16E_OPC_B 0x02
#define MIPS16E_OPC_BEQZ 0x04
#define MIPS16E_OPC_BNEZ 0x05
#define MIPS16E_OPC_I8 0x0c
#define MIPS16E_I8_FUNC_BTEQZ 0x00
#define MIPS16E_I8_FUNC_BTNEZ 0x01
#define MIPS16E_X_JALX 0x01
#define MIPS16E_OPC_RR 0x1d
#define MIPS16E_RR_FUNC_JALRC 0x00
#define MIPS16E_RR_RY_JRRX 0x00
#define MIPS16E_RR_RY_JRRA 0x01
#define MIPS16E_RR_RY_JALR 0x02
#define MIPS16E_RR_RY_JRCRX 0x04
#define MIPS16E_RR_RY_JRCRA 0x05
#define MIPS16E_RR_RY_JALRC 0x06
#define MIPS16E_OPCODE_BREAK 0xE805
#define MIPS16E_OPCODE_NOP 0x6500
/* MIPS reset vector */
#define MIPS_RESET_VECTOR 0x1fc00000
/* Clock periods per count register increment */
#define MIPS4K_COUNT_CLK_PER_CYCLE 2
#define MIPS5K_COUNT_CLK_PER_CYCLE 2
#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1
/**** MIPS 4K/5K families specific fields of CONFIG register ****/
#define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23
#define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF)
#define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU
#define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF)
/**** MIPS 20Kc specific fields of CONFIG register ****/
#define C0_CONFIG_MIPS20KC_EC_SHF 28
#define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF)
#define C0_CONFIG_MIPS20KC_DD_SHF 27
#define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF)
#define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK
#define C0_CONFIG_MIPS20KC_LP_SHF 26
#define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF)
#define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK
#define C0_CONFIG_MIPS20KC_SP_SHF 25
#define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF)
#define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK
#define C0_CONFIG_MIPS20KC_TI_SHF 24
#define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF)
#define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK
/* ********************************************************************* */
/* Interface function definition */
/* ********************************************************************* */
#endif /* #ifndef __MIPS_H__ */

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sdk-modifications/include/mipsregs.h
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@ -1,985 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2003 Maciej W. Rozycki
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
#include <linux/config.h>
#include <linux/linkage.h>
/*
* The following macros are especially useful for __asm__
* inline assembler.
*/
#ifndef __STR
#define __STR(x) #x
#endif
#ifndef STR
#define STR(x) __STR(x)
#endif
/*
* Configure language
*/
#ifdef __ASSEMBLY__
#define _ULCAST_
#else
#define _ULCAST_ (unsigned long)
#endif
/*
* Coprocessor 0 register names
*/
#define CP0_INDEX $0
#define CP0_RANDOM $1
#define CP0_ENTRYLO0 $2
#define CP0_ENTRYLO1 $3
#define CP0_CONF $3
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
#define CP0_INFO $7
#define CP0_BADVADDR $8
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
#define CP0_STATUS $12
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
#define CP0_CONFIG $16
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
#define CP0_DEBUG $23
#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
#define CP0_ECC $26
#define CP0_CACHEERR $27
#define CP0_TAGLO $28
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
#define CP0_DESAVE $31
/*
* R4640/R4650 cp0 register names. These registers are listed
* here only for completeness; without MMU these CPUs are not useable
* by Linux. A future ELKS port might take make Linux run on them
* though ...
*/
#define CP0_IBASE $0
#define CP0_IBOUND $1
#define CP0_DBASE $2
#define CP0_DBOUND $3
#define CP0_CALG $17
#define CP0_IWATCH $18
#define CP0_DWATCH $19
/*
* Coprocessor 0 Set 1 register names
*/
#define CP0_S1_DERRADDR0 $26
#define CP0_S1_DERRADDR1 $27
#define CP0_S1_INTCONTROL $20
/*
* TX39 Series
*/
#define CP0_TX39_CACHE $7
/*
* Coprocessor 1 (FPU) register names
*/
#define CP1_REVISION $0
#define CP1_STATUS $31
/*
* FPU Status Register Values
*/
/*
* Status Register Values
*/
#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
#define FPU_CSR_COND 0x00800000 /* $fcc0 */
#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
/*
* X the exception cause indicator
* E the exception enable
* S the sticky/flag bit
*/
#define FPU_CSR_ALL_X 0x0003f000
#define FPU_CSR_UNI_X 0x00020000
#define FPU_CSR_INV_X 0x00010000
#define FPU_CSR_DIV_X 0x00008000
#define FPU_CSR_OVF_X 0x00004000
#define FPU_CSR_UDF_X 0x00002000
#define FPU_CSR_INE_X 0x00001000
#define FPU_CSR_ALL_E 0x00000f80
#define FPU_CSR_INV_E 0x00000800
#define FPU_CSR_DIV_E 0x00000400
#define FPU_CSR_OVF_E 0x00000200
#define FPU_CSR_UDF_E 0x00000100
#define FPU_CSR_INE_E 0x00000080
#define FPU_CSR_ALL_S 0x0000007c
#define FPU_CSR_INV_S 0x00000040
#define FPU_CSR_DIV_S 0x00000020
#define FPU_CSR_OVF_S 0x00000010
#define FPU_CSR_UDF_S 0x00000008
#define FPU_CSR_INE_S 0x00000004
/* rounding mode */
#define FPU_CSR_RN 0x0 /* nearest */
#define FPU_CSR_RZ 0x1 /* towards zero */
#define FPU_CSR_RU 0x2 /* towards +Infinity */
#define FPU_CSR_RD 0x3 /* towards -Infinity */
/*
* Values for PageMask register
*/
#ifdef CONFIG_CPU_VR41XX
/* Why doesn't stupidity hurt ... */
#define PM_1K 0x00000000
#define PM_4K 0x00001800
#define PM_16K 0x00007800
#define PM_64K 0x0001f800
#define PM_256K 0x0007f800
#else
#define PM_4K 0x00000000
#define PM_16K 0x00006000
#define PM_64K 0x0001e000
#define PM_256K 0x0007e000
#define PM_1M 0x001fe000
#define PM_4M 0x007fe000
#define PM_16M 0x01ffe000
#define PM_64M 0x07ffe000
#define PM_256M 0x1fffe000
#endif
/*
* Values used for computation of new tlb entries
*/
#define PL_4K 12
#define PL_16K 14
#define PL_64K 16
#define PL_256K 18
#define PL_1M 20
#define PL_4M 22
#define PL_16M 24
#define PL_64M 26
#define PL_256M 28
/*
* R4x00 interrupt enable / cause bits
*/
#define IE_SW0 (_ULCAST_(1) << 8)
#define IE_SW1 (_ULCAST_(1) << 9)
#define IE_IRQ0 (_ULCAST_(1) << 10)
#define IE_IRQ1 (_ULCAST_(1) << 11)
#define IE_IRQ2 (_ULCAST_(1) << 12)
#define IE_IRQ3 (_ULCAST_(1) << 13)
#define IE_IRQ4 (_ULCAST_(1) << 14)
#define IE_IRQ5 (_ULCAST_(1) << 15)
/*
* R4x00 interrupt cause bits
*/
#define C_SW0 (_ULCAST_(1) << 8)
#define C_SW1 (_ULCAST_(1) << 9)
#define C_IRQ0 (_ULCAST_(1) << 10)
#define C_IRQ1 (_ULCAST_(1) << 11)
#define C_IRQ2 (_ULCAST_(1) << 12)
#define C_IRQ3 (_ULCAST_(1) << 13)
#define C_IRQ4 (_ULCAST_(1) << 14)
#define C_IRQ5 (_ULCAST_(1) << 15)
/*
* Bitfields in the R4xx0 cp0 status register
*/
#define ST0_IE 0x00000001
#define ST0_EXL 0x00000002
#define ST0_ERL 0x00000004
#define ST0_KSU 0x00000018
# define KSU_USER 0x00000010
# define KSU_SUPERVISOR 0x00000008
# define KSU_KERNEL 0x00000000
#define ST0_UX 0x00000020
#define ST0_SX 0x00000040
#define ST0_KX 0x00000080
#define ST0_DE 0x00010000
#define ST0_CE 0x00020000
/*
* Bitfields in the R[23]000 cp0 status register.
*/
#define ST0_IEC 0x00000001
#define ST0_KUC 0x00000002
#define ST0_IEP 0x00000004
#define ST0_KUP 0x00000008
#define ST0_IEO 0x00000010
#define ST0_KUO 0x00000020
/* bits 6 & 7 are reserved on R[23]000 */
#define ST0_ISC 0x00010000
#define ST0_SWC 0x00020000
#define ST0_CM 0x00080000
/*
* Bits specific to the R4640/R4650
*/
#define ST0_UM (_ULCAST_(1) << 4)
#define ST0_IL (_ULCAST_(1) << 23)
#define ST0_DL (_ULCAST_(1) << 24)
/*
* Bitfields in the TX39 family CP0 Configuration Register 3
*/
#define TX39_CONF_ICS_SHIFT 19
#define TX39_CONF_ICS_MASK 0x00380000
#define TX39_CONF_ICS_1KB 0x00000000
#define TX39_CONF_ICS_2KB 0x00080000
#define TX39_CONF_ICS_4KB 0x00100000
#define TX39_CONF_ICS_8KB 0x00180000
#define TX39_CONF_ICS_16KB 0x00200000
#define TX39_CONF_DCS_SHIFT 16
#define TX39_CONF_DCS_MASK 0x00070000
#define TX39_CONF_DCS_1KB 0x00000000
#define TX39_CONF_DCS_2KB 0x00010000
#define TX39_CONF_DCS_4KB 0x00020000
#define TX39_CONF_DCS_8KB 0x00030000
#define TX39_CONF_DCS_16KB 0x00040000
#define TX39_CONF_CWFON 0x00004000
#define TX39_CONF_WBON 0x00002000
#define TX39_CONF_RF_SHIFT 10
#define TX39_CONF_RF_MASK 0x00000c00
#define TX39_CONF_DOZE 0x00000200
#define TX39_CONF_HALT 0x00000100
#define TX39_CONF_LOCK 0x00000080
#define TX39_CONF_ICE 0x00000020
#define TX39_CONF_DCE 0x00000010
#define TX39_CONF_IRSIZE_SHIFT 2
#define TX39_CONF_IRSIZE_MASK 0x0000000c
#define TX39_CONF_DRSIZE_SHIFT 0
#define TX39_CONF_DRSIZE_MASK 0x00000003
/*
* Status register bits available in all MIPS CPUs.
*/
#define ST0_IM 0x0000ff00
#define STATUSB_IP0 8
#define STATUSF_IP0 (_ULCAST_(1) << 8)
#define STATUSB_IP1 9
#define STATUSF_IP1 (_ULCAST_(1) << 9)
#define STATUSB_IP2 10
#define STATUSF_IP2 (_ULCAST_(1) << 10)
#define STATUSB_IP3 11
#define STATUSF_IP3 (_ULCAST_(1) << 11)
#define STATUSB_IP4 12
#define STATUSF_IP4 (_ULCAST_(1) << 12)
#define STATUSB_IP5 13
#define STATUSF_IP5 (_ULCAST_(1) << 13)
#define STATUSB_IP6 14
#define STATUSF_IP6 (_ULCAST_(1) << 14)
#define STATUSB_IP7 15
#define STATUSF_IP7 (_ULCAST_(1) << 15)
#define STATUSB_IP8 0
#define STATUSF_IP8 (_ULCAST_(1) << 0)
#define STATUSB_IP9 1
#define STATUSF_IP9 (_ULCAST_(1) << 1)
#define STATUSB_IP10 2
#define STATUSF_IP10 (_ULCAST_(1) << 2)
#define STATUSB_IP11 3
#define STATUSF_IP11 (_ULCAST_(1) << 3)
#define STATUSB_IP12 4
#define STATUSF_IP12 (_ULCAST_(1) << 4)
#define STATUSB_IP13 5
#define STATUSF_IP13 (_ULCAST_(1) << 5)
#define STATUSB_IP14 6
#define STATUSF_IP14 (_ULCAST_(1) << 6)
#define STATUSB_IP15 7
#define STATUSF_IP15 (_ULCAST_(1) << 7)
#define ST0_CH 0x00040000
#define ST0_SR 0x00100000
#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
#define ST0_RE 0x02000000
#define ST0_FR 0x04000000
#define ST0_CU 0xf0000000
#define ST0_CU0 0x10000000
#define ST0_CU1 0x20000000
#define ST0_CU2 0x40000000
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000 /* MIPS IV naming */
/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
#define CAUSEB_EXCCODE 2
#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
#define CAUSEB_IP 8
#define CAUSEF_IP (_ULCAST_(255) << 8)
#define CAUSEB_IP0 8
#define CAUSEF_IP0 (_ULCAST_(1) << 8)
#define CAUSEB_IP1 9
#define CAUSEF_IP1 (_ULCAST_(1) << 9)
#define CAUSEB_IP2 10
#define CAUSEF_IP2 (_ULCAST_(1) << 10)
#define CAUSEB_IP3 11
#define CAUSEF_IP3 (_ULCAST_(1) << 11)
#define CAUSEB_IP4 12
#define CAUSEF_IP4 (_ULCAST_(1) << 12)
#define CAUSEB_IP5 13
#define CAUSEF_IP5 (_ULCAST_(1) << 13)
#define CAUSEB_IP6 14
#define CAUSEF_IP6 (_ULCAST_(1) << 14)
#define CAUSEB_IP7 15
#define CAUSEF_IP7 (_ULCAST_(1) << 15)
#define CAUSEB_IV 23
#define CAUSEF_IV (_ULCAST_(1) << 23)
#define CAUSEB_CE 28
#define CAUSEF_CE (_ULCAST_(3) << 28)
#define CAUSEB_BD 31
#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
* Bits in the coprocessor 0 config register.
*/
/* Generic bits. */
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
#define CONF_CM_UNCACHED 2
#define CONF_CM_CACHABLE_NONCOHERENT 3
#define CONF_CM_CACHABLE_CE 4
#define CONF_CM_CACHABLE_COW 5
#define CONF_CM_CACHABLE_CUW 6
#define CONF_CM_CACHABLE_ACCELERATED 7
#define CONF_CM_CMASK 7
#define CONF_BE (_ULCAST_(1) << 15)
/* Bits common to various processors. */
#define CONF_CU (_ULCAST_(1) << 3)
#define CONF_DB (_ULCAST_(1) << 4)
#define CONF_IB (_ULCAST_(1) << 5)
#define CONF_DC (_ULCAST_(7) << 6)
#define CONF_IC (_ULCAST_(7) << 9)
#define CONF_EB (_ULCAST_(1) << 13)
#define CONF_EM (_ULCAST_(1) << 14)
#define CONF_SM (_ULCAST_(1) << 16)
#define CONF_SC (_ULCAST_(1) << 17)
#define CONF_EW (_ULCAST_(3) << 18)
#define CONF_EP (_ULCAST_(15)<< 24)
#define CONF_EC (_ULCAST_(7) << 28)
#define CONF_CM (_ULCAST_(1) << 31)
/* Bits specific to the R4xx0. */
#define R4K_CONF_SW (_ULCAST_(1) << 20)
#define R4K_CONF_SS (_ULCAST_(1) << 21)
#define R4K_CONF_SB (_ULCAST_(3) << 22)
/* Bits specific to the R5000. */
#define R5K_CONF_SE (_ULCAST_(1) << 12)
#define R5K_CONF_SS (_ULCAST_(3) << 20)
/* Bits specific to the R10000. */
#define R10K_CONF_DN (_ULCAST_(3) << 3)
#define R10K_CONF_CT (_ULCAST_(1) << 5)
#define R10K_CONF_PE (_ULCAST_(1) << 6)
#define R10K_CONF_PM (_ULCAST_(3) << 7)
#define R10K_CONF_EC (_ULCAST_(15)<< 9)
#define R10K_CONF_SB (_ULCAST_(1) << 13)
#define R10K_CONF_SK (_ULCAST_(1) << 14)
#define R10K_CONF_SS (_ULCAST_(7) << 16)
#define R10K_CONF_SC (_ULCAST_(7) << 19)
#define R10K_CONF_DC (_ULCAST_(7) << 26)
#define R10K_CONF_IC (_ULCAST_(7) << 29)
/* Bits specific to the VR41xx. */
#define VR41_CONF_CS (_ULCAST_(1) << 12)
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
#define VR41_CONF_AD (_ULCAST_(1) << 23)
/* Bits specific to the R30xx. */
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
#define R30XX_CONF_RF (_ULCAST_(1) << 24)
#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
#define R30XX_CONF_SB (_ULCAST_(1) << 30)
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
/* Bits specific to the TX49. */
#define TX49_CONF_DC (_ULCAST_(1) << 16)
#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
/* Bits specific to the MIPS32/64 PRA. */
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
/*
* R10000 performance counter definitions.
*
* FIXME: The R10000 performance counter opens a nice way to implement CPU
* time accounting with a precission of one cycle. I don't have
* R10000 silicon but just a manual, so ...
*/
/*
* Events counted by counter #0
*/
#define CE0_CYCLES 0
#define CE0_INSN_ISSUED 1
#define CE0_LPSC_ISSUED 2
#define CE0_S_ISSUED 3
#define CE0_SC_ISSUED 4
#define CE0_SC_FAILED 5
#define CE0_BRANCH_DECODED 6
#define CE0_QW_WB_SECONDARY 7
#define CE0_CORRECTED_ECC_ERRORS 8
#define CE0_ICACHE_MISSES 9
#define CE0_SCACHE_I_MISSES 10
#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
#define CE0_EXT_INTERVENTIONS_REQ 12
#define CE0_EXT_INVALIDATE_REQ 13
#define CE0_VIRTUAL_COHERENCY_COND 14
#define CE0_INSN_GRADUATED 15
/*
* Events counted by counter #1
*/
#define CE1_CYCLES 0
#define CE1_INSN_GRADUATED 1
#define CE1_LPSC_GRADUATED 2
#define CE1_S_GRADUATED 3
#define CE1_SC_GRADUATED 4
#define CE1_FP_INSN_GRADUATED 5
#define CE1_QW_WB_PRIMARY 6
#define CE1_TLB_REFILL 7
#define CE1_BRANCH_MISSPREDICTED 8
#define CE1_DCACHE_MISS 9
#define CE1_SCACHE_D_MISSES 10
#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
#define CE1_EXT_INTERVENTION_HITS 12
#define CE1_EXT_INVALIDATE_REQ 13
#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
/*
* These flags define in which priviledge mode the counters count events
*/
#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
#ifndef __ASSEMBLY__
#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
/*
* Functions to access the r10k performance counter and control registers
*/
#define read_r10k_perf_cntr(counter) \
({ unsigned int __res; \
__asm__ __volatile__( \
"mfpc\t%0, "STR(counter) \
: "=r" (__res)); \
__res;})
#define write_r10k_perf_cntr(counter,val) \
__asm__ __volatile__( \
"mtpc\t%0, "STR(counter) \
: : "r" (val));
#define read_r10k_perf_cntl(counter) \
({ unsigned int __res; \
__asm__ __volatile__( \
"mfps\t%0, "STR(counter) \
: "=r" (__res)); \
__res;})
#define write_r10k_perf_cntl(counter,val) \
__asm__ __volatile__( \
"mtps\t%0, "STR(counter) \
: : "r" (val));
/*
* Macros to access the system control coprocessor
*/
#define __read_32bit_c0_register(source, sel) \
({ int __res; \
if (sel == 0) \
__asm__ __volatile__( \
"mfc0\t%0, " #source "\n\t" \
: "=r" (__res)); \
else \
__asm__ __volatile__( \
".set\tmips32\n\t" \
"mfc0\t%0, " #source ", " #sel "\n\t" \
".set\tmips0\n\t" \
: "=r" (__res)); \
__res; \
})
#define __read_64bit_c0_register(source, sel) \
({ unsigned long __res; \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmfc0\t%0, " #source "\n\t" \
".set\tmips0" \
: "=r" (__res)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmfc0\t%0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: "=r" (__res)); \
__res; \
})
#define __write_32bit_c0_register(register, sel, value) \
do { \
if (sel == 0) \
__asm__ __volatile__( \
"mtc0\t%z0, " #register "\n\t" \
: : "Jr" (value)); \
else \
__asm__ __volatile__( \
".set\tmips32\n\t" \
"mtc0\t%z0, " #register ", " #sel "\n\t" \
".set\tmips0" \
: : "Jr" (value)); \
} while (0)
#define __write_64bit_c0_register(register, sel, value) \
do { \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmtc0\t%z0, " #register "\n\t" \
".set\tmips0" \
: : "Jr" (value)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
".set\tmips0" \
: : "Jr" (value)); \
} while (0)
#define __read_ulong_c0_register(reg, sel) \
((sizeof(unsigned long) == 4) ? \
__read_32bit_c0_register(reg, sel) : \
__read_64bit_c0_register(reg, sel))
#define __write_ulong_c0_register(reg, sel, val) \
do { \
if (sizeof(unsigned long) == 4) \
__write_32bit_c0_register(reg, sel, val); \
else \
__write_64bit_c0_register(reg, sel, val); \
} while (0)
/*
* These versions are only needed for systems with more than 38 bits of
* physical address space running the 32-bit kernel. That's none atm :-)
*/
#define __read_64bit_c0_split(source, sel) \
({ \
unsigned long long val; \
unsigned long flags; \
\
local_irq_save(flags); \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (val)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (val)); \
local_irq_restore(flags); \
\
val; \
})
#define __write_64bit_c0_split(source, sel, val) \
do { \
unsigned long flags; \
\
local_irq_save(flags); \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source "\n\t" \
".set\tmips0" \
: : "r" (val)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: : "r" (val)); \
local_irq_restore(flags); \
} while (0)
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
#define read_c0_conf() __read_32bit_c0_register($3, 0)
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
#define read_c0_context() __read_ulong_c0_register($4, 0)
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
#define read_c0_wired() __read_32bit_c0_register($6, 0)
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
#define read_c0_info() __read_32bit_c0_register($7, 0)
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
#define read_c0_compare() __read_32bit_c0_register($11, 0)
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
#define read_c0_cause() __read_32bit_c0_register($13, 0)
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
#define read_c0_prid() __read_32bit_c0_register($15, 0)
#define read_c0_config() __read_32bit_c0_register($16, 0)
#define read_c0_config1() __read_32bit_c0_register($16, 1)
#define read_c0_config2() __read_32bit_c0_register($16, 2)
#define read_c0_config3() __read_32bit_c0_register($16, 3)
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
/*
* The WatchLo register. There may be upto 8 of them.
*/
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
/*
* The WatchHi register. There may be upto 8 of them.
*/
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
#define read_c0_debug() __read_32bit_c0_register($23, 0)
#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
#define read_c0_depc() __read_ulong_c0_register($24, 0)
#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
#define read_c0_epc() __read_ulong_c0_register($14, 0)
#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
#if 1
/*
* Macros to access the system control coprocessor
*/
#define read_32bit_cp0_register(source) \
({ int __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
"mfc0\t%0,"STR(source)"\n\t" \
".set\tpop" \
: "=r" (__res)); \
__res;})
#define read_32bit_cp0_set1_register(source) \
({ int __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
"cfc0\t%0,"STR(source)"\n\t" \
".set\tpop" \
: "=r" (__res)); \
__res;})
/*
* For now use this only with interrupts disabled!
*/
#define read_64bit_cp0_register(source) \
({ int __res; \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmfc0\t%0,"STR(source)"\n\t" \
".set\tmips0" \
: "=r" (__res)); \
__res;})
#define write_32bit_cp0_register(register,value) \
__asm__ __volatile__( \
"mtc0\t%0,"STR(register)"\n\t" \
"nop" \
: : "r" (value));
#define write_32bit_cp0_set1_register(register,value) \
__asm__ __volatile__( \
"ctc0\t%0,"STR(register)"\n\t" \
"nop" \
: : "r" (value));
#define write_64bit_cp0_register(register,value) \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmtc0\t%0,"STR(register)"\n\t" \
".set\tmips0" \
: : "r" (value))
/*
* This should be changed when we get a compiler that support the MIPS32 ISA.
*/
#define read_mips32_cp0_config1() \
({ int __res; \
__asm__ __volatile__( \
".set\tnoreorder\n\t" \
".set\tnoat\n\t" \
"#.set\tmips64\n\t" \
"#mfc0\t$1, $16, 1\n\t" \
"#.set\tmips0\n\t" \
".word\t0x40018001\n\t" \
"move\t%0,$1\n\t" \
".set\tat\n\t" \
".set\treorder" \
:"=r" (__res)); \
__res;})
#endif
/*
* Macros to access the floating point coprocessor control registers
*/
#define read_32bit_cp1_register(source) \
({ int __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
"cfc1\t%0,"STR(source)"\n\t" \
".set\tpop" \
: "=r" (__res)); \
__res;})
/* TLB operations. */
static inline void tlb_probe(void)
{
__asm__ __volatile__(
".set noreorder\n\t"
"tlbp\n\t"
".set reorder");
}
static inline void tlb_read(void)
{
__asm__ __volatile__(
".set noreorder\n\t"
"tlbr\n\t"
".set reorder");
}
static inline void tlb_write_indexed(void)
{
__asm__ __volatile__(
".set noreorder\n\t"
"tlbwi\n\t"
".set reorder");
}
static inline void tlb_write_random(void)
{
__asm__ __volatile__(
".set noreorder\n\t"
"tlbwr\n\t"
".set reorder");
}
/*
* Manipulate bits in a c0 register.
*/
#define __BUILD_SET_C0(name,register) \
static inline unsigned int \
set_c0_##name(unsigned int set) \
{ \
unsigned int res; \
\
res = read_c0_##name(); \
res |= set; \
write_c0_##name(res); \
\
return res; \
} \
\
static inline unsigned int \
clear_c0_##name(unsigned int clear) \
{ \
unsigned int res; \
\
res = read_c0_##name(); \
res &= ~clear; \
write_c0_##name(res); \
\
return res; \
} \
\
static inline unsigned int \
change_c0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
\
res = read_c0_##name(); \
res &= ~change; \
res |= (new & change); \
write_c0_##name(res); \
\
return res; \
}
__BUILD_SET_C0(status,CP0_STATUS)
__BUILD_SET_C0(cause,CP0_CAUSE)
__BUILD_SET_C0(config,CP0_CONFIG)
#define set_cp0_status(x) set_c0_status(x)
#define set_cp0_cause(x) set_c0_cause(x)
#define set_cp0_config(x) set_c0_config(x)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */

56
sdk-modifications/include/mmc_api.h
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@ -1,56 +0,0 @@
#ifndef __MMC_API_H__
#define __MMC_API_H__
/* Error codes */
enum mmc_result_t {
MMC_NO_RESPONSE = -1,
MMC_NO_ERROR = 0,
MMC_ERROR_OUT_OF_RANGE,
MMC_ERROR_ADDRESS,
MMC_ERROR_BLOCK_LEN,
MMC_ERROR_ERASE_SEQ,
MMC_ERROR_ERASE_PARAM,
MMC_ERROR_WP_VIOLATION,
MMC_ERROR_CARD_IS_LOCKED,
MMC_ERROR_LOCK_UNLOCK_FAILED,
MMC_ERROR_COM_CRC,
MMC_ERROR_ILLEGAL_COMMAND,
MMC_ERROR_CARD_ECC_FAILED,
MMC_ERROR_CC,
MMC_ERROR_GENERAL,
MMC_ERROR_UNDERRUN,
MMC_ERROR_OVERRUN,
MMC_ERROR_CID_CSD_OVERWRITE,
MMC_ERROR_STATE_MISMATCH,
MMC_ERROR_HEADER_MISMATCH,
MMC_ERROR_TIMEOUT,
MMC_ERROR_CRC,
MMC_ERROR_DRIVER_FAILURE,
};
/* Get card's sectors*/
extern unsigned int MMC_GetSize(void);
/* initialize MMC/SD card */
extern int MMC_Initialize(void);
/* read a single block from MMC/SD card */
extern int MMC_ReadBlock(unsigned int blockaddr, unsigned char *recbuf);
/* read multi blocks from MMC/SD card */
extern int MMC_ReadMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf);
/* write a block to MMC/SD card */
extern int MMC_WriteBlock(unsigned int blockaddr, unsigned char *recbuf);
/* write multi blocks to MMC/SD card */
extern int MMC_WriteMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf);
/* detect MMC/SD card */
extern int MMC_DetectStatus(void);
#endif /* __MMC_API_H__ */

131
sdk-modifications/include/partition.h
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@ -1,131 +0,0 @@
/*
partition.h
Functions for mounting and dismounting partitions
on various block devices.
Copyright (c) 2006 Michael "Chishm" Chisholm
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2006-07-11 - Chishm
* Original release
*/
#ifndef _PARTITION_H
#define _PARTITION_H
#include "fs_common.h"
#include "disc_io/disc.h"
#include "fs_cache.h"
// Device name
extern const char* DEVICE_NAME;
// Filesystem type
typedef enum {FS_UNKNOWN, FS_FAT12, FS_FAT16, FS_FAT32} FS_TYPE;
#ifdef NDS
typedef enum {PI_DEFAULT, PI_SLOT_1, PI_SLOT_2, PI_CUSTOM} PARTITION_INTERFACE;
#else
typedef enum {PI_CART_SLOT} PARTITION_INTERFACE;
#endif
typedef struct {
u32 fatStart;
u32 sectorsPerFat;
u32 lastCluster;
u32 firstFree;
} FAT;
typedef struct {
const IO_INTERFACE* disc;
CACHE* cache;
// Info about the partition
bool readOnly; // If this is set, then do not try writing to the disc
FS_TYPE filesysType;
u32 totalSize;
u32 rootDirStart;
u32 rootDirCluster;
u32 numberOfSectors;
u32 dataStart;
u32 bytesPerSector;
u32 sectorsPerCluster;
u32 bytesPerCluster;
FAT fat;
// Values that may change after construction
u32 cwdCluster; // Current working directory cluser
u32 openFileCount;
} PARTITION;
/*
Mount the device specified by partitionDevice
PD_DEFAULT is not allowed, use _FAT_partition_setDefaultDevice
PD_CUSTOM is not allowed, use _FAT_partition_mountCustomDevice
*/
bool _FAT_partition_mount (PARTITION_INTERFACE partitionNumber, u32 cacheSize);
/*
Mount a partition on a custom device
*/
bool _FAT_partition_mountCustomInterface (const IO_INTERFACE* device, u32 cacheSize);
/*
Free Mount a partition on a custom device
*/
bool _FAT_partition_freeMount( int partitionNumber, const IO_INTERFACE* device, u32 cacheSize);
/*
Unmount the partition specified by partitionNumber
If there are open files, it will fail
*/
bool _FAT_partition_unmount (PARTITION_INTERFACE partitionNumber);
/*
Forcibly unmount the partition specified by partitionNumber
Any open files on the partition will become invalid
The cache will be invalidated, and any unflushed writes will be lost
*/
bool _FAT_partition_unsafeUnmount (PARTITION_INTERFACE partitionNumber);
/*
Set the default device for access by fat: and fat0:,
based on the device number
*/
bool _FAT_partition_setDefaultInterface (PARTITION_INTERFACE partitionNumber);
/*
Set the default device for access by fat: and fat0:,
based on the partition pointer
*/
bool _FAT_partition_setDefaultPartition (PARTITION* partition);
/*
Return the partition specified in a path
For instance, "fat0:", "fat:", "/" and "fat:/" will all
return the default partition
*/
PARTITION* _FAT_partition_getPartitionFromPath (const char* path);
#endif // _PARTITION_H

10
sdk-modifications/include/tcm.h
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@ -1,10 +0,0 @@
#ifndef __TCM_H
#define __TCM_H
/*
* Function: makes cpu to idle state. It will be waken up by RTC in the next second.
* Of course, it can be waken up by keys at any time.
*/
int enable_enter_idle(void);
#endif

0
sdk-modifications/libsrc/.depend
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13
sdk-modifications/libsrc/Makefile
View File

@ -13,7 +13,7 @@ CONSOLE_DIR = $(TOPDIR)/console
FS_DIR = $(TOPDIR)/fs
KEY_DIR = $(TOPDIR)/key
ZLIB_DIR = $(TOPDIR)/zlib
DMA_DIR = $(TOPDIR)/dma
CORE_DIR = $(TOPDIR)/core
SRC :=
@ -24,14 +24,17 @@ INCLUDES := -I../include
INC := $(INCLUDES)
CFLAGS := -mips32 -O3 -mno-abicalls -fno-pic -fno-builtin \
-fno-exceptions -ffunction-sections -mlong-calls\
-fomit-frame-pointer -msoft-float -G 4
-fno-exceptions -ffunction-sections -mno-long-calls\
-fomit-frame-pointer -msoft-float -G 4 \
-fgcse-sm -fgcse-las -fgcse-after-reload \
-fweb -fpeel-loops
include $(CONSOLE_DIR)/console.mk
include $(FS_DIR)/fs.mk
include $(KEY_DIR)/key.mk
include $(ZLIB_DIR)/zlib.mk
include $(DMA_DIR)/dma.mk
include $(CORE_DIR)/core.mk
#OBJS := $(addsuffix .o , $(basename $(notdir $(SRC))))
#SOBJS := $(addsuffix .o , $(basename $(notdir $(SSRC))))

28
sdk-modifications/libsrc/changes_bag.txt Normal file
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@ -0,0 +1,28 @@
Unofficial libds2a by BassAceGold
Based on 0.13 beta Supercard SDK release, contains full lib with changes
release 1:
-inclusion of ds2_unistd.h and ds2_fcntl.h
-updated zlib to 1.5.2
release 2:
-mkdir no longer freezes
-faster fopen times for file reading
(no longer searches for the next cluster to write to with read only mode)
-makes DS2's DMA (direct memory access hardware) features publically available
-adds extra cpu clock speeds (may be unstable)
ds2_setCPULevel(level)
-can now get the current CPU clock speed as an integer value
ds2_getCPUClock()
release 2 fix 1:
-added ds2_udelay and ds2_mdelay variant functions.
must be used with ds2_setCPULevel for accurate timings,
old functions, udelay and mdelay, should not be used with the new
cpu clock functions
-added further optimizations to makefile
release 2 fix 2:
-fat_getDiskSpaceInfo no longer freezes

0
sdk-modifications/libsrc/console/console.c Normal file → Executable file
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0
sdk-modifications/libsrc/console/console.h Normal file → Executable file
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0
sdk-modifications/libsrc/console/console.mk Normal file → Executable file
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0
sdk-modifications/libsrc/console/font_dot.h Normal file → Executable file
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11
sdk-modifications/libsrc/core/core.mk Normal file
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@ -0,0 +1,11 @@
#fs.mk
SRC += $(CORE_DIR)/ds2_dma.c \
$(CORE_DIR)/ds2_cpuclock.c
SSRC +=
INC += -I$(CORE_DIR)
CFLAGS +=

272
sdk-modifications/libsrc/core/ds2_cpuclock.c Normal file
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@ -0,0 +1,272 @@
#include <ds2_types.h>
#include "ds2_cpuclock.h"
#define REG8(addr) *((volatile u8 *)(addr))
#define REG16(addr) *((volatile u16 *)(addr))
#define REG32(addr) *((volatile u32 *)(addr))
#define SDRAM_TRAS 50 /* RAS# Active Time */
#define SDRAM_RCD 23 /* RAS# to CAS# Delay */
#define SDRAM_TPC 23 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 7813 /* Refresh period: 8192 refresh cycles/64ms */
#define EMC_BASE 0xB3010000
#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
#define REG_EMC_DMCR REG32(EMC_DMCR)
#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
#define REG_EMC_RTCSR REG16(EMC_RTCSR)
#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
#define REG_EMC_RTCOR REG16(EMC_RTCOR)
#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
#define REG_EMC_RTCNT REG16(EMC_RTCNT)
#define CPM_BASE 0xB0000000
#define CPM_CPCCR (CPM_BASE+0x00)
#define CPM_CPPCR (CPM_BASE+0x10)
//#define CPM_RSR (CPM_BASE+0x08)
#define REG_CPM_CPCCR REG32(CPM_CPCCR)
#define REG_CPM_CPPCR REG32(CPM_CPPCR)
#define CPM_CPCCR_CE (1 << 22)
#define EMC_DMCR_TRAS_BIT 13
#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
#define EMC_DMCR_RCD_BIT 11
#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
#define EMC_DMCR_TPC_BIT 8
#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
#define EMC_DMCR_TRWL_BIT 5
#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
#define EMC_DMCR_TRC_BIT 2
#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
#define EMC_RTCSR_CKS_BIT 0
#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
#define CPM_CPCCR_LDIV_BIT 16
#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
#define CPM_CPCCR_MDIV_BIT 12
#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
#define CPM_CPCCR_PDIV_BIT 8
#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
#define CPM_CPCCR_HDIV_BIT 4
#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
#define CPM_CPCCR_CDIV_BIT 0
#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
#define CPM_CPPCR_PLLM_BIT 23
#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
#define CPM_CPPCR_PLLN_BIT 18
#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
#define CPM_CPPCR_PLLOD_BIT 16
#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
#define CPM_CPPCR_PLLS (1 << 10)
#define CPM_CPPCR_PLLBP (1 << 9)
#define CPM_CPPCR_PLLEN (1 << 8)
#define CPM_CPPCR_PLLST_BIT 0
#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
#define PLL_M 0
#define PLL_N 1
#define PLL_CCLK 2
#define PLL_HCLK 3
#define PLL_MCLK 4
#define PLL_PCLK 5
#define CFG_EXTAL 24000000
#define EXTAL_CLK CFG_EXTAL
#define __cpm_get_pllm() \
((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
#define __cpm_get_plln() \
((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
#define __cpm_get_cdiv() \
((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
static unsigned char pll_m_n[CPU_MAX_LEVEL_EX + 1][6] = {
//M, N, CCLK, HCLK, MCLK, PCLK, EXT_CLK=24MHz
{10-2, 2-2, 1, 1, 1, 1}, //0 60, 60, 1/1
{10-2, 2-2, 0, 1, 1, 1}, //1 120, 60, 1/2
{10-2, 2-2, 0, 0, 0, 0}, //2 120, 120, 1/1
{12-2, 2-2, 0, 1, 1, 1}, //3 144, 72, 1/2
{16-2, 2-2, 0, 1, 1, 1}, //4 192, 96, 1/2
{17-2, 2-2, 0, 0, 1, 1}, //5 204, 102, 1/2
{20-2, 2-2, 0, 1, 1, 1}, //6 240, 120, 1/2
{22-2, 2-2, 0, 2, 2, 2}, //7 264, 88, 1/3
{24-2, 2-2, 0, 2, 2, 2}, //8 288, 96, 1/3
{25-2, 2-2, 0, 2, 2, 2}, //9 300, 100, 1/3
{28-2, 2-2, 0, 2, 2, 2}, //10 336, 112, 1/3
{30-2, 2-2, 0, 2, 2, 2}, //11 360, 120, 1/3
{32-2, 2-2, 0, 2, 2, 2}, //12 384, 128, 1/3
{33-2, 2-2, 0, 2, 2, 2}, //13 396, 132, 1/3
{34-2, 2-2, 0, 2, 2, 2}, //14 404, 132, 1/3
{35-2, 2-2, 0, 2, 2, 2}, //15 420, 132, 1/3
{36-2, 2-2, 0, 2, 2, 2}, //16 438, 132, 1/3
{37-2, 2-2, 0, 2, 2, 2}, //17 444, 132, 1/3
{38-2, 2-2, 0, 2, 2, 2}, //18 456, 132, 1/3
//{39-2, 2-2, 0, 2, 2, 2}, //468, instant crash!
};
static int _sdram_convert(unsigned int pllin,unsigned int *sdram_dmcr, unsigned int *sdram_div, unsigned int *sdram_tref)
{
register unsigned int ns, dmcr,tmp;
dmcr = ~(EMC_DMCR_TRAS_MASK | EMC_DMCR_RCD_MASK | EMC_DMCR_TPC_MASK |
EMC_DMCR_TRWL_MASK | EMC_DMCR_TRC_MASK) & REG_EMC_DMCR;
/* Set sdram operation parameter */
//pllin unit is KHz
ns = 1000000*1024 / pllin;
tmp = SDRAM_TRAS*1024/ns;
if (tmp < 4) tmp = 4;
if (tmp > 11) tmp = 11;
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
tmp = SDRAM_RCD*1024/ns;
if (tmp > 3) tmp = 3;
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
tmp = SDRAM_TPC*1024/ns;
if (tmp > 7) tmp = 7;
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
tmp = SDRAM_TRWL*1024/ns;
if (tmp > 3) tmp = 3;
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
tmp = (SDRAM_TRAS + SDRAM_TPC)*1024/ns;
if (tmp > 14) tmp = 14;
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
*sdram_dmcr = dmcr;
/* Set refresh registers */
unsigned int div;
tmp = SDRAM_TREF*1024/ns;
div = (tmp + 254)/255;
if(div <= 4) div = 1; // 1/4
else if(div <= 16) div = 2; // 1/16
else div = 3; // 1/64
*sdram_div = ~EMC_RTCSR_CKS_MASK & REG_EMC_RTCSR | div;
unsigned int divm= 4;
while(--div) divm *= 4;
tmp = tmp/divm + 1;
*sdram_tref = tmp;
return 0;
}
const static int FR2n[] = {
1, 2, 3, 4, 6, 8, 12, 16, 24, 32
};
static unsigned int _pllout;
static unsigned int _iclk;
static void detect_clockNew(void){
_pllout = (__cpm_get_pllm() + 2)* EXTAL_CLK / (__cpm_get_plln() + 2);
_iclk = _pllout / FR2n[__cpm_get_cdiv()];
}
//udelay overclock
void ds2_udelay(unsigned int usec)
{
/*unsigned int i = usec * (_iclk / 2000000);
__asm__ __volatile__ (
"\t.set noreorder\n"
"1:\n\t"
"bne\t%0, $0, 1b\n\t"
"addi\t%0, %0, -1\n\t"
".set reorder\n"
: "=r" (i)
: "0" (i)
);*/
}
//mdelay overclock
void ds2_mdelay(unsigned int msec)
{
/*int i;
for(i=0;i<msec;i++)
{
ds2_udelay(1000);
}*/
}
int ds2_getCPUClock(void){
return (_pllout/1000/1000);
}
/* convert pll while program is running */
int ds2_setCPULevel(unsigned int level){
unsigned int freq_b;
unsigned int dmcr;
unsigned int rtcsr;
unsigned int tref;
unsigned int cpccr;
unsigned int cppcr;
if(level > CPU_MAX_LEVEL_EX) return -1;
freq_b = (pll_m_n[level][PLL_M]+2)*(EXTAL_CLK/1000)/(pll_m_n[level][PLL_N]+2);
//freq_b unit is KHz
_sdram_convert(freq_b/pll_m_n[level][PLL_MCLK], &dmcr, &rtcsr, &tref);
cpccr = REG_CPM_CPCCR;
cppcr = REG_CPM_CPPCR;
REG_CPM_CPCCR = ~CPM_CPCCR_CE & cpccr;
cppcr &= ~(CPM_CPPCR_PLLM_MASK | CPM_CPPCR_PLLN_MASK);
cppcr |= (pll_m_n[level][PLL_M] << CPM_CPPCR_PLLM_BIT) | (pll_m_n[level][PLL_N] << CPM_CPPCR_PLLN_BIT);
cpccr &= ~(CPM_CPCCR_CDIV_MASK | CPM_CPCCR_HDIV_MASK | CPM_CPCCR_PDIV_MASK |
CPM_CPCCR_MDIV_MASK | CPM_CPCCR_LDIV_MASK);
cpccr |= (pll_m_n[level][PLL_CCLK] << CPM_CPCCR_CDIV_BIT) | (pll_m_n[level][PLL_HCLK] << CPM_CPCCR_HDIV_BIT) |
(pll_m_n[level][PLL_MCLK] << CPM_CPCCR_MDIV_BIT) | (pll_m_n[level][PLL_PCLK] << CPM_CPCCR_PDIV_BIT) |
(31 << CPM_CPCCR_LDIV_BIT);
REG_CPM_CPCCR = cpccr;
REG_CPM_CPPCR = cppcr;
REG_CPM_CPCCR |= CPM_CPCCR_CE;
//Wait PLL stable
while(!(CPM_CPPCR_PLLS & REG_CPM_CPPCR));
//REG_EMC_DMCR = dmcr;
REG_EMC_RTCOR = tref;
REG_EMC_RTCNT = tref;
detect_clockNew();
return 0;
}

4
sdk-modifications/include/ds2_cpuclock.h → sdk-modifications/libsrc/core/ds2_cpuclock.h
View File

@ -10,8 +10,8 @@ extern "C" {
extern int ds2_getCPUClock(void);
extern int ds2_setCPULevel(unsigned int level);
extern void ds2_udelay(unsigned int usec);
extern void ds2_mdelay(unsigned int msec);
extern void udelayOC(unsigned int usec);
extern void mdelayOC(unsigned int msec);
//#define ds2_setCPUclocklevel ds2_setCPULevel

34
sdk-modifications/libsrc/core/ds2_dma.c Normal file
View File

@ -0,0 +1,34 @@
#include "ds2_dma.h"
//register a DMA transfer request
//ch: channel id request, there are 6 channles,
//irq_handler: the DMA interruption handle
//arg: argument to the handle
//mode: DMA mode, such as port width, address increased/fixed, and so on
//type: DMA request type
extern int dma_request(int ch, void (*irq_handler)(unsigned int), unsigned int arg,
unsigned int mode, unsigned int type);
//start DMA transfer, must request a DMA first
//ch: channel id
//srcAddr: DMA source address
//dstAddr: DMA destination address
//count: DMA transfer count, the total bytes due the mode in dma_request
extern void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count);
int _dmaCopy(int ch, void *dest, void *src, unsigned int size, unsigned int flags){
int test = 0;
if(!(test = dma_request(ch, 0, 0,
//increment dest addr
DMAC_DCMD_DAI | flags,
//auto request type
DMAC_DRSR_RS_AUTO)))
{
dma_start(ch, (unsigned int)src, (unsigned int)dest, size);
}
return test;
}

142
sdk-modifications/libsrc/core/ds2_dma.h Normal file
View File

@ -0,0 +1,142 @@
#ifndef _DS2_DMA_H__
#define _DS2_DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_DMA_NUM 6 /* max 6 channels */
// DMA request source register
#define DMAC_DRSR_RS_BIT 0
#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
// DMA channel command register
#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
#define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
#define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
#define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
//detect if channel has completed job
#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
#define DMAC_BASE 0xB3020000
#define REG32(addr) *((volatile u32 *)(addr))
#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
#define ds2_DMA_isBusy(n) \
!( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
/*
Copy modes
*/
#define DMA_MODE32BYTE DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TM
#define DMA_MODE16BYTE DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
DMAC_DCMD_DS_16BYTE | DMAC_DCMD_TM
#define DMA_MODE32BIT DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
DMAC_DCMD_DS_32BIT
#define DMA_MODE16BIT DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
DMAC_DCMD_DS_16BIT
#define DMA_MODE8BIT DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_8 | \
DMAC_DCMD_DS_8BIT | DMAC_DCMD_TM
#define DMA_MODECOPY DMAC_DCMD_SAI
extern int _dmaCopy(int ch, void *dest, void *src, unsigned int size, unsigned int flags);
/*
* Copy 'size' bytes from src to dest, in blocks of 32 bytes.
* size is in bytes and must be a multiple of 32.
* Both src and dest must be aligned to 32 bytes.
* Returns 0 on failure, non-zero on success.
*/
#define ds2_DMAcopy_32Byte(ch, dest, src, size)\
_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE32BYTE)
/*
* Copy 'size' bytes from src to dest, in blocks of 16 bytes.
* size is in bytes and must be a multiple of 16.
* Both src and dest must be aligned to 16 bytes.
* Returns 0 on failure, non-zero on success.
*/
#define ds2_DMAcopy_16Byte(ch, dest, src, size)\
_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE16BYTE);
/*
* Copy 'size' bytes from src to dest, in blocks of 32 bits (4 bytes).
* size is in bytes and must be a multiple of 4.
* Both src and dest must be aligned to 32 bits (4 bytes).
* Returns 0 on failure, non-zero on success.
*/
#define ds2_DMAcopy_32Bit(ch, dest, src, size)\
_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE32BIT);
/*
- * Copy 'size' bytes from src to dest, in blocks of 16 bits (2 bytes).
- * size is in bytes and must be a multiple of 2.
- * Both src and dest must be aligned to 16 bits (2 bytes).
- * Returns 0 on failure, non-zero on success.
- */
#define ds2_DMAcopy_16Bit(ch, dest, src, size)\
_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE16BIT)
/*
- * Copy 'size' individual bytes (8 bits at a time) from src to dest.
- * Returns 0 on failure, non-zero on success.
- */
#define ds2_DMAcopy_8Bit(ch, dest, src, size)\
_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE8BIT)
//Stop DMA transfer
extern void dma_stop(int ch);
#define ds2_DMA_stop(ch)\
dma_stop(ch)
//Wait DMA transfer over
extern int dma_wait_finish(int ch);
#define ds2_DMA_wait(ch)\
dma_wait_finish(ch)
#ifdef __cplusplus
}
#endif
#endif //__DMA_H__

9
sdk-modifications/libsrc/dma/dma.mk
View File

@ -1,9 +0,0 @@
#dma.mk
SRC += $(DMA_DIR)/dmacopy.c
SSRC +=
INC += -I$(DMA_DIR)
CFLAGS +=

167
sdk-modifications/libsrc/dma/dmacopy.c
View File

@ -1,167 +0,0 @@
#include <stdlib.h>
#include "ds2_dma.h"
#include "ds2_types.h"
#define MAX_DMA_NUM 6 /* max 6 channels */
// DMA request source register
#define DMAC_DRSR_RS_BIT 0
#define DMAC_DRSR_RS_MASK (0x2f << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
#define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) //SD0
#define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
// DMA channel command register
#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
#define DMAC_BASE 0xB3020000
#define REG32(addr) *((volatile u32 *)(addr))
#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
#define __dmac_channel_transmit_end_detected(n) \
( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
/*
* Copy 'size' bytes from src to dest, in blocks of 32 bytes.
* size is in bytes and must be a multiple of 32.
* Both src and dest must be aligned to 32 bytes.
* Returns 0 on failure, non-zero on success.
*/
int dma_copy32Byte(int ch, void *dest, void *src, unsigned int size){
int test = 0;
if(!(test = dma_request(ch, NULL, 0,
//increment dest addr, increment source addr
DMAC_DCMD_DAI | DMAC_DCMD_SAI |
//set src width 32 bytes, set dest width 32 bytes
DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
//set copy mode to 32 bytes, copy in blocks
DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TM,
//auto request type
DMAC_DRSR_RS_AUTO)))
{
dma_start(ch, (unsigned int)src, (unsigned int)dest, size);
}
return test;
}
/*
int sampleUsage(in ch, void *dest, void *src, unsigned int size){
//channel 0 is used for mmc stuff, so its best to avoid using it
//initialize and start copy
if(dma_copy32Byte(ch, dest, src, size)){
dma_wait_finish(ch);//wait for copy to finish
dma_stop(ch);//must stop after transfer is done to reset channel
return 0;
}
return -1;
}
*/
/*
* Copy 'size' bytes from src to dest, in blocks of 16 bytes.
* size is in bytes and must be a multiple of 16.
* Both src and dest must be aligned to 16 bytes.
* Returns 0 on failure, non-zero on success.
*/
int dma_copy16Byte(int ch, void *dest, void *src, unsigned int size){
int test = 0;
if(!(test = dma_request(ch, NULL, 0,
DMAC_DCMD_DAI | DMAC_DCMD_SAI | DMAC_DCMD_SWDH_16 |
DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_TM,
DMAC_DRSR_RS_AUTO)))
{
dma_start(ch, (unsigned int)src, (unsigned int)dest, size);
}
return test;
}
/*
* Copy 'size' bytes from src to dest, in blocks of 32 bits (4 bytes).
* size is in bytes and must be a multiple of 4.
* Both src and dest must be aligned to 32 bits (4 bytes).
* Returns 0 on failure, non-zero on success.
*/
int dma_copy32Bit(int ch, void *dest, void *src, unsigned int size){
int test = 0;
if(!(test = dma_request(ch, NULL, 0,
DMAC_DCMD_DAI | DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
DMAC_DCMD_DS_32BIT | DMAC_DCMD_TM,
DMAC_DRSR_RS_AUTO)))
{
dma_start(ch, (unsigned int)src, (unsigned int)dest, size);
}
return test;
}
/*
* Copy 'size' bytes from src to dest, in blocks of 16 bits (2 bytes).
* size is in bytes and must be a multiple of 2.
* Both src and dest must be aligned to 16 bits (2 bytes).
* Returns 0 on failure, non-zero on success.
*/
int dma_copy16Bit(int ch, void *dest, void *src, unsigned int size){
int test = 0;
if(!(test = dma_request(ch, NULL, 0,
DMAC_DCMD_DAI | DMAC_DCMD_SAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 |
DMAC_DCMD_DS_16BIT,
DMAC_DRSR_RS_AUTO)))
{
dma_start(ch, (unsigned int)src, (unsigned int)dest, size);
}
return test;
}
//returns if a channel is still copying
int dma_isBusy(int ch){
if(ch < 1 || ch >= MAX_DMA_NUM)
return 0;
return !__dmac_channel_transmit_end_detected(ch);
}
//returns the first non busy channel
int dma_getFree(void){
int i;
for(i = 1; i < MAX_DMA_NUM; i++){
if(!dma_isBusy(i))
return i;
}
return -1;
}

54
sdk-modifications/libsrc/dma/ds2_dma.h
View File

@ -1,54 +0,0 @@
#ifndef __DMA_H__
#define __DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
//register a DMA transfer request
//ch: channel id request, there are 6 channles,
//irq_handler: the DMA interruption handle
//arg: argument to the handle
//mode: DMA mode, such as port width, address increased/fixed, and so on
//type: DMA request type
extern int dma_request(int ch, void (*irq_handler)(unsigned int), unsigned int arg,
unsigned int mode, unsigned int type);
//start DMA transfer, must request a DMA first
//ch: channel id
//srcAddr: DMA source address
//dstAddr: DMA destination address
//count: DMA transfer count, the total bytes due the mode in dma_request
extern void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count);
//Stop DMA transfer
extern void dma_stop(int ch);
//Wait DMA transfer over
extern int dma_wait_finish(int ch);
/*
* Copy 'size' bytes from src to dest, in blocks of 32 bytes.
* size is in bytes and must be a multiple of 32.
* Both src and dest must be aligned to 32 bytes.
* Returns 0 on failure, non-zero on success.
*/
extern int dma_copy32Byte(int ch, void *dest, void *src, unsigned int size);
// Blocks of 16 bytes, aligned to 16 bytes
extern int dma_copy16Byte(int ch, void *dest, void *src, unsigned int size);
// Blocks of 4 bytes, aligned to 4 bytes
extern int dma_copy32Bit(int ch, void *dest, void *src, unsigned int size);
// Blocks of 2 bytes, aligned to 2 bytes
extern int dma_copy16Bit(int ch, void *dest, void *src, unsigned int size);
extern int dma_isBusy(int ch);
extern int dma_isFree(int ch);
extern int dma_getFree(void);
#ifdef __cplusplus
}
#endif
#endif //__DMA_H__

0
sdk-modifications/libsrc/fs/bit_ops.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/cache.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/directory.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/directory.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/disc_io/disc.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/disc_io/disc.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/disc_io/disc_io.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/disc_io/io_ds2_mmcf.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/disc_io/io_ds2_mmcf.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/ds2_fcntl.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/ds2_fcntl.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/ds2_unistd.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/ds2_unistd.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fat.h Normal file → Executable file
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52
sdk-modifications/libsrc/fs/fat_misc.c
View File

@ -1,9 +1,9 @@
//fat_misc.c
//v1.0
//fat_misc.c
//v1.0
#include "fat_misc.h"
#include "fs_api.h"
#include "fs_api.h"
static unsigned int _usedSecNums;
static int strFindFromEnd( char *str,char strValue )
@ -40,11 +40,11 @@ static int strFindFromEnd( char *str,char strValue )
int getDirSize( const char * path, int includeSubdirs, unsigned int * dirSize )
{
char dirPath[MAX_FILENAME_LENGTH];
char dirPath[MAX_FILENAME_LENGTH];
unsigned int size = 0;
if( "" == path ){
return false;
}
}
memset( dirPath,0,MAX_FILENAME_LENGTH );
strcpy( dirPath,path );
@ -54,29 +54,31 @@ int getDirSize( const char * path, int includeSubdirs, unsigned int * dirSize )
if( strlen(dirPath) > MAX_FILENAME_LENGTH )
return false;
DIR_STATE_STRUCT *dir; dir = fat_opendir((const char*)dirPath);
DIR_STATE_STRUCT *dir;
dir = fat_opendir((const char*)dirPath);
if (dir == NULL)
return false;
struct stat stat_buf;
DIR_ENTRY *currentEntry;
char* filename;
while(fat_readdir_ex(dir, &stat_buf) != NULL)
return false;
struct stat stat_buf;
DIR_ENTRY *currentEntry;
char* filename;
while((currentEntry = fat_readdir_ex(dir, &stat_buf)) != NULL)
{
filename = currentEntry->d_name;
filename = currentEntry->d_name;
if (strcmp(filename, ".") == 0 || strcmp(filename, "..") == 0)
continue;
if (!(stat_buf.st_mode & S_IFDIR)) {
size += (stat_buf.st_size+511)/512;
_usedSecNums +=(stat_buf.st_size+511)/512;
}
else if (includeSubdirs)
}
else if (includeSubdirs)
{
// calculate the size recursively
unsigned int subDirSize = 0;
char dirPathBuffer[MAX_FILENAME_LENGTH];
unsigned int subDirSize = 0;
char dirPathBuffer[MAX_FILENAME_LENGTH];
memset( dirPathBuffer,0,MAX_FILENAME_LENGTH );
strcpy( dirPathBuffer,dirPath );
@ -90,8 +92,8 @@ int getDirSize( const char * path, int includeSubdirs, unsigned int * dirSize )
memset( dirPath,0,MAX_FILENAME_LENGTH );
strcpy( dirPath,dirPathBuffer );
}
}
}
fat_closedir(dir);
*dirSize = size;
@ -102,7 +104,7 @@ int fat_getDiskTotalSpace( char * diskName, unsigned int * diskSpace )
{
if( !strcmp("",diskName) )
return false;
unsigned int len = strlen(diskName);
if( *(diskName+len-1) != '/' ){
*(diskName+len) = '/';
@ -116,10 +118,10 @@ int fat_getDiskTotalSpace( char * diskName, unsigned int * diskSpace )
return true;
}
int fat_getDiskSpaceInfo( char * diskName, unsigned int * total, unsigned int * used, unsigned int * freeSpace )
int fat_getDiskSpaceInfo( char * diskName, unsigned int * total, unsigned int * used, unsigned int * freeSpace )
{
_usedSecNums = 0;
if( !strcmp("",diskName) )
return -1;
if( !fat_getDiskTotalSpace(diskName, total) )

0
sdk-modifications/libsrc/fs/fat_misc.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatdir.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatdir_ex.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatdir_ex.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatfile.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatfile.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatfile_ex.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fatfile_ex.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/file_allocation_table.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/filetime.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/filetime.h Normal file → Executable file
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2
sdk-modifications/libsrc/fs/fs.mk
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@ -14,7 +14,7 @@ SRC += $(FS_DIR)/cache.c \
$(FS_DIR)/disc_io/disc.c \
$(FS_DIR)/disc_io/io_ds2_mmcf.c \
$(FS_DIR)/ds2_fcntl.c \
$(FS_DIR)/ds2_unistd.c \
$(FS_DIR)/ds2_unistd.c
SSRC +=

0
sdk-modifications/libsrc/fs/fs_api.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fs_api.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fs_cache.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fs_common.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fs_unicode.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/fs_unicode.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/libfat.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/mem_allocate.h Normal file → Executable file
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0
sdk-modifications/libsrc/fs/partition.c Normal file → Executable file
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0
sdk-modifications/libsrc/fs/partition.h Normal file → Executable file
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0
sdk-modifications/libsrc/key/key.c Normal file → Executable file
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0
sdk-modifications/libsrc/key/key.h Normal file → Executable file
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0
sdk-modifications/libsrc/key/key.mk Normal file → Executable file
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9
sdk-modifications/libsrc/zlib/README
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@ -1 +1,8 @@
This is a modified source release of zlib. zconf.h removes a reference to sys/types.h, which creates type conflicts on the DS2 SDK. For a pristine source release of zlib, please visit <http://zlib.net/>.
This is a modified source release of zlib.
Changes:
zconf.h removes a reference to sys/types.h, which creates type conflicts on the DS2 SDK.
gzguts.h removes standard c library includes for DS2 SDK equivalents
For a pristine source release of zlib, please visit <http://zlib.net>.

0
sdk-modifications/libsrc/zlib/adler32.c Normal file → Executable file
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0
sdk-modifications/libsrc/zlib/compress.c Normal file → Executable file
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0
sdk-modifications/libsrc/zlib/crc32.c Normal file → Executable file
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0
sdk-modifications/libsrc/zlib/crc32.h Normal file → Executable file
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0
sdk-modifications/libsrc/zlib/deflate.c Normal file → Executable file
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sdk-modifications/libsrc/zlib/deflate.h Normal file → Executable file
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sdk-modifications/libsrc/zlib/gzclose.c Normal file → Executable file
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sdk-modifications/libsrc/zlib/gzguts.h Normal file → Executable file
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sdk-modifications/libsrc/zlib/gzlib.c Normal file → Executable file
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sdk-modifications/libsrc/zlib/gzread.c Normal file → Executable file
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sdk-modifications/libsrc/zlib/gzwrite.c Normal file → Executable file
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sdk-modifications/libsrc/zlib/infback.c Normal file → Executable file
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