mirror of
https://github.com/libretro/snes9x2005.git
synced 2025-02-26 03:26:33 +00:00
Merge branch 'optimisation'
This commit is contained in:
Nebuleon Fumika
commit
e036c88be6
2
Makefile
2
Makefile
@ -64,7 +64,7 @@ OBJECTS = $(C_OBJECTS) $(CPP_OBJECTS)
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||||
CFLAGS := -mips32 -Os -mno-abicalls -fno-pic -fno-builtin \
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-fno-exceptions -ffunction-sections -mno-long-calls \
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-fomit-frame-pointer -msoft-float -G 4 \
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-fno-inline -fno-early-inlining \
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-fno-early-inlining \
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-fgcse-sm -fgcse-las -fgcse-after-reload \
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-fsched-spec-load -fsched-stalled-insns=0 -fweb
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213
source/cpuaddr.h
213
source/cpuaddr.h
@ -90,8 +90,6 @@
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#ifndef _CPUADDR_H_
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#define _CPUADDR_H_
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EXTERN_C long OpAddress;
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typedef enum {
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NONE = 0,
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READ = 1,
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@ -100,48 +98,74 @@ typedef enum {
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JUMP = 4
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} AccessMode;
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void Immediate8 (AccessMode a)
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EXTERN_C long OpAddress;
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// The type for a function that can run after the addressing mode is resolved:
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// void NAME (long Addr) {...}
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typedef void (*InternalOp) (long);
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/*
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* The addressing modes in this file do not update the OpAddress variable.
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* Rather, they pass the address they calculate to the operation that needs to
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* be done with it. If you need the calculated value, set a passthrough
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* that gets the calculated address from the internal op and then updates the
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* OpAddress variable.
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*
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* Not updating the OpAddress variable saves a few memory storage instructions
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* per SNES instruction.
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* Calling the operation at the end of the addressing mode calculation saves
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* one return instruction per SNES instruction, because the code can just
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* jump from one to the other.
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*/
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static void Immediate8 (AccessMode a, InternalOp op)
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{
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OpAddress = ICPU.ShiftedPB + CPU.PC - CPU.PCBase;
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long Addr = ICPU.ShiftedPB + CPU.PC - CPU.PCBase;
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CPU.PC++;
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(*op)(Addr);
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}
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void Immediate16 (AccessMode a)
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static void Immediate16 (AccessMode a, InternalOp op)
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{
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OpAddress = ICPU.ShiftedPB + CPU.PC - CPU.PCBase;
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long Addr = ICPU.ShiftedPB + CPU.PC - CPU.PCBase;
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CPU.PC += 2;
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(*op)(Addr);
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}
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void Relative (AccessMode a)
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static void Relative (AccessMode a, InternalOp op)
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{
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Int8 = *CPU.PC++;
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeed;
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#endif
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OpAddress = ((int) (CPU.PC - CPU.PCBase) + Int8) & 0xffff;
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long Addr = ((int) (CPU.PC - CPU.PCBase) + Int8) & 0xffff;
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(*op)(Addr);
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}
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void RelativeLong (AccessMode a)
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static void RelativeLong (AccessMode a, InternalOp op)
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{
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long Addr;
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#ifdef FAST_LSB_WORD_ACCESS
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OpAddress = *(uint16 *) CPU.PC;
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Addr = *(uint16 *) CPU.PC;
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#else
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OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8);
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Addr = *CPU.PC + (*(CPU.PC + 1) << 8);
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#endif
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeedx2 + ONE_CYCLE;
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#endif
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CPU.PC += 2;
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OpAddress += (CPU.PC - CPU.PCBase);
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OpAddress &= 0xffff;
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Addr += (CPU.PC - CPU.PCBase);
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Addr &= 0xffff;
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(*op)(Addr);
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}
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void AbsoluteIndexedIndirect (AccessMode a)
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static void AbsoluteIndexedIndirect (AccessMode a, InternalOp op)
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{
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long Addr;
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#ifdef FAST_LSB_WORD_ACCESS
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OpAddress = (Registers.X.W + *(uint16 *) CPU.PC) & 0xffff;
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Addr = (Registers.X.W + *(uint16 *) CPU.PC) & 0xffff;
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#else
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OpAddress = (Registers.X.W + *CPU.PC + (*(CPU.PC + 1) << 8)) & 0xffff;
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Addr = (Registers.X.W + *CPU.PC + (*(CPU.PC + 1) << 8)) & 0xffff;
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#endif
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeedx2;
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@ -150,18 +174,20 @@ void AbsoluteIndexedIndirect (AccessMode a)
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OpenBus = *(CPU.PC + 1);
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#endif
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CPU.PC += 2;
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OpAddress = S9xGetWord (ICPU.ShiftedPB + OpAddress);
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Addr = S9xGetWord (ICPU.ShiftedPB + Addr);
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#ifndef NO_OPEN_BUS
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if(a&READ) OpenBus = (uint8)(OpAddress>>8);
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if(a&READ) OpenBus = (uint8)(Addr>>8);
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#endif
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(*op)(Addr);
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}
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void AbsoluteIndirectLong (AccessMode a)
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static void AbsoluteIndirectLong (AccessMode a, InternalOp op)
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{
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long Addr;
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#ifdef FAST_LSB_WORD_ACCESS
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OpAddress = *(uint16 *) CPU.PC;
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Addr = *(uint16 *) CPU.PC;
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#else
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OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8);
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Addr = *CPU.PC + (*(CPU.PC + 1) << 8);
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#endif
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#ifndef SA1_OPCODES
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@ -173,21 +199,23 @@ void AbsoluteIndirectLong (AccessMode a)
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CPU.PC += 2;
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#ifndef NO_OPEN_BUS
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if(a&READ) {
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OpAddress = S9xGetWord (OpAddress) | ((OpenBus=S9xGetByte (OpAddress + 2)) << 16);
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Addr = S9xGetWord (Addr) | ((OpenBus=S9xGetByte (Addr + 2)) << 16);
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} else {
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#endif
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OpAddress = S9xGetWord (OpAddress) | (S9xGetByte (OpAddress + 2) << 16);
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Addr = S9xGetWord (Addr) | (S9xGetByte (Addr + 2) << 16);
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#ifndef NO_OPEN_BUS
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}
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#endif
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(*op)(Addr);
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}
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void AbsoluteIndirect (AccessMode a)
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static void AbsoluteIndirect (AccessMode a, InternalOp op)
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{
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long Addr;
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#ifdef FAST_LSB_WORD_ACCESS
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OpAddress = *(uint16 *) CPU.PC;
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Addr = *(uint16 *) CPU.PC;
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#else
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OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8);
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Addr = *CPU.PC + (*(CPU.PC + 1) << 8);
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#endif
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#ifndef SA1_OPCODES
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@ -197,19 +225,21 @@ void AbsoluteIndirect (AccessMode a)
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OpenBus = *(CPU.PC + 1);
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#endif
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CPU.PC += 2;
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OpAddress = S9xGetWord (OpAddress);
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Addr = S9xGetWord (Addr);
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#ifndef NO_OPEN_BUS
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if(a&READ) OpenBus = (uint8)(OpAddress>>8);
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if(a&READ) OpenBus = (uint8)(Addr>>8);
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#endif
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OpAddress += ICPU.ShiftedPB;
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Addr += ICPU.ShiftedPB;
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(*op)(Addr);
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}
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void Absolute (AccessMode a)
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static void Absolute (AccessMode a, InternalOp op)
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{
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long Addr;
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#ifdef FAST_LSB_WORD_ACCESS
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OpAddress = *(uint16 *) CPU.PC + ICPU.ShiftedDB;
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Addr = *(uint16 *) CPU.PC + ICPU.ShiftedDB;
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#else
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OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8) + ICPU.ShiftedDB;
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Addr = *CPU.PC + (*(CPU.PC + 1) << 8) + ICPU.ShiftedDB;
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#endif
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#ifndef NO_OPEN_BUS
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if(a&READ) OpenBus = *(CPU.PC+1);
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@ -218,14 +248,16 @@ void Absolute (AccessMode a)
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeedx2;
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#endif
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(*op)(Addr);
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}
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void AbsoluteLong (AccessMode a)
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static void AbsoluteLong (AccessMode a, InternalOp op)
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{
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long Addr;
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#ifdef FAST_LSB_WORD_ACCESS
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OpAddress = (*(uint32 *) CPU.PC) & 0xffffff;
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Addr = (*(uint32 *) CPU.PC) & 0xffffff;
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#else
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OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16);
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Addr = *CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16);
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#endif
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#ifndef NO_OPEN_BUS
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if(a&READ) OpenBus = *(CPU.PC+2);
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@ -234,78 +266,82 @@ void AbsoluteLong (AccessMode a)
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeedx2 + CPU.MemSpeed;
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#endif
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(*op)(Addr);
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}
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void Direct(AccessMode a)
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static void Direct(AccessMode a, InternalOp op)
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{
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#ifndef NO_OPEN_BUS
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if(a&READ) OpenBus = *CPU.PC;
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#endif
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OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff;
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long Addr = (*CPU.PC++ + Registers.D.W) & 0xffff;
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeed;
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#endif
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// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE;
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(*op)(Addr);
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}
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void DirectIndirectIndexed (AccessMode a)
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static void DirectIndirectIndexed (AccessMode a, InternalOp op)
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{
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#ifndef NO_OPEN_BUS
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OpenBus = *CPU.PC;
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#endif
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OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff;
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long Addr = (*CPU.PC++ + Registers.D.W) & 0xffff;
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeed;
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#endif
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OpAddress = S9xGetWord (OpAddress);
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Addr = S9xGetWord (Addr);
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#ifndef NO_OPEN_BUS
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if(a&READ) OpenBus = (uint8)(OpAddress>>8);
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if(a&READ) OpenBus = (uint8)(Addr>>8);
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#endif
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OpAddress += ICPU.ShiftedDB + Registers.Y.W;
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Addr += ICPU.ShiftedDB + Registers.Y.W;
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// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE;
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// XXX: always add one if STA
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// XXX: else Add one cycle if crosses page boundary
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(*op)(Addr);
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}
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void DirectIndirectIndexedLong (AccessMode a)
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static void DirectIndirectIndexedLong (AccessMode a, InternalOp op)
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{
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#ifndef NO_OPEN_BUS
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OpenBus = *CPU.PC;
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#endif
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OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff;
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long Addr = (*CPU.PC++ + Registers.D.W) & 0xffff;
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#ifndef SA1_OPCODES
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CPU.Cycles += CPU.MemSpeed;
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#endif
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#ifndef NO_OPEN_BUS
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if(a&READ){
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OpAddress = S9xGetWord (OpAddress) + ((OpenBus = S9xGetByte (OpAddress + 2)) << 16) + Registers.Y.W;
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Addr = S9xGetWord (Addr) + ((OpenBus = S9xGetByte (Addr + 2)) << 16) + Registers.Y.W;
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} else {
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#endif
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OpAddress = S9xGetWord (OpAddress) + (S9xGetByte (OpAddress + 2) << 16) + Registers.Y.W;
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Addr = S9xGetWord (Addr) + (S9xGetByte (Addr + 2) << 16) + Registers.Y.W;
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#ifndef NO_OPEN_BUS
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}
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#endif
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// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE;
|
||||
(*op)(Addr);
|
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}
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|
||||
void DirectIndexedIndirect(AccessMode a)
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||||
static void DirectIndexedIndirect(AccessMode a, InternalOp op)
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{
|
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#ifndef NO_OPEN_BUS
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OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.D.W + Registers.X.W) & 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.D.W + Registers.X.W) & 0xffff;
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed;
|
||||
#endif
|
||||
|
||||
OpAddress = S9xGetWord (OpAddress);
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||||
Addr = S9xGetWord (Addr);
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#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = (uint8)(OpAddress>>8);
|
||||
if(a&READ) OpenBus = (uint8)(Addr>>8);
|
||||
#endif
|
||||
OpAddress += ICPU.ShiftedDB;
|
||||
Addr += ICPU.ShiftedDB;
|
||||
|
||||
#ifndef SA1_OPCODES
|
||||
// if (Registers.DL != 0)
|
||||
@ -313,15 +349,16 @@ void DirectIndexedIndirect(AccessMode a)
|
||||
// else
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void DirectIndexedX (AccessMode a)
|
||||
static void DirectIndexedX (AccessMode a, InternalOp op)
|
||||
{
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.D.W + Registers.X.W);
|
||||
OpAddress &= CheckEmulation() ? 0xff : 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.D.W + Registers.X.W);
|
||||
Addr &= CheckEmulation() ? 0xff : 0xffff;
|
||||
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed + ONE_CYCLE;
|
||||
@ -330,15 +367,16 @@ void DirectIndexedX (AccessMode a)
|
||||
// else
|
||||
// CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void DirectIndexedY (AccessMode a)
|
||||
static void DirectIndexedY (AccessMode a, InternalOp op)
|
||||
{
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.D.W + Registers.Y.W);
|
||||
OpAddress &= CheckEmulation() ? 0xff : 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.D.W + Registers.Y.W);
|
||||
Addr &= CheckEmulation() ? 0xff : 0xffff;
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed + ONE_CYCLE;
|
||||
// if (Registers.DL != 0)
|
||||
@ -346,14 +384,16 @@ void DirectIndexedY (AccessMode a)
|
||||
// else
|
||||
// CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void AbsoluteIndexedX (AccessMode a)
|
||||
static void AbsoluteIndexedX (AccessMode a, InternalOp op)
|
||||
{
|
||||
long Addr;
|
||||
#ifdef FAST_LSB_WORD_ACCESS
|
||||
OpAddress = ICPU.ShiftedDB + *(uint16 *) CPU.PC + Registers.X.W;
|
||||
Addr = ICPU.ShiftedDB + *(uint16 *) CPU.PC + Registers.X.W;
|
||||
#else
|
||||
OpAddress = ICPU.ShiftedDB + *CPU.PC + (*(CPU.PC + 1) << 8) +
|
||||
Addr = ICPU.ShiftedDB + *CPU.PC + (*(CPU.PC + 1) << 8) +
|
||||
Registers.X.W;
|
||||
#endif
|
||||
#ifndef NO_OPEN_BUS
|
||||
@ -365,14 +405,16 @@ void AbsoluteIndexedX (AccessMode a)
|
||||
#endif
|
||||
// XXX: always add one cycle for ROL, LSR, etc
|
||||
// XXX: else is cross page boundary add one cycle
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void AbsoluteIndexedY (AccessMode a)
|
||||
static void AbsoluteIndexedY (AccessMode a, InternalOp op)
|
||||
{
|
||||
long Addr;
|
||||
#ifdef FAST_LSB_WORD_ACCESS
|
||||
OpAddress = ICPU.ShiftedDB + *(uint16 *) CPU.PC + Registers.Y.W;
|
||||
Addr = ICPU.ShiftedDB + *(uint16 *) CPU.PC + Registers.Y.W;
|
||||
#else
|
||||
OpAddress = ICPU.ShiftedDB + *CPU.PC + (*(CPU.PC + 1) << 8) +
|
||||
Addr = ICPU.ShiftedDB + *CPU.PC + (*(CPU.PC + 1) << 8) +
|
||||
Registers.Y.W;
|
||||
#endif
|
||||
#ifndef NO_OPEN_BUS
|
||||
@ -384,14 +426,16 @@ void AbsoluteIndexedY (AccessMode a)
|
||||
#endif
|
||||
// XXX: always add cycle for STA
|
||||
// XXX: else is cross page boundary add one cycle
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void AbsoluteLongIndexedX (AccessMode a)
|
||||
static void AbsoluteLongIndexedX (AccessMode a, InternalOp op)
|
||||
{
|
||||
long Addr;
|
||||
#ifdef FAST_LSB_WORD_ACCESS
|
||||
OpAddress = (*(uint32 *) CPU.PC + Registers.X.W) & 0xffffff;
|
||||
Addr = (*(uint32 *) CPU.PC + Registers.X.W) & 0xffffff;
|
||||
#else
|
||||
OpAddress = (*CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16) + Registers.X.W) & 0xffffff;
|
||||
Addr = (*CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16) + Registers.X.W) & 0xffffff;
|
||||
#endif
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = *(CPU.PC+2);
|
||||
@ -400,73 +444,78 @@ void AbsoluteLongIndexedX (AccessMode a)
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeedx2 + CPU.MemSpeed;
|
||||
#endif
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void DirectIndirect (AccessMode a)
|
||||
static void DirectIndirect (AccessMode a, InternalOp op)
|
||||
{
|
||||
#ifndef NO_OPEN_BUS
|
||||
OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.D.W) & 0xffff;
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed;
|
||||
#endif
|
||||
OpAddress = S9xGetWord (OpAddress);
|
||||
Addr = S9xGetWord (Addr);
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = (uint8)(OpAddress>>8);
|
||||
if(a&READ) OpenBus = (uint8)(Addr>>8);
|
||||
#endif
|
||||
OpAddress += ICPU.ShiftedDB;
|
||||
Addr += ICPU.ShiftedDB;
|
||||
|
||||
// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE;
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void DirectIndirectLong (AccessMode a)
|
||||
static void DirectIndirectLong (AccessMode a, InternalOp op)
|
||||
{
|
||||
#ifndef NO_OPEN_BUS
|
||||
OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.D.W) & 0xffff;
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed;
|
||||
#endif
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ){
|
||||
OpAddress = S9xGetWord (OpAddress) + ((OpenBus=S9xGetByte (OpAddress + 2)) << 16);
|
||||
Addr = S9xGetWord (Addr) + ((OpenBus=S9xGetByte (Addr + 2)) << 16);
|
||||
} else {
|
||||
#endif
|
||||
OpAddress = S9xGetWord (OpAddress) + (S9xGetByte (OpAddress + 2) << 16);
|
||||
Addr = S9xGetWord (Addr) + (S9xGetByte (Addr + 2) << 16);
|
||||
#ifndef NO_OPEN_BUS
|
||||
}
|
||||
#endif
|
||||
// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE;
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void StackRelative (AccessMode a)
|
||||
static void StackRelative (AccessMode a, InternalOp op)
|
||||
{
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.S.W) & 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.S.W) & 0xffff;
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed + ONE_CYCLE;
|
||||
#endif
|
||||
(*op)(Addr);
|
||||
}
|
||||
|
||||
void StackRelativeIndirectIndexed (AccessMode a)
|
||||
static void StackRelativeIndirectIndexed (AccessMode a, InternalOp op)
|
||||
{
|
||||
#ifndef NO_OPEN_BUS
|
||||
OpenBus = *CPU.PC;
|
||||
#endif
|
||||
OpAddress = (*CPU.PC++ + Registers.S.W) & 0xffff;
|
||||
long Addr = (*CPU.PC++ + Registers.S.W) & 0xffff;
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += CPU.MemSpeed + TWO_CYCLES;
|
||||
#endif
|
||||
OpAddress = S9xGetWord (OpAddress);
|
||||
Addr = S9xGetWord (Addr);
|
||||
#ifndef NO_OPEN_BUS
|
||||
if(a&READ) OpenBus = (uint8)(OpAddress>>8);
|
||||
if(a&READ) OpenBus = (uint8)(Addr>>8);
|
||||
#endif
|
||||
OpAddress = (OpAddress + ICPU.ShiftedDB +
|
||||
Addr = (Addr + ICPU.ShiftedDB +
|
||||
Registers.Y.W) & 0xffffff;
|
||||
(*op)(Addr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -90,21 +90,21 @@
|
||||
#ifndef _CPUMACRO_H_
|
||||
#define _CPUMACRO_H_
|
||||
|
||||
void SetZN16 (uint16 Work)
|
||||
static void SetZN16 (uint16 Work)
|
||||
{
|
||||
ICPU._Zero = Work != 0;
|
||||
ICPU._Negative = (uint8) (Work >> 8);
|
||||
}
|
||||
|
||||
void SetZN8 (uint8 Work)
|
||||
static void SetZN8 (uint8 Work)
|
||||
{
|
||||
ICPU._Zero = Work;
|
||||
ICPU._Negative = Work;
|
||||
}
|
||||
|
||||
void ADC8 ()
|
||||
static void ADC8 (long Addr)
|
||||
{
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
|
||||
if (CheckDecimal ())
|
||||
{
|
||||
@ -159,9 +159,9 @@ void ADC8 ()
|
||||
}
|
||||
}
|
||||
|
||||
void ADC16 ()
|
||||
static void ADC16 (long Addr)
|
||||
{
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
|
||||
if (CheckDecimal ())
|
||||
{
|
||||
@ -235,19 +235,19 @@ void ADC16 ()
|
||||
}
|
||||
}
|
||||
|
||||
void AND16 ()
|
||||
static void AND16 (long Addr)
|
||||
{
|
||||
Registers.A.W &= S9xGetWord (OpAddress);
|
||||
Registers.A.W &= S9xGetWord (Addr);
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void AND8 ()
|
||||
static void AND8 (long Addr)
|
||||
{
|
||||
Registers.AL &= S9xGetByte (OpAddress);
|
||||
Registers.AL &= S9xGetByte (Addr);
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void A_ASL16 ()
|
||||
static inline void A_ASL16 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -257,7 +257,7 @@ void A_ASL16 ()
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void A_ASL8 ()
|
||||
static inline void A_ASL8 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -267,97 +267,97 @@ void A_ASL8 ()
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void ASL16 ()
|
||||
static void ASL16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
ICPU._Carry = (Work16 & 0x8000) != 0;
|
||||
Work16 <<= 1;
|
||||
//S9xSetWord (Work16, OpAddress);
|
||||
S9xSetByte(Work16>>8, OpAddress+1);
|
||||
S9xSetByte(Work16&0xFF, OpAddress);
|
||||
//S9xSetWord (Work16, Addr);
|
||||
S9xSetByte(Work16>>8, Addr+1);
|
||||
S9xSetByte(Work16&0xFF, Addr);
|
||||
SetZN16 (Work16);
|
||||
}
|
||||
|
||||
void ASL8 ()
|
||||
static void ASL8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
ICPU._Carry = (Work8 & 0x80) != 0;
|
||||
Work8 <<= 1;
|
||||
S9xSetByte (Work8, OpAddress);
|
||||
S9xSetByte (Work8, Addr);
|
||||
SetZN8 (Work8);
|
||||
}
|
||||
|
||||
void BIT16 ()
|
||||
static void BIT16 (long Addr)
|
||||
{
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
ICPU._Overflow = (Work16 & 0x4000) != 0;
|
||||
ICPU._Negative = (uint8) (Work16 >> 8);
|
||||
ICPU._Zero = (Work16 & Registers.A.W) != 0;
|
||||
}
|
||||
|
||||
void BIT8 ()
|
||||
static void BIT8 (long Addr)
|
||||
{
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
ICPU._Overflow = (Work8 & 0x40) != 0;
|
||||
ICPU._Negative = Work8;
|
||||
ICPU._Zero = Work8 & Registers.AL;
|
||||
}
|
||||
|
||||
void CMP16 ()
|
||||
static void CMP16 (long Addr)
|
||||
{
|
||||
Int32 = (long) Registers.A.W -
|
||||
(long) S9xGetWord (OpAddress);
|
||||
(long) S9xGetWord (Addr);
|
||||
ICPU._Carry = Int32 >= 0;
|
||||
SetZN16 ((uint16) Int32);
|
||||
}
|
||||
|
||||
void CMP8 ()
|
||||
static void CMP8 (long Addr)
|
||||
{
|
||||
Int16 = (short) Registers.AL -
|
||||
(short) S9xGetByte (OpAddress);
|
||||
(short) S9xGetByte (Addr);
|
||||
ICPU._Carry = Int16 >= 0;
|
||||
SetZN8 ((uint8) Int16);
|
||||
}
|
||||
|
||||
void CMX16 ()
|
||||
static void CMX16 (long Addr)
|
||||
{
|
||||
Int32 = (long) Registers.X.W -
|
||||
(long) S9xGetWord (OpAddress);
|
||||
(long) S9xGetWord (Addr);
|
||||
ICPU._Carry = Int32 >= 0;
|
||||
SetZN16 ((uint16) Int32);
|
||||
}
|
||||
|
||||
void CMX8 ()
|
||||
static void CMX8 (long Addr)
|
||||
{
|
||||
Int16 = (short) Registers.XL -
|
||||
(short) S9xGetByte (OpAddress);
|
||||
(short) S9xGetByte (Addr);
|
||||
ICPU._Carry = Int16 >= 0;
|
||||
SetZN8 ((uint8) Int16);
|
||||
}
|
||||
|
||||
void CMY16 ()
|
||||
static void CMY16 (long Addr)
|
||||
{
|
||||
Int32 = (long) Registers.Y.W -
|
||||
(long) S9xGetWord (OpAddress);
|
||||
(long) S9xGetWord (Addr);
|
||||
ICPU._Carry = Int32 >= 0;
|
||||
SetZN16 ((uint16) Int32);
|
||||
}
|
||||
|
||||
void CMY8 ()
|
||||
static void CMY8 (long Addr)
|
||||
{
|
||||
Int16 = (short) Registers.YL -
|
||||
(short) S9xGetByte (OpAddress);
|
||||
(short) S9xGetByte (Addr);
|
||||
ICPU._Carry = Int16 >= 0;
|
||||
SetZN8 ((uint8) Int16);
|
||||
}
|
||||
|
||||
void A_DEC16 ()
|
||||
static inline void A_DEC16 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -370,7 +370,7 @@ void A_DEC16 ()
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void A_DEC8 ()
|
||||
static inline void A_DEC8 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -383,7 +383,7 @@ void A_DEC8 ()
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void DEC16 ()
|
||||
static void DEC16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -392,14 +392,14 @@ void DEC16 ()
|
||||
CPU.WaitAddress = NULL;
|
||||
#endif
|
||||
|
||||
Work16 = S9xGetWord (OpAddress) - 1;
|
||||
//S9xSetWord (Work16, OpAddress);
|
||||
S9xSetByte (Work16>>8, OpAddress+1);
|
||||
S9xSetByte (Work16&0xFF, OpAddress);
|
||||
Work16 = S9xGetWord (Addr) - 1;
|
||||
//S9xSetWord (Work16, Addr);
|
||||
S9xSetByte (Work16>>8, Addr+1);
|
||||
S9xSetByte (Work16&0xFF, Addr);
|
||||
SetZN16 (Work16);
|
||||
}
|
||||
|
||||
void DEC8 ()
|
||||
static void DEC8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -408,24 +408,24 @@ void DEC8 ()
|
||||
CPU.WaitAddress = NULL;
|
||||
#endif
|
||||
|
||||
Work8 = S9xGetByte (OpAddress) - 1;
|
||||
S9xSetByte (Work8, OpAddress);
|
||||
Work8 = S9xGetByte (Addr) - 1;
|
||||
S9xSetByte (Work8, Addr);
|
||||
SetZN8 (Work8);
|
||||
}
|
||||
|
||||
void EOR16 ()
|
||||
static void EOR16 (long Addr)
|
||||
{
|
||||
Registers.A.W ^= S9xGetWord (OpAddress);
|
||||
Registers.A.W ^= S9xGetWord (Addr);
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void EOR8 ()
|
||||
static void EOR8 (long Addr)
|
||||
{
|
||||
Registers.AL ^= S9xGetByte (OpAddress);
|
||||
Registers.AL ^= S9xGetByte (Addr);
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void A_INC16 ()
|
||||
static inline void A_INC16 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -438,7 +438,7 @@ void A_INC16 ()
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void A_INC8 ()
|
||||
static inline void A_INC8 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -451,7 +451,7 @@ void A_INC8 ()
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void INC16 ()
|
||||
static void INC16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -460,14 +460,14 @@ void INC16 ()
|
||||
CPU.WaitAddress = NULL;
|
||||
#endif
|
||||
|
||||
Work16 = S9xGetWord (OpAddress) + 1;
|
||||
//S9xSetWord (Work16, OpAddress);
|
||||
S9xSetByte (Work16>>8, OpAddress+1);
|
||||
S9xSetByte (Work16&0xFF, OpAddress);
|
||||
Work16 = S9xGetWord (Addr) + 1;
|
||||
//S9xSetWord (Work16, Addr);
|
||||
S9xSetByte (Work16>>8, Addr+1);
|
||||
S9xSetByte (Work16&0xFF, Addr);
|
||||
SetZN16 (Work16);
|
||||
}
|
||||
|
||||
void INC8 ()
|
||||
static void INC8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -476,48 +476,48 @@ void INC8 ()
|
||||
CPU.WaitAddress = NULL;
|
||||
#endif
|
||||
|
||||
Work8 = S9xGetByte (OpAddress) + 1;
|
||||
S9xSetByte (Work8, OpAddress);
|
||||
Work8 = S9xGetByte (Addr) + 1;
|
||||
S9xSetByte (Work8, Addr);
|
||||
SetZN8 (Work8);
|
||||
}
|
||||
|
||||
void LDA16 ()
|
||||
static void LDA16 (long Addr)
|
||||
{
|
||||
Registers.A.W = S9xGetWord (OpAddress);
|
||||
Registers.A.W = S9xGetWord (Addr);
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void LDA8 ()
|
||||
static void LDA8 (long Addr)
|
||||
{
|
||||
Registers.AL = S9xGetByte (OpAddress);
|
||||
Registers.AL = S9xGetByte (Addr);
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void LDX16 ()
|
||||
static void LDX16 (long Addr)
|
||||
{
|
||||
Registers.X.W = S9xGetWord (OpAddress);
|
||||
Registers.X.W = S9xGetWord (Addr);
|
||||
SetZN16 (Registers.X.W);
|
||||
}
|
||||
|
||||
void LDX8 ()
|
||||
static void LDX8 (long Addr)
|
||||
{
|
||||
Registers.XL = S9xGetByte (OpAddress);
|
||||
Registers.XL = S9xGetByte (Addr);
|
||||
SetZN8 (Registers.XL);
|
||||
}
|
||||
|
||||
void LDY16 ()
|
||||
static void LDY16 (long Addr)
|
||||
{
|
||||
Registers.Y.W = S9xGetWord (OpAddress);
|
||||
Registers.Y.W = S9xGetWord (Addr);
|
||||
SetZN16 (Registers.Y.W);
|
||||
}
|
||||
|
||||
void LDY8 ()
|
||||
static void LDY8 (long Addr)
|
||||
{
|
||||
Registers.YL = S9xGetByte (OpAddress);
|
||||
Registers.YL = S9xGetByte (Addr);
|
||||
SetZN8 (Registers.YL);
|
||||
}
|
||||
|
||||
void A_LSR16 ()
|
||||
static inline void A_LSR16 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -527,7 +527,7 @@ void A_LSR16 ()
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void A_LSR8 ()
|
||||
static inline void A_LSR8 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -537,45 +537,45 @@ void A_LSR8 ()
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void LSR16 ()
|
||||
static void LSR16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
ICPU._Carry = Work16 & 1;
|
||||
Work16 >>= 1;
|
||||
//S9xSetWord (Work16, OpAddress);
|
||||
S9xSetByte (Work16>>8, OpAddress+1);
|
||||
S9xSetByte (Work16&0xFF, OpAddress);
|
||||
//S9xSetWord (Work16, Addr);
|
||||
S9xSetByte (Work16>>8, Addr+1);
|
||||
S9xSetByte (Work16&0xFF, Addr);
|
||||
SetZN16 (Work16);
|
||||
}
|
||||
|
||||
void LSR8 ()
|
||||
static void LSR8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
ICPU._Carry = Work8 & 1;
|
||||
Work8 >>= 1;
|
||||
S9xSetByte (Work8, OpAddress);
|
||||
S9xSetByte (Work8, Addr);
|
||||
SetZN8 (Work8);
|
||||
}
|
||||
|
||||
void ORA16 ()
|
||||
static void ORA16 (long Addr)
|
||||
{
|
||||
Registers.A.W |= S9xGetWord (OpAddress);
|
||||
Registers.A.W |= S9xGetWord (Addr);
|
||||
SetZN16 (Registers.A.W);
|
||||
}
|
||||
|
||||
void ORA8 ()
|
||||
static void ORA8 (long Addr)
|
||||
{
|
||||
Registers.AL |= S9xGetByte (OpAddress);
|
||||
Registers.AL |= S9xGetByte (Addr);
|
||||
SetZN8 (Registers.AL);
|
||||
}
|
||||
|
||||
void A_ROL16 ()
|
||||
static inline void A_ROL16 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -586,7 +586,7 @@ void A_ROL16 ()
|
||||
SetZN16 ((uint16) Work32);
|
||||
}
|
||||
|
||||
void A_ROL8 ()
|
||||
static inline void A_ROL8 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -599,35 +599,35 @@ void A_ROL8 ()
|
||||
SetZN8 ((uint8) Work16);
|
||||
}
|
||||
|
||||
void ROL16 ()
|
||||
static void ROL16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work32 = S9xGetWord (OpAddress);
|
||||
Work32 = S9xGetWord (Addr);
|
||||
Work32 <<= 1;
|
||||
Work32 |= CheckCarry();
|
||||
ICPU._Carry = Work32 >= 0x10000;
|
||||
//S9xSetWord ((uint16) Work32, OpAddress);
|
||||
S9xSetByte((Work32>>8)&0xFF, OpAddress+1);
|
||||
S9xSetByte(Work32&0xFF, OpAddress);
|
||||
//S9xSetWord ((uint16) Work32, Addr);
|
||||
S9xSetByte((Work32>>8)&0xFF, Addr+1);
|
||||
S9xSetByte(Work32&0xFF, Addr);
|
||||
SetZN16 ((uint16) Work32);
|
||||
}
|
||||
|
||||
void ROL8 ()
|
||||
static void ROL8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work16 = S9xGetByte (OpAddress);
|
||||
Work16 = S9xGetByte (Addr);
|
||||
Work16 <<= 1;
|
||||
Work16 |= CheckCarry ();
|
||||
ICPU._Carry = Work16 >= 0x100;
|
||||
S9xSetByte ((uint8) Work16, OpAddress);
|
||||
S9xSetByte ((uint8) Work16, Addr);
|
||||
SetZN8 ((uint8) Work16);
|
||||
}
|
||||
|
||||
void A_ROR16 ()
|
||||
static inline void A_ROR16 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -640,7 +640,7 @@ void A_ROR16 ()
|
||||
SetZN16 ((uint16) Work32);
|
||||
}
|
||||
|
||||
void A_ROR8 ()
|
||||
static inline void A_ROR8 ()
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
@ -652,37 +652,37 @@ void A_ROR8 ()
|
||||
SetZN8 ((uint8) Work16);
|
||||
}
|
||||
|
||||
void ROR16 ()
|
||||
static void ROR16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work32 = S9xGetWord (OpAddress);
|
||||
Work32 = S9xGetWord (Addr);
|
||||
Work32 |= (int) CheckCarry() << 16;
|
||||
ICPU._Carry = (uint8) (Work32 & 1);
|
||||
Work32 >>= 1;
|
||||
//S9xSetWord ((uint16) Work32, OpAddress);
|
||||
S9xSetByte ( (Work32>>8)&0x00FF, OpAddress+1);
|
||||
S9xSetByte (Work32&0x00FF, OpAddress);
|
||||
//S9xSetWord ((uint16) Work32, Addr);
|
||||
S9xSetByte ( (Work32>>8)&0x00FF, Addr+1);
|
||||
S9xSetByte (Work32&0x00FF, Addr);
|
||||
SetZN16 ((uint16) Work32);
|
||||
}
|
||||
|
||||
void ROR8 ()
|
||||
static void ROR8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work16 = S9xGetByte (OpAddress);
|
||||
Work16 = S9xGetByte (Addr);
|
||||
Work16 |= (int) CheckCarry () << 8;
|
||||
ICPU._Carry = (uint8) (Work16 & 1);
|
||||
Work16 >>= 1;
|
||||
S9xSetByte ((uint8) Work16, OpAddress);
|
||||
S9xSetByte ((uint8) Work16, Addr);
|
||||
SetZN8 ((uint8) Work16);
|
||||
}
|
||||
|
||||
void SBC16 ()
|
||||
static void SBC16 (long Addr)
|
||||
{
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
|
||||
if (CheckDecimal ())
|
||||
{
|
||||
@ -750,9 +750,9 @@ void SBC16 ()
|
||||
}
|
||||
}
|
||||
|
||||
void SBC8 ()
|
||||
static void SBC8 (long Addr)
|
||||
{
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
if (CheckDecimal ())
|
||||
{
|
||||
A1 = (Registers.A.W) & 0xF;
|
||||
@ -801,92 +801,92 @@ void SBC8 ()
|
||||
}
|
||||
}
|
||||
|
||||
void STA16 ()
|
||||
static void STA16 (long Addr)
|
||||
{
|
||||
S9xSetWord (Registers.A.W, OpAddress);
|
||||
S9xSetWord (Registers.A.W, Addr);
|
||||
}
|
||||
|
||||
void STA8 ()
|
||||
static void STA8 (long Addr)
|
||||
{
|
||||
S9xSetByte (Registers.AL, OpAddress);
|
||||
S9xSetByte (Registers.AL, Addr);
|
||||
}
|
||||
|
||||
void STX16 ()
|
||||
static void STX16 (long Addr)
|
||||
{
|
||||
S9xSetWord (Registers.X.W, OpAddress);
|
||||
S9xSetWord (Registers.X.W, Addr);
|
||||
}
|
||||
|
||||
void STX8 ()
|
||||
static void STX8 (long Addr)
|
||||
{
|
||||
S9xSetByte (Registers.XL, OpAddress);
|
||||
S9xSetByte (Registers.XL, Addr);
|
||||
}
|
||||
|
||||
void STY16 ()
|
||||
static void STY16 (long Addr)
|
||||
{
|
||||
S9xSetWord (Registers.Y.W, OpAddress);
|
||||
S9xSetWord (Registers.Y.W, Addr);
|
||||
}
|
||||
|
||||
void STY8 ()
|
||||
static void STY8 (long Addr)
|
||||
{
|
||||
S9xSetByte (Registers.YL, OpAddress);
|
||||
S9xSetByte (Registers.YL, Addr);
|
||||
}
|
||||
|
||||
void STZ16 ()
|
||||
static void STZ16 (long Addr)
|
||||
{
|
||||
S9xSetWord (0, OpAddress);
|
||||
S9xSetWord (0, Addr);
|
||||
}
|
||||
|
||||
void STZ8 ()
|
||||
static void STZ8 (long Addr)
|
||||
{
|
||||
S9xSetByte (0, OpAddress);
|
||||
S9xSetByte (0, Addr);
|
||||
}
|
||||
|
||||
void TSB16 ()
|
||||
static void TSB16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
ICPU._Zero = (Work16 & Registers.A.W) != 0;
|
||||
Work16 |= Registers.A.W;
|
||||
//S9xSetWord (Work16, OpAddress);
|
||||
S9xSetByte (Work16>>8, OpAddress+1);
|
||||
S9xSetByte (Work16&0xFF, OpAddress);
|
||||
//S9xSetWord (Work16, Addr);
|
||||
S9xSetByte (Work16>>8, Addr+1);
|
||||
S9xSetByte (Work16&0xFF, Addr);
|
||||
}
|
||||
|
||||
void TSB8 ()
|
||||
static void TSB8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
ICPU._Zero = Work8 & Registers.AL;
|
||||
Work8 |= Registers.AL;
|
||||
S9xSetByte (Work8, OpAddress);
|
||||
S9xSetByte (Work8, Addr);
|
||||
}
|
||||
|
||||
void TRB16 ()
|
||||
static void TRB16 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work16 = S9xGetWord (OpAddress);
|
||||
Work16 = S9xGetWord (Addr);
|
||||
ICPU._Zero = (Work16 & Registers.A.W) != 0;
|
||||
Work16 &= ~Registers.A.W;
|
||||
//S9xSetWord (Work16, OpAddress);
|
||||
S9xSetByte (Work16>>8, OpAddress+1);
|
||||
S9xSetByte (Work16&0xFF, OpAddress);
|
||||
//S9xSetWord (Work16, Addr);
|
||||
S9xSetByte (Work16>>8, Addr+1);
|
||||
S9xSetByte (Work16&0xFF, Addr);
|
||||
}
|
||||
|
||||
void TRB8 ()
|
||||
static void TRB8 (long Addr)
|
||||
{
|
||||
#ifndef SA1_OPCODES
|
||||
CPU.Cycles += ONE_CYCLE;
|
||||
#endif
|
||||
Work8 = S9xGetByte (OpAddress);
|
||||
Work8 = S9xGetByte (Addr);
|
||||
ICPU._Zero = Work8 & Registers.AL;
|
||||
Work8 &= ~Registers.AL;
|
||||
S9xSetByte (Work8, OpAddress);
|
||||
S9xSetByte (Work8, Addr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
1073
source/cpuops.cpp
1073
source/cpuops.cpp
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user