mirror of
https://github.com/libretro/virtualjaguar-libretro.git
synced 2026-11-07 04:36:00 -10:00
Joseph MattielloandClaude Fable 5
7db5de7f20
Pre-tag scrutiny pass, code half (brief items 1-7, 13): - cdrom.c: [SUBCODE] read/write/BUTCH-enable diagnostics LOG_INF -> LOG_DBG, matching the #274 CDDA demotion class (3 sites; the brief named 2, the BUTCH int-enable site is the same class). - cdrom.c: the CDDA-DIAG comment claimed "log unconditionally" while the code rate-limits to the first 40 plus every 500th; fix the comment to describe what the code does. - bus_arbiter: bus_arbiter_dram_cost() has no callers outside bus_arbiter.c and is not in any export list -- make it static and drop the header declaration. - analyze_cd_roms.py: drop the hardcoded absolute ROM path in favour of argv[1] / JAGUAR_ROMS_PRIVATE / test/roms/private, and normalize the Unicode box-drawing comment banners to plain ASCII. - Replace unresolvable citations (/private/tmp/..., .superpowers/...) and bare "Task N" agent-process references in source comments with in-repo doc citations or the symptom being tested. - Normalize em-dashes to "--" in every user-facing / log string added this cycle (core option descriptions, CD + boot log strings, test diagnostics), matching the files' pre-existing convention. No behaviour change. Build clean, c89-lint clean, test_dram_timing passes (0 failures). Co-Authored-By: Claude Fable 5 <[email protected]>
403 lines
15 KiB
C
403 lines
15 KiB
C
/*
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* mister_ground_truth.h -- Expected hardware values extracted from MiSTer FPGA RTL.
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*
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* Source: MiSTer-devel/Jaguar_MiSTer repository, rtl/
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* These constants define the correct behavior according to real hardware
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* as implemented in the MiSTer Jaguar FPGA core.
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*/
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#ifndef MISTER_GROUND_TRUTH_H
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#define MISTER_GROUND_TRUTH_H
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#include <stdint.h>
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/* ================================================================== */
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/* GPU Control Register ($F02114) — from gpu_ctrl.v */
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/* ================================================================== */
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/* Write bits (ctrlwr): */
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#define GPU_CTRL_GO (1 << 0) /* Start GPU execution */
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#define GPU_CTRL_CPUINT (1 << 1) /* Trigger 68K interrupt */
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#define GPU_CTRL_GPUIRQ0 (1 << 2) /* Trigger GPU IRQ 0 (CPU->GPU) */
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#define GPU_CTRL_SINGLE_STEP (1 << 3) /* Single-step mode */
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#define GPU_CTRL_SINGLE_GO (1 << 4) /* Single-step go (one instruction) */
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#define GPU_CTRL_BUS_HOG (1 << 11) /* Bus hog mode */
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/* Read bits (statrd): */
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/* bit 0: go (GPU running) */
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/* bit 3: single_stop (stopped in single-step) */
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/* bit 11: bus_hog */
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/* bit 13: always 1 (TOM version bit — gpu_ctrl.v line 136) */
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/* bits 1-2, 4-10, 12, 14-15: always 0 */
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#define GPU_CTRL_STAT_GO (1 << 0)
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#define GPU_CTRL_STAT_SINGLESTOP (1 << 3)
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#define GPU_CTRL_STAT_BUSHOG (1 << 11)
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#define GPU_CTRL_STAT_VERSION (1 << 13) /* TOM always has this set */
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/* Expected read-back after reset (only version bit set): */
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#define GPU_CTRL_RESET_VALUE 0x00000000 /* go=0, no version bit in VJ impl */
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/* ================================================================== */
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/* GPU Flags Register ($F02100) — from interrupt.v */
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/* ================================================================== */
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/* Flag bits (low nibble): */
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#define GPU_FLAGS_ZERO (1 << 0)
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#define GPU_FLAGS_CARRY (1 << 1)
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#define GPU_FLAGS_NEGA (1 << 2)
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#define GPU_FLAGS_IMASK (1 << 3) /* Set by ISR entry only, NOT writable */
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/* INT_ENA bits (write to enable interrupts): */
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#define GPU_FLAGS_INT_ENA0 (1 << 4) /* CPU->GPU */
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#define GPU_FLAGS_INT_ENA1 (1 << 5) /* DSP */
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#define GPU_FLAGS_INT_ENA2 (1 << 6) /* PIT (timer) */
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#define GPU_FLAGS_INT_ENA3 (1 << 7) /* Object Processor */
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#define GPU_FLAGS_INT_ENA4 (1 << 8) /* Blitter */
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/* INT_CLR bits (write to clear latched interrupts): */
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#define GPU_FLAGS_INT_CLR0 (1 << 9)
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#define GPU_FLAGS_INT_CLR1 (1 << 10)
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#define GPU_FLAGS_INT_CLR2 (1 << 11)
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#define GPU_FLAGS_INT_CLR3 (1 << 12)
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#define GPU_FLAGS_INT_CLR4 (1 << 13)
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/* On READ, bits 6-10 (in MiSTer) / 9-13 (our mapping) return ilatch state.
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* interrupt.v line 130: gpu_dout_out[10:6] on statrd = ilatch[4:0] */
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/* ================================================================== */
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/* GPU Interrupt Priority — from interrupt.v lines 139-161 */
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/* ================================================================== */
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/* Priority: higher number = higher priority.
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* GPU has 5 IRQ sources (0-4):
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* IRQ 0: CPU->GPU (lowest)
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* IRQ 1: DSP
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* IRQ 2: Timer/PIT
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* IRQ 3: Object Processor
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* IRQ 4: Blitter (highest)
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*
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* DSP has 6 IRQ sources (0-5):
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* IRQ 0: CPU->DSP (lowest)
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* IRQ 1: SSI receive
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* IRQ 2: Timer 0
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* IRQ 3: Timer 1
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* IRQ 4: External 0
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* IRQ 5: External 1 (highest, Jerry only)
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*/
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/* ISR vector addresses: base + (irq_number * 16) */
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#define GPU_ISR_BASE 0xF03000
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#define DSP_ISR_BASE 0xF1B000
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#define GPU_ISR_VECTOR(n) (GPU_ISR_BASE + ((n) * 16))
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#define DSP_ISR_VECTOR(n) (DSP_ISR_BASE + ((n) * 16))
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/* ISR entry microcode sequence (interrupt.v lines 259-268):
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* 0: SUBQT #4, R31 (0x1C9F)
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* 1: MOVE PC, R30 (0xCC1E) -- actually MOVPC to R30
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* 2: STORE R30, (R31) (0xBFFE)
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* 3: MOVEI <low>, R30 (MOVEI opcode)
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* 4: <ISR addr low word>
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* 5: <ISR addr high word>
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* 6: JUMP (R30) (0xD3C0)
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* 7: NOP (0xE400)
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*/
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/* ================================================================== */
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/* BUTCH CD Controller ($DFFF00) — from butch.v */
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/* ================================================================== */
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/* Register indices (butch_reg[0..11], each 32-bit at offset*4): */
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#define BUTCH_BASE 0xDFFF00
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#define BUTCH_INT_CTRL (BUTCH_BASE + 0x00) /* butch_reg[0] */
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#define BUTCH_DSCNTRL (BUTCH_BASE + 0x04) /* butch_reg[1] */
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#define BUTCH_DS_DATA (BUTCH_BASE + 0x0A) /* 16-bit access within reg[2] */
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#define BUTCH_I2CNTRL (BUTCH_BASE + 0x10) /* butch_reg[4] */
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#define BUTCH_SBCNTRL (BUTCH_BASE + 0x14) /* butch_reg[5] */
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#define BUTCH_SUBDATA_A (BUTCH_BASE + 0x18) /* butch_reg[6] */
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#define BUTCH_SUBDATA_B (BUTCH_BASE + 0x1C) /* butch_reg[7] */
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#define BUTCH_SB_TIME (BUTCH_BASE + 0x20) /* butch_reg[8] */
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#define BUTCH_I2SDAT1 (BUTCH_BASE + 0x24) /* butch_reg[9] - FIFO */
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#define BUTCH_I2SDAT2 (BUTCH_BASE + 0x28) /* butch_reg[10] - FIFO */
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#define BUTCH_EEPROM (BUTCH_BASE + 0x2C) /* butch_reg[11] */
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/* BUTCH interrupt control bits (butch_reg[0]):
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* butch.v lines 83-95 */
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#define BUTCH_INT_ENABLE (1 << 0) /* Master interrupt enable */
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#define BUTCH_INT_FIFO_EN (1 << 1) /* FIFO half-full int enable */
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#define BUTCH_INT_FRAME_EN (1 << 2) /* Frame int enable */
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#define BUTCH_INT_SUB_EN (1 << 3) /* Subcode int enable */
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#define BUTCH_INT_TBUF_EN (1 << 4) /* TX buffer empty int enable */
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#define BUTCH_INT_RBUF_EN (1 << 5) /* RX buffer full int enable */
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#define BUTCH_INT_CRCERR (1 << 6) /* CRC error flag */
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/* bits 7-8: reserved */
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#define BUTCH_INT_FIFO_ST (1 << 9) /* FIFO half-full status */
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#define BUTCH_INT_FRAME_ST (1 << 10) /* Frame status */
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#define BUTCH_INT_SUB_ST (1 << 11) /* Subcode status */
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#define BUTCH_INT_TBUF_ST (1 << 12) /* TX buffer status */
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#define BUTCH_INT_RBUF_ST (1 << 13) /* RX buffer status */
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#define BUTCH_INT_CDERR (1 << 14) /* CD error */
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/* bits 15-16: reserved */
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#define BUTCH_INT_RESET (1 << 17) /* CD reset */
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#define BUTCH_INT_BIOS (1 << 18) /* BIOS present */
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#define BUTCH_INT_LIDRESET (1 << 19) /* Open lid reset */
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#define BUTCH_INT_KARTRESET (1 << 20) /* Cart pull reset */
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/* eint (external interrupt to Jerry) logic:
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* butch.v line 83:
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* eint = butch_reg[0][0] && (fifo_int || frame_int || sub_int || tbuf_int || rbuf_int)
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* where:
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* fifo_int = butch_reg[0][9] && butch_reg[0][1]
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* frame_int = butch_reg[0][10] && butch_reg[0][2]
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* sub_int = butch_reg[0][11] && butch_reg[0][3]
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* tbuf_int = butch_reg[0][12] && butch_reg[0][4]
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* rbuf_int = butch_reg[0][13] && butch_reg[0][5]
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*/
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/* I2S control (butch_reg[4]) — butch.v lines 228-232: */
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#define BUTCH_I2S_DRIVE (1 << 0) /* i2s_drive */
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#define BUTCH_I2S_JERRY (1 << 1) /* i2s_jerry (route to Jerry DAC) */
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#define BUTCH_I2S_FIFO_EN (1 << 2) /* i2s_fifo_enabled */
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#define BUTCH_I2S_16BIT (1 << 3) /* 16-bit mode */
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#define BUTCH_I2S_FIFONEMPTY (1 << 4) /* FIFO not empty (read-only status) */
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/* FIFO: 16 entries deep, 32-bit wide.
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* butch.v line 295: fifo_half = (fifo_fill >= 8) */
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#define BUTCH_FIFO_DEPTH 16
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#define BUTCH_FIFO_HALF 8
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/* DSA (Disc Servo Assembly) control — butch_reg[1]:
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* Enable bit at bit 16 */
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#define BUTCH_DSA_ENABLE (1 << 16)
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/* EEPROM interface (butch_reg[11]) — butch.v line 302:
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* Note: active-low CS! eeprom_cs = !butch_reg[11][0] */
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#define BUTCH_EE_CS (1 << 0) /* Chip select (active-low in hardware!) */
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#define BUTCH_EE_CLK (1 << 1) /* Serial clock */
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#define BUTCH_EE_DOUT (1 << 2) /* Data out to EEPROM */
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#define BUTCH_EE_DIN (1 << 3) /* Data in from EEPROM (read-only) */
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/* ================================================================== */
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/* DSA Command/Response — from butch.v lines 132-226 */
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/* ================================================================== */
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/* DSA Commands: */
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#define DSA_CMD_PLAY_TITLE 0x01
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#define DSA_CMD_STOP 0x02
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#define DSA_CMD_READ_TOC 0x03
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#define DSA_CMD_PAUSE 0x04
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#define DSA_CMD_PAUSE_RELEASE 0x05
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#define DSA_CMD_SEARCH_FWD 0x06
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#define DSA_CMD_SEARCH_BWD 0x07
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#define DSA_CMD_SEARCH_REL 0x08
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#define DSA_CMD_GET_LENGTH 0x09
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#define DSA_CMD_GET_TIME 0x0D
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#define DSA_CMD_GOTO_MIN 0x10
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#define DSA_CMD_GOTO_SEC 0x11
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#define DSA_CMD_GOTO_FRM 0x12
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#define DSA_CMD_READ_LONG_TOC 0x14
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#define DSA_CMD_SET_MODE 0x15
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#define DSA_CMD_GET_ERROR 0x16
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#define DSA_CMD_CLR_ERROR 0x17
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#define DSA_CMD_SPIN_UP 0x18
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#define DSA_CMD_PLAY_AB_MIN 0x20
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#define DSA_CMD_PLAY_AB_SEC 0x21
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#define DSA_CMD_PLAY_AB_FRM 0x22
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#define DSA_CMD_STOP_AB_MIN 0x23
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#define DSA_CMD_STOP_AB_SEC 0x24
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#define DSA_CMD_STOP_AB_FRM 0x25
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#define DSA_CMD_RELEASE_AB 0x26
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#define DSA_CMD_GET_DISC_ID 0x30
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#define DSA_CMD_GET_STATUS 0x50
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#define DSA_CMD_SET_VOLUME 0x51
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#define DSA_CMD_CLEAR_TOC 0x6A
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#define DSA_CMD_SET_DAC 0x70
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/* DSA Responses: */
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#define DSA_RSP_FOUND 0x01
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#define DSA_RSP_STOPPED 0x02
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#define DSA_RSP_DISC_STATUS 0x03
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#define DSA_RSP_ERROR 0x04
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#define DSA_RSP_LENGTH_LSB 0x09
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#define DSA_RSP_LENGTH_MSB 0x0A
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#define DSA_RSP_ACT_TITLE 0x10
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#define DSA_RSP_ACT_INDEX 0x11
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#define DSA_RSP_ACT_MIN 0x12
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#define DSA_RSP_ACT_SEC 0x13
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#define DSA_RSP_ABS_MIN 0x14
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#define DSA_RSP_ABS_SEC 0x15
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#define DSA_RSP_ABS_FRM 0x16
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#define DSA_RSP_MODE_STATUS 0x17
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#define DSA_RSP_TOC_MIN_TRK 0x20
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#define DSA_RSP_TOC_MAX_TRK 0x21
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#define DSA_RSP_TOC_LO_MIN 0x22
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#define DSA_RSP_TOC_LO_SEC 0x23
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#define DSA_RSP_TOC_LO_FRM 0x24
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#define DSA_RSP_AB_RELEASED 0x26
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#define DSA_RSP_DISC_ID0 0x30
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#define DSA_RSP_DISC_ID1 0x31
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#define DSA_RSP_DISC_ID2 0x32
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#define DSA_RSP_DISC_ID3 0x33
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#define DSA_RSP_DISC_ID4 0x34
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#define DSA_RSP_VOLUME 0x51
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#define DSA_RSP_LONG_TOC_TRK 0x60
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#define DSA_RSP_LONG_TOC_CA 0x61
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#define DSA_RSP_LONG_TOC_MIN 0x62
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#define DSA_RSP_LONG_TOC_SEC 0x63
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#define DSA_RSP_LONG_TOC_FRM 0x64
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#define DSA_RSP_TOC_CLEARED 0x6A
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#define DSA_RSP_DAC_MODE 0x70
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#define DSA_RSP_SERVO_VER 0xF0
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/* DSA Error Codes: */
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#define DSA_ERR_NONE 0x00
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#define DSA_ERR_FOCUS 0x02 /* No disc */
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#define DSA_ERR_SUBCODE 0x07
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#define DSA_ERR_TOC 0x08
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#define DSA_ERR_RADIAL 0x0A
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#define DSA_ERR_SLEDGE 0x0C
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#define DSA_ERR_MOTOR 0x0D
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#define DSA_ERR_EMERGENCY 0x30
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#define DSA_ERR_SEARCH_TIME 0x1F
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#define DSA_ERR_SEARCH_BIN 0x20
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#define DSA_ERR_SEARCH_IDX 0x21
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#define DSA_ERR_SEARCH_TIME2 0x22
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#define DSA_ERR_ILLEGAL_CMD 0x28
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#define DSA_ERR_ILLEGAL_VAL 0x29
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#define DSA_ERR_ILLEGAL_TIME 0x2A
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#define DSA_ERR_COMMS 0x2B
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#define DSA_ERR_TRAY 0x2C
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#define DSA_ERR_HF_DETECT 0x2D
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/* ================================================================== */
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/* TOM Registers — from tom.v, iodec.v */
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/* ================================================================== */
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/* TOM IRQ control ($F000E0) — 5 interrupt sources */
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#define TOM_INT_VIDEO 0 /* Vertical blank */
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#define TOM_INT_GPU 1 /* GPU done */
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#define TOM_INT_OP 2 /* Object Processor */
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#define TOM_INT_TIMER 3 /* PIT timer */
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#define TOM_INT_JERRY 4 /* JERRY cascade */
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/* INT1 register ($F000E0) layout:
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* Write: bits 0-4 = enable, bits 8-12 = clear
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* Read: bits 0-4 = enable state */
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/* ================================================================== */
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/* JERRY Registers — from j_jerry.v, j_jmisc.v */
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/* ================================================================== */
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/* JERRY timer (PIT) registers: */
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#define JERRY_PIT1_PRESCALE 0xF10000 /* PIT1 prescaler (write) */
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#define JERRY_PIT1_DIVIDER 0xF10004 /* PIT1 divider (write) */
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#define JERRY_PIT2_PRESCALE 0xF10008 /* PIT2 prescaler (write) -- unverified */
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#define JERRY_PIT2_DIVIDER 0xF1000C /* PIT2 divider (write) -- unverified */
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/* CLK registers: */
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#define JERRY_CLK1 0xF10010
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#define JERRY_CLK2 0xF10012
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#define JERRY_CLK3 0xF10014
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/* JERRY interrupt control: */
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#define JERRY_INT_CTRL 0xF10020
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/* JERRY IRQ bitmasks (from jerry.h IRQ2_ enum): */
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#define JERRY_IRQ2_EXTERNAL 0x01
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#define JERRY_IRQ2_DSP 0x02
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#define JERRY_IRQ2_TIMER1 0x04
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#define JERRY_IRQ2_TIMER2 0x08
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#define JERRY_IRQ2_ASI 0x10
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#define JERRY_IRQ2_SSI 0x20
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/* ================================================================== */
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/* Memory Map — from address decode logic */
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/* ================================================================== */
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#define JAGUAR_MAIN_RAM_START 0x000000
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#define JAGUAR_MAIN_RAM_END 0x1FFFFF /* 2MB */
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#define JAGUAR_MAIN_RAM_SIZE 0x200000
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#define JAGUAR_GPU_RAM_BASE 0xF03000
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#define JAGUAR_GPU_RAM_SIZE 0x1000 /* 4KB */
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#define JAGUAR_GPU_RAM_END 0xF03FFF
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#define JAGUAR_DSP_RAM_BASE 0xF1B000
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#define JAGUAR_DSP_RAM_SIZE 0x2000 /* 8KB */
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#define JAGUAR_DSP_RAM_END 0xF1CFFF
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#define JAGUAR_CART_ROM_START 0x800000
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#define JAGUAR_CART_ROM_END 0xDFFEFF
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#define JAGUAR_TOM_REG_BASE 0xF00000
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#define JAGUAR_JERRY_REG_BASE 0xF10000
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/* ================================================================== */
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/* Blitter Registers ($F02200-$F022FF) — from dcontrol.v, blit.v */
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/* ================================================================== */
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#define BLIT_A1_BASE 0xF02200
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#define BLIT_A1_FLAGS 0xF02204
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#define BLIT_A1_CLIP 0xF02208
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#define BLIT_A1_PIXEL 0xF0220C
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#define BLIT_A1_STEP 0xF02210
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#define BLIT_A1_FSTEP 0xF02214
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#define BLIT_A1_FPIXEL 0xF02218
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#define BLIT_A1_INC 0xF0221C
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#define BLIT_A1_FINC 0xF02220
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#define BLIT_A2_BASE 0xF02224
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#define BLIT_A2_FLAGS 0xF02228
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#define BLIT_A2_MASK 0xF0222C
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#define BLIT_A2_PIXEL 0xF02230
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#define BLIT_A2_STEP 0xF02234
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#define BLIT_B_CMD 0xF02238
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#define BLIT_B_COUNT 0xF0223C
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#define BLIT_B_SRCD 0xF02240
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#define BLIT_B_DSTD 0xF02248
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#define BLIT_B_DSTZ 0xF02250
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#define BLIT_B_SRCZ1 0xF02258
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#define BLIT_B_SRCZ2 0xF02260
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#define BLIT_B_PATD 0xF02268
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#define BLIT_B_IINC 0xF02270
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#define BLIT_B_ZINC 0xF02274
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#define BLIT_B_STOP 0xF02278
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#define BLIT_B_I3 0xF0227C
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#define BLIT_B_I2 0xF02280
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#define BLIT_B_I1 0xF02284
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#define BLIT_B_I0 0xF02288
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#define BLIT_B_Z3 0xF0228C
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#define BLIT_B_Z2 0xF02290
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#define BLIT_B_Z1 0xF02294
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#define BLIT_B_Z0 0xF02298
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/* Blitter command bits (B_CMD): */
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#define BLIT_SRCEN (1 << 0)
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#define BLIT_SRCENZ (1 << 1)
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#define BLIT_SRCENX (1 << 2)
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#define BLIT_DSTEN (1 << 3)
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#define BLIT_DSTENZ (1 << 4)
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#define BLIT_DSTWRZ (1 << 5)
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#define BLIT_CLIP_A1 (1 << 6)
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#define BLIT_UPDA1F (1 << 8)
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#define BLIT_UPDA1 (1 << 9)
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#define BLIT_UPDA2 (1 << 10)
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#define BLIT_DSTA2 (1 << 11)
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#define BLIT_GOURD (1 << 12) /* dcontrol.v: gpu_din[12] */
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#define BLIT_GOURZ (1 << 13) /* dcontrol.v: gpu_din[13] */
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#define BLIT_TOPBEN (1 << 14)
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#define BLIT_TOPNEN (1 << 15)
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#define BLIT_PATDSEL (1 << 16)
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#define BLIT_ADDDSEL (1 << 17)
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/* ================================================================== */
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/* Caller type IDs (for who parameter in read/write functions) */
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/* ================================================================== */
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#define CALLER_M68K 0
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#define CALLER_GPU 1
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#define CALLER_DSP 2
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#define CALLER_TOM 3
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#define CALLER_JERRY 4
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#define CALLER_BLIT 5
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#endif /* MISTER_GROUND_TRUTH_H */
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