libretro/xmil-libretro
1
0
Fork 0
mirror of https://github.com/libretro/xmil-libretro.git synced 2024-11-27 02:10:21 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

fix...

Browse Source
This commit is contained in:
yui 2004-08-20 23:01:16 +00:00
parent b0af4960b8
commit 4897f407d4
18 changed files with 115 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
debugsub.c
View File

@ -40,7 +40,7 @@ void debugsub_status(void) {
OEMSPRINTF(path, OEMTEXT("z80ram.%.3d"), filenum);
fh = file_create_c(path);
if (fh != FILEH_INVALID) {
file_write(fh, mMAIN, 0x10000);
file_write(fh, mainmem, 0x10000);
file_close(fh);
}
OEMSPRINTF(path, OEMTEXT("x1vram1.%.3d"), filenum);

19
io/memio.c
View File

@ -4,22 +4,29 @@
#include "iocore.h"
UINT8 biosmem[0x8000];
#if defined(SUPPORT_BANKMEM)
UINT8 bankmem[16][0x8000];
#endif
void memio_update(void) {
#if defined(SUPPORT_BANKMEM)
if (memio.bank & 0x10) {
#endif
if (!memio.ram) {
RAM0r = mBIOS;
RAM0w = mMAIN;
z80core.e.memread = biosmem;
}
else {
RAM0r = RAM0w = mMAIN;
z80core.e.memread = mainmem;
}
z80core.e.memwrite = mainmem;
#if defined(SUPPORT_BANKMEM)
}
else {
RAM0r = RAM0w = mBANK[memio.bank & 15];
z80core.e.memread = bankmem[memio.bank & 15];
z80core.e.memwrite = bankmem[memio.bank & 15];
}
#endif
}
@ -45,7 +52,7 @@ void IOOUTCALL memio_rom(UINT port, REG8 dat) {
#if defined(SUPPORT_BANKMEM)
if (memio.bank & 0x10) {
#endif
RAM0r = mBIOS;
z80core.e.memread = biosmem;
#if defined(SUPPORT_BANKMEM)
}
#endif
@ -59,7 +66,7 @@ void IOOUTCALL memio_ram(UINT port, REG8 dat) {
#if defined(SUPPORT_BANKMEM)
if (memio.bank & 0x10) {
#endif
RAM0r = mMAIN;
z80core.e.memread = mainmem;
#if defined(SUPPORT_BANKMEM)
}
#endif

5
io/memio.h
View File

@ -11,6 +11,11 @@ typedef struct {
extern "C" {
#endif
extern UINT8 biosmem[0x8000];
#if defined(SUPPORT_BANKMEM)
extern UINT8 bankmem[16][0x8000];
#endif
void memio_update(void);
#if defined(SUPPORT_BANKMEM)

6
io/pcg.c
View File

@ -4,6 +4,7 @@
#include "iocore.h"
#include "nevent.h"
#include "vram.h"
#include "makescrn.h"
#include "font.h"
@ -111,7 +112,10 @@ void IOOUTCALL pcg_o(UINT port, REG8 value) {
chr = tram[TRAM_ANK + off];
}
chr += (port & 0x0300) - 0x100;
pcg.d[(chr << 3) + line] = value;
if (pcg.d[(chr << 3) + line] != value) {
pcg.d[(chr << 3) + line] = value;
scrnallflash = TRUE;
}
}
REG8 IOINPCALL pcg_i(UINT port) {

19
pccore.c
View File

@ -31,13 +31,6 @@ const OEMCHAR xmilversion[] = OEMTEXT(XMILVER_CORE);
PCCORE pccore;
CORESTAT corestat;
UINT8 mMAIN[0x10000];
UINT8 mBIOS[0x8000];
#if defined(SUPPORT_BANKMEM)
UINT8 mBANK[16][0x8000];
#endif
UINT8 *RAM0r;
UINT8 *RAM0w;
// ----
@ -46,18 +39,18 @@ static void ipl_load(void) {
FILEH hdl;
ZeroMemory(mBIOS, sizeof(mBIOS));
CopyMemory(mBIOS, DEFROM, sizeof(DEFROM));
ZeroMemory(biosmem, 0x8000);
CopyMemory(biosmem, DEFROM, sizeof(DEFROM));
if (pccore.ROM_TYPE >= 2) {
if ((hdl = file_open_c(OEMTEXT("IPLROM.X1T"))) != FILEH_INVALID) {
file_read(hdl, mBIOS, 0x8000);
file_read(hdl, biosmem, 0x8000);
file_close(hdl);
}
}
else if (pccore.ROM_TYPE == 1) {
if ((hdl = file_open_c(OEMTEXT("IPLROM.X1"))) != FILEH_INVALID) {
file_read(hdl, mBIOS, 0x8000);
file_read(hdl, biosmem, 0x8000);
file_close(hdl);
}
}
@ -68,6 +61,7 @@ static void ipl_load(void) {
void pccore_initialize(void) {
Z80_INITIALIZE();
fddfile_initialize();
sndctrl_initialize();
makescrn_initialize();
@ -129,9 +123,6 @@ void pccore_reset(void) {
ipl_load();
RAM0r = mBIOS;
RAM0w = mMAIN;
pal_reset();
makescrn_reset();
timing_reset();

8
pccore.h
View File

@ -56,14 +56,6 @@ extern const OEMCHAR xmilversion[];
extern XMILCFG xmilcfg;
extern PCCORE pccore;
extern CORESTAT corestat;
extern UINT8 *RAM0r;
extern UINT8 *RAM0w;
extern UINT8 mMAIN[0x10000];
extern UINT8 mBIOS[0x8000];
#if defined(SUPPORT_BANKMEM)
extern UINT8 mBANK[16][0x8000];
#endif
void neitem_disp(UINT id);
void neitem_vsync(UINT id);

6
statsave.tbl
View File

@ -28,10 +28,10 @@ static const SFENTRY xmiltbl[] = {
{"PCCORE", 0, STATFLAG_BIN, &pccore, sizeof(pccore)},
{"Z80CORE", 0, STATFLAG_BIN, &z80core.s, sizeof(z80core.s)},
{"MAIN", 0, STATFLAG_BIN, mMAIN, sizeof(mMAIN)},
{"BIOS", 0, STATFLAG_BIN, mBIOS, sizeof(mBIOS)},
{"MAIN", 0, STATFLAG_BIN, mainmem, sizeof(mainmem)},
{"BIOS", 0, STATFLAG_BIN, biosmem, sizeof(biosmem)},
#if defined(SUPPORT_BANKMEM)
{"BANK", 0, STATFLAG_BIN, mBANK, sizeof(mBANK)},
{"BANK", 0, STATFLAG_BIN, bankmem, sizeof(bankmem)},
#endif
{"GRAM", 0, STATFLAG_BIN, gram, sizeof(gram)},
{"TRAM", 0, STATFLAG_BIN, tram, sizeof(tram)},

23
z80c/z80c.c
View File

@ -17,11 +17,12 @@
Z80CORE z80core;
UINT8 mainmem[0x10000];
UINT8 ZSPtable[256];
UINT8 z80inc_flag[256];
UINT8 z80dec_flag[256];
UINT8 z80inc_flag2[256];
UINT8 z80dec_flag2[256];
UINT8 z80szc_flag[512];
UINT8 z80szp_flag[256];
const UINT8 cycles_main[256] = {
4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
@ -98,28 +99,26 @@ void CPUCALL z80c_initialize(void) {
}
}
ZSPtable[i] = (UINT8)f;
z80szp_flag[i] = (UINT8)f;
z80inc_flag[i] = (UINT8)(f & (~V_FLAG));
z80inc_flag2[(i - 1) & 0xff] = (UINT8)(f & (~V_FLAG));
if (!(i & 0x0f)) {
z80inc_flag[i] |= H_FLAG;
z80inc_flag2[(i - 1) & 0xff] |= H_FLAG;
}
z80dec_flag[i] = (UINT8)(f & (~V_FLAG)) | N_FLAG;
z80dec_flag2[(i + 1) & 0xff] = (UINT8)(f & (~V_FLAG)) | N_FLAG;
if ((i & 0x0f) == 0x0f) {
z80dec_flag[i] |= H_FLAG;
z80dec_flag2[(i + 1) & 0xff] |= H_FLAG;
}
z80szc_flag[i] = (UINT8)(f & (~V_FLAG));
z80szc_flag[i+256] = (UINT8)(f & (~V_FLAG)) | C_FLAG;
}
z80inc_flag[0x80] |= V_FLAG;
z80dec_flag[0x7f] |= V_FLAG;
z80inc_flag2[0x80 - 1] |= V_FLAG;
z80dec_flag2[0x7f + 1] |= V_FLAG;
}
void CPUCALL z80c_reset(void) {
z80c_initialize();
ZeroMemory(&z80core.s, sizeof(z80core.s));
R_Z80R = rand_get();
}

6
z80c/z80c.h
View File

@ -7,10 +7,10 @@
//----------------------------------------------------------------------------
extern UINT8 ZSPtable[256];
extern UINT8 z80inc_flag[256];
extern UINT8 z80dec_flag[256];
extern UINT8 z80inc_flag2[256];
extern UINT8 z80dec_flag2[256];
extern UINT8 z80szc_flag[512];
extern UINT8 z80szp_flag[256];
extern const UINT8 cycles_main[256];
extern const UINT8 cycles_xx[256];

26
z80c/z80c.mcr
View File

@ -66,14 +66,14 @@
#define MCR_INC(reg) { \
R_Z80F &= C_FLAG; \
R_Z80F |= z80inc_flag2[(reg)]; \
(reg)++; \
R_Z80F |= z80inc_flag[(reg)]; \
}
#define MCR_DEC(reg) { \
R_Z80F &= C_FLAG; \
R_Z80F |= z80dec_flag2[(reg)]; \
(reg)--; \
R_Z80F |= z80dec_flag[(reg)]; \
}
#define LDB_b(reg) { \
@ -193,7 +193,7 @@
} \
} \
R_Z80A = (UINT8)dst; \
R_Z80F = flg | ZSPtable[dst & 0xff]; \
R_Z80F = flg | z80szp_flag[dst & 0xff]; \
}
#define MCR_JRFLG(flg) { \
@ -226,21 +226,19 @@
}
#define MCR_INC_MEM(adrs) { \
UINT8 tmp; \
REG8 tmp; \
tmp = mem_read8((adrs)); \
tmp++; \
mem_write8((adrs), tmp); \
R_Z80F &= C_FLAG; \
R_Z80F |= z80inc_flag[tmp]; \
R_Z80F |= z80inc_flag2[tmp]; \
mem_write8((adrs), (REG8)(tmp + 1)); \
}
#define MCR_DEC_MEM(adrs) { \
UINT8 tmp; \
REG8 tmp; \
tmp = mem_read8((adrs)); \
tmp--; \
mem_write8((adrs), tmp); \
R_Z80F &= C_FLAG; \
R_Z80F |= z80dec_flag[tmp]; \
R_Z80F |= z80dec_flag2[tmp]; \
mem_write8((adrs), (REG8)(tmp - 1)); \
}
#define LDB_xhl_b { \
@ -343,7 +341,7 @@
#define MCR_AND(b) { \
R_Z80A &= (b); \
R_Z80F = ZSPtable[R_Z80A]; \
R_Z80F = z80szp_flag[R_Z80A]; \
}
#define MCR_AND_XHL { \
@ -354,7 +352,7 @@
#define MCR_XOR(b) { \
R_Z80A ^= (b); \
R_Z80F = ZSPtable[R_Z80A]; \
R_Z80F = z80szp_flag[R_Z80A]; \
}
#define MCR_XOR_XHL { \
@ -366,7 +364,7 @@
#define MCR_OR(b) { \
R_Z80A |= (b); \
R_Z80F = ZSPtable[R_Z80A]; \
R_Z80F = z80szp_flag[R_Z80A]; \
}
#define MCR_OR_XHL { \

16
z80c/z80c_cb.c
View File

@ -19,7 +19,7 @@ static REG8 CPUCALL _cb_rlc(REG8 v) {
R_Z80F = v >> 7;
ret = (v << 1) | R_Z80F;
R_Z80F |= ZSPtable[(UINT8)ret];
R_Z80F |= z80szp_flag[(UINT8)ret];
return(ret);
}
@ -29,7 +29,7 @@ static REG8 CPUCALL _cb_rrc(REG8 v) {
R_Z80F = v & 1;
ret = (v >> 1) | (R_Z80F << 7);
R_Z80F |= ZSPtable[(UINT8)ret];
R_Z80F |= z80szp_flag[(UINT8)ret];
return(ret);
}
@ -38,7 +38,7 @@ static REG8 CPUCALL _cb_rl(REG8 v) {
REG8 ret;
ret = (v << 1) | (R_Z80F & 1);
R_Z80F = ZSPtable[(UINT8)ret] | (v >> 7);
R_Z80F = z80szp_flag[(UINT8)ret] | (v >> 7);
return(ret);
}
@ -47,7 +47,7 @@ static REG8 CPUCALL _cb_rr(REG8 v) {
REG8 ret;
ret = (v >> 1) | (R_Z80F << 7);
R_Z80F = ZSPtable[(UINT8)ret] | (v & 1);
R_Z80F = z80szp_flag[(UINT8)ret] | (v & 1);
return(ret);
}
@ -56,7 +56,7 @@ static REG8 CPUCALL _cb_sla(REG8 v) {
REG8 ret;
ret = (v << 1);
R_Z80F = ZSPtable[(UINT8)ret] | (v >> 7);
R_Z80F = z80szp_flag[(UINT8)ret] | (v >> 7);
return(ret);
}
@ -65,7 +65,7 @@ static REG8 CPUCALL _cb_sra(REG8 v) {
REG8 ret;
ret = (((SINT8)v) >> 1);
R_Z80F = ZSPtable[(UINT8)ret] | (v & 1);
R_Z80F = z80szp_flag[(UINT8)ret] | (v & 1);
return(ret);
}
@ -74,7 +74,7 @@ static REG8 CPUCALL _cb_sll(REG8 v) {
REG8 ret;
ret = (v << 1) | 1;
R_Z80F = ZSPtable[(UINT8)ret] | (v >> 7);
R_Z80F = z80szp_flag[(UINT8)ret] | (v >> 7);
return(ret);
}
@ -83,7 +83,7 @@ static REG8 CPUCALL _cb_srl(REG8 v) {
REG8 ret;
ret = v >> 1;
R_Z80F = ZSPtable[ret] | (v & 1);
R_Z80F = z80szp_flag[ret] | (v & 1);
return(ret);
}

8
z80c/z80c_s.mcr
View File

@ -2,7 +2,7 @@
#define MCR_Z80INF(reg) { \
(reg) = iocore_inp(R_Z80BC); \
R_Z80F &= C_FLAG; \
R_Z80F |= ZSPtable[(reg)]; \
R_Z80F |= z80szp_flag[(reg)]; \
}
#define MCR_Z80OUT(reg) { \
@ -97,7 +97,7 @@
mem_write8(R_Z80HL, (REG8)((tmp >> 4) | (R_Z80A << 4))); \
R_Z80A = (R_Z80A & 0xf0) | (tmp & 0x0f); \
R_Z80F &= C_FLAG; \
R_Z80F |= ZSPtable[R_Z80A]; \
R_Z80F |= z80szp_flag[R_Z80A]; \
}
#define MCR_RLD { \
@ -106,7 +106,7 @@
mem_write8(R_Z80HL, (REG8)((tmp << 4) + (R_Z80A & 0x0f))); \
R_Z80A = (R_Z80A & 0xf0) | (tmp >> 4); \
R_Z80F &= C_FLAG; \
R_Z80F |= ZSPtable[R_Z80A]; \
R_Z80F |= z80szp_flag[R_Z80A]; \
}
@ -114,7 +114,7 @@
REG8 tmp; \
tmp = iocore_inp(R_Z80BC); \
R_Z80F &= C_FLAG; \
R_Z80F |= ZSPtable[tmp]; \
R_Z80F |= z80szp_flag[tmp]; \
}

4
z80c/z80core.h
View File

@ -94,7 +94,8 @@ typedef struct {
} Z80STAT;
typedef struct {
UINT dummy;
UINT8 *memread;
UINT8 *memwrite;
} Z80EXT;
typedef struct {
@ -111,6 +112,7 @@ extern "C" {
#endif
extern Z80CORE z80core;
extern UINT8 mainmem[0x10000];
void CPUCALL z80c_initialize(void);
void CPUCALL z80c_reset(void);

20
z80c/z80mem.c
View File

@ -6,30 +6,30 @@
REG8 MEMCALL mem_read8(UINT addr) {
if (addr & 0x8000) {
return(mMAIN[addr]);
return(mainmem[addr]);
}
else {
return(RAM0r[addr]);
return(z80core.e.memread[addr]);
}
}
SINT MEMCALL mem_read8s(UINT addr) {
if (addr & 0x8000) {
return((SINT)(SINT8)mMAIN[addr]);
return((SINT)(SINT8)mainmem[addr]);
}
else {
return((SINT)(SINT8)RAM0r[addr]);
return((SINT)(SINT8)z80core.e.memread[addr]);
}
}
void MEMCALL mem_write8(UINT addr, REG8 value) {
if (addr & 0x8000) {
mMAIN[addr] = (UINT8)value;
mainmem[addr] = (UINT8)value;
}
else {
RAM0w[addr] = (UINT8)value;
z80core.e.memwrite[addr] = (UINT8)value;
}
}
@ -37,10 +37,10 @@ REG16 MEMCALL mem_read16(UINT addr) {
if ((addr & 0x7fff) != 0x7fff) {
if (addr & 0x8000) {
return(LOADINTELWORD(mMAIN + addr));
return(LOADINTELWORD(mainmem + addr));
}
else {
return(LOADINTELWORD(RAM0r + addr));
return(LOADINTELWORD(z80core.e.memread + addr));
}
}
else {
@ -52,10 +52,10 @@ void MEMCALL mem_write16(UINT addr, REG16 value) {
if ((addr & 0x7fff) != 0x7fff) {
if (addr & 0x8000) {
STOREINTELWORD(mMAIN + addr, value);
STOREINTELWORD(mainmem + addr, value);
}
else {
STOREINTELWORD(RAM0w + addr, value);
STOREINTELWORD(z80core.e.memwrite + addr, value);
}
}
else {

4
z80x/z80core.h
View File

@ -90,7 +90,8 @@ typedef struct {
} Z80STAT;
typedef struct {
UINT dummy;
UINT8 *memread;
UINT8 *memwrite;
} Z80EXT;
typedef struct {
@ -107,6 +108,7 @@ extern "C" {
#endif
extern Z80CORE z80core;
extern UINT8 mainmem[0x10000];
void z80x_initialize(void);
void z80x_reset(void);

3
z80x/z80x.c
View File

@ -5,6 +5,7 @@
Z80CORE z80core;
UINT8 mainmem[0x10000];
UINT8 ZSPtable[256];
UINT8 z80inc_flag[256];
@ -106,8 +107,6 @@ void z80x_initialize(void) {
void z80x_reset(void) {
z80x_initialize();
ZeroMemory(&z80core.s, sizeof(z80core.s));
z80core.s.r1 = rand_get();
}

3
z80x/z80x.inc
View File

@ -43,6 +43,9 @@
.baseclock resd 1
.clock resd 1
.memread resd 1
.memwrite resd 1
endstruc
S_FLAG equ 0x80

50
z80x/z80xmem.x86
View File

@ -1,10 +1,10 @@
%include '../z80x/z80x.inc'
section .bss
extern _mMAIN
extern _RAM0r
extern _RAM0w
extern _z80core
extern _mainmem
section .text
@ -24,18 +24,18 @@ section .text
align 16
lea_ecx_ecx: cmp ecx, 8000h
jc short .low
add ecx, _mMAIN
add ecx, _mainmem
ret
.low: add ecx, [_RAM0r]
.low: add ecx, [_z80core + z80core_t.memread]
ret
align 16
memfetch: cmp ecx, 8000h
jc short .low
movzx eax, byte [_mMAIN + ecx]
movzx eax, byte [_mainmem + ecx]
ret
.low: mov edx, [_RAM0r]
.low: mov edx, [_z80core + z80core_t.memread]
movzx eax, byte [edx + ecx]
ret
@ -43,18 +43,18 @@ memfetch: cmp ecx, 8000h
@z80mem_read8@4:
memrd8_ecx_al: cmp ecx, 8000h
jc short .low
mov al, [_mMAIN + ecx]
mov al, [_mainmem + ecx]
ret
.low: mov edx, [_RAM0r]
.low: mov edx, [_z80core + z80core_t.memread]
mov al, [edx + ecx]
ret
align 16
memrd8_ecx_dl: cmp ecx, 8000h
jc short .low
mov dl, [_mMAIN + ecx]
mov dl, [_mainmem + ecx]
ret
.low: mov edx, [_RAM0r]
.low: mov edx, [_z80core + z80core_t.memread]
mov dl, [edx + ecx]
ret
@ -62,9 +62,9 @@ memrd8_ecx_dl: cmp ecx, 8000h
@z80mem_write8@8:
memwr8_ecx_dl: cmp ecx, 8000h
jc short .low
mov [_mMAIN + ecx], dl
mov [_mainmem + ecx], dl
ret
.low: mov eax, [_RAM0w]
.low: mov eax, [_z80core + z80core_t.memwrite]
mov [eax + ecx], dl
ret
@ -73,18 +73,18 @@ memrd16_ecx_ax: cmp cx, 0xffff
jo short .a7fff
js short .a8000
je short .affff
mov eax, [_RAM0r]
mov eax, [_z80core + z80core_t.memread]
mov ax, [eax + ecx]
ret
.a7fff: mov eax, [_RAM0r]
.a7fff: mov eax, [_z80core + z80core_t.memread]
mov al, [eax + ecx]
mov ah, [_mMAIN + ecx + 1]
mov ah, [_mainmem + ecx + 1]
ret
.a8000: mov ax, [_mMAIN + ecx]
.a8000: mov ax, [_mainmem + ecx]
ret
.affff: mov eax, [_RAM0r]
.affff: mov eax, [_z80core + z80core_t.memread]
mov ah, [eax]
mov al, [_mMAIN + ecx]
mov al, [_mainmem + ecx]
ret
align 16
@ -92,17 +92,17 @@ memwr16_ecx_dx: cmp cx, 0xffff
jo short .a7fff
js short .a8000
je short .affff
mov eax, [_RAM0w]
mov eax, [_z80core + z80core_t.memwrite]
mov [eax + ecx], dx
ret
.a7fff: mov eax, [_RAM0w]
mov [_mMAIN + ecx + 1], dh
.a7fff: mov eax, [_z80core + z80core_t.memwrite]
mov [_mainmem + ecx + 1], dh
mov [eax + ecx], dl
ret
.a8000: mov [_mMAIN + ecx], dx
.a8000: mov [_mainmem + ecx], dx
ret
.affff: mov eax, [_RAM0w]
mov [_mMAIN + ecx], dl
.affff: mov eax, [_z80core + z80core_t.memwrite]
mov [_mainmem + ecx], dl
mov [eax], dh
ret