fix...

debugsub.c

@@ -24,11 +24,13 @@ void debugsub_status(void) {
 						"DE = %04x\nHL = %04x\nIX = %04x\n"		\
 						"IY = %04x\nSP = %04x\nAF'= %04x\n"		\
 						"BC'= %04x\nDE'= %04x\nHL'= %04x\n\n"	\
+						"IFF = %.2x\n"							\
 						"IM = %2d\nADRS = %02x%02x\n\n"			\
 						"FNT_YL = %3d\nTXT_YL = %3d\nSCRN_b = %02x\n",
 						Z80_PC, Z80_AF, Z80_BC, Z80_DE,
 						Z80_HL, Z80_IX, Z80_IY, Z80_SP,
 						Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2,
+						Z80_IFF,
 						Z80_IM, Z80_I, subcpu.Ex[4][0],
 						crtc.e.fonty, crtc.e.yl, crtc.s.SCRN_BITS);
 		file_write(fh, work, STRLEN(work));

fdd/fdd_d88.c

@@ -274,7 +274,7 @@ const _D88SEC	*sec;
 	}
 	sec = (D88SEC)trk->buf;
 	sectors = trk->sectors;
-	if (sectors >= num) {
+	if (num >= sectors) {
 		return(FDDSTAT_RECNFND);
 	}
 	while(num) {

ievent.c

@@ -9,9 +9,6 @@
 // ここでデイジーチェイン
 
 
-	IEVENT	ievent;
-
-
 typedef BRESULT (*IEVENTFN)(UINT id);
 
 static BRESULT dummy(UINT id) {
@@ -31,21 +28,24 @@ static const IEVENTFN ieventfn[IEVENT_MAX] = {
 
 // ----
 
-void ievent_reset(void) {
-}
-
 void ievent_progress(void) {
 
 	UINT	i;
 	UINT	bit;
 
-	if ((CPU_REQIRQ == 0) || (!Z80_ABLEINTERRUPT())) {
+	if ((CPU_REQIRQ == 0) || (Z80_DI)) {
 		return;
 	}
 	for (i=0, bit=1; i<IEVENT_MAX; i++, bit<<=1) {
+		if (CPU_IRQ & bit) {
+			break;
+		}
 		if (CPU_REQIRQ & bit) {
 			CPU_REQIRQ ^= bit;
 			if (ieventfn[i](i)) {
+				if (i != IEVENT_SUBCPU) {		// サブCPUは別処理
+					CPU_IRQ |= bit;
+				}
 				return;
 			}
 		}
@@ -56,13 +56,18 @@ void ievent_setbit(UINT bit) {
 
 	UINT	r;
 
-	r = CPU_REQIRQ;
-	if (r & bit) {
+	if (CPU_REQIRQ & bit) {
 		return;
 	}
 	CPU_REQIRQ |= bit;
-	if ((!r) && (Z80_ABLEINTERRUPT())) {
-		nevent_forceexit();
+	if (Z80_DI) {
+		return;
 	}
+	r = CPU_IRQ;
+	r = (r ^ (r - 1)) >> 1;
+	if (!(r & bit)) {
+		return;
+	}
+	nevent_forceexit();
 }
 

ievent.h

@@ -10,18 +10,12 @@ enum {
 	IEVENT_MAX
 };
 
-typedef struct {
-	UINT	dummy;
-} IEVENT;
-
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-extern	IEVENT	ievent;
-
-void ievent_reset(void);
+#define	ievent_reset()
 void ievent_progress(void);
 void ievent_setbit(UINT bit);
 

io/cgrom.c

@@ -38,6 +38,7 @@ REG8 IOINPCALL cgrom_i(UINT port) {
 			ret = font_knjx1[cgrom.face + cgrom.count + FONTX1_LR];
 			cgrom.flag |= 2;
 		}
+		// 0x0e81 ポートリードの時だけインクリメントの筈だが…？
 		if (cgrom.flag == 3) {
 			cgrom.flag = 0;
 			cgrom.count = (cgrom.count + 1) & 15;

io/crtc.c

@@ -23,13 +23,91 @@ static const UINT16 defpalgrph[64] = {
 
 static const UINT8 defrgbp[4] = {0xaa, 0xcc, 0xf0, 0x00};
 static const UINT8 defreg[18] = {
-				55, 40, 45, 0x36,
-				31, 10, 25, 28,
-				7, 7, 0, 0,
-				0, 0, 0, 0, 0, 0};
+				0x37, 0x28, 0x2d, 0x34,
+				0x1f, 0x02, 0x19, 0x1c,
+				0x00, 0x07, 0x00, 0x00,
+				0x00, 0x00, 0x00, 0x00,
+				0x00, 0x00};
+
+typedef struct {
+	UINT32	clock;
+	UINT	minx;
+	UINT	maxx;
+	UINT	miny;
+	UINT	maxy;
+} GDCCLK;
+
+static const GDCCLK gdcclk[] = {
+			{14318180 / 8, 112 - 8, 112 + 8, 200, 300},
+			{21052600 / 8, 108 - 6, 108 + 6, 400, 575}};
+
+enum {
+	CRTCUPD_CLOCK		= 0x01,
+	CRTCUPD_TIMING		= 0x02,
+	CRTCUPD_POS			= 0x04
+};
 
 
-void crtc_bankupdate(void) {
+static void crtc_clkupdate(void) {
+
+	UINT		clksync;
+const GDCCLK	*clk;
+	UINT		h;
+	UINT		fonty;
+	UINT		v;
+
+	clksync = (crtc.s.SCRN_BITS & SCRN_24KHZ);
+	clk = gdcclk + clksync;
+	h = crtc.s.reg[CRTCREG_HSIZE] + 1;
+	if (crtc.s.width40) {
+		h = h * 2;
+	}
+	if (h < clk->minx) {
+		h = clk->minx;
+	}
+	else if (h > clk->maxx) {
+		h = clk->maxx;
+	}
+	crtc.e.rasterclock8 = (4000000 * h) / (clk->clock >> 8);
+
+	fonty = crtc.s.reg[CRTCREG_CHRCY] & 0x1f;
+	fonty >>= clksync;
+	fonty += 1;
+	crtc.e.fonty = fonty;
+
+	v = (crtc.s.reg[CRTCREG_CHRCY] & 0x1f) + 1;
+	v = v * ((crtc.s.reg[CRTCREG_VSIZE] & 0x7f) + 1);
+	v = v + (crtc.s.reg[CRTCREG_VSIZEA] & 0x1f);
+	if (v < clk->miny) {
+		v = clk->miny;
+	}
+	else if (v > clk->maxy) {
+		v = clk->maxy;
+	}
+	crtc.e.frameclock = ((4000000 * h) / clk->clock) * v;
+}
+
+static void crtc_timingupdate(void) {
+
+	UINT32	fontclock;
+	UINT	yl;
+
+	fontclock = (crtc.s.reg[CRTCREG_CHRCY] & 0x1f) + 1;
+	fontclock = (fontclock * crtc.e.rasterclock8) >> 8;
+
+	// YsIIIが yl==0で disp信号見る…なんで？
+	yl = (crtc.s.reg[CRTCREG_VDISP] & 0x7f);
+	crtc.e.yl = yl;
+	crtc.e.dispclock = fontclock * max(yl, 1);
+	crtc.e.vsyncstart = fontclock * ((crtc.s.reg[CRTCREG_VSYNC] & 0x7f) + 1);
+	crtc.e.vpulseclock = ((crtc.s.reg[CRTCREG_PULSE] >> 4)
+												* crtc.e.rasterclock8) >> 8;
+
+	crtc.e.pos = crtc.s.reg[CRTCREG_POSL]
+									+ ((crtc.s.reg[CRTCREG_POSH] & 7) << 8);
+}
+
+static void crtc_bankupdate(void) {
 
 	UINT	updatemask;
 	UINT8	dispmode;
@@ -49,8 +127,7 @@ void crtc_bankupdate(void) {
 
 	if ((!(crtc.s.EXTPALMODE & 0x80)) || (crtc.s.SCRN_BITS & SCRN_UNDERLINE)) {
 		updatemask = 0x7ff;
-		if ((crtc.s.SCRN_BITS & SCRN_24KHZ) &&
-			(crtc.s.reg[CRTCREG_HDISP] == 80)) {
+		if ((crtc.s.SCRN_BITS & SCRN_24KHZ) && (!crtc.s.width40)) {
 			pal_bank = pal_disp = PAL_HIGHRESO;
 		}
 		if (crtc.s.SCRN_BITS & SCRN_TEXTYx2) {
@@ -61,7 +138,7 @@ void crtc_bankupdate(void) {
 		updatemask = 0x3ff;
 		if (!(crtc.s.SCRN_BITS & SCRN_TEXTYx2)) {
 			if (crtc.s.SCRN_BITS & SCRN_24KHZ) {
-				if (crtc.s.reg[CRTCREG_HDISP] == 40) {
+				if (crtc.s.width40) {
 					if (crtc.s.SCRN_BITS & SCRN_200LINE) {	// width 40,25,0,2
 						dispmode |= SCRN64_320x200;
 					}
@@ -75,7 +152,7 @@ void crtc_bankupdate(void) {
 				}
 			}
 			else {
-				if (crtc.s.reg[CRTCREG_HDISP] == 40) {		// width 40,25,0,1
+				if (crtc.s.width40) {						// width 40,25,0,1
 					if (crtc.s.EXTPALMODE & 0x10) {
 						if (crtc.s.ZPRY & 0x10) {
 							dispmode = SCRN64_L320x200x2 |
@@ -106,7 +183,7 @@ void crtc_bankupdate(void) {
 		}
 		else {
 			if (crtc.s.SCRN_BITS & SCRN_24KHZ) {
-				if (crtc.s.reg[CRTCREG_HDISP] == 40) {
+				if (crtc.s.width40) {
 					if (crtc.s.SCRN_BITS & SCRN_200LINE) {	// width 40,12,0,2
 						dispmode |= SCRN64_320x100;
 					}
@@ -119,7 +196,7 @@ void crtc_bankupdate(void) {
 				}
 			}
 			else {
-				if (crtc.s.reg[CRTCREG_HDISP] == 40) {		// width 40,12,0,1
+				if (crtc.s.width40) {						// width 40,12,0,1
 					if (crtc.s.EXTPALMODE & 0x10) {
 						if (crtc.s.ZPRY & 0x10) {
 							dispmode = SCRN64_320x100x2 |
@@ -154,33 +231,6 @@ void crtc_bankupdate(void) {
 	crtc.e.pal_disp = pal_disp;
 }
 
-void crtc_regupdate(void) {
-
-	UINT	fonty;
-	SINT32	fontyclock;
-
-	crtc.e.pos = crtc.s.reg[CRTCREG_POSL]
-									+ ((crtc.s.reg[CRTCREG_POSH] & 7) << 8);
-
-	fonty = crtc.s.reg[CRTCREG_CHRCY] & 0x1f;
-	if (crtc.s.SCRN_BITS & SCRN_24KHZ) {
-		fonty >>= 1;
-	}
-	fonty += 1;
-	crtc.e.fonty = fonty;
-	crtc.e.yl = (crtc.s.reg[CRTCREG_VDISP] & 0x7f);
-
-	fontyclock = fonty * RASTER_CLOCK;
-	crtc.e.dispclock = fontyclock * crtc.e.yl;
-	// YsIIIが yl==0で disp信号見る…なんで？
-	if (!crtc.e.dispclock) {
-		crtc.e.dispclock = fontyclock;
-	}
-	crtc.e.vsyncstart = fontyclock * ((crtc.s.reg[CRTCREG_VSYNC] & 0x7f) + 1);
-	crtc.e.vpulseclock = (crtc.s.reg[CRTCREG_PULSE] >> 4) * RASTER_CLOCK;
-	crtc.e.vl = fonty * ((crtc.s.reg[CRTCREG_VSIZE] & 0x7f) + 1)
-						+ (crtc.s.reg[CRTCREG_VSIZEA] & 0x1f);
-}
 
 
 // ---- CRTC
@@ -195,9 +245,10 @@ void IOOUTCALL crtc_o(UINT port, REG8 value) {
 		if (crtc.s.regnum < CRTCREG_MAX) {
 			if (crtc.s.reg[crtc.s.regnum] != value) {
 				crtc.s.reg[crtc.s.regnum] = value;
+				crtc_clkupdate();
+				crtc_timingupdate();
 				crtc_bankupdate();
 				makescrn.remakeattr = 1;
-				crtc_regupdate();
 				scrnallflash = 1;
 			}
 		}
@@ -217,7 +268,8 @@ void IOOUTCALL scrn_o(UINT port, REG8 value) {
 //		pal_reset();					// ‚È‚ñ‚Å<E2809A>H
 		scrnallflash = 1;
 		makescrn.palandply = 1;
-		crtc_regupdate();
+		crtc_clkupdate();
+		crtc_timingupdate();
 	}
 	crtc_bankupdate();
 	(void)port;
@@ -418,6 +470,24 @@ REG8 IOINPCALL blackctrl_i(UINT port) {
 }
 
 
+// ----
+
+void crtc_update(void) {
+
+	crtc_clkupdate();
+	crtc_timingupdate();
+	crtc_bankupdate();
+	makescrn.palandply = 1;
+	scrnallflash = 1;
+}
+
+void crtc_setwidth(REG8 width40) {
+
+	crtc.s.width40 = width40;
+	crtc_update();
+}
+
+
 // ----
 
 static void resetpal(void) {
@@ -442,19 +512,19 @@ void crtc_reset(void) {
 	ZeroMemory(&crtc, sizeof(crtc));
 	CopyMemory(crtc.s.rgbp, defrgbp, 4);
 	CopyMemory(crtc.s.reg, defreg, 18);
+	crtc.s.width40 = 1;
 	if (pccore.ROM_TYPE < 3) {
 		resetpal();
 	}
-	if ((pccore.ROM_TYPE >= 2) && (!(pccore.DIP_SW & 1))) {
-		crtc.s.SCRN_BITS = SCRN_200LINE;
-		crtc.s.reg[CRTCREG_CHRCY] = 15;
-	}
+//	IPLが勝手に切り替える筈である
+//	if ((pccore.ROM_TYPE >= 2) && (!(pccore.DIP_SW & 1))) {
+//		crtc.s.SCRN_BITS = SCRN_200LINE;
+//		crtc.s.reg[CRTCREG_CHRCY] = 15;
+//	}
 
 	pal_reset();
-	crtc_bankupdate();
-	crtc_regupdate();
 	makescrn.palandply = 1;
-	scrnallflash = 1;
+	crtc_update();
 }
 
 void crtc_forcesetwidth(REG8 width) {

io/crtc.h

@@ -82,9 +82,11 @@ enum {
 
 
 typedef struct {
-	UINT8	rgbp[4];
 	UINT8	SCRN_BITS;
+	UINT8	width40;
 	UINT8	regnum;
+	UINT8	padding;
+	UINT8	rgbp[4];
 	UINT8	reg[CRTCREG_MAX];
 	UINT8	BLACKPAL;
 	UINT8	EXTPALMODE;
@@ -94,6 +96,11 @@ typedef struct {
 } CRTCSTAT;
 
 typedef struct {
+	SINT32	rasterclock8;
+	UINT	fonty;
+	UINT	yl;
+	SINT32	frameclock;
+
 	UINT8	*gram;				// curvram
 	UINT	updatemask;			// updatemsk
 	UINT8	updatebit;			// curupdt
@@ -102,13 +109,10 @@ typedef struct {
 	UINT8	pal_disp;
 
 	UINT	pos;
-	UINT	fonty;
-	UINT	yl;
 
 	SINT32	dispclock;
 	SINT32	vsyncstart;
 	SINT32	vpulseclock;
-	UINT	vl;
 } CRTCEXT;
 
 typedef struct {
@@ -126,8 +130,10 @@ typedef struct {
 
 // ----
 
-void crtc_bankupdate(void);								// vrambank_patch
-void crtc_regupdate(void);
+void crtc_setwidth(REG8 width40);
+void crtc_update(void);
+// void crtc_bankupdate(void);							// vrambank_patch
+// void crtc_regupdate(void);
 
 void IOOUTCALL crtc_o(UINT port, REG8 value);			// x1_crtc_w
 

io/ctc.c

@@ -74,6 +74,7 @@ static REG8 ctcwork(CTCCH *ch) {
 		if (count <= 0) {
 			count = ch->countmax[3] - ((0 - count) % ch->countmax[3]);
 			intr |= (ch->cmd[3] & 0x80) >> (7 - 3);
+TRACEOUT(("ctc3 !"));
 		}
 		ch->count[3] = count;
 	}
@@ -174,7 +175,7 @@ BRESULT ieitem_ctc(UINT id) {
 				else if (!r) {
 					r = TRUE;
 					intr ^= bit;
-//					TRACEOUT(("ctc int %d %d", ch->num, i));
+					TRACEOUT(("ctc int %d %d", ch->num, i));
 					Z80_INTERRUPT((REG8)(ch->vector + (i << 1)));
 				}
 			}

io/dmac.c

@@ -41,6 +41,7 @@ void dmac_sendready(BRESULT ready) {
 	}
 }
 
+
 BRESULT ieitem_dmac(UINT id) {
 
 	REG8	vect;
@@ -192,10 +193,11 @@ void IOOUTCALL dmac_o(UINT port, REG8 value) {
 			case 6:
 				switch(value) {
 					case 0x83:				// dma disable
-						dma.enable = 0;
+					//	dma.enable = 0;
 						break;
 
 					case 0x87:				// dma enable
+						dma.increment = 0;
 						dma.enable = 1;
 						break;
 
@@ -232,8 +234,9 @@ void IOOUTCALL dmac_o(UINT port, REG8 value) {
 					case 0xc3:				// reset
 											// ローグアライアンス	// ver0.25
 						dma.cmd = 0;
-						dma.enable = 0;
+					//	dma.enable = 0;
 						dma.INT_ENBL = 0;
+						dma.increment = 0;
 						break;
 
 					case 0xc7:						// リセットタイミングA
@@ -247,32 +250,10 @@ void IOOUTCALL dmac_o(UINT port, REG8 value) {
 						dma.BYT_N.w = 0;
 						dma.ENDB_FLG = 0;
 						dma.MACH_FLG = 0;			// 0619
-						dma.enable = 0;
+					//	dma.enable = 0;
 						break;
 
 					case 0xd3:						// コンティニュー
-						if (dma.DMA_STOP) {			// 前回途中でNOT READY
-							dma.DMA_STOP = 0;
-							// ここでインクリメントするのはちょい無理が…
-							switch(dma.WR[1] & 0x30) {
-								case 0x00:
-									dma.CNT_A.w--;
-									break;
-
-								case 0x10:
-									dma.CNT_A.w++;
-									break;
-							}
-							switch(dma.WR[2] & 0x30) {
-								case 0x00:
-									dma.CNT_B.w--;
-									break;
-
-								case 0x10:
-									dma.CNT_B.w++;
-									break;
-							}
-						}
 						dma.BYT_N.w = 0;			// 0619
 						dma.MACH_FLG = 0;			// 0619
 						dma.ENDB_FLG = 0;

io/dmac.h

@@ -19,6 +19,7 @@ typedef union {
 
 typedef struct {
 	UINT8	working;
+	UINT8	increment;
 
 	UINT8	enable;				// DMA_ENBL
 	UINT8	ready;				// DMA_REDY
@@ -37,8 +38,9 @@ typedef struct {
 
 	UINT8	RR_MSK;
 	UINT8	RR;
-	UINT8	DMA_STOP;
+
 	UINT8	dummydat;
+	UINT8	padding[3];
 
 	DMAPAIR	ADR_A;
 	DMAPAIR	ADR_B;

io/fdc.c

@@ -29,6 +29,10 @@ static void setbusy(SINT32 clock) {
 		fdc.s.busy = TRUE;
 		nevent_set(NEVENT_FDC, clock, neitem_fdcbusy, NEVENT_ABSOLUTE);
 	}
+	else {
+		fdc.s.busy = FALSE;
+		nevent_reset(NEVENT_FDC);
+	}
 }
 
 static void setmotor(REG8 drvcmd) {
@@ -240,6 +244,7 @@ static REG8 crccmd(void) {
 
 	track = (fdc.s.c << 1) + fdc.s.h;
 	fdd = fddfile + fdc.s.drv;
+TRACEOUT(("fdd->crc %d %d %d", fdc.s.drv, track, fdc.s.crcnum));
 	stat = fdd->crc(fdd, fdc.s.media, track, fdc.s.crcnum, fdc.s.buffer);
 	if (stat & FDDSTAT_RECNFND) {
 		fdc.s.crcnum = 0;
@@ -249,6 +254,7 @@ static REG8 crccmd(void) {
 		fdc.s.bufdir = FDCDIR_IN;
 		fdc.s.bufsize = 6;
 		fdc.s.rreg = fdc.s.buffer[0];
+		fdc.s.crcnum++;
 	}
 	else {
 		fdc.s.bufdir = FDCDIR_NONE;
@@ -322,9 +328,6 @@ void IOOUTCALL fdc_o(UINT port, REG8 value) {
 			setbusy(20);
 			switch(cmd) {
 				case 0x00:								// リストア
-				//	if (value & 8) {					// LAYDOCK
-				//		setbusy(0);
-				//	}
 					fdc.s.motor = 0x80;					// モーターOn?
 					fdc.s.c = 0;
 					fdc.s.step = 1;
@@ -387,6 +390,7 @@ void IOOUTCALL fdc_o(UINT port, REG8 value) {
 				case 0x0d:								// フォースインタラプト
 					setbusy(0);							// 必要ない？
 //					fdc.s.skip = 0;						// 000330
+					fdc.s.stat = 0;
 					dmac_sendready(FALSE);
 					break;
 
@@ -469,7 +473,7 @@ REG8 IOINPCALL fdc_i(UINT port) {
 			if (!(ret & 0x02)) {
 				dmac_sendready(FALSE);
 			}
-//			TRACEOUT(("ret->%.2x", ret));
+			TRACEOUT(("ret->%.2x", ret));
 			return(ret);
 
 		case 1:									// トラック
@@ -482,7 +486,7 @@ REG8 IOINPCALL fdc_i(UINT port) {
 			if (fdc.s.motor) {
 				if (fdc.s.bufdir == FDCDIR_IN) {
 					fdc.s.data = fdc.s.buffer[fdc.s.bufpos];
-// TRACEOUT(("read %.2x %.2x [%.4x]", fdc.s.data, fdc.s.bufpos, Z80_PC));
+TRACEOUT(("read %.2x - %.2x [%.4x]", fdc.s.bufpos, fdc.s.data, Z80_PC));
 					bufposinc();
 				}
 			}

io/pcg.c

@@ -52,12 +52,16 @@ static UINT nowsyncoffset(UINT *line) {
 	if (corestat.vsync) {
 		clock += corestat.dispclock;
 	}
-	v = clock / RASTER_CLOCK;
-	h = clock - (v * RASTER_CLOCK);
+	clock = clock << 8;
+	v = clock / crtc.e.rasterclock8;
+	h = clock - (v * crtc.e.rasterclock8);
+	if (crtc.s.SCRN_BITS & SCRN_24KHZ) {
+		v = v >> 1;
+	}
 	ret = v / crtc.e.fonty;
 	*line = (v - (ret * crtc.e.fonty)) & 7;
 	ret = (ret * crtc.s.reg[CRTCREG_HDISP]) + crtc.e.pos;
-	ret += (h * crtc.s.reg[CRTCREG_HDISP]) / RASTER_CLOCK;
+	ret += (h * crtc.s.reg[CRTCREG_HDISP]) / crtc.e.rasterclock8;
 	if (ret >= 0x0800) {
 		ret = 0x07ff;		// ƒI<C692>[ƒo<C692>[ƒtƒ<74><C692>[
 	}
@@ -92,17 +96,17 @@ void IOOUTCALL pcg_o(UINT port, REG8 value) {
 
 REG8 IOINPCALL pcg_i(UINT port) {
 
-	BRESULT	ank;
+	UINT	upper;
 	UINT	line;
 	UINT	off;
 	UINT	chr;
 	UINT	knj;
 	UINT	addr;
 
-	ank = ((port & 0xff00) == 0x1400);
+	upper = port & 0x0300;
 	if (crtc.s.SCRN_BITS & SCRN_PCGMODE) {
 		line = port & 0x0f;
-		if (ank) {
+		if (!upper) {
 			off = knj_offset();
 			chr = tram[TRAM_ANK + off];
 			knj = tram[TRAM_KNJ + off];
@@ -135,11 +139,11 @@ REG8 IOINPCALL pcg_i(UINT port) {
 		off = nowsyncoffset(&line);
 		chr = tram[TRAM_ANK + off];
 	}
-	if (ank) {
+	if (!upper) {
 		return(font_ank[(chr << 3) + line]);
 	}
 	else {
-		chr += (port & 0x0300) - 0x100;
+		chr += upper - 0x100;
 		return(pcg.d[(chr << 3) + line]);
 	}
 }

io/ppi.c

@@ -41,28 +41,24 @@ static REG8 getportb(void) {
 
 static void setportc(REG8 dat) {
 
-	REG8	oldc;
-	UINT8	xl;
-
-	oldc = ppi.portc;
-	if (crtc.s.reg[CRTCREG_HDISP] == 40) {
-		oldc |= 0x40;
-	}
-	else {
-		oldc &= ~0x40;
-	}
-	ppi.portc = dat;
+	REG8	modify;
 
+	modify = ppi.portc ^ dat;
 //	cmt_write((REG8)(dat & 1));
-	if ((oldc & 0x20) && (!(dat & 0x20))) {
+	if ((modify & 0x20) && (!(dat & 0x20))) {
 		iocore.s.mode = 1;
 	}
+	if (modify & 0x40) {
+		crtc_setwidth((REG8)(dat & 0x40));
+	}
+#if 0
 	xl = ((dat & 0x40)?40:80);
 	if (crtc.s.reg[CRTCREG_HDISP] != xl) {
 		crtc.s.reg[CRTCREG_HDISP] = (UINT8)xl;
 		crtc_bankupdate();
 		scrnallflash = 1;
 	}
+#endif
 }
 
 
@@ -119,14 +115,7 @@ REG8 IOINPCALL ppi_i(UINT port) {
 			return(getportb());
 
 		case 2:
-#if 1
-			if (crtc.s.reg[CRTCREG_HDISP] == 40) {
-				ppi.portc |= 0x40;
-			}
-			else {
-				ppi.portc &= ~0x40;
-			}
-#endif
+		// mode?
 			return(ppi.portc);
 
 		case 3:

pccore.c

@@ -192,7 +192,7 @@ void neitem_vsync(UINT id) {
 
 // ----
 
-// #define	SINGLESTEPONLY
+#define	SINGLESTEPONLY
 
 void pccore_exec(BRESULT draw) {
 
@@ -202,7 +202,8 @@ void pccore_exec(BRESULT draw) {
 	corestat.drawframe = draw;
 	soundmng_sync();
 
-	frameclock = 266 * RASTER_CLOCK * pccore.multiple / 2;
+	timing_setrate(crtc.e.frameclock);
+	frameclock = crtc.e.frameclock * pccore.multiple / 2;
 	dispclock = min(frameclock, crtc.e.dispclock);
 	corestat.dispclock = dispclock;
 	corestat.syncclock = frameclock - dispclock;
@@ -215,6 +216,7 @@ void pccore_exec(BRESULT draw) {
 		}
 #else
 		while(CPU_REMCLOCK > 0) {
+		//	TRACEOUT(("%.4x", Z80_PC));
 #if defined(TRACE) && IPTRACE
 			treip[trpos & (IPTRACE - 1)] = Z80_PC;
 			trpos++;

pccore.h

@@ -39,10 +39,6 @@ typedef struct {
 	UINT8	soundrenewal;
 } CORESTAT;
 
-enum {
-	RASTER_CLOCK		= 250
-};
-
 enum {
 	DIPSW_RESOLUTE		= 0x01,
 	DIPSW_BOOTMEDIA		= 0x04

statsave.c

@@ -760,8 +760,7 @@ const SFENTRY	*tblterm;
 	statflag_close(sffh);
 
 	memio_update();
-	crtc_bankupdate();
-	crtc_regupdate();
+	crtc_update();
 	sndboard_update();
 
 	pal_reset();

timing.c

@@ -1,14 +1,17 @@
 #include	"compiler.h"
-#include	"timing.h"
+#include	"pccore.h"
+#include	"diskdrv.h"
 #include	"fdd_mtr.h"
+#include	"timing.h"
 
 
-static const UINT8 tick3[3] = {16, 17, 17};
+#define	MSSHIFT		16
 
 typedef struct {
 	UINT32	tick;
+	UINT32	msstep;
 	UINT	cnt;
-	UINT	fraction;
+	UINT32	fraction;
 } TIMING;
 
 static	TIMING	timing;
@@ -21,6 +24,12 @@ void timing_reset(void) {
 	timing.fraction = 0;
 }
 
+void timing_setrate(UINT32 clock) {
+
+//	timing.msstep = (1 << MSSHIFT) / (clock / 4000);
+	timing.msstep = (4000 << MSSHIFT) / clock;
+}
+
 void timing_setcount(UINT value) {
 
 	timing.cnt = value;
@@ -30,33 +39,20 @@ UINT timing_getcount(void) {
 
 	UINT32	ticknow;
 	UINT32	span;
-	UINT32	steps;
+	UINT32	fraction;
 
 	ticknow = GETTICK();
 	span = ticknow - timing.tick;
-#if 1
-	if (span < tick3[timing.fraction]) {
-		ticknow = GETTICK();
-		span = ticknow - timing.tick;
-	}
-#endif
 	if (span) {
-		FDDMTR_CALLBACK(ticknow);
-		if (span >= 50) {
-			steps = span / 50;
-			span %= 50;
-			timing.tick += (steps * 50);
-			timing.cnt += steps * 3;
-		}
-		while(span >= tick3[timing.fraction]) {
-			span -= tick3[timing.fraction];
-			timing.tick += tick3[timing.fraction];
-			timing.cnt++;
-			timing.fraction++;
-			if (timing.fraction >= 3) {
-				timing.fraction = 0;
-			}
+		timing.tick = ticknow;
+		fddmtr_callback(ticknow);
+
+		if (span >= 1000) {
+			span = 1000;
 		}
+		fraction = timing.fraction + (span * timing.msstep);
+		timing.cnt += fraction >> MSSHIFT;
+		timing.fraction = fraction & ((1 << MSSHIFT) - 1);
 	}
 	return(timing.cnt);
 }

timing.h

@@ -4,6 +4,7 @@ extern "C" {
 #endif
 
 void timing_reset(void);
+void timing_setrate(UINT32 clock);
 void timing_setcount(UINT value);
 UINT timing_getcount(void);
 

vram/makescrn.c

@@ -168,9 +168,9 @@ static void changecrtc(void) {
 
 	makescrn.vramtop = crtc.e.pos;
 
-	scrnxmax = (crtc.s.reg[CRTCREG_HDISP] <= 40)?40:80;
+	scrnxmax = (crtc.s.width40)?40:80;
 	scrnymax = 200;
-	if (crtc.s.reg[CRTCREG_HDISP] <= 40) {
+	if (crtc.s.width40) {
 		if (lastdisp & SCRN_DRAW4096) {
 			widthmode = SCRNWIDTHMODE_4096;
 		}

z80c/z80c.c

@@ -124,12 +124,6 @@ void CPUCALL z80c_reset(void) {
 	R_Z80R = rand_get();
 }
 
-REG8 CPUCALL z80c_ableinterrupt(void) {
-
-	return((Z80_IFF & ((1 << IFF_IFLAG) | (1 << IFF_IRQ) | (1 << IFF_NMI)))
-																		?0:1);
-}
-
 void CPUCALL z80c_interrupt(REG8 vect) {
 
 	REG16	pc;
@@ -138,7 +132,7 @@ void CPUCALL z80c_interrupt(REG8 vect) {
 		Z80_IFF ^= (1 << IFF_HALT);
 		R_Z80PC++;
 	}
-	Z80_IFF |= (1 << IFF_IRQ) | (1 << IFF_IFLAG);
+	Z80_IFF |= (1 << IFF_IFLAG);
 	switch(R_Z80IM) {
 		case 0:
 			if ((vect != 0xdd) && (vect != 0xed) && (vect != 0xfd)) {

z80c/z80c.mcr

@@ -573,8 +573,7 @@
 			Z80_IFF = (UINT8)(iff & (~(1 << IFF_IFLAG)));				\
 			rem = CPU_REMCLOCK - 1;										\
 			if ((rem < 0) ||											\
-				((!(iff & ((1 << IFF_IRQ) | (1 << IFF_NMI)))) &&		\
-					(CPU_REQIRQ != 0))) {								\
+				((!(iff & (1 << IFF_NMI))) && (CPU_REQIRQ != 0))) {		\
 				CPU_BASECLOCK -= rem;									\
 				CPU_REMCLOCK = 1;										\
 			}															\

z80c/z80c_s.mcr

@@ -38,7 +38,7 @@
 	}
 
 #define	MCR_RETN {														\
-		Z80_IFF &= ~((1 << IFF_NMI) | (1 << IFF_IRQ));					\
+		Z80_IFF &= ~(1 << IFF_NMI);										\
 		MCR_RET															\
 	}
 
@@ -62,15 +62,11 @@
 	}
 
 #define MCR_RETI {														\
-		REG8 iff;														\
-		iff = Z80_IFF;													\
-		if (iff & (1 << IFF_IRQ)) {										\
-			Z80_IFF = (UINT8)(iff & (~(1 << IFF_IRQ)));					\
-			if ((!(iff & ((1 << IFF_IFLAG) | (1 << IFF_NMI)))) &&		\
-				(CPU_REQIRQ != 0)) {									\
-				CPU_BASECLOCK -= CPU_REMCLOCK;							\
-				CPU_REMCLOCK = 0;										\
-			}															\
+		CPU_IRQ = CPU_IRQ & (CPU_IRQ - 1);								\
+		if ((!(Z80_IFF & ((1 << IFF_IFLAG) | (1 << IFF_NMI)))) &&		\
+			(CPU_REQIRQ != 0)) {										\
+			CPU_BASECLOCK -= CPU_REMCLOCK;								\
+			CPU_REMCLOCK = 0;											\
 		}																\
 		MCR_RET															\
 	}

z80c/z80core.h

@@ -22,9 +22,8 @@ enum {
 
 enum {
 	IFF_IFLAG	= 0,
-	IFF_IRQ		= 1,
-	IFF_NMI		= 2,
-	IFF_HALT	= 3
+	IFF_NMI		= 1,
+	IFF_HALT	= 2
 };
 
 
@@ -86,7 +85,8 @@ typedef struct {
 	UINT8	r2;
 	UINT8	iff;
 	UINT8	padding[3];
-	UINT	reqirq;
+	UINT32	irq;
+	UINT32	reqirq;
 
 	SINT32	remainclock;
 	SINT32	baseclock;
@@ -115,7 +115,6 @@ extern	Z80CORE		z80core;
 void CPUCALL z80c_initialize(void);
 void CPUCALL z80c_reset(void);
 void CPUCALL z80c_maketable(void);
-REG8 CPUCALL z80c_ableinterrupt(void);
 void CPUCALL z80c_interrupt(REG8 irq);
 void CPUCALL z80c_nonmaskedinterrupt(void);
 void CPUCALL z80c_execute(void);
@@ -155,16 +154,19 @@ void CPUCALL z80c_step(void);
 #define Z80_R2			z80core.s.r2
 #define	Z80_IFF			z80core.s.iff
 
+#define	CPU_IRQ			z80core.s.irq
 #define	CPU_REQIRQ		z80core.s.reqirq
 
 #define	CPU_REMCLOCK	z80core.s.remainclock
 #define	CPU_BASECLOCK	z80core.s.baseclock
 #define	CPU_CLOCK		z80core.s.clock
 
+#define	Z80_DI			((z80core.s.iff & 3) != 0)
+#define	Z80_EI			((z80core.s.iff & 3) == 0)
+
 #define	Z80_INITIALIZE			z80c_initialize
 #define	Z80_DEINITIALIZE()		
 #define	Z80_RESET				z80c_reset
-#define	Z80_ABLEINTERRUPT		z80c_ableinterrupt
 #define	Z80_INTERRUPT(a)		z80c_interrupt(a)
 #define	Z80_NMI					z80c_nonmaskedinterrupt
 #define	Z80_EXECUTE				z80c_execute

z80c/z80dmap.c

@@ -32,12 +32,21 @@ void z80dmap(void) {
 	}
 
 	do {		// dma_lp
+		if (dma.increment) {
+			if (!(flag1 & 0x20)) {
+				*off1 += (flag1 & 0x10)?1:-1;
+			}
+			if (!(flag2 & 0x20)) {
+				*off2 += (flag2 & 0x10)?1:-1;
+			}
+		}
+		dma.increment = 1;
 		addr = *off1;
 		if (flag1 & 8) {
 			dat = iocore_inp(addr);
 		}
 		else {
-			dat = mem_read8(addr);
+			dat = z80mem_read8(addr);
 		}
 		if (dma.cmd & 1) {
 			addr = *off2;
@@ -45,7 +54,8 @@ void z80dmap(void) {
 				iocore_out(addr, dat);
 			}
 			else {
-				mem_write8(addr, dat);
+				TRACEOUT(("dma->%.4x", addr));
+				z80mem_write8(addr, dat);
 			}
 		}
 		if (dma.cmd & 2) {
@@ -54,21 +64,7 @@ void z80dmap(void) {
 				dma.MACH_FLG = 1;
 			}
 		}
-		if (dma.mode != 1) {
-			dma.DMA_STOP = (dma.WR[5] ^ dma.ready) & 8;
-			if (dma.DMA_STOP) {
-				dma.working = FALSE;			// 既にセットされてる筈だが
-				goto dma_stop;
-			}
-		}
-		if (!(flag1 & 0x20)) {
-			*off1 += (flag1 & 0x10)?1:-1;
-		}
-		if (!(flag2 & 0x20)) {
-			*off2 += (flag2 & 0x10)?1:-1;
-		}
 
-dma_stop:
 		dma.BYT_N.w++;
 		if (dma.BYT_N.w == 0) {
 			dma.working = FALSE;
@@ -81,7 +77,7 @@ dma_stop:
 			goto intr;
 		}
 		if (!dma.working) {
-			goto intr;
+			return;
 		}
 	} while(dma.mode);
 	return;

z80c/z80mem.h

@@ -14,8 +14,8 @@ void MEMCALL mem_write8(UINT addr, REG8 value);
 void MEMCALL mem_write16(UINT addr, REG16 value);
 SINT MEMCALL mem_read8s(UINT addr);
 
-#define	z80mem_read8(a)		mem_read8(a)
-#define	z80mem_write8(a)	mem_write8(a)
+#define	z80mem_read8(a)			mem_read8(a)
+#define	z80mem_write8(a, v)		mem_write8(a, v)
 
 #ifdef __cplusplus
 }

z80x/z80core.h

@@ -18,9 +18,8 @@ enum {
 
 enum {
 	IFF_IFLAG	= 0,
-	IFF_IRQ		= 1,
-	IFF_NMI		= 2,
-	IFF_HALT	= 3
+	IFF_NMI		= 1,
+	IFF_HALT	= 2
 };
 
 
@@ -82,7 +81,8 @@ typedef struct {
 	UINT8	r2;
 	UINT8	iff;				// 4byte align
 	UINT8	padding[3];
-	UINT	reqirq;
+	UINT32	irq;
+	UINT32	reqirq;
 
 	SINT32	remainclock;
 	SINT32	baseclock;
@@ -111,7 +111,6 @@ extern	Z80CORE		z80core;
 void z80x_initialize(void);
 void z80x_reset(void);
 void z80x_maketable(void);
-REG8 z80x_ableinterrupt(void);
 void __fastcall z80x_interrupt(REG8 irq);
 void z80x_nonmaskedinterrupt(void);
 void z80x_execute(void);
@@ -151,16 +150,19 @@ void z80x_step(void);
 #define Z80_R2			z80core.s.r2
 #define	Z80_IFF			z80core.s.iff
 
+#define	CPU_IRQ			z80core.s.irq
 #define	CPU_REQIRQ		z80core.s.reqirq
 
 #define	CPU_REMCLOCK	z80core.s.remainclock
 #define	CPU_BASECLOCK	z80core.s.baseclock
 #define	CPU_CLOCK		z80core.s.clock
 
+#define	Z80_DI			((z80core.s.iff & 3) != 0)
+#define	Z80_EI			((z80core.s.iff & 3) == 0)
+
 #define	Z80_INITIALIZE			z80x_initialize
 #define	Z80_DEINITIALIZE()		
 #define	Z80_RESET				z80x_reset
-#define	Z80_ABLEINTERRUPT		z80x_ableinterrupt
 #define	Z80_INTERRUPT(a)		z80x_interrupt(a)
 #define	Z80_NMI					z80x_nonmaskedinterrupt
 #define	Z80_EXECUTE				z80x_execute

z80x/z80dmap.c

@@ -32,6 +32,15 @@ void z80dmap(void) {
 	}
 
 	do {		// dma_lp
+		if (dma.increment) {
+			if (!(flag1 & 0x20)) {
+				*off1 += (flag1 & 0x10)?1:-1;
+			}
+			if (!(flag2 & 0x20)) {
+				*off2 += (flag2 & 0x10)?1:-1;
+			}
+		}
+		dma.increment = 1;
 		addr = *off1;
 		if (flag1 & 8) {
 			dat = iocore_inp(addr);
@@ -45,6 +54,7 @@ void z80dmap(void) {
 				iocore_out(addr, dat);
 			}
 			else {
+				TRACEOUT(("dma->%.4x", addr));
 				z80mem_write8(addr, dat);
 			}
 		}
@@ -54,21 +64,7 @@ void z80dmap(void) {
 				dma.MACH_FLG = 1;
 			}
 		}
-		if (dma.mode != 1) {
-			dma.DMA_STOP = (dma.WR[5] ^ dma.ready) & 8;
-			if (dma.DMA_STOP) {
-				dma.working = FALSE;			// 既にセットされてる筈だが
-				goto dma_stop;
-			}
-		}
-		if (!(flag1 & 0x20)) {
-			*off1 += (flag1 & 0x10)?1:-1;
-		}
-		if (!(flag2 & 0x20)) {
-			*off2 += (flag2 & 0x10)?1:-1;
-		}
 
-dma_stop:
 		dma.BYT_N.w++;
 		if (dma.BYT_N.w == 0) {
 			dma.working = FALSE;
@@ -81,7 +77,7 @@ dma_stop:
 			goto intr;
 		}
 		if (!dma.working) {
-			goto intr;
+			return;
 		}
 	} while(dma.mode);
 	return;

z80x/z80x.inc

@@ -37,6 +37,7 @@
 .r2				resb	1
 .iff			resw	1
 				resw	1
+.irq			resd	1
 .reqirq			resd	1
 .remainclock	resd	1
 .baseclock		resd	1
@@ -52,9 +53,8 @@ N_FLAG		equ		0x02
 C_FLAG		equ		0x01
 
 IFF_IFLAG	equ		0
-IFF_IRQ		equ		1
-IFF_NMI		equ		2
-IFF_HALT	equ		3
+IFF_NMI		equ		1
+IFF_HALT	equ		2
 
 R_Z80A		equ		reg8_t.a
 R_Z80F		equ		reg8_t.f
@@ -84,4 +84,6 @@ R_Z80IM		equ		z80core_t.im
 R_Z80R		equ		z80core_t.r1
 R_Z80R2		equ		z80core_t.r2
 R_Z80IFF	equ		z80core_t.iff
+R_Z80IRQ	equ		z80core_t.irq
+R_Z80REQIRQ	equ		z80core_t.reqirq
 

z80x/z80x_if.x86

@@ -21,12 +21,6 @@ section .text
 	extern	_z80dmap
 	extern	_dma
 
-				align	16
-_z80x_ableinterrupt:
-				test	byte [_z80core + R_Z80IFF], ((1 << IFF_IFLAG) | (1 << IFF_IRQ) | (1 << IFF_NMI))
-				setz	al
-				ret
-
 
 				align	16
 @z80x_interrupt@4:
@@ -36,7 +30,7 @@ _z80x_ableinterrupt:
 				je		short .setintr
 				inc		word [edx + R_Z80PC]
 				and		al, ~(1 << IFF_HALT)
-.setintr:		or		al, ((1 << IFF_IRQ) | (1 << IFF_IFLAG))
+.setintr:		or		al, (1 << IFF_IFLAG)
 				cmp		byte [edx + R_Z80IM], 1
 				mov		[edx + R_Z80IFF], al
 				je		short .im1

z80x/z80x_mn.x86

@@ -150,9 +150,9 @@ _ei:			mov		al, [edi + R_Z80IFF]
 				and		al, ~(1 << IFF_IFLAG)
 				mov		edx, [edi + z80core_t.remainclock]
 				mov		[edi + R_Z80IFF], al
-				test	al, ((1 << IFF_IRQ) | (1 << IFF_NMI))
+				test	al, (1 << IFF_NMI)
 				jne		short .nextop
-				cmp		dword [edi + z80core_t.reqirq], byte 0
+				cmp		dword [edi + R_Z80REQIRQ], byte 0
 				jne		short .eventexit
 .nextop:		cmp		edx, byte 1
 				jge		short .ed

z80x/z80x_sb.x86

@@ -34,23 +34,24 @@ im_2:			mov		byte [edi + R_Z80IM], 2
 
 
 				align	16
-_retn:			and		byte [edi + R_Z80IFF], ~((1 << IFF_NMI) | (1 << IFF_IRQ))
+_retn:			and		byte [edi + R_Z80IFF], ~(1 << IFF_NMI)
 				MRET
 
 				align	16
-_reti:			mov		dl, [edi + R_Z80IFF]
-				test	dl, ((1 << IFF_IFLAG) | (1 << IFF_NMI))
+_reti:			mov		eax, [edi + R_Z80IRQ]
+				lea		edx, [eax - 1]
+				and		eax, edx
+				test	byte [edi + R_Z80IFF], ((1 << IFF_IFLAG) | (1 << IFF_NMI))
+				mov		[edi + R_Z80IRQ], eax
 				jne		short .mn
-				cmp		dword [edi + z80core_t.reqirq], byte 0
+				cmp		dword [edi + R_Z80REQIRQ], byte 0
 				je		short .mn
 				mov		eax, [edi + z80core_t.remainclock]
 				cmp		eax, byte 0
 				jle		short .mn
 				sub		[edi + z80core_t.remainclock], eax
 				sub		[edi + z80core_t.baseclock], eax
-.mn:			and		dl, ~(1 << IFF_IRQ)
-				mov		[edi + R_Z80IFF], dl
-				MRET
+.mn:			MRET
 
 				align	16
 adc_hl_bc:		ADCR16	R_Z80BC