LIEF/doc/sphinx/extended/disassembler/cpp/arch/riscv.md

{fa}solid fa-microchip RISC-V

Instruction

.. doxygenclass:: LIEF::assembly::riscv::Instruction

Opcodes

See LIEF::assembly::riscv::OPCODE in include/asm/riscv/opcodes.hpp

Operands

.. doxygenclass:: LIEF::assembly::riscv::Operand

Immediate

.. doxygenclass:: LIEF::assembly::riscv::operands::Immediate

Register

.. doxygenclass:: LIEF::assembly::riscv::operands::Register

Memory

.. doxygenclass:: LIEF::assembly::riscv::operands::Memory

PCRelative

.. doxygenclass:: LIEF::assembly::riscv::operands::PCRelative