mirror of
https://github.com/mupen64plus-ae/mupen64plus-rsp-cxd4.git
synced 2024-11-23 13:40:01 +00:00
new scalar load/store pseudo-op-codes if RS == 0
This commit is contained in:
unknown
parent
da3cbab9bb
commit
54d47f9ea2
208
su.h
208
su.h
@ -376,9 +376,7 @@ static void LB(void) /* 100000 sssss ttttt iiiiiiiiiiiiiiii */
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addr = BES(SR[inst.I.rs] + offset) & 0x00000FFF;
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SR[inst.I.rt] = (signed char)(RSP.DMEM[addr]);
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#if (0)
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SR[0] = 0x00000000; /* if (rt == 0), then NOP is called, not LB. */
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#endif
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SR[0] = 0x00000000;
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return;
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}
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static void LH(void) /* 100001 sssss ttttt iiiiiiiiiiiiiiii */
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@ -388,11 +386,6 @@ static void LH(void) /* 100001 sssss ttttt iiiiiiiiiiiiiiii */
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const signed int offset = (signed short)(inst.I.imm);
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addr = (SR[inst.I.rs] + offset) & 0x00000FFF;
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#if (0)
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SR_B(rt, 2) = RSP.DMEM[BES(addr)];
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addr = (addr + 0x001) & 0xFFF;
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SR_B(rt, 3) = RSP.DMEM[BES(addr)];
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#else
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if (addr%4 == 0x003)
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{
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SR_B(rt, 2) = RSP.DMEM[addr - BES(0x000)];
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@ -401,11 +394,8 @@ static void LH(void) /* 100001 sssss ttttt iiiiiiiiiiiiiiii */
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}
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else
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SR[rt] = *(short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1));
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#endif
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SR[rt] = (signed short)(SR[rt]);
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#if (0)
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SR[0] = 0x00000000; /* if (rt == 0), then NOP is called, not LH. */
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#endif
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SR[0] = 0x00000000;
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return;
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}
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extern void ULW(int rd, unsigned long addr);
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@ -422,9 +412,7 @@ static void LW(void) /* 100011 sssss ttttt iiiiiiiiiiiiiiii */
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return;
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}
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SR[rt] = *(long *)(RSP.DMEM + addr);
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#if (0)
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SR[0] = 0x00000000; /* if (rt == 0), then NOP is called, not LW. */
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#endif
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SR[0] = 0x00000000;
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return;
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}
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static void LBU(void) /* 100100 sssss ttttt iiiiiiiiiiiiiiii */
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@ -434,9 +422,7 @@ static void LBU(void) /* 100100 sssss ttttt iiiiiiiiiiiiiiii */
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addr = BES(SR[inst.I.rs] + offset) & 0x00000FFF;
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SR[inst.I.rt] = (unsigned char)(RSP.DMEM[addr]);
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#if (0)
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SR[0] = 0x00000000; /* if (rt == 0), then NOP is called, not LBU. */
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#endif
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SR[0] = 0x00000000;
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return;
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}
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static void LHU(void) /* 100101 sssss ttttt iiiiiiiiiiiiiiii */
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@ -446,11 +432,6 @@ static void LHU(void) /* 100101 sssss ttttt iiiiiiiiiiiiiiii */
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const signed int offset = (signed short)(inst.I.imm);
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addr = (SR[inst.I.rs] + offset) & 0x00000FFF;
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#if (0)
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SR_B(rt, 2) = RSP.DMEM[BES(addr)];
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addr = (addr + 0x001) & 0xFFF;
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SR_B(rt, 3) = RSP.DMEM[BES(addr)];
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#else
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if (addr%4 == 0x003)
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{
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SR[rt] = RSP.DMEM[addr - BES(0x000)] << 8;
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@ -458,12 +439,8 @@ static void LHU(void) /* 100101 sssss ttttt iiiiiiiiiiiiiiii */
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SR[rt] |= RSP.DMEM[addr + BES(0x000)];
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return;
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}
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SR[rt] = *(short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1));
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#endif
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SR[rt] = (unsigned short)(SR[rt]);
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#if (0)
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SR[0] = 0x00000000; /* if (rt == 0), then NOP is called, not LHU. */
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#endif
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SR[rt] = *(unsigned short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1));
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SR[0] = 0x00000000;
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return;
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}
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static void SB(void) /* 101000 sssss ttttt iiiiiiiiiiiiiiii */
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@ -482,11 +459,6 @@ static void SH(void) /* 101001 sssss ttttt iiiiiiiiiiiiiiii */
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const signed int offset = (signed short)(inst.I.imm);
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addr = (SR[inst.I.rs] + offset) & 0x00000FFF;
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#if (0)
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RSP.DMEM[BES(addr)] = SR_B(rt, 2);
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addr = (addr + 0x001) & 0xFFF;
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RSP.DMEM[BES(addr)] = SR_B(rt, 3);
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#else
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if (addr%4 == 0x003)
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{
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RSP.DMEM[addr - BES(0x000)] = SR_B(rt, 2);
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@ -495,7 +467,6 @@ static void SH(void) /* 101001 sssss ttttt iiiiiiiiiiiiiiii */
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return;
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}
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*(short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1)) = (short)(SR[rt]);
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#endif
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return;
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}
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extern void USW(int rs, unsigned long addr);
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@ -1099,6 +1070,10 @@ static void SLV(void)
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}
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static void SDV(void)
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{
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#if (0)
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LS_Group_I(1, 8);
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return;
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#else
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register unsigned long addr;
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const int vt = inst.R.rt;
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const int e = inst.R.sa >> 1;
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@ -1179,6 +1154,7 @@ static void SDV(void)
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*(short *)(RSP.DMEM + addr + 0x005) = VR_S(vt, e+0x6);
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return;
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}
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#endif
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}
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/*
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@ -2155,6 +2131,120 @@ static void LZI(void)
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SR[0] = 0x00000000;
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return;
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}
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static void LBA(void)
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{ /* "Load Byte from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const signed int offset = (signed short)(inst.I.imm);
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addr = BES(0x00000000 + offset) & 0x00000FFF;
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SR[inst.I.rt] = (signed char)(RSP.DMEM[addr]);
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SR[0] = 0x00000000;
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return;
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}
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static void LHA(void)
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{ /* "Load Halfword from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const int rt = inst.I.rt;
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const signed int offset = (signed short)(inst.I.imm);
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addr = (0x00000000 + offset) & 0x00000FFF;
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if (addr%4 == 0x003)
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{
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SR_B(rt, 2) = RSP.DMEM[addr - BES(0x000)];
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addr = (addr + 0x001) & 0xFFF;
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SR_B(rt, 3) = RSP.DMEM[addr + BES(0x000)];
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}
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else
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SR[rt] = *(short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1));
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SR[rt] = (signed short)(SR[rt]);
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SR[0] = 0x00000000;
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return;
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}
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static void LWA(void)
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{ /* "Load Word from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const int rt = inst.I.rt;
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const signed int offset = (signed short)(inst.I.imm);
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addr = (0x00000000 + offset) & 0x00000FFF;
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if (addr & 0x00000003)
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{
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ULW(rt, addr); /* Address Error exception: RSP bypass MIPS pseudo-op */
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return;
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}
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SR[rt] = *(long *)(RSP.DMEM + addr);
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SR[0] = 0x00000000;
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return;
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}
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static void LBUA(void)
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{ /* "Load Byte Unsigned from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const signed int offset = (signed short)(inst.I.imm);
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addr = BES(0x00000000 + offset) & 0x00000FFF;
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SR[inst.I.rt] = (unsigned char)(RSP.DMEM[addr]);
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SR[0] = 0x00000000;
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return;
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}
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static void LHUA(void)
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{ /* "Load Halfword Unsigned from Absolute Address" (unofficial...) */
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register unsigned long addr;
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const int rt = inst.I.rt;
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const signed int offset = (signed short)(inst.I.imm);
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addr = (0x00000000 + offset) & 0x00000FFF;
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if (addr%4 == 0x003)
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{
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SR[rt] = RSP.DMEM[addr - BES(0x000)] << 8;
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addr = (addr + 0x001) & 0xFFF;
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SR[rt] |= RSP.DMEM[addr + BES(0x000)];
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return;
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}
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SR[rt] = *(unsigned short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1));
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SR[0] = 0x00000000;
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return;
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}
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static void SBA(void)
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{ /* "Store Byte from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const signed int offset = (signed short)(inst.I.imm);
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addr = BES(0x00000000 + offset) & 0x00000FFF;
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RSP.DMEM[addr] = (unsigned char)(SR[inst.I.rt]);
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return;
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}
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static void SHA(void)
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{ /* "Store Halfword from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const int rt = inst.I.rt;
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const signed int offset = (signed short)(inst.I.imm);
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addr = (0x00000000 + offset) & 0x00000FFF;
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if (addr%4 == 0x003)
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{
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RSP.DMEM[addr - BES(0x000)] = SR_B(rt, 2);
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addr = (addr + 0x001) & 0xFFF;
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RSP.DMEM[addr + BES(0x000)] = SR_B(rt, 3);
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return;
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}
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*(short *)(RSP.DMEM + addr - HES(0x000)*(addr%4 - 1)) = (short)(SR[rt]);
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return;
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}
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static void SWA(void)
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{ /* "Store Word from Absolute Address" (unofficial, created by me) */
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register unsigned long addr;
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const int rt = inst.I.rt;
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const signed int offset = (signed short)(inst.I.imm);
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addr = (0x00000000 + offset) & 0x00000FFF;
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if (addr & 0x00000003)
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{
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USW(rt, addr); /* Address Error exception: RSP bypass MIPS pseudo-op */
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return;
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}
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*(long *)(RSP.DMEM + addr) = SR[rt];
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return;
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}
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static void (*EX_SCALAR[64][64])(void) = {
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{ /* SPECIAL */
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@ -2481,21 +2571,21 @@ static void (*EX_SCALAR[64][64])(void) = {
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res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S
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},
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{ /* Load Byte */
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NOP ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LBA ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LB ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LB ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LB ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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NOP ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LBA ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LB ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LB ,LB ,LB ,LB ,LB ,LB ,LB ,LB ,
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LB ,LB ,LB ,LB ,LB ,LB ,LB ,LB
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},
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{ /* Load Halfword */
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NOP ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LHA ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LH ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LH ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LH ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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NOP ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LHA ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LH ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LH ,LH ,LH ,LH ,LH ,LH ,LH ,LH ,
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LH ,LH ,LH ,LH ,LH ,LH ,LH ,LH
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@ -2511,31 +2601,31 @@ static void (*EX_SCALAR[64][64])(void) = {
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res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S
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},
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{ /* Load Word */
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NOP ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LWA ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LW ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LW ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LW ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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NOP ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LWA ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LW ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LW ,LW ,LW ,LW ,LW ,LW ,LW ,LW ,
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LW ,LW ,LW ,LW ,LW ,LW ,LW ,LW
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},
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{ /* Load Byte Unsigned */
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NOP ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBUA ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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NOP ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBUA ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,
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LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU ,LBU
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},
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{ /* Load Halfword Unsigned */
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NOP ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHUA ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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NOP ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHUA ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,
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LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU ,LHU
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@ -2561,21 +2651,21 @@ static void (*EX_SCALAR[64][64])(void) = {
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res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S
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},
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{ /* Store Byte */
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SBA ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SBA ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB ,
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SB ,SB ,SB ,SB ,SB ,SB ,SB ,SB
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},
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{ /* Store Halfword */
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SHA ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SHA ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH ,
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SH ,SH ,SH ,SH ,SH ,SH ,SH ,SH
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@ -2591,11 +2681,11 @@ static void (*EX_SCALAR[64][64])(void) = {
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res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S ,res_S
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},
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{ /* Store Word */
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SWA ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SWA ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW ,
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SW ,SW ,SW ,SW ,SW ,SW ,SW ,SW
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@ -2844,18 +2934,18 @@ const int sub_op_table[64] = {
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OFF_OPCODE,
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OFF_OPCODE,
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OFF_OPCODE,
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OFF_RT, /* LB */
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OFF_RT, /* LH */
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OFF_RS, /* LB */
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OFF_RS, /* LH */
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OFF_OPCODE,
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OFF_RT, /* LW */
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OFF_RT, /* LBU */
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OFF_RT, /* LHU */
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OFF_RS, /* LW */
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OFF_RS, /* LBU */
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OFF_RS, /* LHU */
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OFF_OPCODE,
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OFF_OPCODE,
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OFF_OPCODE, /* SB */
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OFF_OPCODE, /* SH */
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OFF_RS, /* SB */
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OFF_RS, /* SH */
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OFF_OPCODE,
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OFF_OPCODE, /* SW */
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OFF_RS, /* SW */
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OFF_OPCODE,
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OFF_OPCODE,
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OFF_OPCODE,
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