mupen64plus-ae/mupen64plus-rsp-cxd4
1
0
Fork 0
mirror of https://github.com/mupen64plus-ae/mupen64plus-rsp-cxd4.git synced 2024-11-23 13:40:01 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

optimized LWC2 and SWC2 offset decoding

Browse Source
This commit is contained in:
unknown 2015-02-18 22:01:19 -05:00
parent c7c7f9c54d
commit c40a4eff31
2 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
su.c
View File

@ -1574,7 +1574,7 @@ EX:
#endif
switch (op)
{
signed int offset;
s16 offset;
register u32 addr;
case 000: /* SPECIAL */
@ -1906,14 +1906,24 @@ EX:
CONTINUE;
case 062: /* LWC2 */
element = (inst & 0x000007FF) >> 7;
offset = (signed)(inst);
offset = SE(offset, 6);
offset = (s16)(inst);
#ifdef ARCH_MIN_SSE2
offset <<= 5 + 4; /* safe on x86, skips 5-bit rd, 4-bit element */
offset >>= 5 + 4;
#else
offset = SE(offset, 6); /* sign-extended seven-bit offset */
#endif
LWC2[rd](rt, element, offset, base);
CONTINUE;
case 072: /* SWC2 */
element = (inst & 0x000007FF) >> 7;
offset = (signed)(inst);
offset = SE(offset, 6);
offset = (s16)(inst);
#ifdef ARCH_MIN_SSE2
offset <<= 5 + 4; /* safe on x86, skips 5-bit rd, 4-bit element */
offset >>= 5 + 4;
#else
offset = SE(offset, 6); /* sign-extended seven-bit offset */
#endif
SWC2[rd](rt, element, offset, base);
CONTINUE;
default:

2
su.h
View File

@ -103,6 +103,8 @@ extern void set_PC(unsigned int address);
#define SR_B(s, i) (*(pi8)(((pi8)(SR + s)) + BES(i)))
#define SR_S(s, i) (*(pi16)(((pi8)(SR + s)) + HES(i)))
/* (-(x & (1 << b)) | (x)) */
#define SE(x, b) (-(x & (1 << b)) | (x & ~(~0 << b)))
#define ZE(x, b) (+(x & (1 << b)) | (x & ~(~0 << b)))