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Hook up COP0.
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parent
b27e0eebcc
commit
5cb32cd39b
70
rsp_jit.cpp
70
rsp_jit.cpp
@ -500,8 +500,16 @@ void CPU::jit_handle_delay_slot(jit_state_t *_jit, const InstructionInfo &last_i
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}
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}
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void CPU::jit_exit(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_info, ReturnMode mode, bool first_instruction)
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void CPU::jit_exit(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_info,
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ReturnMode mode, bool first_instruction)
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{
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jit_movi(JIT_REGISTER_MODE, mode);
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jit_exit_dynamic(_jit, pc, last_info, first_instruction);
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}
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void CPU::jit_exit_dynamic(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_info, bool first_instruction)
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{
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// We must not touch REGISTER_MODE / TMP1 here, fortunately we don't need to.
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if (first_instruction)
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{
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// Need to consider that we need to move delay slot to PC.
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@ -511,7 +519,6 @@ void CPU::jit_exit(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_i
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// Common case.
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// Immediately exit.
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jit_movi(JIT_REGISTER_MODE, mode);
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jit_movi(JIT_REGISTER_NEXT_PC, (pc + 4) & 0xffcu);
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jit_patch_abs(jit_jmpi(), thunks.return_thunk);
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@ -559,7 +566,6 @@ void CPU::jit_exit(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_i
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jit_patch(to_end);
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}
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jit_movi(JIT_REGISTER_MODE, mode);
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jit_patch_abs(jit_jmpi(), thunks.return_thunk);
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}
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@ -1148,8 +1154,64 @@ void CPU::jit_instruction(jit_state_t *_jit, uint32_t pc, uint32_t instr,
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}
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case 020: // COP0
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DISASM("cop0 %u\n", 0);
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{
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unsigned rd = (instr >> 11) & 31;
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unsigned rs = (instr >> 21) & 31;
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unsigned rt = (instr >> 16) & 31;
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switch (rs)
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{
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case 000: // MFC0
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{
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if (last_info.conditional)
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jit_save_cond_branch_taken(_jit);
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jit_prepare();
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jit_pushargr(JIT_REGISTER_STATE);
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jit_pushargi(rt);
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jit_pushargi(rd);
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jit_finishi(reinterpret_cast<jit_pointer_t>(RSP_MFC0));
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jit_retval(JIT_REGISTER_MODE);
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if (last_info.conditional)
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jit_restore_cond_branch_taken(_jit);
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jit_node_t *noexit = jit_beqi(JIT_REGISTER_MODE, MODE_CONTINUE);
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jit_exit_dynamic(_jit, pc, last_info, first_instruction);
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jit_patch(noexit);
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DISASM("mfc0 %s, %s\n", NAME(rt), NAME(rd));
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break;
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}
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case 004: // MTC0
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{
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if (last_info.conditional)
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jit_save_cond_branch_taken(_jit);
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jit_prepare();
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jit_pushargr(JIT_REGISTER_STATE);
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jit_pushargi(rd);
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jit_pushargi(rt);
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jit_finishi(reinterpret_cast<jit_pointer_t>(RSP_MTC0));
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jit_retval(JIT_REGISTER_MODE);
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if (last_info.conditional)
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jit_restore_cond_branch_taken(_jit);
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jit_node_t *noexit = jit_beqi(JIT_REGISTER_MODE, MODE_CONTINUE);
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jit_exit_dynamic(_jit, pc, last_info, first_instruction);
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jit_patch(noexit);
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DISASM("mtc0 %s, %s\n", NAME(rd), NAME(rt));
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break;
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}
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default:
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break;
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}
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break;
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}
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case 022: // COP2
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DISASM("cop2 %u\n", 0);
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@ -102,6 +102,7 @@ private:
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void jit_instruction(jit_state_t *_jit, uint32_t pc, uint32_t instr, InstructionInfo &info, const InstructionInfo &last_info,
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bool first_instruction, bool next_instruction_is_target);
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void jit_exit(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_info, ReturnMode mode, bool first_instruction);
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void jit_exit_dynamic(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_info, bool first_instruction);
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void jit_end_of_block(jit_state_t *_jit, uint32_t pc, const InstructionInfo &last_info);
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static void jit_load_register(jit_state_t *_jit, unsigned jit_register, unsigned mips_register);
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static void jit_store_register(jit_state_t *_jit, unsigned jit_register, unsigned mips_register);
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