From 5d67f413bfed8971a891edc7814a1581551b7521 Mon Sep 17 00:00:00 2001
From: Hans-Kristian Arntzen <maister@archlinux.us>
Date: Tue, 4 Feb 2020 20:38:03 +0100
Subject: [PATCH] Optimize some common cases with $0 register.

---
 rsp_jit.cpp | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/rsp_jit.cpp b/rsp_jit.cpp
index d1435f8..6805d3e 100644
--- a/rsp_jit.cpp
+++ b/rsp_jit.cpp
@@ -1341,6 +1341,8 @@ void CPU::jit_instruction(jit_state_t *_jit, uint32_t pc, uint32_t instr,
 		break;
 	}
 
+#define TWO_REG_RS_IS_ZERO() (((instr >> 21) & 31) == 0)
+
 #define TWO_REG_IMM_OP(op, immtype, ext) \
 	unsigned rt = (instr >> 16) & 31; \
 	NOP_IF_RT_ZERO(); \
@@ -1354,7 +1356,17 @@ void CPU::jit_instruction(jit_state_t *_jit, uint32_t pc, uint32_t instr,
 	case 010: // ADDI
 	case 011:
 	{
-		TWO_REG_IMM_OP(addi, int16_t, noext);
+		if (TWO_REG_RS_IS_ZERO())
+		{
+			unsigned rt = (instr >> 16) & 31;
+			NOP_IF_RT_ZERO();
+			regs.immediate_mips_register(_jit, rt, int16_t(instr));
+			regs.unlock_mips_register(rt);
+		}
+		else
+		{
+			TWO_REG_IMM_OP(addi, int16_t, noext);
+		}
 		break;
 	}
 
@@ -1378,7 +1390,17 @@ void CPU::jit_instruction(jit_state_t *_jit, uint32_t pc, uint32_t instr,
 
 	case 015: // ORI
 	{
-		TWO_REG_IMM_OP(ori, uint16_t, noext);
+		if (TWO_REG_RS_IS_ZERO())
+		{
+			unsigned rt = (instr >> 16) & 31;
+			NOP_IF_RT_ZERO();
+			regs.immediate_mips_register(_jit, rt, uint16_t(instr));
+			regs.unlock_mips_register(rt);
+		}
+		else
+		{
+			TWO_REG_IMM_OP(ori, uint16_t, noext);
+		}
 		break;
 	}