mirror of
https://github.com/mupen64plus-ae/parallel-rsp.git
synced 2024-11-23 05:29:39 +00:00
585 lines
10 KiB
C++
585 lines
10 KiB
C++
#include "rsp_disasm.hpp"
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#include <assert.h>
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namespace RSP
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{
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#define DISASM(asmfmt, ...) do { \
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char buf[1024]; \
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sprintf(buf, "0x%03x " asmfmt, pc, __VA_ARGS__); \
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return buf; \
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} while(0)
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#define DISASM_NOP() do { \
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char buf[1024]; \
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sprintf(buf, "0x%03x nop", pc); \
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return buf; \
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} while(0)
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static const char *reg_names[32] = {
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
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};
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#define NAME(reg) reg_names[reg]
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const char *register_name(unsigned reg_index)
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{
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assert(reg_index < 32);
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return reg_names[reg_index];
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}
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std::string disassemble(uint32_t pc, uint32_t instr)
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{
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// VU
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if ((instr >> 25) == 0x25)
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{
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// VU instruction. COP2, and high bit of opcode is set.
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uint32_t op = instr & 63;
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uint32_t vd = (instr >> 6) & 31;
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uint32_t vs = (instr >> 11) & 31;
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uint32_t vt = (instr >> 16) & 31;
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uint32_t e = (instr >> 21) & 15;
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static const char *ops_str[64] = {
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"VMULF", "VMULU", nullptr, nullptr, "VMUDL", "VMUDM", "VMUDN", "VMUDH", "VMACF", "VMACU", nullptr,
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nullptr, "VMADL", "VMADM", "VMADN", "VMADH", "VADD", "VSUB", nullptr, "VABS", "VADDC", "VSUBC",
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, "VSAR", nullptr, nullptr, "VLT",
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"VEQ", "VNE", "VGE", "VCL", "VCH", "VCR", "VMRG", "VAND", "VNAND", "VOR", "VNOR",
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"VXOR", "VNXOR", nullptr, nullptr, "VRCP", "VRCPL", "VRCPH", "VMOV", "VRSQ", "VRSQL", "VRSQH",
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"VNOP",
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};
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if (ops_str[op])
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DISASM("%s v%u, v%u, v%u[%u]", ops_str[op], vd, vs, vt, e);
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else
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DISASM("cop2 %u reserved", op);
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}
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// TODO: Meaningful register allocation.
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// For now, always flush register state to memory after an instruction for simplicity.
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// Should be red-hot in L1 cache, so probably won't be that bad.
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// On x86 and x64, we unfortunately have an anemic register bank to work with in Lightning.
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uint32_t type = instr >> 26;
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#define NOP_IF_RD_ZERO() if (rd == 0) { DISASM_NOP(); break; }
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#define NOP_IF_RT_ZERO() if (rt == 0) { DISASM_NOP(); break; }
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switch (type)
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{
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case 000:
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{
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auto rd = (instr >> 11) & 31;
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auto rt = (instr >> 16) & 31;
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auto shift = (instr >> 6) & 31;
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auto rs = (instr >> 21) & 31;
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switch (instr & 63)
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{
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#define FIXED_SHIFT_OP(asmop) \
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NOP_IF_RD_ZERO(); \
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DISASM(#asmop " %s, %s, %u", NAME(rd), NAME(rt), shift)
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case 000: // SLL
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{
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FIXED_SHIFT_OP(sll);
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break;
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}
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case 002: // SRL
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{
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FIXED_SHIFT_OP(srl);
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break;
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}
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case 003: // SRA
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{
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FIXED_SHIFT_OP(sra);
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break;
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}
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#define VARIABLE_SHIFT_OP(asmop) \
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NOP_IF_RD_ZERO(); \
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DISASM(#asmop " %s, %s, %s", NAME(rd), NAME(rt), NAME(rs))
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case 004: // SLLV
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{
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VARIABLE_SHIFT_OP(sllv);
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break;
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}
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case 006: // SRLV
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{
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VARIABLE_SHIFT_OP(srlv);
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break;
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}
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case 007: // SRAV
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{
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VARIABLE_SHIFT_OP(srav);
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break;
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}
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// If the last instruction is also a branch instruction, we will need to do some funky handling
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// so make sure we save the old branch taken register.
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case 010: // JR
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{
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DISASM("jr %s", NAME(rs));
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break;
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}
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case 011: // JALR
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{
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DISASM("jalr %s", NAME(rs));
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break;
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}
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case 015: // BREAK
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{
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DISASM("break %u", 0);
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break;
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}
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#define THREE_REG_OP(asmop) \
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NOP_IF_RD_ZERO(); \
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DISASM(#asmop " %s, %s, %s", NAME(rd), NAME(rt), NAME(rs))
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case 040: // ADD
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case 041: // ADDU
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{
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THREE_REG_OP(addu);
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break;
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}
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case 042: // SUB
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case 043: // SUBU
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{
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THREE_REG_OP(subu);
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break;
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}
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case 044: // AND
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{
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THREE_REG_OP(and);
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break;
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}
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case 045: // OR
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{
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THREE_REG_OP(or);
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break;
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}
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case 046: // XOR
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{
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THREE_REG_OP(xor);
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break;
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}
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case 047: // NOR
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{
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NOP_IF_RD_ZERO();
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DISASM("nor %s, %s, %s", NAME(rd), NAME(rt), NAME(rs));
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break;
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}
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case 052: // SLT
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{
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THREE_REG_OP(slt);
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break;
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}
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case 053: // SLTU
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{
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THREE_REG_OP(sltu);
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break;
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}
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default:
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break;
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}
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break;
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}
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case 001: // REGIMM
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{
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unsigned rt = (instr >> 16) & 31;
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switch (rt)
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{
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case 020: // BLTZAL
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{
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unsigned rs = (instr >> 21) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("bltzal %s, 0x%03x", NAME(rs), target_pc);
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break;
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}
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case 000: // BLTZ
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{
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unsigned rs = (instr >> 21) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("bltz %s, 0x%03x", NAME(rs), target_pc);
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break;
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}
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case 021: // BGEZAL
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{
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unsigned rs = (instr >> 21) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("bltzal %s, 0x%03x", NAME(rs), target_pc);
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break;
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}
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case 001: // BGEZ
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{
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unsigned rs = (instr >> 21) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("bgez %s, 0x%03x", NAME(rs), target_pc);
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break;
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}
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default:
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break;
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}
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break;
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}
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case 003: // JAL
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{
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uint32_t target_pc = (instr & 0x3ffu) << 2;
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DISASM("jal 0x%03x", target_pc);
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break;
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}
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case 002: // J
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{
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uint32_t target_pc = (instr & 0x3ffu) << 2;
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DISASM("j 0x%03x", target_pc);
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break;
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}
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case 004: // BEQ
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{
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unsigned rs = (instr >> 21) & 31;
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unsigned rt = (instr >> 16) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("beq %s, %s, 0x%03x", NAME(rs), NAME(rt), target_pc);
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break;
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}
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case 005: // BNE
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{
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unsigned rs = (instr >> 21) & 31;
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unsigned rt = (instr >> 16) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("bne %s, %s, 0x%03x", NAME(rs), NAME(rt), target_pc);
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break;
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}
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case 006: // BLEZ
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{
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unsigned rs = (instr >> 21) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("blez %s, 0x%03x", NAME(rs), target_pc);
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break;
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}
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case 007: // BGTZ
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{
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unsigned rs = (instr >> 21) & 31;
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uint32_t target_pc = (pc + 4 + (instr << 2)) & 0xffc;
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DISASM("bgtz %s, 0x%03x", NAME(rs), target_pc);
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break;
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}
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#define TWO_REG_IMM_OP(asmop, immtype) \
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unsigned rt = (instr >> 16) & 31; \
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NOP_IF_RT_ZERO(); \
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unsigned rs = (instr >> 21) & 31; \
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DISASM(#asmop " %s, %s, %d", NAME(rt), NAME(rs), immtype(instr))
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case 010: // ADDI
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case 011:
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{
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TWO_REG_IMM_OP(addi, int16_t);
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break;
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}
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case 012: // SLTI
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{
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TWO_REG_IMM_OP(slti, int16_t);
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break;
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}
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case 013: // SLTIU
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{
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TWO_REG_IMM_OP(sltiu, uint16_t);
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break;
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}
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case 014: // ANDI
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{
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TWO_REG_IMM_OP(andi, uint16_t);
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break;
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}
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case 015: // ORI
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{
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TWO_REG_IMM_OP(ori, uint16_t);
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break;
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}
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case 016: // XORI
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{
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TWO_REG_IMM_OP(xori, uint16_t);
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break;
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}
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case 017: // LUI
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{
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unsigned rt = (instr >> 16) & 31;
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NOP_IF_RT_ZERO();
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int16_t imm = int16_t(instr);
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DISASM("lui %s, %d", NAME(rt), imm);
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break;
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}
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case 020: // COP0
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{
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unsigned rd = (instr >> 11) & 31;
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unsigned rs = (instr >> 21) & 31;
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unsigned rt = (instr >> 16) & 31;
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switch (rs)
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{
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case 000: // MFC0
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{
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DISASM("mfc0 %s, %s", NAME(rt), NAME(rd));
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break;
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}
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case 004: // MTC0
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{
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DISASM("mtc0 %s, %s", NAME(rd), NAME(rt));
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break;
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}
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default:
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break;
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}
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break;
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}
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case 022: // COP2
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{
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unsigned rd = (instr >> 11) & 31;
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unsigned rs = (instr >> 21) & 31;
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unsigned rt = (instr >> 16) & 31;
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unsigned imm = (instr >> 7) & 15;
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switch (rs)
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{
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case 000: // MFC2
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{
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DISASM("mfc2 %s, %s, %u", NAME(rt), NAME(rd), imm);
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break;
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}
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case 002: // CFC2
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{
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DISASM("cfc2 %s, %s", NAME(rt), NAME(rd));
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break;
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}
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case 004: // MTC2
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{
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DISASM("mtc2 %s, %s, %u", NAME(rt), NAME(rd), imm);
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break;
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}
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case 006: // CTC2
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{
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DISASM("ctc2 %s, %s", NAME(rt), NAME(rd));
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break;
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}
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default:
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break;
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}
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break;
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}
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case 040: // LB
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("lb %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 041: // LH
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("lh %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 043: // LW
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("lw %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 044: // LBU
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("lbu %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 045: // LHU
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("lhu %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 050: // SB
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("sb %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 051: // SH
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("sh %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 053: // SW
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{
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unsigned rt = (instr >> 16) & 31;
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if (rt == 0)
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{
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DISASM_NOP();
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break;
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}
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int16_t simm = int16_t(instr);
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unsigned rs = (instr >> 21) & 31;
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DISASM("sw %s, %d(%s)", NAME(rt), simm, NAME(rs));
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break;
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}
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case 062: // LWC2
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{
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unsigned rt = (instr >> 16) & 31;
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int16_t simm = instr;
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// Sign-extend.
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simm <<= 9;
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simm >>= 9;
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unsigned rs = (instr >> 21) & 31;
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unsigned rd = (instr >> 11) & 31;
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unsigned imm = (instr >> 7) & 15;
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static const char *lwc2_ops[32] = {
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"LBV", "LSV", "LLV", "LDV", "LQV", "LRV", "LPV", "LUV", "LHV", nullptr, nullptr, "LTV",
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};
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const char *op = lwc2_ops[rd];
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if (op)
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DISASM("%s v%u, %u, %d(%s)", op, rt, imm, simm, NAME(rs));
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else
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DISASM_NOP();
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break;
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}
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case 072: // SWC2
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{
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unsigned rt = (instr >> 16) & 31;
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int16_t simm = instr;
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// Sign-extend.
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simm <<= 9;
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simm >>= 9;
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unsigned rs = (instr >> 21) & 31;
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unsigned rd = (instr >> 11) & 31;
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|
unsigned imm = (instr >> 7) & 15;
|
|
|
|
static const char *swc2_ops[32] = {
|
|
"SBV", "SSV", "SLV", "SDV", "SQV", "SRV", "SPV", "SUV", "SHV", "SFV", nullptr, "STV",
|
|
};
|
|
|
|
const char *op = swc2_ops[rd];
|
|
if (op)
|
|
DISASM("%s v%u, %u, %d(%s)", op, rt, imm, simm, NAME(rs));
|
|
else
|
|
DISASM_NOP();
|
|
|
|
break;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return "???";
|
|
}
|
|
} |