mirror of
https://github.com/mupen64plus-ae/parallel-rsp.git
synced 2024-11-26 23:10:21 +00:00
147 lines
3.1 KiB
C++
147 lines
3.1 KiB
C++
#ifndef STATE_HPP__
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#define STATE_HPP__
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#include "rsp.h"
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#define DMEM_SIZE (4 * 1024)
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#define IMEM_SIZE (4 * 1024)
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#define DMEM_WORDS (DMEM_SIZE / 4)
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#define IMEM_WORDS (IMEM_SIZE / 4)
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#define CODE_BLOCK_SIZE (256)
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#define CODE_BLOCK_WORDS (CODE_BLOCK_SIZE / 4)
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#define CODE_BLOCK_SIZE_LOG2 (8)
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#define CODE_BLOCKS (IMEM_SIZE / CODE_BLOCK_SIZE)
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namespace RSP
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{
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enum RSPFlags
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{
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RSP_VCO = 0,
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RSP_VCC = 1,
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RSP_VCE = 2
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};
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enum RSPAccumulator
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{
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RSP_ACC_LO = 16,
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RSP_ACC_MD = 8,
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RSP_ACC_HI = 0
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};
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enum CP0Registers
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{
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CP0_REGISTER_DMA_CACHE = 0,
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CP0_REGISTER_DMA_DRAM = 1,
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CP0_REGISTER_DMA_READ_LENGTH = 2,
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CP0_REGISTER_DMA_WRITE_LENGTH = 3,
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CP0_REGISTER_SP_STATUS = 4,
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CP0_REGISTER_DMA_FULL = 5,
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CP0_REGISTER_DMA_BUSY = 6,
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CP0_REGISTER_SP_RESERVED = 7,
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CP0_REGISTER_CMD_START = 8,
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CP0_REGISTER_CMD_END = 9,
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CP0_REGISTER_CMD_CURRENT = 10,
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CP0_REGISTER_CMD_STATUS = 11,
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CP0_REGISTER_CMD_CLOCK = 12,
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CP0_REGISTER_CMD_BUSY = 13,
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CP0_REGISTER_CMD_PIPE_BUSY = 14,
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CP0_REGISTER_CMD_TMEM_BUSY = 15,
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};
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// SP_STATUS read bits.
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#define SP_STATUS_HALT 0x0001
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#define SP_STATUS_BROKE 0x0002
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#define SP_STATUS_DMA_BUSY 0x0004
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#define SP_STATUS_DMA_FULL 0x0008
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#define SP_STATUS_IO_FULL 0x0010
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#define SP_STATUS_SSTEP 0x0020
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#define SP_STATUS_INTR_BREAK 0x0040
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#define SP_STATUS_SIG0 0x0080
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#define SP_STATUS_SIG1 0x0100
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#define SP_STATUS_SIG2 0x0200
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#define SP_STATUS_SIG3 0x0400
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#define SP_STATUS_SIG4 0x0800
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#define SP_STATUS_SIG5 0x1000
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#define SP_STATUS_SIG6 0x2000
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#define SP_STATUS_SIG7 0x4000
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// SP_STATUS write bits.
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#define SP_CLR_HALT 0x00000001
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#define SP_SET_HALT 0x00000002
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#define SP_CLR_BROKE 0x00000004
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#define SP_CLR_INTR 0x00000008
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#define SP_SET_INTR 0x00000010
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#define SP_CLR_SSTEP 0x00000020
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#define SP_SET_SSTEP 0x00000040
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#define SP_CLR_INTR_BREAK 0x00000080
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#define SP_SET_INTR_BREAK 0x00000100
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#define SP_CLR_SIG0 0x00000200
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#define SP_SET_SIG0 0x00000400
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#define SP_CLR_SIG1 0x00000800
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#define SP_SET_SIG1 0x00001000
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#define SP_CLR_SIG2 0x00002000
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#define SP_SET_SIG2 0x00004000
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#define SP_CLR_SIG3 0x00008000
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#define SP_SET_SIG3 0x00010000
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#define SP_CLR_SIG4 0x00020000
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#define SP_SET_SIG4 0x00040000
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#define SP_CLR_SIG5 0x00080000
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#define SP_SET_SIG5 0x00100000
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#define SP_CLR_SIG6 0x00200000
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#define SP_SET_SIG6 0x00400000
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#define SP_CLR_SIG7 0x00800000
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#define SP_SET_SIG7 0x01000000
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template <int N>
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struct alignas(rsp_vect_t) AlignedRSPVector
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{
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uint16_t e[8 * N];
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};
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struct CP0
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{
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uint32_t *cr[16] = {};
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uint32_t *irq = nullptr;
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};
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struct alignas(64) CP2
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{
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AlignedRSPVector<1> regs[32];
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AlignedRSPVector<2> flags[3];
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AlignedRSPVector<3> acc;
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int16_t div_out;
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int16_t div_in;
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int8_t dp_flag;
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};
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struct CPUState
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{
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uint32_t pc = 0;
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uint32_t dirty_blocks = 0;
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static_assert(CODE_BLOCKS <= 32, "Code blocks must fit in 32-bit register.");
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uint32_t has_delay_slot = 0;
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uint32_t branch_target = 0;
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uint32_t sr[32] = {};
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uint32_t *dmem = nullptr;
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uint32_t *imem = nullptr;
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uint32_t *rdram = nullptr;
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CP2 cp2 = {};
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CP0 cp0;
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};
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enum ReturnMode
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{
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MODE_ENTER = 0,
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MODE_CONTINUE = 1,
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MODE_BREAK = 2,
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MODE_DMA_READ = 3,
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MODE_CHECK_FLAGS = 4
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};
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} // namespace RSP
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#endif
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