diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 81ce9d63..cfbf8767 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -359,7 +359,7 @@ struct compile_state
   uint64_t branch_unneeded_reg[MAXBLOCK];
 };
 
-  #define HACK_ENABLED(x) ((ndrc_g.hacks | ndrc_g.hacks_pergame) & (x))
+  #define HACK_ENABLED(x) ((NDHACK_NO_STALLS|NDHACK_NO_COMPAT_HACKS) & (x))
 
   /* registers that may be allocated */
   /* 1-31 gpr */
@@ -851,6 +851,7 @@ static int cycle_multiplier_active;
 
 static int CLOCK_ADJUST(int x)
 {
+  return x * 2;
   int m = cycle_multiplier_active;
   int s = (x >> 31) | 1;
   return (x * m + s * 50) / 100;
@@ -1056,6 +1057,9 @@ static noinline u_int generate_exception(u_int pc)
 static void noinline *get_addr(struct ht_entry *ht, const u_int vaddr,
   enum ndrc_compile_mode compile_mode)
 {
+#ifdef DRC_DBG
+printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc);
+#endif
   int set_smrv_regs = (compile_mode != ndrc_cm_compile_offline);
   u_int start_page = get_page_prev(vaddr);
   u_int i, page, end_page = get_page(vaddr);
@@ -7717,6 +7721,7 @@ static noinline void pass2b_unneeded_regs(struct compile_state *st,
     u|=1;
     // Save it
     st->unneeded_reg[i]=u;
+    st->unneeded_reg[i]=1;//u;
     gte_unneeded[i]=gte_u;
     /*
     printf("ur (%d,%d) %x: ",istart,iend,st->start+i*4);
@@ -8861,6 +8866,7 @@ static noinline void pass5a_preallocate1(struct compile_state *st)
 // to use, which can avoid a load-use penalty on certain CPUs.
 static noinline void pass5b_preallocate2(struct compile_state *st)
 {
+ return;
   int i, hr, limit = min(st->slen - 1, MAXBLOCK - 2);
   for (i = 0; i < limit; i++)
   {
@@ -10009,6 +10015,10 @@ static int noinline new_recompile_block(u_int addr)
 
 #ifdef ASSEM_PRINT
   fflush(stdout);
+#endif
+#ifdef DRC_DBG
+printf("new_recompile_block done\n");
+fflush(stdout);
 #endif
   stat_inc(stat_bc_direct);
   return 0;
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index e0520eab..5d2810fb 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -236,6 +236,8 @@ static void write_biu(u32 value)
 		return;
 	}
 
+extern u32 handler_cycle;
+handler_cycle = psxRegs.cycle;
 	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
 	psxRegs.biuReg = value;
 }
diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
index 471980ea..dc13969f 100644
--- a/libpcsxcore/psxcounters.c
+++ b/libpcsxcore/psxcounters.c
@@ -455,9 +455,12 @@ void psxRcntUpdate()
 
 /******************************************************************************/
 
+extern u32 handler_cycle;
+
 void psxRcntWcount( u32 index, u32 value )
 {
     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWcount( index, value );
     psxRcntSet();
@@ -466,6 +469,7 @@ void psxRcntWcount( u32 index, u32 value )
 void psxRcntWmode( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWmode( index, value );
     _psxRcntWcount( index, 0 );
@@ -477,6 +481,7 @@ void psxRcntWmode( u32 index, u32 value )
 void psxRcntWtarget( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     rcnts[index].target = value;
 
@@ -490,6 +495,7 @@ u32 psxRcntRcount0()
 {
     u32 index = 0;
     u32 count;
+handler_cycle = psxRegs.cycle;
 
     if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
         (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
diff --git a/libpcsxcore/psxevents.c b/libpcsxcore/psxevents.c
index 1e2d01f6..0ee15974 100644
--- a/libpcsxcore/psxevents.c
+++ b/libpcsxcore/psxevents.c
@@ -77,11 +77,13 @@ void irq_test(psxCP0Regs *cp0)
 		}
 	}
 
-	cp0->n.Cause &= ~0x400;
+	u32 c2 = cp0->n.Cause & ~0x400;
 	if (psxHu32_(regs, 0x1070) & psxHu32_(regs, 0x1074))
-		cp0->n.Cause |= 0x400;
-	if (((cp0->n.Cause | 1) & cp0->n.SR & 0x401) == 0x401)
+		c2 |= 0x400;
+	if (((c2 | 1) & cp0->n.SR & 0x401) == 0x401) {
+		cp0->n.Cause = c2;
 		psxException(0, 0, cp0);
+	}
 }
 
 void gen_interupt(psxCP0Regs *cp0)
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 55bf2d41..55b559b2 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -236,7 +236,7 @@ static inline void addCycle(psxRegisters *regs)
 {
 	assert(regs->subCycleStep >= 0x10000);
 	regs->subCycle += regs->subCycleStep;
-	regs->cycle += regs->subCycle >> 16;
+	regs->cycle += 2; //regs->subCycle >> 16;
 	regs->subCycle &= 0xffff;
 }
 
@@ -434,7 +434,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
 		regs->CP0.n.Target = pc_final;
 	regs->branching = 0;
 
+	psxRegs.cycle += 2;
 	psxBranchTest(regs);
+	psxRegs.cycle -= 2;
 }
 
 static void doBranchReg(psxRegisters *regs, u32 tar) {
@@ -969,7 +971,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
 	}
 }
 
-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(regs_); }
 
 // no exception
 static inline void psxNULLne(psxRegisters *regs) {
@@ -1123,6 +1125,7 @@ OP(psxHLE) {
 	dloadFlush(regs_);
 	psxHLEt[hleCode]();
 	regs_->branchSeen = R3000A_BRANCH_HLE_RETURN;
+	regs_->cycle -= 2;
 }
 
 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
@@ -1165,12 +1168,14 @@ static inline void execI_(
 {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static inline void execIbp(
@@ -1179,7 +1184,7 @@ static inline void execIbp(
 {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	if (execBreakCheck(regs, pc))
@@ -1188,6 +1193,8 @@ static inline void execIbp(
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static void intExecute(psxRegisters *regs) {
@@ -1208,14 +1215,19 @@ static void intExecuteBp(psxRegisters *regs) {
 		execIbp(fetch, memRLUT, regs);
 }
 
+ extern int last_count;
+ void do_insn_cmp(void);
 static void intExecuteBlock(psxRegisters *regs, enum blockExecCaller caller) {
 	u32 (INT_ATTR *fetch)(struct psxRegisters *r, const uintptr_t *luts, u32 pc) =
 		regs->ptrs.intFetch;
 	const uintptr_t *memRLUT = regs->ptrs.memRLUT;
 
+ last_count = 0;
 	regs->branchSeen = 0;
-	while (!regs->branchSeen)
+	while (!regs->branchSeen || (regs->dloadReg[0] || regs->dloadReg[1])) {
+		do_insn_cmp();
 		execI_(fetch, memRLUT, regs);
+	}
 }
 
 static void intExecuteBlockBp(psxRegisters *regs, enum blockExecCaller caller) {
@@ -1223,9 +1235,12 @@ static void intExecuteBlockBp(psxRegisters *regs, enum blockExecCaller caller) {
 		regs->ptrs.intFetch;
 	const uintptr_t *memRLUT = regs->ptrs.memRLUT;
 
+ last_count = 0;
 	regs->branchSeen = 0;
-	while (!regs->branchSeen)
+	while (!regs->branchSeen || (regs->dloadReg[0] || regs->dloadReg[1])) {
+		do_insn_cmp();
 		execIbp(fetch, memRLUT, regs);
+	}
 }
 
 static void intClear(u32 Addr, u32 Size) {
@@ -1272,7 +1287,7 @@ static void setupCop(u32 sr)
 	else
 		psxBSC[17] = psxCOPd;
 	if (sr & (1u << 30))
-		psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
+		psxBSC[18] = psxCOP2;
 	else
 		psxBSC[18] = psxCOPd;
 	if (sr & (1u << 31))
@@ -1291,7 +1306,7 @@ void intApplyConfig() {
 	assert(psxSPC[26] == psxDIV   || psxSPC[26] == psxDIV_stall);
 	assert(psxSPC[27] == psxDIVU  || psxSPC[27] == psxDIVU_stall);
 
-	if (Config.DisableStalls) {
+	if (1) {
 		psxBSC[18] = psxCOP2;
 		psxBSC[50] = gteLWC2;
 		psxBSC[58] = gteSWC2;
@@ -1379,11 +1394,14 @@ void execI(psxRegisters *regs) {
 	const uintptr_t *memRLUT = regs->ptrs.memRLUT;
 	int loop = 0;
 
+ printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, regs->next_interupt);
+ last_count = 0;
 	do {
 		execIbp(fetch, memRLUT, regs);
 #ifdef HANDLE_LOAD_DELAY
 		loop = regs->dloadReg[0] | regs->dloadReg[1];
 #endif
+		if (loop) do_insn_cmp();
 	} while (loop);
 }
 
