mirror of
https://github.com/openharmony/ark_js_runtime.git
synced 2026-07-22 07:35:27 -04:00
zhangyukun
331 lines
14 KiB
C++
331 lines
14 KiB
C++
/*
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* Copyright (c) 2021 Huawei Device Co., Ltd.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "ecmascript/compiler/scheduler.h"
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#include <cmath>
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#include "ecmascript/compiler/verifier.h"
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namespace kungfu {
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using DominatorTreeInfo = std::tuple<std::vector<AddrShift>, std::unordered_map<AddrShift, size_t>,
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std::vector<size_t>>;
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DominatorTreeInfo Scheduler::CalculateDominatorTree(const Circuit *circuit)
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{
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std::vector<AddrShift> bbGatesList;
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std::unordered_map<AddrShift, size_t> bbGatesAddrToIdx;
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std::unordered_map<AddrShift, size_t> dfsTimestamp;
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circuit->AdvanceTime();
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{
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size_t timestamp = 0;
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std::deque<AddrShift> pendingList;
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auto startGate = Circuit::GetCircuitRoot(OpCode(OpCode::STATE_ENTRY));
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circuit->SetMark(startGate, MarkCode::VISITED);
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pendingList.push_back(startGate);
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while (!pendingList.empty()) {
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auto curGate = pendingList.back();
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dfsTimestamp[curGate] = timestamp++;
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pendingList.pop_back();
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bbGatesList.push_back(curGate);
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if (circuit->GetOpCode(curGate) != OpCode::LOOP_BACK) {
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for (const auto &succGate : circuit->GetOutVector(curGate)) {
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if (circuit->GetOpCode(succGate).IsState() && circuit->GetMark(succGate) == MarkCode::EMPTY) {
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circuit->SetMark(succGate, MarkCode::VISITED);
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pendingList.push_back(succGate);
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}
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}
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}
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}
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for (size_t idx = 0; idx < bbGatesList.size(); idx++) {
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bbGatesAddrToIdx[bbGatesList[idx]] = idx;
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}
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}
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std::vector<size_t> immDom(bbGatesList.size());
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{
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std::vector<std::vector<size_t>> dom(bbGatesList.size());
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dom[0] = {0};
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for (size_t idx = 1; idx < dom.size(); idx++) {
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dom[idx].resize(dom.size());
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std::iota(dom[idx].begin(), dom[idx].end(), 0);
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}
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bool changed = true;
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while (changed) {
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changed = false;
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for (size_t idx = 1; idx < dom.size(); idx++) {
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auto &curDom = dom[idx];
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size_t origSize = curDom.size();
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curDom.resize(dom.size());
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std::iota(curDom.begin(), curDom.end(), 0);
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for (const auto &predGate : circuit->GetInVector(bbGatesList[idx])) {
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if (bbGatesAddrToIdx.count(predGate) > 0) {
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std::vector<size_t> tmp(curDom.size());
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const auto &predDom = dom[bbGatesAddrToIdx[predGate]];
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auto it = std::set_intersection(
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curDom.begin(), curDom.end(), predDom.begin(), predDom.end(), tmp.begin());
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tmp.resize(it - tmp.begin());
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curDom = tmp;
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}
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}
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auto it = std::find(curDom.begin(), curDom.end(), idx);
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if (it == curDom.end()) {
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curDom.push_back(idx);
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std::sort(curDom.begin(), curDom.end());
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}
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if (dom[idx].size() != origSize) {
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changed = true;
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}
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}
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}
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immDom[0] = dom[0].front();
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for (size_t idx = 1; idx < dom.size(); idx++) {
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auto it = std::remove(dom[idx].begin(), dom[idx].end(), idx);
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dom[idx].resize(it - dom[idx].begin());
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immDom[idx] = *std::max_element(dom[idx].begin(), dom[idx].end(),
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[bbGatesList, dfsTimestamp](const size_t &lhs, const size_t &rhs) -> bool {
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return dfsTimestamp.at(bbGatesList[lhs]) < dfsTimestamp.at(bbGatesList[rhs]);
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});
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}
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}
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return {bbGatesList, bbGatesAddrToIdx, immDom};
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}
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std::vector<std::vector<AddrShift>> Scheduler::Run(const Circuit *circuit)
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{
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#ifndef NDEBUG
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if (!Verifier::Run(circuit)) {
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UNREACHABLE();
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}
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#endif
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std::vector<AddrShift> bbGatesList;
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std::unordered_map<AddrShift, size_t> bbGatesAddrToIdx;
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std::vector<size_t> immDom;
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std::tie(bbGatesList, bbGatesAddrToIdx, immDom) = Scheduler::CalculateDominatorTree(circuit);
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std::vector<std::vector<AddrShift>> result(bbGatesList.size());
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for (size_t idx = 0; idx < bbGatesList.size(); idx++) {
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result[idx].push_back(bbGatesList[idx]);
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}
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// assuming CFG is always reducible
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std::vector<std::vector<size_t>> sonList(result.size());
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for (size_t idx = 1; idx < immDom.size(); idx++) {
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sonList[immDom[idx]].push_back(idx);
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}
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const size_t sizeLog = std::ceil(std::log2(static_cast<double>(result.size())) + 1);
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std::vector<size_t> timeIn(result.size());
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std::vector<size_t> timeOut(result.size());
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std::vector<std::vector<size_t>> jumpUp;
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jumpUp.assign(result.size(), std::vector<size_t>(sizeLog + 1));
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{
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size_t timestamp = 0;
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std::function<void(size_t, size_t)> dfs = [&](size_t cur, size_t prev) {
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timeIn[cur] = timestamp;
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timestamp++;
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jumpUp[cur][0] = prev;
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for (size_t stepSize = 1; stepSize <= sizeLog; stepSize++) {
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jumpUp[cur][stepSize] = jumpUp[jumpUp[cur][stepSize - 1]][stepSize - 1];
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}
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for (const auto &succ : sonList[cur]) {
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dfs(succ, cur);
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}
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timeOut[cur] = timestamp;
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timestamp++;
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};
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size_t root = 0;
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dfs(root, root);
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}
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auto isAncestor = [&](size_t nodeA, size_t nodeB) -> bool {
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return (timeIn[nodeA] <= timeIn[nodeB]) && (timeOut[nodeA] >= timeOut[nodeB]);
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};
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auto lowestCommonAncestor = [&](size_t nodeA, size_t nodeB) -> size_t {
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if (isAncestor(nodeA, nodeB)) {
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return nodeA;
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}
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if (isAncestor(nodeB, nodeA)) {
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return nodeB;
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}
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for (size_t stepSize = sizeLog + 1; stepSize > 0; stepSize--) {
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if (!isAncestor(jumpUp[nodeA][stepSize - 1], nodeB)) {
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nodeA = jumpUp[nodeA][stepSize - 1];
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}
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}
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return jumpUp[nodeA][0];
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};
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{
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std::vector<AddrShift> order;
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auto lowerBound =
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Scheduler::CalculateSchedulingLowerBound(circuit, bbGatesAddrToIdx, lowestCommonAncestor, &order).value();
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for (const auto &schedulableGate : order) {
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result[lowerBound.at(schedulableGate)].push_back(schedulableGate);
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}
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auto argList = circuit->GetOutVector(Circuit::GetCircuitRoot(OpCode(OpCode::ARG_LIST)));
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std::sort(argList.begin(), argList.end(), [&](const AddrShift &lhs, const AddrShift &rhs) -> bool {
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return circuit->GetBitField(lhs) > circuit->GetBitField(rhs);
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});
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for (const auto &arg : argList) {
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result.front().push_back(arg);
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}
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for (const auto &bbGate : bbGatesList) {
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for (const auto &succGate : circuit->GetOutVector(bbGate)) {
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if (circuit->GetOpCode(succGate).IsFixed()) {
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result[bbGatesAddrToIdx.at(circuit->GetIn(succGate, 0))].push_back(succGate);
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}
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}
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}
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}
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return result;
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}
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std::optional<std::unordered_map<AddrShift, size_t>> Scheduler::CalculateSchedulingUpperBound(const Circuit *circuit,
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const std::unordered_map<AddrShift, size_t> &bbGatesAddrToIdx,
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const std::function<bool(size_t, size_t)> &isAncestor, const std::vector<AddrShift> &schedulableGatesList)
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{
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std::unordered_map<AddrShift, size_t> upperBound;
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std::function<std::optional<size_t>(AddrShift)> dfs = [&](AddrShift curGate) -> std::optional<size_t> {
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if (upperBound.count(curGate) > 0) {
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return upperBound[curGate];
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}
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if (circuit->GetOpCode(curGate).IsProlog() || circuit->GetOpCode(curGate).IsRoot()) {
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return 0;
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}
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if (circuit->GetOpCode(curGate).IsFixed()) {
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return bbGatesAddrToIdx.at(circuit->GetIn(curGate, 0));
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}
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// then cur is schedulable
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size_t curUpperBound = 0;
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for (const auto &predGate : circuit->GetInVector(curGate)) {
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auto predResult = dfs(predGate);
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if (!predResult.has_value()) {
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return std::nullopt;
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}
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auto predUpperBound = predResult.value();
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if (!isAncestor(curUpperBound, predUpperBound) && !isAncestor(predUpperBound, curUpperBound)) {
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std::cerr << "[Verifier][Error] Scheduling upper bound of gate (id=" << curGate << ") does not exist"
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<< std::endl;
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return std::nullopt;
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}
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if (isAncestor(curUpperBound, predUpperBound)) {
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curUpperBound = predUpperBound;
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}
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}
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return (upperBound[curGate] = curUpperBound);
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};
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for (const auto &schedulableGate : schedulableGatesList) {
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if (upperBound.count(schedulableGate) == 0) {
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if (!dfs(schedulableGate).has_value()) {
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return std::nullopt;
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}
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}
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}
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return upperBound;
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}
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std::optional<std::unordered_map<AddrShift, size_t>> Scheduler::CalculateSchedulingLowerBound(const Circuit *circuit,
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const std::unordered_map<AddrShift, size_t> &bbGatesAddrToIdx,
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const std::function<size_t(size_t, size_t)> &lowestCommonAncestor, std::vector<AddrShift> *order)
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{
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std::unordered_map<AddrShift, size_t> lowerBound;
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std::unordered_map<AddrShift, size_t> useCount;
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std::deque<AddrShift> pendingList;
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std::vector<AddrShift> bbAndFixedGatesList;
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for (const auto &item : bbGatesAddrToIdx) {
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bbAndFixedGatesList.push_back(item.first);
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for (const auto &succGate : circuit->GetOutVector(item.first)) {
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if (circuit->GetOpCode(succGate).IsFixed()) {
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bbAndFixedGatesList.push_back(succGate);
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}
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}
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}
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std::function<void(AddrShift)> dfsVisit = [&](AddrShift curGate) {
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for (const auto &prevGate : circuit->GetInVector(curGate)) {
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if (circuit->GetOpCode(prevGate).IsSchedulable()) {
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useCount[prevGate]++;
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if (useCount[prevGate] == 1) {
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dfsVisit(prevGate);
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}
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}
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}
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};
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for (const auto &gate : bbAndFixedGatesList) {
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dfsVisit(gate);
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}
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std::function<void(AddrShift)> dfsFinish = [&](AddrShift curGate) {
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size_t cnt = 0;
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for (const auto &prevGate : circuit->GetInVector(curGate)) {
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if (circuit->GetOpCode(prevGate).IsSchedulable()) {
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useCount[prevGate]--;
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size_t curLowerBound;
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if (circuit->GetOpCode(curGate).IsState()) { // cur_opcode would not be STATE_ENTRY
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curLowerBound = bbGatesAddrToIdx.at(curGate);
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} else if (circuit->GetOpCode(curGate).IsFixed()) {
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ASSERT(cnt > 0);
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curLowerBound = bbGatesAddrToIdx.at(circuit->GetIn(circuit->GetIn(curGate, 0), cnt - 1));
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} else {
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curLowerBound = lowerBound.at(curGate);
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}
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if (lowerBound.count(prevGate) == 0) {
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lowerBound[prevGate] = curLowerBound;
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} else {
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lowerBound[prevGate] = lowestCommonAncestor(lowerBound[prevGate], curLowerBound);
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}
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if (useCount[prevGate] == 0) {
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if (order != nullptr) {
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order->push_back(prevGate);
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}
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dfsFinish(prevGate);
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}
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}
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cnt++;
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}
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};
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for (const auto &gate : bbAndFixedGatesList) {
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dfsFinish(gate);
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}
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return lowerBound;
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}
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void Scheduler::Print(const std::vector<std::vector<AddrShift>> *cfg, const Circuit *circuit)
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{
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std::vector<AddrShift> bbGatesList;
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std::unordered_map<AddrShift, size_t> bbGatesAddrToIdx;
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std::vector<size_t> immDom;
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std::tie(bbGatesList, bbGatesAddrToIdx, immDom) = Scheduler::CalculateDominatorTree(circuit);
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std::cout << "==========================================================================" << std::endl;
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for (size_t bbIdx = 0; bbIdx < cfg->size(); bbIdx++) {
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std::cout << "BB_" << bbIdx << "_" << circuit->GetOpCode((*cfg)[bbIdx].front()).Str() << ":"
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<< " immDom=" << immDom[bbIdx];
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std::cout << " pred=[";
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bool isFirst = true;
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for (const auto &predStates : circuit->GetInVector((*cfg)[bbIdx].front())) {
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if (circuit->GetOpCode(predStates).IsState() || circuit->GetOpCode(predStates) == OpCode::STATE_ENTRY) {
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std::cout << (isFirst ? "" : " ") << bbGatesAddrToIdx.at(predStates);
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isFirst = false;
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}
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}
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std::cout << "] succ=[";
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isFirst = true;
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for (const auto &succStates : circuit->GetOutVector((*cfg)[bbIdx].front())) {
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if (circuit->GetOpCode(succStates).IsState() || circuit->GetOpCode(succStates) == OpCode::STATE_ENTRY) {
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std::cout << (isFirst ? "" : " ") << bbGatesAddrToIdx.at(succStates);
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isFirst = false;
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}
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}
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std::cout << "]";
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std::cout << std::endl;
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for (size_t instIdx = (*cfg)[bbIdx].size(); instIdx > 0; instIdx--) {
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circuit->Print((*cfg)[bbIdx][instIdx - 1]);
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}
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}
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std::cout << "==========================================================================" << std::endl;
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}
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} // namespace kungfu
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