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https://gitee.com/openharmony/arkcompiler_ets_runtime
synced 2024-10-07 08:03:29 +00:00
64ee28fbd9
Merge pull request !7004 from linxinyq/Allow-i64ptr-to-create-both-MIR-ref-type-and-MIR-ptr-type
508 lines
21 KiB
C++
508 lines
21 KiB
C++
/*
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* Copyright (c) 2021 Huawei Device Co., Ltd.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "ecmascript/compiler/scheduler.h"
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#include <cmath>
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#include <stack>
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#include "ecmascript/compiler/gate_accessor.h"
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#include "ecmascript/compiler/verifier.h"
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namespace panda::ecmascript::kungfu {
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size_t UnionFind(std::vector<size_t> &semiDom, std::vector<size_t> &parent, std::vector<size_t> &minIdx, size_t idx)
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{
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std::stack<size_t> allIdxs;
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allIdxs.emplace(idx);
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size_t pIdx = parent[idx];
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while (pIdx != allIdxs.top()) {
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allIdxs.emplace(pIdx);
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pIdx = parent[pIdx];
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}
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size_t unionFindSetRoot = pIdx;
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while (!allIdxs.empty()) {
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if (semiDom[minIdx[allIdxs.top()]] > semiDom[minIdx[pIdx]]) {
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minIdx[allIdxs.top()] = minIdx[pIdx];
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}
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parent[allIdxs.top()] = unionFindSetRoot;
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pIdx = allIdxs.top();
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allIdxs.pop();
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}
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return unionFindSetRoot;
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}
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void Scheduler::CalculateDominatorTree(const Circuit *circuit,
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std::vector<GateRef>& bbGatesList,
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std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
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std::vector<size_t> &immDom)
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{
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GateAccessor acc(const_cast<Circuit*>(circuit));
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std::unordered_map<GateRef, size_t> dfsTimestamp;
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std::unordered_map<GateRef, size_t> dfsFatherIdx;
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circuit->AdvanceTime();
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{
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size_t timestamp = 0;
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std::deque<GateRef> pendingList;
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auto startGate = acc.GetStateRoot();
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acc.SetMark(startGate, MarkCode::VISITED);
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pendingList.push_back(startGate);
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while (!pendingList.empty()) {
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auto curGate = pendingList.back();
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dfsTimestamp[curGate] = timestamp++;
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pendingList.pop_back();
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bbGatesList.push_back(curGate);
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if (acc.GetOpCode(curGate) != OpCode::LOOP_BACK) {
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auto uses = acc.Uses(curGate);
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for (auto useIt = uses.begin(); useIt != uses.end(); useIt++) {
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if (useIt.GetIndex() < acc.GetStateCount(*useIt) &&
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acc.IsState(*useIt) && acc.GetMark(*useIt) == MarkCode::NO_MARK) {
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acc.SetMark(*useIt, MarkCode::VISITED);
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pendingList.push_back(*useIt);
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dfsFatherIdx[*useIt] = dfsTimestamp[curGate];
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}
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}
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}
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}
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for (size_t idx = 0; idx < bbGatesList.size(); idx++) {
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bbGatesAddrToIdx[bbGatesList[idx]] = idx;
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}
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}
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immDom.resize(bbGatesList.size());
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std::vector<size_t> semiDom(bbGatesList.size());
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std::vector<std::vector<size_t> > semiDomTree(bbGatesList.size());
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{
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std::vector<size_t> parent(bbGatesList.size());
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std::iota(parent.begin(), parent.end(), 0);
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std::vector<size_t> minIdx(bbGatesList.size());
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auto merge = [&] (size_t fatherIdx, size_t sonIdx) -> void {
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size_t parentFatherIdx = UnionFind(semiDom, parent, minIdx, fatherIdx);
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size_t parentSonIdx = UnionFind(semiDom, parent, minIdx, sonIdx);
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parent[parentSonIdx] = parentFatherIdx;
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};
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std::iota(semiDom.begin(), semiDom.end(), 0);
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semiDom[0] = semiDom.size();
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ASSERT(bbGatesList.size() > 0);
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for (size_t idx = bbGatesList.size() - 1; idx >= 1; idx--) {
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std::vector<GateRef> preGates;
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acc.GetInStates(bbGatesList[idx], preGates);
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for (const auto &predGate : preGates) {
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if (bbGatesAddrToIdx.count(predGate) > 0) {
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size_t preGateIdx = bbGatesAddrToIdx[predGate];
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if (preGateIdx < idx) {
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semiDom[idx] = std::min(semiDom[idx], preGateIdx);
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} else {
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UnionFind(semiDom, parent, minIdx, preGateIdx);
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semiDom[idx] = std::min(semiDom[idx], semiDom[minIdx[preGateIdx]]);
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}
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}
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}
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for (const auto &succDomIdx : semiDomTree[idx]) {
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UnionFind(semiDom, parent, minIdx, succDomIdx);
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if (idx == semiDom[minIdx[succDomIdx]]) {
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immDom[succDomIdx] = idx;
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} else {
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immDom[succDomIdx] = minIdx[succDomIdx];
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}
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}
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minIdx[idx] = idx;
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merge(dfsFatherIdx[bbGatesList[idx]], idx);
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semiDomTree[semiDom[idx]].push_back(idx);
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}
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for (size_t idx = 1; idx < bbGatesList.size(); idx++) {
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if (immDom[idx] != semiDom[idx]) {
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immDom[idx] = immDom[immDom[idx]];
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}
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}
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semiDom[0] = 0;
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}
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}
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void Scheduler::Run(const Circuit *circuit, ControlFlowGraph &result,
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[[maybe_unused]] const std::string& methodName, [[maybe_unused]] bool enableLog)
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{
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GateAccessor acc(const_cast<Circuit*>(circuit));
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std::vector<GateRef> bbGatesList;
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std::unordered_map<GateRef, size_t> bbGatesAddrToIdx;
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std::vector<size_t> immDom;
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Scheduler::CalculateDominatorTree(circuit, bbGatesList, bbGatesAddrToIdx, immDom);
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ASSERT(result.size() == 0);
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result.resize(bbGatesList.size());
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for (size_t idx = 0; idx < bbGatesList.size(); idx++) {
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result[idx].push_back(bbGatesList[idx]);
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}
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// assuming CFG is always reducible
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std::vector<std::vector<size_t>> sonList(result.size());
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for (size_t idx = 1; idx < immDom.size(); idx++) {
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sonList[immDom[idx]].push_back(idx);
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}
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const size_t sizeLog = std::ceil(std::log2(static_cast<double>(result.size())) + 1);
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std::vector<size_t> timeIn(result.size());
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std::vector<size_t> timeOut(result.size());
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std::vector<std::vector<size_t>> jumpUp;
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jumpUp.assign(result.size(), std::vector<size_t>(sizeLog + 1));
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{
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size_t timestamp = 0;
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struct DFSState {
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size_t cur;
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std::vector<size_t> &succList;
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size_t idx;
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};
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std::stack<DFSState> dfsStack;
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size_t root = 0;
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dfsStack.push({root, sonList[root], 0});
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timeIn[root] = timestamp++;
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jumpUp[root][0] = root;
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for (size_t stepSize = 1; stepSize <= sizeLog; stepSize++) {
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auto jumpUpHalf = jumpUp[root][stepSize - 1];
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jumpUp[root][stepSize] = jumpUp[jumpUpHalf][stepSize - 1];
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}
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while (!dfsStack.empty()) {
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auto &curState = dfsStack.top();
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auto &cur = curState.cur;
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auto &succList = curState.succList;
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auto &idx = curState.idx;
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if (idx == succList.size()) {
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timeOut[cur] = timestamp++;
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dfsStack.pop();
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continue;
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}
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const auto &succ = succList[idx];
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dfsStack.push({succ, sonList[succ], 0});
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timeIn[succ] = timestamp++;
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jumpUp[succ][0] = cur;
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for (size_t stepSize = 1; stepSize <= sizeLog; stepSize++) {
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auto jumpUpHalf = jumpUp[succ][stepSize - 1];
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jumpUp[succ][stepSize] = jumpUp[jumpUpHalf][stepSize - 1];
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}
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idx++;
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}
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}
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auto isAncestor = [&](size_t nodeA, size_t nodeB) -> bool {
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return (timeIn[nodeA] <= timeIn[nodeB]) && (timeOut[nodeA] >= timeOut[nodeB]);
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};
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auto lowestCommonAncestor = [&](size_t nodeA, size_t nodeB) -> size_t {
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if (isAncestor(nodeA, nodeB)) {
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return nodeA;
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}
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if (isAncestor(nodeB, nodeA)) {
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return nodeB;
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}
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for (size_t stepSize = sizeLog + 1; stepSize > 0; stepSize--) {
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if (!isAncestor(jumpUp[nodeA][stepSize - 1], nodeB)) {
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nodeA = jumpUp[nodeA][stepSize - 1];
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}
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}
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return jumpUp[nodeA][0];
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};
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{
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std::vector<GateRef> order;
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std::unordered_map<GateRef, size_t> lowerBound;
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Scheduler::CalculateSchedulingLowerBound(circuit, bbGatesAddrToIdx, lowestCommonAncestor, lowerBound, &order);
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for (const auto &schedulableGate : order) {
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result[lowerBound.at(schedulableGate)].push_back(schedulableGate);
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}
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std::vector<GateRef> argList;
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acc.GetOuts(acc.GetArgRoot(), argList);
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std::sort(argList.begin(), argList.end(), [&](const GateRef &lhs, const GateRef &rhs) -> bool {
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return acc.TryGetValue(lhs) > acc.TryGetValue(rhs);
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});
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for (const auto &arg : argList) {
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result.front().push_back(arg);
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}
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for (const auto &bbGate : bbGatesList) {
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auto uses = acc.Uses(bbGate);
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for (auto i = uses.begin(); i != uses.end(); i++) {
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GateRef succGate = *i;
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if (acc.IsFixed(succGate)) {
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result[bbGatesAddrToIdx.at(acc.GetIn(succGate, 0))].push_back(succGate);
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}
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}
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}
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}
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if (enableLog) {
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Print(&result, circuit);
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}
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}
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bool Scheduler::CalculateSchedulingUpperBound(const Circuit *circuit,
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const std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
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const std::function<bool(size_t, size_t)> &isAncestor,
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const std::vector<GateRef> &schedulableGatesList,
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std::unordered_map<GateRef, size_t> &upperBound)
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{
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GateAccessor acc(const_cast<Circuit*>(circuit));
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struct DFSState {
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GateRef curGate = Circuit::NullGate();
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std::vector<GateRef> predGates;
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size_t idx = 0;
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size_t curUpperBound = 0;
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};
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DFSState emptyState = {Circuit::NullGate(), std::vector<GateRef>(0), 0, 0};
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bool getReturn = false;
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std::optional<size_t> returnValue = 0;
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std::stack<DFSState> dfsStack;
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auto CheckUnschedulable = [&](GateRef gate) -> void {
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if (upperBound.count(gate) > 0) {
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returnValue = upperBound[gate];
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getReturn = true;
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} else if (acc.IsProlog(gate) || acc.IsRoot(gate) || acc.IsVirtualState(gate)) {
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returnValue = 0;
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getReturn = true;
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} else if (acc.IsFixed(gate)) {
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returnValue = bbGatesAddrToIdx.at(acc.GetIn(gate, 0));
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getReturn = true;
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} else if (acc.IsState(gate)) {
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returnValue = bbGatesAddrToIdx.at(gate);
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getReturn = true;
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}
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// then gate is schedulable
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};
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for (const auto &schedulableGate : schedulableGatesList) {
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if (upperBound.count(schedulableGate) != 0) {
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continue;
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}
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getReturn = false;
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CheckUnschedulable(schedulableGate);
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if (getReturn) {
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continue;
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}
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dfsStack.push(emptyState);
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auto &rootState = dfsStack.top();
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auto &rootPredGates = rootState.predGates;
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rootState.curGate = schedulableGate;
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acc.GetIns(schedulableGate, rootPredGates);
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while (!dfsStack.empty()) {
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auto &curState = dfsStack.top();
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auto &curGate = curState.curGate;
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const auto &predGates = curState.predGates;
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auto &idx = curState.idx;
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auto &curUpperBound = curState.curUpperBound;
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if (idx == predGates.size()) {
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upperBound[curGate] = curUpperBound;
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returnValue = curUpperBound;
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dfsStack.pop();
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getReturn = true;
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continue;
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}
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if (getReturn) {
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if (!returnValue.has_value()) {
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break;
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}
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auto predUpperBound = returnValue.value();
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if (!isAncestor(curUpperBound, predUpperBound) && !isAncestor(predUpperBound, curUpperBound)) {
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PrintUpperBoundError(circuit, curGate, predUpperBound, curUpperBound);
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returnValue = std::nullopt;
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break;
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}
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if (isAncestor(curUpperBound, predUpperBound)) {
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curUpperBound = predUpperBound;
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}
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getReturn = false;
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idx++;
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} else {
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const auto &predGate = predGates[idx];
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CheckUnschedulable(predGate);
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if (getReturn) {
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continue;
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}
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dfsStack.push(emptyState);
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auto &newState = dfsStack.top();
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auto &newPredGates = newState.predGates;
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newState.curGate = predGate;
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acc.GetIns(predGate, newPredGates);
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}
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}
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if (!returnValue.has_value()) {
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return false;
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}
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}
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return true;
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}
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void Scheduler::PrintUpperBoundError(const Circuit *circuit, GateRef curGate,
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GateRef predUpperBound, GateRef curUpperBound)
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{
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GateAccessor ac(const_cast<Circuit*>(circuit));
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LOG_COMPILER(ERROR) << "[Verifier][Error] Scheduling upper bound of gate (id="
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<< ac.GetId(curGate)
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<< ") does not exist, current-upper-bound = "
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<< curUpperBound << ", pred-upper-bound = "
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<< predUpperBound << ", there is no dominator relationship between them.";
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}
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void Scheduler::CalculateFixedGatesList(const Circuit *circuit,
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const std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
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std::vector<GateRef> &bbAndFixedGatesList)
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{
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GateAccessor acc(const_cast<Circuit*>(circuit));
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for (const auto &item : bbGatesAddrToIdx) {
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bbAndFixedGatesList.push_back(item.first);
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auto uses = acc.Uses(item.first);
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for (auto i = uses.begin(); i != uses.end(); i++) {
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GateRef succGate = *i;
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if (acc.IsFixed(succGate)) {
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bbAndFixedGatesList.push_back(succGate);
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}
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}
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}
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}
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void Scheduler::CalculateSchedulingLowerBound(const Circuit *circuit,
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const std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
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const std::function<size_t(size_t, size_t)> &lowestCommonAncestor,
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std::unordered_map<GateRef, size_t> &lowerBound,
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std::vector<GateRef> *order)
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{
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GateAccessor acc(const_cast<Circuit*>(circuit));
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std::vector<GateRef> bbAndFixedGatesList;
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CalculateFixedGatesList(circuit, bbGatesAddrToIdx, bbAndFixedGatesList);
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std::unordered_map<GateRef, size_t> useCount;
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struct DFSVisitState {
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std::vector<GateRef> prevGates;
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size_t idx = 0;
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};
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DFSVisitState emptyVisitState = {std::vector<GateRef>(0), 0};
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std::stack<DFSVisitState> dfsVisitStack;
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for (const auto &gate : bbAndFixedGatesList) {
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dfsVisitStack.push(emptyVisitState);
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auto &rootState = dfsVisitStack.top();
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auto &rootPrevGates = rootState.prevGates;
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acc.GetIns(gate, rootPrevGates);
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while (!dfsVisitStack.empty()) {
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auto &curState = dfsVisitStack.top();
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auto &prevGates = curState.prevGates;
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auto &idx = curState.idx;
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if (idx == prevGates.size()) {
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dfsVisitStack.pop();
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continue;
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}
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const auto &prevGate = prevGates[idx];
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if (!acc.IsSchedulable(prevGate)) {
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++idx;
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continue;
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}
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useCount[prevGate]++;
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if (useCount[prevGate] == 1) {
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dfsVisitStack.push(emptyVisitState);
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auto &newState = dfsVisitStack.top();
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auto &newPrevGates = newState.prevGates;
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acc.GetIns(prevGate, newPrevGates);
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}
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++idx;
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}
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}
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struct DFSFinishState {
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GateRef curGate = Circuit::NullGate();
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std::vector<GateRef> prevGates;
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size_t idx = 0;
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};
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DFSFinishState emptyFinishState = {Circuit::NullGate(), std::vector<GateRef>(0), 0};
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std::stack<DFSFinishState> dfsFinishStack;
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for (const auto &gate : bbAndFixedGatesList) {
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dfsFinishStack.push(emptyFinishState);
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auto &rootState = dfsFinishStack.top();
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auto &rootPrevGates = rootState.prevGates;
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rootState.curGate = gate;
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acc.GetIns(gate, rootPrevGates);
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while (!dfsFinishStack.empty()) {
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auto &curState = dfsFinishStack.top();
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auto &curGate = curState.curGate;
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auto &prevGates = curState.prevGates;
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auto &idx = curState.idx;
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if (idx == prevGates.size()) {
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dfsFinishStack.pop();
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continue;
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}
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const auto &prevGate = prevGates[idx];
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if (!acc.IsSchedulable(prevGate)) {
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++idx;
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continue;
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}
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useCount[prevGate]--;
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size_t curLowerBound;
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if (acc.IsState(curGate)) { // cur_opcode would not be STATE_ENTRY
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curLowerBound = bbGatesAddrToIdx.at(curGate);
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} else if (acc.IsSelector(curGate)) {
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ASSERT(idx > 0);
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curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(acc.GetIn(curGate, 0), idx - 1));
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} else if (acc.IsFixed(curGate)) {
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ASSERT(idx > 0);
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curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(curGate, 0));
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} else {
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curLowerBound = lowerBound.at(curGate);
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}
|
|
if (lowerBound.count(prevGate) == 0) {
|
|
lowerBound[prevGate] = curLowerBound;
|
|
} else {
|
|
lowerBound[prevGate] = lowestCommonAncestor(lowerBound[prevGate], curLowerBound);
|
|
}
|
|
if (useCount[prevGate] == 0) {
|
|
if (order != nullptr) {
|
|
order->push_back(prevGate);
|
|
}
|
|
dfsFinishStack.push(emptyFinishState);
|
|
auto &newState = dfsFinishStack.top();
|
|
auto &newPrevGates = newState.prevGates;
|
|
newState.curGate = prevGate;
|
|
acc.GetIns(prevGate, newPrevGates);
|
|
}
|
|
++idx;
|
|
}
|
|
}
|
|
}
|
|
|
|
void Scheduler::Print(const std::vector<std::vector<GateRef>> *cfg, const Circuit *circuit)
|
|
{
|
|
GateAccessor acc(const_cast<Circuit*>(circuit));
|
|
std::vector<GateRef> bbGatesList;
|
|
std::unordered_map<GateRef, size_t> bbGatesAddrToIdx;
|
|
std::vector<size_t> immDom;
|
|
Scheduler::CalculateDominatorTree(circuit, bbGatesList, bbGatesAddrToIdx, immDom);
|
|
LOG_COMPILER(INFO) << "==================================== Scheduling ==================================";
|
|
for (size_t bbIdx = 0; bbIdx < cfg->size(); bbIdx++) {
|
|
auto opcode = acc.GetOpCode((*cfg)[bbIdx].front());
|
|
LOG_COMPILER(INFO) << "B" << bbIdx << "_" << opcode << ":"
|
|
<< " immDom=" << immDom[bbIdx];
|
|
LOG_COMPILER(INFO) << " pred=[";
|
|
bool isFirst = true;
|
|
GateRef head = cfg->at(bbIdx).front();
|
|
auto ins = acc.Ins(head);
|
|
for (auto i = ins.begin(); i != ins.end(); i++) {
|
|
GateRef predState = *i;
|
|
if (acc.IsState(predState) ||
|
|
acc.GetOpCode(predState) == OpCode::STATE_ENTRY) {
|
|
LOG_COMPILER(INFO) << (isFirst ? "" : " ") << bbGatesAddrToIdx.at(predState);
|
|
isFirst = false;
|
|
}
|
|
}
|
|
LOG_COMPILER(INFO) << "] succ=[";
|
|
isFirst = true;
|
|
GateRef h = cfg->at(bbIdx).front();
|
|
auto uses = acc.Uses(h);
|
|
for (auto i = uses.begin(); i != uses.end(); i++) {
|
|
GateRef succState = *i;
|
|
if (acc.IsState(succState) ||
|
|
acc.GetOpCode(succState) == OpCode::STATE_ENTRY) {
|
|
LOG_COMPILER(INFO) << (isFirst ? "" : " ") << bbGatesAddrToIdx.at(succState);
|
|
isFirst = false;
|
|
}
|
|
}
|
|
LOG_COMPILER(INFO) << "]";
|
|
for (size_t instIdx = (*cfg)[bbIdx].size(); instIdx > 0; instIdx--) {
|
|
acc.Print((*cfg)[bbIdx][instIdx - 1]);
|
|
}
|
|
}
|
|
LOG_COMPILER(INFO) << "==================================== Scheduling ==================================";
|
|
}
|
|
} // namespace panda::ecmascript::kungfu
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