From 06b7cdacc5e0727ebbf1d7b091dfdbc567db4f06 Mon Sep 17 00:00:00 2001 From: zhaoxc0502 Date: Thu, 21 Jul 2022 17:16:10 +0800 Subject: [PATCH 1/5] modify beta2 format Signed-off-by: zhaoxc0502 --- imx8mm/drivers/audio/codec/src/wm8904.c | 88 +- imx8mm/drivers/audio/soc/src/sai_driver.c | 1003 +++++++++-------- .../wifi/ap6212/hdfadapter/hdf_mac80211.c | 79 +- 3 files changed, 657 insertions(+), 513 deletions(-) diff --git a/imx8mm/drivers/audio/codec/src/wm8904.c b/imx8mm/drivers/audio/codec/src/wm8904.c index 5147d77..f9dd444 100644 --- a/imx8mm/drivers/audio/codec/src/wm8904.c +++ b/imx8mm/drivers/audio/codec/src/wm8904.c @@ -722,33 +722,8 @@ struct AudioPcmHwParams g_PcmParams = {0}; #define FORMAT_HW (16385) #define RATE_MULTIPLE (10) #define LOW_SAMPLE_RATES (24000) -int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwParams *param) +int WM8904GetAif1(int width, unsigned int *aif1) { - int fs = 0, width = 0, channel = 0, slots = 0, dir = 0; - int ret = 0, i = 0, best = 0, best_val = 0, cur_val = 0, errno = 0; - unsigned int aif1 = 0, aif2 = 0, aif3 = 0, clock1 = 0, dac_digital1 = 0; - - errno = memcpy_s(&g_PcmParams, sizeof(struct AudioPcmHwParams), param, sizeof(struct AudioPcmHwParams)); - if (errno != 0) { - WM8904_CODEC_LOG_ERR("Memcpy pcm parameters failed!"); - } - - fs = param->rate; - Frame_To_Bit_Width(param->format, &width); - channel = param->channels; - slots = 1; - - dir = param->streamType == AUDIO_RENDER_STREAM ? 1 : 0; - - WM8904_Set_Fmt(FORMAT_HW); - msleep(SLEEP_TIME_10); - WM8904_Set_Sysclk(1, 0); - msleep(SLEEP_TIME_10); - - /* What BCLK do we need? */ - gpwm8904->fs = fs; - gpwm8904->bclk = fs * width * channel * slots; - switch (width) { case BIT_WIDTH_16: break; @@ -764,14 +739,13 @@ int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwPa default: return -EINVAL; } + return HDF_SUCCESS; +} - ret = WM8904_Configure_Clocking(); - if (ret != 0) { - return ret; - } - +void WM8904HwParamsGetClkRate(unsigned int *dac_digital1, unsigned int *aif2, unsigned int *aif3, unsigned int *clock1) +{ + int ret = 0, i = 0, best = 0, best_val = 0, cur_val = 0; /* Select nearest CLK_SYS_RATE */ - best = 0; best_val = abs((gpwm8904->sysclk_rate / clk_sys_rates[0].ratio) - gpwm8904->fs); for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { cur_val = abs((gpwm8904->sysclk_rate / clk_sys_rates[i].ratio) - gpwm8904->fs); @@ -780,7 +754,7 @@ int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwPa best_val = cur_val; } } - clock1 |= (clk_sys_rates[best].clk_sys_rate << WM8904_CLK_SYS_RATE_SHIFT); + *clock1 |= (clk_sys_rates[best].clk_sys_rate << WM8904_CLK_SYS_RATE_SHIFT); /* SAMPLE_RATE */ best = 0; @@ -793,12 +767,12 @@ int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwPa best_val = cur_val; } } - WM8904_CODEC_LOG_DEBUG("Selected SAMPLE_RATE of %dHz", sample_rates[best].rate); - clock1 |= (sample_rates[best].sample_rate << WM8904_SAMPLE_RATE_SHIFT); + WM8904_CODEC_LOG_DEBUG("Selected SAMPLE_RATE of %dHz", sample_rates[best].rate); + *clock1 |= (sample_rates[best].sample_rate << WM8904_SAMPLE_RATE_SHIFT); /* Enable sloping stopband filter for low sample rates */ if (gpwm8904->fs <= LOW_SAMPLE_RATES) { - dac_digital1 |= WM8904_DAC_SB_FILT; + *dac_digital1 |= WM8904_DAC_SB_FILT; } /* BCLK_DIV */ @@ -815,17 +789,51 @@ int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwPa } } gpwm8904->bclk = (gpwm8904->sysclk_rate * RATE_MULTIPLE) / bclk_divs[best].div; + *aif2 |= bclk_divs[best].bclk_div; + *aif3 |= gpwm8904->bclk / gpwm8904->fs; +} - aif2 |= bclk_divs[best].bclk_div; - aif3 |= gpwm8904->bclk / gpwm8904->fs; +int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwParams *param) +{ + int fs = 0, width = 0, channel = 0, slots = 1, dir = 0, ret = 0, errno = 0; + unsigned int aif1 = 0, aif2 = 0, aif3 = 0, clock1 = 0, dac_digital1 = 0; + + errno = memcpy_s(&g_PcmParams, sizeof(struct AudioPcmHwParams), param, sizeof(struct AudioPcmHwParams)); + if (errno != 0) { + WM8904_CODEC_LOG_ERR("Memcpy pcm parameters failed!"); + } + + fs = param->rate; + channel = param->channels; + dir = param->streamType == AUDIO_RENDER_STREAM ? 1 : 0; + Frame_To_Bit_Width(param->format, &width); + + WM8904_Set_Fmt(FORMAT_HW); + msleep(SLEEP_TIME_10); + WM8904_Set_Sysclk(1, 0); + msleep(SLEEP_TIME_10); + + /* What BCLK do we need? */ + gpwm8904->fs = fs; + gpwm8904->bclk = fs * width * channel * slots; + + ret = WM8904GetAif1(&aif1); + if (ret != 0) { + return ret; + } + + ret = WM8904_Configure_Clocking(); + if (ret != 0) { + return ret; + } + WM8904HwParamsGetClkRate(&dac_digital1, &aif2, &aif3, &clock1); /* Apply the settings */ WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_1, WM8904_DAC_SB_FILT, dac_digital1, BYTE_NUM); WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_1, WM8904_AIF_WL_MASK, aif1, BYTE_NUM); WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_2, WM8904_BCLK_DIV_MASK, aif2, BYTE_NUM); WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_3, WM8904_LRCLK_RATE_MASK, aif3, BYTE_NUM); - WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_1, - WM8904_SAMPLE_RATE_MASK | WM8904_CLK_SYS_RATE_MASK, clock1, BYTE_NUM); + WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_1, WM8904_SAMPLE_RATE_MASK | WM8904_CLK_SYS_RATE_MASK, clock1, BYTE_NUM); /* Update filters for the new settings */ WM8904_Set_Retune_Mobile(); diff --git a/imx8mm/drivers/audio/soc/src/sai_driver.c b/imx8mm/drivers/audio/soc/src/sai_driver.c index dc06410..1dd38e0 100644 --- a/imx8mm/drivers/audio/soc/src/sai_driver.c +++ b/imx8mm/drivers/audio/soc/src/sai_driver.c @@ -68,38 +68,11 @@ static struct fsl_sai *GetDrvSai(const struct PlatformData *pd) return NULL; } -int32_t SaiPrintAllRegister() +int32_t SaiPrintTFRegister() { struct fsl_sai *sai = g_sai; u32 read_val = 0; - regmap_read(sai->regmap, FSL_SAI_TCSR(BYTE_NUM), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCSR %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TCR1(BYTE_NUM), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR1 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TCR2(BYTE_NUM), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR2 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TCR3(BYTE_NUM), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR3 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TCR4(BYTE_NUM), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR4 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TCR5(BYTE_NUM), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR5 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR0, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR0 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR1, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR1 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR2, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR2 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR3, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR3 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR4, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR4 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR5, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR5 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR6, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR6 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_TDR7, &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR7 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TFR0, &read_val); AUDIO_DRIVER_LOG_ERR("FSL_SAI_TFR0 %08x", read_val); regmap_read(sai->regmap, FSL_SAI_TFR1, &read_val); @@ -116,6 +89,55 @@ int32_t SaiPrintAllRegister() AUDIO_DRIVER_LOG_ERR("FSL_SAI_TFR6 %08x", read_val); regmap_read(sai->regmap, FSL_SAI_TFR7, &read_val); AUDIO_DRIVER_LOG_ERR("FSL_SAI_TFR7 %08x", read_val); + + return 0; +} + +int32_t SaiPrintTDRegister() +{ + struct fsl_sai *sai = g_sai; + u32 read_val = 0; + + regmap_read(sai->regmap, FSL_SAI_TDR0, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR0 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR1, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR1 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR2, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR2 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR3, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR3 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR4, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR4 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR5, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR5 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR6, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR6 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TDR7, &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TDR7 %08x", read_val); + + return 0; +} + +int32_t SaiPrintAllRegister() +{ + struct fsl_sai *sai = g_sai; + u32 read_val = 0; + regmap_read(sai->regmap, FSL_SAI_TCSR(BYTE_NUM), &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCSR %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TCR1(BYTE_NUM), &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR1 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TCR2(BYTE_NUM), &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR2 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TCR3(BYTE_NUM), &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR3 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TCR4(BYTE_NUM), &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR4 %08x", read_val); + regmap_read(sai->regmap, FSL_SAI_TCR5(BYTE_NUM), &read_val); + AUDIO_DRIVER_LOG_ERR("FSL_SAI_TCR5 %08x", read_val); + + SaiPrintTDRegister(); + SaiPrintTFRegister(); + regmap_read(sai->regmap, FSL_SAI_TMR, &read_val); AUDIO_DRIVER_LOG_ERR("FSL_SAI_TMR %08x", read_val); regmap_read(sai->regmap, FSL_SAI_TTCTL, &read_val); @@ -132,6 +154,43 @@ int32_t SaiPrintAllRegister() return 0; } +static bool fsl_sai_rx_irq(int irq, void *devid) +{ + u32 flags = 0, xcsr = 0, mask = 0; + bool irq_none = true; + struct PrivPlatformData *ppd = (struct PrivPlatformData *)devid; + struct fsl_sai *sai = (struct fsl_sai *)&(ppd->sai); + unsigned char offset = sai->reg_offset; + + regmap_read(sai->regmap, FSL_SAI_RCSR(offset), &xcsr); + flags = xcsr & mask; + + if (flags) { + irq_none = false; + } else { + if (irq_none) { + return IRQ_NONE; + } else { + return IRQ_HANDLED; + } + } + + if (flags & FSL_SAI_CSR_FEF) { + AUDIO_DRIVER_LOG_ERR("isr: Receive overflow detected\n"); + /* FIFO reset for safety */ + xcsr |= FSL_SAI_CSR_FR; + } + + flags &= FSL_SAI_CSR_xF_W_MASK; + xcsr &= ~FSL_SAI_CSR_xF_MASK; + + if (flags) { + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), flags | xcsr); + } + + return irq_none; +} + static irqreturn_t fsl_sai_isr(int irq, void *devid) { struct PrivPlatformData *ppd = (struct PrivPlatformData *)devid; @@ -164,28 +223,12 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) } } - if (flags & FSL_SAI_CSR_WSF) { - AUDIO_DRIVER_LOG_ERR("isr: Start of Rx word detected\n"); - } - - if (flags & FSL_SAI_CSR_SEF) { - AUDIO_DRIVER_LOG_ERR("isr: Rx Frame sync error detected\n"); - } - if (flags & FSL_SAI_CSR_FEF) { AUDIO_DRIVER_LOG_ERR("isr: Receive overflow detected\n"); /* FIFO reset for safety */ xcsr |= FSL_SAI_CSR_FR; } - if (flags & FSL_SAI_CSR_FWF) { - AUDIO_DRIVER_LOG_ERR("isr: Enabled receive FIFO is full\n"); - } - - if (flags & FSL_SAI_CSR_FRF) { - AUDIO_DRIVER_LOG_ERR("isr: Receive FIFO watermark has been reached\n"); - } - flags &= FSL_SAI_CSR_xF_W_MASK; xcsr &= ~FSL_SAI_CSR_xF_MASK; @@ -200,28 +243,12 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) } } - if (flags & FSL_SAI_CSR_WSF) { - AUDIO_DRIVER_LOG_ERR("isr: Start of Tx word detected\n"); - } - - if (flags & FSL_SAI_CSR_SEF) { - AUDIO_DRIVER_LOG_ERR("isr: Tx Frame sync error detected\n"); - } - if (flags & FSL_SAI_CSR_FEF) { AUDIO_DRIVER_LOG_ERR("isr: Transmit underrun detected\n"); /* FIFO reset for safety */ xcsr |= FSL_SAI_CSR_FR; } - if (flags & FSL_SAI_CSR_FWF) { - AUDIO_DRIVER_LOG_ERR("isr: Enabled transmit FIFO is empty\n"); - } - - if (flags & FSL_SAI_CSR_FRF) { - AUDIO_DRIVER_LOG_ERR("isr: Transmit FIFO watermark has been reached\n"); - } - flags &= FSL_SAI_CSR_xF_W_MASK; xcsr &= ~FSL_SAI_CSR_xF_MASK; @@ -230,47 +257,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) } /* Rx IRQ */ - regmap_read(sai->regmap, FSL_SAI_RCSR(offset), &xcsr); - flags = xcsr & mask; - - if (flags) { - irq_none = false; - } else { - if (irq_none) { - return IRQ_NONE; - } else { - return IRQ_HANDLED; - } - } - - if (flags & FSL_SAI_CSR_WSF) { - AUDIO_DRIVER_LOG_ERR("isr: Start of Rx word detected\n"); - } - - if (flags & FSL_SAI_CSR_SEF) { - AUDIO_DRIVER_LOG_ERR("isr: Rx Frame sync error detected\n"); - } - - if (flags & FSL_SAI_CSR_FEF) { - AUDIO_DRIVER_LOG_ERR("isr: Receive overflow detected\n"); - /* FIFO reset for safety */ - xcsr |= FSL_SAI_CSR_FR; - } - - if (flags & FSL_SAI_CSR_FWF) { - AUDIO_DRIVER_LOG_ERR("isr: Enabled receive FIFO is full\n"); - } - - if (flags & FSL_SAI_CSR_FRF) { - AUDIO_DRIVER_LOG_ERR("isr: Receive FIFO watermark has been reached\n"); - } - - flags &= FSL_SAI_CSR_xF_W_MASK; - xcsr &= ~FSL_SAI_CSR_xF_MASK; - - if (flags) { - regmap_write(sai->regmap, FSL_SAI_RCSR(offset), flags | xcsr); - } + irq_none = fsl_sai_rx_irq(irq, devid); if (irq_none) { return IRQ_NONE; @@ -304,6 +291,61 @@ static struct reg_default fsl_sai_v3_reg_defaults[] = { {FSL_SAI_MDIV, 0}, }; +static bool fsl_sai_readable_tfr_reg(unsigned int reg) +{ + bool ret = false; + switch (reg) { + case FSL_SAI_TFR0: fallthrough; + case FSL_SAI_TFR1: fallthrough; + case FSL_SAI_TFR2: fallthrough; + case FSL_SAI_TFR3: fallthrough; + case FSL_SAI_TFR4: fallthrough; + case FSL_SAI_TFR5: fallthrough; + case FSL_SAI_TFR6: fallthrough; + case FSL_SAI_TFR7: + ret = true; + break; + + default: + ret = false; + break; + } + + return ret; +} + +static bool fsl_sai_readable_rxr_reg(unsigned int reg) +{ + bool ret = false; + switch (reg) { + case FSL_SAI_RDR0: fallthrough; + case FSL_SAI_RDR1: fallthrough; + case FSL_SAI_RDR2: fallthrough; + case FSL_SAI_RDR3: fallthrough; + case FSL_SAI_RDR4: fallthrough; + case FSL_SAI_RDR5: fallthrough; + case FSL_SAI_RDR6: fallthrough; + case FSL_SAI_RDR7: fallthrough; + case FSL_SAI_RFR0: fallthrough; + case FSL_SAI_RFR1: fallthrough; + case FSL_SAI_RFR2: fallthrough; + case FSL_SAI_RFR3: fallthrough; + case FSL_SAI_RFR4: fallthrough; + case FSL_SAI_RFR5: fallthrough; + case FSL_SAI_RFR6: fallthrough; + case FSL_SAI_RFR7: fallthrough; + case FSL_SAI_RMR: + ret = true; + break; + + default: + ret = false; + break; + } + + return ret; +} + static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) { struct fsl_sai *sai = dev_get_drvdata(dev); @@ -317,44 +359,27 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) return true; } + if (fsl_sai_readable_tfr_reg(reg) == true) { + return true; + } + + if (fsl_sai_readable_rxr_reg(reg) == true) { + return true; + } + switch (reg) { - case FSL_SAI_TFR0: - case FSL_SAI_TFR1: - case FSL_SAI_TFR2: - case FSL_SAI_TFR3: - case FSL_SAI_TFR4: - case FSL_SAI_TFR5: - case FSL_SAI_TFR6: - case FSL_SAI_TFR7: - case FSL_SAI_TMR: - case FSL_SAI_RDR0: - case FSL_SAI_RDR1: - case FSL_SAI_RDR2: - case FSL_SAI_RDR3: - case FSL_SAI_RDR4: - case FSL_SAI_RDR5: - case FSL_SAI_RDR6: - case FSL_SAI_RDR7: - case FSL_SAI_RFR0: - case FSL_SAI_RFR1: - case FSL_SAI_RFR2: - case FSL_SAI_RFR3: - case FSL_SAI_RFR4: - case FSL_SAI_RFR5: - case FSL_SAI_RFR6: - case FSL_SAI_RFR7: - case FSL_SAI_RMR: - case FSL_SAI_MCTL: - case FSL_SAI_MDIV: - case FSL_SAI_VERID: - case FSL_SAI_PARAM: - case FSL_SAI_TTCTN: - case FSL_SAI_RTCTN: - case FSL_SAI_TTCTL: - case FSL_SAI_TBCTN: - case FSL_SAI_TTCAP: - case FSL_SAI_RTCTL: - case FSL_SAI_RBCTN: + case FSL_SAI_TMR: fallthrough; + case FSL_SAI_MCTL: fallthrough; + case FSL_SAI_MDIV: fallthrough; + case FSL_SAI_VERID: fallthrough; + case FSL_SAI_PARAM: fallthrough; + case FSL_SAI_TTCTN: fallthrough; + case FSL_SAI_RTCTN: fallthrough; + case FSL_SAI_TTCTL: fallthrough; + case FSL_SAI_TBCTN: fallthrough; + case FSL_SAI_TTCAP: fallthrough; + case FSL_SAI_RTCTL: fallthrough; + case FSL_SAI_RBCTN: fallthrough; case FSL_SAI_RTCAP: return true; default: @@ -667,71 +692,47 @@ static int fsl_sai_set_bclk(struct fsl_sai *sai, bool tx, u32 freq) return 0; } - -int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType streamType) +struct fsl_hwParams_register { - struct fsl_sai *sai = GetDrvSai(pd); - unsigned char offset = sai->reg_offset; - u32 channels = 0; - u32 rate = 0; - u32 word_width = 0; - bool tx = streamType == AUDIO_RENDER_STREAM; + u32 cr3; + u32 cr4; + u32 cr5; + u32 mr; +}; + +int32_t SaiGetHwParams(const struct PlatformData *pd, const enum AudioStreamType streamType, u32 *channels, u32 *rate, u32 *word_width) +{ + int32_t ret = 0; if (streamType == AUDIO_RENDER_STREAM) { - channels = pd->renderPcmInfo.channels; - rate = pd->renderPcmInfo.rate; - word_width = pd->renderPcmInfo.bitWidth; + *channels = pd->renderPcmInfo.channels; + *rate = pd->renderPcmInfo.rate; + *word_width = pd->renderPcmInfo.bitWidth; } else if (streamType == AUDIO_CAPTURE_STREAM) { - channels = pd->capturePcmInfo.channels; - rate = pd->capturePcmInfo.rate; - word_width = pd->capturePcmInfo.bitWidth; + *channels = pd->capturePcmInfo.channels; + *rate = pd->capturePcmInfo.rate; + *word_width = pd->capturePcmInfo.bitWidth; } else { AUDIO_DRIVER_LOG_ERR("streamType is invaild "); return HDF_FAILURE; } + return ret; +} - u32 val_cr4 = 0, val_cr5 = 0; - u32 slots = (channels == 1) ? 2 : channels; - u32 slot_width = word_width; - u32 pins = 0, bclk = 0; - int32_t ret = 0, i = 0, trce_mask = 0, dl_cfg_cnt, dl_cfg_idx = 0; - struct fsl_sai_dl_cfg *dl_cfg = NULL; +int32_t SaiSetHwParamsPin(struct fsl_sai *sai, u32 channels, u32 *pins, u32 *slots) +{ + int32_t ret = 0; if (sai->slots) { - slots = sai->slots; + *slots = sai->slots; } - pins = DIV_ROUND_UP(channels, slots); - sai->is_dsd = false; - dl_cfg = sai->pcm_dl_cfg; - dl_cfg_cnt = sai->pcm_dl_cfg_cnt; - for (i = 0; i < dl_cfg_cnt; i++) { - if (dl_cfg[i].pins == pins) { - dl_cfg_idx = i; - break; - } - } - - if (dl_cfg_idx >= dl_cfg_cnt) { - AUDIO_DRIVER_LOG_ERR("fsl,dataline%s invalid or not provided.", - sai->is_dsd ? ",dsd" : ""); - return HDF_FAILURE; - } - - if (sai->slot_width) { - slot_width = sai->slot_width; - } - - AUDIO_DRIVER_LOG_ERR("rate = %d, slots = %d, slot_width = %d", rate, slots, slot_width); - - bclk = rate*(sai->bitclk_ratio ? sai->bitclk_ratio : slots * slot_width); + *pins = DIV_ROUND_UP(channels, *slots); if (!IS_ERR_OR_NULL(sai->pinctrl)) { - AUDIO_DRIVER_LOG_ERR("pin cntrl"); sai->pins_state = pinctrl_lookup_state(sai->pinctrl, "default"); if (!IS_ERR_OR_NULL(sai->pins_state)) { - AUDIO_DRIVER_LOG_ERR("pin cntrl"); ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); if (ret) { AUDIO_DRIVER_LOG_ERR("failed to set proper pins state"); @@ -739,7 +740,12 @@ int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType } } } + return ret; +} +int32_t SaiSetHwParamsClk(struct fsl_sai *sai, bool tx, u32 bclk, const enum AudioStreamType streamType) +{ + int32_t ret = 0; if (!sai->slave_mode[tx]) { ret = fsl_sai_set_bclk(sai, tx, bclk); if (ret) { @@ -757,10 +763,12 @@ int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType sai->mclk_streams |= BIT(streamType); } } + return ret; +} - if (!sai->is_dsp_mode) { - val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); - } +u32 SaiGetHwParamsCR5(struct fsl_sai *sai, u32 slot_width, u32 word_width) +{ + u32 val_cr5; val_cr5 |= FSL_SAI_CR5_WNW(slot_width); val_cr5 |= FSL_SAI_CR5_W0W(slot_width); @@ -771,42 +779,75 @@ int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); } + return val_cr5; +} + +u32 SaiGetHwParamsCR4(struct fsl_sai *sai, u32 slot_width, u32 slots) +{ + u32 val_cr4 = 0; + + if (!sai->is_dsp_mode) { + val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); + } val_cr4 |= FSL_SAI_CR4_FRSZ(slots); /* Output Mode - data pins transmit 0 when slots are masked * or channels are disabled */ val_cr4 |= FSL_SAI_CR4_CHMOD; + return val_cr4; +} - /* - * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will - * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), - * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync - * error. - */ +u32 SaiGetdlMask(struct fsl_sai *sai, bool tx, u32 pins) +{ + int32_t i = 0, dl_cfg_cnt, dl_cfg_idx = 0; + struct fsl_sai_dl_cfg *dl_cfg = NULL; + + + sai->is_dsd = false; + dl_cfg = sai->pcm_dl_cfg; + dl_cfg_cnt = sai->pcm_dl_cfg_cnt; + for (i = 0; i < dl_cfg_cnt; i++) { + if (dl_cfg[i].pins == pins) { + dl_cfg_idx = i; + break; + } + } + + if (dl_cfg_idx >= dl_cfg_cnt) { + AUDIO_DRIVER_LOG_ERR("fsl,dataline%s invalid or not provided.", sai->is_dsd ? ",dsd" : ""); + return HDF_FAILURE; + } + + return dl_cfg[dl_cfg_idx].mask[tx]; +} + +SaiSetHwParamsRegister(struct fsl_sai *sai, bool tx, struct fsl_hwParams_register *val, unsigned int dl_mask) +{ + unsigned char offset = sai->reg_offset; if (!sai->slave_mode[tx]) { if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { regmap_update_bits(sai->regmap, FSL_SAI_TCR4(offset), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | FSL_SAI_CR4_CHMOD_MASK, - val_cr4); + val->cr4); regmap_update_bits(sai->regmap, FSL_SAI_TCR5(offset), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | - FSL_SAI_CR5_FBT_MASK, val_cr5); + FSL_SAI_CR5_FBT_MASK, val->cr5); } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { regmap_update_bits(sai->regmap, FSL_SAI_RCR4(offset), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | FSL_SAI_CR4_CHMOD_MASK, - val_cr4); + val->cr4); regmap_update_bits(sai->regmap, FSL_SAI_RCR5(offset), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | - FSL_SAI_CR5_FBT_MASK, val_cr5); + FSL_SAI_CR5_FBT_MASK, val->cr5); } } if (sai->dataline != 0x1) { - if (dl_cfg[dl_cfg_idx].mask[tx] <= 1 || sai->is_multi_lane) { + if (dl_mask <= 1 || sai->is_multi_lane) { regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset), FSL_SAI_CR4_FCOMB_MASK, 0); } else { @@ -815,38 +856,75 @@ int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType } } - if (__sw_hweight8(dl_cfg[dl_cfg_idx].mask[tx] & 0xFF) < pins) { - AUDIO_DRIVER_LOG_ERR("channel not supported"); - return -EINVAL; - } - - /* find a proper tcre setting */ - for (i = 0; i < BYTE_NUM; i++) { - trce_mask = (1 << (i + 1)) - 1; - if (__sw_hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) { - break; - } - } - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset), FSL_SAI_CR3_TRCE_MASK, - FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); + FSL_SAI_CR3_TRCE(val->cr3)); regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | FSL_SAI_CR4_CHMOD_MASK, - val_cr4); + val->cr4); regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | - FSL_SAI_CR5_FBT_MASK, val_cr5); + FSL_SAI_CR5_FBT_MASK, val->cr5); - regmap_write(sai->regmap, FSL_SAI_xMR(tx), - ~0UL - ((1 << min(channels, slots)) - 1)); + regmap_write(sai->regmap, FSL_SAI_xMR(tx), val->mr); return HDF_SUCCESS; } +int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType streamType) +{ + struct fsl_sai *sai = GetDrvSai(pd); + u32 channels = 0, rate = 0, word_width = 0, pins = 0, bclk = 0, slot_width = word_width, slots = (channels == 1) ? 2 : channels; + bool tx = streamType == AUDIO_RENDER_STREAM; + struct fsl_hwParams_register val; + int32_t trce_mask = 0, ret = 0; + unsigned int dl_mask, i; + + ret = SaiGetHwParams(sai, &channels, &rate, &word_width); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiGetHwParams fail ret=%d", ret); + return ret; + } + + ret = SaiSetHwParamsPin(sai, channels, &pins, &slots); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiSetHwParamsPin fail ret=%d", ret); + return ret; + } + + if (sai->slot_width) { + slot_width = sai->slot_width; + } + bclk = rate*(sai->bitclk_ratio ? sai->bitclk_ratio : slots * slot_width); + ret = SaiSetHwParamsClk(sai, tx, bclk, streamType); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiSetHwParamsClk fail ret=%d", ret); + return ret; + } + + val.cr5 = SaiGetHwParamsCR5(sai, slot_width, word_width); + val.cr4 = SaiGetHwParamsCR4(sai, slot_width, slots); + dl_mask = SaiGetdlMask(sai, tx, pins); + if (__sw_hweight8(dl_mask & 0xFF) < pins) { + AUDIO_DRIVER_LOG_ERR("channel not supported"); + return -EINVAL; + } + for (i = 0; i < BYTE_NUM; i++) { + trce_mask = (1 << (i + 1)) - 1; + if (__sw_hweight8(dl_mask & trce_mask) == pins) { + break; + } + } + val.cr3 = dl_mask & trce_mask; + val.mr = ~0UL - ((1 << min(channels, slots)) - 1); + + SaiSetHwParamsRegister(sai, &val, dl_mask); + return HDF_SUCCESS; +} + int32_t SaiSetDaiTdmSlot(const struct PlatformData *pd, int32_t tx_mask, int32_t rx_mask, int32_t slots, int32_t slot_width) { @@ -980,17 +1058,95 @@ int32_t SaiSetSysclk(const struct PlatformData *pd, int clk_id, unsigned int fre return HDF_SUCCESS; } +static int32_t HandleDaiMode(unsigned int fmt, int32_t *val_cr2, int32_t *val_cr4, struct fsl_sai **sai) +{ + /* DAI mode */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + /* + * Frame low, 1clk before data, one word length for frame sync, + * frame sync starts one serial clock cycle earlier, + * that is, together with the last bit of the previous + * data word. + */ + *val_cr2 |= FSL_SAI_CR2_BCP; + *val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; + break; + case SND_SOC_DAIFMT_LEFT_J: + /* + * Frame high, one word length for frame sync, + * frame sync asserts with the first bit of the frame. + */ + *val_cr2 |= FSL_SAI_CR2_BCP; + break; + case SND_SOC_DAIFMT_DSP_A: + /* + * Frame high, 1clk before data, one bit for frame sync, + * frame sync starts one serial clock cycle earlier, + * that is, together with the last bit of the previous + * data word. + */ + *val_cr2 |= FSL_SAI_CR2_BCP; + *val_cr4 |= FSL_SAI_CR4_FSE; + (*sai)->is_dsp_mode = true; + break; + case SND_SOC_DAIFMT_DSP_B: + /* + * Frame high, one bit for frame sync, + * frame sync asserts with the first bit of the frame. + */ + *val_cr2 |= FSL_SAI_CR2_BCP; + (*sai)->is_dsp_mode = true; + break; + case SND_SOC_DAIFMT_PDM: + *val_cr2 |= FSL_SAI_CR2_BCP; + *val_cr4 &= ~FSL_SAI_CR4_MF; + (*sai)->is_dsp_mode = true; + break; + case SND_SOC_DAIFMT_RIGHT_J: + /* To be done */ + default: + return -EINVAL; + } + return 0; +} + +static int32_t HandleDaiCLK(unsigned int fmt, int32_t *val_cr2, int32_t *val_cr4) +{ + /* DAI clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_IB_IF: + /* Invert both clocks */ + *val_cr2 ^= FSL_SAI_CR2_BCP; + *val_cr4 ^= FSL_SAI_CR4_FSP; + break; + case SND_SOC_DAIFMT_IB_NF: + /* Invert bit clock */ + *val_cr2 ^= FSL_SAI_CR2_BCP; + break; + case SND_SOC_DAIFMT_NB_IF: + /* Invert frame clock */ + *val_cr4 ^= FSL_SAI_CR4_FSP; + break; + case SND_SOC_DAIFMT_NB_NF: + /* Nothing to do for both normal cases */ + break; + default: + return -EINVAL; + } + + return 0; +} + static int32_t SaiSetDaiFmtTr(struct PrivPlatformData *ppd, unsigned int fmt, int fsl_dir) { struct fsl_sai *sai = NULL; unsigned char offset = 0; - int32_t val_cr2 = 0; - int32_t val_cr4 = 0; + int32_t val_cr2 = 0, val_cr4 = 0; bool tx = fsl_dir == FSL_FMT_TRANSMITTER; uint32_t read_val; if (ppd == NULL) { - AUDIO_DRIVER_LOG_ERR("pdd is null"); return HDF_FAILURE; } @@ -1002,78 +1158,15 @@ static int32_t SaiSetDaiFmtTr(struct PrivPlatformData *ppd, unsigned int fmt, in } sai->is_dsp_mode = false; - - /* DAI mode */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: - /* - * Frame low, 1clk before data, one word length for frame sync, - * frame sync starts one serial clock cycle earlier, - * that is, together with the last bit of the previous - * data word. - */ - val_cr2 |= FSL_SAI_CR2_BCP; - val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; - break; - case SND_SOC_DAIFMT_LEFT_J: - /* - * Frame high, one word length for frame sync, - * frame sync asserts with the first bit of the frame. - */ - val_cr2 |= FSL_SAI_CR2_BCP; - break; - case SND_SOC_DAIFMT_DSP_A: - /* - * Frame high, 1clk before data, one bit for frame sync, - * frame sync starts one serial clock cycle earlier, - * that is, together with the last bit of the previous - * data word. - */ - val_cr2 |= FSL_SAI_CR2_BCP; - val_cr4 |= FSL_SAI_CR4_FSE; - sai->is_dsp_mode = true; - break; - case SND_SOC_DAIFMT_DSP_B: - /* - * Frame high, one bit for frame sync, - * frame sync asserts with the first bit of the frame. - */ - val_cr2 |= FSL_SAI_CR2_BCP; - sai->is_dsp_mode = true; - break; - case SND_SOC_DAIFMT_PDM: - val_cr2 |= FSL_SAI_CR2_BCP; - val_cr4 &= ~FSL_SAI_CR4_MF; - sai->is_dsp_mode = true; - break; - case SND_SOC_DAIFMT_RIGHT_J: - /* To be done */ - default: - return -EINVAL; + if (HandleDaiMode(fmt, &val_cr2, &val_cr4, &sai) < 0) { + return -EINVAL; } - /* DAI clock inversion */ - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { - case SND_SOC_DAIFMT_IB_IF: - /* Invert both clocks */ - val_cr2 ^= FSL_SAI_CR2_BCP; - val_cr4 ^= FSL_SAI_CR4_FSP; - break; - case SND_SOC_DAIFMT_IB_NF: - /* Invert bit clock */ - val_cr2 ^= FSL_SAI_CR2_BCP; - break; - case SND_SOC_DAIFMT_NB_IF: - /* Invert frame clock */ - val_cr4 ^= FSL_SAI_CR4_FSP; - break; - case SND_SOC_DAIFMT_NB_NF: - /* Nothing to do for both normal cases */ - break; - default: - return -EINVAL; + if (HandleDaiCLK(fmt, &val_cr2, &val_cr4) < 0) { + return -EINVAL; } + sai->slave_mode[tx] = false; /* DAI clock master masks */ @@ -1097,10 +1190,7 @@ static int32_t SaiSetDaiFmtTr(struct PrivPlatformData *ppd, unsigned int fmt, in } regmap_read(sai->regmap, FSL_SAI_xCR2(tx, offset), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_xCR2 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_xCR4(tx, offset), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_xCR4 %08x", read_val); regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, offset), FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); @@ -1109,10 +1199,7 @@ static int32_t SaiSetDaiFmtTr(struct PrivPlatformData *ppd, unsigned int fmt, in FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); regmap_read(sai->regmap, FSL_SAI_xCR2(tx, offset), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_xCR2 %08x", read_val); - regmap_read(sai->regmap, FSL_SAI_xCR4(tx, offset), &read_val); - AUDIO_DRIVER_LOG_ERR("FSL_SAI_xCR4 %08x", read_val); return HDF_SUCCESS; } @@ -1158,45 +1245,17 @@ int32_t SaiHwFree(const struct DaiData *pd, int isTx) #define NUM_128 (128) #define DELAY_10 (10) -int32_t SaiDriverInit(struct PlatformData *pd) +int32_t SaiDriverInitClk(struct PrivPlatformData *ppd, void __iomem *base) { - struct PrivPlatformData *ppd = (struct PrivPlatformData *)pd->dmaPrv; - struct device_node *np = NULL; - struct resource *res = NULL; - struct fsl_sai *sai = NULL; - void __iomem *base = NULL; - char tmp[8]; - int irq = 0, ret = 0, i = 0; + int ret = 0, i = 0;; + struct fsl_sai *sai = &ppd->sai; unsigned long clk_rate = 0; - int ret = 0; + char tmp[8]; - sai = &ppd->sai; - g_sai = sai; - - np = ppd->pdev->dev.of_node; - - ret = of_clk_set_defaults(np, false); - if (ret < 0) { - AUDIO_DRIVER_LOG_ERR("sai driver init clk set default failed"); - return HDF_FAILURE; - } - - sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); - - res = platform_get_resource(ppd->pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&ppd->pdev->dev, res); - if (IS_ERR(base)) { - return PTR_ERR(base); - } - - sai->reg_offset = FSL_REG_OFFSET; - - sai->regmap = devm_regmap_init_mmio_clk(&ppd->pdev->dev, "bus", base, - &fsl_sai_regmap_config); + sai->regmap = devm_regmap_init_mmio_clk(&ppd->pdev->dev, "bus", base, &fsl_sai_regmap_config); if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER) { - sai->regmap = devm_regmap_init_mmio_clk(&ppd->pdev->dev, - "sai", base, &fsl_sai_regmap_config); + sai->regmap = devm_regmap_init_mmio_clk(&ppd->pdev->dev, "sai", base, &fsl_sai_regmap_config); } if (IS_ERR(sai->regmap)) { AUDIO_DRIVER_LOG_ERR("regmap init failed\n"); @@ -1220,12 +1279,10 @@ int32_t SaiDriverInit(struct PlatformData *pd) } sai->mclk_clk[i] = devm_clk_get(&ppd->pdev->dev, tmp); if (IS_ERR(sai->mclk_clk[i])) { - AUDIO_DRIVER_LOG_ERR("failed to get mclk%d clock: %ld\n", - i, PTR_ERR(sai->mclk_clk[i])); + AUDIO_DRIVER_LOG_ERR("failed to get mclk%d clock: %ld\n", i, PTR_ERR(sai->mclk_clk[i])); sai->mclk_clk[i] = NULL; } clk_rate = clk_get_rate(sai->mclk_clk[i]); - AUDIO_DRIVER_LOG_ERR("mclk %d rate %d", i, clk_rate); } sai->pll8k_clk = devm_clk_get(&ppd->pdev->dev, "pll8k"); @@ -1237,10 +1294,13 @@ int32_t SaiDriverInit(struct PlatformData *pd) if (IS_ERR(sai->pll11k_clk)) { sai->pll11k_clk = NULL; } + return ret; +} - sai->reg_offset = FSL_REG_OFFSET; - sai->dataline = 0xFF; - sai->fifo_depth = NUM_128; +int32_t SaiDriverInitDataline(struct PrivPlatformData *ppd) +{ + int ret = 0; + struct fsl_sai *sai = &ppd->sai; ret = fsl_sai_read_dlcfg(ppd->pdev, "fsl,dataline", &sai->pcm_dl_cfg, sai->dataline); @@ -1258,6 +1318,14 @@ int32_t SaiDriverInit(struct PlatformData *pd) sai->dsd_dl_cfg_cnt = ret; + return ret; +} + +int32_t SaiDriverInitIrq(struct PrivPlatformData *ppd, struct device_node *np) +{ + int irq = 0, ret = 0; + struct fsl_sai *sai = &ppd->sai; + irq = platform_get_irq(ppd->pdev, 0); if (irq < 0) { AUDIO_DRIVER_LOG_ERR("failed to get irq"); @@ -1291,6 +1359,14 @@ int32_t SaiDriverInit(struct PlatformData *pd) sai->synchronous[TX] = false; } + return ret; +} + +int32_t SaiDriverInitDma(struct PrivPlatformData *ppd, struct device_node *np) +{ + int ret = 0; + struct fsl_sai *sai = &ppd->sai; + platform_set_drvdata(ppd->pdev, sai); ret = fsl_sai_check_ver(sai, &ppd->pdev->dev); if (ret < 0) { @@ -1313,136 +1389,183 @@ int32_t SaiDriverInit(struct PlatformData *pd) pm_runtime_enable(&ppd->pdev->dev); - AUDIO_DRIVER_LOG_ERR("success probe in sai driver"); + return ret; +} +int32_t SaiDriverInit(struct PlatformData *pd) +{ + struct PrivPlatformData *ppd = (struct PrivPlatformData *)pd->dmaPrv; + struct device_node *np = ppd->pdev->dev.of_node; + struct resource *res = NULL; + struct fsl_sai *sai = &ppd->sai; + void __iomem *base = NULL; + int ret = 0; + g_sai = sai; + + ret = of_clk_set_defaults(np, false); + if (ret < 0) { + AUDIO_DRIVER_LOG_ERR("sai driver init clk set default failed"); + return HDF_FAILURE; + } + + sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); + res = platform_get_resource(ppd->pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&ppd->pdev->dev, res); + if (IS_ERR(base)) { + return PTR_ERR(base); + } + + sai->reg_offset = FSL_REG_OFFSET; + ret = SaiDriverInitClk(ppd, base); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiDriverInitClk fail ret=%d", ret); + return ret; + } + sai->dataline = 0xFF; + sai->fifo_depth = NUM_128; + ret = SaiDriverInitDataline(ppd); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiDriverInitDataline fail ret=%d", ret); + return ret; + } + ret = SaiDriverInitIrq(ppd, np); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiDriverInitIrq fail ret=%d", ret); + return ret; + } + ret = SaiDriverInitDma(ppd, np); + if (ret != HDF_SUCCESS) { + ADM_LOG_ERR("SaiDriverInitDma fail ret=%d", ret); + return ret; + } + AUDIO_DRIVER_LOG_ERR("success probe in sai driver"); return HDF_SUCCESS; } +void SaiTriggerStart(struct fsl_sai *sai, bool tx, u8 channels, u32 dl_mask, u32 pins) +{ + unsigned char offset = sai->reg_offset; + int i = 0, j = 0, k = 0; + /* + * Asynchronous mode: Clear SYNC for both Tx and Rx. + * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. + * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. + */ + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset), FSL_SAI_CR2_SYNC, + sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset), FSL_SAI_CR2_SYNC, + sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); + + while (tx && i < channels) { + if (dl_mask & (1 << j)) { + regmap_write(sai->regmap, FSL_SAI_TDR0 + j * 0x4, 0x0); + i++; + k++; + } + j++; + + if ((pins != 0) && (k % pins) == 0) { + j = 0; + } + } + + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), + FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); + + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), + FSL_SAI_CSR_SE, FSL_SAI_CSR_SE); + if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { + regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), offset), + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); + } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { + regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), offset), + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); + } + + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), + FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); +} +void SaiTriggerStop(struct fsl_sai *sai, bool tx) +{ + unsigned char offset = sai->reg_offset; + u32 xcsr = 0, count = 100; + + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), + FSL_SAI_CSR_FRDE, 0); + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), + FSL_SAI_CSR_xIE_MASK, 0); + + /* Check if the opposite FRDE is also disabled */ + regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, offset), &xcsr); + if (!(xcsr & FSL_SAI_CSR_FRDE)) { + /* Disable both directions and reset their FIFOs */ + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(offset), + FSL_SAI_CSR_TERE, 0); + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(offset), + FSL_SAI_CSR_TERE, 0); + + /* TERE will remain set till the end of current frame */ + do { + udelay(DELAY_10); + regmap_read(sai->regmap, FSL_SAI_xCSR(tx, offset), &xcsr); + } while (((--count) && (xcsr)) & (FSL_SAI_CSR_TERE)); + + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(offset), + FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(offset), + FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); + + /* + * For sai master mode, after several open/close sai, + * there will be no frame clock, and can't recover + * anymore. Add software reset to fix this issue. + * This is a hardware bug, and will be fix in the + * next sai version. + */ + if (!sai->slave_mode[tx]) { + /* Software Reset for both Tx and Rx */ + regmap_write(sai->regmap, + FSL_SAI_TCSR(offset), FSL_SAI_CSR_SR); + regmap_write(sai->regmap, + FSL_SAI_RCSR(offset), FSL_SAI_CSR_SR); + /* Clear SR bit to finish the reset */ + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), 0); + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), 0); + } + } +} + int32_t SaiTrigger(const struct DaiData *pd, int cmd, int isTx) { struct fsl_sai *sai = g_sai; - unsigned char offset = sai->reg_offset; - u8 channels = 0; bool tx = isTx == TRIGGER_TX; + u8 channels = 0; + u32 slots = (channels == 1) ? 2 : channels; + u32 pins = 0; + u32 dl_mask = 0; + if (isTx == TRIGGER_TX) { channels = pd->pcmInfo.channels; } else if (isTx == TRIGGER_RX) { channels = pd->pcmInfo.channels; } - u32 slots = (channels == 1) ? 2 : channels; - u32 xcsr = 0, count = 100; - u32 pins = 0; - int i = 0, j = 0, k = 0, dl_cfg_cnt = 0, dl_cfg_idx = 0; - struct fsl_sai_dl_cfg *dl_cfg; - if (sai->slots) { slots = sai->slots; } pins = DIV_ROUND_UP(channels, slots); - sai->is_dsd = false; + dl_mask = SaiGetdlMask(sai, tx, pins); - dl_cfg = sai->pcm_dl_cfg; - dl_cfg_cnt = sai->pcm_dl_cfg_cnt; - - for (i = 0; i < dl_cfg_cnt; i++) { - if (dl_cfg[i].pins == pins) { - dl_cfg_idx = i; - break; - } - } - - i = 0; if (cmd == TRIGGER_START) { - /* - * Asynchronous mode: Clear SYNC for both Tx and Rx. - * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. - * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. - */ - regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset), FSL_SAI_CR2_SYNC, - sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); - regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset), FSL_SAI_CR2_SYNC, - sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); - - while (tx && i < channels) { - if (dl_cfg[dl_cfg_idx].mask[tx] & (1 << j)) { - regmap_write(sai->regmap, FSL_SAI_TDR0 + j * 0x4, 0x0); - i++; - k++; - } - j++; - - if ((pins != 0) && (k % pins) == 0) { - j = 0; - } - } - - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), - FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); - - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), - FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), - FSL_SAI_CSR_SE, FSL_SAI_CSR_SE); - if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { - regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), offset), - FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); - } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { - regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), offset), - FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); - } - - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), - FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); + SaiTriggerStart(sai, tx, channels, dl_mask); } else { - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), - FSL_SAI_CSR_FRDE, 0); - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset), - FSL_SAI_CSR_xIE_MASK, 0); - - /* Check if the opposite FRDE is also disabled */ - regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, offset), &xcsr); - if (!(xcsr & FSL_SAI_CSR_FRDE)) { - /* Disable both directions and reset their FIFOs */ - regmap_update_bits(sai->regmap, FSL_SAI_TCSR(offset), - FSL_SAI_CSR_TERE, 0); - regmap_update_bits(sai->regmap, FSL_SAI_RCSR(offset), - FSL_SAI_CSR_TERE, 0); - - /* TERE will remain set till the end of current frame */ - do { - udelay(DELAY_10); - regmap_read(sai->regmap, FSL_SAI_xCSR(tx, offset), &xcsr); - } while (((--count) && (xcsr)) & (FSL_SAI_CSR_TERE)); - - regmap_update_bits(sai->regmap, FSL_SAI_TCSR(offset), - FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); - regmap_update_bits(sai->regmap, FSL_SAI_RCSR(offset), - FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); - - /* - * For sai master mode, after several open/close sai, - * there will be no frame clock, and can't recover - * anymore. Add software reset to fix this issue. - * This is a hardware bug, and will be fix in the - * next sai version. - */ - if (!sai->slave_mode[tx]) { - /* Software Reset for both Tx and Rx */ - regmap_write(sai->regmap, - FSL_SAI_TCSR(offset), FSL_SAI_CSR_SR); - regmap_write(sai->regmap, - FSL_SAI_RCSR(offset), FSL_SAI_CSR_SR); - /* Clear SR bit to finish the reset */ - regmap_write(sai->regmap, FSL_SAI_TCSR(offset), 0); - regmap_write(sai->regmap, FSL_SAI_RCSR(offset), 0); - } - } + SaiTriggerStop(sai, tx); } SaiPrintAllRegister(); - return HDF_SUCCESS; } diff --git a/imx8mm/drivers/wifi/ap6212/hdfadapter/hdf_mac80211.c b/imx8mm/drivers/wifi/ap6212/hdfadapter/hdf_mac80211.c index 0224abe..d924b8a 100644 --- a/imx8mm/drivers/wifi/ap6212/hdfadapter/hdf_mac80211.c +++ b/imx8mm/drivers/wifi/ap6212/hdfadapter/hdf_mac80211.c @@ -713,27 +713,13 @@ int32_t WalDisconnect(NetDevice *netDev, uint16_t reasonCode) return retVal; } -struct cfg80211_scan_request g_request; -int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) +int32_t WalBuildChannelInfo(struct wiphy* wiphy, struct WlanScanRequest *scanParam, + struct cfg80211_scan_request **request) { int32_t loop; int32_t count = 0; - int32_t retVal = 0; - enum Ieee80211Band band = IEEE80211_BAND_2GHZ; struct ieee80211_channel *chan = NULL; - struct wiphy* wiphy = wrap_get_wiphy(); - - struct cfg80211_scan_request *request = &g_request; - - if (request == NULL) { - HDF_LOGE("%s: calloc request null!\n", __func__); - return HDF_FAILURE; - } - - // basic info - request->wiphy = wiphy; - request->wdev = GET_NET_DEV_CFG80211_WIRELESS(netDev); - request->n_ssids = scanParam->ssidCount; + enum Ieee80211Band band = IEEE80211_BAND_2GHZ; // channel info if ((scanParam->freqs == NULL) || (scanParam->freqsCount == 0)) { @@ -747,17 +733,16 @@ int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) if ((chan->flags & WIFI_CHAN_DISABLED) != 0) { continue; } - request->channels[count++] = chan; + (*request)->channels[count++] = chan; } } else { for (loop = 0; loop < scanParam->freqsCount; loop++) { chan = GetChannelByFreq(wiphy, (uint16_t)(scanParam->freqs[loop])); if (chan == NULL) { - HDF_LOGE("%s: freq not found!freq=%d!\n", __func__, scanParam->freqs[loop]); continue; } - request->channels[count++] = chan; + (*request)->channels[count++] = chan; } } @@ -765,11 +750,14 @@ int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) HDF_LOGE("%s: invalid freq info!\n", __func__); return HDF_FAILURE; } - request->n_channels = count; + (*request)->n_channels = count; - // ssid info - count = 0; - loop = 0; + return HDF_SUCCESS; +} + +int32_t WalBuildSSidInfo(struct WlanScanRequest *scanParam, struct cfg80211_scan_request **request) +{ + int32_t loop, count = 0, retVal = 0; if (scanParam->ssidCount > WPAS_MAX_SCAN_SSIDS) { HDF_LOGE("%s:unexpected numSsids!numSsids=%u", __func__, scanParam->ssidCount); return HDF_FAILURE; @@ -780,7 +768,7 @@ int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) return HDF_SUCCESS; } - request->ssids = (struct cfg80211_ssid *)OsalMemCalloc(scanParam->ssidCount * sizeof(struct cfg80211_ssid)); + (*request)->ssids = (struct cfg80211_ssid *)OsalMemCalloc(scanParam->ssidCount * sizeof(struct cfg80211_ssid)); if (request->ssids == NULL) { HDF_LOGE("%s: calloc request->ssids null", __func__); return HDF_FAILURE; @@ -795,25 +783,53 @@ int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) continue; } - request->ssids[count].ssid_len = scanParam->ssids[loop].ssidLen; - if (memcpy_s(request->ssids[count].ssid, OAL_IEEE80211_MAX_SSID_LEN, scanParam->ssids[loop].ssid, + (*request)->ssids[count].ssid_len = scanParam->ssids[loop].ssidLen; + if (memcpy_s((*request)->ssids[count].ssid, OAL_IEEE80211_MAX_SSID_LEN, scanParam->ssids[loop].ssid, scanParam->ssids[loop].ssidLen) != 0) { continue; } count++; } - request->n_ssids = count; + (*request)->n_ssids = count; + + return HDF_SUCCESS; +} + +struct cfg80211_scan_request g_request; +int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) +{ + int32_t loop, count = 0, retVal = 0; + enum Ieee80211Band band = IEEE80211_BAND_2GHZ; + struct ieee80211_channel *chan = NULL; + struct wiphy* wiphy = wrap_get_wiphy(); + struct cfg80211_scan_request *request = &g_request; + + if (request == NULL) { + return HDF_FAILURE; + } + + // basic info + request->wiphy = wiphy; + request->wdev = GET_NET_DEV_CFG80211_WIRELESS(netDev); + request->n_ssids = scanParam->ssidCount; + + if (WalBuildChannelInfo(wiphy, scanParam, &request) == HDF_FAILURE) { + return HDF_FAILURE; + } + + // ssid info + if (WalBuildSSidInfo(scanParam, &request) == HDF_FAILURE) { + return HDF_FAILURE; + } // User Ie Info if (scanParam->extraIEsLen > 512) { - HDF_LOGE("%s:unexpected extra len!extraIesLen=%d", __func__, scanParam->extraIEsLen); return HDF_FAILURE; } if ((scanParam->extraIEs != NULL) && (scanParam->extraIEsLen != 0)) { request->ie = (uint8_t *)OsalMemCalloc(scanParam->extraIEsLen); if (request->ie == NULL) { - HDF_LOGE("%s: calloc request->ie null", __func__); if (request->ie != NULL) { OsalMemFree((void*)request->ie); request->ie = NULL; @@ -827,7 +843,6 @@ int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) retVal = (int32_t)wl_cfg80211_ops.scan(wiphy, request); if (retVal < 0) { - HDF_LOGE("%s: scan Failed!", __func__); if (request != NULL) { if ((request)->ie != NULL) { OsalMemFree((void*)(request->ie)); @@ -840,8 +855,6 @@ int32_t WalStartScan(NetDevice *netDev, struct WlanScanRequest *scanParam) OsalMemFree(request); request = NULL; } - } else { - HDF_LOGE("%s: scan OK!", __func__); } return retVal; From 42b8c0d59f2463598fbbb524977b3a8470d9d681 Mon Sep 17 00:00:00 2001 From: zhaoxc0502 Date: Thu, 21 Jul 2022 17:20:21 +0800 Subject: [PATCH 2/5] modify imx8mm format problem Signed-off-by: zhaoxc0502 --- imx8mm/common/unittest/platform/BUILD.gn | 80 - .../platform/common/hdf_emmc_test.cpp | 73 - .../platform/common/hdf_gpio_test.cpp | 128 - .../unittest/platform/common/hdf_i2c_test.cpp | 108 - .../platform/common/hdf_mipi_dsi_test.cpp | 110 - .../unittest/platform/common/hdf_pwm_test.cpp | 128 - .../unittest/platform/common/hdf_rtc_test.cpp | 265 - .../platform/common/hdf_sdio_test.cpp | 149 - .../unittest/platform/common/hdf_spi_test.cpp | 120 - .../platform/common/hdf_uart_test.cpp | 154 - .../platform/common/hdf_watchdog_test.cpp | 105 - .../001_imx_8m_mini_arch_modify_content.patch | 100716 -- ..._8m_mini_certs_crypto_modify_content.patch | 1365 - ...3_imx_8m_mini_drivers_modify_content.patch | 774154 --------------- .../004_imx_8m_mini_fs_modify_content.patch | 1329 - ...5_imx_8m_mini_include_modify_content.patch | 28250 - ...x_8m_mini_init_kernel_modify_content.patch | 430 - .../007_imx_8m_mini_mm_modify_content.patch | 814 - .../008_imx_8m_mini_net_modify_content.patch | 4594 - ...009_imx_8m_mini_other_modify_content.patch | 4009 - ..._imx_8m_mini_security_modify_content.patch | 1392 - ...011_imx_8m_mini_sound_modify_content.patch | 35552 - 22 files changed, 954025 deletions(-) delete mode 100644 imx8mm/common/unittest/platform/BUILD.gn delete mode 100644 imx8mm/common/unittest/platform/common/hdf_emmc_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_gpio_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_i2c_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_mipi_dsi_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_pwm_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_rtc_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_sdio_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_spi_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_uart_test.cpp delete mode 100644 imx8mm/common/unittest/platform/common/hdf_watchdog_test.cpp delete mode 100644 imx8mm/kernel/patches/001_imx_8m_mini_arch_modify_content.patch delete mode 100644 imx8mm/kernel/patches/002_imx_8m_mini_certs_crypto_modify_content.patch delete mode 100644 imx8mm/kernel/patches/003_imx_8m_mini_drivers_modify_content.patch delete mode 100644 imx8mm/kernel/patches/004_imx_8m_mini_fs_modify_content.patch delete mode 100644 imx8mm/kernel/patches/005_imx_8m_mini_include_modify_content.patch delete mode 100644 imx8mm/kernel/patches/006_imx_8m_mini_init_kernel_modify_content.patch delete mode 100644 imx8mm/kernel/patches/007_imx_8m_mini_mm_modify_content.patch delete mode 100644 imx8mm/kernel/patches/008_imx_8m_mini_net_modify_content.patch delete mode 100644 imx8mm/kernel/patches/009_imx_8m_mini_other_modify_content.patch delete mode 100644 imx8mm/kernel/patches/010_imx_8m_mini_security_modify_content.patch delete mode 100644 imx8mm/kernel/patches/011_imx_8m_mini_sound_modify_content.patch diff --git a/imx8mm/common/unittest/platform/BUILD.gn b/imx8mm/common/unittest/platform/BUILD.gn deleted file mode 100644 index 01d796a..0000000 --- a/imx8mm/common/unittest/platform/BUILD.gn +++ /dev/null @@ -1,80 +0,0 @@ -# Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd -# This file contains confidential and proprietary information of -# OSWare Technology Co., Ltd -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import("//build/test.gni") - -module_output_path = "hdf/platform" -ohos_unittest("hdf_adapter_uhdf_test_platform") { - module_out_path = module_output_path - include_dirs = [ - "//drivers/framework/include/platform", - "//drivers/framework/include/core", - "//drivers/framework/include/osal", - "//drivers/adapter/uhdf/posix/include", - "//drivers/framework/include/utils", - "//drivers/framework/include", - "//drivers/framework/test/unittest/include", - "//drivers/framework/test/unittest/platform/common", - "//drivers/framework/core/host/include", - "//drivers/framework/core/manager/include", - "//drivers/adapter/uhdf2/include/host", - "//drivers/framework/support/platform/include", - "//drivers/framework/support/platform/include/fwk", - "//drivers/framework/model/storage/include/mmc", - "//drivers/framework/support/platform/include/spi", - "//drivers/framework/support/platform/include/watchdog", - "//drivers/framework/support/platform/include/i2c", - "//drivers/framework/support/platform/include/uart", - "//drivers/framework/support/platform/include/rtc", - ] - - sources = [ - "common/hdf_emmc_test.cpp", - "common/hdf_gpio_test.cpp", - "common/hdf_i2c_test.cpp", - "common/hdf_pwm_test.cpp", - "common/hdf_rtc_test.cpp", - "common/hdf_spi_test.cpp", - "common/hdf_uart_test.cpp", - "common/hdf_watchdog_test.cpp", - "common/hdf_mipi_dsi_test.cpp", - "common/hdf_sdio_test.cpp", - ] - - defines = [ "__USER__" ] - deps = [ - "//drivers/adapter/build/test_common:libhdf_test_common", - "//drivers/adapter/uhdf2/utils:libhdf_utils", - ] - resource_config_file = - "//drivers/adapter/uhdf2/test/resource/platform/ohos_test.xml" - cflags = [ - "-Wall", - "-Wextra", - "-Werror", - "-fsigned-char", - "-fno-common", - "-fno-strict-aliasing", - ] - if (is_standard_system) { - external_deps = [ - "hiviewdfx_hilog_native:libhilog", - "utils_base:utils", - ] - } else { - external_deps = [ "hilog:libhilog" ] - } -} diff --git a/imx8mm/common/unittest/platform/common/hdf_emmc_test.cpp b/imx8mm/common/unittest/platform/common/hdf_emmc_test.cpp deleted file mode 100644 index 66180a6..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_emmc_test.cpp +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "emmc_if.h" -#include "hdf_io_service_if.h" -#include "hdf_uhdf_test.h" - -using namespace testing::ext; - -enum EmmcTestCmd { - EMMC_GET_CID_01 = 0, -}; - -class HdfLiteEmmcTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteEmmcTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteEmmcTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteEmmcTest::SetUp() -{ -} - -void HdfLiteEmmcTest::TearDown() -{ -} - - -/** - * @tc.name: EmmcGetCid001 - * @tc.desc: test EmmcGetCid/EmmcGetHuid interface in kernel and user status. - * @tc.type: FUNC - * @tc.require: AR000F5LSD AR000F5LV3 - */ -HWTEST_F(HdfLiteEmmcTest, EmmcGetCid001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_EMMC_TYPE, EMMC_GET_CID_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_gpio_test.cpp b/imx8mm/common/unittest/platform/common/hdf_gpio_test.cpp deleted file mode 100644 index 5d0c0e3..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_gpio_test.cpp +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "gpio_test.h" -#include "hdf_uhdf_test.h" -#include "hdf_io_service_if.h" - -using namespace testing::ext; - -class HdfLiteGpioTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteGpioTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteGpioTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteGpioTest::SetUp() -{ -} - -void HdfLiteGpioTest::TearDown() -{ -} - -/** - * @tc.name: GpioTestSetGetDir001 - * @tc.desc: gpio set and get dir test - * @tc.type: FUNC - * @tc.require: AR000F868H - */ -HWTEST_F(HdfLiteGpioTest, GpioTestSetGetDir001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_GPIO_TYPE, GPIO_TEST_SET_GET_DIR, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: GpioTestWriteRead001 - * @tc.desc: gpio write and read test - * @tc.type: FUNC - * @tc.require: AR000F868H - */ -HWTEST_F(HdfLiteGpioTest, GpioTestWriteRead001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_GPIO_TYPE, GPIO_TEST_WRITE_READ, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: GpioTestIrqLevel001 - * @tc.desc: gpio level irq trigger test - * @tc.type: FUNC - * @tc.require: AR000F868H - */ -HWTEST_F(HdfLiteGpioTest, GpioTestIrqLevel001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_GPIO_TYPE, GPIO_TEST_IRQ_LEVEL, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: GpioTestIrqEdge001 - * @tc.desc: gpio edge irq trigger test - * @tc.type: FUNC - * @tc.require: AR000F868H - */ -HWTEST_F(HdfLiteGpioTest, GpioTestIrqEdge001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_GPIO_TYPE, GPIO_TEST_IRQ_EDGE, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: GpioTestIrqThread001 - * @tc.desc: gpio thread irq trigger test - * @tc.type: FUNC - * @tc.require: AR000F868H - */ -HWTEST_F(HdfLiteGpioTest, GpioTestIrqThread001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_GPIO_TYPE, GPIO_TEST_IRQ_THREAD, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: GpioTestReliability001 - * @tc.desc: gpio reliability test - * @tc.type: FUNC - * @tc.require: AR000F868H - */ -HWTEST_F(HdfLiteGpioTest, GpioTestReliability001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_GPIO_TYPE, GPIO_TEST_RELIABILITY, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_i2c_test.cpp b/imx8mm/common/unittest/platform/common/hdf_i2c_test.cpp deleted file mode 100644 index d090e80..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_i2c_test.cpp +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "i2c_test.h" -#include "hdf_io_service_if.h" - -using namespace testing::ext; - -class HdfLiteI2cTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteI2cTest::SetUpTestCase() -{ - struct HdfTestMsg msg = {TEST_PAL_I2C_TYPE, I2C_TEST_CMD_SETUP_ALL, -1}; - HdfTestOpenService(); - HdfTestSendMsgToService(&msg); -} - -void HdfLiteI2cTest::TearDownTestCase() -{ - struct HdfTestMsg msg = {TEST_PAL_I2C_TYPE, I2C_TEST_CMD_TEARDOWN_ALL, -1}; - HdfTestSendMsgToService(&msg); - HdfTestCloseService(); -} - -void HdfLiteI2cTest::SetUp() -{ -} - -void HdfLiteI2cTest::TearDown() -{ -} - -/** - * @tc.name: HdfLiteI2cTestTransfer001 - * @tc.desc: i2c transfer test - * @tc.type: FUNC - * @tc.require: AR000F8688 - */ -HWTEST_F(HdfLiteI2cTest, HdfLiteI2cTestTransfer001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_I2C_TYPE, I2C_TEST_CMD_TRANSFER, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: HdfLiteI2cTestWriteRead001 - * @tc.desc: i2c write and read test - * @tc.type: FUNC - * @tc.require: AR000F8688 - */ -HWTEST_F(HdfLiteI2cTest, HdfLiteI2cTestWriteRead001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_I2C_TYPE, I2C_TEST_CMD_WRITE_READ, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: HdfLiteI2cTestMultiThread001 - * @tc.desc: i2c multithread test - * @tc.type: FUNC - * @tc.require: AR000F8688 - */ -HWTEST_F(HdfLiteI2cTest, HdfLiteI2cTestMultiThread001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_I2C_TYPE, I2C_TEST_CMD_MULTI_THREAD, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: HdfLiteI2cTestReliability001 - * @tc.desc: i2c reliability test - * @tc.type: FUNC - * @tc.require: AR000F8688 - */ -HWTEST_F(HdfLiteI2cTest, HdfLiteI2cTestReliability001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_I2C_TYPE, I2C_TEST_CMD_RELIABILITY, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_mipi_dsi_test.cpp b/imx8mm/common/unittest/platform/common/hdf_mipi_dsi_test.cpp deleted file mode 100644 index 388438d..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_mipi_dsi_test.cpp +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "hdf_uhdf_test.h" - -using namespace testing::ext; - -// pal mipi dsi test case number -enum MipiDsiTestCmd { - MIPI_DSI_TEST_SET_CFG = 0, - MIPI_DSI_TEST_GET_CFG = 1, - MIPI_DSI_TEST_TX_RX = 2, - MIPI_DSI_TEST_TO_LP_TO_HS = 3, - MIPI_DSI_TEST_ENTER_ULPS_EXIT_ULPS = 4, - MIPI_DSI_TEST_POWER_CONTROL = 5, - MIPI_DSI_TEST_MAX = 6, -}; - -class HdfLiteMipiDsiTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteMipiDsiTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteMipiDsiTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteMipiDsiTest::SetUp() -{ -} - -void HdfLiteMipiDsiTest::TearDown() -{ -} - -static void MipiDsiTest(enum MipiDsiTestCmd cmd) -{ - struct HdfTestMsg msg = {TEST_PAL_MIPI_DSI_TYPE, (uint8_t)cmd, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: MipiDsiSetCfgTest001 - * @tc.desc: mipi dsi function test - * @tc.type: FUNC - * @tc.require: AR000F868F - */ -HWTEST_F(HdfLiteMipiDsiTest, MipiDsiSetCfgTest001, TestSize.Level1) -{ - MipiDsiTest(MIPI_DSI_TEST_SET_CFG); -} - -/** - * @tc.name: MipiDsiGetCfgTest001 - * @tc.desc: mipi dsi function test - * @tc.type: FUNC - * @tc.require: AR000F868F - */ -HWTEST_F(HdfLiteMipiDsiTest, MipiDsiGetCfgTest001, TestSize.Level1) -{ - MipiDsiTest(MIPI_DSI_TEST_GET_CFG); -} - -/** - * @tc.name: MipiDsiTxRxTest001 - * @tc.desc: mipi dsi function test - * @tc.type: FUNC - * @tc.require: AR000F868F - */ -HWTEST_F(HdfLiteMipiDsiTest, MipiDsiTxRxTest001, TestSize.Level1) -{ - MipiDsiTest(MIPI_DSI_TEST_TX_RX); -} - -/** - * @tc.name: MipiDsiLpHsTest001 - * @tc.desc: mipi dsi function test - * @tc.type: FUNC - * @tc.require: AR000F868F - */ -HWTEST_F(HdfLiteMipiDsiTest, MipiDsiLpHsTest001, TestSize.Level1) -{ - MipiDsiTest(MIPI_DSI_TEST_TO_LP_TO_HS); -} - diff --git a/imx8mm/common/unittest/platform/common/hdf_pwm_test.cpp b/imx8mm/common/unittest/platform/common/hdf_pwm_test.cpp deleted file mode 100644 index 6b8ba9a..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_pwm_test.cpp +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "pwm_test.h" -#include "hdf_io_service_if.h" - -using namespace testing::ext; - -class HdfLitePwmTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLitePwmTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLitePwmTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLitePwmTest::SetUp() -{ -} - -void HdfLitePwmTest::TearDown() -{ -} - -/** - * @tc.name: PwmSetPeriodTest001 - * @tc.desc: pwm function test - * @tc.type: FUNC - * @tc.require: AR000F868C - */ -HWTEST_F(HdfLitePwmTest, PwmSetPeriodTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_PWM_TYPE, PWM_SET_PERIOD_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: PwmSetDutyTest001 - * @tc.desc: pwm function test - * @tc.type: FUNC - * @tc.require: AR000F868C - */ -HWTEST_F(HdfLitePwmTest, PwmSetDutyTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_PWM_TYPE, PWM_SET_DUTY_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: PwmSetPolarityTest001 - * @tc.desc: pwm function test - * @tc.type: FUNC - * @tc.require: AR000F868C - */ -HWTEST_F(HdfLitePwmTest, PwmSetPolarityTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_PWM_TYPE, PWM_SET_POLARITY_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: PwmSetGetConfigTest001 - * @tc.desc: pwm function test - * @tc.type: FUNC - * @tc.require: AR000F868D - */ -HWTEST_F(HdfLitePwmTest, PwmSetGetConfigTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_PWM_TYPE, PWM_SET_GET_CONFIG_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: PwmEnableTest001 - * @tc.desc: pwm function test - * @tc.type: FUNC - * @tc.require: AR000F868D - */ -HWTEST_F(HdfLitePwmTest, PwmEnableTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_PWM_TYPE, PWM_ENABLE_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: PwmDisableTest001 - * @tc.desc: pwm function test - * @tc.type: FUNC - * @tc.require: AR000F868D - */ -HWTEST_F(HdfLitePwmTest, PwmDisableTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_PWM_TYPE, PWM_DISABLE_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_rtc_test.cpp b/imx8mm/common/unittest/platform/common/hdf_rtc_test.cpp deleted file mode 100644 index 4a38c0c..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_rtc_test.cpp +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "hdf_io_service_if.h" -#include "rtc_test.h" - -using namespace testing::ext; - -class HdfRtcTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfRtcTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfRtcTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfRtcTest::SetUp() -{ -} - -void HdfRtcTest::TearDown() -{ -} - -/** - * @tc.name: testRtcReadWriteTime001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcReadWriteTime001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_WR_TIME, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcReadWriteMaxTime001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcReadWriteMaxTime001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_WR_MAX_TIME, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcReadWriteMinTime001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcReadWriteMinTime001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_WR_MIN_TIME, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcReadWriteAlarmTime001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcReadWriteAlarmTime001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_WR_ALARM_TIME, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcReadWriteAlarmMaxTime001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcReadWriteAlarmMaxTime001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_WR_ALARM_MAX_TIME, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} -/** - * @tc.name: testRtcReadWriteAlarmMinTime001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcReadWriteAlarmMinTime001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_WR_ALARM_MIN_TIME, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -#ifndef HDF_LITEOS_TEST -/** - * @tc.name: testRtcAlarmEnable001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000F868I - */ -HWTEST_F(HdfRtcTest, testRtcAlarmEnable001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_ALARM_ENABLE, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} -#endif - -#if defined(HDF_LITEOS_TEST) - -/** - * @tc.name: testRtcAlarmIrq001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcAlarmIrq001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_ALARM_IRQ, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcRegCallback001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcRegCallback001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_REGISTER_CALLBACK, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcRegCallbackNull001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcRegCallbackNull001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_REGISTER_CALLBACK_NULL, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcFreq001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcFreq001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_WR_FREQ, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcMaxFreq001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcMaxFreq001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_WR_MAX_FREQ, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcMinFreq001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcMinFreq001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_WR_MIN_FREQ, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcUserReg001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcUserReg001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_WR_USER_REG, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: testRtcUserRegMaxIndex001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcUserRegMaxIndex001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_WR_USER_REG_MAX_INDEX, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} -#endif -/** - * @tc.name: testRtcReliability001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcReliability001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_WR_RELIABILITY, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -#if defined(HDF_LITEOS_TEST) -/** - * @tc.name: testRtcModule001 - * @tc.desc: rtc function test - * @tc.type: FUNC - * @tc.require: AR000EKRKU - */ -HWTEST_F(HdfRtcTest, testRtcModule001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_RTC_TYPE, RTC_TEST_CMD_RTC_FUNCTION_TEST, -1 }; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} -#endif diff --git a/imx8mm/common/unittest/platform/common/hdf_sdio_test.cpp b/imx8mm/common/unittest/platform/common/hdf_sdio_test.cpp deleted file mode 100644 index 791796c..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_sdio_test.cpp +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "hdf_io_service_if.h" - -using namespace testing::ext; - -enum SdioTestCmd { - SDIO_DISABLE_FUNC_01 = 0, - SDIO_ENABLE_FUNC_01, - SDIO_SET_BLOCK_SIZE_01, - SDIO_INCR_ADDR_READ_AND_WRITE_BYTES_01, - SDIO_FIXED_ADDR_READ_AND_WRITE_BYTES_01, - SDIO_FUNC0_READ_AND_WRITE_BYTES_01, - SDIO_SET_AND_GET_COMMON_INFO_01, -}; - -class HdfLiteSdioTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteSdioTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteSdioTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteSdioTest::SetUp() -{ -} - -void HdfLiteSdioTest::TearDown() -{ -} - -/** - * @tc.name: SdioDisableFunc001 - * @tc.desc: SdioDisableFunc Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioDisableFunc001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SDIO_TYPE, SDIO_DISABLE_FUNC_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SdioEnableFunc001 - * @tc.desc: SdioEnableFunc Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioEnableFunc001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SDIO_TYPE, SDIO_ENABLE_FUNC_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SdioSetBlockSize001 - * @tc.desc: SdioSetBlockSize Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioSetBlockSize001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SDIO_TYPE, SDIO_SET_BLOCK_SIZE_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SdioIncrAddrReadAndWriteBytes001 - * @tc.desc: SdioReadBytes and SdioWriteBytes Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioIncrAddrReadAndWriteBytes001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SDIO_TYPE, SDIO_INCR_ADDR_READ_AND_WRITE_BYTES_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SdioFixedAddrReadAndWriteBytes001 - * @tc.desc: SdioReadBytesFromFixedAddr and SdioWriteBytesToFixedAddr Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioFixedAddrReadAndWriteBytes001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SDIO_TYPE, SDIO_FIXED_ADDR_READ_AND_WRITE_BYTES_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SdioFunc0ReadAndWriteBytes001 - * @tc.desc: SdioReadBytesFromFunc0 and SdioWriteBytesToFunc0 Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioFunc0ReadAndWriteBytes001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_SDIO_TYPE, SDIO_FUNC0_READ_AND_WRITE_BYTES_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SdioSetAndGetCommonInfo001 - * @tc.desc: SdioGetCommonInfo and SdioSetCommonInfo Interface test - * @tc.type: FUNC - * @tc.require: AR000F868B - */ -HWTEST_F(HdfLiteSdioTest, SdioSetAndGetCommonInfo001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SDIO_TYPE, SDIO_SET_AND_GET_COMMON_INFO_01, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_spi_test.cpp b/imx8mm/common/unittest/platform/common/hdf_spi_test.cpp deleted file mode 100644 index 9ed76e1..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_spi_test.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "hdf_io_service_if.h" -#include "spi_test.h" - -using namespace testing::ext; - -class HdfLiteSpiTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteSpiTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteSpiTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteSpiTest::SetUp() -{ -} - -void HdfLiteSpiTest::TearDown() -{ -} - -/** - * @tc.name: SpiTransferTest001 - * @tc.desc: spi function test - * @tc.type: FUNC - * @tc.require: SR000DQ0VO - */ -HWTEST_F(HdfLiteSpiTest, SpiTransferTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SPI_TYPE, SPI_TRANSFER_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SpiMultiTransferTest001 - * @tc.desc: spi function test - * @tc.type: FUNC - * @tc.require: SR000DQ0VO - */ -#ifdef __LITEOS__ -HWTEST_F(HdfLiteSpiTest, SpiMultiTransferTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SPI_TYPE, SPI_MULTI_TRANSFER_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); - - EXPECT_EQ(0, SpiTestExecute(SPI_MULTI_TRANSFER_TEST)); -} -#endif - -/** - * @tc.name: SpiDmaTransferTest001 - * @tc.desc: Spi function test - * @tc.type: FUNC - * @tc.require: NA - */ -HWTEST_F(HdfLiteSpiTest, SpiDmaTransferTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SPI_TYPE, SPI_DMA_TRANSFER_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SpiIntTransferTest001 - * @tc.desc: Spi function test - * @tc.type: FUNC - * @tc.require: NA - */ -HWTEST_F(HdfLiteSpiTest, SpiIntTransferTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SPI_TYPE, SPI_INT_TRANSFER_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: SpiReliabilityTest001 - * @tc.desc: spi function test - * @tc.type: FUNC - * @tc.require: SR000DQ0VO - */ -HWTEST_F(HdfLiteSpiTest, SpiReliabilityTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_SPI_TYPE, SPI_RELIABILITY_TEST, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_uart_test.cpp b/imx8mm/common/unittest/platform/common/hdf_uart_test.cpp deleted file mode 100644 index 7dadcc9..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_uart_test.cpp +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "hdf_io_service_if.h" -#include "uart_test.h" - -using namespace testing::ext; - -class HdfLiteUartTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteUartTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteUartTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteUartTest::SetUp() -{ -} - -void HdfLiteUartTest::TearDown() -{ -} - -#ifdef HDF_LITEOS_TEST -/** - * @tc.name: UartSetTransModeTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartSetTransModeTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_SET_TRANSMODE, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} -#endif - -/** - * @tc.name: UartWriteTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartWriteTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_WRITE, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: UartReadTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartReadTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = { TEST_PAL_UART_TYPE, UART_TEST_CMD_READ, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: UartSetBaudTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartSetBaudTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_SET_BAUD, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: UartGetBaudTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartGetBaudTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_GET_BAUD, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: UartSetAttributeTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartSetAttributeTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_SET_ATTRIBUTE, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: UartGetAttributeTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartGetAttributeTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_GET_ATTRIBUTE, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: UartReliabilityTest001 - * @tc.desc: uart function test - * @tc.type: FUNC - * @tc.require: AR000F8689 - */ -HWTEST_F(HdfLiteUartTest, UartReliabilityTest001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_UART_TYPE, UART_TEST_CMD_RELIABILITY, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} diff --git a/imx8mm/common/unittest/platform/common/hdf_watchdog_test.cpp b/imx8mm/common/unittest/platform/common/hdf_watchdog_test.cpp deleted file mode 100644 index fb11254..0000000 --- a/imx8mm/common/unittest/platform/common/hdf_watchdog_test.cpp +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd - * This file contains confidential and proprietary information of - * OSWare Technology Co., Ltd - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "hdf_uhdf_test.h" -#include "hdf_io_service_if.h" -#include "watchdog_test.h" - -using namespace testing::ext; - -class HdfLiteWatchdogTest : public testing::Test { -public: - static void SetUpTestCase(); - static void TearDownTestCase(); - void SetUp(); - void TearDown(); -}; - -void HdfLiteWatchdogTest::SetUpTestCase() -{ - HdfTestOpenService(); -} - -void HdfLiteWatchdogTest::TearDownTestCase() -{ - HdfTestCloseService(); -} - -void HdfLiteWatchdogTest::SetUp() -{ -} - -void HdfLiteWatchdogTest::TearDown() -{ -} - -/** - * @tc.name: HdfLiteWatchdogTestSetGetTimeout001 - * @tc.desc: watchdog function test - * @tc.type: FUNC - * @tc.require: AR000F868G - */ -HWTEST_F(HdfLiteWatchdogTest, HdfLiteWatchdogTestSetGetTimeout001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_WDT_TYPE, WATCHDOG_TEST_SET_GET_TIMEOUT, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: HdfLiteWatchdogTestStartStop001 - * @tc.desc: watchdog function test - * @tc.type: FUNC - * @tc.require: AR000F868G - */ -HWTEST_F(HdfLiteWatchdogTest, HdfLiteWatchdogTestStartStop001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_WDT_TYPE, WATCHDOG_TEST_START_STOP, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: HdfLiteWatchdogTestFeed001 - * @tc.desc: watchdog function test - * @tc.type: FUNC - * @tc.require: AR000F868G - */ -HWTEST_F(HdfLiteWatchdogTest, HdfLiteWatchdogTestFeed001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_WDT_TYPE, WATCHDOG_TEST_FEED, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - -/** - * @tc.name: HdfLiteWatchdogTestReliability001 - * @tc.desc: watchdog function test - * @tc.type: FUNC - * @tc.require: AR000F868G - */ -HWTEST_F(HdfLiteWatchdogTest, HdfLiteWatchdogTestReliability001, TestSize.Level1) -{ - struct HdfTestMsg msg = {TEST_PAL_WDT_TYPE, WATCHDOG_TEST_RELIABILITY, -1}; - EXPECT_EQ(0, HdfTestSendMsgToService(&msg)); -} - diff --git a/imx8mm/kernel/patches/001_imx_8m_mini_arch_modify_content.patch b/imx8mm/kernel/patches/001_imx_8m_mini_arch_modify_content.patch deleted file mode 100644 index 799c2e0..0000000 --- a/imx8mm/kernel/patches/001_imx_8m_mini_arch_modify_content.patch +++ /dev/null @@ -1,100716 +0,0 @@ -commit 36293d49b2b5e3ed870151fb85bfd63e5a86c3fc -Author: zhaoxc0502 -Date: Wed Jun 1 11:52:12 2022 +0800 - - modify kernel arch for imx8m mini - - Change-Id: I6f9efcd55cc779d8084229f38803aef1ff05aa63 - -diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h -index 00c9aafa3..209936150 100644 ---- a/arch/arm/include/asm/assembler.h -+++ b/arch/arm/include/asm/assembler.h -@@ -108,16 +108,6 @@ - .endm - #endif - --#if __LINUX_ARM_ARCH__ < 7 -- .macro dsb, args -- mcr p15, 0, r0, c7, c10, 4 -- .endm -- -- .macro isb, args -- mcr p15, 0, r0, c7, c5, 4 -- .endm --#endif -- - .macro asm_trace_hardirqs_off, save=1 - #if defined(CONFIG_TRACE_IRQFLAGS) - .if \save -diff --git a/arch/arm/include/asm/spectre.h b/arch/arm/include/asm/spectre.h -deleted file mode 100644 -index 85f9e538f..000000000 ---- a/arch/arm/include/asm/spectre.h -+++ /dev/null -@@ -1,38 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ -- --#ifndef __ASM_SPECTRE_H --#define __ASM_SPECTRE_H -- --enum { -- SPECTRE_UNAFFECTED, -- SPECTRE_MITIGATED, -- SPECTRE_VULNERABLE, --}; -- --enum { -- __SPECTRE_V2_METHOD_BPIALL, -- __SPECTRE_V2_METHOD_ICIALLU, -- __SPECTRE_V2_METHOD_SMC, -- __SPECTRE_V2_METHOD_HVC, -- __SPECTRE_V2_METHOD_LOOP8, --}; -- --enum { -- SPECTRE_V2_METHOD_BPIALL = BIT(__SPECTRE_V2_METHOD_BPIALL), -- SPECTRE_V2_METHOD_ICIALLU = BIT(__SPECTRE_V2_METHOD_ICIALLU), -- SPECTRE_V2_METHOD_SMC = BIT(__SPECTRE_V2_METHOD_SMC), -- SPECTRE_V2_METHOD_HVC = BIT(__SPECTRE_V2_METHOD_HVC), -- SPECTRE_V2_METHOD_LOOP8 = BIT(__SPECTRE_V2_METHOD_LOOP8), --}; -- --#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES --void spectre_v2_update_state(unsigned int state, unsigned int methods); --#else --static inline void spectre_v2_update_state(unsigned int state, -- unsigned int methods) --{} --#endif -- --int spectre_bhb_update_vectors(unsigned int method); -- --#endif -diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h -index 0b2b1c577..be04f5b50 100644 ---- a/arch/arm/include/asm/vmlinux.lds.h -+++ b/arch/arm/include/asm/vmlinux.lds.h -@@ -26,19 +26,6 @@ - #define ARM_MMU_DISCARD(x) x - #endif - --/* -- * ld.lld does not support NOCROSSREFS: -- * https://github.com/ClangBuiltLinux/linux/issues/1609 -- */ --#ifdef CONFIG_LD_IS_LLD --#define NOCROSSREFS --#endif -- --/* Set start/end symbol names to the LMA for the section */ --#define ARM_LMA(sym, section) \ -- sym##_start = LOADADDR(section); \ -- sym##_end = LOADADDR(section) + SIZEOF(section) -- - #define PROC_INFO \ - . = ALIGN(4); \ - __proc_info_begin = .; \ -@@ -128,31 +115,19 @@ - * only thing that matters is their relative offsets - */ - #define ARM_VECTORS \ -- __vectors_lma = .; \ -- OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) { \ -- .vectors { \ -- *(.vectors) \ -- } \ -- .vectors.bhb.loop8 { \ -- *(.vectors.bhb.loop8) \ -- } \ -- .vectors.bhb.bpiall { \ -- *(.vectors.bhb.bpiall) \ -- } \ -+ __vectors_start = .; \ -+ .vectors 0xffff0000 : AT(__vectors_start) { \ -+ *(.vectors) \ - } \ -- ARM_LMA(__vectors, .vectors); \ -- ARM_LMA(__vectors_bhb_loop8, .vectors.bhb.loop8); \ -- ARM_LMA(__vectors_bhb_bpiall, .vectors.bhb.bpiall); \ -- . = __vectors_lma + SIZEOF(.vectors) + \ -- SIZEOF(.vectors.bhb.loop8) + \ -- SIZEOF(.vectors.bhb.bpiall); \ -+ . = __vectors_start + SIZEOF(.vectors); \ -+ __vectors_end = .; \ - \ -- __stubs_lma = .; \ -- .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) { \ -+ __stubs_start = .; \ -+ .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) { \ - *(.stubs) \ - } \ -- ARM_LMA(__stubs, .stubs); \ -- . = __stubs_lma + SIZEOF(.stubs); -+ . = __stubs_start + SIZEOF(.stubs); \ -+ __stubs_end = .; - \ - #define ARM_TCM \ - __itcm_start = ALIGN(4); \ -diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile -index 292378fbb..c38c8b019 100644 ---- a/arch/arm/kernel/Makefile -+++ b/arch/arm/kernel/Makefile -@@ -110,6 +110,4 @@ endif - - obj-$(CONFIG_HAVE_ARM_SMCCC) += smccc-call.o - --obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += spectre.o -- - extra-y := $(head-y) vmlinux.lds -diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S -index e3eca3f83..cd0a00032 100644 ---- a/arch/arm/kernel/entry-armv.S -+++ b/arch/arm/kernel/entry-armv.S -@@ -1007,11 +1007,12 @@ __kuser_helper_end: - sub lr, lr, #\correction - .endif - -- @ Save r0, lr_ (parent PC) -+ @ -+ @ Save r0, lr_ (parent PC) and spsr_ -+ @ (parent CPSR) -+ @ - stmia sp, {r0, lr} @ save r0, lr -- -- @ Save spsr_ (parent CPSR) --2: mrs lr, spsr -+ mrs lr, spsr - str lr, [sp, #8] @ save spsr - - @ -@@ -1032,44 +1033,6 @@ __kuser_helper_end: - movs pc, lr @ branch to handler in SVC mode - ENDPROC(.Lvector_\name) - --#ifdef CONFIG_HARDEN_BRANCH_HISTORY -- .subsection 1 -- .align 5 --vector_bhb_loop8_\name: -- .if \correction -- sub lr, lr, #\correction -- .endif -- -- @ Save r0, lr_ (parent PC) -- stmia sp, {r0, lr} -- -- @ bhb workaround -- mov r0, #8 --3: b . + 4 -- subs r0, r0, #1 -- bne 3b -- dsb -- isb -- b 2b --ENDPROC(vector_bhb_loop8_\name) -- --vector_bhb_bpiall_\name: -- .if \correction -- sub lr, lr, #\correction -- .endif -- -- @ Save r0, lr_ (parent PC) -- stmia sp, {r0, lr} -- -- @ bhb workaround -- mcr p15, 0, r0, c7, c5, 6 @ BPIALL -- @ isb not needed due to "movs pc, lr" in the vector stub -- @ which gives a "context synchronisation". -- b 2b --ENDPROC(vector_bhb_bpiall_\name) -- .previous --#endif -- - .align 2 - @ handler addresses follow this label - 1: -@@ -1082,10 +1045,6 @@ ENDPROC(vector_bhb_bpiall_\name) - #endif - @ This must be the first word - .word vector_swi --#ifdef CONFIG_HARDEN_BRANCH_HISTORY -- .word vector_bhb_loop8_swi -- .word vector_bhb_bpiall_swi --#endif - - .Lvector_rst: - ARM( swi SYS_ERROR0 ) -@@ -1200,10 +1159,8 @@ ENDPROC(vector_bhb_bpiall_\name) - * FIQ "NMI" handler - *----------------------------------------------------------------------------- - * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 -- * systems. This must be the last vector stub, so lets place it in its own -- * subsection. -+ * systems. - */ -- .subsection 2 - vector_stub fiq, FIQ_MODE, 4 - - .long __fiq_usr @ 0 (USR_26 / USR_32) -@@ -1234,30 +1191,6 @@ ENDPROC(vector_bhb_bpiall_\name) - W(b) .Lvector_irq - W(b) .Lvector_fiq - --#ifdef CONFIG_HARDEN_BRANCH_HISTORY -- .section .vectors.bhb.loop8, "ax", %progbits --.L__vectors_bhb_loop8_start: -- W(b) .Lvector_rst -- W(b) vector_bhb_loop8_und -- W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 -- W(b) vector_bhb_loop8_pabt -- W(b) vector_bhb_loop8_dabt -- W(b) .Lvector_addrexcptn -- W(b) vector_bhb_loop8_irq -- W(b) vector_bhb_loop8_fiq -- -- .section .vectors.bhb.bpiall, "ax", %progbits --.L__vectors_bhb_bpiall_start: -- W(b) .Lvector_rst -- W(b) vector_bhb_bpiall_und -- W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 -- W(b) vector_bhb_bpiall_pabt -- W(b) vector_bhb_bpiall_dabt -- W(b) .Lvector_addrexcptn -- W(b) vector_bhb_bpiall_irq -- W(b) vector_bhb_bpiall_fiq --#endif -- - .data - .align 2 - -diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S -index 7a2e63dfb..fee279e28 100644 ---- a/arch/arm/kernel/entry-common.S -+++ b/arch/arm/kernel/entry-common.S -@@ -165,29 +165,6 @@ ENDPROC(ret_from_fork) - *----------------------------------------------------------------------------- - */ - -- .align 5 --#ifdef CONFIG_HARDEN_BRANCH_HISTORY --ENTRY(vector_bhb_loop8_swi) -- sub sp, sp, #PT_REGS_SIZE -- stmia sp, {r0 - r12} -- mov r8, #8 --1: b 2f --2: subs r8, r8, #1 -- bne 1b -- dsb -- isb -- b 3f --ENDPROC(vector_bhb_loop8_swi) -- -- .align 5 --ENTRY(vector_bhb_bpiall_swi) -- sub sp, sp, #PT_REGS_SIZE -- stmia sp, {r0 - r12} -- mcr p15, 0, r8, c7, c5, 6 @ BPIALL -- isb -- b 3f --ENDPROC(vector_bhb_bpiall_swi) --#endif - .align 5 - ENTRY(vector_swi) - #ifdef CONFIG_CPU_V7M -@@ -195,7 +172,6 @@ ENTRY(vector_swi) - #else - sub sp, sp, #PT_REGS_SIZE - stmia sp, {r0 - r12} @ Calling r0 - r12 --3: - ARM( add r8, sp, #S_PC ) - ARM( stmdb r8, {sp, lr}^ ) @ Calling sp, lr - THUMB( mov r8, sp ) -diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c -index 84ac00f47..76ea4178a 100644 ---- a/arch/arm/kernel/stacktrace.c -+++ b/arch/arm/kernel/stacktrace.c -@@ -53,18 +53,18 @@ int notrace unwind_frame(struct stackframe *frame) - return -EINVAL; - - frame->sp = frame->fp; -- frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp)); -+ frame->fp = *(unsigned long *)(fp); - frame->pc = frame->lr; -- frame->lr = READ_ONCE_NOCHECK(*(unsigned long *)(fp + 4)); -+ frame->lr = *(unsigned long *)(fp + 4); - #else - /* check current frame pointer is within bounds */ - if (fp < low + 12 || fp > high - 4) - return -EINVAL; - - /* restore the registers from the stack frame */ -- frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp - 12)); -- frame->sp = READ_ONCE_NOCHECK(*(unsigned long *)(fp - 8)); -- frame->pc = READ_ONCE_NOCHECK(*(unsigned long *)(fp - 4)); -+ frame->fp = *(unsigned long *)(fp - 12); -+ frame->sp = *(unsigned long *)(fp - 8); -+ frame->pc = *(unsigned long *)(fp - 4); - #endif - - return 0; -diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c -index 2d9e72ad1..17d5a785d 100644 ---- a/arch/arm/kernel/traps.c -+++ b/arch/arm/kernel/traps.c -@@ -30,7 +30,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -807,59 +806,10 @@ static inline void __init kuser_init(void *vectors) - } - #endif - --#ifndef CONFIG_CPU_V7M --static void copy_from_lma(void *vma, void *lma_start, void *lma_end) --{ -- memcpy(vma, lma_start, lma_end - lma_start); --} -- --static void flush_vectors(void *vma, size_t offset, size_t size) --{ -- unsigned long start = (unsigned long)vma + offset; -- unsigned long end = start + size; -- -- flush_icache_range(start, end); --} -- --#ifdef CONFIG_HARDEN_BRANCH_HISTORY --int spectre_bhb_update_vectors(unsigned int method) --{ -- extern char __vectors_bhb_bpiall_start[], __vectors_bhb_bpiall_end[]; -- extern char __vectors_bhb_loop8_start[], __vectors_bhb_loop8_end[]; -- void *vec_start, *vec_end; -- -- if (system_state > SYSTEM_SCHEDULING) { -- pr_err("CPU%u: Spectre BHB workaround too late - system vulnerable\n", -- smp_processor_id()); -- return SPECTRE_VULNERABLE; -- } -- -- switch (method) { -- case SPECTRE_V2_METHOD_LOOP8: -- vec_start = __vectors_bhb_loop8_start; -- vec_end = __vectors_bhb_loop8_end; -- break; -- -- case SPECTRE_V2_METHOD_BPIALL: -- vec_start = __vectors_bhb_bpiall_start; -- vec_end = __vectors_bhb_bpiall_end; -- break; -- -- default: -- pr_err("CPU%u: unknown Spectre BHB state %d\n", -- smp_processor_id(), method); -- return SPECTRE_VULNERABLE; -- } -- -- copy_from_lma(vectors_page, vec_start, vec_end); -- flush_vectors(vectors_page, 0, vec_end - vec_start); -- -- return SPECTRE_MITIGATED; --} --#endif -- - void __init early_trap_init(void *vectors_base) - { -+#ifndef CONFIG_CPU_V7M -+ unsigned long vectors = (unsigned long)vectors_base; - extern char __stubs_start[], __stubs_end[]; - extern char __vectors_start[], __vectors_end[]; - unsigned i; -@@ -880,20 +830,17 @@ void __init early_trap_init(void *vectors_base) - * into the vector page, mapped at 0xffff0000, and ensure these - * are visible to the instruction stream. - */ -- copy_from_lma(vectors_base, __vectors_start, __vectors_end); -- copy_from_lma(vectors_base + 0x1000, __stubs_start, __stubs_end); -+ memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start); -+ memcpy((void *)vectors + 0x1000, __stubs_start, __stubs_end - __stubs_start); - - kuser_init(vectors_base); - -- flush_vectors(vectors_base, 0, PAGE_SIZE * 2); --} -+ flush_icache_range(vectors, vectors + PAGE_SIZE * 2); - #else /* ifndef CONFIG_CPU_V7M */ --void __init early_trap_init(void *vectors_base) --{ - /* - * on V7-M there is no need to copy the vector table to a dedicated - * memory area. The address is configurable and so a table in the kernel - * image can be used. - */ --} - #endif -+} -diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig -index 8b6fc72f2..02692fbe2 100644 ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -833,7 +833,6 @@ config CPU_BPREDICT_DISABLE - - config CPU_SPECTRE - bool -- select GENERIC_CPU_VULNERABILITIES - - config HARDEN_BRANCH_PREDICTOR - bool "Harden the branch predictor against aliasing attacks" if EXPERT -@@ -854,16 +853,6 @@ config HARDEN_BRANCH_PREDICTOR - - If unsure, say Y. - --config HARDEN_BRANCH_HISTORY -- bool "Harden Spectre style attacks against branch history" if EXPERT -- depends on CPU_SPECTRE -- default y -- help -- Speculation attacks against some high-performance processors can -- make use of branch history to influence future speculation. When -- taking an exception, a sequence of branches overwrites the branch -- history, or branch history is invalidated. -- - config TLS_REG_EMUL - bool - select NEED_KUSER_HELPERS -diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c -index d98fa83f5..cc9678275 100644 ---- a/arch/arm/mm/mmu.c -+++ b/arch/arm/mm/mmu.c -@@ -295,6 +295,13 @@ static struct mem_type mem_types[] __ro_after_init = { - .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, - .domain = DOMAIN_KERNEL, - }, -+ [MT_MEMORY_RW_NS] = { -+ .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | -+ L_PTE_XN, -+ .prot_l1 = PMD_TYPE_TABLE, -+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN, -+ .domain = DOMAIN_KERNEL, -+ }, - [MT_ROM] = { - .prot_sect = PMD_TYPE_SECT, - .domain = DOMAIN_KERNEL, -@@ -622,6 +629,7 @@ static void __init build_mem_type_table(void) - } - kern_pgprot |= PTE_EXT_AF; - vecs_pgprot |= PTE_EXT_AF; -+ mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte; - - /* - * Set PXN for user mappings -@@ -647,6 +655,7 @@ static void __init build_mem_type_table(void) - mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; - mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; - mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; -+ mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd; - mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; - mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; - mem_types[MT_ROM].prot_sect |= cp->pmd; -diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c -index 06dbfb968..114c05ab4 100644 ---- a/arch/arm/mm/proc-v7-bugs.c -+++ b/arch/arm/mm/proc-v7-bugs.c -@@ -6,35 +6,8 @@ - #include - #include - #include --#include - #include - --#ifdef CONFIG_ARM_PSCI --static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void) --{ -- struct arm_smccc_res res; -- -- arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, -- ARM_SMCCC_ARCH_WORKAROUND_1, &res); -- -- switch ((int)res.a0) { -- case SMCCC_RET_SUCCESS: -- return SPECTRE_MITIGATED; -- -- case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED: -- return SPECTRE_UNAFFECTED; -- -- default: -- return SPECTRE_VULNERABLE; -- } --} --#else --static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void) --{ -- return SPECTRE_VULNERABLE; --} --#endif -- - #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR - DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); - -@@ -63,61 +36,13 @@ static void __maybe_unused call_hvc_arch_workaround_1(void) - arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); - } - --static unsigned int spectre_v2_install_workaround(unsigned int method) -+static void cpu_v7_spectre_init(void) - { - const char *spectre_v2_method = NULL; - int cpu = smp_processor_id(); - - if (per_cpu(harden_branch_predictor_fn, cpu)) -- return SPECTRE_MITIGATED; -- -- switch (method) { -- case SPECTRE_V2_METHOD_BPIALL: -- per_cpu(harden_branch_predictor_fn, cpu) = -- harden_branch_predictor_bpiall; -- spectre_v2_method = "BPIALL"; -- break; -- -- case SPECTRE_V2_METHOD_ICIALLU: -- per_cpu(harden_branch_predictor_fn, cpu) = -- harden_branch_predictor_iciallu; -- spectre_v2_method = "ICIALLU"; -- break; -- -- case SPECTRE_V2_METHOD_HVC: -- per_cpu(harden_branch_predictor_fn, cpu) = -- call_hvc_arch_workaround_1; -- cpu_do_switch_mm = cpu_v7_hvc_switch_mm; -- spectre_v2_method = "hypervisor"; -- break; -- -- case SPECTRE_V2_METHOD_SMC: -- per_cpu(harden_branch_predictor_fn, cpu) = -- call_smc_arch_workaround_1; -- cpu_do_switch_mm = cpu_v7_smc_switch_mm; -- spectre_v2_method = "firmware"; -- break; -- } -- -- if (spectre_v2_method) -- pr_info("CPU%u: Spectre v2: using %s workaround\n", -- smp_processor_id(), spectre_v2_method); -- -- return SPECTRE_MITIGATED; --} --#else --static unsigned int spectre_v2_install_workaround(unsigned int method) --{ -- pr_info("CPU%u: Spectre V2: workarounds disabled by configuration\n", -- smp_processor_id()); -- -- return SPECTRE_VULNERABLE; --} --#endif -- --static void cpu_v7_spectre_v2_init(void) --{ -- unsigned int state, method = 0; -+ return; - - switch (read_cpuid_part()) { - case ARM_CPU_PART_CORTEX_A8: -@@ -126,133 +51,69 @@ static void cpu_v7_spectre_v2_init(void) - case ARM_CPU_PART_CORTEX_A17: - case ARM_CPU_PART_CORTEX_A73: - case ARM_CPU_PART_CORTEX_A75: -- state = SPECTRE_MITIGATED; -- method = SPECTRE_V2_METHOD_BPIALL; -+ per_cpu(harden_branch_predictor_fn, cpu) = -+ harden_branch_predictor_bpiall; -+ spectre_v2_method = "BPIALL"; - break; - - case ARM_CPU_PART_CORTEX_A15: - case ARM_CPU_PART_BRAHMA_B15: -- state = SPECTRE_MITIGATED; -- method = SPECTRE_V2_METHOD_ICIALLU; -+ per_cpu(harden_branch_predictor_fn, cpu) = -+ harden_branch_predictor_iciallu; -+ spectre_v2_method = "ICIALLU"; - break; - -+#ifdef CONFIG_ARM_PSCI - case ARM_CPU_PART_BRAHMA_B53: - /* Requires no workaround */ -- state = SPECTRE_UNAFFECTED; - break; -- - default: - /* Other ARM CPUs require no workaround */ -- if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) { -- state = SPECTRE_UNAFFECTED; -+ if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) - break; -- } -- - fallthrough; -- -- /* Cortex A57/A72 require firmware workaround */ -+ /* Cortex A57/A72 require firmware workaround */ - case ARM_CPU_PART_CORTEX_A57: -- case ARM_CPU_PART_CORTEX_A72: -- state = spectre_v2_get_cpu_fw_mitigation_state(); -- if (state != SPECTRE_MITIGATED) -- break; -+ case ARM_CPU_PART_CORTEX_A72: { -+ struct arm_smccc_res res; -+ -+ arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, -+ ARM_SMCCC_ARCH_WORKAROUND_1, &res); -+ if ((int)res.a0 != 0) -+ return; - - switch (arm_smccc_1_1_get_conduit()) { - case SMCCC_CONDUIT_HVC: -- method = SPECTRE_V2_METHOD_HVC; -+ per_cpu(harden_branch_predictor_fn, cpu) = -+ call_hvc_arch_workaround_1; -+ cpu_do_switch_mm = cpu_v7_hvc_switch_mm; -+ spectre_v2_method = "hypervisor"; - break; - - case SMCCC_CONDUIT_SMC: -- method = SPECTRE_V2_METHOD_SMC; -+ per_cpu(harden_branch_predictor_fn, cpu) = -+ call_smc_arch_workaround_1; -+ cpu_do_switch_mm = cpu_v7_smc_switch_mm; -+ spectre_v2_method = "firmware"; - break; - - default: -- state = SPECTRE_VULNERABLE; - break; - } - } -- -- if (state == SPECTRE_MITIGATED) -- state = spectre_v2_install_workaround(method); -- -- spectre_v2_update_state(state, method); --} -- --#ifdef CONFIG_HARDEN_BRANCH_HISTORY --static int spectre_bhb_method; -- --static const char *spectre_bhb_method_name(int method) --{ -- switch (method) { -- case SPECTRE_V2_METHOD_LOOP8: -- return "loop"; -- -- case SPECTRE_V2_METHOD_BPIALL: -- return "BPIALL"; -- -- default: -- return "unknown"; -- } --} -- --static int spectre_bhb_install_workaround(int method) --{ -- if (spectre_bhb_method != method) { -- if (spectre_bhb_method) { -- pr_err("CPU%u: Spectre BHB: method disagreement, system vulnerable\n", -- smp_processor_id()); -- -- return SPECTRE_VULNERABLE; -- } -- -- if (spectre_bhb_update_vectors(method) == SPECTRE_VULNERABLE) -- return SPECTRE_VULNERABLE; -- -- spectre_bhb_method = method; -+#endif - } - -- pr_info("CPU%u: Spectre BHB: using %s workaround\n", -- smp_processor_id(), spectre_bhb_method_name(method)); -- -- return SPECTRE_MITIGATED; -+ if (spectre_v2_method) -+ pr_info("CPU%u: Spectre v2: using %s workaround\n", -+ smp_processor_id(), spectre_v2_method); - } - #else --static int spectre_bhb_install_workaround(int method) -+static void cpu_v7_spectre_init(void) - { -- return SPECTRE_VULNERABLE; - } - #endif - --static void cpu_v7_spectre_bhb_init(void) --{ -- unsigned int state, method = 0; -- -- switch (read_cpuid_part()) { -- case ARM_CPU_PART_CORTEX_A15: -- case ARM_CPU_PART_BRAHMA_B15: -- case ARM_CPU_PART_CORTEX_A57: -- case ARM_CPU_PART_CORTEX_A72: -- state = SPECTRE_MITIGATED; -- method = SPECTRE_V2_METHOD_LOOP8; -- break; -- -- case ARM_CPU_PART_CORTEX_A73: -- case ARM_CPU_PART_CORTEX_A75: -- state = SPECTRE_MITIGATED; -- method = SPECTRE_V2_METHOD_BPIALL; -- break; -- -- default: -- state = SPECTRE_UNAFFECTED; -- break; -- } -- -- if (state == SPECTRE_MITIGATED) -- state = spectre_bhb_install_workaround(method); -- -- spectre_v2_update_state(state, method); --} -- - static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned, - u32 mask, const char *msg) - { -@@ -281,17 +142,16 @@ static bool check_spectre_auxcr(bool *warned, u32 bit) - void cpu_v7_ca8_ibe(void) - { - if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) -- cpu_v7_spectre_v2_init(); -+ cpu_v7_spectre_init(); - } - - void cpu_v7_ca15_ibe(void) - { - if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) -- cpu_v7_spectre_v2_init(); -+ cpu_v7_spectre_init(); - } - - void cpu_v7_bugs_init(void) - { -- cpu_v7_spectre_v2_init(); -- cpu_v7_spectre_bhb_init(); -+ cpu_v7_spectre_init(); - } -diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig -index 09c41d56f..3eb2326e2 100644 ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -1148,7 +1148,7 @@ config XEN - Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. - - config FORCE_MAX_ZONEORDER -- int -+ int "Maximum zone order" - default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) - default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) - default "11" -@@ -1182,15 +1182,6 @@ config UNMAP_KERNEL_AT_EL0 - - If unsure, say Y. - --config MITIGATE_SPECTRE_BRANCH_HISTORY -- bool "Mitigate Spectre style attacks against branch history" if EXPERT -- default y -- help -- Speculation attacks against some high-performance processors can -- make use of branch history to influence future speculation. -- When taking an exception from user-space, a sequence of branches -- or a firmware call overwrites the branch history. -- - config RODATA_FULL_DEFAULT_ENABLED - bool "Apply r/o permissions of VM areas also to their linear aliases" - default y -diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms -index 5c4ac1c9f..7c46cf293 100644 ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -191,14 +191,19 @@ config ARCH_MXC - select ARM64_ERRATUM_845719 if COMPAT - select IMX_GPCV2 - select IMX_GPCV2_PM_DOMAINS -+ select HAVE_IMX_BUSFREQ - select PM - select PM_GENERIC_DOMAINS - select SOC_BUS - select TIMER_IMX_SYS_CTR -+ select CLKSRC_IMX_TPM - help - This enables support for the ARMv8 based SoCs in the - NXP i.MX family. - -+config HAVE_IMX_BUSFREQ -+ bool "i.MX8M busfreq" -+ - config ARCH_QCOM - bool "Qualcomm Platforms" - select GPIOLIB -@@ -235,9 +240,18 @@ config ARCH_ROCKCHIP - - config ARCH_S32 - bool "NXP S32 SoC Family" -+ select ARCH_S32_CLK -+ select PINCTRL - help - This enables support for the NXP S32 family of processors. - -+if ARCH_S32 -+menu "S32 SOC selection" -+ config SOC_S32V234 -+ bool "S32V234 SOC" -+endmenu -+endif -+ - config ARCH_SEATTLE - bool "AMD Seattle SoC Family" - help -diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile -index 9b1170658..7ddd0648a 100644 ---- a/arch/arm64/boot/dts/Makefile -+++ b/arch/arm64/boot/dts/Makefile -@@ -12,6 +12,7 @@ subdir-y += broadcom - subdir-y += cavium - subdir-y += exynos - subdir-y += freescale -+subdir-y += myir - subdir-y += hisilicon - subdir-y += intel - subdir-y += lg -diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile -index f8d59433a..49642e6f3 100644 ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -1,4 +1,15 @@ - # SPDX-License-Identifier: GPL-2.0 -+ -+# required for overlay support -+DTC_FLAGS_fsl-ls1028a-qds := -@ -+DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ -+DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ -+DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ -+DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ -+DTC_FLAGS_fsl-ls1028a-qds-899b := -@ -+DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ -+ -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb -@@ -10,16 +21,35 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb-dpdk.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-sdk.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-usdpaa.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-shared-mac9-only.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa-shared-mac10.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa-shared.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb -@@ -27,17 +57,65 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb - - dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \ -+ imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb imx8mm-evk-revb-qca-wifi.dtb \ -+ imx8mm-evk-ecspi-slave.dtb \ -+ imx8mm-evk-pcie-ep.dtb \ -+ imx8mm-evk-usd-wifi.dtb \ -+ imx8mm-evk-qca-wifi.dtb \ -+ imx8mm-evk-rm67199.dtb \ -+ imx8mm-evk-dpdk.dtb \ -+ imx8mm-evk-lk.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-rpmsg-wm8524.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb \ -+ imx8mm-evk-iqaudio-dacplus.dtb imx8mm-evk-iqaudio-dacpro.dtb imx8mm-evk-hifiberry-dacplus.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb imx8mm-ddr4-evk-rm67191.dtb imx8mm-ddr4-evk-revb.dtb \ -+ imx8mm-ddr4-evk-revb-rm67191.dtb imx8mm-ddr4-evk-root.dtb \ -+ imx8mm-ddr4-evk-pcie-ep.dtb \ -+ imx8mm-ddr4-evk-inmate.dtb \ -+ imx8mm-ddr4-evk-revb-rm67199.dtb \ -+ imx8mm-ddr4-evk-rm67199.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-evk-rpmsg.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb imx8mm-ddr4-ab2.dtb imx8mm-ddr4-ab2-m4.dtb \ -+ imx8mm-ddr4-ab2-revb.dtb imx8mm-ddr4-ab2-m4-revb.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-evk-rpmsg.dtb imx8mn-evk-ak5558.dtb \ -+ imx8mn-evk-8mic-revE.dtb imx8mn-ddr3l-evk.dtb \ -+ imx8mn-evk-iqaudio-dacplus.dtb imx8mn-evk-iqaudio-dacpro.dtb imx8mn-evk-hifiberry-dacplus.dtb \ -+ imx8mn-evk-rm67199.dtb \ -+ imx8mn-ddr3l-evk-ak5558.dtb imx8mn-ddr3l-evk-rpmsg.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb imx8mn-ddr4-evk-rm67191.dtb \ -+ imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb imx8mn-ddr4-evk-rm67199.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb imx8mn-evk-root.dtb imx8mn-evk-inmate.dtb imx8mn-evk-lk.dtb imx8mn-ddr4-evk-lk.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ab2.dtb imx8mn-ddr4-ab2.dtb imx8mn-ddr3l-ab2.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-rm67191.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \ -+ imx8mp-evk-pcie-ep.dtb imx8mp-evk-rpmsg.dtb imx8mp-evk-ecspi-slave.dtb \ -+ imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-evk-flexcan2.dtb \ -+ imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-ov2775.dtb \ -+ imx8mp-evk-ov2775-ov5640.dtb imx8mp-evk-basler-ov5640.dtb imx8mp-evk-basler.dtb \ -+ imx8mp-evk-basler-ov2775.dtb imx8mp-evk-dual-basler.dtb \ -+ imx8mp-evk-dual-ov2775.dtb imx8mp-evk-spdif-lb.dtb \ -+ imx8mp-evk-sof-wm8960.dtb imx8mp-evk-dsp.dtb\ -+ imx8mp-evk-iqaudio-dacplus.dtb imx8mp-evk-iqaudio-dacpro.dtb imx8mp-evk-hifiberry-dacplus.dtb \ -+ imx8mp-evk-usdhc1-m2.dtb imx8mp-evk-rm67199.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mp-ab2.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-ndm.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ -+ imx8mq-evk-usdhc2-m2.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67191.dtb imx8mq-evk-lcdif-adv7535.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67199.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67191.dtb imx8mq-evk-dcss-adv7535.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67199.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dual-display.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb -@@ -45,10 +123,90 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie-ep.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ -+ imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb \ -+ imx8qm-mek-hdmi.dtb \ -+ imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ -+ imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ -+ imx8qm-mek-pcie-ep.dtb \ -+ imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-usd-wifi.dtb \ -+ imx8qm-mek-hdmi-rx.dtb \ -+ imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ -+ imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ -+ imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ -+ imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \ -+ imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \ -+ imx8qm-mek-dsi-rm67191.dtb imx8qm-lpddr4-val-dp.dtb\ -+ imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb \ -+ imx8qm-mek-cockpit-a53.dtb imx8qm-mek-cockpit-a72.dtb \ -+ imx8qm-mek-esai.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ -+ imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb \ -+ imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb \ -+ imx8dxl-evk-pcie-ep.dtb \ -+ imx8dxl-evk-lcdif.dtb \ -+ imx8dxl-evk-lpspi-slave.dtb \ -+ imx8dxl-evk-rpmsg.dtb \ -+ imx8dxl-ddr3-evk.dtb \ -+ imx8dxl-ddr3-evk-rpmsg.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb \ -+ imx8dxl-phantom-mek-rpmsg.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-ov5640.dtb \ -+ imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb \ -+ imx8qxp-mek-sof-cs42888.dtb imx8qxp-mek-sof-wm8960.dtb \ -+ imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb \ -+ imx8qxp-mek-it6263-lvds0-dual-channel.dtb \ -+ imx8qxp-mek-it6263-lvds1-dual-channel.dtb \ -+ imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ -+ imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ -+ imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ -+ imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ -+ imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ -+ imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ -+ imx8qxp-mek-dsi-rm67191.dtb \ -+ imx8qxp-mek-dsi-rm67191-rpmsg.dtb \ -+ imx8qxp-mek-ov5640-rpmsg.dtb \ -+ imx8qxp-mek-dpu-lcdif.dtb \ -+ imx8qxp-mek-dpu-lcdif-rpmsg.dtb \ -+ imx8qxp-mek-pcie-ep.dtb \ -+ imx8dx-mek.dtb imx8dx-mek-rpmsg.dtb \ -+ imx8dx-mek-enet2-tja1100.dtb \ -+ imx8dx-mek-it6263-lvds0-dual-channel.dtb \ -+ imx8dx-mek-it6263-lvds1-dual-channel.dtb \ -+ imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ -+ imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ -+ imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \ -+ imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \ -+ imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ -+ imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ -+ imx8dx-mek-ov5640.dtb \ -+ imx8dx-mek-ov5640-rpmsg.dtb \ -+ imx8dx-mek-dsi-rm67191.dtb \ -+ imx8dx-mek-dsi-rm67191-rpmsg.dtb \ -+ imx8qxp-mek-lcdif.dtb \ -+ imx8qxp-mek-lcdif-rpmsg.dtb \ -+ imx8qxp-lpddr4-val-a0.dtb \ -+ imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \ -+ imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ -+ imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ -+ imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ -+ imx8qxp-mek-inmate.dtb -+ -+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-root.dtb imx8dxl-evk-inmate.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb imx8ulp-evk-rk055hdmipi4m.dtb \ -+ imx8ulp-evk-lpspi-slave.dtb imx8ulp-evk-sof-btsco.dtb \ -+ imx8ulp-evk-i3c.dtb imx8ulp-evk-epdc.dtb \ -+ imx8ulp-evk-flexio-i2c.dtb imx8ulp-evk-nd.dtb - --dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb -+dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \ -+ s32v234-sbc.dtb -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts -new file mode 100644 -index 000000000..119bf4b38 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts -@@ -0,0 +1,89 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for NXP LS1012A 2G5RDB Board. -+ * -+ * Copyright 2017 NXP -+ * -+ * Bhaskar Upadhaya -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A 2G5RDB Board"; -+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii-2500"; -+ phy-handle = <&sgmii_phy1>; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii-2500"; -+ phy-handle = <&sgmii_phy2>; -+ }; -+ -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x1>; -+ }; -+ -+ sgmii_phy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x2>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -index 67702667e..3c1748ea2 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -13,6 +13,11 @@ / { - model = "LS1012A Freedom Board"; - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -89,6 +94,45 @@ s25fs512s0: flash@0 { - }; - }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy1>; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy2>; -+ }; -+ -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sgmii_phy1: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ -+ sgmii_phy2: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ }; -+}; -+ - &sai2 { - status = "okay"; - }; -@@ -96,3 +140,18 @@ &sai2 { - &sata { - status = "okay"; - }; -+ -+&qspi { -+ status = "okay"; -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <2>; -+ }; -+ -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -index 6290e2f9d..47df8f2c4 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -@@ -14,6 +14,58 @@ - / { - model = "LS1012A FRWY Board"; - compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ -+ sys_mclk: clock-mclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <25000000>; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,widgets = -+ "Microphone", "Microphone Jack", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Speaker Ext", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "MIC_IN", "Microphone Jack", -+ "Microphone Jack", "Mic Bias", -+ "LINE_IN", "Line In Jack", -+ "Headphone Jack", "HP_OUT", -+ "Speaker Ext", "LINE_OUT"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ frame-master; -+ bitclock-master; -+ system-clock-frequency = <25000000>; -+ }; -+ }; -+}; -+ -+&pcie1 { -+ status = "okay"; - }; - - &duart0 { -@@ -22,6 +74,74 @@ &duart0 { - - &i2c0 { - status = "okay"; -+ -+ codec: sgtl5000@a { -+ compatible = "fsl,sgtl5000"; -+ #sound-dai-cells = <0>; -+ reg = <0xa>; -+ VDDA-supply = <®_1p8v>; -+ VDDIO-supply = <®_1p8v>; -+ clocks = <&sys_mclk>; -+ }; -+}; -+ -+&qspi { -+ num-cs = <1>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: w25q16dw@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy1>; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy2>; -+ }; -+ -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sgmii_phy1: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ -+ sgmii_phy2: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ }; -+}; -+ -+&sai2 { -+ status = "okay"; - }; - - &qspi { -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -index 449475a97..92f10a9b5 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -13,6 +13,11 @@ / { - model = "LS1012A QDS Board"; - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -57,6 +62,10 @@ simple-audio-card,codec { - }; - }; - -+&pcie1 { -+ status = "okay"; -+}; -+ - &dspi { - bus-num = <0>; - status = "okay"; -@@ -143,6 +152,47 @@ s25fs512s0: flash@0 { - }; - }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x2>; -+ phy-mode = "sgmii-2500"; -+ phy-handle = <&sgmii_phy1>; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x3>; -+ phy-mode = "sgmii-2500"; -+ phy-handle = <&sgmii_phy2>; -+ }; -+ -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x1>; -+ }; -+ -+ sgmii_phy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x2>; -+ }; -+ }; -+}; -+ - &sai2 { - status = "okay"; - }; -@@ -150,3 +200,18 @@ &sai2 { - &sata { - status = "okay"; - }; -+ -+&qspi { -+ status = "okay"; -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <2>; -+ }; -+ -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -index d45c17620..37d823676 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -12,6 +12,15 @@ - / { - model = "LS1012A RDB Board"; - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+}; -+ -+&pcie1 { -+ status = "okay"; - }; - - &duart0 { -@@ -53,3 +62,56 @@ s25fs512s0: flash@0 { - &sata { - status = "okay"; - }; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy>; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&rgmii_phy>; -+ }; -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sgmii_phy: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ -+ rgmii_phy: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ -+ s25fs512s0: flash@0 { -+ compatible = "jedec,spi-nor"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -index 5fd3ea202..e31eb5914 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -@@ -18,6 +18,8 @@ / { - - aliases { - crypto = &crypto; -+ mmc0 = &esdhc0; -+ mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; - rtic-a = &rtic_a; - rtic-b = &rtic_b; -@@ -276,7 +278,7 @@ sec_mon: sec_mon@1e90000 { - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1012a-dcfg", - "syscon"; -- reg = <0x0 0x1ee0000 0x0 0x10000>; -+ reg = <0x0 0x1ee0000 0x0 0x1000>; - big-endian; - }; - -@@ -334,12 +336,13 @@ tmu: tmu@1f00000 { - }; - - i2c0: i2c@2180000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; -+ scl-gpios = <&gpio0 13 0>; - status = "disabled"; - }; - -@@ -456,13 +459,15 @@ edma0: edma@2c00000 { - }; - - usb0: usb3@2f00000 { -- compatible = "snps,dwc3"; -+ compatible = "fsl,ls1012a-dwc3", "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ dma-coherent; - }; - - sata: sata@3200000 { -@@ -513,6 +518,7 @@ pcie1: pcie@3400000 { - <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; - status = "disabled"; - }; - -@@ -531,6 +537,35 @@ ftm_alarm0: timer@29d0000 { - }; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ pfe_reserved: packetbuffer@83400000 { -+ reg = <0 0x83400000 0 0xc00000>; -+ }; -+ }; -+ -+ pfe: pfe@4000000 { -+ compatible = "fsl,pfe"; -+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ -+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ -+ reg-names = "pfe", "pfe-ddr"; -+ fsl,pfe-num-interfaces = <0x2>; -+ interrupts = <0 172 0x4>, /* HIF interrupt */ -+ <0 173 0x4>, /*HIF_NOCPY interrupt */ -+ <0 174 0x4>; /* WoL interrupt */ -+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; -+ memory-region = <&pfe_reserved>; -+ fsl,pfe-scfg = <&scfg 0>; -+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "pfe"; -+ -+ status = "okay"; -+ }; -+ - firmware { - optee { - compatible = "linaro,optee-tz"; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts -new file mode 100644 -index 000000000..a9e36e451 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts -@@ -0,0 +1,109 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree fragment for LS1028A QDS board, serdes 13bb -+ * -+ * Copyright 2019 NXP -+ * -+ * Requires a LS1028A QDS board with lane B rework. -+ * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. -+ * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ fragment@0 { -+ target = <&mdio_slot1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ slot1_sgmii: ethernet-phy@2 { -+ /* AQR112 */ -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&enetc_port0>; -+ __overlay__ { -+ phy-handle = <&slot1_sgmii>; -+ phy-mode = "usxgmii"; -+ managed = "in-band-status"; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mdio_slot2>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* 4 ports on AQR412 */ -+ slot2_qxgmii0: ethernet-phy@0 { -+ reg = <0x0>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ -+ slot2_qxgmii1: ethernet-phy@1 { -+ reg = <0x1>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ -+ slot2_qxgmii2: ethernet-phy@2 { -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ -+ slot2_qxgmii3: ethernet-phy@3 { -+ reg = <0x3>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&mscc_felix_ports>; -+ __overlay__ { -+ port@0 { -+ status = "okay"; -+ phy-handle = <&slot2_qxgmii0>; -+ phy-mode = "usxgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@1 { -+ status = "okay"; -+ phy-handle = <&slot2_qxgmii1>; -+ phy-mode = "usxgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ phy-handle = <&slot2_qxgmii2>; -+ phy-mode = "usxgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@3 { -+ status = "okay"; -+ phy-handle = <&slot2_qxgmii3>; -+ phy-mode = "usxgmii"; -+ managed = "in-band-status"; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&mscc_felix>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi -new file mode 100644 -index 000000000..64ab346ed ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes 1xxx -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot1 { -+ slot1_sgmii: ethernet-phy@2 { -+ /* AQR112 */ -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+}; -+ -+&enetc_port0 { -+ phy-handle = <&slot1_sgmii>; -+ phy-connection-type = "usxgmii"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts -new file mode 100644 -index 000000000..fdcf00a0c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts -@@ -0,0 +1,103 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree fragment for LS1028A QDS board, serdes 69xx -+ * -+ * Copyright 2019 NXP -+ * -+ * Requires a LS1028A QDS board with lane B rework. -+ * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ fragment@0 { -+ target = <&mdio_slot1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ slot1_sgmii: ethernet-phy@2 { -+ /* AQR112 */ -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&enetc_port0>; -+ __overlay__ { -+ phy-handle = <&slot1_sgmii>; -+ phy-mode = "2500base-x"; -+ managed = "in-band-status"; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mdio_slot2>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* 4 ports on VSC8514 */ -+ slot2_qsgmii0: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ -+ slot2_qsgmii1: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ -+ slot2_qsgmii2: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ -+ slot2_qsgmii3: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&mscc_felix_ports>; -+ __overlay__ { -+ port@0 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii0>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@1 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii1>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii2>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@3 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii3>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&mscc_felix>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi -new file mode 100644 -index 000000000..40aa217da ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes 6xxx -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot1 { -+ slot1_sgmii: ethernet-phy@2 { -+ /* AQR112 */ -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+}; -+ -+&enetc_port0 { -+ phy-handle = <&slot1_sgmii>; -+ phy-connection-type = "2500base-x"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts -new file mode 100644 -index 000000000..6b097a54a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts -@@ -0,0 +1,81 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree fragment for LS1028A QDS board, serdes 7777 -+ * -+ * Copyright 2019 NXP -+ * -+ * Requires a LS1028A QDS board without lane B rework. -+ * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing -+ * disabled, plugged in slot 1. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ fragment@0 { -+ target = <&mdio_slot1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* 4 ports on AQR412 */ -+ slot1_sxgmii0: ethernet-phy@0 { -+ reg = <0x0>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ -+ slot1_sxgmii1: ethernet-phy@1 { -+ reg = <0x1>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ -+ slot1_sxgmii2: ethernet-phy@2 { -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ -+ slot1_sxgmii3: ethernet-phy@3 { -+ reg = <0x3>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&mscc_felix_ports>; -+ __overlay__ { -+ port@0 { -+ status = "okay"; -+ phy-handle = <&slot1_sxgmii0>; -+ phy-mode = "2500base-x"; -+ }; -+ -+ port@1 { -+ status = "okay"; -+ phy-handle = <&slot1_sxgmii1>; -+ phy-mode = "2500base-x"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ phy-handle = <&slot1_sxgmii2>; -+ phy-mode = "2500base-x"; -+ }; -+ -+ port@3 { -+ status = "okay"; -+ phy-handle = <&slot1_sxgmii3>; -+ phy-mode = "2500base-x"; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mscc_felix>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi -new file mode 100644 -index 000000000..cc7d3e862 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi -@@ -0,0 +1,56 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes 9999 -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot1 { -+ /* two ports on AQR412 */ -+ slot1_sxgmii2: ethernet-phy@2 { -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ slot1_sxgmii3: ethernet-phy@3 { -+ reg = <0x3>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+}; -+ -+&mdio_slot2 { -+ slot2_sxgmii0: ethernet-phy@2 { -+ /* AQR112 */ -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+}; -+ -+&mdio_slot3 { -+ slot3_sxgmii0: ethernet-phy@2 { -+ /* AQR112 */ -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+}; -+ -+/* l2switch ports */ -+&switch_port0 { -+ phy-handle = <&slot1_sxgmii2>; -+ phy-connection-type = "2500base-x"; -+}; -+ -+&switch_port1 { -+ phy-handle = <&slot2_sxgmii0>; -+ phy-connection-type = "2500base-x"; -+}; -+ -+&switch_port2 { -+ phy-handle = <&slot3_sxgmii0>; -+ phy-connection-type = "2500base-x"; -+}; -+ -+&switch_port3 { -+ phy-handle = <&slot1_sxgmii3>; -+ phy-connection-type = "2500base-x"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts -new file mode 100644 -index 000000000..5f836cf08 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree fragment for LS1028A QDS board, serdes 85bb -+ * -+ * Copyright 2019 NXP -+ * -+ * Requires a LS1028A QDS board with lane B rework. -+ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ fragment@0 { -+ target = <&mdio_slot1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ slot1_sgmii: ethernet-phy@1c { -+ /* 1st port on VSC8234 */ -+ reg = <0x1c>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&enetc_port0>; -+ __overlay__ { -+ phy-handle = <&slot1_sgmii>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mdio_slot2>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* 4 ports on VSC8514 */ -+ slot2_qsgmii0: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ -+ slot2_qsgmii1: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ -+ slot2_qsgmii2: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ -+ slot2_qsgmii3: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&mscc_felix_ports>; -+ __overlay__ { -+ port@0 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii0>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@1 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii1>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii2>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@3 { -+ status = "okay"; -+ phy-handle = <&slot2_qsgmii3>; -+ phy-mode = "qsgmii"; -+ managed = "in-band-status"; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&mscc_felix>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts -new file mode 100644 -index 000000000..89d8595b3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts -@@ -0,0 +1,75 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree fragment for LS1028A QDS board, serdes 85xx -+ * -+ * Copyright 2019 NXP -+ * -+ * Requires a LS1028A QDS board without lane B rework. -+ * Requires a SCH-24801 card in slot 1. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ fragment@0 { -+ target = <&mdio_slot1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* VSC8234 */ -+ slot1_sgmii0: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ -+ slot1_sgmii1: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ -+ slot1_sgmii2: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ -+ slot1_sgmii3: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&enetc_port0>; -+ __overlay__ { -+ phy-handle = <&slot1_sgmii0>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mscc_felix_ports>; -+ __overlay__ { -+ port@1 { -+ status = "okay"; -+ phy-handle = <&slot1_sgmii1>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ phy-handle = <&slot1_sgmii2>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ }; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&mscc_felix>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi -new file mode 100644 -index 000000000..8b19092e1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes 8xxx -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot1 { -+ slot1_sgmii: ethernet-phy@1c { -+ /* 1st port on VSC8234 */ -+ reg = <0x1c>; -+ }; -+}; -+ -+&enetc_port0 { -+ phy-handle = <&slot1_sgmii>; -+ phy-connection-type = "sgmii"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts -new file mode 100644 -index 000000000..6c0bc3266 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts -@@ -0,0 +1,79 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree fragment for LS1028A QDS board, serdes 85xx -+ * -+ * Copyright 2019 NXP -+ * -+ * Requires a LS1028A QDS board without lane B rework. -+ * Requires a SCH-24801 card in slot 1. -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ fragment@0 { -+ target = <&mdio_slot1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* VSC8234 */ -+ slot1_sgmii0: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ -+ slot1_sgmii1: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ -+ slot1_sgmii2: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ -+ slot1_sgmii3: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&mscc_felix_ports>; -+ __overlay__ { -+ port@0 { -+ status = "okay"; -+ phy-handle = <&slot1_sgmii0>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@1 { -+ status = "okay"; -+ phy-handle = <&slot1_sgmii1>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ phy-handle = <&slot1_sgmii2>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ }; -+ -+ port@3 { -+ status = "okay"; -+ phy-handle = <&slot1_sgmii3>; -+ phy-mode = "sgmii"; -+ managed = "in-band-status"; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mscc_felix>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi -new file mode 100644 -index 000000000..706798ebd ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes 9999 -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot1 { -+ /* VSC8234 */ -+ slot1_sgmii0: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ slot1_sgmii1: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ slot1_sgmii2: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ slot1_sgmii3: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+}; -+ -+&mdio_slot2 { -+ /* VSC8234 */ -+ slot2_sgmii0: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ slot2_sgmii1: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ slot2_sgmii2: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ slot2_sgmii3: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+}; -+ -+/* l2switch ports */ -+&switch_port0 { -+ phy-handle = <&slot1_sgmii0>; -+ phy-connection-type = "sgmii"; -+}; -+ -+&switch_port1 { -+ phy-handle = <&slot2_sgmii0>; -+ phy-connection-type = "sgmii"; -+}; -+ -+&switch_port2 { -+ phy-handle = <&slot1_sgmii2>; -+ phy-connection-type = "sgmii"; -+}; -+ -+&switch_port3 { -+ phy-handle = <&slot1_sgmii3>; -+ phy-connection-type = "sgmii"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi -new file mode 100644 -index 000000000..4220cf2d8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi -@@ -0,0 +1,48 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes x3xx -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot2 { -+ /* 4 ports on AQR412 */ -+ slot2_qsgmii0: ethernet-phy@0 { -+ reg = <0x0>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ slot2_qsgmii1: ethernet-phy@1 { -+ reg = <0x1>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ slot2_qsgmii2: ethernet-phy@2 { -+ reg = <0x2>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+ slot2_qsgmii3: ethernet-phy@3 { -+ reg = <0x3>; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ }; -+}; -+ -+/* l2switch ports */ -+&switch_port0 { -+ phy-handle = <&slot2_qsgmii0>; -+ phy-connection-type = "usxgmii"; -+}; -+ -+&switch_port1 { -+ phy-handle = <&slot2_qsgmii1>; -+ phy-connection-type = "usxgmii"; -+}; -+ -+&switch_port2 { -+ phy-handle = <&slot2_qsgmii2>; -+ phy-connection-type = "usxgmii"; -+}; -+ -+&switch_port3 { -+ phy-handle = <&slot2_qsgmii3>; -+ phy-connection-type = "usxgmii"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi -new file mode 100644 -index 000000000..33aa21bb1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for LS1028A QDS board, serdes x5xx -+ * -+ * Copyright 2019 NXP -+ * -+ */ -+ -+&mdio_slot2 { -+ /* 4 ports on VSC8514 */ -+ slot2_qsgmii0: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ slot2_qsgmii1: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ slot2_qsgmii2: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ slot2_qsgmii3: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+}; -+ -+/* l2switch ports */ -+&mscc_felix_port0 { -+ phy-handle = <&slot2_qsgmii0>; -+ phy-connection-type = "qsgmii"; -+}; -+ -+&mscc_felix_port1 { -+ phy-handle = <&slot2_qsgmii1>; -+ phy-connection-type = "qsgmii"; -+}; -+ -+&mscc_felix_port2 { -+ phy-handle = <&slot2_qsgmii2>; -+ phy-connection-type = "qsgmii"; -+}; -+ -+&mscc_felix_port3 { -+ phy-handle = <&slot2_qsgmii3>; -+ phy-connection-type = "qsgmii"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts -index 13cdc958b..62996a12e 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts -@@ -2,7 +2,7 @@ - /* - * Device Tree file for NXP LS1028A QDS Board. - * -- * Copyright 2018 NXP -+ * Copyright 2018-2019 NXP - * - * Harninder Rai - * -@@ -104,9 +104,37 @@ qds_phy1: ethernet-phy@5 { - reg = <5>; - }; - }; -+ -+ mdio_slot1: mdio@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <4>; -+ }; -+ -+ mdio_slot2: mdio@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <5>; -+ }; -+ -+ mdio_slot3: mdio@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <6>; -+ }; -+ -+ mdio_slot4: mdio@7 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <7>; -+ }; - }; - }; - -+&ftm_alarm1 { -+ status = "okay"; -+}; -+ - &dspi0 { - bus-num = <0>; - status = "okay"; -@@ -192,6 +220,14 @@ flash@0 { - }; - }; - -+&can0 { -+ status = "okay"; -+}; -+ -+&can1 { -+ status = "okay"; -+}; -+ - &duart0 { - status = "okay"; - }; -@@ -223,6 +259,91 @@ mt35xu02g0: flash@0 { - }; - }; - -+&dspi0 { -+ bus-num = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "sst25wf040b", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "en25s64", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <1>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "m25q512a", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <2>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&dspi1 { -+ bus-num = <1>; -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "sst25wf040b", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "en25s64", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <1>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "m25q512a", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <2>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&dspi2 { -+ bus-num = <2>; -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "en25s64", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -261,11 +382,6 @@ temperature-sensor@4c { - vcc-supply = <&sb_3v3>; - }; - -- rtc@51 { -- compatible = "nxp,pcf2129"; -- reg = <0x51>; -- }; -- - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; -@@ -307,16 +423,37 @@ mux: mux-controller { - - }; - -+&i2c1 { -+ status = "okay"; -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ }; -+}; -+ - &enetc_port1 { - phy-handle = <&qds_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; - }; - -+&enetc_port2 { -+ status = "okay"; -+}; -+ - &lpuart0 { - status = "okay"; - }; - -+&lpuart1 { -+ status = "okay"; -+}; -+ -+&mscc_felix_port4 { -+ ethernet = <&enetc_port2>; -+ status = "okay"; -+}; -+ - &sai1 { - status = "okay"; - }; -@@ -324,3 +461,11 @@ &sai1 { - &sata { - status = "okay"; - }; -+ -+&hdptx0 { -+ lane-mapping = <0x4e>; -+ status = "okay"; -+}; -+ -+#include "fsl-ls1028a-qds-8xxx.dtsi" -+#include "fsl-ls1028a-qds-x5xx.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts -new file mode 100644 -index 000000000..ac9044386 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * NXP LS1028A RDB Board device tree file for DPDK -+ * -+ * Copyright 2018-2020 NXP -+ */ -+ -+/dts-v1/; -+#include "fsl-ls1028a-rdb.dts" -+ -+&enetc_port0 { -+ /delete-property/ phy-handle; -+ /delete-property/ phy-connection-type; -+ /delete-node/ mdio; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+}; -+ -+/delete-node/ &enetc_mdio_pf3; -+ -+/* l2switch ports */ -+&mscc_felix_port0 { -+ /delete-property/ phy-handle; -+}; -+ -+&mscc_felix_port1 { -+ /delete-property/ phy-handle; -+}; -+ -+&mscc_felix_port2 { -+ /delete-property/ phy-handle; -+}; -+ -+&mscc_felix_port3 { -+ /delete-property/ phy-handle; -+}; -+ -+&mscc_felix_port5 { -+ status = "okay"; -+}; -+ -+&enetc_port3 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts -index 1efb61cff..1b6497808 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts -@@ -2,7 +2,7 @@ - /* - * Device Tree file for NXP LS1028A RDB Board. - * -- * Copyright 2018 NXP -+ * Copyright 2018-2019 NXP - * - * Harninder Rai - * -@@ -113,6 +113,10 @@ mt35xu02g0: flash@0 { - }; - }; - -+&ftm_alarm1 { -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -169,6 +173,22 @@ rtc@51 { - }; - }; - -+&can0 { -+ status = "okay"; -+ -+ can-transceiver { -+ max-bitrate = <5000000>; -+ }; -+}; -+ -+&can1 { -+ status = "okay"; -+ -+ can-transceiver { -+ max-bitrate = <5000000>; -+ }; -+}; -+ - &duart0 { - status = "okay"; - }; -@@ -256,6 +276,15 @@ &mscc_felix_port4 { - status = "okay"; - }; - -+&hdptx0 { -+ lane-mapping = <0x4e>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ - &sai4 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi -index 580690057..75fa5e810 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi -@@ -18,7 +18,9 @@ / { - #size-cells = <2>; - - aliases { -- rtc1 = &ftm_alarm0; -+ mmc0 = &esdhc; -+ mmc1 = &esdhc1; -+ rtc1 = &ftm_alarm1; - }; - - cpus { -@@ -69,6 +71,13 @@ CPU_PW20: cpu-pw20 { - }; - }; - -+ rtc_clk: rtc-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "rtc_clk"; -+ }; -+ - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -387,7 +396,8 @@ esdhc1: mmc@2150000 { - }; - - can0: can@2180000 { -- compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; -+ compatible = "fsl,ls1028ar1-flexcan", -+ "fsl,lx2160ar1-flexcan"; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clocks = <&sysclk>, <&clockgen 4 1>; -@@ -396,7 +406,8 @@ can0: can@2180000 { - }; - - can1: can@2190000 { -- compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; -+ compatible = "fsl,ls1028ar1-flexcan", -+ "fsl,lx2160ar1-flexcan"; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clocks = <&sysclk>, <&clockgen 4 1>; -@@ -549,6 +560,7 @@ usb0: usb@3100000 { - snps,dis_rxdet_inp3_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ dma-coherent; - }; - - usb1: usb@3110000 { -@@ -559,6 +571,7 @@ usb1: usb@3110000 { - snps,dis_rxdet_inp3_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ dma-coherent; - }; - - sata: sata@3200000 { -@@ -598,6 +611,18 @@ pcie1: pcie@3400000 { - status = "disabled"; - }; - -+ pcie_ep1: pcie_ep@3400000 { -+ compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; -+ reg = <0x00 0x03400000 0x0 0x00100000 -+ 0x80 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; -+ num-ib-windows = <6>; -+ num-ob-windows = <8>; -+ status = "disabled"; -+ }; -+ - pcie2: pcie@3500000 { - compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -@@ -625,6 +650,18 @@ pcie2: pcie@3500000 { - status = "disabled"; - }; - -+ pcie_ep2: pcie_ep@3500000 { -+ compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; -+ reg = <0x00 0x03500000 0x0 0x00100000 -+ 0x88 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; -+ num-ib-windows = <6>; -+ num-ob-windows = <8>; -+ status = "disabled"; -+ }; -+ - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; -@@ -750,6 +787,16 @@ cluster1_core1_watchdog: watchdog@c010000 { - clock-names = "wdog_clk", "apb_pclk"; - }; - -+ gpu@f0c0000 { -+ compatible = "fsl,ls1028a-gpu"; -+ reg = <0x0 0x0f0c0000 0x0 0x10000>, -+ <0x0 0x80000000 0x0 0x80000000>, -+ <0x0 0x0 0x0 0x3000000>; -+ reg-names = "base", "phys_baseaddr", -+ "contiguous_mem"; -+ interrupts = ; -+ }; -+ - sai1: audio-controller@f100000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; -@@ -963,7 +1010,7 @@ mscc_felix: ethernet-switch@0,5 { - interrupts = ; - status = "disabled"; - -- ports { -+ mscc_felix_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - -@@ -991,6 +1038,7 @@ mscc_felix_port3: port@3 { - /* Internal ports */ - mscc_felix_port4: port@4 { - reg = <4>; -+ ethernet = <&enetc_port2>; - phy-mode = "internal"; - status = "disabled"; - -@@ -1026,6 +1074,100 @@ fixed-link { - }; - }; - -+ /* Integrated Endpoint Register Block */ -+ ierb@1f0800000 { -+ compatible = "fsl,ls1028a-enetc-ierb"; -+ reg = <0x01 0xf0800000 0x0 0x10000>; -+ }; -+ -+ pwm0: pwm@2800000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2800000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@2810000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2810000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@2820000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2820000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@2830000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2830000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@2840000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2840000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm5: pwm@2850000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2850000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm6: pwm@2860000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2860000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ pwm7: pwm@2870000 { -+ compatible = "fsl,vf610-ftm-pwm"; -+ #pwm-cells = <3>; -+ reg = <0x0 0x2870000 0x0 0x10000>; -+ clock-names = "ftm_sys", "ftm_ext", -+ "ftm_fix", "ftm_cnt_clk_en"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&rtc_clk>, <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ - rcpm: power-controller@1e34040 { - compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1e34040 0x0 0x1c>; -@@ -1038,6 +1180,22 @@ ftm_alarm0: timer@2800000 { - reg = <0x0 0x2800000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; - interrupts = ; -+ status = "disabled"; -+ }; -+ -+ ftm_alarm1: timer@2810000 { -+ compatible = "fsl,ls1028a-ftm-alarm"; -+ reg = <0x0 0x2810000 0x0 0x10000>; -+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; - }; - }; - -@@ -1055,7 +1213,23 @@ malidp0: display@f080000 { - - port { - dp0_out: endpoint { -+ remote-endpoint = <&dp1_out>; -+ }; -+ }; -+ }; -+ -+ hdptx0: display@f200000 { -+ compatible = "cdn,ls1028a-dp"; -+ reg = <0x0 0xf200000 0x0 0xfffff>; -+ interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>, -+ <&clockgen 2 2>, <&clockgen 2 2>, <&dpclk>; -+ clock-names = "clk_core", "pclk", "sclk", -+ "cclk", "clk_vif", "clk_pxl"; - -+ port { -+ dp1_out: endpoint { -+ remote-endpoint = <&dp0_out>; - }; - }; - }; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts -new file mode 100644 -index 000000000..0878d6b8c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts -@@ -0,0 +1,263 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1043a-qds.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+/delete-property/ dma-coherent; -+ -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+ -+pcie@3400000 { -+ /delete-property/ iommu-map; -+ dma-coherent; -+}; -+ -+pcie@3500000 { -+ /delete-property/ iommu-map; -+ dma-coherent; -+}; -+ -+pcie@3600000 { -+ /delete-property/ iommu-map; -+ dma-coherent; -+}; -+ -+/delete-node/ iommu@9000000; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+ dma-coherent; -+}; -+ -+&clockgen { -+ dma-coherent; -+}; -+ -+&scfg { -+ dma-coherent; -+}; -+ -+&crypto { -+ dma-coherent; -+}; -+ -+&dcfg { -+ dma-coherent; -+}; -+ -+&ifc { -+ dma-coherent; -+}; -+ -+&qspi { -+ dma-coherent; -+}; -+ -+&esdhc { -+ dma-coherent; -+}; -+ -+&ddr { -+ dma-coherent; -+}; -+ -+&tmu { -+ dma-coherent; -+}; -+ -+&qman { -+ dma-coherent; -+}; -+ -+&bman { -+ dma-coherent; -+}; -+ -+&bportals { -+ dma-coherent; -+}; -+ -+&qportals { -+ dma-coherent; -+}; -+ -+&dspi0 { -+ dma-coherent; -+}; -+ -+&dspi1 { -+ dma-coherent; -+}; -+ -+&i2c0 { -+ dma-coherent; -+}; -+ -+&i2c1 { -+ dma-coherent; -+}; -+ -+&i2c2 { -+ dma-coherent; -+}; -+ -+&i2c3 { -+ dma-coherent; -+}; -+ -+&duart0 { -+ dma-coherent; -+}; -+ -+&duart1 { -+ dma-coherent; -+}; -+ -+&duart2 { -+ dma-coherent; -+}; -+ -+&duart3 { -+ dma-coherent; -+}; -+ -+&gpio1 { -+ dma-coherent; -+}; -+ -+&gpio2 { -+ dma-coherent; -+}; -+ -+&gpio3 { -+ dma-coherent; -+}; -+ -+&gpio4 { -+ dma-coherent; -+}; -+ -+&uqe { -+ dma-coherent; -+}; -+ -+&lpuart0 { -+ dma-coherent; -+}; -+ -+&lpuart1 { -+ dma-coherent; -+}; -+ -+&lpuart2 { -+ dma-coherent; -+}; -+ -+&lpuart3 { -+ dma-coherent; -+}; -+ -+&lpuart4 { -+ dma-coherent; -+}; -+ -+&lpuart5 { -+ dma-coherent; -+}; -+ -+&ftm0 { -+ dma-coherent; -+}; -+ -+&wdog0 { -+ dma-coherent; -+}; -+ -+&edma0 { -+ dma-coherent; -+}; -+ -+&qdma { -+ dma-coherent; -+}; -+ -+&msi1 { -+ dma-coherent; -+}; -+ -+&msi2 { -+ dma-coherent; -+}; -+ -+&msi3 { -+ dma-coherent; -+}; -+ -+&ptp_timer0 { -+ dma-coherent; -+}; -+ -+&fsldpaa { -+ dma-coherent; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts -index fea167d22..9269ec5bb 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts -@@ -3,7 +3,7 @@ - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. -- * Copyright 2018 NXP -+ * Copyright 2018-2019 NXP - * - * Mingkai Hu - */ -@@ -24,6 +24,22 @@ aliases { - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; -+ sgmii-riser-s1-p1 = &sgmii_phy_s1_p1; -+ sgmii-riser-s2-p1 = &sgmii_phy_s2_p1; -+ sgmii-riser-s3-p1 = &sgmii_phy_s3_p1; -+ sgmii-riser-s4-p1 = &sgmii_phy_s4_p1; -+ qsgmii-s1-p1 = &qsgmii_phy_s1_p1; -+ qsgmii-s1-p2 = &qsgmii_phy_s1_p2; -+ qsgmii-s1-p3 = &qsgmii_phy_s1_p3; -+ qsgmii-s1-p4 = &qsgmii_phy_s1_p4; -+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1; -+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2; -+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3; -+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4; -+ emi1-slot1 = &ls1043mdio_s1; -+ emi1-slot2 = &ls1043mdio_s2; -+ emi1-slot3 = &ls1043mdio_s3; -+ emi1-slot4 = &ls1043mdio_s4; - }; - - chosen { -@@ -62,8 +78,11 @@ nand@1,0 { - }; - - fpga: board-control@2,0 { -- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; -+ compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus"; - reg = <0x2 0x0 0x0000100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 2 0 0x100>; - }; - }; - -@@ -153,3 +172,149 @@ &usb0 { - }; - - #include "fsl-ls1043-post.dtsi" -+ -+&fman0 { -+ ethernet@e0000 { -+ phy-handle = <&qsgmii_phy_s2_p1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e2000 { -+ phy-handle = <&qsgmii_phy_s2_p2>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&qsgmii_phy_s2_p3>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&qsgmii_phy_s2_p4>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@f0000 { /* DTSEC9/10GEC1 */ -+ fixed-link = <1 1 10000 0 0>; -+ phy-connection-type = "xgmii"; -+ }; -+}; -+ -+&fpga { -+ mdio-mux-emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&mdio0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1 */ -+ -+ /* On-board RGMII1 PHY */ -+ ls1043mdio0: mdio@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */ -+ reg = <0x1>; -+ rtl821x,aldps-disable; -+ }; -+ }; -+ -+ /* On-board RGMII2 PHY */ -+ ls1043mdio1: mdio@1 { -+ reg = <0x20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */ -+ reg = <0x2>; -+ rtl821x,aldps-disable; -+ }; -+ }; -+ -+ /* Slot 1 */ -+ ls1043mdio_s1: mdio@2 { -+ reg = <0x40>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ qsgmii_phy_s1_p1: ethernet-phy@4 { -+ reg = <0x4>; -+ }; -+ qsgmii_phy_s1_p2: ethernet-phy@5 { -+ reg = <0x5>; -+ }; -+ qsgmii_phy_s1_p3: ethernet-phy@6 { -+ reg = <0x6>; -+ }; -+ qsgmii_phy_s1_p4: ethernet-phy@7 { -+ reg = <0x7>; -+ }; -+ -+ sgmii_phy_s1_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ -+ /* Slot 2 */ -+ ls1043mdio_s2: mdio@3 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ qsgmii_phy_s2_p1: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ qsgmii_phy_s2_p2: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ qsgmii_phy_s2_p3: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ qsgmii_phy_s2_p4: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+ -+ sgmii_phy_s2_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ -+ /* Slot 3 */ -+ ls1043mdio_s3: mdio@4 { -+ reg = <0x80>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s3_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ -+ /* Slot 4 */ -+ ls1043mdio_s4: mdio@5 { -+ reg = <0xa0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s4_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts -new file mode 100644 -index 000000000..5bfd2262d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts -@@ -0,0 +1,262 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1043a-rdb.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+/delete-property/ dma-coherent; -+ -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+ -+pcie@3400000 { -+ /delete-property/ iommu-map; -+ dma-coherent; -+}; -+ -+pcie@3500000 { -+ /delete-property/ iommu-map; -+ dma-coherent; -+}; -+ -+pcie@3600000 { -+ /delete-property/ iommu-map; -+ dma-coherent; -+}; -+ -+/delete-node/ iommu@9000000; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; -+ -+&clockgen { -+ dma-coherent; -+}; -+ -+&scfg { -+ dma-coherent; -+}; -+ -+&crypto { -+ dma-coherent; -+}; -+ -+&dcfg { -+ dma-coherent; -+}; -+ -+&ifc { -+ dma-coherent; -+}; -+ -+&qspi { -+ dma-coherent; -+}; -+ -+&esdhc { -+ dma-coherent; -+}; -+ -+&ddr { -+ dma-coherent; -+}; -+ -+&tmu { -+ dma-coherent; -+}; -+ -+&qman { -+ dma-coherent; -+}; -+ -+&bman { -+ dma-coherent; -+}; -+ -+&bportals { -+ dma-coherent; -+}; -+ -+&qportals { -+ dma-coherent; -+}; -+ -+&dspi0 { -+ dma-coherent; -+}; -+ -+&dspi1 { -+ dma-coherent; -+}; -+ -+&i2c0 { -+ dma-coherent; -+}; -+ -+&i2c1 { -+ dma-coherent; -+}; -+ -+&i2c2 { -+ dma-coherent; -+}; -+ -+&i2c3 { -+ dma-coherent; -+}; -+ -+&duart0 { -+ dma-coherent; -+}; -+ -+&duart1 { -+ dma-coherent; -+}; -+ -+&duart2 { -+ dma-coherent; -+}; -+ -+&duart3 { -+ dma-coherent; -+}; -+ -+&gpio1 { -+ dma-coherent; -+}; -+ -+&gpio2 { -+ dma-coherent; -+}; -+ -+&gpio3 { -+ dma-coherent; -+}; -+ -+&gpio4 { -+ dma-coherent; -+}; -+ -+&lpuart0 { -+ dma-coherent; -+}; -+ -+&lpuart1 { -+ dma-coherent; -+}; -+ -+&lpuart2 { -+ dma-coherent; -+}; -+ -+&lpuart3 { -+ dma-coherent; -+}; -+ -+&lpuart4 { -+ dma-coherent; -+}; -+ -+&lpuart5 { -+ dma-coherent; -+}; -+ -+&ftm0 { -+ dma-coherent; -+}; -+ -+&wdog0 { -+ dma-coherent; -+}; -+ -+&edma0 { -+ dma-coherent; -+}; -+ -+&qdma { -+ dma-coherent; -+}; -+ -+&msi1 { -+ dma-coherent; -+}; -+ -+&msi2 { -+ dma-coherent; -+}; -+ -+&msi3 { -+ dma-coherent; -+}; -+ -+&fman0 { -+ dma-coherent; -+}; -+ -+&ptp_timer0 { -+ dma-coherent; -+}; -+ -+&fsldpaa { -+ dma-coherent; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts -new file mode 100644 -index 000000000..7beb9985a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts -@@ -0,0 +1,140 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright (C) 2014-2015, Freescale Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "fsl-ls1043a-rdb-sdk.dts" -+ -+&soc { -+ bp7: buffer-pool@7 { -+ compatible = "fsl,p4080-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,p4080-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,p4080-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus"; -+ dma-coherent; -+ -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; -+ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; -+ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; -+ }; -+ -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; -+ }; -+ -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; -+ }; -+ -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; -+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; -+ }; -+ -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x60 1 0x61 1>; -+ fsl,qman-frame-queues-tx = <0x80 1 0x81 1>; -+ }; -+ -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; -+ -+ }; -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* */ -+ fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+ -+ pcie@3400000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3500000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3600000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ /delete-node/ iommu@9000000; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* For legacy usdpaa based use-cases, update the size and -+ alignment parameters. e.g. to allocate 256 MB memory: -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ */ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x1000>; -+ alignment = <0 0x1000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -index 3516af472..3a669238a 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -@@ -50,6 +50,10 @@ rtc@68 { - compatible = "pericom,pt7c4338"; - reg = <0x68>; - }; -+ rtc@51 { -+ compatible = "nxp,pcf85263"; -+ reg = <0x51>; -+ }; - }; - - &ifc { -@@ -162,10 +166,12 @@ ethernet@f0000 { /* 10GEC1 */ - mdio@fc000 { - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; -+ rtl821x,aldps-disable; - }; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; -+ rtl821x,aldps-disable; - }; - - qsgmii_phy1: ethernet-phy@4 { -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -index b1b9544d8..29459c17f 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -299,6 +299,8 @@ soc: soc { - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; -+ dma-coherent; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1043a-clockgen"; -@@ -307,10 +309,78 @@ clockgen: clocking@1ee1000 { - clocks = <&sysclk>; - }; - -+ smmu: iommu@9000000 { -+ compatible = "arm,mmu-500"; -+ reg = <0 0x9000000 0 0x400000>; -+ dma-coherent; -+ stream-match-mask = <0x7f00>; -+ #global-interrupts = <2>; -+ #iommu-cells = <1>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ }; -+ - scfg: scfg@1570000 { - compatible = "fsl,ls1043a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x1570000 0x10000>; -+ -+ extirq: interrupt-controller@1ac { -+ compatible = "fsl,ls1043a-extirq"; -+ #interrupt-cells = <2>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x1ac 4>; -+ interrupt-map = -+ <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, -+ <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, -+ <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, -+ <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, -+ <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, -+ <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, -+ <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, -+ <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, -+ <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, -+ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, -+ <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, -+ <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-map-mask = <0xffffffff 0x0>; -+ }; - }; - - crypto: crypto@1700000 { -@@ -359,7 +429,7 @@ sec_jr3: jr@40000 { - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1043a-dcfg", "syscon"; -- reg = <0x0 0x1ee0000 0x0 0x10000>; -+ reg = <0x0 0x1ee0000 0x0 0x1000>; - big-endian; - }; - -@@ -493,7 +563,7 @@ dspi1: spi@2110000 { - }; - - i2c0: i2c@2180000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; -@@ -503,6 +573,7 @@ i2c0: i2c@2180000 { - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; -+ scl-gpios = <&gpio4 12 0>; - status = "disabled"; - }; - -@@ -726,6 +797,16 @@ lpuart5: serial@29a0000 { - status = "disabled"; - }; - -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>, -+ <0x0 0x1ee2140 0x0 0x4>; -+ reg-names = "ftm", "FlexTimer1"; -+ interrupts = <0 86 0x4>; -+ big-endian; -+ status = "okay"; -+ }; -+ - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; -@@ -751,47 +832,69 @@ edma0: edma@2c00000 { - <&clockgen 4 0>; - }; - -- usb0: usb3@2f00000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x2f00000 0x0 0x10000>; -- interrupts = <0 60 0x4>; -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- status = "disabled"; -- }; -+ aux_bus: aux_bus { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ compatible = "simple-bus"; -+ ranges; -+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; -+ -+ usb0: usb3@2f00000 { -+ compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = <0 60 0x4>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ configure-gfladj; -+ dma-coherent; -+ status = "disabled"; -+ }; - -- usb1: usb3@3000000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x3000000 0x0 0x10000>; -- interrupts = <0 61 0x4>; -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- status = "disabled"; -- }; -+ usb1: usb3@3000000 { -+ compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; -+ reg = <0x0 0x3000000 0x0 0x10000>; -+ interrupts = <0 61 0x4>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ configure-gfladj; -+ dma-coherent; -+ status = "disabled"; -+ }; - -- usb2: usb3@3100000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x3100000 0x0 0x10000>; -- interrupts = <0 63 0x4>; -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- status = "disabled"; -- }; -+ usb2: usb3@3100000 { -+ compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 63 0x4>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ configure-gfladj; -+ dma-coherent; -+ status = "disabled"; -+ }; - -- sata: sata@3200000 { -- compatible = "fsl,ls1043a-ahci"; -- reg = <0x0 0x3200000 0x0 0x10000>, -- <0x0 0x20140520 0x0 0x4>; -- reg-names = "ahci", "sata-ecc"; -- interrupts = <0 69 0x4>; -- clocks = <&clockgen 4 0>; -- dma-coherent; -+ sata: sata@3200000 { -+ compatible = "fsl,ls1043a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>, -+ <0x0 0x20140520 0x0 0x4>; -+ reg-names = "ahci", "sata-ecc"; -+ interrupts = <0 69 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; - }; - - msi1: msi-controller1@1571000 { -@@ -820,13 +923,13 @@ pcie1: pcie@3400000 { - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <0 118 0x4>, /* controller interrupt */ -- <0 117 0x4>; /* PME interrupt */ -- interrupt-names = "intr", "pme"; -+ interrupts = <0 117 0x4>, /* PME interrupt */ -+ <0 118 0x4>; /* aer interrupt */ -+ interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -- dma-coherent; -+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */ - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -838,6 +941,8 @@ pcie1: pcie@3400000 { - <0000 0 0 2 &gic 0 111 0x4>, - <0000 0 0 3 &gic 0 112 0x4>, - <0000 0 0 4 &gic 0 113 0x4>; -+ fsl,pcie-scfg = <&scfg 0>; -+ big-endian; - status = "disabled"; - }; - -@@ -846,13 +951,13 @@ pcie2: pcie@3500000 { - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <0 128 0x4>, -- <0 127 0x4>; -- interrupt-names = "intr", "pme"; -+ interrupts = <0 127 0x4>, -+ <0 128 0x4>; -+ interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -- dma-coherent; -+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */ - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -864,6 +969,8 @@ pcie2: pcie@3500000 { - <0000 0 0 2 &gic 0 121 0x4>, - <0000 0 0 3 &gic 0 122 0x4>, - <0000 0 0 4 &gic 0 123 0x4>; -+ fsl,pcie-scfg = <&scfg 1>; -+ big-endian; - status = "disabled"; - }; - -@@ -872,13 +979,13 @@ pcie3: pcie@3600000 { - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <0 162 0x4>, -- <0 161 0x4>; -- interrupt-names = "intr", "pme"; -+ interrupts = <0 161 0x4>, -+ <0 162 0x4>; -+ interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -- dma-coherent; -+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */ - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -890,6 +997,8 @@ pcie3: pcie@3600000 { - <0000 0 0 2 &gic 0 155 0x4>, - <0000 0 0 3 &gic 0 156 0x4>, - <0000 0 0 4 &gic 0 157 0x4>; -+ fsl,pcie-scfg = <&scfg 2>; -+ big-endian; - status = "disabled"; - }; - -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts -new file mode 100644 -index 000000000..c46a14a09 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts -@@ -0,0 +1,241 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2019 NXP. -+ * -+ */ -+ -+#include "fsl-ls1046a-frwy.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+/delete-property/ dma-coherent; -+ -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+ -+ pcie@3400000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3500000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3600000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ /delete-node/ iommu@9000000; -+}; -+ -+&fsldpaa { -+ ethernet@1 { -+ status = "disabled"; -+ }; -+ ethernet@2 { -+ status = "disabled"; -+ }; -+ ethernet@3 { -+ status = "disabled"; -+ }; -+ ethernet@6 { -+ status = "disabled"; -+ }; -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet7>; -+ dma-coherent; -+ }; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; -+ -+&clockgen { -+ dma-coherent; -+}; -+ -+&scfg { -+ dma-coherent; -+}; -+ -+&crypto { -+ dma-coherent; -+}; -+ -+&dcfg { -+ dma-coherent; -+}; -+ -+&ifc { -+ dma-coherent; -+}; -+ -+&qspi { -+ dma-coherent; -+}; -+ -+&esdhc { -+ dma-coherent; -+}; -+ -+&ddr { -+ dma-coherent; -+}; -+ -+&tmu { -+ dma-coherent; -+}; -+ -+&qman { -+ dma-coherent; -+}; -+ -+&bman { -+ dma-coherent; -+}; -+ -+&bportals { -+ dma-coherent; -+}; -+ -+&qportals { -+ dma-coherent; -+}; -+ -+&dspi { -+ dma-coherent; -+}; -+ -+&i2c0 { -+ dma-coherent; -+}; -+ -+&i2c1 { -+ dma-coherent; -+}; -+ -+&i2c2 { -+ dma-coherent; -+}; -+ -+&i2c3 { -+ dma-coherent; -+}; -+ -+&duart0 { -+ dma-coherent; -+}; -+ -+&duart1 { -+ dma-coherent; -+}; -+ -+&duart2 { -+ dma-coherent; -+}; -+ -+&duart3 { -+ dma-coherent; -+}; -+ -+&gpio0 { -+ dma-coherent; -+}; -+ -+&gpio1 { -+ dma-coherent; -+}; -+ -+&gpio2 { -+ dma-coherent; -+}; -+ -+&gpio3 { -+ dma-coherent; -+}; -+ -+&lpuart0 { -+ dma-coherent; -+}; -+ -+&lpuart1 { -+ dma-coherent; -+}; -+ -+&lpuart2 { -+ dma-coherent; -+}; -+ -+&lpuart3 { -+ dma-coherent; -+}; -+ -+&lpuart4 { -+ dma-coherent; -+}; -+ -+&lpuart5 { -+ dma-coherent; -+}; -+ -+&ftm0 { -+ dma-coherent; -+}; -+ -+&wdog0 { -+ dma-coherent; -+}; -+ -+&edma0 { -+ dma-coherent; -+}; -+ -+&sata { -+ dma-coherent; -+}; -+ -+&qdma { -+ dma-coherent; -+}; -+ -+&msi1 { -+ dma-coherent; -+}; -+ -+&msi2 { -+ dma-coherent; -+}; -+ -+&msi3 { -+ dma-coherent; -+}; -+ -+&fman0 { -+ dma-coherent; -+}; -+ -+&ptp_timer0 { -+ dma-coherent; -+}; -+ -+&fsldpaa { -+ dma-coherent; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts -new file mode 100644 -index 000000000..bd4f884eb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts -@@ -0,0 +1,117 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2019 NXP. -+ * -+ */ -+ -+#include "fsl-ls1046a-frwy-sdk.dts" -+ -+&soc { -+ bp7: buffer-pool@7 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; -+ dma-coherent; -+ -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; -+ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; -+ }; -+ -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; -+ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; -+ }; -+ -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; -+ }; -+ -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; -+ }; -+ -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* */ -+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+ -+ pcie@3400000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3500000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3600000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ /delete-node/ iommu@9000000; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ /* For legacy usdpaa based use-cases, update the size and -+ alignment parameters. e.g. to allocate 256 MB memory: -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ */ -+ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x1000>; -+ alignment = <0 0x1000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts -new file mode 100644 -index 000000000..644632275 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts -@@ -0,0 +1,264 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1046a-qds.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+/delete-property/ dma-coherent; -+ -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+ -+pcie@3400000 { -+ /delete-property/ iommu-map; -+}; -+ -+pcie@3500000 { -+ /delete-property/ iommu-map; -+}; -+ -+pcie@3600000 { -+ /delete-property/ iommu-map; -+}; -+ -+/delete-node/ iommu@9000000; -+}; -+ -+&fsldpaa { -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet7>; -+ dma-coherent; -+ }; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+ dma-coherent; -+}; -+ -+&clockgen { -+ dma-coherent; -+}; -+ -+&scfg { -+ dma-coherent; -+}; -+ -+&crypto { -+ dma-coherent; -+}; -+ -+&dcfg { -+ dma-coherent; -+}; -+ -+&ifc { -+ dma-coherent; -+}; -+ -+&qspi { -+ dma-coherent; -+}; -+ -+&esdhc { -+ dma-coherent; -+}; -+ -+&ddr { -+ dma-coherent; -+}; -+ -+&tmu { -+ dma-coherent; -+}; -+ -+&qman { -+ dma-coherent; -+}; -+ -+&bman { -+ dma-coherent; -+}; -+ -+&bportals { -+ dma-coherent; -+}; -+ -+&qportals { -+ dma-coherent; -+}; -+ -+&dspi { -+ dma-coherent; -+}; -+ -+&i2c0 { -+ dma-coherent; -+}; -+ -+&i2c1 { -+ dma-coherent; -+}; -+ -+&i2c2 { -+ dma-coherent; -+}; -+ -+&i2c3 { -+ dma-coherent; -+}; -+ -+&duart0 { -+ dma-coherent; -+}; -+ -+&duart1 { -+ dma-coherent; -+}; -+ -+&duart2 { -+ dma-coherent; -+}; -+ -+&duart3 { -+ dma-coherent; -+}; -+ -+&gpio0 { -+ dma-coherent; -+}; -+ -+&gpio1 { -+ dma-coherent; -+}; -+ -+&gpio2 { -+ dma-coherent; -+}; -+ -+&gpio3 { -+ dma-coherent; -+}; -+ -+&lpuart0 { -+ dma-coherent; -+}; -+ -+&lpuart1 { -+ dma-coherent; -+}; -+ -+&lpuart2 { -+ dma-coherent; -+}; -+ -+&lpuart3 { -+ dma-coherent; -+}; -+ -+&lpuart4 { -+ dma-coherent; -+}; -+ -+&lpuart5 { -+ dma-coherent; -+}; -+ -+&ftm0 { -+ dma-coherent; -+}; -+ -+&wdog0 { -+ dma-coherent; -+}; -+ -+&edma0 { -+ dma-coherent; -+}; -+ -+&sata { -+ dma-coherent; -+}; -+ -+&qdma { -+ dma-coherent; -+}; -+ -+&msi1 { -+ dma-coherent; -+}; -+ -+&msi2 { -+ dma-coherent; -+}; -+ -+&msi3 { -+ dma-coherent; -+}; -+ -+&ptp_timer0 { -+ dma-coherent; -+}; -+ -+&fsldpaa { -+ dma-coherent; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts -index eec62c63d..860ae33ed 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts -@@ -3,7 +3,7 @@ - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. -- * Copyright 2018 NXP -+ * Copyright 2018-2019 NXP - * - * Shaohui Xie - */ -@@ -25,6 +25,20 @@ aliases { - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; -+ -+ emi1-slot1 = &ls1046mdio_s1; -+ emi1-slot2 = &ls1046mdio_s2; -+ emi1-slot4 = &ls1046mdio_s4; -+ -+ sgmii-s1-p1 = &sgmii_phy_s1_p1; -+ sgmii-s1-p2 = &sgmii_phy_s1_p2; -+ sgmii-s1-p3 = &sgmii_phy_s1_p3; -+ sgmii-s1-p4 = &sgmii_phy_s1_p4; -+ sgmii-s4-p1 = &sgmii_phy_s4_p1; -+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1; -+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2; -+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3; -+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4; - }; - - chosen { -@@ -153,8 +167,9 @@ nand@1,0 { - }; - - fpga: board-control@2,0 { -- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; -+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus"; - reg = <0x2 0x0 0x0000100>; -+ ranges = <0 2 0 0x100>; - }; - }; - -@@ -169,7 +184,7 @@ qflash0: flash@0 { - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; -- spi-max-frequency = <20000000>; -+ spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; -@@ -177,3 +192,139 @@ qflash0: flash@0 { - }; - - #include "fsl-ls1046-post.dtsi" -+ -+&fman0 { -+ ethernet@e0000 { -+ phy-handle = <&qsgmii_phy_s2_p1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e2000 { -+ phy-handle = <&sgmii_phy_s4_p1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&sgmii_phy_s1_p3>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&sgmii_phy_s1_p4>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@f0000 { /* DTSEC9/10GEC1 */ -+ phy-handle = <&sgmii_phy_s1_p1>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ ethernet@f2000 { /* DTSEC10/10GEC2 */ -+ phy-handle = <&sgmii_phy_s1_p2>; -+ phy-connection-type = "xgmii"; -+ }; -+}; -+ -+&fpga { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ mdio-mux-emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&mdio0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1 */ -+ -+ /* On-board RGMII1 PHY */ -+ ls1046mdio0: mdio@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */ -+ reg = <0x1>; -+ rtl821x,aldps-disable; -+ }; -+ }; -+ -+ /* On-board RGMII2 PHY */ -+ ls1046mdio1: mdio@1 { -+ reg = <0x20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */ -+ reg = <0x2>; -+ rtl821x,aldps-disable; -+ }; -+ }; -+ -+ /* Slot 1 */ -+ ls1046mdio_s1: mdio@2 { -+ reg = <0x40>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s1_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ -+ sgmii_phy_s1_p2: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ -+ sgmii_phy_s1_p3: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ -+ sgmii_phy_s1_p4: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+ }; -+ -+ /* Slot 2 */ -+ ls1046mdio_s2: mdio@3 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ qsgmii_phy_s2_p1: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ qsgmii_phy_s2_p2: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ qsgmii_phy_s2_p3: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ qsgmii_phy_s2_p4: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+ }; -+ -+ /* Slot 4 */ -+ ls1046mdio_s4: mdio@5 { -+ reg = <0x80>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s4_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts -new file mode 100644 -index 000000000..de4d3b5bf ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts -@@ -0,0 +1,273 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1046a-rdb.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+/delete-property/ dma-coherent; -+ -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+ -+pcie@3400000 { -+ /delete-property/ iommu-map; -+}; -+ -+pcie@3500000 { -+ /delete-property/ iommu-map; -+}; -+ -+pcie@3600000 { -+ /delete-property/ iommu-map; -+}; -+ -+/delete-node/ iommu@9000000; -+}; -+ -+&fsldpaa { -+ ethernet@0 { -+ status = "disabled"; -+ }; -+ ethernet@1 { -+ status = "disabled"; -+ }; -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet7>; -+ dma-coherent; -+ }; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; -+ -+&clockgen { -+ dma-coherent; -+}; -+ -+&scfg { -+ dma-coherent; -+}; -+ -+&crypto { -+ dma-coherent; -+}; -+ -+&dcfg { -+ dma-coherent; -+}; -+ -+&ifc { -+ dma-coherent; -+}; -+ -+&qspi { -+ dma-coherent; -+}; -+ -+&esdhc { -+ dma-coherent; -+}; -+ -+&ddr { -+ dma-coherent; -+}; -+ -+&tmu { -+ dma-coherent; -+}; -+ -+&qman { -+ dma-coherent; -+}; -+ -+&bman { -+ dma-coherent; -+}; -+ -+&bportals { -+ dma-coherent; -+}; -+ -+&qportals { -+ dma-coherent; -+}; -+ -+&dspi { -+ dma-coherent; -+}; -+ -+&i2c0 { -+ dma-coherent; -+}; -+ -+&i2c1 { -+ dma-coherent; -+}; -+ -+&i2c2 { -+ dma-coherent; -+}; -+ -+&i2c3 { -+ dma-coherent; -+}; -+ -+&duart0 { -+ dma-coherent; -+}; -+ -+&duart1 { -+ dma-coherent; -+}; -+ -+&duart2 { -+ dma-coherent; -+}; -+ -+&duart3 { -+ dma-coherent; -+}; -+ -+&gpio0 { -+ dma-coherent; -+}; -+ -+&gpio1 { -+ dma-coherent; -+}; -+ -+&gpio2 { -+ dma-coherent; -+}; -+ -+&gpio3 { -+ dma-coherent; -+}; -+ -+&lpuart0 { -+ dma-coherent; -+}; -+ -+&lpuart1 { -+ dma-coherent; -+}; -+ -+&lpuart2 { -+ dma-coherent; -+}; -+ -+&lpuart3 { -+ dma-coherent; -+}; -+ -+&lpuart4 { -+ dma-coherent; -+}; -+ -+&lpuart5 { -+ dma-coherent; -+}; -+ -+&ftm0 { -+ dma-coherent; -+}; -+ -+&wdog0 { -+ dma-coherent; -+}; -+ -+&edma0 { -+ dma-coherent; -+}; -+ -+&sata { -+ dma-coherent; -+}; -+ -+&qdma { -+ dma-coherent; -+}; -+ -+&msi1 { -+ dma-coherent; -+}; -+ -+&msi2 { -+ dma-coherent; -+}; -+ -+&msi3 { -+ dma-coherent; -+}; -+ -+&fman0 { -+ dma-coherent; -+}; -+ -+&ptp_timer0 { -+ dma-coherent; -+}; -+ -+&fsldpaa { -+ dma-coherent; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts -new file mode 100644 -index 000000000..7f29a2b84 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts -@@ -0,0 +1,108 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright 2019-2021 NXP -+ * Device Tree file to support Shared Mac interface for 1046A family SoC. -+ * This file is for MAC9 as shared and rest of the interfaces are assigned to Linux Kernel only -+ */ -+ -+#include "fsl-ls1046a-rdb-sdk.dts" -+ -+&bportals { -+ bman-bpids@0 { -+ compatible = "fsl,bpid-range"; -+ fsl,bpid-range = <16 48>; -+ }; -+}; -+ -+&soc { -+ chosen { -+ name = "chosen"; -+ dpaa-extended-args { -+ fman0-extd-args { -+ -+ cell-index = <0>; -+ compatible = "fsl,fman-extended-args"; -+ dma-aid-mode = "port"; -+ -+ fman0_rxt0-extd-args { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-10g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ }; -+ }; -+ }; -+ -+ bp7: buffer-pool@7 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; -+ dma-coherent; -+ -+ ethernet@8 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1 0x8a 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1 0x84 1>; -+ }; -+ -+ -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* */ -+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* For legacy usdpaa based use-cases, update the size and -+ alignment parameters. e.g. to allocate 256 MB memory: -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ */ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x1000>; -+ alignment = <0 0x1000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts -new file mode 100644 -index 000000000..bfb48d038 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts -@@ -0,0 +1,142 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright 2019-2021 NXP -+ * Device Tree file to support Shared Mac interface for 1046A family SoC. -+ * This file is for MAC10 as shared and rest of the interfaces are for Userspace-DPDK -+ */ -+ -+#include "fsl-ls1046a-rdb-sdk.dts" -+ -+&bportals { -+ bman-bpids@0 { -+ compatible = "fsl,bpid-range"; -+ fsl,bpid-range = <16 48>; -+ }; -+}; -+ -+&soc { -+ chosen { -+ name = "chosen"; -+ dpaa-extended-args { -+ fman0-extd-args { -+ -+ cell-index = <0>; -+ compatible = "fsl,fman-extended-args"; -+ dma-aid-mode = "port"; -+ -+ fman0_rxt1-extd-args { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-10g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ }; -+ }; -+ }; -+ -+ bp7: buffer-pool@7 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; -+ dma-coherent; -+ -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; -+ }; -+ -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; -+ }; -+ -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; -+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; -+ }; -+ -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; -+ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; -+ }; -+ -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; -+ }; -+ -+ ethernet@9 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1 0x8b 1>; -+ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1 0x85 1>; -+ }; -+ -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* */ -+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* For legacy usdpaa based use-cases, update the size and -+ alignment parameters. e.g. to allocate 256 MB memory: -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ */ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x1000>; -+ alignment = <0 0x1000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts -new file mode 100644 -index 000000000..cf09f77c7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts -@@ -0,0 +1,189 @@ -+/* -+ * Device Tree file to support Shared Mac interface for 1046A family SoC. -+ * -+ * Copyright 2019-2021 NXP -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "fsl-ls1046a-rdb-sdk.dts" -+ -+&bportals { -+ bman-bpids@0 { -+ compatible = "fsl,bpid-range"; -+ fsl,bpid-range = <16 48>; -+ }; -+}; -+ -+&soc { -+ chosen { -+ name = "chosen"; -+ dpaa-extended-args { -+ fman0-extd-args { -+ -+ cell-index = <0>; -+ compatible = "fsl,fman-extended-args"; -+ dma-aid-mode = "port"; -+ -+ fman0_rx2-extd-args { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-1g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rx3-extd-args { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-1g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rx4-extd-args { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-1g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rx5-extd-args { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-1g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rx6-extd-args { -+ cell-index = <6>; -+ compatible = "fsl,fman-port-1g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rx7-extd-args { -+ cell-index = <7>; -+ compatible = "fsl,fman-port-1g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rxt0-extd-args { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-10g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ fman0_rxt1-extd-args { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-10g-rx-extended-args"; -+ /* Define Virtual storage profile */ -+ /* */ -+ vsp-window = <2 0>; -+ }; -+ }; -+ }; -+ }; -+ -+ bp7: buffer-pool@7 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; -+ dma-coherent; -+ -+ ethernet@2 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1 0x86 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1 0x80 1>; -+ }; -+ -+ ethernet@3 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1 0x87 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1 0x81 1>; -+ }; -+ -+ ethernet@4 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1 0x88 1>; -+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1 0x82 1>; -+ }; -+ -+ ethernet@5 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1 0x89 1>; -+ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1 0x83 1>; -+ }; -+ -+ ethernet@8 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1 0x8a 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1 0x84 1>; -+ }; -+ -+ ethernet@9 { -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1 0x8b 1>; -+ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1 0x85 1>; -+ }; -+ -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* */ -+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* For legacy usdpaa based use-cases, update the size and -+ alignment parameters. e.g. to allocate 256 MB memory: -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ */ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x1000>; -+ alignment = <0 0x1000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts -new file mode 100644 -index 000000000..343c9d81a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts -@@ -0,0 +1,133 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "fsl-ls1046a-rdb-sdk.dts" -+ -+&soc { -+ bp7: buffer-pool@7 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ dma-coherent; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; -+ dma-coherent; -+ -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; -+ }; -+ -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; -+ }; -+ -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; -+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; -+ }; -+ -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; -+ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; -+ }; -+ -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; -+ }; -+ -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>; -+ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>; -+ }; -+ -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* */ -+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+ -+ pcie@3400000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3500000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ pcie@3600000 { -+ /delete-property/ iommu-map; -+ }; -+ -+ /delete-node/ iommu@9000000; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* For legacy usdpaa based use-cases, update the size and -+ alignment parameters. e.g. to allocate 256 MB memory: -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ */ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x1000>; -+ alignment = <0 0x1000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -index 07139e356..898117357 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -@@ -3,6 +3,7 @@ - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2019-2020 NXP - * - * Mingkai Hu - */ -@@ -69,6 +70,8 @@ &i2c3 { - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; -+ /* IRQ_RTC_B -> IRQ05, active low */ -+ interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; - }; - }; - -@@ -101,7 +104,7 @@ s25fs512s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; -- spi-rx-bus-width = <4>; -+ spi-rx-bus-width = <1>; - spi-tx-bus-width = <1>; - reg = <0>; - }; -@@ -111,7 +114,7 @@ s25fs512s1: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; -- spi-rx-bus-width = <4>; -+ spi-rx-bus-width = <1>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -@@ -157,10 +160,12 @@ ethernet@f2000 { /* 10GEC2 */ - mdio@fc000 { - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; -+ rtl821x,aldps-disable; - }; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; -+ rtl821x,aldps-disable; - }; - - sgmii_phy1: ethernet-phy@3 { -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -index acf2ae2e1..45b8fbaed 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -@@ -271,6 +271,8 @@ soc: soc { - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; -+ dma-coherent; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; -@@ -310,10 +312,78 @@ esdhc: esdhc@1560000 { - bus-width = <4>; - }; - -+ smmu: iommu@9000000 { -+ compatible = "arm,mmu-500"; -+ reg = <0 0x9000000 0 0x400000>; -+ dma-coherent; -+ stream-match-mask = <0x7f00>; -+ #global-interrupts = <2>; -+ #iommu-cells = <1>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ }; -+ - scfg: scfg@1570000 { - compatible = "fsl,ls1046a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x1570000 0x10000>; -+ -+ extirq: interrupt-controller@1ac { -+ compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; -+ #interrupt-cells = <2>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x1ac 4>; -+ interrupt-map = -+ <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, -+ <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, -+ <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, -+ <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, -+ <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, -+ <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, -+ <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, -+ <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, -+ <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, -+ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, -+ <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, -+ <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-map-mask = <0xffffffff 0x0>; -+ }; - }; - - crypto: crypto@1700000 { -@@ -458,7 +528,7 @@ dspi: spi@2100000 { - }; - - i2c0: i2c@2180000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; -@@ -467,6 +537,7 @@ i2c0: i2c@2180000 { - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; -+ scl-gpios = <&gpio3 12 0>; - status = "disabled"; - }; - -@@ -491,12 +562,13 @@ i2c2: i2c@21a0000 { - }; - - i2c3: i2c@21b0000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21b0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; -+ scl-gpios = <&gpio3 12 0>; - status = "disabled"; - }; - -@@ -626,6 +698,15 @@ lpuart5: serial@29a0000 { - status = "disabled"; - }; - -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>, -+ <0x0 0x1ee2140 0x0 0x4>; -+ reg-names = "ftm", "FlexTimer1"; -+ interrupts = ; -+ big-endian; -+ }; -+ - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; -@@ -650,43 +731,63 @@ edma0: edma@2c00000 { - <&clockgen 4 1>; - }; - -- usb0: usb@2f00000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x2f00000 0x0 0x10000>; -- interrupts = ; -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- }; -- -- usb1: usb@3000000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x3000000 0x0 0x10000>; -- interrupts = ; -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- }; -- -- usb2: usb@3100000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x3100000 0x0 0x10000>; -- interrupts = ; -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- }; -- -- sata: sata@3200000 { -- compatible = "fsl,ls1046a-ahci"; -- reg = <0x0 0x3200000 0x0 0x10000>, -- <0x0 0x20140520 0x0 0x4>; -- reg-names = "ahci", "sata-ecc"; -- interrupts = ; -- clocks = <&clockgen 4 1>; -+ aux_bus: aux_bus { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ compatible = "simple-bus"; -+ ranges; -+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; -+ -+ usb0: usb@2f00000 { -+ compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = ; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ snps,host-vbus-glitches; -+ dma-coherent; -+ }; -+ -+ usb1: usb@3000000 { -+ compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; -+ reg = <0x0 0x3000000 0x0 0x10000>; -+ interrupts = ; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ snps,host-vbus-glitches; -+ dma-coherent; -+ }; -+ -+ usb2: usb@3100000 { -+ compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = ; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ snps,host-vbus-glitches; -+ dma-coherent; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1046a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>, -+ <0x0 0x20140520 0x0 0x4>; -+ reg-names = "ahci", "sata-ecc"; -+ interrupts = ; -+ clocks = <&clockgen 4 1>; -+ }; - }; - - msi1: msi-controller@1580000 { -@@ -731,6 +832,7 @@ pcie1: pcie@3400000 { - #size-cells = <2>; - device_type = "pci"; - dma-coherent; -+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */ - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -742,6 +844,7 @@ pcie1: pcie@3400000 { - <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; - status = "disabled"; - }; - -@@ -750,8 +853,11 @@ pcie_ep1: pcie_ep@3400000 { - reg = <0x00 0x03400000 0x0 0x00100000 - 0x40 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; - num-ib-windows = <6>; - num-ob-windows = <8>; -+ big-endian; - status = "disabled"; - }; - -@@ -767,6 +873,7 @@ pcie2: pcie@3500000 { - #size-cells = <2>; - device_type = "pci"; - dma-coherent; -+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */ - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -778,6 +885,7 @@ pcie2: pcie@3500000 { - <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; - status = "disabled"; - }; - -@@ -786,8 +894,11 @@ pcie_ep2: pcie_ep@3500000 { - reg = <0x00 0x03500000 0x0 0x00100000 - 0x48 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; - num-ib-windows = <6>; - num-ob-windows = <8>; -+ big-endian; - status = "disabled"; - }; - -@@ -803,6 +914,7 @@ pcie3: pcie@3600000 { - #size-cells = <2>; - device_type = "pci"; - dma-coherent; -+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */ - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -814,6 +926,7 @@ pcie3: pcie@3600000 { - <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; - status = "disabled"; - }; - -@@ -822,8 +935,11 @@ pcie_ep3: pcie_ep@3600000 { - reg = <0x00 0x03600000 0x0 0x00100000 - 0x50 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; - num-ib-windows = <6>; - num-ob-windows = <8>; -+ big-endian; - status = "disabled"; - }; - -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts -index 41d8b15f2..5b2699fe4 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts -@@ -131,6 +131,30 @@ fpga: board-control@3,0 { - }; - }; - -+&qspi { -+ status = "okay"; -+ fsl,qspi-has-second-chip; -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ }; -+ -+ qflash1: s25fs512s@1 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ }; -+}; -+ - &duart0 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -index 5633e59fe..5a4a7ff6a 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -@@ -2,7 +2,7 @@ - /* - * Device Tree file for NXP LS1088A RDB Board. - * -- * Copyright 2017 NXP -+ * Copyright 2017-2020 NXP - * - * Harninder Rai - * -@@ -17,6 +17,113 @@ / { - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; - }; - -+&dpmac2 { -+ phy-handle = <&mdio2_aquantia_phy>; -+ phy-connection-type = "10gbase-r"; -+ pcs-handle = <&pcs2>; -+}; -+ -+&dpmac3 { -+ phy-handle = <&mdio1_phy5>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs3_0>; -+}; -+ -+&dpmac4 { -+ phy-handle = <&mdio1_phy6>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs3_1>; -+}; -+ -+&dpmac5 { -+ phy-handle = <&mdio1_phy7>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs3_2>; -+}; -+ -+&dpmac6 { -+ phy-handle = <&mdio1_phy8>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs3_3>; -+}; -+ -+&dpmac7 { -+ phy-handle = <&mdio1_phy1>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs7_0>; -+}; -+ -+&dpmac8 { -+ phy-handle = <&mdio1_phy2>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs7_1>; -+}; -+ -+&dpmac9 { -+ phy-handle = <&mdio1_phy3>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs7_2>; -+}; -+ -+&dpmac10 { -+ phy-handle = <&mdio1_phy4>; -+ phy-connection-type = "qsgmii"; -+ managed = "in-band-status"; -+ pcs-handle = <&pcs7_3>; -+}; -+ -+&emdio1 { -+ status = "okay"; -+ -+ mdio1_phy5: ethernet-phy@c { -+ reg = <0xc>; -+ }; -+ -+ mdio1_phy6: ethernet-phy@d { -+ reg = <0xd>; -+ }; -+ -+ mdio1_phy7: ethernet-phy@e { -+ reg = <0xe>; -+ }; -+ -+ mdio1_phy8: ethernet-phy@f { -+ reg = <0xf>; -+ }; -+ -+ mdio1_phy1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ -+ mdio1_phy2: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ -+ mdio1_phy3: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ -+ mdio1_phy4: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+}; -+ -+&emdio2 { -+ status = "okay"; -+ -+ mdio2_aquantia_phy: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -51,8 +158,8 @@ temp-sensor@4c { - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; -- /* IRQ10_B */ -- interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; -+ /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU), active low */ -+ interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; -@@ -74,6 +181,31 @@ fpga: board-control@2,0 { - }; - }; - -+&qspi { -+ status = "okay"; -+ -+ s25fs512s0: flash@0 { -+ compatible = "jedec,spi-nor"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; -+ }; -+ -+ s25fs512s1: flash@1 { -+ compatible = "jedec,spi-nor"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; -+ }; -+ -+}; -+ - &duart0 { - status = "okay"; - }; -@@ -87,6 +219,18 @@ &esdhc { - status = "okay"; - }; - -+&pcs_mdio2 { -+ status = "okay"; -+}; -+ -+&pcs_mdio3 { -+ status = "okay"; -+}; -+ -+&pcs_mdio7 { -+ status = "okay"; -+}; -+ - &qspi { - status = "okay"; - -@@ -123,3 +267,4 @@ &usb1 { - dr_mode = "otg"; - status = "okay"; - }; -+ -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -index 692d8f4a2..c79b37b46 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -@@ -188,6 +188,11 @@ timer { - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ - }; - -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = ; -+ }; -+ - psci { - compatible = "arm,psci-0.2"; - method = "smc"; -@@ -200,6 +205,19 @@ sysclk: sysclk { - clock-output-names = "sysclk"; - }; - -+ rstcr: syscon@1e60000 { -+ compatible = "fsl,ls1088a-rstcr", "syscon"; -+ reg = <0x0 0x1e60000 0x0 0x4>; -+ }; -+ -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&rstcr>; -+ offset = <0x0>; -+ mask = <0x02>; -+ }; -+ -+ - soc { - compatible = "simple-bus"; - #address-cells = <2>; -@@ -220,6 +238,37 @@ dcfg: dcfg@1e00000 { - little-endian; - }; - -+ isc: syscon@1f70000 { -+ compatible = "fsl,ls1088a-isc", "syscon"; -+ reg = <0x0 0x1f70000 0x0 0x10000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x1f70000 0x10000>; -+ -+ extirq: interrupt-controller@14 { -+ compatible = "fsl,ls1088a-extirq"; -+ #interrupt-cells = <2>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x14 4>; -+ interrupt-map = -+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, -+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, -+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, -+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, -+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, -+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, -+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, -+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, -+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, -+ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, -+ <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, -+ <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-map-mask = <0xffffffff 0x0>; -+ }; -+ }; -+ - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; -@@ -354,13 +403,20 @@ ifc: ifc@2240000 { - status = "disabled"; - }; - -+ ftm0: ftm0@2800000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x2800000 0x0 0x10000>; -+ interrupts = <0 44 4>; -+ }; -+ - i2c0: i2c@2000000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; -+ scl-gpios = <&gpio3 30 0>; - status = "disabled"; - }; - -@@ -421,23 +477,28 @@ esdhc: esdhc@2140000 { - }; - - usb0: usb3@3100000 { -- compatible = "snps,dwc3"; -+ compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ dma-coherent; - status = "disabled"; - }; - - usb1: usb3@3110000 { -- compatible = "snps,dwc3"; -+ compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ dma-coherent; - status = "disabled"; - }; - -@@ -517,6 +578,20 @@ pcie1: pcie@3400000 { - status = "disabled"; - }; - -+ pcie_ep1: pcie_ep@3400000 { -+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; -+ reg = <0x00 0x03400000 0x0 0x00100000 -+ 0x20 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; -+ num-ib-windows = <24>; -+ num-ob-windows = <128>; -+ max-functions = /bits/ 8 <2>; -+ big-endian; -+ status = "disabled"; -+ }; -+ - pcie2: pcie@3500000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -@@ -543,6 +618,19 @@ pcie2: pcie@3500000 { - status = "disabled"; - }; - -+ pcie_ep2: pcie_ep@3500000 { -+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; -+ reg = <0x00 0x03500000 0x0 0x00100000 -+ 0x28 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; -+ num-ib-windows = <6>; -+ num-ob-windows = <8>; -+ big-endian; -+ status = "disabled"; -+ }; -+ - pcie3: pcie@3600000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -@@ -569,6 +657,18 @@ pcie3: pcie@3600000 { - status = "disabled"; - }; - -+ pcie_ep3: pcie_ep@3600000 { -+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; -+ reg = <0x00 0x03600000 0x0 0x00100000 -+ 0x30 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ interrupts = ; /* PME interrupt */ -+ interrupt-names = "pme"; -+ num-ib-windows = <6>; -+ num-ob-windows = <8>; -+ status = "disabled"; -+ }; -+ - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; -@@ -672,6 +772,87 @@ ptp-timer@8b95000 { - fsl,extts-fifo; - }; - -+ emdio1: mdio@8b96000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8b96000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ emdio2: mdio@8b97000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8b97000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcs_mdio2: mdio@8c0b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs2: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio3: mdio@8c0f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs3_0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ pcs3_1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ pcs3_2: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ pcs3_3: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ }; -+ -+ pcs_mdio7: mdio@8c1f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs7_0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ pcs7_1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ pcs7_2: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ pcs7_3: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ }; -+ - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; -@@ -749,52 +930,52 @@ dpmacs { - #address-cells = <1>; - #size-cells = <0>; - -- dpmac1: dpmac@1 { -+ dpmac1: ethernet@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - }; - -- dpmac2: dpmac@2 { -+ dpmac2: ethernet@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <2>; - }; - -- dpmac3: dpmac@3 { -+ dpmac3: ethernet@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <3>; - }; - -- dpmac4: dpmac@4 { -+ dpmac4: ethernet@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <4>; - }; - -- dpmac5: dpmac@5 { -+ dpmac5: ethernet@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <5>; - }; - -- dpmac6: dpmac@6 { -+ dpmac6: ethernet@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <6>; - }; - -- dpmac7: dpmac@7 { -+ dpmac7: ethernet@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <7>; - }; - -- dpmac8: dpmac@8 { -+ dpmac8: ethernet@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <8>; - }; - -- dpmac9: dpmac@9 { -+ dpmac9: ethernet@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <9>; - }; - -- dpmac10: dpmac@a { -+ dpmac10: ethernet@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts -index f6c3ee78a..20157fd69 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts -@@ -23,3 +23,65 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - }; -+ -+&ifc { -+ boardctrl: board-control@3,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; -+ reg = <3 0 0x300>; /* TODO check address */ -+ ranges = <0 3 0 0x300>; -+ -+ mdio_mux_emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&emdio1>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1_MDIO */ -+ -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ /* Child MDIO buses, one for each riser card: -+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. -+ * VSC8234 PHYs on the riser cards. -+ */ -+ -+ mdio_mux3: mdio@60 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio0_phy12: mdio_phy0@1c { -+ reg = <0x1c>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy13: mdio_phy1@1d { -+ reg = <0x1d>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy14: mdio_phy2@1e { -+ reg = <0x1e>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy15: mdio_phy3@1f { -+ reg = <0x1f>; -+ phy-connection-type = "sgmii"; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ -+&dpmac9 { -+ phy-handle = <&mdio0_phy12>; -+}; -+&dpmac10 { -+ phy-handle = <&mdio0_phy13>; -+}; -+&dpmac11 { -+ phy-handle = <&mdio0_phy14>; -+}; -+&dpmac12 { -+ phy-handle = <&mdio0_phy15>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts -index 448943560..2ed99e98f 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts -@@ -23,3 +23,83 @@ chosen { - stdout-path = "serial1:115200n8"; - }; - }; -+ -+&emdio1 { -+ status = "disabled"; -+ /* CS4340 PHYs */ -+ mdio1_phy1: emdio1_phy@1 { -+ reg = <0x10>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy2: emdio1_phy@2 { -+ reg = <0x11>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy3: emdio1_phy@3 { -+ reg = <0x12>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy4: emdio1_phy@4 { -+ reg = <0x13>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+&emdio2 { -+ /* AQR405 PHYs */ -+ mdio2_phy1: emdio2_phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 1 0x4>; /* Level high type */ -+ reg = <0x0>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy2: emdio2_phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 2 0x4>; /* Level high type */ -+ reg = <0x1>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy3: emdio2_phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 4 0x4>; /* Level high type */ -+ reg = <0x2>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy4: emdio2_phy@4 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 5 0x4>; /* Level high type */ -+ reg = <0x3>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under the assumption of -+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. -+ */ -+/* Leave Cortina nodes commented out until driver is integrated -+ *&dpmac1 { -+ * phy-handle = <&mdio1_phy1>; -+ *}; -+ *&dpmac2 { -+ * phy-handle = <&mdio1_phy2>; -+ *}; -+ *&dpmac3 { -+ * phy-handle = <&mdio1_phy3>; -+ *}; -+ *&dpmac4 { -+ * phy-handle = <&mdio1_phy4>; -+ *}; -+ */ -+ -+&dpmac5 { -+ phy-handle = <&mdio2_phy1>; -+}; -+&dpmac6 { -+ phy-handle = <&mdio2_phy2>; -+}; -+&dpmac7 { -+ phy-handle = <&mdio2_phy3>; -+}; -+&dpmac8 { -+ phy-handle = <&mdio2_phy4>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -index f9c1d30cf..2b05c7e39 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -@@ -118,6 +118,18 @@ CPU_PW20: cpu-pw20 { - }; - }; - -+&timer { -+ fsl,erratum-a008585; -+}; -+ -+&usb0 { -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+}; -+ -+&usb1 { -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+}; -+ - &pcie1 { - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts -new file mode 100644 -index 000000000..0e240a97f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts -@@ -0,0 +1,127 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for NXP LS2081A RDB Board. -+ * -+ * Copyright 2017 NXP -+ * -+ * Priyanka Jain -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls2088a.dtsi" -+ -+/ { -+ model = "NXP Layerscape 2081A RDB Board"; -+ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; -+ -+ aliases { -+ serial0 = &serial0; -+ serial1 = &serial1; -+ }; -+ -+ chosen { -+ stdout-path = "serial1:115200n8"; -+ }; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "disabled"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@75 { -+ compatible = "nxp,pca9547"; -+ reg = <0x75>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x01>; -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x02>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <500>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ adt7481@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&dspi { -+ status = "okay"; -+ dflash0: n25q512a@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <0>; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ fsl,qspi-has-second-chip; -+ flash0: s25fs512s@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spansion,m25p80"; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ flash1: s25fs512s@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ compatible = "spansion,m25p80"; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts -index 7c17b1bd4..01a377552 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts -@@ -22,3 +22,65 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - }; -+ -+&ifc { -+ boardctrl: board-control@3,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; -+ reg = <3 0 0x300>; /* TODO check address */ -+ ranges = <0 3 0 0x300>; -+ -+ mdio_mux_emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&emdio1>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1_MDIO */ -+ -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ /* Child MDIO buses, one for each riser card: -+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. -+ * VSC8234 PHYs on the riser cards. -+ */ -+ -+ mdio_mux3: mdio@60 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio0_phy12: mdio_phy0@1c { -+ reg = <0x1c>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy13: mdio_phy1@1d { -+ reg = <0x1d>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy14: mdio_phy2@1e { -+ reg = <0x1e>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy15: mdio_phy3@1f { -+ reg = <0x1f>; -+ phy-connection-type = "sgmii"; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ -+&dpmac9 { -+ phy-handle = <&mdio0_phy12>; -+}; -+&dpmac10 { -+ phy-handle = <&mdio0_phy13>; -+}; -+&dpmac11 { -+ phy-handle = <&mdio0_phy14>; -+}; -+&dpmac12 { -+ phy-handle = <&mdio0_phy15>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts -index f6b4d75a2..60563917b 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts -@@ -22,3 +22,123 @@ chosen { - stdout-path = "serial1:115200n8"; - }; - }; -+ -+&dpmac1 { -+ phy-handle = <&mdio1_phy1>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac2 { -+ phy-handle = <&mdio1_phy2>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac3 { -+ phy-handle = <&mdio1_phy3>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac4 { -+ phy-handle = <&mdio1_phy4>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac5 { -+ phy-handle = <&mdio2_phy1>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac6 { -+ phy-handle = <&mdio2_phy2>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac7 { -+ phy-handle = <&mdio2_phy3>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&dpmac8 { -+ phy-handle = <&mdio2_phy4>; -+ phy-connection-type = "10gbase-r"; -+}; -+ -+&emdio1 { -+ status = "okay"; -+ -+ mdio1_phy1: ethernet-phy@10 { -+ compatible = "ethernet-phy-id13e5.1002"; -+ reg = <0x10>; -+ }; -+ -+ mdio1_phy2: ethernet-phy@11 { -+ compatible = "ethernet-phy-id13e5.1002"; -+ reg = <0x11>; -+ }; -+ -+ mdio1_phy3: ethernet-phy@12 { -+ compatible = "ethernet-phy-id13e5.1002"; -+ reg = <0x12>; -+ }; -+ -+ mdio1_phy4: ethernet-phy@13 { -+ compatible = "ethernet-phy-id13e5.1002"; -+ reg = <0x13>; -+ }; -+}; -+ -+&emdio2 { -+ status = "okay"; -+ -+ mdio2_phy1: ethernet-phy@0 { -+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ }; -+ -+ mdio2_phy2: ethernet-phy@1 { -+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; -+ reg = <0x1>; -+ }; -+ -+ mdio2_phy3: ethernet-phy@2 { -+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; -+ reg = <0x2>; -+ }; -+ -+ mdio2_phy4: ethernet-phy@3 { -+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; -+ reg = <0x3>; -+ }; -+}; -+ -+&pcs_mdio1 { -+ status = "okay"; -+}; -+ -+&pcs_mdio2 { -+ status = "okay"; -+}; -+ -+&pcs_mdio3 { -+ status = "okay"; -+}; -+ -+&pcs_mdio4 { -+ status = "okay"; -+}; -+ -+&pcs_mdio5 { -+ status = "okay"; -+}; -+ -+&pcs_mdio6 { -+ status = "okay"; -+}; -+ -+&pcs_mdio7 { -+ status = "okay"; -+}; -+ -+&pcs_mdio8 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi -index 10d2fe091..2d05e840f 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi -@@ -129,6 +129,7 @@ dflash2: en25s64@2 { - - &qspi { - status = "okay"; -+ fsl,qspi-has-second-chip; - flash0: s25fl256s1@0 { - #address-cells = <1>; - #size-cells = <1>; -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi -index d0d670227..e8b048a58 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi -@@ -3,7 +3,7 @@ - * Device Tree file for Freescale LS2080A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. -- * Copyright 2017 NXP -+ * Copyright 2017-2020 NXP - * - * Abhimanyu Saini - * -@@ -49,6 +49,7 @@ pca9547@75 { - reg = <0x75>; - #address-cells = <1>; - #size-cells = <0>; -+ idle-state = <0>; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; -@@ -56,6 +57,8 @@ i2c@1 { - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; -+ /* IRQ_RTC_B -> IRQ06, active low */ -+ interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>; - }; - }; - -diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi -index 4d34d82b8..4f2815b16 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi -@@ -3,7 +3,7 @@ - * Device Tree Include file for Freescale Layerscape-2080A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. -- * Copyright 2017 NXP -+ * Copyright 2017-2020 NXP - * - * Abhimanyu Saini - * -@@ -238,13 +238,12 @@ map0 { - }; - }; - -- timer { -+ timer: timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ - <1 14 4>, /* Physical Non-Secure PPI, active-low */ - <1 11 4>, /* Virtual PPI, active-low */ - <1 10 4>; /* Hypervisor PPI, active-low */ -- fsl,erratum-a008585; - }; - - pmu { -@@ -277,6 +276,37 @@ dcfg: dcfg@1e00000 { - little-endian; - }; - -+ isc: syscon@1f70000 { -+ compatible = "fsl,ls2080a-isc", "syscon"; -+ reg = <0x0 0x1f70000 0x0 0x10000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x1f70000 0x10000>; -+ -+ extirq: interrupt-controller@14 { -+ compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq"; -+ #interrupt-cells = <2>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x14 4>; -+ interrupt-map = -+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, -+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, -+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, -+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, -+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, -+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, -+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, -+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, -+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, -+ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, -+ <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, -+ <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-map-mask = <0xffffffff 0x0>; -+ }; -+ }; -+ - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; -@@ -353,56 +383,56 @@ serial3: serial@21d0600 { - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc100000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc110000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster3_core0_watchdog: wdt@c200000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc200000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster3_core1_watchdog: wdt@c210000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc210000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster4_core0_watchdog: wdt@c300000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc300000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster4_core1_watchdog: wdt@c310000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc310000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clocks = <&clockgen 4 31>, <&clockgen 4 31>; - clock-names = "wdog_clk", "apb_pclk"; - }; - -@@ -458,6 +488,232 @@ ptp-timer@8b95000 { - fsl,extts-fifo; - }; - -+ emdio1: mdio@8b96000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8b96000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ emdio2: mdio@8b97000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8b97000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcs_mdio1: mdio@8c07000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c07000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs1: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio2: mdio@8c0b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs2: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio3: mdio@8c0f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs3: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio4: mdio@8c13000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c13000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs4: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio5: mdio@8c17000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c17000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs5: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio6: mdio@8c1b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs6: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio7: mdio@8c1f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs7: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio8: mdio@8c23000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c23000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs8: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio9: mdio@8c27000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c27000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs9: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio10: mdio@8c2b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c2b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs10: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio11: mdio@8c2f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c2f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs11: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio12: mdio@8c33000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c33000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs12: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio13: mdio@8c37000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c37000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs13: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio14: mdio@8c3b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c3b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs14: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio15: mdio@8c3f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c3f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs15: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio16: mdio@8c43000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c43000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs16: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -@@ -482,84 +738,100 @@ dpmacs { - #address-cells = <1>; - #size-cells = <0>; - -- dpmac1: dpmac@1 { -+ dpmac1: ethernet@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; -+ pcs-handle = <&pcs1>; - }; - -- dpmac2: dpmac@2 { -+ dpmac2: ethernet@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; -+ pcs-handle = <&pcs2>; - }; - -- dpmac3: dpmac@3 { -+ dpmac3: ethernet@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; -+ pcs-handle = <&pcs3>; - }; - -- dpmac4: dpmac@4 { -+ dpmac4: ethernet@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; -+ pcs-handle = <&pcs4>; - }; - -- dpmac5: dpmac@5 { -+ dpmac5: ethernet@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; -+ pcs-handle = <&pcs5>; - }; - -- dpmac6: dpmac@6 { -+ dpmac6: ethernet@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; -+ pcs-handle = <&pcs6>; - }; - -- dpmac7: dpmac@7 { -+ dpmac7: ethernet@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; -+ pcs-handle = <&pcs7>; - }; - -- dpmac8: dpmac@8 { -+ dpmac8: ethernet@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; -+ pcs-handle = <&pcs8>; - }; - -- dpmac9: dpmac@9 { -+ dpmac9: ethernet@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; -+ pcs-handle = <&pcs9>; - }; - -- dpmac10: dpmac@a { -+ dpmac10: ethernet@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; -+ pcs-handle = <&pcs10>; - }; - -- dpmac11: dpmac@b { -+ dpmac11: ethernet@b { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xb>; -+ pcs-handle = <&pcs11>; - }; - -- dpmac12: dpmac@c { -+ dpmac12: ethernet@c { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xc>; -+ pcs-handle = <&pcs12>; - }; - -- dpmac13: dpmac@d { -+ dpmac13: ethernet@d { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xd>; -+ pcs-handle = <&pcs13>; - }; - -- dpmac14: dpmac@e { -+ dpmac14: ethernet@e { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xe>; -+ pcs-handle = <&pcs14>; - }; - -- dpmac15: dpmac@f { -+ dpmac15: ethernet@f { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xf>; -+ pcs-handle = <&pcs15>; - }; - -- dpmac16: dpmac@10 { -+ dpmac16: ethernet@10 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x10>; -+ pcs-handle = <&pcs16>; - }; - }; - }; -@@ -685,13 +957,14 @@ gpio3: gpio@2330000 { - - i2c0: i2c@2000000 { - status = "disabled"; -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -+ clocks = <&clockgen 4 1>; -+ scl-gpios = <&gpio3 10 0>; - }; - - i2c1: i2c@2010000 { -@@ -702,7 +975,7 @@ i2c1: i2c@2010000 { - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -+ clocks = <&clockgen 4 1>; - }; - - i2c2: i2c@2020000 { -@@ -713,7 +986,7 @@ i2c2: i2c@2020000 { - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -+ clocks = <&clockgen 4 1>; - }; - - i2c3: i2c@2030000 { -@@ -724,7 +997,7 @@ i2c3: i2c@2030000 { - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -+ clocks = <&clockgen 4 1>; - }; - - ifc: ifc@2240000 { -@@ -756,8 +1029,8 @@ qspi: spi@20c0000 { - pcie1: pcie@3400000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; -- interrupts = <0 108 0x4>; /* Level high type */ -- interrupt-names = "intr"; -+ interrupts = <0 108 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -778,8 +1051,8 @@ pcie1: pcie@3400000 { - pcie2: pcie@3500000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; -- interrupts = <0 113 0x4>; /* Level high type */ -- interrupt-names = "intr"; -+ interrupts = <0 113 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -800,8 +1073,8 @@ pcie2: pcie@3500000 { - pcie3: pcie@3600000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; -- interrupts = <0 118 0x4>; /* Level high type */ -- interrupt-names = "intr"; -+ interrupts = <0 118 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -822,8 +1095,8 @@ pcie3: pcie@3600000 { - pcie4: pcie@3700000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; -- interrupts = <0 123 0x4>; /* Level high type */ -- interrupt-names = "intr"; -+ interrupts = <0 123 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -861,24 +1134,26 @@ sata1: sata@3210000 { - - usb0: usb3@3100000 { - status = "disabled"; -- compatible = "snps,dwc3"; -+ compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; - }; - - usb1: usb3@3110000 { - status = "disabled"; -- compatible = "snps,dwc3"; -+ compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; - }; - - ccn@4000000 { -diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts -index 2d1fe6c37..bafb643c5 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts -@@ -2,7 +2,7 @@ - // - // Device Tree file for LX2160AQDS - // --// Copyright 2018 NXP -+// Copyright 2018-2019 NXP - - /dts-v1/; - -@@ -29,6 +29,138 @@ sb_3v3: regulator-sb3v3 { - regulator-boot-on; - regulator-always-on; - }; -+ -+ mdio-mux-1 { -+ compatible = "mdio-mux-multiplexer"; -+ mux-controls = <&mux 0>; -+ mdio-parent-bus = <&emdio1>; -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ mdio@0 { /* On-board PHY #1 RGMI1*/ -+ reg = <0x00>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@8 { /* On-board PHY #2 RGMI2*/ -+ reg = <0x8>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@18 { /* Slot #1 */ -+ reg = <0x18>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@19 { /* Slot #2 */ -+ reg = <0x19>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1a { /* Slot #3 */ -+ reg = <0x1a>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1b { /* Slot #4 */ -+ reg = <0x1b>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1c { /* Slot #5 */ -+ reg = <0x1c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1d { /* Slot #6 */ -+ reg = <0x1d>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1e { /* Slot #7 */ -+ reg = <0x1e>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1f { /* Slot #8 */ -+ reg = <0x1f>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ -+ mdio-mux-2 { -+ compatible = "mdio-mux-multiplexer"; -+ mux-controls = <&mux 1>; -+ mdio-parent-bus = <&emdio2>; -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ mdio@0 { /* Slot #1 (secondary EMI) */ -+ reg = <0x00>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1 { /* Slot #2 (secondary EMI) */ -+ reg = <0x01>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@2 { /* Slot #3 (secondary EMI) */ -+ reg = <0x02>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@3 { /* Slot #4 (secondary EMI) */ -+ reg = <0x03>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@4 { /* Slot #5 (secondary EMI) */ -+ reg = <0x04>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@5 { /* Slot #6 (secondary EMI) */ -+ reg = <0x05>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@6 { /* Slot #7 (secondary EMI) */ -+ reg = <0x06>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@7 { /* Slot #8 (secondary EMI) */ -+ reg = <0x07>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+}; -+ -+&can0 { -+ status = "okay"; -+}; -+ -+&can1 { -+ status = "okay"; - }; - - &crypto { -@@ -71,6 +203,14 @@ dflash2: flash@0 { - }; - }; - -+&emdio1 { -+ status = "okay"; -+}; -+ -+&emdio2 { -+ status = "okay"; -+}; -+ - &esdhc0 { - status = "okay"; - }; -@@ -97,6 +237,19 @@ mt35xu512aba0: flash@0 { - &i2c0 { - status = "okay"; - -+ fpga@66 { -+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", -+ "simple-mfd"; -+ reg = <0x66>; -+ -+ mux: mux-controller { -+ compatible = "reg-mux"; -+ #mux-control-cells = <1>; -+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ -+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ -+ }; -+ }; -+ - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; -@@ -177,3 +330,19 @@ &usb0 { - &usb1 { - status = "okay"; - }; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&sata2 { -+ status = "okay"; -+}; -+ -+&sata3 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts -index 54fe8cd3a..5f7659bac 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts -@@ -2,7 +2,7 @@ - // - // Device Tree file for LX2160ARDB - // --// Copyright 2018 NXP -+// Copyright 2018-2020 NXP - - /dts-v1/; - -@@ -31,10 +31,38 @@ sb_3v3: regulator-sb3v3 { - }; - }; - -+&can0 { -+ status = "okay"; -+ -+ can-transceiver { -+ max-bitrate = <5000000>; -+ }; -+}; -+ -+&can1 { -+ status = "okay"; -+ -+ can-transceiver { -+ max-bitrate = <5000000>; -+ }; -+}; -+ - &crypto { - status = "okay"; - }; - -+&dpmac3 { -+ phy-handle = <&aquantia_phy1>; -+ phy-connection-type = "usxgmii"; -+ managed = "in-band-status"; -+}; -+ -+&dpmac4 { -+ phy-handle = <&aquantia_phy2>; -+ phy-connection-type = "usxgmii"; -+ managed = "in-band-status"; -+}; -+ - &dpmac17 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -@@ -61,6 +89,24 @@ rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - eee-broken-1000t; - }; -+ -+ aquantia_phy1: ethernet-phy@4 { -+ /* AQR107 PHY */ -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = ; -+ reg = <0x4>; -+ }; -+ -+ aquantia_phy2: ethernet-phy@5 { -+ /* AQR107 PHY */ -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = ; -+ reg = <0x5>; -+ }; -+}; -+ -+&emdio2 { -+ status = "okay"; - }; - - &esdhc0 { -@@ -151,11 +197,19 @@ &i2c4 { - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; -- // IRQ10_B -- interrupts = <0 150 0x4>; -+ /* IRQ_RTC_B -> IRQ08, active low */ -+ interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>; - }; - }; - -+&pcs_mdio3 { -+ status = "okay"; -+}; -+ -+&pcs_mdio4 { -+ status = "okay"; -+}; -+ - &sata0 { - status = "okay"; - }; -@@ -187,3 +241,18 @@ &usb0 { - &usb1 { - status = "okay"; - }; -+ -+&emdio2 { -+ inphi_phy: ethernet-phy@0 { -+ compatible = "ethernet-phy-id0210.7440"; -+ reg = <0x0>; -+ }; -+}; -+ -+&dpmac5 { -+ phy-handle = <&inphi_phy>; -+}; -+ -+&dpmac6 { -+ phy-handle = <&inphi_phy>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi -index 83072da6f..cff0699d7 100644 ---- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi -@@ -17,6 +17,8 @@ / { - #size-cells = <2>; - - aliases { -+ mmc0 = &esdhc0; -+ mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; - }; - -@@ -664,6 +666,37 @@ dcfg: syscon@1e00000 { - little-endian; - }; - -+ isc: syscon@1f70000 { -+ compatible = "fsl,lx2160a-isc", "syscon"; -+ reg = <0x0 0x1f70000 0x0 0x10000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x1f70000 0x10000>; -+ -+ extirq: interrupt-controller@14 { -+ compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; -+ #interrupt-cells = <2>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x14 4>; -+ interrupt-map = -+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, -+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, -+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, -+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, -+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, -+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, -+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, -+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, -+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, -+ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, -+ <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, -+ <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-map-mask = <0xffffffff 0x0>; -+ }; -+ }; -+ - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; -@@ -686,7 +719,7 @@ i2c0: i2c@2000000 { - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; -- scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; -+ scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - -@@ -731,7 +764,7 @@ i2c4: i2c@2040000 { - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; -- scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; -+ scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - -@@ -847,6 +880,24 @@ esdhc1: esdhc@2150000 { - status = "disabled"; - }; - -+ can0: can@2180000 { -+ compatible = "fsl,lx2160ar1-flexcan"; -+ reg = <0x0 0x2180000 0x0 0x10000>; -+ interrupts = ; -+ clocks = <&sysclk>, <&clockgen 4 7>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ can1: can@2190000 { -+ compatible = "fsl,lx2160ar1-flexcan"; -+ reg = <0x0 0x2190000 0x0 0x10000>; -+ interrupts = ; -+ clocks = <&sysclk>, <&clockgen 4 7>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ - uart0: serial@21c0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21c0000 0x0 0x1000>; -@@ -946,24 +997,32 @@ ftm_alarm0: timer@2800000 { - }; - - usb0: usb@3100000 { -- compatible = "snps,dwc3"; -+ compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ dma-coherent; - status = "disabled"; - }; - - usb1: usb@3110000 { -- compatible = "snps,dwc3"; -+ compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,host-vbus-glitches; -+ dma-coherent; - status = "disabled"; - }; - -@@ -1039,6 +1098,15 @@ pcie1: pcie@3400000 { - status = "disabled"; - }; - -+ pcie_ep1: pcie_ep@3400000 { -+ compatible = "fsl,lx2160a-pcie-ep"; -+ reg = <0x00 0x03400000 0x0 0x00100000 -+ 0x80 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ apio-wins = <8>; -+ status = "disabled"; -+ }; -+ - pcie2: pcie@3500000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -@@ -1067,6 +1135,15 @@ pcie2: pcie@3500000 { - status = "disabled"; - }; - -+ pcie_ep2: pcie_ep@3500000 { -+ compatible = "fsl,lx2160a-pcie-ep"; -+ reg = <0x00 0x03500000 0x0 0x00100000 -+ 0x88 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ apio-wins = <8>; -+ status = "disabled"; -+ }; -+ - pcie3: pcie@3600000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -@@ -1095,6 +1172,16 @@ pcie3: pcie@3600000 { - status = "disabled"; - }; - -+ pcie_ep3: pcie_ep@3600000 { -+ compatible = "fsl,lx2160a-pcie-ep"; -+ reg = <0x00 0x03600000 0x0 0x00100000 -+ 0x90 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ apio-wins = <256>; -+ max-functions = /bits/ 8 <2>; -+ status = "disabled"; -+ }; -+ - pcie4: pcie@3700000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ -@@ -1123,6 +1210,15 @@ pcie4: pcie@3700000 { - status = "disabled"; - }; - -+ pcie_ep4: pcie_ep@3700000 { -+ compatible = "fsl,lx2160a-pcie-ep"; -+ reg = <0x00 0x03700000 0x0 0x00100000 -+ 0x98 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ apio-wins = <8>; -+ status = "disabled"; -+ }; -+ - pcie5: pcie@3800000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ -@@ -1151,6 +1247,16 @@ pcie5: pcie@3800000 { - status = "disabled"; - }; - -+ pcie_ep5: pcie_ep@3800000 { -+ compatible = "fsl,lx2160a-pcie-ep"; -+ reg = <0x00 0x03800000 0x0 0x00100000 -+ 0xa0 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ apio-wins = <256>; -+ max-functions = /bits/ 8 <2>; -+ status = "disabled"; -+ }; -+ - pcie6: pcie@3900000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ -@@ -1179,6 +1285,15 @@ pcie6: pcie@3900000 { - status = "disabled"; - }; - -+ pcie_ep6: pcie_ep@3900000 { -+ compatible = "fsl,lx2160a-pcie-ep"; -+ reg = <0x00 0x03900000 0x0 0x00100000 -+ 0xa8 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ apio-wins = <8>; -+ status = "disabled"; -+ }; -+ - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; -@@ -1305,6 +1420,240 @@ emdio2: mdio@8b97000 { - status = "disabled"; - }; - -+ pcs_mdio1: mdio@8c07000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c07000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs1: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio2: mdio@8c0b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs2: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio3: mdio@8c0f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs3: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio4: mdio@8c13000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c13000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs4: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio5: mdio@8c17000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c17000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs5: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio6: mdio@8c1b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs6: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio7: mdio@8c1f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs7: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio8: mdio@8c23000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c23000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs8: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio9: mdio@8c27000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c27000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs9: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio10: mdio@8c2b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c2b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs10: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio11: mdio@8c2f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c2f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs11: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio12: mdio@8c33000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c33000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs12: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio13: mdio@8c37000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c37000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs13: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio14: mdio@8c3b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c3b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs14: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio15: mdio@8c3f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c3f000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs15: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio16: mdio@8c43000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c43000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs16: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio17: mdio@8c47000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c47000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs17: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ -+ pcs_mdio18: mdio@8c4b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c4b000 0x0 0x1000>; -+ little-endian; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ pcs18: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, -@@ -1330,96 +1679,121 @@ dpmacs { - #address-cells = <1>; - #size-cells = <0>; - -- dpmac1: dpmac@1 { -+ dpmac1: ethernet@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; -+ pcs-handle = <&pcs1>; - }; - -- dpmac2: dpmac@2 { -+ dpmac2: ethernet@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; -+ pcs-handle = <&pcs2>; - }; - -- dpmac3: dpmac@3 { -+ dpmac3: ethernet@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; -+ pcs-handle = <&pcs3>; - }; - -- dpmac4: dpmac@4 { -+ dpmac4: ethernet@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; -+ pcs-handle = <&pcs4>; - }; - -- dpmac5: dpmac@5 { -+ dpmac5: ethernet@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; -+ pcs-handle = <&pcs5>; - }; - -- dpmac6: dpmac@6 { -+ dpmac6: ethernet@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; -+ pcs-handle = <&pcs6>; - }; - -- dpmac7: dpmac@7 { -+ dpmac7: ethernet@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; -+ pcs-handle = <&pcs7>; - }; - -- dpmac8: dpmac@8 { -+ dpmac8: ethernet@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; -+ pcs-handle = <&pcs8>; - }; - -- dpmac9: dpmac@9 { -+ dpmac9: ethernet@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; -+ pcs-handle = <&pcs9>; - }; - -- dpmac10: dpmac@a { -+ dpmac10: ethernet@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; -+ pcs-handle = <&pcs10>; - }; - -- dpmac11: dpmac@b { -+ dpmac11: ethernet@b { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xb>; -+ pcs-handle = <&pcs11>; - }; - -- dpmac12: dpmac@c { -+ dpmac12: ethernet@c { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xc>; -+ pcs-handle = <&pcs12>; - }; - -- dpmac13: dpmac@d { -+ dpmac13: ethernet@d { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xd>; -+ pcs-handle = <&pcs13>; - }; - -- dpmac14: dpmac@e { -+ dpmac14: ethernet@e { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xe>; -+ pcs-handle = <&pcs14>; - }; - -- dpmac15: dpmac@f { -+ dpmac15: ethernet@f { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xf>; -+ pcs-handle = <&pcs15>; - }; - -- dpmac16: dpmac@10 { -+ dpmac16: ethernet@10 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x10>; -+ pcs-handle = <&pcs16>; - }; - -- dpmac17: dpmac@11 { -+ dpmac17: ethernet@11 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x11>; -+ pcs-handle = <&pcs17>; - }; - -- dpmac18: dpmac@12 { -+ dpmac18: ethernet@12 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x12>; -+ pcs-handle = <&pcs18>; - }; - }; - }; - }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts -new file mode 100644 -index 000000000..13d3119a9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts -@@ -0,0 +1,581 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+// -+// Device Tree file for LX2162AQDS -+// -+// Copyright 2020 NXP -+ -+/dts-v1/; -+ -+#include "fsl-lx2160a.dtsi" -+ -+/ { -+ model = "NXP Layerscape LX2162AQDS"; -+ compatible = "fsl,lx2162a-qds", "fsl,lx2160a"; -+ -+ aliases { -+ crypto = &crypto; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ sb_3v3: regulator-sb3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "MC34717-3.3VSB"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ mdio-mux-1 { -+ compatible = "mdio-mux-multiplexer"; -+ mux-controls = <&mux 0>; -+ mdio-parent-bus = <&emdio1>; -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ mdio@0 { /* On-board RTL8211F PHY #1 RGMII1*/ -+ reg = <0x00>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916"; -+ reg = <0x1>; -+ eee-broken-1000t; -+ }; -+ }; -+ -+ mdio@8 { /* On-board RTL8211F PHY #2 RGMII2*/ -+ reg = <0x8>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-id001c.c916"; -+ reg = <0x2>; -+ eee-broken-1000t; -+ }; -+ }; -+ -+ mdio@18 { /* Slot #1 */ -+ reg = <0x18>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@19 { /* Slot #2 */ -+ reg = <0x19>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1a { /* Slot #3 */ -+ reg = <0x1a>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1b { /* Slot #4 */ -+ reg = <0x1b>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1c { /* Slot #5 */ -+ reg = <0x1c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1d { /* Slot #6 */ -+ reg = <0x1d>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1e { /* Slot #7 */ -+ reg = <0x1e>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1f { /* Slot #8 */ -+ reg = <0x1f>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ -+ mdio-mux-2 { -+ compatible = "mdio-mux-multiplexer"; -+ mux-controls = <&mux 1>; -+ mdio-parent-bus = <&emdio2>; -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ mdio@0 { /* Slot #1 (secondary EMI) */ -+ reg = <0x00>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@1 { /* Slot #2 (secondary EMI) */ -+ reg = <0x01>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@2 { /* Slot #3 (secondary EMI) */ -+ reg = <0x02>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@3 { /* Slot #4 (secondary EMI) */ -+ reg = <0x03>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@4 { /* Slot #5 (secondary EMI) */ -+ reg = <0x04>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@5 { /* Slot #6 (secondary EMI) */ -+ reg = <0x05>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@6 { /* Slot #7 (secondary EMI) */ -+ reg = <0x06>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio@7 { /* Slot #8 (secondary EMI) */ -+ reg = <0x07>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+}; -+ -+&can0 { -+ status = "okay"; -+}; -+ -+&can1 { -+ status = "okay"; -+}; -+ -+&crypto { -+ status = "okay"; -+}; -+ -+&dpmac17 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii-id"; -+}; -+ -+&dpmac18 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii-id"; -+}; -+ -+&dspi0 { -+ status = "okay"; -+ -+ dflash0: flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <1000000>; -+ }; -+}; -+ -+&dspi1 { -+ status = "okay"; -+ -+ dflash1: flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <1000000>; -+ }; -+}; -+ -+&dspi2 { -+ status = "okay"; -+ -+ dflash2: flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <1000000>; -+ }; -+}; -+ -+&emdio1 { -+ status = "okay"; -+}; -+ -+&emdio2 { -+ status = "okay"; -+}; -+ -+&esdhc0 { -+ sd-uhs-sdr104; -+ sd-uhs-sdr50; -+ sd-uhs-sdr25; -+ sd-uhs-sdr12; -+ status = "okay"; -+}; -+ -+&esdhc1 { -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ -+&fspi { -+ status = "okay"; -+ -+ mt35xu512aba0: flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ m25p,fast-read; -+ spi-max-frequency = <50000000>; -+ reg = <0>; -+ spi-rx-bus-width = <8>; -+ spi-tx-bus-width = <8>; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ fpga@66 { -+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", -+ "simple-mfd"; -+ reg = <0x66>; -+ -+ mux: mux-controller { -+ compatible = "reg-mux"; -+ #mux-control-cells = <1>; -+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ -+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ -+ }; -+ }; -+ -+ i2c-mux@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ power-monitor@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <500>; -+ }; -+ -+ power-monitor@41 { -+ compatible = "ti,ina220"; -+ reg = <0x41>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ temperature-sensor@4c { -+ compatible = "nxp,sa56004"; -+ reg = <0x4c>; -+ vcc-supply = <&sb_3v3>; -+ }; -+ -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */ -+ interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; -+ }; -+ }; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&sata2 { -+ status = "okay"; -+}; -+ -+&sata3 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ compatible = "fsl,ls2088a-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = , /* AER interrupt */ -+ , /* PME interrupt */ -+ ; /* controller interrupt */ -+ interrupt-names = "aer", "pme", "intr"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-viewport = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+}; -+ -+&pcie_ep1 { -+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; -+ reg = <0x00 0x03400000 0x0 0x00100000 -+ 0x80 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ num-ob-windows = <8>; -+ num-ib-windows = <8>; -+ status = "disabled"; -+}; -+ -+&pcie2 { -+ compatible = "fsl,ls2088a-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = , /* AER interrupt */ -+ , /* PME interrupt */ -+ ; /* controller interrupt */ -+ interrupt-names = "aer", "pme", "intr"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-viewport = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+}; -+ -+&pcie_ep2 { -+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; -+ reg = <0x00 0x03500000 0x0 0x00100000 -+ 0x88 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ num-ob-windows = <8>; -+ num-ib-windows = <8>; -+ status = "disabled"; -+}; -+ -+&pcie3 { -+ compatible = "fsl,ls2088a-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = , /* AER interrupt */ -+ , /* PME interrupt */ -+ ; /* controller interrupt */ -+ interrupt-names = "aer", "pme", "intr"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-viewport = <256>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+}; -+ -+&pcie_ep3 { -+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; -+ reg = <0x00 0x03600000 0x0 0x00100000 -+ 0x90 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ num-ob-windows = <256>; -+ num-ib-windows = <24>; -+ status = "disabled"; -+}; -+ -+&pcie4 { -+ compatible = "fsl,ls2088a-pcie"; -+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ -+ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = , /* AER interrupt */ -+ , /* PME interrupt */ -+ ; /* controller interrupt */ -+ interrupt-names = "aer", "pme", "intr"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-viewport = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+}; -+ -+&pcie_ep4 { -+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; -+ reg = <0x00 0x03700000 0x0 0x00100000 -+ 0x98 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ num-ob-windows = <8>; -+ num-ib-windows = <8>; -+ status = "disabled"; -+}; -+ -+&pcie5 { -+ compatible = "fsl,ls2088a-pcie"; -+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ -+ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = , /* AER interrupt */ -+ , /* PME interrupt */ -+ ; /* controller interrupt */ -+ interrupt-names = "aer", "pme", "intr"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-viewport = <256>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+}; -+ -+&pcie_ep5 { -+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; -+ reg = <0x00 0x03800000 0x0 0x00100000 -+ 0xa0 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ num-ob-windows = <256>; -+ num-ib-windows = <24>; -+ status = "disabled"; -+}; -+ -+&pcie6 { -+ compatible = "fsl,ls2088a-pcie"; -+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ -+ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = , /* AER interrupt */ -+ , /* PME interrupt */ -+ ; /* controller interrupt */ -+ interrupt-names = "aer", "pme", "intr"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-viewport = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+}; -+ -+&pcie_ep6 { -+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; -+ reg = <0x00 0x03900000 0x0 0x00100000 -+ 0xa8 0x00000000 0x8 0x00000000>; -+ reg-names = "regs", "addr_space"; -+ num-ob-windows = <8>; -+ num-ib-windows = <8>; -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi -new file mode 100644 -index 000000000..841758bd2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+#include "imx8-ss-audio.dtsi" -+#include "imx8-ss-dma.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi -new file mode 100644 -index 000000000..9c2157704 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi -@@ -0,0 +1,672 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+audio_subsys: bus@59000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x59000000 0x0 0x59000000 0x1000000>; -+ -+ audio_ipg_clk: clock-audio-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <175000000>; -+ clock-output-names = "audio_ipg_clk"; -+ }; -+ -+ edma0: dma-controller@591F0000 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x591f0000 0x10000>, -+ <0x59200000 0x10000>, /* asrc0 */ -+ <0x59210000 0x10000>, -+ <0x59220000 0x10000>, -+ <0x59230000 0x10000>, -+ <0x59240000 0x10000>, -+ <0x59250000 0x10000>, -+ <0x59260000 0x10000>, /* esai0 rx */ -+ <0x59270000 0x10000>, /* esai0 tx */ -+ <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x592e0000 0x10000>, /* sai1 rx */ -+ <0x592f0000 0x10000>, /* sai1 tx */ -+ <0x59300000 0x10000>, /* sai2 rx */ -+ <0x59310000 0x10000>, /* sai3 rx */ -+ <0x59350000 0x10000>, -+ <0x59370000 0x10000>; -+ #dma-cells = <3>; -+ shared-interrupt; -+ dma-channels = <18>; -+ interrupts = , /* asrc 0 */ -+ , -+ , -+ , -+ , -+ , -+ , /* esai0 */ -+ , -+ , /* spdif0 */ -+ , -+ , /* sai0 */ -+ , -+ , /* sai1 */ -+ , -+ , /* sai2 */ -+ , /* sai3 */ -+ , -+ ; -+ interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ -+ "edma0-chan2-rx", "edma0-chan3-tx", -+ "edma0-chan4-tx", "edma0-chan5-tx", -+ "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ -+ "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ -+ "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ -+ "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ -+ "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ -+ "edma0-chan21-tx", /* gpt5 */ -+ "edma0-chan23-rx"; /* gpt7 */ -+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>, -+ <&pd IMX_SC_R_DMA_0_CH1>, -+ <&pd IMX_SC_R_DMA_0_CH2>, -+ <&pd IMX_SC_R_DMA_0_CH3>, -+ <&pd IMX_SC_R_DMA_0_CH4>, -+ <&pd IMX_SC_R_DMA_0_CH5>, -+ <&pd IMX_SC_R_DMA_0_CH6>, -+ <&pd IMX_SC_R_DMA_0_CH7>, -+ <&pd IMX_SC_R_DMA_0_CH8>, -+ <&pd IMX_SC_R_DMA_0_CH9>, -+ <&pd IMX_SC_R_DMA_0_CH12>, -+ <&pd IMX_SC_R_DMA_0_CH13>, -+ <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>, -+ <&pd IMX_SC_R_DMA_0_CH16>, -+ <&pd IMX_SC_R_DMA_0_CH17>, -+ <&pd IMX_SC_R_DMA_0_CH21>, -+ <&pd IMX_SC_R_DMA_0_CH23>; -+ power-domain-names = "edma0-chan0", "edma0-chan1", -+ "edma0-chan2", "edma0-chan3", -+ "edma0-chan4", "edma0-chan5", -+ "edma0-chan6", "edma0-chan7", -+ "edma0-chan8", "edma0-chan9", -+ "edma0-chan12", "edma0-chan13", -+ "edma0-chan14", "edma0-chan15", -+ "edma0-chan16", "edma0-chan17", -+ "edma0-chan21", "edma0-chan23"; -+ status = "okay"; -+ }; -+ -+ edma1: dma-controller@599F0000 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x599F0000 0x10000>, -+ <0x59A00000 0x10000>, /* asrc1 */ -+ <0x59A10000 0x10000>, -+ <0x59A20000 0x10000>, -+ <0x59A30000 0x10000>, -+ <0x59A40000 0x10000>, -+ <0x59A50000 0x10000>, -+ <0x59A80000 0x10000>, /* sai4 rx */ -+ <0x59A90000 0x10000>, /* sai4 tx */ -+ <0x59AA0000 0x10000>; /* sai5 tx */ -+ #dma-cells = <3>; -+ shared-interrupt; -+ dma-channels = <9>; -+ interrupts = , /* asrc 1 */ -+ , -+ , -+ , -+ , -+ , -+ , /* sai4 */ -+ , -+ ; /* sai5 */ -+ interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ -+ "edma1-chan2-rx", "edma1-chan3-tx", -+ "edma1-chan4-tx", "edma1-chan5-tx", -+ "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ -+ "edma1-chan10-tx"; /* sai5 */ -+ power-domains = <&pd IMX_SC_R_DMA_1_CH0>, -+ <&pd IMX_SC_R_DMA_1_CH1>, -+ <&pd IMX_SC_R_DMA_1_CH2>, -+ <&pd IMX_SC_R_DMA_1_CH3>, -+ <&pd IMX_SC_R_DMA_1_CH4>, -+ <&pd IMX_SC_R_DMA_1_CH5>, -+ <&pd IMX_SC_R_DMA_1_CH8>, -+ <&pd IMX_SC_R_DMA_1_CH9>, -+ <&pd IMX_SC_R_DMA_1_CH10>; -+ power-domain-names = "edma1-chan0", "edma1-chan1", -+ "edma1-chan2", "edma1-chan3", -+ "edma1-chan4", "edma1-chan5", -+ "edma1-chan8", "edma1-chan9", -+ "edma1-chan10"; -+ status = "okay"; -+ }; -+ -+ acm: acm@59e00000 { -+ compatible = "nxp,imx8qxp-acm"; -+ reg = <0x59e00000 0x1D0000>; -+ #clock-cells = <1>; -+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_MCLK_OUT_0>, -+ <&pd IMX_SC_R_MCLK_OUT_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>, -+ <&pd IMX_SC_R_ASRC_0>, -+ <&pd IMX_SC_R_ASRC_1>, -+ <&pd IMX_SC_R_ESAI_0>, -+ <&pd IMX_SC_R_SAI_0>, -+ <&pd IMX_SC_R_SAI_1>, -+ <&pd IMX_SC_R_SAI_2>, -+ <&pd IMX_SC_R_SAI_3>, -+ <&pd IMX_SC_R_SAI_4>, -+ <&pd IMX_SC_R_SAI_5>, -+ <&pd IMX_SC_R_SPDIF_0>, -+ <&pd IMX_SC_R_MQS_0>; -+ }; -+ -+ asrc0: asrc@59000000 { -+ compatible = "fsl,imx8qm-asrc"; -+ reg = <0x59000000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&asrc0_lpcg 0>, -+ <&asrc0_lpcg 0>, -+ <&aud_pll_div0_lpcg 0>, -+ <&aud_pll_div1_lpcg 0>, -+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, -+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "ipg", "mem", -+ "asrck_0", "asrck_1", "asrck_2", "asrck_3", -+ "asrck_4", "asrck_5", "asrck_6", "asrck_7", -+ "asrck_8", "asrck_9", "asrck_a", "asrck_b", -+ "asrck_c", "asrck_d", "asrck_e", "asrck_f", -+ "spba"; -+ dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, -+ <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; -+ dma-names = "rxa", "rxb", "rxc", -+ "txa", "txb", "txc"; -+ fsl,asrc-rate = <8000>; -+ fsl,asrc-width = <16>; -+ fsl,asrc-clk-map = <0>; -+ power-domains = <&pd IMX_SC_R_ASRC_0>; -+ status = "disabled"; -+ }; -+ -+ esai0: esai@59010000 { -+ compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; -+ reg = <0x59010000 0x10000>; -+ interrupts = ; -+ clocks = <&esai0_lpcg 1>, -+ <&esai0_lpcg 0>, -+ <&esai0_lpcg 1>, -+ <&clk_dummy>; -+ clock-names = "core", "extal", "fsys", "spba"; -+ dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd IMX_SC_R_ESAI_0>; -+ status = "disabled"; -+ }; -+ -+ spdif0: spdif@59020000 { -+ compatible = "fsl,imx8qm-spdif"; -+ reg = <0x59020000 0x10000>; -+ interrupts = , /* rx */ -+ ; /* tx */ -+ clocks = <&spdif0_lpcg 1>, /* core */ -+ <&clk_dummy>, /* rxtx0 */ -+ <&spdif0_lpcg 0>, /* rxtx1 */ -+ <&clk_dummy>, /* rxtx2 */ -+ <&clk_dummy>, /* rxtx3 */ -+ <&clk_dummy>, /* rxtx4 */ -+ <&audio_ipg_clk>, /* rxtx5 */ -+ <&clk_dummy>, /* rxtx6 */ -+ <&clk_dummy>, /* rxtx7 */ -+ <&clk_dummy>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd IMX_SC_R_SPDIF_0>; -+ status = "disabled"; -+ }; -+ -+ spdif1: spdif@59030000 { -+ compatible = "fsl,imx8qm-spdif"; -+ reg = <0x59030000 0x10000>; -+ interrupts = , /* rx */ -+ ; /* tx */ -+ clocks = <&spdif1_lpcg 1>, /* core */ -+ <&clk_dummy>, /* rxtx0 */ -+ <&spdif1_lpcg 0>, /* rxtx1 */ -+ <&clk_dummy>, /* rxtx2 */ -+ <&clk_dummy>, /* rxtx3 */ -+ <&clk_dummy>, /* rxtx4 */ -+ <&audio_ipg_clk>, /* rxtx5 */ -+ <&clk_dummy>, /* rxtx6 */ -+ <&clk_dummy>, /* rxtx7 */ -+ <&clk_dummy>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd IMX_SC_R_SPDIF_1>; -+ status = "disabled"; -+ }; -+ -+ sai0: sai@59040000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59040000 0x10000>; -+ interrupts = ; -+ clocks = <&sai0_lpcg 1>, -+ <&clk_dummy>, -+ <&sai0_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx", "tx"; -+ dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; -+ power-domains = <&pd IMX_SC_R_SAI_0>; -+ status = "disabled"; -+ }; -+ -+ sai1: sai@59050000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59050000 0x10000>; -+ interrupts = ; -+ clocks = <&sai1_lpcg 1>, -+ <&clk_dummy>, -+ <&sai1_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx", "tx"; -+ dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; -+ power-domains = <&pd IMX_SC_R_SAI_1>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@59060000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59060000 0x10000>; -+ interrupts = ; -+ clocks = <&sai2_lpcg 1>, -+ <&clk_dummy>, -+ <&sai2_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx"; -+ dmas = <&edma0 16 0 1>; -+ power-domains = <&pd IMX_SC_R_SAI_2>; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@59070000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59070000 0x10000>; -+ interrupts = ; -+ clocks = <&sai3_lpcg 1>, -+ <&clk_dummy>, -+ <&sai3_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx"; -+ dmas = <&edma0 17 0 1>; -+ power-domains = <&pd IMX_SC_R_SAI_3>; -+ status = "disabled"; -+ }; -+ -+ asrc1: asrc@59800000 { -+ compatible = "fsl,imx8qm-asrc"; -+ reg = <0x59800000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&asrc1_lpcg 0>, -+ <&asrc1_lpcg 0>, -+ <&aud_pll_div0_lpcg 0>, -+ <&aud_pll_div1_lpcg 0>, -+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, -+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "ipg", "mem", -+ "asrck_0", "asrck_1", "asrck_2", "asrck_3", -+ "asrck_4", "asrck_5", "asrck_6", "asrck_7", -+ "asrck_8", "asrck_9", "asrck_a", "asrck_b", -+ "asrck_c", "asrck_d", "asrck_e", "asrck_f", -+ "spba"; -+ dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, -+ <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; -+ dma-names = "rxa", "rxb", "rxc", -+ "txa", "txb", "txc"; -+ fsl,asrc-rate = <8000>; -+ fsl,asrc-width = <16>; -+ fsl,asrc-clk-map = <1>; -+ power-domains = <&pd IMX_SC_R_ASRC_1>; -+ status = "disabled"; -+ }; -+ -+ sai4: sai@59820000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59820000 0x10000>; -+ interrupts = ; -+ clocks = <&sai4_lpcg 1>, -+ <&clk_dummy>, -+ <&sai4_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx", "tx"; -+ dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; -+ power-domains = <&pd IMX_SC_R_SAI_4>; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@59830000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59830000 0x10000>; -+ interrupts = ; -+ clocks = <&sai5_lpcg 1>, -+ <&clk_dummy>, -+ <&sai5_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx"; -+ dmas = <&edma1 10 0 0>; -+ power-domains = <&pd IMX_SC_R_SAI_5>; -+ status = "disabled"; -+ }; -+ -+ amix: amix@59840000 { -+ compatible = "fsl,imx8qm-audmix"; -+ reg = <0x59840000 0x10000>; -+ clocks = <&amix_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_AMIX>; -+ dais = <&sai4>, <&sai5>; -+ status = "disabled"; -+ }; -+ -+ mqs: mqs@59850000 { -+ compatible = "fsl,imx8qm-mqs"; -+ reg = <0x59850000 0x10000>; -+ clocks = <&mqs0_lpcg 1>, -+ <&mqs0_lpcg 0>; -+ clock-names = "core", "mclk"; -+ power-domains = <&pd IMX_SC_R_MQS_0>; -+ status = "disabled"; -+ }; -+ -+ asrc0_lpcg: clock-controller@59400000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59400000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&audio_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "asrc0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ASRC_0>; -+ }; -+ -+ esai0_lpcg: clock-controller@59410000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59410000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "esai0_lpcg_extal_clk", -+ "esai0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ESAI_0>; -+ }; -+ -+ spdif0_lpcg: clock-controller@59420000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59420000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "spdif0_lpcg_tx_clk", -+ "spdif0_lpcg_gclkw"; -+ power-domains = <&pd IMX_SC_R_SPDIF_0>; -+ }; -+ -+ spdif1_lpcg: clock-controller@59430000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59430000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "spdif1_lpcg_tx_clk", -+ "spdif1_lpcg_gclkw"; -+ power-domains = <&pd IMX_SC_R_SPDIF_1>; -+ status = "disabled"; -+ }; -+ -+ sai0_lpcg: clock-controller@59440000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59440000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "sai0_lpcg_mclk", -+ "sai0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_0>; -+ }; -+ -+ sai1_lpcg: clock-controller@59450000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59450000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "sai1_lpcg_mclk", -+ "sai1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_1>; -+ }; -+ -+ sai2_lpcg: clock-controller@59460000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59460000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "sai2_lpcg_mclk", -+ "sai2_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_2>; -+ }; -+ -+ sai3_lpcg: clock-controller@59470000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59470000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "sai3_lpcg_mclk", -+ "sai3_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_3>; -+ }; -+ -+ dsp_lpcg: clock-controller@59580000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59580000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&audio_ipg_clk>, -+ <&audio_ipg_clk>, -+ <&audio_ipg_clk>; -+ bit-offset = <16 20 28>; -+ clock-output-names = "dsp_lpcg_adb_aclk", -+ "dsp_lpcg_ipg_clk", -+ "dsp_lpcg_core_clk"; -+ power-domains = <&pd IMX_SC_R_DSP>; -+ }; -+ -+ dsp_ram_lpcg: clock-controller@59590000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59590000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&audio_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "dsp_ram_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_DSP_RAM>; -+ }; -+ -+ asrc1_lpcg: clock-controller@59c00000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c00000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&audio_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "asrc1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ASRC_1>; -+ }; -+ -+ sai4_lpcg: clock-controller@59c20000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c20000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "sai4_lpcg_mclk", -+ "sai4_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_4>; -+ }; -+ -+ sai5_lpcg: clock-controller@59c30000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c30000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "sai5_lpcg_mclk", -+ "sai5_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_5>; -+ }; -+ -+ amix_lpcg: clock-controller@59c40000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c40000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&audio_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "amix_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_AMIX>; -+ }; -+ -+ mqs0_lpcg: clock-controller@59c50000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c50000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "mqs0_lpcg_mclk", -+ "mqs0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MQS_0>; -+ }; -+ -+ aud_rec0_lpcg: clock-controller@59d00000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59d00000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; -+ bit-offset = <0>; -+ clock-output-names = "aud_rec_clk0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; -+ }; -+ -+ aud_rec1_lpcg: clock-controller@59d10000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59d10000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; -+ bit-offset = <0>; -+ clock-output-names = "aud_rec_clk1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; -+ }; -+ -+ aud_pll_div0_lpcg: clock-controller@59d20000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59d20000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; -+ bit-offset = <0>; -+ clock-output-names = "aud_pll_div_clk0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; -+ }; -+ -+ aud_pll_div1_lpcg: clock-controller@59d30000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59d30000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; -+ bit-offset = <0>; -+ clock-output-names = "aud_pll_div_clk1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; -+ }; -+ -+ mclkout0_lpcg: clock-controller@59d50000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59d50000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; -+ bit-offset = <0>; -+ clock-output-names = "mclkout0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; -+ }; -+ -+ mclkout1_lpcg: clock-controller@59d60000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59d60000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; -+ bit-offset = <0>; -+ clock-output-names = "mclkout1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi -new file mode 100644 -index 000000000..2ca0eeff1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi -@@ -0,0 +1,92 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+cm40_subsys: bus@34000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x34000000 0x0 0x34000000 0x4000000>; -+ -+ cm40_ipg_clk: clock-cm40-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <132000000>; -+ clock-output-names = "cm40_ipg_clk"; -+ }; -+ -+ cm40_i2c: i2c@37230000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x37230000 0x1000>; -+ interrupts = <9 0>; -+ interrupt-parent = <&cm40_intmux>; -+ clocks = <&cm40_i2c_lpcg 0>, -+ <&cm40_i2c_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_M4_0_I2C>; -+ status = "disabled"; -+ }; -+ -+ cm40_i2c_lpcg: clock-controller@37630000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x37630000 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, -+ <&cm40_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "cm40_lpcg_i2c_clk", -+ "cm40_lpcg_i2c_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_M4_0_I2C>; -+ }; -+ -+ cm40_intmux: intmux@37400000 { -+ compatible = "fsl,imx8qxp-intmux", "fsl,imx-intmux"; -+ reg = <0x37400000 0x1000>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <2>; -+ clocks = <&cm40_ipg_clk>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; -+ status = "disabled"; -+ }; -+ -+ cm40_lpuart: serial@37220000 { -+ compatible = "fsl,imx8qxp-lpuart"; -+ reg = <0x37220000 0x1000>; -+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&cm40_intmux>; -+ clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>; -+ clock-names = "ipg", "baud"; -+ assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_M4_0_UART>; -+ status = "disabled"; -+ }; -+ -+ cm40_uart_lpcg: clock-controller@37620000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x37620000 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>, -+ <&cm40_ipg_clk>; -+ bit-offset = <0 4>; -+ clock-output-names = "cm40_lpcg_uart_clk", -+ "cm40_lpcg_uart_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_M4_0_UART>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi -new file mode 100644 -index 000000000..d0551f381 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi -@@ -0,0 +1,67 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+cm41_subsys: bus@38000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x38000000 0x0 0x38000000 0x4000000>; -+ -+ cm41_ipg_clk: clock-cm41-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <132000000>; -+ clock-output-names = "cm41_ipg_clk"; -+ }; -+ -+ cm41_i2c: i2c@3b230000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x3b230000 0x1000>; -+ interrupts = <9 0>; -+ interrupt-parent = <&cm41_intmux>; -+ clocks = <&cm41_i2c_lpcg 0>, -+ <&cm41_i2c_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_M4_1_I2C>; -+ status = "disabled"; -+ }; -+ -+ cm41_i2c_lpcg: clock-controller@3b630000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x3b630000 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, -+ <&cm41_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "cm41_lpcg_i2c_clk", -+ "cm41_lpcg_i2c_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_M4_1_I2C>; -+ }; -+ -+ cm41_intmux: intmux@3b400000 { -+ compatible = "fsl,imx8qxp-intmux", "fsl,imx-intmux"; -+ reg = <0x3b400000 0x1000>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <2>; -+ clocks = <&cm41_ipg_clk>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi -new file mode 100644 -index 000000000..c97c8a6f5 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi -@@ -0,0 +1,378 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+conn_subsys: bus@5b000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; -+ -+ conn_axi_clk: clock-conn-axi { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <333333333>; -+ clock-output-names = "conn_axi_clk"; -+ }; -+ -+ conn_ahb_clk: clock-conn-ahb { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <166666666>; -+ clock-output-names = "conn_ahb_clk"; -+ }; -+ -+ conn_ipg_clk: clock-conn-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <83333333>; -+ clock-output-names = "conn_ipg_clk"; -+ }; -+ -+ conn_bch_clk: clock-conn-bch { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ clock-output-names = "conn_bch_clk"; -+ }; -+ -+ usbotg1: usb@5b0d0000 { -+ compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", -+ "fsl,imx27-usb"; -+ reg = <0x5b0d0000 0x200>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ fsl,usbphy = <&usbphy1>; -+ fsl,usbmisc = <&usbmisc1 0>; -+ clocks = <&usb2_lpcg 0>; -+ ahb-burst-config = <0x0>; -+ tx-burst-size-dword = <0x10>; -+ rx-burst-size-dword = <0x10>; -+ power-domains = <&pd IMX_SC_R_USB_0>; -+ status = "disabled"; -+ }; -+ -+ usbmisc1: usbmisc@5b0d0200 { -+ #index-cells = <1>; -+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; -+ reg = <0x5b0d0200 0x200>; -+ }; -+ -+ usbphy1: usbphy@0x5b100000 { -+ compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", -+ "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; -+ reg = <0x5b100000 0x1000>; -+ clocks = <&usb2_lpcg 1>; -+ power-domains = <&pd IMX_SC_R_USB_0_PHY>; -+ status = "disabled"; -+ }; -+ -+ usdhc1: mmc@5b010000 { -+ interrupts = ; -+ reg = <0x5b010000 0x10000>; -+ clocks = <&sdhc0_lpcg 1>, -+ <&sdhc0_lpcg 0>, -+ <&sdhc0_lpcg 2>; -+ clock-names = "ipg", "per", "ahb"; -+ power-domains = <&pd IMX_SC_R_SDHC_0>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ status = "disabled"; -+ }; -+ -+ usdhc2: mmc@5b020000 { -+ interrupts = ; -+ reg = <0x5b020000 0x10000>; -+ clocks = <&sdhc1_lpcg 1>, -+ <&sdhc1_lpcg 0>, -+ <&sdhc1_lpcg 2>; -+ clock-names = "ipg", "per", "ahb"; -+ power-domains = <&pd IMX_SC_R_SDHC_1>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@5b030000 { -+ interrupts = ; -+ reg = <0x5b030000 0x10000>; -+ clocks = <&sdhc2_lpcg 1>, -+ <&sdhc2_lpcg 0>, -+ <&sdhc2_lpcg 2>; -+ clock-names = "ipg", "per", "ahb"; -+ power-domains = <&pd IMX_SC_R_SDHC_2>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ status = "disabled"; -+ }; -+ -+ fec1: ethernet@5b040000 { -+ reg = <0x5b040000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&enet0_lpcg 4>, -+ <&enet0_lpcg 2>, -+ <&enet0_lpcg 3>, -+ <&enet0_lpcg 0>, -+ <&enet0_lpcg 1>; -+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; -+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; -+ assigned-clock-rates = <250000000>, <125000000>; -+ fsl,num-tx-queues=<3>; -+ fsl,num-rx-queues=<3>; -+ power-domains = <&pd IMX_SC_R_ENET_0>; -+ status = "disabled"; -+ }; -+ -+ fec2: ethernet@5b050000 { -+ reg = <0x5b050000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&enet1_lpcg 4>, -+ <&enet1_lpcg 2>, -+ <&enet1_lpcg 3>, -+ <&enet1_lpcg 0>, -+ <&enet1_lpcg 1>; -+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; -+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; -+ assigned-clock-rates = <250000000>, <125000000>; -+ fsl,num-tx-queues=<3>; -+ fsl,num-rx-queues=<3>; -+ power-domains = <&pd IMX_SC_R_ENET_1>; -+ status = "disabled"; -+ }; -+ -+ usb3_phy: usb-phy@5b160000 { -+ compatible = "nxp,salvo-phy"; -+ reg = <0x5B160000 0x40000>; -+ clocks = <&usb3_lpcg 4>; -+ clock-names = "salvo_phy_clk"; -+ power-domains = <&pd IMX_SC_R_USB_2_PHY>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usbotg3: usb@5b110000 { -+ compatible = "fsl,imx8qm-usb3"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ reg = <0x5B110000 0x10000>; -+ clocks = <&usb3_lpcg 1>, -+ <&usb3_lpcg 0>, -+ <&usb3_lpcg 5>, -+ <&usb3_lpcg 2>, -+ <&usb3_lpcg 3>; -+ clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", -+ "usb3_ipg_clk", "usb3_core_pclk"; -+ assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, -+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <125000000>, <12000000>, <250000000>; -+ power-domains = <&pd IMX_SC_R_USB_2>; -+ status = "disabled"; -+ -+ usbotg3_cdns3: usb@5b120000 { -+ compatible = "cdns,usb3"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "host", "peripheral", "otg", "wakeup"; -+ reg = <0x5B130000 0x10000>, /* memory area for HOST registers */ -+ <0x5B140000 0x10000>, /* memory area for DEVICE registers */ -+ <0x5B120000 0x10000>; /* memory area for OTG/DRD registers */ -+ reg-names = "xhci", "dev", "otg"; -+ phys = <&usb3_phy>; -+ phy-names = "cdns3,usb3-phy"; -+ status = "disabled"; -+ }; -+ }; -+ -+ /* LPCG clocks */ -+ sdhc0_lpcg: clock-controller@5b200000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b200000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, -+ <&conn_ipg_clk>, <&conn_axi_clk>; -+ bit-offset = <0 16 20>; -+ clock-output-names = "sdhc0_lpcg_per_clk", -+ "sdhc0_lpcg_ipg_clk", -+ "sdhc0_lpcg_ahb_clk"; -+ power-domains = <&pd IMX_SC_R_SDHC_0>; -+ }; -+ -+ sdhc1_lpcg: clock-controller@5b210000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b210000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, -+ <&conn_ipg_clk>, <&conn_axi_clk>; -+ bit-offset = <0 16 20>; -+ clock-output-names = "sdhc1_lpcg_per_clk", -+ "sdhc1_lpcg_ipg_clk", -+ "sdhc1_lpcg_ahb_clk"; -+ power-domains = <&pd IMX_SC_R_SDHC_1>; -+ }; -+ -+ sdhc2_lpcg: clock-controller@5b220000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b220000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, -+ <&conn_ipg_clk>, <&conn_axi_clk>; -+ bit-offset = <0 16 20>; -+ clock-output-names = "sdhc2_lpcg_per_clk", -+ "sdhc2_lpcg_ipg_clk", -+ "sdhc2_lpcg_ahb_clk"; -+ power-domains = <&pd IMX_SC_R_SDHC_2>; -+ }; -+ -+ enet0_lpcg: clock-controller@5b230000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b230000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, -+ <&conn_axi_clk>, -+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, -+ <&conn_ipg_clk>, -+ <&conn_ipg_clk>; -+ bit-offset = <0 4 8 12 16 20>; -+ clock-output-names = "enet0_lpcg_timer_clk", -+ "enet0_lpcg_txc_sampling_clk", -+ "enet0_lpcg_ahb_clk", -+ "enet0_lpcg_rgmii_txc_clk", -+ "enet0_lpcg_ipg_clk", -+ "enet0_lpcg_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_ENET_0>; -+ }; -+ -+ enet1_lpcg: clock-controller@5b240000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b240000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, -+ <&conn_axi_clk>, -+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, -+ <&conn_ipg_clk>, -+ <&conn_ipg_clk>; -+ bit-offset = <0 4 8 12 16 20>; -+ clock-output-names = "enet1_lpcg_timer_clk", -+ "enet1_lpcg_txc_sampling_clk", -+ "enet1_lpcg_ahb_clk", -+ "enet1_lpcg_rgmii_txc_clk", -+ "enet1_lpcg_ipg_clk", -+ "enet1_lpcg_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_ENET_1>; -+ }; -+ -+ usb2_lpcg: clock-controller@5b270000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b270000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; -+ bit-offset = <24 28>; -+ clock-output-names = "usboh3_ahb_clk", -+ "usboh3_phy_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_USB_0_PHY>; -+ }; -+ -+ usb3_lpcg: clock-controller@5b280000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b280000 0x10000>; -+ #clock-cells = <1>; -+ bit-offset = <0 4 16 20 24 28>; -+ clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, -+ <&conn_ipg_clk>, -+ <&conn_ipg_clk>, -+ <&conn_ipg_clk>, -+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; -+ clock-output-names = "usb3_app_clk", -+ "usb3_lpm_clk", -+ "usb3_ipg_clk", -+ "usb3_core_pclk", -+ "usb3_phy_clk", -+ "usb3_aclk"; -+ power-domains = <&pd IMX_SC_R_USB_2_PHY>; -+ }; -+ -+ rawnand_0_lpcg: clock-controller@5b290000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b290000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, -+ <&conn_axi_clk>, -+ <&conn_axi_clk>; -+ bit-offset = <0 4 16 20>; -+ clock-output-names = "bch_clk", -+ "gpmi_clk", -+ "gpmi_apb_clk", -+ "bch_apb_clk"; -+ power-domains = <&pd IMX_SC_R_NAND>; -+ }; -+ -+ rawnand_4_lpcg: clock-controller@5b290004 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b290004 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&conn_axi_clk>; -+ bit-offset = <16>; -+ clock-output-names = "apbhdma_hclk"; -+ power-domains = <&pd IMX_SC_R_NAND>; -+ }; -+ -+ dma_apbh: dma-apbh@5b810000 { -+ compatible = "fsl,imx28-dma-apbh"; -+ reg = <0x5b810000 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&rawnand_4_lpcg 0>; -+ clock-names = "apbhdma_hclk"; -+ power-domains = <&pd IMX_SC_R_NAND>; -+ }; -+ -+ gpmi: gpmi-nand@5b812000{ -+ compatible = "fsl,imx8qxp-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&rawnand_0_lpcg 1>, -+ <&rawnand_0_lpcg 2>, -+ <&rawnand_0_lpcg 0>, -+ <&rawnand_0_lpcg 3>; -+ clock-names = "gpmi_clk", "gpmi_apb_clk", -+ "bch_clk", "bch_apb_clk"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ power-domains = <&pd IMX_SC_R_NAND>; -+ assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <50000000>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi -new file mode 100644 -index 000000000..eef051915 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi -@@ -0,0 +1,487 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+dc0_subsys: bus@56000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x56000000 0x0 0x56000000 0x300000>; -+ -+ dc0_cfg_clk: clock-dc-cfg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "dc0_cfg_clk"; -+ }; -+ -+ dc0_axi_int_clk: clock-dc-axi-int { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ clock-output-names = "dc0_axi_int_clk"; -+ }; -+ -+ dc0_axi_ext_clk: clock-dc-axi-ext { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <800000000>; -+ clock-output-names = "dc0_axi_ext_clk"; -+ }; -+ -+ dc0_disp_lpcg: clock-controller@56010000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; -+ bit-offset = <0 4>; -+ clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_dpr0_lpcg: clock-controller@56010018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_cfg_clk>, -+ <&dc0_axi_ext_clk>; -+ bit-offset = <16 20>; -+ clock-output-names = "dc0_dpr0_lpcg_apb_clk", -+ "dc0_dpr0_lpcg_b_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_rtram0_lpcg: clock-controller@5601001c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5601001c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>; -+ bit-offset = <0>; -+ clock-output-names = "dc0_rtram0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ -+ dc0_prg0_lpcg: clock-controller@56010020 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010020 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg0_lpcg_rtram_clk", -+ "dc0_prg0_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg1_lpcg: clock-controller@56010024 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010024 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg1_lpcg_rtram_clk", -+ "dc0_prg1_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg2_lpcg: clock-controller@56010028 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010028 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg2_lpcg_rtram_clk", -+ "dc0_prg2_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_dpr1_lpcg: clock-controller@5601002c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5601002c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_cfg_clk>, -+ <&dc0_axi_ext_clk>; -+ bit-offset = <16 20>; -+ clock-output-names = "dc0_dpr1_lpcg_apb_clk", -+ "dc0_dpr1_lpcg_b_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_rtram1_lpcg: clock-controller@56010030 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010030 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>; -+ bit-offset = <0>; -+ clock-output-names = "dc0_rtram1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg3_lpcg: clock-controller@56010034 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010034 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg3_lpcg_rtram_clk", -+ "dc0_prg3_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg4_lpcg: clock-controller@56010038 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010038 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg4_lpcg_rtram_clk", -+ "dc0_prg4_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg5_lpcg: clock-controller@5601003c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5601003c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg5_lpcg_rtram_clk", -+ "dc0_prg5_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg6_lpcg: clock-controller@56010040 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010040 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg6_lpcg_rtram_clk", -+ "dc0_prg6_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg7_lpcg: clock-controller@56010044 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010044 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg7_lpcg_rtram_clk", -+ "dc0_prg7_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_prg8_lpcg: clock-controller@56010048 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56010048 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc0_axi_ext_clk>, -+ <&dc0_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc0_prg8_lpcg_rtram_clk", -+ "dc0_prg8_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_irqsteer: irqsteer@56000000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x56000000 0x10000>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ clocks = <&dc0_cfg_clk>; -+ clock-names = "ipg"; -+ fsl,channel = <0>; -+ fsl,num-irqs = <512>; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ }; -+ -+ dc0_pc: pixel-combiner@56020000 { -+ compatible = "fsl,imx8qxp-pixel-combiner", -+ "fsl,imx8qm-pixel-combiner"; -+ reg = <0x56020000 0x10000>; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg1: prg@56040000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x56040000 0x10000>; -+ clocks = <&dc0_prg0_lpcg 0>, -+ <&dc0_prg0_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg2: prg@56050000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x56050000 0x10000>; -+ clocks = <&dc0_prg1_lpcg 0>, -+ <&dc0_prg1_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg3: prg@56060000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x56060000 0x10000>; -+ clocks = <&dc0_prg2_lpcg 0>, -+ <&dc0_prg2_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg4: prg@56070000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x56070000 0x10000>; -+ clocks = <&dc0_prg3_lpcg 0>, -+ <&dc0_prg3_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg5: prg@56080000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x56080000 0x10000>; -+ clocks = <&dc0_prg4_lpcg 0>, -+ <&dc0_prg4_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg6: prg@56090000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x56090000 0x10000>; -+ clocks = <&dc0_prg5_lpcg 0>, -+ <&dc0_prg5_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg7: prg@560a0000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x560a0000 0x10000>; -+ clocks = <&dc0_prg6_lpcg 0>, -+ <&dc0_prg6_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg8: prg@560b0000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x560b0000 0x10000>; -+ clocks = <&dc0_prg7_lpcg 0>, -+ <&dc0_prg7_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_prg9: prg@560c0000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x560c0000 0x10000>; -+ clocks = <&dc0_prg8_lpcg 0>, -+ <&dc0_prg8_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_dpr1_channel1: dpr-channel@560d0000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x560d0000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc0_prg1>; -+ clocks = <&dc0_dpr0_lpcg 0>, -+ <&dc0_dpr0_lpcg 1>, -+ <&dc0_rtram0_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_dpr1_channel2: dpr-channel@560e0000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x560e0000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; -+ clocks = <&dc0_dpr0_lpcg 0>, -+ <&dc0_dpr0_lpcg 1>, -+ <&dc0_rtram0_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_dpr1_channel3: dpr-channel@560f0000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x560f0000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc0_prg3>; -+ clocks = <&dc0_dpr0_lpcg 0>, -+ <&dc0_dpr0_lpcg 1>, -+ <&dc0_rtram0_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_dpr2_channel1: dpr-channel@56100000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x56100000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; -+ clocks = <&dc0_dpr1_lpcg 0>, -+ <&dc0_dpr1_lpcg 1>, -+ <&dc0_rtram1_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_dpr2_channel2: dpr-channel@56110000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x56110000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc0_prg6>, <&dc0_prg7>; -+ clocks = <&dc0_dpr1_lpcg 0>, -+ <&dc0_dpr1_lpcg 1>, -+ <&dc0_rtram1_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dc0_dpr2_channel3: dpr-channel@56120000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x56120000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc0_prg8>, <&dc0_prg9>; -+ clocks = <&dc0_dpr1_lpcg 0>, -+ <&dc0_dpr1_lpcg 1>, -+ <&dc0_rtram1_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_0>; -+ status = "disabled"; -+ }; -+ -+ dpu1: dpu@56180000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x56180000 0x40000>; -+ interrupt-parent = <&dc0_irqsteer>; -+ interrupts = <448>, <449>, <450>, <64>, -+ <65>, <66>, <67>, <68>, -+ <69>, <70>, <193>, <194>, -+ <195>, <196>, <197>, <72>, -+ <73>, <74>, <75>, <76>, -+ <77>, <78>, <79>, <80>, -+ <81>, <199>, <200>, <201>, -+ <202>, <203>, <204>, <205>, -+ <206>, <207>, <208>, <5>, -+ <0>, <1>, <2>, <3>, -+ <4>, <82>, <83>, <84>, -+ <85>, <209>, <210>, <211>, -+ <212>; -+ interrupt-names = "store9_shdload", -+ "store9_framecomplete", -+ "store9_seqcomplete", -+ "extdst0_shdload", -+ "extdst0_framecomplete", -+ "extdst0_seqcomplete", -+ "extdst4_shdload", -+ "extdst4_framecomplete", -+ "extdst4_seqcomplete", -+ "extdst1_shdload", -+ "extdst1_framecomplete", -+ "extdst1_seqcomplete", -+ "extdst5_shdload", -+ "extdst5_framecomplete", -+ "extdst5_seqcomplete", -+ "disengcfg_shdload0", -+ "disengcfg_framecomplete0", -+ "disengcfg_seqcomplete0", -+ "framegen0_int0", -+ "framegen0_int1", -+ "framegen0_int2", -+ "framegen0_int3", -+ "sig0_shdload", -+ "sig0_valid", -+ "sig0_error", -+ "disengcfg_shdload1", -+ "disengcfg_framecomplete1", -+ "disengcfg_seqcomplete1", -+ "framegen1_int0", -+ "framegen1_int1", -+ "framegen1_int2", -+ "framegen1_int3", -+ "sig1_shdload", -+ "sig1_valid", -+ "sig1_error", -+ "reserved", -+ "cmdseq_error", -+ "comctrl_sw0", -+ "comctrl_sw1", -+ "comctrl_sw2", -+ "comctrl_sw3", -+ "framegen0_primsync_on", -+ "framegen0_primsync_off", -+ "framegen0_secsync_on", -+ "framegen0_secsync_off", -+ "framegen1_primsync_on", -+ "framegen1_primsync_off", -+ "framegen1_secsync_on", -+ "framegen1_secsync_off"; -+ clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>, -+ <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; -+ clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; -+ power-domains = <&pd IMX_SC_R_DC_0>, -+ <&pd IMX_SC_R_DC_0_PLL_0>, -+ <&pd IMX_SC_R_DC_0_PLL_1>; -+ power-domain-names = "dc", "pll0", "pll1"; -+ fsl,dpr-channels = <&dc0_dpr1_channel1>, -+ <&dc0_dpr1_channel2>, -+ <&dc0_dpr1_channel3>, -+ <&dc0_dpr2_channel1>, -+ <&dc0_dpr2_channel2>, -+ <&dc0_dpr2_channel3>; -+ fsl,pixel-combiner = <&dc0_pc>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi -new file mode 100644 -index 000000000..c05a3eb7f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi -@@ -0,0 +1,488 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+dc1_subsys: bus@57000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x57000000 0x0 0x57000000 0x300000>; -+ -+ dc1_cfg_clk: clock-dc-cfg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "dc1_cfg_clk"; -+ }; -+ -+ dc1_axi_int_clk: clock-dc-axi-int { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ clock-output-names = "dc1_axi_int_clk"; -+ }; -+ -+ dc1_axi_ext_clk: clock-dc-axi-ext { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <800000000>; -+ clock-output-names = "dc1_axi_ext_clk"; -+ }; -+ -+ dc1_disp_lpcg: clock-controller@57010000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; -+ bit-offset = <0 4>; -+ clock-output-names = "dc1_disp0_lpcg_clk", "dc1_disp1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_dpr0_lpcg: clock-controller@57010018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_cfg_clk>, -+ <&dc1_axi_ext_clk>; -+ bit-offset = <16 20>; -+ clock-output-names = "dc1_dpr0_lpcg_apb_clk", -+ "dc1_dpr0_lpcg_b_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_rtram0_lpcg: clock-controller@5701001c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5701001c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>; -+ bit-offset = <0>; -+ clock-output-names = "dc1_rtram0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ -+ dc1_prg0_lpcg: clock-controller@57010020 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010020 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg0_lpcg_rtram_clk", -+ "dc1_prg0_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg1_lpcg: clock-controller@57010024 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010024 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg1_lpcg_rtram_clk", -+ "dc1_prg1_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg2_lpcg: clock-controller@57010028 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010028 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg2_lpcg_rtram_clk", -+ "dc1_prg2_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_dpr1_lpcg: clock-controller@5701002c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5701002c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_cfg_clk>, -+ <&dc1_axi_ext_clk>; -+ bit-offset = <16 20>; -+ clock-output-names = "dc1_dpr1_lpcg_apb_clk", -+ "dc1_dpr1_lpcg_b_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_rtram1_lpcg: clock-controller@57010030 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010030 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>; -+ bit-offset = <0>; -+ clock-output-names = "dc1_rtram1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg3_lpcg: clock-controller@57010034 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010034 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg3_lpcg_rtram_clk", -+ "dc1_prg3_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg4_lpcg: clock-controller@57010038 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010038 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg4_lpcg_rtram_clk", -+ "dc1_prg4_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg5_lpcg: clock-controller@5701003c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5701003c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg5_lpcg_rtram_clk", -+ "dc1_prg5_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg6_lpcg: clock-controller@57010040 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010040 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg6_lpcg_rtram_clk", -+ "dc1_prg6_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg7_lpcg: clock-controller@57010044 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010044 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg7_lpcg_rtram_clk", -+ "dc1_prg7_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_prg8_lpcg: clock-controller@57010048 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57010048 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dc1_axi_ext_clk>, -+ <&dc1_cfg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "dc1_prg8_lpcg_rtram_clk", -+ "dc1_prg8_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_irqsteer: irqsteer@57000000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x57000000 0x10000>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ clocks = <&dc1_cfg_clk>; -+ clock-names = "ipg"; -+ fsl,channel = <0>; -+ fsl,num-irqs = <512>; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ }; -+ -+ dc1_pc: pixel-combiner@57020000 { -+ compatible = "fsl,imx8qxp-pixel-combiner", -+ "fsl,imx8qm-pixel-combiner"; -+ reg = <0x57020000 0x10000>; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg1: prg@57040000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x57040000 0x10000>; -+ clocks = <&dc1_prg0_lpcg 0>, -+ <&dc1_prg0_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg2: prg@57050000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x57050000 0x10000>; -+ clocks = <&dc1_prg1_lpcg 0>, -+ <&dc1_prg1_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg3: prg@57060000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x57060000 0x10000>; -+ clocks = <&dc1_prg2_lpcg 0>, -+ <&dc1_prg2_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg4: prg@57070000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x57070000 0x10000>; -+ clocks = <&dc1_prg3_lpcg 0>, -+ <&dc1_prg3_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg5: prg@57080000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x57080000 0x10000>; -+ clocks = <&dc1_prg4_lpcg 0>, -+ <&dc1_prg4_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg6: prg@57090000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x57090000 0x10000>; -+ clocks = <&dc1_prg5_lpcg 0>, -+ <&dc1_prg5_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg7: prg@570a0000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x570a0000 0x10000>; -+ clocks = <&dc1_prg6_lpcg 0>, -+ <&dc1_prg6_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg8: prg@570b0000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x570b0000 0x10000>; -+ clocks = <&dc1_prg7_lpcg 0>, -+ <&dc1_prg7_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_prg9: prg@570c0000 { -+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; -+ reg = <0x570c0000 0x10000>; -+ clocks = <&dc1_prg8_lpcg 0>, -+ <&dc1_prg8_lpcg 1>; -+ clock-names = "rtram", "apb"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_dpr1_channel1: dpr-channel@570d0000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x570d0000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc1_prg1>; -+ clocks = <&dc1_dpr0_lpcg 0>, -+ <&dc1_dpr0_lpcg 1>, -+ <&dc1_rtram0_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_dpr1_channel2: dpr-channel@570e0000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x570e0000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc1_prg2>, <&dc1_prg1>; -+ clocks = <&dc1_dpr0_lpcg 0>, -+ <&dc1_dpr0_lpcg 1>, -+ <&dc1_rtram0_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_dpr1_channel3: dpr-channel@570f0000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x570f0000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc1_prg3>; -+ clocks = <&dc1_dpr0_lpcg 0>, -+ <&dc1_dpr0_lpcg 1>, -+ <&dc1_rtram0_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_dpr2_channel1: dpr-channel@57100000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x57100000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc1_prg4>, <&dc1_prg5>; -+ clocks = <&dc1_dpr1_lpcg 0>, -+ <&dc1_dpr1_lpcg 1>, -+ <&dc1_rtram1_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_dpr2_channel2: dpr-channel@57110000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x57110000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc1_prg6>, <&dc1_prg7>; -+ clocks = <&dc1_dpr1_lpcg 0>, -+ <&dc1_dpr1_lpcg 1>, -+ <&dc1_rtram1_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dc1_dpr2_channel3: dpr-channel@57120000 { -+ compatible = "fsl,imx8qxp-dpr-channel", -+ "fsl,imx8qm-dpr-channel"; -+ reg = <0x57120000 0x10000>; -+ fsl,sc-resource = ; -+ fsl,prgs = <&dc1_prg8>, <&dc1_prg9>; -+ clocks = <&dc1_dpr1_lpcg 0>, -+ <&dc1_dpr1_lpcg 1>, -+ <&dc1_rtram1_lpcg 0>; -+ clock-names = "apb", "b", "rtram"; -+ power-domains = <&pd IMX_SC_R_DC_1>; -+ status = "disabled"; -+ }; -+ -+ dpu2: dpu@57180000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x57180000 0x40000>; -+ interrupt-parent = <&dc1_irqsteer>; -+ interrupts = <448>, <449>, <450>, <64>, -+ <65>, <66>, <67>, <68>, -+ <69>, <70>, <193>, <194>, -+ <195>, <196>, <197>, <72>, -+ <73>, <74>, <75>, <76>, -+ <77>, <78>, <79>, <80>, -+ <81>, <199>, <200>, <201>, -+ <202>, <203>, <204>, <205>, -+ <206>, <207>, <208>, <5>, -+ <0>, <1>, <2>, <3>, -+ <4>, <82>, <83>, <84>, -+ <85>, <209>, <210>, <211>, -+ <212>; -+ interrupt-names = "store9_shdload", -+ "store9_framecomplete", -+ "store9_seqcomplete", -+ "extdst0_shdload", -+ "extdst0_framecomplete", -+ "extdst0_seqcomplete", -+ "extdst4_shdload", -+ "extdst4_framecomplete", -+ "extdst4_seqcomplete", -+ "extdst1_shdload", -+ "extdst1_framecomplete", -+ "extdst1_seqcomplete", -+ "extdst5_shdload", -+ "extdst5_framecomplete", -+ "extdst5_seqcomplete", -+ "disengcfg_shdload0", -+ "disengcfg_framecomplete0", -+ "disengcfg_seqcomplete0", -+ "framegen0_int0", -+ "framegen0_int1", -+ "framegen0_int2", -+ "framegen0_int3", -+ "sig0_shdload", -+ "sig0_valid", -+ "sig0_error", -+ "disengcfg_shdload1", -+ "disengcfg_framecomplete1", -+ "disengcfg_seqcomplete1", -+ "framegen1_int0", -+ "framegen1_int1", -+ "framegen1_int2", -+ "framegen1_int3", -+ "sig1_shdload", -+ "sig1_valid", -+ "sig1_error", -+ "reserved", -+ "cmdseq_error", -+ "comctrl_sw0", -+ "comctrl_sw1", -+ "comctrl_sw2", -+ "comctrl_sw3", -+ "framegen0_primsync_on", -+ "framegen0_primsync_off", -+ "framegen0_secsync_on", -+ "framegen0_secsync_off", -+ "framegen1_primsync_on", -+ "framegen1_primsync_off", -+ "framegen1_secsync_on", -+ "framegen1_secsync_off"; -+ clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>, -+ <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>; -+ clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; -+ power-domains = <&pd IMX_SC_R_DC_1>, -+ <&pd IMX_SC_R_DC_1_PLL_0>, -+ <&pd IMX_SC_R_DC_1_PLL_1>; -+ power-domain-names = "dc", "pll0", "pll1"; -+ fsl,dpr-channels = <&dc1_dpr1_channel1>, -+ <&dc1_dpr1_channel2>, -+ <&dc1_dpr1_channel3>, -+ <&dc1_dpr2_channel1>, -+ <&dc1_dpr2_channel2>, -+ <&dc1_dpr2_channel3>; -+ fsl,pixel-combiner = <&dc1_pc>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi -new file mode 100644 -index 000000000..defe5a7f9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+ddr_subsys: bus@5c000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; -+ -+ ddr_pmu0: ddr-pmu@5c020000 { -+ compatible = "fsl,imx8-ddr-pmu"; -+ reg = <0x5c020000 0x10000>; -+ interrupts = ; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi -new file mode 100644 -index 000000000..6343f28de ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi -@@ -0,0 +1,630 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+dma_subsys: bus@5a000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; -+ -+ dma_ipg_clk: clock-dma-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <120000000>; -+ clock-output-names = "dma_ipg_clk"; -+ }; -+ -+ lpspi0: spi@5a000000 { -+ compatible = "fsl,imx7ulp-spi"; -+ reg = <0x5a000000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&spi0_lpcg 0>, -+ <&spi0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <20000000>; -+ power-domains = <&pd IMX_SC_R_SPI_0>; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 1 0 0>, <&edma2 0 0 1>; -+ status = "disabled"; -+ }; -+ -+ lpspi1: spi@5a010000 { -+ compatible = "fsl,imx7ulp-spi"; -+ reg = <0x5a010000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&spi1_lpcg 0>, -+ <&spi1_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <60000000>; -+ power-domains = <&pd IMX_SC_R_SPI_1>; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 3 0 0>, <&edma2 2 0 1>; -+ status = "disabled"; -+ }; -+ -+ lpspi2: spi@5a020000 { -+ compatible = "fsl,imx7ulp-spi"; -+ reg = <0x5a020000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&spi2_lpcg 0>, -+ <&spi2_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <60000000>; -+ power-domains = <&pd IMX_SC_R_SPI_2>; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 5 0 0>, <&edma2 4 0 1>; -+ status = "disabled"; -+ }; -+ -+ lpspi3: spi@5a030000 { -+ compatible = "fsl,imx7ulp-spi"; -+ reg = <0x5a030000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&spi3_lpcg 0>, -+ <&spi3_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <60000000>; -+ power-domains = <&pd IMX_SC_R_SPI_3>; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 7 0 0>, <&edma2 6 0 1>; -+ status = "disabled"; -+ }; -+ -+ lpuart0: serial@5a060000 { -+ reg = <0x5a060000 0x1000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>; -+ clock-names = "ipg", "baud"; -+ assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd IMX_SC_R_UART_0>; -+ status = "disabled"; -+ }; -+ -+ lpuart1: serial@5a070000 { -+ reg = <0x5a070000 0x1000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>; -+ clock-names = "ipg", "baud"; -+ assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd IMX_SC_R_UART_1>; -+ power-domain-names = "uart"; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 11 0 0>, -+ <&edma2 10 0 1>; -+ status = "disabled"; -+ }; -+ -+ lpuart2: serial@5a080000 { -+ reg = <0x5a080000 0x1000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>; -+ clock-names = "ipg", "baud"; -+ assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd IMX_SC_R_UART_2>; -+ power-domain-names = "uart"; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 13 0 0>, -+ <&edma2 12 0 1>; -+ status = "disabled"; -+ }; -+ -+ lpuart3: serial@5a090000 { -+ reg = <0x5a090000 0x1000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>; -+ clock-names = "ipg", "baud"; -+ assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd IMX_SC_R_UART_3>; -+ power-domain-names = "uart"; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 15 0 0>, -+ <&edma2 14 0 1>; -+ status = "disabled"; -+ }; -+ -+ emvsim0: sim0@5a0d0000 { -+ compatible = "fsl,imx8-emvsim"; -+ reg = <0x5a0d0000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&emvsim0_lpcg 0>, -+ <&emvsim0_lpcg 1>; -+ clock-names = "sim", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>; -+ power-domain-names = "sim_pd", "sim_aux_pd"; -+ status = "disabled"; -+ }; -+ -+ edma2: dma-controller@5a1f0000 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x5a1f0000 0x10000>, -+ <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ -+ <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ -+ <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ -+ <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ -+ <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ -+ <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ -+ <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ -+ <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ -+ <0x5a280000 0x10000>, /* channel8 UART0 rx */ -+ <0x5a290000 0x10000>, /* channel9 UART0 tx */ -+ <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ -+ <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ -+ <0x5a2c0000 0x10000>, /* channel12 UART2 rx */ -+ <0x5a2d0000 0x10000>, /* channel13 UART2 tx */ -+ <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ -+ <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ -+ #dma-cells = <3>; -+ dma-channels = <16>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", -+ "edma2-chan2-rx", "edma2-chan3-tx", -+ "edma2-chan4-rx", "edma2-chan5-tx", -+ "edma2-chan6-rx", "edma2-chan7-tx", -+ "edma2-chan8-rx", "edma2-chan9-tx", -+ "edma2-chan10-rx", "edma2-chan11-tx", -+ "edma2-chan12-rx", "edma2-chan13-tx", -+ "edma2-chan14-rx", "edma2-chan15-tx"; -+ power-domains = <&pd IMX_SC_R_DMA_2_CH0>, -+ <&pd IMX_SC_R_DMA_2_CH1>, -+ <&pd IMX_SC_R_DMA_2_CH2>, -+ <&pd IMX_SC_R_DMA_2_CH3>, -+ <&pd IMX_SC_R_DMA_2_CH4>, -+ <&pd IMX_SC_R_DMA_2_CH5>, -+ <&pd IMX_SC_R_DMA_2_CH6>, -+ <&pd IMX_SC_R_DMA_2_CH7>, -+ <&pd IMX_SC_R_DMA_2_CH8>, -+ <&pd IMX_SC_R_DMA_2_CH9>, -+ <&pd IMX_SC_R_DMA_2_CH10>, -+ <&pd IMX_SC_R_DMA_2_CH11>, -+ <&pd IMX_SC_R_DMA_2_CH12>, -+ <&pd IMX_SC_R_DMA_2_CH13>, -+ <&pd IMX_SC_R_DMA_2_CH14>, -+ <&pd IMX_SC_R_DMA_2_CH15>; -+ power-domain-names = "edma2-chan0", "edma2-chan1", -+ "edma2-chan2", "edma2-chan3", -+ "edma2-chan4", "edma2-chan5", -+ "edma2-chan6", "edma2-chan7", -+ "edma2-chan8", "edma2-chan9", -+ "edma2-chan10", "edma2-chan11", -+ "edma2-chan12", "edma2-chan13", -+ "edma2-chan14", "edma2-chan15"; -+ status = "disabled"; -+ }; -+ -+ spi0_lpcg: clock-controller@5a400000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a400000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "spi0_lpcg_clk", -+ "spi0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SPI_0>; -+ }; -+ -+ spi1_lpcg: clock-controller@5a410000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a410000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "spi1_lpcg_clk", -+ "spi1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SPI_1>; -+ }; -+ -+ spi2_lpcg: clock-controller@5a420000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a420000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "spi2_lpcg_clk", -+ "spi2_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SPI_2>; -+ }; -+ -+ spi3_lpcg: clock-controller@5a430000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a430000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "spi3_lpcg_clk", -+ "spi3_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SPI_3>; -+ }; -+ -+ uart0_lpcg: clock-controller@5a460000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a460000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "uart0_lpcg_baud_clk", -+ "uart0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_UART_0>; -+ }; -+ -+ uart1_lpcg: clock-controller@5a470000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a470000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "uart1_lpcg_baud_clk", -+ "uart1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_UART_1>; -+ }; -+ -+ uart2_lpcg: clock-controller@5a480000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a480000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "uart2_lpcg_baud_clk", -+ "uart2_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_UART_2>; -+ }; -+ -+ uart3_lpcg: clock-controller@5a490000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a490000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "uart3_lpcg_baud_clk", -+ "uart3_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_UART_3>; -+ }; -+ -+ emvsim0_lpcg: clock-controller@5a4d0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a4d0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "emvsim0_lpcg_clk", -+ "emvsim0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_EMVSIM_0>; -+ }; -+ -+ adc0: adc@5a880000 { -+ compatible = "fsl,imx8qxp-adc"; -+ reg = <0x5a880000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&adc0_lpcg 0>, -+ <&adc0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_ADC_0>; -+ status = "disabled"; -+ }; -+ -+ adc1: adc@5a890000 { -+ compatible = "fsl,imx8qxp-adc"; -+ reg = <0x5a890000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&adc1_lpcg 0>, -+ <&adc1_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_ADC_1>; -+ status = "disabled"; -+ }; -+ -+ -+ i2c0: i2c@5a800000 { -+ reg = <0x5a800000 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&i2c0_lpcg 0>, -+ <&i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@5a810000 { -+ reg = <0x5a810000 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&i2c1_lpcg 0>, -+ <&i2c1_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_I2C_1>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@5a820000 { -+ reg = <0x5a820000 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&i2c2_lpcg 0>, -+ <&i2c2_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_I2C_2>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@5a830000 { -+ reg = <0x5a830000 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&i2c3_lpcg 0>, -+ <&i2c3_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_I2C_3>; -+ status = "disabled"; -+ }; -+ -+ flexcan1: can@5a8d0000 { -+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; -+ reg = <0x5a8d0000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&can0_lpcg 1>, -+ <&can0_lpcg 0>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <40000000>; -+ power-domains = <&pd IMX_SC_R_CAN_0>; -+ /* SLSlice[4] */ -+ fsl,clk-source= <0>; -+ status = "disabled"; -+ }; -+ -+ flexcan2: can@5a8e0000 { -+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; -+ reg = <0x5a8e0000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ /* CAN0 clock and PD is shared among all CAN instances as -+ * CAN1 shares CAN0's clock and to enable CAN0's clock it -+ * has to be powered on. -+ */ -+ clocks = <&can0_lpcg 1>, -+ <&can0_lpcg 0>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <40000000>; -+ power-domains = <&pd IMX_SC_R_CAN_1>; -+ /* SLSlice[4] */ -+ fsl,clk-source = <0>; -+ status = "disabled"; -+ }; -+ -+ flexcan3: can@5a8f0000 { -+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; -+ reg = <0x5a8f0000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ /* CAN0 clock and PD is shared among all CAN instances as -+ * CAN2 shares CAN0's clock and to enable CAN0's clock it -+ * has to be powered on. -+ */ -+ clocks = <&can0_lpcg 1>, -+ <&can0_lpcg 0>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <40000000>; -+ power-domains = <&pd IMX_SC_R_CAN_2>; -+ /* SLSlice[4] */ -+ fsl,clk-source = <0>; -+ status = "disabled"; -+ }; -+ -+ adc0_lpcg: clock-controller@5ac80000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac80000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "adc0_lpcg_clk", -+ "adc0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ADC_0>; -+ }; -+ -+ adc1_lpcg: clock-controller@5ac90000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac90000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "adc1_lpcg_clk", -+ "adc1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ADC_1>; -+ }; -+ -+ i2c0_lpcg: clock-controller@5ac00000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac00000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "i2c0_lpcg_clk", -+ "i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_I2C_0>; -+ }; -+ -+ i2c1_lpcg: clock-controller@5ac10000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac10000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "i2c1_lpcg_clk", -+ "i2c1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_I2C_1>; -+ }; -+ -+ i2c2_lpcg: clock-controller@5ac20000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac20000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "i2c2_lpcg_clk", -+ "i2c2_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_I2C_2>; -+ }; -+ -+ i2c3_lpcg: clock-controller@5ac30000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac30000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "i2c3_lpcg_clk", -+ "i2c3_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_I2C_3>; -+ }; -+ -+ can0_lpcg: clock-controller@5acd0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5acd0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>, <&dma_ipg_clk>; -+ bit-offset = <0 16 20>; -+ clock-output-names = "can0_lpcg_pe_clk", -+ "can0_lpcg_ipg_clk", -+ "can0_lpcg_chi_clk"; -+ power-domains = <&pd IMX_SC_R_CAN_0>; -+ }; -+ -+ i2c_rpbus_0: i2c-rpbus-0 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_1: i2c-rpbus-1 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_5: i2c-rpbus-5 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_12: i2c-rpbus-12 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_13: i2c-rpbus-13 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_14: i2c-rpbus-14 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_15: i2c-rpbus-15 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ adma_pwm: pwm@5a190000 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+ reg = <0x5a190000 0x1000>; -+ clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ adma_pwm_lpcg: clock-controller@5a590000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a590000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "adma_pwm_lpcg_clk", -+ "adma_pwm_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi -new file mode 100644 -index 000000000..28aeeecb1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+gpu0_subsys: bus@53100000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x53100000 0x0 0x53100000 0x40000>, -+ <0x80000000 0x0 0x80000000 0x80000000>, -+ <0x0 0x0 0x0 0x10000000>; -+ -+ gpu_3d0: gpu@53100000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x53100000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; -+ clock-names = "core", "shader"; -+ assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; -+ assigned-clock-rates = <700000000>, <850000000>; -+ power-domains = <&pd IMX_SC_R_GPU_0_PID0>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi -new file mode 100644 -index 000000000..0e84e5199 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi -@@ -0,0 +1,31 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+gpu1_subsys: bus@54100000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x54100000 0x0 0x54100000 0x40000>, -+ <0x80000000 0x0 0x80000000 0x80000000>, -+ <0x0 0x0 0x0 0x10000000>; -+ -+ gpu_3d1: gpu@54100000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x54100000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; -+ clock-names = "core", "shader"; -+ assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; -+ assigned-clock-rates = <800000000>, <1000000000>; -+ fsl,sc_gpu_pid = ; -+ power-domains = <&pd IMX_SC_R_GPU_1_PID0>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi -new file mode 100644 -index 000000000..c6629e048 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi -@@ -0,0 +1,164 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Richard Zhu -+ */ -+#include -+ -+hsio_subsys: bus@5f000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */ -+ dma-ranges = <0x80000000 0 0x80000000 0x80000000>; -+ ranges = <0x5f000000 0x0 0x5f000000 0x21000000>; -+ -+ xtal100m: clock-xtal100m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "xtal_100MHz"; -+ }; -+ -+ hsio_refa_clk: clock-hsio-refa { -+ compatible = "gpio-gate-clock"; -+ clocks = <&xtal100m>; -+ #clock-cells = <0>; -+ enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; -+ }; -+ -+ hsio_refb_clk: clock-hsio-refb { -+ compatible = "gpio-gate-clock"; -+ clocks = <&xtal100m>; -+ #clock-cells = <0>; -+ enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ }; -+ -+ hsio_axi_clk: clock-hsio-axi { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ clock-output-names = "hsio_axi_clk"; -+ }; -+ -+ hsio_per_clk: clock-hsio-per { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133333333>; -+ clock-output-names = "hsio_per_clk"; -+ }; -+ -+ pcieb_lpcg: clock-controller@5f060000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f060000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; -+ bit-offset = <16 20 24>; -+ clock-output-names = "hsio_pcieb_mstr_axi_clk", -+ "hsio_pcieb_slv_axi_clk", -+ "hsio_pcieb_dbi_axi_clk"; -+ power-domains = <&pd IMX_SC_R_PCIE_B>; -+ }; -+ -+ phyx1_crr1_lpcg: clock-controller@5f0b0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f0b0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_per_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_phyx1_per_clk"; -+ power-domains = <&pd IMX_SC_R_SERDES_1>; -+ }; -+ -+ pcieb_crr3_lpcg: clock-controller@5f0d0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f0d0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_per_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_pcieb_per_clk"; -+ power-domains = <&pd IMX_SC_R_PCIE_B>; -+ }; -+ -+ misc_crr5_lpcg: clock-controller@5f0f0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f0f0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_per_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_misc_per_clk"; -+ power-domains = <&pd IMX_SC_R_HSIO_GPIO>; -+ }; -+ -+ pcieb: pcie@0x5f010000 { -+ compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; -+ reg = <0x5f010000 0x10000>, /* Controller reg */ -+ <0x7ff00000 0x80000>, /* PCI cfg space */ -+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ -+ reg-names = "dbi", "config", "hsio"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ -+ 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic 0 105 4>, -+ <0 0 0 2 &gic 0 106 4>, -+ <0 0 0 3 &gic 0 107 4>, -+ <0 0 0 4 &gic 0 108 4>; -+ clocks = <&pcieb_lpcg 0>, -+ <&pcieb_lpcg 1>, -+ <&pcieb_lpcg 2>, -+ <&phyx1_lpcg 0>, -+ <&phyx1_crr1_lpcg 0>, -+ <&pcieb_crr3_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "phy_per", "pcie_per", "misc_per"; -+ power-domains = <&pd IMX_SC_R_PCIE_B>, -+ <&pd IMX_SC_R_SERDES_1>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; -+ fsl,max-link-speed = <3>; -+ hsio-cfg = ; -+ local-addr = <0x80000000>; -+ status = "disabled"; -+ }; -+ -+ pcieb_ep: pcie_ep@0x5f010000 { -+ compatible = "fsl,imx8qxp-pcie-ep"; -+ reg = <0x5f010000 0x00010000>, -+ <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */ -+ <0x70000000 0x10000000>; -+ reg-names = "regs", "hsio", "addr_space"; -+ num-lanes = <1>; -+ interrupts = ; /* eDMA */ -+ interrupt-names = "dma"; -+ clocks = <&pcieb_lpcg 0>, -+ <&pcieb_lpcg 1>, -+ <&pcieb_lpcg 2>, -+ <&phyx1_lpcg 0>, -+ <&phyx1_crr1_lpcg 0>, -+ <&pcieb_crr3_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "phy_per", "pcie_per", "misc_per"; -+ power-domains = <&pd IMX_SC_R_PCIE_B>, -+ <&pd IMX_SC_R_SERDES_1>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; -+ fsl,max-link-speed = <3>; -+ hsio-cfg = ; -+ local-addr = <0x80000000>; -+ num-ib-windows = <6>; -+ num-ob-windows = <6>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi -new file mode 100644 -index 000000000..8962390ed ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi -@@ -0,0 +1,604 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019-2020 NXP -+ * Zhou Guoniu -+ */ -+img_subsys: bus@58000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x58000000 0x0 0x58000000 0x1000000>; -+ -+ img_ipg_clk: clock-img-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "img_ipg_clk"; -+ }; -+ -+ img_axi_clk: clock-img-axi { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ clock-output-names = "img_axi_clk"; -+ }; -+ -+ img_pxl_clk: clock-img-pxl { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <600000000>; -+ clock-output-names = "img_pxl_clk"; -+ }; -+ -+ csi0_core_lpcg: clock-controller@58223018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58223018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; -+ bit-offset = <16>; -+ clock-output-names = "csi0_lpcg_core_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ csi0_esc_lpcg: clock-controller@5822301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5822301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; -+ bit-offset = <16>; -+ clock-output-names = "csi0_lpcg_esc_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ csi1_core_lpcg: clock-controller@58243018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58243018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; -+ bit-offset = <16>; -+ clock-output-names = "csi1_lpcg_core_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ csi1_esc_lpcg: clock-controller@5824301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5824301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; -+ bit-offset = <16>; -+ clock-output-names = "csi1_lpcg_esc_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ pi0_pxl_lpcg: clock-controller@58263018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0>; -+ clock-output-names = "pi0_lpcg_pxl_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ pi0_ipg_lpcg: clock-controller@58263004 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263004 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; -+ bit-offset = <16>; -+ clock-output-names = "pi0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ pi0_misc_lpcg: clock-controller@5826301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5826301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; -+ bit-offset = <0>; -+ clock-output-names = "pi0_lpcg_misc_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ pdma0_lpcg: clock-controller@58500000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58500000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ }; -+ -+ pdma1_lpcg: clock-controller@58510000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58510000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH1>; -+ }; -+ -+ pdma2_lpcg: clock-controller@58520000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58520000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma2_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH2>; -+ }; -+ -+ pdma3_lpcg: clock-controller@58530000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58530000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma3_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH3>; -+ }; -+ -+ pdma4_lpcg: clock-controller@58540000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58540000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma4_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH4>; -+ }; -+ -+ pdma5_lpcg: clock-controller@58550000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58550000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma5_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH5>; -+ }; -+ -+ pdma6_lpcg: clock-controller@58560000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58560000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma6_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH6>; -+ }; -+ -+ pdma7_lpcg: clock-controller@58570000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58570000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "pdma7_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_ISI_CH7>; -+ }; -+ -+ csi0_pxl_lpcg: clock-controller@58580000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58580000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "csi0_lpcg_pxl_clk"; -+ power-domains = <&pd IMX_SC_R_CSI_0>; -+ }; -+ -+ csi1_pxl_lpcg: clock-controller@58590000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58590000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "csi1_lpcg_pxl_clk"; -+ power-domains = <&pd IMX_SC_R_CSI_1>; -+ }; -+ -+ hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x585a0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_pxl_clk>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_pxl_link_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ }; -+ -+ img_jpeg_dec_clk: clock-controller@585d0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x585d0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_ipg_clk>, <&img_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "img_jpeg_dec_clk", -+ "img_jpeg_dec_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; -+ }; -+ -+ img_jpeg_enc_clk: clock-controller@585f0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x585f0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&img_ipg_clk>, <&img_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "img_jpeg_enc_clk", -+ "img_jpeg_enc_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; -+ }; -+ -+ irqsteer_csi0: irqsteer@58220000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x58220000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ clocks = <&img_ipg_clk>; -+ clock-names = "ipg"; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_csi", "pd_isi_ch0"; -+ status = "disabled"; -+ }; -+ -+ irqsteer_csi1: irqsteer@58240000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x58240000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ clocks = <&img_ipg_clk>; -+ clock-names = "ipg"; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_csi", "pd_isi_ch0"; -+ status = "disabled"; -+ }; -+ -+ irqsteer_parallel: irqsteer@58260000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x58260000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ clocks = <&clk_dummy>; -+ clock-names = "ipg"; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_pi", "pd_isi_ch0"; -+ status = "disabled"; -+ }; -+ -+ gpio0_mipi_csi0: gpio@58222000 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+ reg = <0x58222000 0x1000>; -+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_csi0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_csi", "pd_isi_ch0"; -+ }; -+ -+ i2c_mipi_csi0: i2c@58226000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x58226000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_csi0>; -+ clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&img_ipg_clk>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ i2c0_parallel: i2c@58266000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x58266000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_parallel>; -+ clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&img_ipg_clk>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ gpio0_mipi_csi1: gpio@58242000 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+ reg = <0x58242000 0x1000>; -+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_csi1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_csi", "pd_isi_ch0"; -+ }; -+ -+ i2c_mipi_csi1: i2c@58246000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x58246000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_csi1>; -+ clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&img_ipg_clk>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ cameradev: camera { -+ compatible = "fsl,mxc-md", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ isi_0: isi@58100000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58100000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma0_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>; -+ interface = <2 0 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ -+ m2m_device{ -+ compatible = "imx-isi-m2m"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_1: isi@58110000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58110000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma1_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH1>; -+ interface = <2 1 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_2: isi@58120000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58120000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma2_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH2>; -+ interface = <2 2 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_3: isi@58130000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58130000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma3_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH3>; -+ interface = <2 3 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_4: isi@58140000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58140000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma4_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH4>; -+ interface = <3 0 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_5: isi@58150000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58150000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma5_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH5>; -+ interface = <3 1 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_6: isi@58160000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58160000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma6_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH6>; -+ interface = <3 2 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_7: isi@58170000 { -+ compatible = "fsl,imx8-isi"; -+ reg = <0x58170000 0x10000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&pdma7_lpcg 0>; -+ clock-names = "per"; -+ power-domains = <&pd IMX_SC_R_ISI_CH7>; -+ interface = <3 3 2>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ mipi_csi_0: csi@58227000 { -+ compatible = "fsl,mxc-mipi-csi2"; -+ reg = <0x58227000 0x1000>, -+ <0x58221000 0x1000>; -+ clocks = <&csi0_core_lpcg 0>, -+ <&csi0_esc_lpcg 0>, -+ <&csi0_pxl_lpcg 0>; -+ clock-names = "clk_core", "clk_esc", "clk_pxl"; -+ assigned-clocks = <&csi0_core_lpcg 0>, -+ <&csi0_esc_lpcg 0>; -+ assigned-clock-rates = <360000000>, <72000000>; -+ power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_csi", "pd_isi_ch0"; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: csi@58247000{ -+ compatible = "fsl,mxc-mipi-csi2"; -+ reg = <0x58247000 0x1000>, -+ <0x58241000 0x1000>; -+ clocks = <&csi1_core_lpcg 0>, -+ <&csi1_esc_lpcg 0>, -+ <&csi1_pxl_lpcg 0>; -+ clock-names = "clk_core", "clk_esc", "clk_pxl"; -+ assigned-clocks = <&csi1_core_lpcg 0>, -+ <&csi1_esc_lpcg 0>; -+ assigned-clock-rates = <360000000>, <72000000>; -+ power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_csi", "pd_isi_ch0"; -+ status = "disabled"; -+ }; -+ -+ parallel_csi: pcsi@58261000 { -+ compatible = "fsl,mxc-parallel-csi"; -+ reg = <0x58261000 0x1000>; -+ clocks = <&pi0_pxl_lpcg 0>, -+ <&pi0_ipg_lpcg 0>, -+ <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; -+ clock-names = "pixel", "ipg", "div", "dpll"; -+ assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; -+ assigned-clock-rates = <160000000>; /* 160MHz */ -+ power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; -+ power-domain-names = "pd_pi", "pd_isi_ch0"; -+ status = "disabled"; -+ }; -+ -+ jpegdec: jpegdec@58400000 { -+ compatible = "fsl,imx8-jpgdec"; -+ reg = <0x58400000 0x00050000 >; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&img_jpeg_dec_clk 0>, -+ <&img_jpeg_dec_clk 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&img_jpeg_dec_clk 0>, -+ <&img_jpeg_dec_clk 1>; -+ assigned-clock-rates = <200000000>; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>, -+ <&pd IMX_SC_R_MJPEG_DEC_MP>, -+ <&pd IMX_SC_R_MJPEG_DEC_S0>, -+ <&pd IMX_SC_R_MJPEG_DEC_S1>, -+ <&pd IMX_SC_R_MJPEG_DEC_S2>, -+ <&pd IMX_SC_R_MJPEG_DEC_S3>; -+ power-domain-names = "pd_isi_ch0", "pd_dec_mp", -+ "pd_dec_s0", "pd_dec_s1", -+ "pd_dec_s2", "pd_dec_s3"; -+ status = "disabled"; -+ }; -+ -+ jpegenc: jpegenc@58450000 { -+ compatible = "fsl,imx8-jpgenc"; -+ reg = <0x58450000 0x00050000 >; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&img_jpeg_enc_clk 0>, -+ <&img_jpeg_enc_clk 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&img_jpeg_enc_clk 0>, -+ <&img_jpeg_enc_clk 1>; -+ assigned-clock-rates = <200000000>; -+ power-domains = <&pd IMX_SC_R_ISI_CH0>, -+ <&pd IMX_SC_R_MJPEG_ENC_MP>, -+ <&pd IMX_SC_R_MJPEG_ENC_S0>, -+ <&pd IMX_SC_R_MJPEG_ENC_S1>, -+ <&pd IMX_SC_R_MJPEG_ENC_S2>, -+ <&pd IMX_SC_R_MJPEG_ENC_S3>; -+ power-domain-names = "pd_isi_ch0", "pd_enc_mp", -+ "pd_enc_s0", "pd_enc_s1", -+ "pd_enc_s2", "pd_enc_s3"; -+ status = "disabled"; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi -new file mode 100644 -index 000000000..4bf058106 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi -@@ -0,0 +1,48 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+lcdif_subsys: bus@5a180000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5a180000 0x0 0x5a180000 0x500000>; -+ -+ ipg_dma_clk: clock-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <120000000>; -+ clock-output-names = "ipg_dma_clk"; -+ }; -+ -+ lcd_clk_lpcg: clock-controller@5a580000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a580000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, -+ <&ipg_dma_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LCD_0>; -+ }; -+ -+ adma_lcdif: lcdif@5a180000 { -+ compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; -+ reg = <0x5a180000 0x10000>; -+ clocks = <&lcd_clk_lpcg 0>, -+ <&lcd_clk_lpcg 1>, -+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; -+ clock-names = "pix", "axi", "disp_axi"; -+ assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; -+ assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; -+ assigned-clock-rates = <0>, <24000000>, <804000000>; -+ interrupts = ; -+ power-domains = <&pd IMX_SC_R_LCD_0>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi -new file mode 100644 -index 000000000..83bb00300 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi -@@ -0,0 +1,367 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+ -+lsio_subsys: bus@5d000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, -+ <0x08000000 0x0 0x08000000 0x10000000>; -+ -+ lsio_mem_clk: clock-lsio-mem { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "lsio_mem_clk"; -+ }; -+ -+ lsio_bus_clk: clock-lsio-bus { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "lsio_bus_clk"; -+ }; -+ -+ pwm0: pwm@5d000000 { -+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; -+ reg = <0x5d000000 0x10000>; -+ clock-names = "ipg", "per"; -+ clocks = <&pwm0_lpcg 4>, -+ <&pwm0_lpcg 1>; -+ assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@5d010000 { -+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; -+ reg = <0x5d010000 0x10000>; -+ clock-names = "ipg", "per"; -+ clocks = <&pwm1_lpcg 4>, -+ <&pwm1_lpcg 1>; -+ assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@5d020000 { -+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; -+ reg = <0x5d020000 0x10000>; -+ clock-names = "ipg", "per"; -+ clocks = <&pwm2_lpcg 4>, -+ <&pwm2_lpcg 1>; -+ assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@5d030000 { -+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; -+ reg = <0x5d030000 0x10000>; -+ clock-names = "ipg", "per"; -+ clocks = <&pwm3_lpcg 4>, -+ <&pwm3_lpcg 1>; -+ assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ lsio_gpio0: gpio@5d080000 { -+ reg = <0x5d080000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_0>; -+ }; -+ -+ lsio_gpio1: gpio@5d090000 { -+ reg = <0x5d090000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_1>; -+ }; -+ -+ lsio_gpio2: gpio@5d0a0000 { -+ reg = <0x5d0a0000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_2>; -+ }; -+ -+ lsio_gpio3: gpio@5d0b0000 { -+ reg = <0x5d0b0000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_3>; -+ }; -+ -+ lsio_gpio4: gpio@5d0c0000 { -+ reg = <0x5d0c0000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_4>; -+ }; -+ -+ lsio_gpio5: gpio@5d0d0000 { -+ reg = <0x5d0d0000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_5>; -+ }; -+ -+ lsio_gpio6: gpio@5d0e0000 { -+ reg = <0x5d0e0000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_6>; -+ }; -+ -+ lsio_gpio7: gpio@5d0f0000 { -+ reg = <0x5d0f0000 0x10000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ power-domains = <&pd IMX_SC_R_GPIO_7>; -+ }; -+ -+ flexspi0: spi@5d120000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8qxp-fspi"; -+ reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; -+ clock-names = "fspi", "fspi_en"; -+ power-domains = <&pd IMX_SC_R_FSPI_0>; -+ status = "disabled"; -+ }; -+ -+ lsio_mu0: mailbox@5d1b0000 { -+ reg = <0x5d1b0000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ lsio_mu1: mailbox@5d1c0000 { -+ reg = <0x5d1c0000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ }; -+ -+ lsio_mu2: mailbox@5d1d0000 { -+ reg = <0x5d1d0000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ lsio_mu3: mailbox@5d1e0000 { -+ reg = <0x5d1e0000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ lsio_mu4: mailbox@5d1f0000 { -+ reg = <0x5d1f0000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ lsio_mu5: mailbox@5d200000 { -+ compatible = "fsl,imx6sx-mu"; -+ reg = <0x5d200000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_MU_5A>; -+ }; -+ -+ lsio_mu13: mailbox@5d280000 { -+ compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; -+ reg = <0x5d280000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_MU_13A>; -+ fsl,dsp_ap_mu_id = <13>; -+ }; -+ -+ /* LPCG clocks */ -+ pwm0_lpcg: clock-controller@5d400000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d400000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm0_lpcg_ipg_clk", -+ "pwm0_lpcg_ipg_hf_clk", -+ "pwm0_lpcg_ipg_s_clk", -+ "pwm0_lpcg_ipg_slv_clk", -+ "pwm0_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_0>; -+ }; -+ -+ pwm1_lpcg: clock-controller@5d410000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d410000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm1_lpcg_ipg_clk", -+ "pwm1_lpcg_ipg_hf_clk", -+ "pwm1_lpcg_ipg_s_clk", -+ "pwm1_lpcg_ipg_slv_clk", -+ "pwm1_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_1>; -+ }; -+ -+ pwm2_lpcg: clock-controller@5d420000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d420000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm2_lpcg_ipg_clk", -+ "pwm2_lpcg_ipg_hf_clk", -+ "pwm2_lpcg_ipg_s_clk", -+ "pwm2_lpcg_ipg_slv_clk", -+ "pwm2_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_2>; -+ }; -+ -+ pwm3_lpcg: clock-controller@5d430000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d430000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm3_lpcg_ipg_clk", -+ "pwm3_lpcg_ipg_hf_clk", -+ "pwm3_lpcg_ipg_s_clk", -+ "pwm3_lpcg_ipg_slv_clk", -+ "pwm3_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_3>; -+ }; -+ -+ pwm4_lpcg: clock-controller@5d440000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d440000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm4_lpcg_ipg_clk", -+ "pwm4_lpcg_ipg_hf_clk", -+ "pwm4_lpcg_ipg_s_clk", -+ "pwm4_lpcg_ipg_slv_clk", -+ "pwm4_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_4>; -+ }; -+ -+ pwm5_lpcg: clock-controller@5d450000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d450000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm5_lpcg_ipg_clk", -+ "pwm5_lpcg_ipg_hf_clk", -+ "pwm5_lpcg_ipg_s_clk", -+ "pwm5_lpcg_ipg_slv_clk", -+ "pwm5_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_5>; -+ }; -+ -+ pwm6_lpcg: clock-controller@5d460000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d460000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm6_lpcg_ipg_clk", -+ "pwm6_lpcg_ipg_hf_clk", -+ "pwm6_lpcg_ipg_s_clk", -+ "pwm6_lpcg_ipg_slv_clk", -+ "pwm6_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_6>; -+ }; -+ -+ pwm7_lpcg: clock-controller@5d470000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5d470000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, -+ <&lsio_bus_clk>, -+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; -+ bit-offset = <0 4 16 20 24>; -+ clock-output-names = "pwm7_lpcg_ipg_clk", -+ "pwm7_lpcg_ipg_hf_clk", -+ "pwm7_lpcg_ipg_s_clk", -+ "pwm7_lpcg_ipg_slv_clk", -+ "pwm7_lpcg_ipg_mstr_clk"; -+ power-domains = <&pd IMX_SC_R_PWM_7>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi -new file mode 100644 -index 000000000..57734ed8a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi -@@ -0,0 +1,106 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include -+ -+security_subsys: bus@31400000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x31400000 0x0 0x31400000 0x410000>; -+ -+ crypto: crypto@31400000 { -+ compatible = "fsl,sec-v4.0"; -+ reg = <0x31400000 0x90000>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x31400000 0x90000>; -+ fsl,sec-era = <9>; -+ power-domains = <&pd IMX_SC_R_CAAM_JR2>; -+ power-domain-names = "jr"; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = ; -+ power-domains = <&pd IMX_SC_R_CAAM_JR2>; -+ power-domain-names = "jr"; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = ; -+ power-domains = <&pd IMX_SC_R_CAAM_JR3>; -+ power-domain-names = "jr"; -+ }; -+ }; -+ -+ caam_sm: caam-sm@31800000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x31800000 0x10000>; -+ }; -+ -+ sec_mu2: mu@31560000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x31560000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_SECO_MU_2>; -+ status = "okay"; -+ }; -+ -+ sec_mu3: mu@31570000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x31570000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_SECO_MU_3>; -+ status = "okay"; -+ }; -+ -+ sec_mu4: mu@31580000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x31580000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_SECO_MU_4>; -+ status = "okay"; -+ }; -+}; -+ -+seco_mu1: seco_mu1 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&sec_mu2 2 0 -+ &sec_mu2 3 0>; -+ -+ fsl,seco_mu_id = <1>; -+ fsl,seco_max_users = <4>; -+ status = "okay"; -+}; -+ -+seco_mu2: seco_mu2 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&sec_mu3 2 0 -+ &sec_mu3 3 0>; -+ -+ fsl,seco_mu_id = <2>; -+ fsl,seco_max_users = <4>; -+ status = "okay"; -+}; -+ -+seco_mu3: seco_mu3 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&sec_mu4 2 0 -+ &sec_mu4 3 0>; -+ -+ fsl,seco_mu_id = <3>; -+ fsl,seco_max_users = <4>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi -new file mode 100644 -index 000000000..5ee8c6a26 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include -+ -+v2x_subsys: bus@2C000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x2c000000 0x0 0x2c000000 0x50000>; -+ -+ v2x_sv0: mu@2C000000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x2c000000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_V2X_MU_0>; -+ status = "okay"; -+ }; -+ v2x_sv1: mu@2c010000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x2c010000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_V2X_MU_1>; -+ status = "okay"; -+ }; -+ v2x_she: mu@2c020000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x2c020000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_V2X_MU_2>; -+ status = "okay"; -+ }; -+ v2x_sg0: mu@2c030000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x2c030000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_V2X_MU_3>; -+ status = "okay"; -+ }; -+ v2x_sg1: mu@2c040000 { -+ compatible = "fsl,imx8-mu-seco"; -+ reg = <0x2c040000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_V2X_MU_4>; -+ status = "okay"; -+ }; -+}; -+ -+v2x_mu_sv0: v2x_mu_sv0 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&v2x_sv0 2 0 -+ &v2x_sv0 3 0>; -+ -+ fsl,seco_mu_id = <4>; -+ fsl,seco_max_users = <2>; -+ fsl,cmd_tag = /bits/ 8 <0x18>; -+ fsl,rsp_tag = /bits/ 8 <0xe2>; -+ status = "okay"; -+}; -+v2x_mu_sv1: v2x_mu_sv1 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&v2x_sv1 2 0 -+ &v2x_sv1 3 0>; -+ -+ fsl,seco_mu_id = <5>; -+ fsl,seco_max_users = <2>; -+ fsl,cmd_tag = /bits/ 8 <0x19>; -+ fsl,rsp_tag = /bits/ 8 <0xe3>; -+ status = "okay"; -+}; -+v2x_mu_she: v2x_mu_she { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&v2x_she 2 0 -+ &v2x_she 3 0>; -+ -+ fsl,seco_mu_id = <6>; -+ fsl,seco_max_users = <2>; -+ fsl,cmd_tag = /bits/ 8 <0x1a>; -+ fsl,rsp_tag = /bits/ 8 <0xe4>; -+ status = "okay"; -+}; -+v2x_mu_sg0: v2x_mu_sg0 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&v2x_sg0 2 0 -+ &v2x_sg0 3 0>; -+ -+ fsl,seco_mu_id = <7>; -+ fsl,seco_max_users = <2>; -+ fsl,cmd_tag = /bits/ 8 <0x1d>; -+ fsl,rsp_tag = /bits/ 8 <0xe7>; -+ status = "okay"; -+}; -+v2x_mu_sg1: v2x_mu_sg1 { -+ compatible = "fsl,imx-seco-mu"; -+ mbox-names = "txdb", "rxdb"; -+ mboxes = <&v2x_sg1 2 0 -+ &v2x_sg1 3 0>; -+ -+ fsl,seco_mu_id = <8>; -+ fsl,seco_max_users = <2>; -+ fsl,cmd_tag = /bits/ 8 <0x1e>; -+ fsl,rsp_tag = /bits/ 8 <0xe8>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi -new file mode 100755 -index 000000000..96787fb70 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi -@@ -0,0 +1,81 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+vpu_subsys: bus@2c000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; -+ -+ vpu_lpcg: clock-controller@2d000000 { -+ compatible = "fsl,imx8qxp-lpcg-vpu"; -+ reg = <0x2c000000 0x2000000>; -+ #clock-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ vpu_decoder: vpu_decoder@2c000000 { -+ compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; -+ reg = <0x2c000000 0x1000000>; -+ reg-names = "vpu_regs"; -+ power-domains = <&pd IMX_SC_R_VPU_DEC_0>, -+ <&pd IMX_SC_R_VPU>; -+ power-domain-names = "vpudec", "vpu"; -+ -+ mbox-names = "tx0", "tx1", "rx"; -+ mboxes = <&mu_m0 0 0 -+ &mu_m0 0 1 -+ &mu_m0 1 0>; -+ -+ status = "disabled"; -+ }; -+ -+ vpu_encoder: vpu_encoder@2d000000 { -+ compatible = "nxp,imx8qxp-b0-vpuenc"; -+ reg = <0x2d000000 0x1000000>, /*VPU Encoder*/ -+ <0x2c000000 0x2000000>; /*VPU*/ -+ reg-names = "vpu_regs"; -+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>, -+ <&pd IMX_SC_R_VPU>; -+ power-domain-names = "vpuenc1", "vpu"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ mu_m0: mailbox@2d000000 { -+ compatible = "fsl,imx8-mu0-vpu-m0", "fsl,imx6sx-mu"; -+ reg = <0x2d000000 0x20000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_VPU_MU_0>; -+ power-domain-names = "vpumu0"; -+ fsl,vpu_ap_mu_id = <16>; -+ status = "okay"; -+ }; -+ -+ mu1_m0: mailbox@2d020000 { -+ compatible = "fsl,imx8-mu1-vpu-m0", "fsl,imx6sx-mu"; -+ reg = <0x2d020000 0x20000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <17>; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_VPU_MU_1>; -+ power-domain-names = "vpumu1"; -+ status = "okay"; -+ }; -+ -+ mu2_m0: mailbox@2d040000 { -+ compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu"; -+ reg = <0x2d040000 0x20000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <18>; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_VPU_MU_2>; -+ power-domain-names = "vpumu2"; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts -new file mode 100644 -index 000000000..ad663b270 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dm.dtsi" -+#include "imx8q-val.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DM Validation Board"; -+ compatible = "fsl,imx8dm-val", "fsl,imx8dm", "fsl,imx8qm"; -+}; -+ -+&gpu_3d1 { -+ status = "disabled"; -+}; -+ -+&dc1_prg1 { -+ status = "disabled"; -+}; -+ -+&dc1_prg2 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dm.dtsi b/arch/arm64/boot/dts/freescale/imx8dm.dtsi -new file mode 100644 -index 000000000..23cbfb330 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dm.dtsi -@@ -0,0 +1,35 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8qm.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DM"; -+ compatible = "fsl, imx8dm", "fsl,imx8qm"; -+ -+}; -+ -+&thermal_zones { -+ /delete-node/ cpu-thermal0; -+ -+ pmic-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&cpus { -+ /delete-node/ cpu-map; -+ /delete-node/ cpu@0; -+ /delete-node/ cpu@1; -+ /delete-node/ cpu@2; -+ /delete-node/ cpu@3; -+ /delete-node/ l2-cache0; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts -new file mode 100644 -index 000000000..8fff0b531 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts -@@ -0,0 +1,15 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dx.dtsi" -+#include "imx8x-17x17-val.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DX 17x17 Validation Board"; -+ compatible = "fsl,imx8dx-17x17-val", "fsl,imx8dx", "fsl,imx8qxp"; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts -new file mode 100644 -index 000000000..0556fd01b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts -@@ -0,0 +1,15 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dx.dtsi" -+#include "imx8x-val.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DX VALIDATION"; -+ compatible = "fsl,imx8dx-val", "fsl,imx8dx", "fsl,imx8qxp"; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts -new file mode 100644 -index 000000000..7696e3dc7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek-dsi-rm67191.dts" -+#include "imx8x-mek-rpmsg.dtsi" -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts -new file mode 100644 -index 000000000..3157b4720 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dx-mek.dts" -+ -+/delete-node/ &adv_bridge0; -+/delete-node/ &adv_bridge1; -+ -+&ldb1_phy { -+ status = "disabled"; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -+ -+&ldb2_phy { -+ status = "disabled"; -+}; -+ -+&ldb2 { -+ status = "disabled"; -+}; -+ -+&lvds_bridge0 { -+ status = "disabled"; -+}; -+ -+&lvds_bridge1 { -+ status = "disabled"; -+}; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ -+ panel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ -+ port@0 { -+ reg = <0>; -+ panel0_in: endpoint { -+ remote-endpoint = <&mipi0_panel_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ mipi0_panel_out: endpoint { -+ remote-endpoint = <&panel0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ -+ panel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ -+ port@0 { -+ reg = <0>; -+ panel1_in: endpoint { -+ remote-endpoint = <&mipi1_panel_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ mipi1_panel_out: endpoint { -+ remote-endpoint = <&panel1_in>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts -new file mode 100644 -index 000000000..67e9ba641 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts -@@ -0,0 +1,15 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek.dts" -+#include "imx8qxp-enet2-tja1100.dtsi" -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&fec2 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts -new file mode 100644 -index 000000000..6dde34436 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek-rpmsg.dts" -+#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts -new file mode 100644 -index 000000000..511d32784 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek.dts" -+#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts -new file mode 100644 -index 000000000..e81c9510c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek-rpmsg.dts" -+#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts -new file mode 100644 -index 000000000..b05ee54a3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek.dts" -+#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts -new file mode 100644 -index 000000000..88d31032b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek-rpmsg.dts" -+#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts -new file mode 100644 -index 000000000..9ad1f1ed3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek.dts" -+#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts -new file mode 100644 -index 000000000..631ab3719 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek-rpmsg.dts" -+#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts -new file mode 100644 -index 000000000..4349fc034 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek.dts" -+#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts -new file mode 100644 -index 000000000..e0271bc7c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts -@@ -0,0 +1,4 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2020 -+#include "imx8dx-mek-ov5640.dts" -+#include "imx8x-mek-rpmsg.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts -new file mode 100644 -index 000000000..62fa5eae3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts -@@ -0,0 +1,71 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2020 -+ -+#include "imx8dx-mek.dts" -+ -+&isi_1 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_2 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_3 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ /delete-property/virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_ep>; -+ data-lanes = <1 2>; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi0 { -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&xtal24m>; -+ clock-names = "xclk"; -+ csi_id = <0>; -+ powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ port { -+ ov5640_mipi_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2>; -+ clocks-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ /delete-node/max9286_mipi@6a; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts -new file mode 100644 -index 000000000..a219f1632 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dx-mek.dts" -+#include "imx8x-mek-rpmsg.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts -new file mode 100644 -index 000000000..807d8cdc9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts -@@ -0,0 +1,48 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+#include "imx8dx.dtsi" -+#include "imx8x-mek.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DX MEK"; -+ compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp"; -+ -+ reserved-memory { -+/* -+ * Memory reserved for optee usage. Please do not use. -+ * This will be automaticky added to dtb if OP-TEE is installed. -+ * optee@96000000 { -+ * reg = <0 0x96000000 0 0x2000000>; -+ * no-map; -+ * }; -+ */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x14000000>; -+ alloc-ranges = <0 0x98000000 0 0x14000000>; -+ linux,cma-default; -+ }; -+ }; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&imx8_gpu_ss { -+ reg = <0x80000000 0x40000000>, <0x0 0x08000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dx.dtsi b/arch/arm64/boot/dts/freescale/imx8dx.dtsi -new file mode 100644 -index 000000000..05a7f593e ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dx.dtsi -@@ -0,0 +1,13 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxp.dtsi" -+ -+&gpu_3d0 { -+ assigned-clock-rates = <372000000>, <372000000>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk-rpmsg.dts -new file mode 100644 -index 000000000..242e2c795 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk-rpmsg.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl-ddr3-evk.dts" -+ -+&imx8dxl_cm4 { -+ /* Assume you have partitioned M4, so M4 is not controled by Linux */ -+ /delete-property/ power-domains; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ status = "disabled"; -+}; -+ -+&flexcan3 { -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ status = "disabled"; -+}; -+ -+&cm40_lpuart { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts -new file mode 100644 -index 000000000..4a9b73821 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-evk.dts -@@ -0,0 +1,919 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DXL DDR3 EVK"; -+ compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; -+ -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x20000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@90000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@90008000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90008000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring0: vdev1vring0@90010000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90010000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring1: vdev1vring1@90018000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90018000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90400000 0 0x100000>; -+ no-map; -+ }; -+ -+/* -+ * Memory reserved for optee usage. Please do not use. -+ * This will be automaticky added to dtb if OP-TEE is installed. -+ * optee@96000000 { -+ * reg = <0 0x96000000 0 0x2000000>; -+ * no-map; -+ * }; -+ */ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x8000000>; -+ alloc-ranges = <0 0x98000000 0 0x8000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ reg_can0_stby: regulator-can0-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can0-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can1_stby: regulator-can1-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can1-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ off-on-delay-us = <3480>; -+ }; -+ -+ reg_vref_1v8: regulator-adc-vref { -+ compatible = "regulator-fixed"; -+ regulator-name = "vref_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&wm8960_1>; -+ audio-asrc = <&asrc0>; -+ hp-det-gpio = <&pca6416_2 11 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ sound-wm8960-2 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio-2"; -+ audio-cpu = <&sai2>; -+ audio-codec = <&wm8960_2>; -+ capture-only; -+ hp-det-gpio = <&pca6416_2 12 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ sound-wm8960-3 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio-3"; -+ audio-cpu = <&sai3>; -+ audio-codec = <&wm8960_3>; -+ capture-only; -+ hp-det-gpio = <&pca6416_2 13 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ sound-wm8960-4 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio-4"; -+ audio-cpu = <&sai0>; -+ audio-codec = <&wm8960_4>; -+ hp-det-gpio = <&pca6416_2 10 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+}; -+ -+&adc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_adc>; -+ vref-supply = <®_vref_1v8>; -+ status = "okay"; -+}; -+ -+&edma2 { -+ status = "okay"; -+}; -+ -+&eqos { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_eqos>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; -+ snps,reset-delays-us = <10 20 200000>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ eee-broken-1000t; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; -+ phy-reset-duration = <10>; -+ phy-reset-post-delay = <150>; -+ status = "disabled"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can0_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can1_stby>; -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ mt35xu512aba0: flash@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand_1>; -+ status = "okay"; -+ nand-on-flash-bbt; -+ fsl,max-nand-cs = <1>; -+}; -+ -+&i2c2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pca6416_1: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca6416_2: gpio@21 { -+ compatible = "ti,tca6416"; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&lsio_gpio2>; -+ interrupts = <5 IRQ_TYPE_EDGE_BOTH>; -+ }; -+ -+ pca9548_1: pca9548@70 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x70>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ status = "disabled"; -+ }; -+ }; -+ -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; -+ -+ wm8960_1: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ wm8960_2: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ wm8960_3: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x4>; -+ -+ wm8960_4: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x5>; -+ }; -+ -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x6>; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ pca6416_3: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9548_2: pca9548@70 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x70>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; -+ }; -+ -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x4>; -+ }; -+ }; -+}; -+ -+&lpspi3 { -+ fsl,spi-num-chipselects = <1>; -+ fsl,spi-only-use-cs1-sel; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi3>; -+ pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <30000000>; -+ }; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-1 = <&pinctrl_lpuart1>; -+ status = "okay"; -+}; -+ -+&lsio_gpio4 { -+ status = "okay"; -+}; -+ -+&lsio_gpio5 { -+ status = "okay"; -+}; -+ -+&pcieb{ -+ compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ status = "disabled"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&sai0 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai0>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ status = "okay"; -+}; -+ -+&sai2 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai2_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&sai3 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai3_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; -+ max-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usbotg2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg2>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c -+ IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c -+ >; -+ }; -+ -+ pinctrl_adc: adcgrp{ -+ fsl,pins = < -+ IMX8DXL_ADC_IN0_ADMA_ADC_IN0 0x06000021 -+ IMX8DXL_ADC_IN1_ADMA_ADC_IN1 0x06000021 -+ IMX8DXL_ADC_IN4_ADMA_ADC_IN4 0x06000021 -+ IMX8DXL_ADC_IN5_ADMA_ADC_IN5 0x06000021 -+ >; -+ }; -+ -+ pinctrl_eqos: eqosgrp { -+ fsl,pins = < -+ IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 -+ IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 -+ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 -+ IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan2grp { -+ fsl,pins = < -+ IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 -+ IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 -+ IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpmi_nand_1: gpmi-nand-1 { -+ fsl,pins = < -+ IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c -+ IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c -+ IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c -+ IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c -+ IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c -+ IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c -+ IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c -+ IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c -+ IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c -+ IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c -+ IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c -+ IMX8DXL_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c -+ -+ IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c -+ IMX8DXL_USDHC1_WP_CONN_NAND_ALE 0x0e00004c -+ IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c -+ >; -+ }; -+ -+ pinctrl_lpspi3: lpspi3grp { -+ fsl,pins = < -+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 -+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 -+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 -+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 -+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 -+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c -+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x0600004c -+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x0600004c -+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600004c -+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600004c -+ >; -+ }; -+ -+ -+ pinctrl_pcieb: pcieagrp{ -+ fsl,pins = < -+ IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 -+ IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 -+ IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 -+ >; -+ }; -+ pinctrl_sai0: sai0grp { -+ fsl,pins = < -+ IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 -+ IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 -+ IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 -+ IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 -+ IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 -+ IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 -+ IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_sai2: sai2grp { -+ fsl,pins = < -+ IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 -+ IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 -+ IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 -+ IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 -+ IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ -+ IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ -+ IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usbotg1: otg1 { -+ fsl,pins = < -+ IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usbotg2: otg2 { -+ fsl,pins = < -+ IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 -+ >; -+ }; -+}; -+ -+&imx8dxl_cm4 { -+ memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, -+ <&vdev1vring0>, <&vdev1vring1>; -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts -new file mode 100644 -index 000000000..b1de12136 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dxl-evk-enet0.dts" -+ -+ðphy1 { -+ status = "disabled"; -+}; -+ -+&fec1 { -+ pinctrl-0 = <&pinctrl_fec1_rmii>; -+ clocks = <&enet0_lpcg 4>, -+ <&enet0_lpcg 2>, -+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, -+ <&enet0_lpcg 0>, -+ <&enet0_lpcg 1>; -+ phy-mode = "rmii"; -+ phy-handle = <ðphy2>; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <2>; -+ tja110x,refclk_in; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_fec1_rmii: fec1rmiigrp { -+ fsl,pins = < -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000060 -+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000060 -+ >; -+ }; -+}; -+ -+&max7322 { -+ status = "disabled"; -+}; -+ -+®_fec1_io { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts -new file mode 100644 -index 000000000..9f4d94ec6 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts -@@ -0,0 +1,36 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl-evk.dts" -+ -+®_fec1_sel { -+ status = "okay"; -+}; -+ -+®_fec1_io { -+ status = "okay"; -+}; -+ -+&mii_select { -+ /delete-property/ enable-active-high; -+}; -+ -+&eqos { -+ status = "disabled"; -+}; -+ -+&fec1 { -+ status = "okay"; -+}; -+ -+&max7322 { -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-inmate.dts -new file mode 100644 -index 000000000..75a546eb0 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-inmate.dts -@@ -0,0 +1,255 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ model = "Freescale i.MX8DXL EVK"; -+ compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; -+ interrupt-parent = <&gic>; -+ #address-cells = <0x2>; -+ #size-cells = <0x2>; -+ -+ aliases { -+ mmc0 = &usdhc1; -+ serial4 = &cm40_lpuart; -+ }; -+ -+ cpus { -+ #address-cells = <0x2>; -+ #size-cells = <0x0>; -+ -+ cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x1>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", "tx1", "tx2", "tx3", -+ "rx0", "rx1", "rx2", "rx3", -+ "gip3"; -+ mboxes = <&lsio_mu2 0 0 -+ &lsio_mu2 0 1 -+ &lsio_mu2 0 2 -+ &lsio_mu2 0 3 -+ &lsio_mu2 1 0 -+ &lsio_mu2 1 1 -+ &lsio_mu2 1 2 -+ &lsio_mu2 1 3 -+ &lsio_mu2 3 3>; -+ -+ pd: imx8dxl-pd { -+ compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8dxl-iomuxc"; -+ }; -+ }; -+ -+ soc { -+ compatible = "fsl,imx8qxp-soc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ pci@bf700000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xbf700000 0x0 0x00100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ /* For early console */ -+ serial@5a060000 { -+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx7ulp-lpuart"; -+ reg = <0x0 0x5a060000 0x0 0x1000>; -+ }; -+ -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-cm40.dtsi" -+}; -+ -+#include "imx8dxl-ss-lsio.dtsi" -+#include "imx8dxl-ss-adma.dtsi" -+#include "imx8dxl-ss-conn.dtsi" -+ -+&edma0 { -+ status = "disabled"; -+}; -+ -+&acm { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl_cm40_lpuart: cm40_lpuartgrp { -+ fsl,pins = < -+ IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 -+ IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&lsio_mu1 { -+ status = "disabled"; -+}; -+ -+&lsio_mu2 { -+ status = "okay"; -+}; -+ -+&lsio_gpio0 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio1 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio2 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio3 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio4 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio5 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio6 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio7 { -+ status = "disabled"; -+}; -+ -+&cm40_intmux { -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+&cm40_intmux { -+ status = "okay"; -+}; -+ -+&cm40_lpuart { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cm40_lpuart>; -+ status = "okay"; -+}; -+ -+/delete-node/ &lpuart0; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts -new file mode 100644 -index 000000000..a4d9752b2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts -@@ -0,0 +1,118 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8dxl-evk.dts" -+ -+/ { -+ panel { -+ compatible = "wks,101wx001"; -+ blctr-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; -+ pinctrl-assert-gpios = <&pca6416_1 3 GPIO_ACTIVE_LOW>, -+ <&pca6416_1 4 GPIO_ACTIVE_LOW>, -+ <&pca6416_1 6 GPIO_ACTIVE_LOW>, -+ <&pca6416_1 7 GPIO_ACTIVE_LOW>, -+ <&pca6416_1 8 GPIO_ACTIVE_LOW>; -+ -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&lcdif_out>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ >; -+ }; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&m2_uart1_sel { -+ status = "disabled"; -+}; -+ -+&cm40_lpuart { -+ status = "disabled"; -+}; -+ -+&lpuart1 { -+ status = "disabled"; -+}; -+ -+&eqos { -+ status = "disabled"; -+}; -+ -+&lpspi3 { -+ status = "disabled"; -+}; -+ -+&wm8960_1 { -+ status = "disabled"; -+}; -+ -+&wm8960_2 { -+ status = "disabled"; -+}; -+ -+&wm8960_3 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl_lcdif: lcdifgrp { -+ fsl,pins = < -+ IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 0xe8000023 -+ IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 0xe8000023 -+ IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 0xe8000023 -+ IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 0xd0000023 -+ IMX8DXL_UART1_TX_ADMA_LCDIF_D04 0xe8000023 -+ IMX8DXL_UART1_RX_ADMA_LCDIF_D05 0xe8000023 -+ IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 0xe8000023 -+ IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 0xe8000023 -+ IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 0xe8000023 -+ IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 0xe8000023 -+ IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 0xe8000023 -+ IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 0xe8000023 -+ IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 0xe8000023 -+ IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 0xe8200003 -+ IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 0xe8200003 -+ IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 0xe8200003 -+ IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 0xe8200003 -+ IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 0xe8200003 -+ IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC 0xd0000023 -+ IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET 0xd0000023 -+ IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN 0xd0000023 -+ IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC 0xd0000023 -+ IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK 0xd0000023 -+ >; -+ }; -+}; -+ -+&adma_lcdif { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lcdif>; -+ status = "okay"; -+ -+ assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; -+ assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; -+ assigned-clock-rates = <0>, <24000000>, <711000000>; -+ interrupts = ; -+ -+ port@0 { -+ lcdif_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts -new file mode 100644 -index 000000000..a85925342 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8dxl-evk.dts" -+ -+/delete-node/&spidev0; -+ -+&pinctrl_lpspi3 { -+ fsl,pins = < -+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 -+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 -+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 -+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 -+ >; -+}; -+ -+&lpspi3 { -+ #address-cells = <0>; -+ pinctrl-0 = <&pinctrl_lpspi3>; -+ /delete-property/ cs-gpios; -+ spi-slave; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts -new file mode 100644 -index 000000000..4d7b4ad55 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl-evk-rpmsg.dts" -+ -+&pcieb { -+ status = "disabled"; -+}; -+ -+&pcieb_ep { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-root.dts -new file mode 100644 -index 000000000..a58637225 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-root.dts -@@ -0,0 +1,100 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright NXP 2020 -+ */ -+ -+#include "imx8dxl-evk.dts" -+ -+/ { -+ domu { -+ /* -+ * There are 5 MUs, 0A is used by root cell, 1A is used -+ * by ATF, so for non-root cell, 2A/3A/4A could be used. -+ * SC_R_MU_0A -+ * SC_R_MU_1A -+ * SC_R_MU_2A -+ * SC_R_MU_3A -+ * SC_R_MU_4A -+ * The rsrcs and pads will be configured by uboot scu_rm cmd -+ */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ doma { -+ /* -+ * This is not for domu, this is just reuse -+ * the method for jailhouse inmate non root cell -+ * Linux. -+ */ -+ compatible = "xen,domu"; -+ /* -+ * The reg property will be updated by U-Boot to -+ * reflect the partition id. -+ */ -+ reg = <0>; -+ init_on_rsrcs = < -+ IMX_SC_R_MU_2A -+ >; -+ rsrcs = < -+ IMX_SC_R_SDHC_0 -+ IMX_SC_R_M4_0_INTMUX -+ IMX_SC_R_M4_0_UART -+ IMX_SC_R_MU_2A -+ >; -+ pads = < -+ /* emmc */ -+ IMX8DXL_EMMC0_CLK -+ IMX8DXL_EMMC0_CMD -+ IMX8DXL_EMMC0_DATA0 -+ IMX8DXL_EMMC0_DATA1 -+ IMX8DXL_EMMC0_DATA2 -+ IMX8DXL_EMMC0_DATA3 -+ IMX8DXL_EMMC0_DATA4 -+ IMX8DXL_EMMC0_DATA5 -+ IMX8DXL_EMMC0_DATA6 -+ IMX8DXL_EMMC0_DATA7 -+ IMX8DXL_EMMC0_STROBE -+ /* cm40_lpuart */ -+ IMX8DXL_ADC_IN3 -+ IMX8DXL_ADC_IN2 -+ >; -+ }; -+ }; -+}; -+ -+&{/reserved-memory} { -+ -+ jh_reserved: jh@bfc00000 { -+ no-map; -+ reg = <0x0 0xbfc00000 0x0 0x400000>; -+ }; -+ -+ loader_reserved: loader@bfb00000 { -+ no-map; -+ reg = <0x0 0xbfb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem_reserved: ivshmem@bf900000 { -+ no-map; -+ reg = <0x0 0xbf900000 0x0 0x00200000>; -+ }; -+ -+ pci_reserved: pci@bf700000 { -+ no-map; -+ reg = <0x0 0xbf700000 0x0 0x00200000>; -+ }; -+ -+ /* Decrease if no need such big memory */ -+ inmate_reserved: inmate@a1700000 { -+ no-map; -+ reg = <0x0 0xa1700000 0x0 0x1e000000>; -+ }; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+}; -+ -+&cm40_lpuart { -+ /* Let inmate linux use this for console */ -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts -new file mode 100644 -index 000000000..dcfc76276 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl-evk.dts" -+ -+&imx8dxl_cm4 { -+ /* Assume you have partitioned M4, so M4 is ont controled by Linux */ -+ /delete-property/ power-domains; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ status = "disabled"; -+}; -+ -+&flexcan3 { -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ status = "disabled"; -+}; -+ -+&cm40_lpuart { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts -new file mode 100644 -index 000000000..12cde4b87 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts -@@ -0,0 +1,1002 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DXL EVK"; -+ compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; -+ -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x40000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ -+/* -+ * Memory reserved for optee usage. Please do not use. -+ * This will be automaticky added to dtb if OP-TEE is installed. -+ * optee@96000000 { -+ * reg = <0 0x96000000 0 0x2000000>; -+ * no-map; -+ * }; -+ */ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x14000000>; -+ alloc-ranges = <0 0x98000000 0 0x14000000>; -+ linux,cma-default; -+ }; -+ -+ vdev0vring0: vdev0vring0@90000000 { -+ reg = <0 0x90000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@90008000 { -+ reg = <0 0x90008000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring0: vdev1vring0@90010000 { -+ reg = <0 0x90010000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring1: vdev1vring1@90018000 { -+ reg = <0 0x90018000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@900ff000 { -+ reg = <0 0x900ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ m2_uart1_sel: fixedregulator@101 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "m2_uart1_sel"; -+ gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ mux3_en: fixedregulator@102 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "mux3_en"; -+ gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>; -+ regulator-always-on; -+ }; -+ -+ pcie_clk_sel_ext: fixedregulator@103 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "clk_ext_sel"; -+ gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ reg_fec1_sel: regfec1_sel { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec1_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ status = "disabled"; -+ }; -+ -+ reg_fec1_io: regfec1_io { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec1_io_supply"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ status = "disabled"; -+ }; -+ -+ reg_can0_stby: regulator-can0-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can0-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can1_stby: regulator-can1-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can1-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ off-on-delay-us = <3480>; -+ }; -+ -+ reg_vref_1v8: regulator-adc-vref { -+ compatible = "regulator-fixed"; -+ regulator-name = "vref_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&wm8960_1>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ sound-wm8960-2 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio-2"; -+ audio-cpu = <&sai2>; -+ audio-codec = <&wm8960_2>; -+ capture-only; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ sound-wm8960-3 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio-3"; -+ audio-cpu = <&sai3>; -+ audio-codec = <&wm8960_3>; -+ capture-only; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ scu_gpio0: scu-gpio0 { -+ compatible = "fsl,imx-scu-gpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ }; -+ -+ mii_select: mii_select { -+ compatible = "regulator-fixed"; -+ regulator-name = "mii-select"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&scu_gpio0 6 GPIO_ACTIVE_HIGH>; -+ -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+}; -+ -+&adc0 { -+ vref-supply = <®_vref_1v8>; -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&edma2 { -+ status = "okay"; -+}; -+ -+&eqos { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_eqos>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ nvmem-cells = <&fec_mac1>; -+ nvmem-cell-names = "mac-address"; -+ snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; -+ snps,reset-delays-us = <10 20 200000>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ eee-broken-1000t; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; -+ phy-reset-duration = <10>; -+ phy-reset-post-delay = <150>; -+ status = "disabled"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ nxp,fspi-dll-slvdly = <4>; -+ status = "okay"; -+ -+ mt35xu512aba0: flash@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <8>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&imx8dxl_cm4 { -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, -+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; -+ status = "disabled"; -+}; -+ -+&lpspi3 { -+ fsl,spi-num-chipselects = <1>; -+ fsl,spi-only-use-cs1-sel; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi3>; -+ pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <30000000>; -+ }; -+}; -+ -+&i2c2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pca6416_1: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca6416_2: gpio@21 { -+ compatible = "ti,tca6416"; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9548_1: pca9548@70 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x70>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ status = "disabled"; -+ }; -+ }; -+ -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; -+ -+ wm8960_1: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout1_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout1_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ wm8960_2: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout1_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout1_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ wm8960_3: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; -+ clocks = <&mclkout1_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout1_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x4>; -+ }; -+ -+ i2c@5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x5>; -+ }; -+ -+ i2c@6 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x6>; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ pca6416_3: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&lsio_gpio2>; -+ interrupts = <5 IRQ_TYPE_EDGE_RISING>; -+ }; -+ -+ pca9548_2: pca9548@70 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x70>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; -+ }; -+ -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ }; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x4>; -+ }; -+ }; -+}; -+ -+&cm40_intmux { -+ status = "okay"; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&cm40_lpuart { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cm40_lpuart>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can0_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can1_stby>; -+ status = "okay"; -+}; -+ -+&lsio_gpio4 { -+ status = "okay"; -+}; -+ -+&lsio_gpio5 { -+ status = "okay"; -+}; -+ -+&pcieb{ -+ compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; -+ ext_osc = <0>; -+ epdev_on-supply = <&epdev_on>; -+ status = "okay"; -+}; -+ -+&pcieb_ep{ -+ compatible = "fsl,imx8qxp-pcie-ep"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ ext_osc = <0>; -+ status = "disabled"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ status = "okay"; -+}; -+ -+&sai2 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai2_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&sai3 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai3_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usbotg2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg2>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; -+ max-frequency = <100000000>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 -+ IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c -+ IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c -+ >; -+ }; -+ -+ pinctrl_usbotg1: otg1 { -+ fsl,pins = < -+ IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usbotg2: otg2 { -+ fsl,pins = < -+ IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_eqos: eqosgrp { -+ fsl,pins = < -+ IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 -+ IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 -+ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 -+ IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 -+ IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 -+ IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan2grp { -+ fsl,pins = < -+ IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 -+ IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 -+ IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 -+ IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_lpspi3: lpspi3grp { -+ fsl,pins = < -+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 -+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 -+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 -+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 -+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 -+ >; -+ }; -+ -+ pinctrl_cm40_lpuart: cm40_lpuartgrp { -+ fsl,pins = < -+ IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 -+ IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 -+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 -+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 -+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 -+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 -+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_pcieb: pcieagrp{ -+ fsl,pins = < -+ IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 -+ IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 -+ IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 -+ IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 -+ IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 -+ IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_sai2: sai2grp { -+ fsl,pins = < -+ IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 -+ IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 -+ IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 -+ IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 -+ IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ -+ IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ -+ IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts -new file mode 100755 -index 000000000..d336ff759 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl-phantom-mek.dtsi" -+ -+/delete-node/ &cm40_i2c; -+ -+&i2c_rpbus_5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&cm40_i2c_lpcg { -+ status = "disabled"; -+}; -+ -+&can0_lpcg { -+ status = "disabled"; -+}; -+ -+®_can0_en { -+ status = "disabled"; -+}; -+ -+®_can0_stby { -+ status = "disabled"; -+}; -+ -+®_can1_en { -+ status = "disabled"; -+}; -+ -+®_can1_stby { -+ status = "disabled"; -+}; -+ -+&cm40_intmux { -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ status = "disabled"; -+}; -+ -+&flexcan2 { -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts -new file mode 100755 -index 000000000..d7702a2a8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxl-phantom-mek.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi -new file mode 100755 -index 000000000..c72b5750c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi -@@ -0,0 +1,665 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qxp.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DXL Phantom MEK"; -+ compatible = "fsl,imx8dxl-phantom-mek", "fsl,imx8dxl-phantom", "fsl,imx8qxp"; -+ -+ chosen { -+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; -+ stdout-path = &lpuart0; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_modem_reset>; -+ pinctrl-1 = <&pinctrl_modem_reset_sleep>; -+ reset-gpios = <&lsio_gpio3 1 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_can0_en: regulator-can0-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can0-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 2 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can1_en: regulator-can1-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can1-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can0_stby: regulator-can0-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can0-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can0_en>; -+ }; -+ -+ reg_can1_stby: regulator-can1-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can1-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can1_en>; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ /*gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; removing as i2c bus is changing in new board */ -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2_vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <3480>; -+ enable-active-high; -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_wlreg_on>; -+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&lsio_gpio3 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usb_otg1_vbus: regulator@0 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb_vbus>; -+ reg = <0>; -+ regulator-name = "usb_otg1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ }; -+ -+ sound: sound { -+ compatible = "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&wm8960>; -+ audio-asrc = <&asrc0>; -+ hp-det-gpio = <&lsio_gpio0 13 0>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "AMIC", -+ "RINPUT2", "AMIC", -+ "Mic Jack", "MICB", -+ "AMIC", "MICB"; -+ }; -+}; -+ -+&lvds_subsys { -+ status = "disabled"; -+}; -+ -+&acm { -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx8dxl-phantom-mek { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 -+ IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 -+ IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 -+ IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 -+ IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 -+ IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 -+ IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 -+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 -+ IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 -+ IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 -+ IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 -+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 -+ IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 -+ IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 -+ IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 -+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x21 -+ IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ >; -+ }; -+ -+ pinctrl_cm40_i2c: cm40i2cgrp { -+ fsl,pins = < -+ IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c -+ IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c -+ >; -+ }; -+ -+ pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { -+ fsl,pins = < -+ IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 -+ >; -+ }; -+ -+ pinctrl_modem_reset: modemresetgrp { -+ fsl,pins = < -+ IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x06000021 -+ >; -+ }; -+ -+ pinctrl_modem_reset_sleep: modemreset_sleepgrp { -+ fsl,pins = < -+ IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x07800021 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000040 -+ IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC 0x06000040 -+ IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS 0x06000040 -+ IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 -+ IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x06000040 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ pinctrl_reg_usb_vbus: regusbvbusgrp { -+ fsl,pins = < -+ IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 -+ IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 -+ IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 -+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_pcieb: pcieagrp{ -+ fsl,pins = < -+ IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 -+ IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 -+ IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 -+ IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x06000021 -+ IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpio3: gpio3grp{ -+ fsl,pins = < -+ IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 -+ IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_wlreg_on: wlregongrp{ -+ fsl,pins = < -+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x06000000 -+ >; -+ }; -+ -+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ -+ fsl,pins = < -+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x07800000 -+ >; -+ }; -+ }; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ phy-reset-gpio=<&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac1>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can0_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can1_stby>; -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&cm40_intmux { -+ status = "okay"; -+}; -+ -+&cm40_i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cm40_i2c>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ fsl,sai-synchronous-rx; -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ vbus-supply = <®_usb_otg1_vbus>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-polarity-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbphy1 { -+ fsl,tx-d-cal = <114>; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&lsio_gpio3 { -+ pinctrl-name = "default"; -+ pinctrl-0 = <&pinctrl_gpio3>; -+}; -+ -+&tsens { -+ tsens-num = <3>; -+}; -+ -+&thermal_zones { -+ cpu-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens 497>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&a35_opp_table { -+ /delete-node/ opp-900000000; -+}; -+ -+&cpus { -+ /delete-node/ cpu@2; -+ /delete-node/ cpu@3; -+}; -+ -+&pcieb{ -+ compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; -+ epdev_on-supply = <&epdev_on>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi -new file mode 100644 -index 000000000..33135ea76 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi -@@ -0,0 +1,246 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+ -+/delete-node/ &asrc1; -+/delete-node/ &asrc1_lpcg; -+/delete-node/ &adc1; -+/delete-node/ &adc1_lpcg; -+/delete-node/ &amix; -+/delete-node/ &amix_lpcg; -+/delete-node/ &dsp_lpcg; -+/delete-node/ &dsp_ram_lpcg; -+/delete-node/ &edma1; -+/delete-node/ &emvsim0; -+/delete-node/ &emvsim0_lpcg; -+/delete-node/ &esai0; -+/delete-node/ &esai0_lpcg; -+/delete-node/ &sai4; -+/delete-node/ &sai4_lpcg; -+/delete-node/ &sai5; -+/delete-node/ &sai5_lpcg; -+/delete-node/ &spdif1; -+/delete-node/ &spdif1_lpcg; -+ -+&acm { -+ compatible = "nxp,imx8dxl-acm"; -+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_MCLK_OUT_0>, -+ <&pd IMX_SC_R_MCLK_OUT_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>, -+ <&pd IMX_SC_R_ASRC_0>, -+ <&pd IMX_SC_R_SAI_0>, -+ <&pd IMX_SC_R_SAI_1>, -+ <&pd IMX_SC_R_SAI_2>, -+ <&pd IMX_SC_R_SAI_3>, -+ <&pd IMX_SC_R_SPDIF_0>, -+ <&pd IMX_SC_R_MQS_0>; -+}; -+ -+&adc0 { -+ interrupts = ; -+}; -+ -+&audio_ipg_clk { -+ clock-frequency = <160000000>; -+}; -+ -+&dma_ipg_clk { -+ clock-frequency = <160000000>; -+}; -+ -+&edma0 { -+ reg = <0x591f0000 0x10000>, -+ <0x59200000 0x10000>, /* asrc0 */ -+ <0x59210000 0x10000>, -+ <0x59220000 0x10000>, -+ <0x59230000 0x10000>, -+ <0x59240000 0x10000>, -+ <0x59250000 0x10000>, -+ <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x592e0000 0x10000>, /* sai1 rx */ -+ <0x592f0000 0x10000>, /* sai1 tx */ -+ <0x59300000 0x10000>, /* sai2 rx */ -+ <0x59310000 0x10000>, /* sai3 rx */ -+ <0x59350000 0x10000>, /* gpt0 */ -+ <0x59360000 0x10000>, /* gpt1 */ -+ <0x59370000 0x10000>, /* gpt2 */ -+ <0x59380000 0x10000>; /* gpt3 */ -+ interrupts = , /* asrc 0 */ -+ , -+ , -+ , -+ , -+ , -+ , /* spdif0 */ -+ , -+ , /* sai0 */ -+ , -+ , /* sai1 */ -+ , -+ , /* sai2 */ -+ , /* sai3 */ -+ , /* gpt0 */ -+ , /* gpt1 */ -+ , /* gpt2 */ -+ ; /* gpt3 */ -+ interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ -+ "edma0-chan2-rx", "edma0-chan3-tx", -+ "edma0-chan4-tx", "edma0-chan5-tx", -+ "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ -+ "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ -+ "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ -+ "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ -+ "edma0-chan21-tx", /* gpt0 */ -+ "edma0-chan22-tx", /* gpt1 */ -+ "edma0-chan23-tx", /* gpt2 */ -+ "edma0-chan24-rx"; /* gpt3 */ -+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>, -+ <&pd IMX_SC_R_DMA_0_CH1>, -+ <&pd IMX_SC_R_DMA_0_CH2>, -+ <&pd IMX_SC_R_DMA_0_CH3>, -+ <&pd IMX_SC_R_DMA_0_CH4>, -+ <&pd IMX_SC_R_DMA_0_CH5>, -+ <&pd IMX_SC_R_DMA_0_CH8>, -+ <&pd IMX_SC_R_DMA_0_CH9>, -+ <&pd IMX_SC_R_DMA_0_CH12>, -+ <&pd IMX_SC_R_DMA_0_CH13>, -+ <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>, -+ <&pd IMX_SC_R_DMA_0_CH16>, -+ <&pd IMX_SC_R_DMA_0_CH17>, -+ <&pd IMX_SC_R_DMA_0_CH21>, -+ <&pd IMX_SC_R_DMA_0_CH22>, -+ <&pd IMX_SC_R_DMA_0_CH23>, -+ <&pd IMX_SC_R_DMA_0_CH24>; -+ power-domain-names = "edma0-chan0", "edma0-chan1", -+ "edma0-chan2", "edma0-chan3", -+ "edma0-chan4", "edma0-chan5", -+ "edma0-chan8", "edma0-chan9", -+ "edma0-chan12", "edma0-chan13", -+ "edma0-chan14", "edma0-chan15", -+ "edma0-chan16", "edma0-chan17", -+ "edma0-chan21", "edma0-chan22", -+ "edma0-chan23", "edma0-chan24"; -+}; -+ -+&edma2 { -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+&flexcan1 { -+ compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; -+ interrupts = ; -+}; -+ -+&flexcan2 { -+ compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; -+ interrupts = ; -+}; -+ -+&flexcan3 { -+ compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; -+ interrupts = ; -+}; -+ -+&i2c0 { -+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ interrupts = ; -+}; -+ -+&i2c1 { -+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ interrupts = ; -+}; -+ -+&i2c2 { -+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ interrupts = ; -+}; -+ -+&i2c3 { -+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ interrupts = ; -+}; -+ -+&lpspi0 { -+ compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; -+ interrupts = ; -+}; -+ -+&lpspi1 { -+ compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; -+ interrupts = ; -+}; -+ -+&lpspi2 { -+ compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; -+ interrupts = ; -+}; -+ -+&lpspi3 { -+ compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; -+ interrupts = ; -+}; -+ -+&lpuart0 { -+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+ interrupts = ; -+}; -+ -+&lpuart1 { -+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+ interrupts = ; -+}; -+ -+&lpuart2 { -+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+ interrupts = ; -+}; -+ -+&lpuart3 { -+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+ interrupts = ; -+}; -+ -+&sai0 { -+ interrupts = ; -+}; -+ -+&sai1 { -+ interrupts = ; -+}; -+ -+&sai2 { -+ interrupts = ; -+}; -+ -+&sai3 { -+ interrupts = ; -+}; -+ -+&spdif0 { -+ interrupts = , /* rx */ -+ ; /* tx */ -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi -new file mode 100644 -index 000000000..f81e2e836 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi -@@ -0,0 +1,162 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+ -+/delete-node/ &enet1_lpcg; -+/delete-node/ &fec2; -+/delete-node/ &usbotg3; -+/delete-node/ &usb3_lpcg; -+/delete-node/ &usb3_phy; -+ -+&conn_subsys { -+ conn_enet0_root_clk: clock-conn-enet0-root { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <250000000>; -+ clock-output-names = "conn_enet0_root_clk"; -+ }; -+ -+ eqos: ethernet@5b050000 { -+ compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; -+ reg = <0x5b050000 0x10000>; -+ interrupt-parent = <&gic>; -+ interrupts = , -+ ; -+ interrupt-names = "eth_wake_irq", "macirq"; -+ clocks = <&eqos_lpcg 2>, -+ <&eqos_lpcg 4>, -+ <&eqos_lpcg 0>, -+ <&eqos_lpcg 3>, -+ <&eqos_lpcg 1>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; -+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <125000000>; -+ power-domains = <&pd IMX_SC_R_ENET_1>; -+ clk_csr = <0>; -+ status = "disabled"; -+ }; -+ -+ usbotg2: usb@5b0e0000 { -+ compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb"; -+ reg = <0x5b0e0000 0x200>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ fsl,usbphy = <&usbphy2>; -+ fsl,usbmisc = <&usbmisc2 0>; -+ /* -+ * usbotg1 and usbotg2 share one clcok -+ * scfw disable clock access and keep it always on -+ * in case other core (M4) use one of these. -+ */ -+ clocks = <&clk_dummy>; -+ ahb-burst-config = <0x0>; -+ tx-burst-size-dword = <0x10>; -+ rx-burst-size-dword = <0x10>; -+ #stream-id-cells = <1>; -+ power-domains = <&pd IMX_SC_R_USB_1>; -+ status = "disabled"; -+ }; -+ -+ usbmisc2: usbmisc@5b0e0200 { -+ #index-cells = <1>; -+ compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc"; -+ reg = <0x5b0e0200 0x200>; -+ }; -+ -+ usbphy2: usbphy@0x5b110000 { -+ compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; -+ reg = <0x5b110000 0x1000>; -+ clocks = <&usb2_2_lpcg 0>; -+ power-domains = <&pd IMX_SC_R_USB_1_PHY>; -+ status = "disabled"; -+ }; -+ -+ eqos_lpcg: clock-controller@5b240000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b240000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&conn_enet0_root_clk>, -+ <&conn_axi_clk>, -+ <&conn_axi_clk>, -+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, -+ <&conn_ipg_clk>; -+ bit-offset = <0 8 16 20 24>; -+ clock-output-names = "eqos_ptp", -+ "eqos_mem_clk", -+ "eqos_aclk", -+ "eqos_clk", -+ "eqos_csr_clk"; -+ power-domains = <&pd IMX_SC_R_ENET_1>; -+ }; -+ -+ usb2_2_lpcg: clock-controller@5b280000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5b280000 0x10000>; -+ #clock-cells = <1>; -+ -+ bit-offset = <28>; -+ clocks = <&conn_ipg_clk>; -+ clock-output-names = "usboh3_2_phy_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_USB_1_PHY>; -+ }; -+ -+}; -+ -+&dma_apbh { -+ compatible = "fsl,imx8dxl-dma-apbh", "fsl,imx28-dma-apbh"; -+ interrupts = , -+ , -+ , -+ ; -+}; -+ -+&enet0_lpcg { -+ clocks = <&conn_enet0_root_clk>, -+ <&conn_enet0_root_clk>, -+ <&conn_axi_clk>, -+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, -+ <&conn_ipg_clk>, -+ <&conn_ipg_clk>; -+}; -+ -+&fec1 { -+ compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec"; -+ interrupts = , -+ , -+ , -+ ; -+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; -+ assigned-clock-rates = <125000000>; -+}; -+ -+&gpmi { -+ compatible = "fsl,imx8dxl-gpmi-nand", "fsl,imx8qxp-gpmi-nand"; -+ interrupts = ; -+}; -+ -+&usdhc1 { -+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; -+ interrupts = ; -+}; -+ -+&usdhc2 { -+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; -+ interrupts = ; -+}; -+ -+&usdhc3 { -+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; -+ interrupts = ; -+}; -+ -+&usbotg1 { -+ interrupts = ; -+ /* -+ * usbotg1 and usbotg2 share one clcok -+ * scfw disable clock access and keep it always on -+ * in case other core (M4) use one of these. -+ */ -+ clocks = <&clk_dummy>; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi -new file mode 100644 -index 000000000..4c7e26780 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+&ddr_pmu0 { -+ compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; -+ interrupts = ; -+}; -+ -+&ddr_subsys { -+ db_ipg_clk: clock-db-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <456000000>; -+ clock-output-names = "db_ipg_clk"; -+ }; -+ -+ db_pmu0: db-pmu@5ca40000 { -+ compatible = "fsl,imx8dxl-db-pmu"; -+ reg = <0x5ca40000 0x10000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>; -+ clock-names = "ipg", "cnt"; -+ power-domains = <&pd IMX_SC_R_PERF>; -+ }; -+ -+ db_pmu0_lpcg: clock-controller@5cae0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5cae0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&db_ipg_clk>, <&db_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "perf_lpcg_cnt_clk", -+ "perf_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_PERF>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi -new file mode 100644 -index 000000000..0efe8a862 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+ -+&hsio_subsys { -+ phyx1_lpcg: clock-controller@5f090000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f090000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_refb_clk>, <&hsio_per_clk>, -+ <&hsio_per_clk>, <&hsio_per_clk>; -+ bit-offset = <0 4 8 16>; -+ clock-output-names = "hsio_phyx1_pclk", -+ "hsio_phyx1_epcs_tx_clk", -+ "hsio_phyx1_epcs_rx_clk", -+ "hsio_phyx1_apb_clk"; -+ power-domains = <&pd IMX_SC_R_SERDES_1>; -+ }; -+}; -+ -+&pcieb { -+ compatible = "fsl,imx8dxl-pcie", "fsl,imx8qxp-pcie", "snps,dw-pcie"; -+ interrupts = , -+ ; -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic 0 47 4>, -+ <0 0 0 2 &gic 0 48 4>, -+ <0 0 0 3 &gic 0 49 4>, -+ <0 0 0 4 &gic 0 50 4>; -+}; -+ -+&pcieb_ep { -+ compatible = "fsl,imx8qxp-pcie-ep"; -+ interrupts = ; -+ interrupt-names = "dma"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi -new file mode 100644 -index 000000000..b93c98988 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+&flexspi0 { -+ compatible = "nxp,imx8dxl-fspi"; -+ interrupts = ; -+}; -+ -+&lsio_gpio0 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio1 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio2 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio3 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio4 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio5 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio6 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_gpio7 { -+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; -+ interrupts = ; -+}; -+ -+&lsio_mu0 { -+ compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+ interrupts = ; -+}; -+ -+&lsio_mu1 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+ interrupts = ; -+}; -+ -+&lsio_mu2 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+ interrupts = ; -+}; -+ -+&lsio_mu3 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+ interrupts = ; -+}; -+ -+&lsio_mu4 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+ interrupts = ; -+}; -+ -+&lsio_mu5 { -+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+ interrupts = ; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi -new file mode 100644 -index 000000000..c6dfc52ac ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+&sec_mu2 { -+ interrupts = ; -+}; -+ -+&sec_mu3 { -+ interrupts = ; -+}; -+ -+&sec_mu4 { -+ interrupts = ; -+}; -+ -+&sec_jr2 { -+ interrupts = ; -+}; -+ -+&sec_jr3 { -+ interrupts = ; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi -new file mode 100644 -index 000000000..00c7690a5 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi -@@ -0,0 +1,282 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019~2020 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ can0 = &flexcan1; -+ can1 = &flexcan2; -+ can2 = &flexcan3; -+ ethernet0 = &fec1; -+ ethernet1 = &eqos; -+ gpio0 = &lsio_gpio0; -+ gpio1 = &lsio_gpio1; -+ gpio2 = &lsio_gpio2; -+ gpio3 = &lsio_gpio3; -+ gpio4 = &lsio_gpio4; -+ gpio5 = &lsio_gpio5; -+ gpio6 = &lsio_gpio6; -+ gpio7 = &lsio_gpio7; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ mmc0 = &usdhc1; -+ mmc1 = &usdhc2; -+ mu1 = &lsio_mu1; -+ serial0 = &lpuart0; -+ serial1 = &lpuart1; -+ serial2 = &lpuart2; -+ serial3 = &lpuart3; -+ serial4 = &cm40_lpuart; -+ }; -+ -+ cpus: cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ /* We have 1 clusters with 2 Cortex-A35 cores */ -+ A35_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35"; -+ reg = <0x0 0x0>; -+ enable-method = "psci"; -+ next-level-cache = <&A35_L2>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; -+ #cooling-cells = <2>; -+ operating-points-v2 = <&a35_opp_table>; -+ }; -+ -+ A35_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35"; -+ reg = <0x0 0x1>; -+ enable-method = "psci"; -+ next-level-cache = <&A35_L2>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; -+ #cooling-cells = <2>; -+ operating-points-v2 = <&a35_opp_table>; -+ }; -+ -+ A35_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a35_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ imx8dxl_cm4: imx8dxl_cm4@0 { -+ compatible = "fsl,imx8qxp-cm4"; -+ rsc-da = <0x90000000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&lsio_mu5 0 1 -+ &lsio_mu5 1 1 -+ &lsio_mu5 3 1>; -+ mub-partition = <3>; -+ core-index = <0>; -+ core-id = ; -+ status = "disabled"; -+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, -+ <&pd IMX_SC_R_M4_0_MU_1A>; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", -+ "rx0", -+ "gip3"; -+ mboxes = <&lsio_mu1 0 0 -+ &lsio_mu1 1 0 -+ &lsio_mu1 3 3>; -+ -+ pd: imx8dxl-pd { -+ compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ wakeup-irq = <160 163 235 236 237 228 229 230 231 238 -+ 239 240 166 169>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8dxl-iomuxc"; -+ }; -+ -+ ocotp: imx8qx-ocotp { -+ compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ fec_mac0: mac@2c4 { -+ reg = <0x2c4 6>; -+ }; -+ -+ fec_mac1: mac@2c6 { -+ reg = <0x2c6 6>; -+ }; -+ }; -+ -+ rtc: rtc { -+ compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc"; -+ }; -+ -+ watchdog { -+ compatible = "fsl,imx-sc-wdt"; -+ timeout-sec = <60>; -+ }; -+ -+ tsens: thermal-sensor { -+ compatible = "fsl,imx-sc-thermal"; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ }; -+ -+ thermal_zones: thermal-zones { -+ cpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; -+ -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ imx_ion { -+ compatible = "fsl,mxc-ion"; -+ fsl,heap-id = <0>; -+ }; -+ -+ sc_pwrkey: sc-powerkey { -+ compatible = "fsl,imx8-pwrkey"; -+ linux,keycode = ; -+ wakeup-source; -+ }; -+ -+ /* sorted in register address */ -+ #include "imx8-ss-v2x.dtsi" -+ #include "imx8-ss-security.dtsi" -+ #include "imx8-ss-cm40.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-ddr.dtsi" -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-hsio.dtsi" -+ #include "imx8-ss-lcdif.dtsi" -+}; -+ -+#include "imx8dxl-ss-adma.dtsi" -+#include "imx8dxl-ss-conn.dtsi" -+#include "imx8dxl-ss-lsio.dtsi" -+#include "imx8dxl-ss-hsio.dtsi" -+#include "imx8dxl-ss-ddr.dtsi" -+#include "imx8dxl-ss-security.dtsi" -+ -+&cm40_intmux { -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts -new file mode 100644 -index 000000000..15b28e151 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8dxp.dtsi" -+#include "imx8x-val.dtsi" -+ -+/ { -+ model = "Freescale i.MX8DXP VALIDATION"; -+ compatible = "fsl,imx8dxp-val", "fsl,imx8dxp", "fsl,imx8qxp"; -+}; -+ -+&usbotg3 { -+ dr_mode = "otg"; -+ extcon = <&typec_ptn5150>; -+ status = "okay"; -+}; -+ -+&vpu_decoder { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8dxp.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi -new file mode 100644 -index 000000000..fba74a311 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8dxp.dtsi -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp.dtsi" -+ -+&thermal_zones { -+ cpu-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&cpus { -+ /delete-node/ cpu@2; -+ /delete-node/ cpu@3; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts -new file mode 100644 -index 000000000..105eae347 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts -@@ -0,0 +1,97 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ab2.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ reg = <0 0x80000000 0 0x0101E400>; -+ no-map; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc-table { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ leds { -+ panel { -+ status = "disabled"; -+ }; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ status = "disabled"; -+ }; -+ -+ sound-bt-sco { -+ status = "disabled"; -+ }; -+ -+ imx8mm-cm4 { -+ compatible = "fsl,imx8mm-cm4"; -+ rsc-da = <0xb8000000>; -+ clocks = <&clk IMX8MM_CLK_M4_DIV>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; -+ syscon = <&src>; -+ }; -+}; -+ -+&clk { -+ init-on-array = < -+ IMX8MM_CLK_UART4_ROOT -+ IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE -+ IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB -+ IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB -+ IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV -+ IMX8MM_ARM_PLL_OUT -+ >; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&sai2 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts -new file mode 100755 -index 000000000..ee91a92d0 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk.dts" -+#include "imx8mm-ab2.dtsi" -+ -+/ { -+ model = "FSL i.MX8MM Audio board 2.0"; -+ compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi -new file mode 100755 -index 000000000..c2ca975eb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi -@@ -0,0 +1,377 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/ { -+ /delete-node/ ir-receiver; -+ /delete-node/ audio-codec; -+ /delete-node/ regulator-audio-board; -+ /delete-node/ sound-wm8524; -+ /delete-node/ sound-ak5558; -+ /delete-node/ sound-ak4497; -+ /delete-node/ sound-micfil; -+ -+ leds { -+ panel { -+ label = "green:panel"; -+ gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ }; -+ -+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr { -+ compatible = "regulator-fixed"; -+ regulator-name = "ANA_12V0"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; -+ vin-supply = <&buck5_reg>; -+ enable-active-high; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "VDD_5V0"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ vin-supply = <&buck5_reg>; -+ enable-active-high; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ADC_DVDD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_adc_avdd_5v0: reg-adc-avdd-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ADC_AVDD_5V0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "DAC_DVDD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_dac_avdd_5v0: reg-dac-avdd-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "DAC_AVDD_5V0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_cph_3v3: reg-cph-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "CPH_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <®_ab2_vdd_pwr_5v0>; -+ }; -+ -+ reg_cph_1v8: reg-cph-1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "CPH_1V8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <®_cph_3v3>; -+ }; -+ -+ sound-ak4458 { -+ compatible = "fsl,imx-audio-ak4458"; -+ model = "ak4458-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&ak4458_1>, <&ak4458_2>; -+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sound-ak5552 { -+ compatible = "fsl,imx-audio-ak5552"; -+ model = "ak5552-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&ak5552>; -+ }; -+}; -+ -+&csi1_bridge { -+ status = "disabled"; -+ /delete-node/ port; -+}; -+ -+&fec1 { -+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; -+ phy-reset-post-delay = <150>; -+ phy-reset-duration = <10>; -+ -+ mdio { -+ ethphy0: ethernet-phy@0 { -+ /delete-property/ at803x,eee-disabled; -+ /delete-property/ at803x,vddio-1p8v; -+ max-speed = <100>; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ /delete-node/ adv7535@3d; -+ -+ pca6408_2: gpio@20 { -+ compatible = "ti,tca6408"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ vcc-supply = <&buck4_reg>; -+ }; -+ -+ ptn5110: tcpc@50 { -+ status = "disabled"; -+ /delete-node/ port; -+ }; -+ -+ ptn5150: tcpc@1d { -+ compatible = "nxp,ptn5150"; -+ reg = <0x1d>; -+ status = "okay"; -+ -+ typec_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <15000000>; -+ self-powered; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ /delete-node/ ak5558@13; -+ /delete-node/ ak4497@11; -+ /delete-node/ ov5640_mipi@3c; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ vcc-supply = <&buck5_reg>; -+ }; -+ -+ ak4458_1: ak4458@10 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x10>; -+ AVDD-supply = <®_dac_avdd_5v0>; -+ DVDD-supply = <®_dac_dvdd_3v3>; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x12>; -+ AVDD-supply = <®_dac_avdd_5v0>; -+ DVDD-supply = <®_dac_dvdd_3v3>; -+ }; -+ -+ ak4458_3: ak4458@11 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x11>; -+ AVDD-supply = <®_dac_avdd_5v0>; -+ DVDD-supply = <®_dac_dvdd_3v3>; -+ status = "disabled"; -+ }; -+ -+ ak5552: ak5552@13 { -+ compatible = "asahi-kasei,ak5552"; -+ reg = <0x13>; -+ reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_adc_avdd_5v0>; -+ DVDD-supply = <®_adc_dvdd_3v3>; -+ }; -+}; -+ -+&i2c4 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c4>; -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ /delete-node/ csi_pwn_grp; -+ /delete-node/ csi_rst_grp; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 -+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */ -+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */ -+ >; -+ }; -+ -+ pinctrl_i2c4: i2c4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_ab2_ana_pwr: ab2anapwrgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&mipi_csi_1 { -+ status = "disabled"; -+ /delete-node/ port; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+ /delete-node/ port@1; -+}; -+ -+&pcie0 { -+ status = "disabled"; -+ /delete-property/ pinctrl-0; -+}; -+ -+&pcie0_ep { -+ /delete-property/ pinctrl-0; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ dr_mode = "peripheral"; -+ /delete-property/ usb-role-switch; -+ /delete-node/ port; -+}; -+ -+&usdhc2 { -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts -new file mode 100644 -index 000000000..6ff765cb4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts -@@ -0,0 +1,22 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ddr4-ab2-m4.dts" -+ -+/ { -+ model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; -+}; -+ -+/* -+ * External OSC is used as PCIe REFCLK on RevC board. -+ * Use the -revb.dts file to distiguish the different -+ * HW design. -+ */ -+&pcie0 { -+ ext_osc = <0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts -new file mode 100644 -index 000000000..1d2991308 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts -@@ -0,0 +1,81 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ddr4-ab2.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ reg = <0 0x80000000 0 0x0101E400>; -+ no-map; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc-table { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ leds { -+ panel { -+ status = "disabled"; -+ }; -+ }; -+ -+ imx8mm-cm4 { -+ compatible = "fsl,imx8mm-cm4"; -+ rsc-da = <0xb8000000>; -+ clocks = <&clk IMX8MM_CLK_M4_DIV>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; -+ syscon = <&src>; -+ }; -+}; -+ -+&clk { -+ init-on-array = < -+ IMX8MM_CLK_UART4_ROOT -+ IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE -+ IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB -+ IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB -+ IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV -+ IMX8MM_ARM_PLL_OUT -+ >; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts -new file mode 100644 -index 000000000..833c0f0a8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts -@@ -0,0 +1,22 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ddr4-ab2.dts" -+ -+/ { -+ model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; -+}; -+ -+/* -+ * External OSC is used as PCIe REFCLK on RevC board. -+ * Use the -revb.dts file to distiguish the different -+ * HW design. -+ */ -+&pcie0 { -+ ext_osc = <0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts -new file mode 100644 -index 000000000..d2c75f530 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ddr4-evk.dts" -+#include "imx8mm-ab2.dtsi" -+ -+/ { -+ model = "FSL i.MX8MM DDR4 Audio Board 2.0"; -+ compatible = "fsl,imx8mm-ddr4-ab2", "fsl,imx8mm"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts -new file mode 100644 -index 000000000..fe6961f39 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm.dtsi" -+ -+/ { -+ model = "Freescale i.MX8MM EVK"; -+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; -+ interrupt-parent = <&gic>; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ clk_dummy: clock@7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ /* The clocks are configured by 1st OS */ -+ clk_266m: clock@9 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <266000000>; -+ clock-output-names = "266m"; -+ }; -+ clk_80m: clock@10 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <80000000>; -+ clock-output-names = "80m"; -+ }; -+ clk_100m: clock@11 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "100m"; -+ }; -+ -+ display-subsystem { -+ /delete-property/ compatible; -+ }; -+ -+ pci@bb800000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xbb800000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+}; -+ -+/delete-node/ &{/reserved-memory}; -+/delete-node/ &{/busfreq}; -+/delete-node/ &{/soc@0/ddr-pmu@3d800000}; -+ -+&hsiomix_pd { -+ status = "disabled"; -+}; -+ -+&pcie_pd { -+ status = "disabled"; -+}; -+ -+&usb_otg1_pd { -+ status = "disabled"; -+}; -+ -+&usb_otg2_pd { -+ status = "disabled"; -+}; -+ -+&gpumix_pd { -+ status = "disabled"; -+}; -+ -+&vpumix_pd { -+ status = "disabled"; -+}; -+ -+&vpu_g1_pd { -+ status = "disabled"; -+}; -+ -+&vpu_g2_pd { -+ status = "disabled"; -+}; -+ -+&vpu_h1_pd { -+ status = "disabled"; -+}; -+ -+&dispmix_pd { -+ status = "disabled"; -+}; -+ -+&mipi_pd { -+ status = "disabled"; -+}; -+ -+&gpio1 { -+ status = "disabled"; -+}; -+&gpio2 { -+ status = "disabled"; -+}; -+&gpio3 { -+ status = "disabled"; -+}; -+&gpio4 { -+ status = "disabled"; -+}; -+&gpio5 { -+ status = "disabled"; -+}; -+ -+/delete-node/ &tmu; -+/delete-node/ &{/thermal-zones}; -+&iomuxc { -+ status = "disabled"; -+}; -+ -+&gpr { -+ /delete-property/ compatible; -+}; -+ -+/delete-node/ &anatop; -+/delete-node/ &snvs; -+ -+&clk { -+ /delete-property/ compatible; -+}; -+ -+&src { -+ /delete-property/ compatible; -+}; -+ -+/delete-node/ &system_counter; -+ -+&ocotp { -+ /delete-property/ compatible; -+ status = "disabled"; -+}; -+ -+&dispmix_gpr { -+ /delete-property/ compatible; -+}; -+ -+&sdma1 { -+ status = "disabled"; -+}; -+ -+&sdma2 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+/*/delete-node/ &{/imx_ion};*/ -+/delete-node/ &pcie0; -+/delete-node/ &crypto; -+/delete-node/ &caam_sm; -+/delete-node/ &caam_snvs; -+/delete-node/ &irq_sec_vio; -+ -+/delete-node/ &{/cpus/cpu@0}; -+/delete-node/ &{/cpus/cpu@1}; -+/delete-node/ &{/pmu}; -+ -+&uart4 { -+ clocks = <&osc_24m>, -+ <&osc_24m>; -+ clock-names = "ipg", "per"; -+ /delete-property/ dmas; -+ /delete-property/ dmas-names; -+ status = "okay"; -+}; -+ -+&dma_apbh { -+ clocks = <&clk_266m>; -+ status = "okay"; -+}; -+ -+&gpmi { -+ clocks = <&clk_100m>, -+ <&clk_266m>; -+ status = "okay"; -+ nand-on-flash-bbt; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts -new file mode 100644 -index 000000000..da61f5b76 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ddr4-evk.dts" -+ -+&pcie0{ -+ status = "disabled"; -+}; -+ -+&pcie0_ep{ -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts -new file mode 100644 -index 000000000..1175756de ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019,2021 NXP -+ */ -+ -+#include "imx8mm-ddr4-evk-revb.dts" -+ -+&adv_bridge { -+ status = "disabled"; -+}; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; /* 0: burst mode -+ * 1: non-burst mode with sync event -+ * 2: non-burst mode with sync pulse -+ */ -+ panel-width-mm = <68>; -+ panel-height-mm = <121>; -+ status = "okay"; -+ }; -+}; -+ -+&i2c2 { -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts -new file mode 100644 -index 000000000..277807e77 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mm-ddr4-evk-revb-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c2 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts -new file mode 100644 -index 000000000..d442c9e89 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts -@@ -0,0 +1,22 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-ddr4-evk.dts" -+ -+/ { -+ model = "FSL i.MX8MM DDR4 EVK RevB board"; -+}; -+ -+/* -+ * External OSC is used as PCIe REFCLK on RevC board. -+ * Use the -revb.dts file to distiguish the different -+ * HW design. -+ */ -+&pcie0{ -+ ext_osc = <0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts -new file mode 100644 -index 000000000..ddda6a7f3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019,2021 NXP -+ */ -+ -+#include "imx8mm-ddr4-evk.dts" -+ -+&adv_bridge { -+ status = "disabled"; -+}; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; /* 0: burst mode -+ * 1: non-burst mode with sync event -+ * 2: non-burst mode with sync pulse -+ */ -+ panel-width-mm = <68>; -+ panel-height-mm = <121>; -+ status = "okay"; -+ }; -+}; -+ -+&i2c2 { -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts -new file mode 100644 -index 000000000..e69f59d51 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mm-ddr4-evk-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c2 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts -new file mode 100644 -index 000000000..4f9bfd1eb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts -@@ -0,0 +1,96 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mm-ddr4-evk.dts" -+ -+/ { -+ interrupt-parent = <&gic>; -+}; -+ -+&cpu_pd_wait { -+ /delete-property/ compatible; -+ /*arm,psci-suspend-param = <0x0>;*/ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&{/busfreq} { -+ /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ -+ status = "disabled"; -+}; -+ -+&{/reserved-memory} { -+ -+ ivshmem_reserved: ivshmem@bbb00000 { -+ no-map; -+ reg = <0 0xbbb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem2_reserved: ivshmem2@bba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00100000>; -+ }; -+ -+ pci_reserved: pci@bb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@bb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@b7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x24000000>; -+ }; -+}; -+ -+&uart2 { -+ /* uart2 is used by the 2nd OS, so configure pin and clk */ -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>, <&pinctrl_gpmi_nand>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+}; -+ -+&usdhc2 { -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -+ -+&dma_apbh { -+ status = "disabled"; -+}; -+ -+&gpmi { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts -index 6c079c0a3..248fef5bb 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts -@@ -18,6 +18,129 @@ status { - gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - }; - }; -+ -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1_gpio>; -+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+/delete-node/&pmic_nxp; -+ -+&i2c1 { -+ pmic_rohm: pmic@4b { -+ compatible = "rohm,bd71847"; -+ reg = <0x4b>; -+ pinctrl-0 = <&pinctrl_pmic>; -+ pinctrl-names = "default"; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ rohm,reset-snvs-powered; -+ -+ #clock-cells = <0>; -+ clocks = <&osc_32k 0>; -+ clock-output-names = "clk-32k-out"; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ // BUCK5 in datasheet -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck4_reg: BUCK4 { -+ // BUCK6 in datasheet -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: BUCK5 { -+ // BUCK7 in datasheet -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ // BUCK8 in datasheet -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "LDO6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; - }; - - &gpmi { -@@ -27,6 +150,30 @@ &gpmi { - status = "okay"; - }; - -+&usdhc1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; -+ bus-width = <4>; -+ cap-power-off-card; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ status = "okay"; -+ -+ brcmf: bcrmf@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&gpio2>; -+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < -@@ -54,4 +201,11 @@ pinctrl_gpio_led_2: gpioled2grp { - MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 - >; - }; -+ -+ pinctrl_wlan: wlangrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 -+ >; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts -new file mode 100644 -index 000000000..ec4108c4c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts -@@ -0,0 +1,120 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ mic_leds { -+ compatible = "gpio-leds"; -+ mic0 { -+ label = "mic0"; -+ gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic1 { -+ label = "mic1"; -+ gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic2 { -+ label = "mic2"; -+ gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic3 { -+ label = "mic3"; -+ gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic4 { -+ label = "mic4"; -+ gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic5 { -+ label = "mic5"; -+ gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic6 { -+ label = "mic6"; -+ gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic7 { -+ label = "mic7"; -+ gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ }; -+ -+ sw_keys { -+ compatible = "gpio-keys"; -+ -+ sw4: volume_down { -+ label = "Volume Down"; -+ gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ sw3: volume_up { -+ label = "Volume Up"; -+ gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ sw2: volume_mute { -+ label = "Volume Mute"; -+ gpios = <&pca9555 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ sw1: key_act { -+ label = "Key Act"; -+ gpios = <&pca9555 17 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ }; -+ -+ reg_vddext_3v3: regulator-vddext { -+ compatible = "regulator-fixed"; -+ regulator-name = "VDDEXT_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_swpdm_mute_irq: swpdm_mute_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 -+ >; -+ }; -+ -+ pinctrl_pushbutton_irq: pushbutton_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 -+ >; -+ }; -+}; -+ -+&i2c3 { -+ pca9555: gpio@21 { -+ compatible = "nxp,pca9555"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pushbutton_irq>; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ vcc-supply = <®_vddext_3v3>; -+ status = "okay"; -+ }; -+}; -+ -+&uart3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts -new file mode 100644 -index 000000000..b93225c37 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts -@@ -0,0 +1,35 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mm-evk-8mic-revE.dts" -+ -+/ { -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-swpdm { -+ compatible = "fsl,imx-pdm-mic"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_swpdm_mute_irq>; -+ mute-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; -+ model = "imx-swpdm-audio"; -+ audio-cpu = <&sai5>; -+ decimation = <64>; -+ status = "okay"; -+ fixed-mclk; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; -+ assigned-clock-rates = <24576000>; -+ fsl,dataline,dsd = <4 0xf 0xf>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts -new file mode 100644 -index 000000000..18aacba54 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts -@@ -0,0 +1,66 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ sound-ak4458 { -+ status = "disabled"; -+ }; -+ -+ sound-ak4497 { -+ status = "okay"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai1_pcm: sai1grp_pcm { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1_pcm>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ assigned-clock-rates = <22579200>; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0x11>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "okay"; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts -new file mode 100644 -index 000000000..4d3da8e33 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ sound-ak5558 { -+ status = "okay"; -+ }; -+ sound-micfil { -+ status = "disabled"; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts -new file mode 100644 -index 000000000..7e34cd63f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts -@@ -0,0 +1,25 @@ -+/* -+ * Copyright 2018 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mm-evk-ak5558.dts" -+ -+/ { -+ sound-ak4458 { -+ fsl,tdm; -+ }; -+ -+ sound-ak5558 { -+ fsl,tdm; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts -new file mode 100644 -index 000000000..3b5503933 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts -@@ -0,0 +1,10 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+&fec1 { -+ compatible = "fsl,imx8mm-fec-uio"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts -new file mode 100644 -index 000000000..e06dbc00d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// Copyright 2020 NXP -+ -+#include "imx8mm-evk.dts" -+ -+/delete-node/&spidev0; -+ -+&ecspi2 { -+ #address-cells = <0>; -+ /delete-property/cs-gpios; -+ spi-slave; -+}; -+ -+&pinctrl_ecspi2_cs { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 -+ >; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts -new file mode 100644 -index 000000000..847ce29db ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ ext_osc_22m: ext-osc-22m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <22579200>; -+ clock-output-names = "sclk0"; -+ }; -+ -+ ext_osc_24m: ext-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ clock-output-names = "sclk1"; -+ }; -+ -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-ak4458 { -+ status = "disabled"; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ bitclock-master = <&pcm512x>; -+ frame-master = <&pcm512x>; -+ dac,24db_digital_gain; -+ dac,led_status; -+ }; -+}; -+ -+&i2c3 { -+ ak4458_1: ak4458@10 { -+ status = "disabled"; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ status = "disabled"; -+ }; -+ -+ ak5558: ak5558@13 { -+ status = "disabled"; -+ }; -+ -+ ak4497: ak4497@11 { -+ status = "disabled"; -+ }; -+ -+ pcm512x: pcm512x@4d { -+ compatible = "ti,pcm5122"; -+ reg = <0x4d>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ clocks = <&ext_osc_22m>, <&ext_osc_24m>; -+ clock-names = "sclk0", "sclk1"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts -new file mode 100644 -index 000000000..6afccc2c1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts -@@ -0,0 +1,184 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+ -+/ { -+ model = "Freescale i.MX8MM EVK"; -+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial3 = &uart4; -+ mmc2 = &usdhc3; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ interrupt-affinity = <&A53_2>, <&A53_3>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ clk_dummy: clock@7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ /* The clocks are configured by 1st OS */ -+ clk_200m: clock@8 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "200m"; -+ }; -+ clk_266m: clock@9 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <266000000>; -+ clock-output-names = "266m"; -+ }; -+ clk_80m: clock@10 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <80000000>; -+ clock-output-names = "80m"; -+ }; -+ -+ osc_24m: clock-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ pci@bb800000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xbb800000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ -+ aips3: bus@30800000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x8000000 0x8000000 0x10000000>; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; -+ -+&uart4 { -+ clocks = <&osc_24m>, -+ <&osc_24m>; -+ clock-names = "ipg", "per"; -+ /delete-property/ dmas; -+ /delete-property/ dmas-names; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ clocks = <&clk_dummy>, -+ <&clk_266m>, -+ <&clk_200m>; -+ /delete-property/assigned-clocks; -+ /delete-property/assigned-clock-rates; -+ clock-names = "ipg", "ahb", "per"; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts -new file mode 100644 -index 000000000..170db2331 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts -@@ -0,0 +1,79 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-ak4458 { -+ status = "disabled"; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ dac,24db_digital_gain; -+ }; -+}; -+ -+&i2c3 { -+ ak4458_1: ak4458@10 { -+ status = "disabled"; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ status = "disabled"; -+ }; -+ -+ ak4497: ak4497@11 { -+ status = "disabled"; -+ }; -+ -+ pcm512x: pcm512x@4c { -+ compatible = "ti,pcm5122"; -+ reg = <0x4c>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts -new file mode 100644 -index 000000000..3d1398c12 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts -@@ -0,0 +1,79 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-ak4458 { -+ status = "disabled"; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ dac,24db_digital_gain; -+ }; -+}; -+ -+&i2c3 { -+ ak4458_1: ak4458@10 { -+ status = "disabled"; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ status = "disabled"; -+ }; -+ -+ ak4497: ak4497@11 { -+ status = "disabled"; -+ }; -+ -+ pcm512x: pcm512x@4c { -+ compatible = "ti,pcm5142"; -+ reg = <0x4c>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts -new file mode 100644 -index 000000000..ccf3e9901 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts -@@ -0,0 +1,123 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019-2021 NXP -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ interrupt-parent = <&gic>; -+ -+ ivshm_rpmsg { -+ compatible = "fsl,ivshm-rpmsg"; -+ -+ rpmsg_console { -+ compatible = "fsl,rpmsg-console"; -+ id = <2>; -+ size = <16384>; -+ }; -+ }; -+}; -+ -+&cpu_pd_wait { -+ /delete-property/ compatible; -+ /*arm,psci-suspend-param = <0x0>;*/ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&gpio5 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&{/busfreq} { -+ /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ -+ status = "disabled"; -+}; -+ -+&{/reserved-memory} { -+ ivshmem_reserved: ivshmem@bba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00400000>; -+ }; -+ -+ pci_reserved: pci@bb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@bb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@b7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x20000000>; -+ }; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ status = "disabled"; -+}; -+ -+&{/reserved-memory/linux,cma} { -+ alloc-ranges = <0 0x40000000 0 0x60000000>; -+}; -+ -+&uart2 { -+ /* uart2 is used by the 2nd OS, so configure pin and clk */ -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ /* sdhc3 is used by 2nd linux, configure the pin */ -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts -new file mode 100644 -index 000000000..2f96420e3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk.dts" -+ -+&pcie0{ -+ status = "disabled"; -+}; -+ -+&pcie0_ep{ -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts -new file mode 100755 -index 000000000..a5965c687 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ model = "FSL i.MX8MM LPDDR4 EVK with QCA WIFI revC board "; -+}; -+ -+/delete-node/&pmic_nxp; -+ -+&i2c1 { -+ pmic_rohm: pmic@4b { -+ compatible = "rohm,bd71847"; -+ reg = <0x4b>; -+ pinctrl-0 = <&pinctrl_pmic>; -+ pinctrl-names = "default"; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ rohm,reset-snvs-powered; -+ -+ #clock-cells = <0>; -+ clocks = <&osc_32k 0>; -+ clock-output-names = "clk-32k-out"; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ // BUCK5 in datasheet -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck4_reg: BUCK4 { -+ // BUCK6 in datasheet -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: BUCK5 { -+ // BUCK7 in datasheet -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ // BUCK8 in datasheet -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "LDO6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts -new file mode 100644 -index 000000000..e9f23182d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts -@@ -0,0 +1,22 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk-qca-wifi.dts" -+ -+/ { -+ model = "FSL i.MX8MM LPDDR4 EVK with QCA WIFI revB board "; -+}; -+ -+/* -+ * External OSC is used as PCIe REFCLK on RevC board. -+ * Use the -revb.dts file to distiguish the different -+ * HW design. -+ */ -+&pcie0{ -+ ext_osc = <0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts -new file mode 100644 -index 000000000..925f67255 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019,2021 NXP -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+&adv_bridge { -+ status = "disabled"; -+}; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; /* 0: burst mode -+ * 1: non-burst mode with sync event -+ * 2: non-burst mode with sync pulse -+ */ -+ panel-width-mm = <68>; -+ panel-height-mm = <121>; -+ status = "okay"; -+ }; -+}; -+ -+&i2c2 { -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts -new file mode 100644 -index 000000000..68b5cc47b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mm-evk-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c2 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts -new file mode 100644 -index 000000000..426b0adc3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts -@@ -0,0 +1,95 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ interrupt-parent = <&gic>; -+}; -+ -+&cpu_pd_wait { -+ /delete-property/ compatible; -+ /*arm,psci-suspend-param = <0x0>;*/ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&{/busfreq} { -+ /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ -+ status = "disabled"; -+}; -+ -+&{/reserved-memory} { -+ -+ ivshmem_reserved: ivshmem@bbb00000 { -+ no-map; -+ reg = <0 0xbbb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem2_reserved: ivshmem2@bba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00100000>; -+ }; -+ -+ pci_reserved: pci@bb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@bb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@b7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x24000000>; -+ }; -+}; -+ -+&{/reserved-memory/linux,cma} { -+ alloc-ranges = <0 0x40000000 0 0x60000000>; -+}; -+ -+&uart2 { -+ /* uart2 is used by the 2nd OS, so configure pin and clk */ -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ /* sdhc3 is used by 2nd linux, configure the pin */ -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts -new file mode 100644 -index 000000000..fa0242aac ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts -@@ -0,0 +1,163 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@b80ff000 { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ status = "disabled"; -+ }; -+ -+ sound-bt-sco { -+ status = "disabled"; -+ }; -+ -+ sound-wm8524 { -+ status = "disabled"; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ wm8524: audio-codec { -+ status = "disabled"; -+ }; -+ -+ rpmsg_audio: rpmsg_audio { -+ compatible = "fsl,imx8mm-rpmsg-audio"; -+ model = "wm8524-audio"; -+ fsl,platform = "rpmsg-audio-channel"; -+ fsl,enable-lpa; -+ fsl,rpmsg-out; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>, -+ <&clk IMX8MM_CLK_SAI3_ROOT>, -+ <&clk IMX8MM_CLK_SDMA3_ROOT>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ status = "okay"; -+ }; -+ -+ rpmsg_micfil: rpmsg_micfil { -+ compatible = "fsl,imx8mm-rpmsg-audio"; -+ model = "micfil-audio"; -+ fsl,platform = "rpmsg-micfil-channel"; -+ fsl,rpmsg-in; -+ assigned-clocks = <&clk IMX8MM_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ clocks = <&clk IMX8MM_CLK_PDM_IPG>, -+ <&clk IMX8MM_CLK_PDM_ROOT>, -+ <&clk IMX8MM_CLK_SDMA3_ROOT>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ status = "okay"; -+ }; -+ -+ imx8mm-cm4 { -+ compatible = "fsl,imx8mm-cm4"; -+ rsc-da = <0xb8000000>; -+ clocks = <&clk IMX8MM_CLK_M4_DIV>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; -+ syscon = <&src>; -+ }; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+/* -+ * ATTENTION: M4 may use IPs like below -+ * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 -+ */ -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&sai2 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&uart3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts -new file mode 100644 -index 000000000..28c38e9d1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts -@@ -0,0 +1,132 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@b80ff000 { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ status = "disabled"; -+ }; -+ -+ sound-bt-sco { -+ status = "disabled"; -+ }; -+ -+ sound-wm8524 { -+ status = "disabled"; -+ }; -+ -+ wm8524: audio-codec { -+ status = "disabled"; -+ }; -+ -+ rpmsg_audio: rpmsg_audio { -+ compatible = "fsl,imx8mm-rpmsg-audio"; -+ model = "ak4497-audio"; -+ fsl,enable-lpa; -+ fsl,rpmsg-out; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, -+ <&clk IMX8MM_CLK_SDMA3_ROOT>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ status = "okay"; -+ }; -+ -+ imx8mm-cm4 { -+ compatible = "fsl,imx8mm-cm4"; -+ rsc-da = <0xb8000000>; -+ clocks = <&clk IMX8MM_CLK_M4_DIV>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; -+ syscon = <&src>; -+ }; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+/* -+ * ATTENTION: M4 may use IPs like below -+ * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 -+ */ -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&sai2 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts -new file mode 100644 -index 000000000..33c12e501 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts -@@ -0,0 +1,58 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm-evk.dts" -+ -+&pinctrl_usdhc2 { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 -+ >; -+}; -+ -+&pinctrl_usdhc2_100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 -+ >; -+}; -+ -+&pinctrl_usdhc2_200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 -+ >; -+}; -+ -+&usdhc2 { -+ pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; -+ /delete-property/ cd-gpios; -+ keep-power-in-suspend; -+ non-removable; -+ wakeup-source; -+ fsl,sdio-interrupt-enabled; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+ /delete-node/ wifi_wake_host; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts -old mode 100644 -new mode 100755 -index 4e2820d19..86922c452 ---- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts -@@ -15,6 +15,13 @@ / { - aliases { - spi0 = &flexspi; - }; -+ -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1_gpio>; -+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; -+ }; - }; - - &ddrc { -@@ -48,11 +55,32 @@ flash@0 { - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; -- spi-tx-bus-width = <4>; -+ spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; - }; - -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; -+ bus-width = <4>; -+ keep-power-in-suspend; -+ non-removable; -+ wakeup-source; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ fsl,sdio-interrupt-enabled; -+ status = "okay"; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpio2>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; -@@ -125,4 +153,11 @@ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; -+ -+ pinctrl_wlan: wlangrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159 -+ >; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi -old mode 100644 -new mode 100755 -index 521eb3a5a..7bb3541a1 ---- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi -@@ -18,6 +18,14 @@ memory@40000000 { - reg = <0x0 0x40000000 0 0x80000000>; - }; - -+ ir_recv: ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ir_recv>; -+ linux,autosuspend-period = <125>; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -30,6 +38,23 @@ status { - }; - }; - -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ reg_audio_board: regulator-audio-board { -+ compatible = "regulator-fixed"; -+ regulator-name = "EXT_PWREN"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ startup-delay-us = <300000>; -+ gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ }; -+ - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; -@@ -38,9 +63,34 @@ reg_usdhc2_vmmc: regulator-usdhc2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <20000>; - enable-active-high; - }; - -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; -+ }; -+ -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; -@@ -73,6 +123,45 @@ simple-audio-card,codec { - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - }; -+ -+ sound-ak4458 { -+ compatible = "fsl,imx-audio-ak4458"; -+ model = "ak4458-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&ak4458_1>, <&ak4458_2>; -+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sound-ak5558 { -+ compatible = "fsl,imx-audio-ak5558"; -+ model = "ak5558-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&ak5558>; -+ status = "disabled"; -+ }; -+ -+ sound-ak4497 { -+ compatible = "fsl,imx-audio-ak4497"; -+ model = "ak4497-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&ak4497>; -+ status = "disabled"; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif1>; -+ spdif-out; -+ spdif-in; -+ }; -+ -+ sound-micfil { -+ compatible = "fsl,imx-audio-micfil"; -+ model = "imx-audio-micfil"; -+ cpu-dai = <&micfil>; -+ }; -+ - }; - - &A53_0 { -@@ -91,6 +180,32 @@ &A53_3 { - cpu-supply = <&buck2_reg>; - }; - -+&csi1_bridge { -+ fsl,mipi-mode; -+ status = "okay"; -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&ecspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ - &fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; -@@ -106,8 +221,8 @@ mdio { - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; -- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; -- reset-assert-us = <10000>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; - }; - }; - }; -@@ -118,78 +233,69 @@ &i2c1 { - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - -- pmic@4b { -- compatible = "rohm,bd71847"; -- reg = <0x4b>; -- pinctrl-names = "default"; -+ pmic_nxp: pca9450@25 { -+ compatible = "nxp,pca9450a"; -+ reg = <0x25>; - pinctrl-0 = <&pinctrl_pmic>; -+ pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; -- rohm,reset-snvs-powered; -- -- #clock-cells = <0>; -- clocks = <&osc_32k 0>; -- clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { -- regulator-name = "buck1"; -- regulator-min-microvolt = <700000>; -- regulator-max-microvolt = <1300000>; -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; -- regulator-ramp-delay = <1250>; -+ regulator-ramp-delay = <3125>; -+ nxp,dvs-run-voltage = <850000>; -+ nxp,dvs-standby-voltage = <800000>; - }; - - buck2_reg: BUCK2 { -- regulator-name = "buck2"; -- regulator-min-microvolt = <700000>; -- regulator-max-microvolt = <1300000>; -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; -- regulator-ramp-delay = <1250>; -- rohm,dvs-run-voltage = <1000000>; -- rohm,dvs-idle-voltage = <900000>; -+ regulator-ramp-delay = <3125>; - }; - - buck3_reg: BUCK3 { -- // BUCK5 in datasheet -- regulator-name = "buck3"; -- regulator-min-microvolt = <700000>; -- regulator-max-microvolt = <1350000>; -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { -- // BUCK6 in datasheet -- regulator-name = "buck4"; -- regulator-min-microvolt = <3000000>; -- regulator-max-microvolt = <3300000>; -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { -- // BUCK7 in datasheet -- regulator-name = "buck5"; -- regulator-min-microvolt = <1605000>; -- regulator-max-microvolt = <1995000>; -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { -- // BUCK8 in datasheet -- regulator-name = "buck6"; -- regulator-min-microvolt = <800000>; -- regulator-max-microvolt = <1400000>; -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { -- regulator-name = "ldo1"; -+ regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; -@@ -197,35 +303,33 @@ ldo1_reg: LDO1 { - }; - - ldo2_reg: LDO2 { -- regulator-name = "ldo2"; -+ regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; -- regulator-max-microvolt = <900000>; -+ regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { -- regulator-name = "ldo3"; -- regulator-min-microvolt = <1800000>; -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { -- regulator-name = "ldo4"; -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <1800000>; -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - -- ldo6_reg: LDO6 { -- regulator-name = "ldo6"; -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -+ ldo5_reg: LDO5 { -+ regulator-name = "LDO5"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; - }; - }; - }; -@@ -237,6 +341,25 @@ &i2c2 { - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - -+ adv_bridge: adv7535@3d { -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ -+ status = "okay"; -+ -+ port { -+ adv7535_from_dsim: endpoint { -+ remote-endpoint = <&dsim_to_adv7535>; -+ }; -+ }; -+ }; -+ - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; -@@ -268,7 +391,7 @@ typec1_con: connector { - }; - - &i2c3 { -- clock-frequency = <400000>; -+ clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -@@ -278,9 +401,175 @@ pca6416: gpio@20 { - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; -+ vcc-supply = <&buck4_reg>; -+ }; -+ -+ ak4458_1: ak4458@10 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x10>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x12>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ }; -+ -+ ak5558: ak5558@13 { -+ compatible = "asahi-kasei,ak5558"; -+ reg = <0x13>; -+ reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ }; -+ -+ ak4497: ak4497@11 { -+ compatible = "asahi-kasei,ak4497"; -+ reg = <0x11>; -+ reset-gpios = <&pca6416 5 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ dsd-path = <1>; -+ }; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MM_CLK_CLKO1>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ }; -+ }; - }; - }; - -+&lcdif { -+ status = "okay"; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi1_sensor_ep: endpoint@1 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ -+ csi1_mipi_ep: endpoint@2 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pdm>; -+ assigned-clocks = <&clk IMX8MM_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ dsim_to_adv7535: endpoint { -+ remote-endpoint = <&adv7535_from_dsim>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&pcie0{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&clk IMX8MM_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <100000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, -+ <&clk IMX8MM_SYS_PLL2_100M>, -+ <&clk IMX8MM_SYS_PLL2_250M>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -+ -+&pcie0_ep{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&clk IMX8MM_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <100000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, -+ <&clk IMX8MM_SYS_PLL2_100M>, -+ <&clk IMX8MM_SYS_PLL2_250M>; -+ ext_osc = <1>; -+ l1ss-disabled; -+ status = "disabled"; -+}; -+ -+&sai2 { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI2>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "okay"; -+}; -+ - &sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; -@@ -290,22 +579,79 @@ &sai3 { - status = "okay"; - }; - -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "disabled"; -+}; -+ -+&sai6 { -+ fsl,sai-monitor-spdif; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ - &snvs_pwrkey { - status = "okay"; - }; - -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, -+ <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", -+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ - &uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - }; - -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ - &usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; -+ disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; -@@ -330,6 +676,22 @@ &usdhc2 { - status = "okay"; - }; - -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_h1 { -+ status = "okay"; -+}; -+ -+&vpu_v4l2 { -+ status = "okay"; -+}; -+ - &wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; -@@ -337,7 +699,44 @@ &wdog1 { - status = "okay"; - }; - -+&gpu { -+ status = "okay"; -+}; -+ - &iomuxc { -+ pinctrl_ir_recv: ir-recv { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f -+ >; -+ }; -+ -+ pinctrl_csi_pwn: csi_pwn_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 -+ >; -+ }; -+ -+ pinctrl_ecspi2: ecspi2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 -+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 -+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 -+ >; -+ }; -+ -+ pinctrl_ecspi2_cs: ecspi2cs { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 -+ >; -+ }; -+ - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -@@ -384,6 +783,12 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - -+ pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ -+ >; -+ }; -+ - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -@@ -391,6 +796,32 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ -+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 -+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 -+ >; -+ }; -+ -+ pinctrl_pdm: pdmgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 -+ >; -+ }; -+ - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 -@@ -403,6 +834,49 @@ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai2: sai2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 -+ >; -+ }; -+ - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -@@ -412,12 +886,40 @@ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 -+ >; -+ }; -+ -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 -+ >; -+ }; -+ - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 -+ >; -+ }; -+ - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 -@@ -425,6 +927,54 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 -+ MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 -+ MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 -+ MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1_gpio: usdhc1grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 -diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi -old mode 100644 -new mode 100755 -index 05ee06254..d2c2b96cb ---- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi -@@ -4,9 +4,11 @@ - */ - - #include -+#include - #include - #include - #include -+#include - #include - - #include "imx8mm-pinfunc.h" -@@ -30,6 +32,11 @@ aliases { - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; -+ sai1 = &sai1; -+ sai2 = &sai2; -+ sai3 = &sai3; -+ sai5 = &sai5; -+ sai6 = &sai6; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; -@@ -144,6 +151,21 @@ opp-1800000000 { - }; - }; - -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x80000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ }; -+ - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -198,6 +220,110 @@ pmu { - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; - }; - -+ power-domains { -+ compatible = "simple-bus"; -+ /* HSIO SS */ -+ hsiomix_pd: hsiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <0>; -+ domain-name = "hsiomix"; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ }; -+ -+ pcie_pd: pcie-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <1>; -+ domain-name = "pcie"; -+ parent-domains = <&hsiomix_pd>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; -+ }; -+ -+ usb_otg1_pd: usbotg1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <2>; -+ domain-name = "usb_otg1"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ usb_otg2_pd: usbotg2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <3>; -+ domain-name = "usb_otg2"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ /* GPU SS */ -+ gpumix_pd: gpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <4>; -+ domain-name = "gpumix"; -+ clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_CLK_GPU2D_ROOT>, -+ <&clk IMX8MM_CLK_GPU3D_ROOT>; -+ }; -+ -+ /* VPU SS */ -+ vpumix_pd: vpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <5>; -+ domain-name = "vpumix"; -+ clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ }; -+ -+ vpu_g1_pd: vpug1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <6>; -+ domain-name = "vpu_g1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; -+ }; -+ -+ vpu_g2_pd: vpug2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <7>; -+ domain-name = "vpu_g2"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; -+ }; -+ -+ vpu_h1_pd: vpuh1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <8>; -+ domain-name = "vpu_h1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; -+ }; -+ -+ /* DISP SS */ -+ dispmix_pd: dispmix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <9>; -+ domain-name = "dispmix"; -+ clocks = <&clk IMX8MM_CLK_DISP_ROOT>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ }; -+ -+ mipi_pd: mipi-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <10>; -+ domain-name = "mipi"; -+ parent-domains = <&dispmix_pd>; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ -@@ -256,11 +382,37 @@ usbphynop2: usbphynop2 { - clock-names = "main_clk"; - }; - -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT>, -+ <&clk IMX8MM_CLK_DRAM_APB>, <&clk IMX8MM_CLK_DRAM_APB>, -+ <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, -+ <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, -+ <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, -+ <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, -+ <&clk IMX8MM_DRAM_PLL>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", -+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", -+ "sys_pll1_800m", "dram_pll_div"; -+ interrupts = , , -+ , ; -+ interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ }; -+ - soc@0 { -- compatible = "simple-bus"; -+ compatible = "fsl,imx8mm-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; -+ nvmem-cells = <&imx8mm_uid>; -+ nvmem-cell-names = "soc_unique_id"; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; -@@ -274,12 +426,13 @@ sai1: sai@30010000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; -- clocks = <&clk IMX8MM_CLK_SAI1_IPG>, -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI1_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; - dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xff 0xff>; - status = "disabled"; - }; - -@@ -288,10 +441,10 @@ sai2: sai@30020000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30020000 0x10000>; - interrupts = ; -- clocks = <&clk IMX8MM_CLK_SAI2_IPG>, -+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI2_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -302,10 +455,10 @@ sai3: sai@30030000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; -- clocks = <&clk IMX8MM_CLK_SAI3_IPG>, -+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI3_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -316,12 +469,13 @@ sai5: sai@30050000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; -- clocks = <&clk IMX8MM_CLK_SAI5_IPG>, -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI5_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; - dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xf 0xf>; - status = "disabled"; - }; - -@@ -330,15 +484,58 @@ sai6: sai@30060000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30060000 0x10000>; - interrupts = ; -- clocks = <&clk IMX8MM_CLK_SAI6_IPG>, -+ clocks = <&clk IMX8MM_CLK_SAI6_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI6_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - -+ micfil: micfil@30080000 { -+ compatible = "fsl,imx8mm-micfil"; -+ reg = <0x30080000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&clk IMX8MM_CLK_PDM_IPG>, -+ <&clk IMX8MM_CLK_PDM_ROOT>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>, -+ <&clk IMX8MM_CLK_EXT3>; -+ clock-names = "ipg_clk", "ipg_clk_app", -+ "pll8k", "pll11k", "clkext3"; -+ dmas = <&sdma2 24 25 0x80000000>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ spdif1: spdif@30090000 { -+ compatible = "fsl,imx8mm-spdif"; -+ reg = <0x30090000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ -+ <&clk IMX8MM_CLK_24M>, /* rxtx0 */ -+ <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MM_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ - gpio1: gpio@30200000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; -@@ -463,7 +660,7 @@ iomuxc: pinctrl@30330000 { - }; - - gpr: iomuxc-gpr@30340000 { -- compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; -+ compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - -@@ -475,9 +672,17 @@ ocotp: efuse@30350000 { - #address-cells = <1>; - #size-cells = <1>; - -+ imx8mm_uid: unique-id@410 { -+ reg = <0x4 0x8>; -+ }; -+ - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; -+ -+ fec_mac_address: mac-address@640 { -+ reg = <0x90 6>; -+ }; - }; - - anatop: anatop@30360000 { -@@ -485,6 +690,22 @@ anatop: anatop@30360000 { - reg = <0x30360000 0x10000>; - }; - -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; -+ clock-names = "ipg"; -+ }; -+ - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; -@@ -780,6 +1001,7 @@ mu: mailbox@30aa0000 { - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_MU_ROOT>; -+ clock-names = "mu"; - #mbox-cells = <2>; - }; - -@@ -850,7 +1072,7 @@ sdma1: dma-controller@30bd0000 { - }; - - fec1: ethernet@30be0000 { -- compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; -+ compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , -@@ -866,18 +1088,47 @@ fec1: ethernet@30be0000 { - assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, - <&clk IMX8MM_CLK_ENET_TIMER>, - <&clk IMX8MM_CLK_ENET_REF>, -- <&clk IMX8MM_CLK_ENET_TIMER>; -+ <&clk IMX8MM_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_SYS_PLL2_100M>, -- <&clk IMX8MM_SYS_PLL2_125M>; -- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; -+ <&clk IMX8MM_SYS_PLL2_125M>, -+ <&clk IMX8MM_SYS_PLL2_50M>; -+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; -+ nvmem-cells = <&fec_mac_address>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ fsl,stop-mode = <&gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; - status = "disabled"; - }; - - }; - -+ noc: interconnect@32700000 { -+ compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; -+ reg = <0x32700000 0x100000>; -+ clocks = <&clk IMX8MM_CLK_NOC>; -+ fsl,ddrc = <&ddrc>; -+ #interconnect-cells = <1>; -+ operating-points-v2 = <&noc_opp_table>; -+ -+ noc_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-150M { -+ opp-hz = /bits/ 64 <150000000>; -+ }; -+ opp-375M { -+ opp-hz = /bits/ 64 <375000000>; -+ }; -+ opp-750M { -+ opp-hz = /bits/ 64 <750000000>; -+ }; -+ }; -+ }; -+ - aips4: bus@32c00000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; -@@ -885,6 +1136,100 @@ aips4: bus@32c00000 { - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - -+ lcdif: lcdif@32e00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-lcdif"; -+ reg = <0x32e00000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MM_CLK_DISP_AXI>, -+ <&clk IMX8MM_CLK_DISP_APB>; -+ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, -+ <&clk IMX8MM_SYS_PLL2_1000M>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rate = <594000000>, <500000000>, <200000000>; -+ interrupts = ; -+ lcdif-gpr = <&dispmix_gpr>; -+ resets = <&lcdif_resets>; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ -+ lcdif_disp0: port@0 { -+ reg = <0>; -+ -+ lcdif_to_dsim: endpoint { -+ remote-endpoint = <&dsim_from_lcdif>; -+ }; -+ }; -+ }; -+ -+ mipi_dsi: mipi_dsi@32e10000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-mipi-dsim"; -+ reg = <0x32e10000 0x400>; -+ clocks = <&clk IMX8MM_CLK_DSI_CORE>, -+ <&clk IMX8MM_CLK_DSI_PHY_REF>; -+ clock-names = "cfg", "pll-ref"; -+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, -+ <&clk IMX8MM_CLK_DSI_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, -+ <&clk IMX8MM_CLK_24M>; -+ assigned-clock-rates = <266000000>, <12000000>; -+ interrupts = ; -+ dsi-gpr = <&dispmix_gpr>; -+ resets = <&mipi_dsi_resets>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ dsim_from_lcdif: endpoint { -+ remote-endpoint = <&lcdif_to_dsim>; -+ }; -+ }; -+ }; -+ -+ csi1_bridge: csi1_bridge@32e20000 { -+ compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x32e20000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_CSI1_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: mipi_csi@32e30000 { -+ compatible = "fsl,imx8mm-mipi-csi"; -+ reg = <0x32e30000 0x1000>; -+ interrupts = ; -+ clock-frequency = <333000000>; -+ clocks = <&clk IMX8MM_CLK_CSI1_CORE>, -+ <&clk IMX8MM_CLK_CSI1_PHY_REF>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; -+ bus-width = <4>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ }; -+ -+ dispmix_gpr: display-gpr@32e28000 { -+ compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; -+ reg = <0x32e28000 0x100>; -+ }; -+ -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif_disp0>; -+ }; -+ - usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x32e40000 0x200>; -@@ -895,6 +1240,7 @@ usbotg1: usb@32e40000 { - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; -+ power-domains = <&usb_otg1_pd>; - status = "disabled"; - }; - -@@ -914,6 +1260,7 @@ usbotg2: usb@32e50000 { - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; -+ power-domains = <&usb_otg2_pd>; - status = "disabled"; - }; - -@@ -923,6 +1270,10 @@ usbmisc2: usbmisc@32e50200 { - reg = <0x32e50200 0x200>; - }; - -+ pcie_phy: pcie-phy@32f00000 { -+ compatible = "fsl,imx7d-pcie-phy"; -+ reg = <0x32f00000 0x10000>; -+ }; - }; - - dma_apbh: dma-controller@33000000 { -@@ -954,6 +1305,60 @@ gpmi: nand-controller@33002000{ - status = "disabled"; - }; - -+ pcie0: pcie@33800000 { -+ compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; -+ reg = <0x33800000 0x400000>, -+ <0x1ff00000 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = ; -+ interrupt-names = "msi"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; -+ linux,pci-domain = <0>; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pcie_pd>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "clkreq", "turnoff"; -+ fsl,imx7d-pcie-phy = <&pcie_phy>; -+ status = "disabled"; -+ }; -+ -+ pcie0_ep: pcie_ep@33800000 { -+ compatible = "fsl,imx8mm-pcie-ep"; -+ reg = <0x33800000 0x000400000>, -+ <0x18000000 0x08000000>; -+ reg-names = "regs", "addr_space"; -+ num-lanes = <1>; -+ interrupts = ; /* eDMA */ -+ interrupt-names = "dma"; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pcie_pd>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "clkreq", "turnoff"; -+ fsl,imx7d-pcie-phy = <&pcie_phy>; -+ num-ib-windows = <4>; -+ num-ob-windows = <4>; -+ status = "disabled"; -+ }; -+ - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ -@@ -979,4 +1384,160 @@ ddr-pmu@3d800000 { - interrupts = ; - }; - }; -+ -+ dispmix-reset { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { -+ compatible = "fsl,imx8mm-dispmix-sft-rstn"; -+ reg = <0x0 0x32e28000 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_clk_en: dispmix-clk-en@32e28004 { -+ compatible = "fsl,imx8mm-dispmix-clk-en"; -+ reg = <0x0 0x32e28004 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { -+ compatible = "fsl,imx8mm-dispmix-mipi-rst"; -+ reg = <0x0 0x32e28008 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ lcdif_resets: lcdif-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ lcdif-clk-enable { -+ compatible = "lcdif,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, -+ <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; -+ }; -+ }; -+ -+ mipi_dsi_resets: mipi-dsi-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ dsi-soft-resetn { -+ compatible = "dsi,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; -+ }; -+ -+ dsi-clk-enable { -+ compatible = "dsi,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, -+ <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; -+ }; -+ -+ dsi-mipi-reset { -+ compatible = "dsi,mipi-reset"; -+ resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; -+ }; -+ }; -+ -+ vpu_h1: vpu_h1@38320000 { -+ compatible = "nxp,imx8mm-hantro-h1"; -+ reg = <0x0 0x38320000 0x0 0x10000>; -+ reg-names = "regs_hantro_h1"; -+ interrupts = ; -+ interrupt-names = "irq_hantro_h1"; -+ clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_h1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g1: vpu_g1@38300000 { -+ compatible = "nxp,imx8mm-hantro"; -+ reg = <0x0 0x38300000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_g1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g2: vpu_g2@38310000 { -+ compatible = "nxp,imx8mm-hantro"; -+ reg = <0x0 0x38310000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_g2_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_v4l2: vpu_v4l2 { -+ compatible = "nxp,imx8m-vsiv4l2"; -+ status = "disabled"; -+ }; -+ -+ gpu: gpu@38000000 { -+ compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; -+ reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, -+ <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "phys_baseaddr", "contiguous_mem"; -+ interrupts = , -+ ; -+ interrupt-names = "irq_3d", "irq_2d"; -+ clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_CLK_GPU2D_ROOT>, -+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>; -+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", -+ "gpu3d_axi_clk", "gpu3d_ahb_clk", -+ "gpu2d_clk", "gpu2d_axi_clk", -+ "gpu2d_ahb_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, -+ <&clk IMX8MM_CLK_GPU2D_SRC>, -+ <&clk IMX8MM_CLK_GPU_AXI>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_GPU_PLL_OUT>; -+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, -+ <&clk IMX8MM_GPU_PLL_OUT>, -+ <&clk IMX8MM_SYS_PLL1_800M>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; -+ -+ power-domains = <&gpumix_pd>; -+ -+ status = "disabled"; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts -new file mode 100644 -index 000000000..4cd82ed94 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mn-evk.dts" -+#include "imx8mn-ab2.dtsi" -+ -+/ { -+ model = "NXP i.MX8MNano Audio board 2.0"; -+ compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; -+}; -+ -+&i2c2 { -+ pca6408_2: gpio@20 { -+ vcc-supply = <&buck4>; -+ }; -+}; -+ -+&i2c3 { -+ pca6416: gpio@20 { -+ vcc-supply = <&buck5>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi -new file mode 100644 -index 000000000..69c1ed444 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi -@@ -0,0 +1,299 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/ { -+ /delete-node/ audio-codec; -+ /delete-node/ ir-receiver; -+ /delete-node/ regulator-audio-board; -+ /delete-node/ sound-wm8524; -+ /delete-node/ sound-micfil; -+ /delete-node/ sound-ak5558; -+ -+ gpio-leds { -+ panel { -+ label = "green:panel"; -+ gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ }; -+ -+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr { -+ compatible = "regulator-fixed"; -+ regulator-name = "ANA_12V0"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "VDD_5V0"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ADC_DVDD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_adc_avdd_5v0: reg-adc-avdd-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ADC_DVDD_5V0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "DAC_DVDD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_dac_avdd_5v0: reg-dac-avdd-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ADC_DVDD_5V0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ reg_cph_3v3: reg-cph-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "CPH_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <®_ab2_vdd_pwr_5v0>; -+ }; -+ -+ reg_cph_1v8: reg-cph-1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "CPH_1V8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <®_ab2_vdd_pwr_5v0>; -+ }; -+ -+ sound-ak4458 { -+ compatible = "fsl,imx-audio-ak4458"; -+ model = "ak4458-audio"; -+ audio-cpu = <&sai3>; -+ audio-codec = <&ak4458_1>, <&ak4458_2>; -+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cameradev { -+ status = "disabled"; -+}; -+ -+&fec1 { -+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; -+ phy-reset-post-delay = <150>; -+ phy-reset-duration = <10>; -+ -+ mdio { -+ ethphy0: ethernet-phy@0 { -+ /delete-property/ at803x,eee-disabled; -+ /delete-property/ at803x,vddio-1p8v; -+ max-speed = <100>; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ /delete-node/ adv7535@3d; -+ -+ pca6408_2: gpio@20 { -+ compatible = "ti,tca6408"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ ptn5110: tcpc@50 { -+ status = "disabled"; -+ /delete-node/ port; -+ }; -+ -+ ptn5150: tcpc@1d { -+ compatible = "nxp,ptn5150"; -+ reg = <0x1d>; -+ status = "okay"; -+ -+ typec_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <15000000>; -+ self-powered; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ /delete-node/ ak5558@13; -+ /delete-node/ ak4497@11; -+ /delete-node/ ov5640_mipi@3c; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ ak4458_1: ak4458@10 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x10>; -+ AVDD-supply = <®_dac_avdd_5v0>; -+ DVDD-supply = <®_dac_dvdd_3v3>; -+ status = "okay"; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x12>; -+ AVDD-supply = <®_dac_avdd_5v0>; -+ DVDD-supply = <®_dac_dvdd_3v3>; -+ status = "okay"; -+ }; -+ -+ ak4458_3: ak4458@11 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x11>; -+ AVDD-supply = <®_dac_avdd_5v0>; -+ DVDD-supply = <®_dac_dvdd_3v3>; -+ status = "disabled"; -+ }; -+ -+ ak5552: ak5552@13 { -+ compatible = "asahi-kasei,ak5552"; -+ reg = <0x13>; -+ reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_adc_avdd_5v0>; -+ DVDD-supply = <®_adc_dvdd_3v3>; -+ status = "disabled"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_ab2_ana_pwr: ab2anapwrgrp { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 -+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 -+ MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0xd6 -+ >; -+ }; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&mipi_csi_1 { -+ status = "disabled"; -+ /delete-node/ port@0; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+ /delete-node/ port@1; -+}; -+ -+ -+&usbotg1 { -+ dr_mode = "peripheral"; -+ /delete-property/ usb-role-switch; -+ /delete-node/ port; -+}; -+ -+&usdhc2 { -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, -+ <&clk IMX8MN_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts -new file mode 100644 -index 000000000..c319eb246 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ /* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mn-ab2.dts" -+ -+/ { -+ model = "NXP i.MX8MNano DDR3L Audio board 2.0"; -+}; -+ -+&aips4 { -+ /delete-node/ display-subsystem; -+}; -+ -+/delete-node/ &gpu; -+/delete-node/ &lcdif; -+/delete-node/ &mipi_dsi; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts -new file mode 100644 -index 000000000..bd541601a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts -@@ -0,0 +1,40 @@ -+/* -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mn-ddr3l-evk.dts" -+ -+/ { -+ sound-wm8524 { -+ audio-asrc = <0>; -+ }; -+ sound-ak5558 { -+ asrc-controller = <&easrc>; -+ status = "okay"; -+ }; -+ sound-micfil { -+ status = "disabled"; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -+ -+&ak5558 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts -new file mode 100644 -index 000000000..155a28771 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mn-ddr3l-evk.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x14000000>; -+ alloc-ranges = <0 0x40000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ -+ m_core_reserved: m_core@0x77000000 { -+ no-map; -+ reg = <0 0x77000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@78000000 { -+ reg = <0 0x78000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@78008000 { -+ reg = <0 0x78008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@0x780ff000 { -+ reg = <0 0x780ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@78400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x78400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ sound-wm8524 { -+ status = "disabled"; -+ }; -+ -+ wm8524: audio-codec { -+ status = "disabled"; -+ }; -+ -+ rpmsg_audio: rpmsg_audio { -+ compatible = "fsl,imx8mn-rpmsg-audio"; -+ model = "wm8524-audio"; -+ fsl,enable-lpa; -+ fsl,rpmsg-out; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MN_CLK_SAI3_IPG>, -+ <&clk IMX8MN_CLK_SAI3_ROOT>, -+ <&clk IMX8MN_CLK_SDMA3_ROOT>, -+ <&clk IMX8MN_AUDIO_PLL1_OUT>, -+ <&clk IMX8MN_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ status = "okay"; -+ }; -+ -+ imx8mn-cm7 { -+ compatible = "fsl,imx8mn-cm7"; -+ rsc-da = <0xb8000000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, <&rsc_table>; -+ status = "okay"; -+ }; -+}; -+ -+&clk { -+ init-on-array = < -+ IMX8MN_CLK_UART4_ROOT -+ >; -+}; -+ -+/* -+ * ATTENTION: M core may use IPs like below -+ * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM -+ */ -+ -+&ecspi2 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts -new file mode 100644 -index 000000000..e903abdd5 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ /* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ model = "NXP i.MX8MNano DDR3L EVK board"; -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck1>; -+}; -+ -+&aips4 { -+ /delete-node/ display-subsystem; -+}; -+ -+/delete-node/ &adv_bridge; -+/delete-node/ &gpu; -+/delete-node/ &lcdif; -+/delete-node/ &mipi_dsi; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts -new file mode 100644 -index 000000000..436b68df6 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mn-ddr4-evk.dts" -+#include "imx8mn-ab2.dtsi" -+ -+/ { -+ model = "NXP i.MX8MNano DDR4 Audio board 2.0"; -+ compatible = "fsl,imx8mn-ddr4-ab2", "fsl,imx8mn"; -+}; -+ -+&i2c2 { -+ pca6408_2: gpio@20 { -+ vcc-supply = <&buck4_reg>; -+ }; -+}; -+ -+&i2c3 { -+ pca6416: gpio@20 { -+ vcc-supply = <&buck5_reg>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts -new file mode 100644 -index 000000000..fa46cf85b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts -@@ -0,0 +1,31 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk.dts" -+ -+/ { -+ sound-wm8524 { -+ audio-asrc = <0>; -+ }; -+ sound-ak5558 { -+ asrc-controller = <&easrc>; -+ status = "okay"; -+ }; -+ sound-micfil { -+ status = "disabled"; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -+ -+&ak5558 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts -new file mode 100644 -index 000000000..96a7616bb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts -@@ -0,0 +1,179 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+ -+/ { -+ model = "Freescale i.MX8MN EVK"; -+ compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial3 = &uart4; -+ mmc2 = &usdhc3; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ osc_24m: clock-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ clk_dummy: clock@7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ /* The clocks are configured by 1st OS */ -+ clk_200m: clock@8 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "200m"; -+ }; -+ clk_266m: clock@9 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <266000000>; -+ clock-output-names = "266m"; -+ }; -+ clk_80m: clock@10 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <80000000>; -+ clock-output-names = "80m"; -+ }; -+ -+ pci@bb800000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xbb800000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; -+ -+ aips3: bus@30800000 { -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x08000000 0x08000000 0x10000000>; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; -+ -+&uart4 { -+ clocks = <&osc_24m>, -+ <&osc_24m>; -+ clock-names = "ipg", "per"; -+ /delete-property/ dmas; -+ /delete-property/ dmas-names; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ clocks = <&clk_dummy>, -+ <&clk_266m>, -+ <&clk_200m>; -+ /delete-property/assigned-clocks; -+ /delete-property/assigned-clock-rates; -+ clock-names = "ipg", "ahb", "per"; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts -new file mode 100644 -index 000000000..1f9839c0c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts -@@ -0,0 +1,125 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019-2021 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk.dts" -+ -+&{/} { -+ ivshm_rpmsg { -+ compatible = "fsl,ivshm-rpmsg"; -+ -+ rpmsg_console { -+ compatible = "fsl,rpmsg-console"; -+ id = <2>; -+ size = <16384>; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ -+ ivshmem_reserved: ivshmem@0xbba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00400000>; -+ }; -+ -+ pci_reserved: pci@0xbb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@0xbb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@0xb7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@0x93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x20000000>; -+ }; -+ }; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&gpio5 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ status = "disabled"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MN_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MN_CLK_24M>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts -new file mode 100644 -index 000000000..cba54b620 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2018-2019,2021 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk.dts" -+ -+&adv_bridge { -+ status = "disabled"; -+}; -+ -+&i2c2 { -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "okay"; -+ }; -+}; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; /* 0: burst mode -+ * 1: non-burst mode with sync event -+ * 2: non-burst mode with sync pulse -+ */ -+ panel-width-mm = <68>; -+ panel-height-mm = <121>; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts -new file mode 100644 -index 000000000..d91afbe5e ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c2 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts -new file mode 100644 -index 000000000..5388f8fff ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts -@@ -0,0 +1,95 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk.dts" -+ -+/* -+TODO: need uncomment when linux ready -+&cpu_pd_wait { -+ /delete-property/ compatible; -+}; -+*/ -+ -+&{/} { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ -+ ivshmem_reserved: ivshmem@0xbbb00000 { -+ no-map; -+ reg = <0 0xbbb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem2_reserved: ivshmem2@0xbba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00100000>; -+ }; -+ -+ pci_reserved: pci@0xbb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@0xbb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@0xb7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@0x93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x24000000>; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MN_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MN_CLK_24M>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts -new file mode 100644 -index 000000000..12952ae8a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m_core_reserved: m_core@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@b80ff000 { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ sound-wm8524 { -+ status = "disabled"; -+ }; -+ -+ wm8524: audio-codec { -+ status = "disabled"; -+ }; -+ -+ rpmsg_audio: rpmsg_audio { -+ compatible = "fsl,imx8mn-rpmsg-audio"; -+ model = "wm8524-audio"; -+ fsl,enable-lpa; -+ fsl,rpmsg-out; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MN_CLK_SAI3_IPG>, -+ <&clk IMX8MN_CLK_SAI3_ROOT>, -+ <&clk IMX8MN_CLK_SDMA3_ROOT>, -+ <&clk IMX8MN_AUDIO_PLL1_OUT>, -+ <&clk IMX8MN_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ status = "okay"; -+ }; -+ -+ imx8mn-cm7 { -+ compatible = "fsl,imx8mn-cm7"; -+ rsc-da = <0xb8000000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; -+ status = "okay"; -+ }; -+}; -+ -+&clk { -+ init-on-array = < -+ IMX8MN_CLK_UART4_ROOT -+ >; -+}; -+ -+/* -+ * ATTENTION: M core may use IPs like below -+ * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM -+ */ -+ -+&ecspi2 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts -new file mode 100644 -index 000000000..846f384dc ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mn-ddr4-evk.dts" -+ -+&usdhc2 { -+ /delete-property/ cd-gpios; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ cap-power-off-card; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts -index 7dfee715a..e5924dc81 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts -@@ -67,6 +67,8 @@ buck1_reg: BUCK1 { - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <850000>; -+ rohm,dvs-suspend-voltage = <750000>; - }; - - buck2_reg: BUCK2 { -@@ -76,13 +78,9 @@ buck2_reg: BUCK2 { - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; -- }; -- -- buck3_reg: BUCK3 { -- // BUCK5 in datasheet -- regulator-name = "buck3"; -- regulator-min-microvolt = <700000>; -- regulator-max-microvolt = <1350000>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ rohm,dvs-suspend-voltage = <0>; - }; - - buck4_reg: BUCK4 { -@@ -136,14 +134,6 @@ ldo3_reg: LDO3 { - regulator-always-on; - }; - -- ldo4_reg: LDO4 { -- regulator-name = "ldo4"; -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <1800000>; -- regulator-boot-on; -- regulator-always-on; -- }; -- - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; -@@ -154,3 +144,20 @@ ldo6_reg: LDO6 { - }; - }; - }; -+ -+&gpu { -+ assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, -+ <&clk IMX8MN_CLK_GPU_SHADER_SRC>, -+ <&clk IMX8MN_CLK_GPU_AXI>, -+ <&clk IMX8MN_CLK_GPU_AHB>, -+ <&clk IMX8MN_GPU_PLL>, -+ <&clk IMX8MN_CLK_GPU_CORE_DIV>, -+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>; -+ assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, -+ <&clk IMX8MN_GPU_PLL_OUT>, -+ <&clk IMX8MN_SYS_PLL1_800M>, -+ <&clk IMX8MN_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, -+ <400000000>, <400000000>; -+ status= "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts -new file mode 100644 -index 000000000..93e4090dc ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts -@@ -0,0 +1,120 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ mic_leds { -+ compatible = "gpio-leds"; -+ mic0 { -+ label = "mic0"; -+ gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic1 { -+ label = "mic1"; -+ gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic2 { -+ label = "mic2"; -+ gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic3 { -+ label = "mic3"; -+ gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic4 { -+ label = "mic4"; -+ gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic5 { -+ label = "mic5"; -+ gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic6 { -+ label = "mic6"; -+ gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ mic7 { -+ label = "mic7"; -+ gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ }; -+ -+ sw_keys { -+ compatible = "gpio-keys"; -+ -+ sw4: volume_down { -+ label = "Volume Down"; -+ gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ sw3: volume_up { -+ label = "Volume Up"; -+ gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ sw2: volume_mute { -+ label = "Volume Mute"; -+ gpios = <&pca9555 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ sw1: key_act { -+ label = "Key Act"; -+ gpios = <&pca9555 17 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ }; -+ -+ reg_vddext_3v3: regulator-vddext { -+ compatible = "regulator-fixed"; -+ regulator-name = "VDDEXT_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_swpdm_mute_irq: swpdm_mute_grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 -+ >; -+ }; -+ -+ pinctrl_pushbutton_irq: pushbutton_grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 -+ >; -+ }; -+}; -+ -+&i2c3 { -+ pca9555: gpio@21 { -+ compatible = "nxp,pca9555"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pushbutton_irq>; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ vcc-supply = <®_vddext_3v3>; -+ status = "okay"; -+ }; -+}; -+ -+&uart3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts -new file mode 100644 -index 000000000..d12173af9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts -@@ -0,0 +1,40 @@ -+/* -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ sound-wm8524 { -+ audio-asrc = <0>; -+ }; -+ sound-ak5558 { -+ asrc-controller = <&easrc>; -+ status = "okay"; -+ }; -+ sound-micfil { -+ status = "disabled"; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -+ -+&ak5558 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts -new file mode 100644 -index 000000000..d78aabaaf ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts -@@ -0,0 +1,82 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ ext_osc_22m: ext-osc-22m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <22579200>; -+ clock-output-names = "sclk0"; -+ }; -+ -+ ext_osc_24m: ext-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ clock-output-names = "sclk1"; -+ }; -+ -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ bitclock-master = <&pcm512x>; -+ frame-master = <&pcm512x>; -+ dac,24db_digital_gain; -+ dac,led_status; -+ }; -+}; -+ -+&i2c3 { -+ pcm512x: pcm512x@4d { -+ compatible = "ti,pcm5122"; -+ reg = <0x4d>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ clocks = <&ext_osc_22m>, <&ext_osc_24m>; -+ clock-names = "sclk0", "sclk1"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts -new file mode 100644 -index 000000000..f2434ad36 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts -@@ -0,0 +1,187 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+ -+/ { -+ model = "Freescale i.MX8MN EVK"; -+ compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial3 = &uart4; -+ mmc2 = &usdhc3; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ interrupt-affinity = <&A53_2>, <&A53_3>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ osc_24m: clock-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ clk_dummy: clock@7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ /* The clocks are configured by 1st OS */ -+ clk_200m: clock@8 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "200m"; -+ }; -+ clk_266m: clock@9 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <266000000>; -+ clock-output-names = "266m"; -+ }; -+ clk_80m: clock@10 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <80000000>; -+ clock-output-names = "80m"; -+ }; -+ -+ pci@bb800000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xbb800000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; -+ -+ aips3: bus@30800000 { -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x08000000 0x08000000 0x10000000>; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; -+ -+&uart4 { -+ clocks = <&osc_24m>, -+ <&osc_24m>; -+ clock-names = "ipg", "per"; -+ /delete-property/ dmas; -+ /delete-property/ dmas-names; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ clocks = <&clk_dummy>, -+ <&clk_266m>, -+ <&clk_200m>; -+ /delete-property/assigned-clocks; -+ /delete-property/assigned-clock-rates; -+ clock-names = "ipg", "ahb", "per"; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts -new file mode 100644 -index 000000000..99e7d8ab8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts -@@ -0,0 +1,63 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ dac,24db_digital_gain; -+ }; -+}; -+ -+&i2c3 { -+ pcm512x: pcm512x@4c { -+ compatible = "ti,pcm5122"; -+ reg = <0x4c>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts -new file mode 100644 -index 000000000..0f4baf7ba ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts -@@ -0,0 +1,63 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ dac,24db_digital_gain; -+ }; -+}; -+ -+&i2c3 { -+ pcm512x: pcm512x@4c { -+ compatible = "ti,pcm5142"; -+ reg = <0x4c>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts -new file mode 100644 -index 000000000..af6744a56 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts -@@ -0,0 +1,125 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+&{/} { -+ ivshm_rpmsg { -+ compatible = "fsl,ivshm-rpmsg"; -+ -+ rpmsg_console { -+ compatible = "fsl,rpmsg-console"; -+ id = <2>; -+ size = <16384>; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ -+ ivshmem_reserved: ivshmem@0xbba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00400000>; -+ }; -+ -+ pci_reserved: pci@0xbb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@0xbb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@0xb7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@0x93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x20000000>; -+ }; -+ }; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&gpio5 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ status = "disabled"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MN_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MN_CLK_24M>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts -new file mode 100644 -index 000000000..deb1c9dea ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019,2021 NXP -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+&adv_bridge { -+ status = "disabled"; -+}; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; /* 0: burst mode -+ * 1: non-burst mode with sync event -+ * 2: non-burst mode with sync pulse -+ */ -+ panel-width-mm = <68>; -+ panel-height-mm = <121>; -+ status = "okay"; -+ }; -+}; -+ -+&i2c2 { -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts -new file mode 100644 -index 000000000..48162d936 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mn-evk-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c2 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts -new file mode 100644 -index 000000000..91bce566c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts -@@ -0,0 +1,88 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+&{/} { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x93c00000>; -+ linux,cma-default; -+ }; -+ -+ ivshmem_reserved: ivshmem@0xbbb00000 { -+ no-map; -+ reg = <0 0xbbb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem2_reserved: ivshmem2@0xbba00000 { -+ no-map; -+ reg = <0 0xbba00000 0x0 0x00100000>; -+ }; -+ -+ pci_reserved: pci@0xbb800000 { -+ no-map; -+ reg = <0 0xbb800000 0x0 0x00200000>; -+ }; -+ -+ loader_reserved: loader@0xbb700000 { -+ no-map; -+ reg = <0 0xbb700000 0x0 0x00100000>; -+ }; -+ -+ jh_reserved: jh@0xb7c00000 { -+ no-map; -+ reg = <0 0xb7c00000 0x0 0x00400000>; -+ }; -+ -+ /* 512MB */ -+ inmate_reserved: inmate@0x93c00000 { -+ no-map; -+ reg = <0 0x93c00000 0x0 0x24000000>; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MN_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MN_CLK_24M>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts -new file mode 100644 -index 000000000..83bc36b39 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mn-evk.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m_core_reserved: m_core@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@b80ff000 { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ sound-wm8524 { -+ status = "disabled"; -+ }; -+ -+ wm8524: audio-codec { -+ status = "disabled"; -+ }; -+ -+ rpmsg_audio: rpmsg_audio { -+ compatible = "fsl,imx8mn-rpmsg-audio"; -+ model = "wm8524-audio"; -+ fsl,enable-lpa; -+ fsl,rpmsg-out; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MN_CLK_SAI3_IPG>, -+ <&clk IMX8MN_CLK_SAI3_ROOT>, -+ <&clk IMX8MN_CLK_SDMA3_ROOT>, -+ <&clk IMX8MN_AUDIO_PLL1_OUT>, -+ <&clk IMX8MN_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ status = "okay"; -+ }; -+ -+ imx8mn-cm7 { -+ compatible = "fsl,imx8mn-cm7"; -+ rsc-da = <0xb8000000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; -+ status = "okay"; -+ }; -+}; -+ -+&clk { -+ init-on-array = < -+ IMX8MN_CLK_UART4_ROOT -+ >; -+}; -+ -+/* -+ * ATTENTION: M core may use IPs like below -+ * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM -+ */ -+ -+&ecspi2 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts -index 8311b95de..7d7d6f3b9 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts -@@ -31,6 +31,8 @@ buck1: BUCK1{ - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; -+ nxp,dvs-run-voltage = <950000>; -+ nxp,dvs-standby-voltage = <750000>; - }; - - buck2: BUCK2 { -@@ -40,8 +42,6 @@ buck2: BUCK2 { - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; -- nxp,dvs-run-voltage = <950000>; -- nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ -@@ -112,17 +112,9 @@ ldo5: LDO5 { - }; - - &A53_0 { -- /delete-property/operating-points-v2; --}; -- --&A53_1 { -- /delete-property/operating-points-v2; --}; -- --&A53_2 { -- /delete-property/operating-points-v2; -+ cpu-supply = <&buck2>; - }; - --&A53_3 { -- /delete-property/operating-points-v2; -+&gpu { -+ status= "okay"; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi -index 4aa0dbd57..1493b546e 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi -@@ -28,6 +28,21 @@ memory@40000000 { - reg = <0x0 0x40000000 0 0x80000000>; - }; - -+ ir_recv: ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ir_recv>; -+ linux,autosuspend-period = <125>; -+ }; -+ -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1_gpio>; -+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; -+ }; -+ - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; -@@ -36,8 +51,97 @@ reg_usdhc2_vmmc: regulator-usdhc2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <12000>; -+ enable-active-high; -+ }; -+ -+ reg_audio_board: regulator-audio-board { -+ compatible = "regulator-fixed"; -+ regulator-name = "EXT_PWREN"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - enable-active-high; -+ startup-delay-us = <300000>; -+ gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; - }; -+ -+ -+ wm8524: audio-codec { -+ #sound-dai-cells = <0>; -+ compatible = "wlf,wm8524"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_wlf>; -+ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; -+ clock-names = "mclk"; -+ }; -+ -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ -+ sound-wm8524 { -+ compatible = "fsl,imx-audio-wm8524"; -+ model = "wm8524-audio"; -+ audio-cpu = <&sai3>; -+ audio-codec = <&wm8524>; -+ audio-routing = -+ "Line Out Jack", "LINEVOUTL", -+ "Line Out Jack", "LINEVOUTR"; -+ audio-asrc = <&easrc>; -+ }; -+ -+ sound-micfil { -+ compatible = "fsl,imx-audio-micfil"; -+ model = "imx-audio-micfil"; -+ cpu-dai = <&micfil>; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif1>; -+ spdif-out; -+ spdif-in; -+ }; -+ -+ sound-ak5558 { -+ compatible = "fsl,imx-audio-ak5558"; -+ model = "ak5558-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&ak5558>; -+ status = "disabled"; -+ }; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&easrc { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; - }; - - &fec1 { -@@ -55,10 +159,28 @@ mdio { - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; - }; - }; - }; - -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ - &i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; -@@ -68,10 +190,27 @@ &i2c1 { - - &i2c2 { - clock-frequency = <400000>; -- pinctrl-names = "default"; -+ pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; -+ pinctrl-1 = <&pinctrl_i2c2_gpio>; -+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; -+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - status = "okay"; - -+ adv_bridge: adv7535@3d { -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ status = "okay"; -+ -+ port { -+ adv7535_from_dsim: endpoint { -+ remote-endpoint = <&dsim_to_adv7535>; -+ }; -+ }; -+ }; -+ - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; -@@ -116,22 +255,241 @@ pca6416: gpio@20 { - }; - }; - -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ pinctrl-1 = <&pinctrl_i2c3_gpio>; -+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; -+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ ak4458_1: ak4458@10 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x10>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ status = "disabled"; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x12>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ status = "disabled"; -+ }; -+ -+ ak5558: ak5558@13 { -+ compatible = "asahi-kasei,ak5558"; -+ reg = <0x13>; -+ reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ status = "disabled"; -+ }; -+ -+ ak4497: ak4497@11 { -+ compatible = "asahi-kasei,ak4497"; -+ reg = <0x11>; -+ reset-gpios = <&pca6416 5 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_audio_board>; -+ DVDD-supply = <®_audio_board>; -+ status = "disabled"; -+ }; -+ -+ ov5640_mipi_0: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MN_CLK_CLKO1>; -+ clock-names = "xclk"; -+ assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; -+ assigned-clock-parents = <&clk IMX8MN_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ port { -+ ov5640_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ data-lanes = <1 2>; -+ clocks-lanes = <0>; -+ }; -+ }; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&lcdif { -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ dsim_to_adv7535: endpoint { -+ remote-endpoint = <&adv7535_from_dsim>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pdm>; -+ assigned-clocks = <&clk IMX8MN_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "okay"; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port@0 { -+ reg = <0>; -+ mipi1_sensor_ep: endpoint { -+ remote-endpoint = <&ov5640_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ }; -+}; -+ -+&sai2 { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI2>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MN_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, -+ <&clk IMX8MN_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, -+ <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", -+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ - &snvs_pwrkey { - status = "okay"; - }; - -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MN_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ - &uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - }; - -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MN_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; -+ bus-width = <4>; -+ keep-power-in-suspend; -+ non-removable; -+ wakeup-source; -+ /delete-property/ vmmc-supply; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ fsl,sdio-interrupt-enabled; -+ status = "okay"; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpio2>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; -+ disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; -@@ -176,6 +534,25 @@ &wdog1 { - }; - - &iomuxc { -+ pinctrl_csi_pwn: csi_pwn_grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 -+ >; -+ }; -+ -+ pinctrl_ir_recv: ir-recv { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f -+ >; -+ }; -+ - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -@@ -196,12 +573,42 @@ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 -+ MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 -+ MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 -+ MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 -+ MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 -+ MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 -+ >; -+ }; -+ - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - -+ pinctrl_i2c2_gpio: i2c2grp-gpio { -+ fsl,pins = < -+ MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 -+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 -+ >; -+ }; -+ -+ pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_gpio_wlf: gpiowlfgrp { -+ fsl,pins = < -+ MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 -+ >; -+ }; -+ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 -@@ -223,12 +630,75 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - -+ pinctrl_i2c3_gpio: i2c3grp-gpio { -+ fsl,pins = < -+ MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 -+ MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 -+ >; -+ }; -+ - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 -+ >; -+ }; -+ -+ pinctrl_pdm: pdmgrp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai2: sai2grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 -+ MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 -+ MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 -+ MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 -+ >; -+ }; -+ -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 -+ >; -+ }; -+ -+ - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 -@@ -241,6 +711,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 -+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 -+ >; -+ }; -+ - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 -@@ -248,6 +727,54 @@ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 -+ MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 -+ MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 -+ MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1_gpio: usdhc1grpgpio { -+ fsl,pins = < -+ MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 -+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 -+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 -+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 -+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 -+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 -+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 -+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 -+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 -+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 -+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 -@@ -343,4 +870,11 @@ pinctrl_wdog: wdoggrp { - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -+ -+ pinctrl_wlan: wlangrp { -+ fsl,pins = < -+ MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159 -+ >; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi -index 16c720288..9fd40f8e2 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -37,6 +38,8 @@ aliases { - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; -+ isi0 = &isi_0; -+ csi0 = &mipi_csi_1; - }; - - cpus { -@@ -144,6 +147,21 @@ opp-1500000000 { - }; - }; - -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ }; -+ - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -186,12 +204,86 @@ clk_ext4: clock-ext4 { - clock-output-names = "clk_ext4"; - }; - -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>, -+ <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>, -+ <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, -+ <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, -+ <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, -+ <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, -+ <&clk IMX8MN_DRAM_PLL>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", -+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", -+ "sys_pll1_800m", "dram_pll_div"; -+ }; -+ -+ power-domains { -+ compatible = "simple-bus"; -+ -+ /* HSIOMIX */ -+ hsiomix_pd: hsiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ domain-index = <0>; -+ #power-domain-cells = <0>; -+ domain-name = "hsiomix"; -+ clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; -+ }; -+ -+ usb_otg1_pd: usbotg1-pd{ -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <2>; -+ domain-name = "usb_otg1"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ /* GPU2D&3D */ -+ gpumix_pd: gpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ domain-index = <4>; -+ #power-domain-cells = <0>; -+ domain-name = "gpumix"; -+ clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, -+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>, -+ <&clk IMX8MN_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MN_CLK_GPU_AHB>; -+ }; -+ -+ dispmix_pd: dispmix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ domain-index = <9>; -+ #power-domain-cells = <0>; -+ domain-name = "dispmix"; -+ clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ }; -+ -+ mipi_pd: mipi-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ domain-index = <10>; -+ #power-domain-cells = <0>; -+ domain-name = "mipi"; -+ parent-domains = <&dispmix_pd>; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; -+ }; -+ - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - -- thermal-zones { -+ thermal: thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; -@@ -233,11 +325,156 @@ timer { - arm,no-tick-in-suspend; - }; - -+ lcdif_resets: lcdif-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ lcdif-soft-resetn { -+ compatible = "lcdif,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, -+ <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; -+ }; -+ -+ lcdif-clk-enable { -+ compatible = "lcdif,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, -+ <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; -+ }; -+ }; -+ -+ mipi_dsi_resets: mipi-dsi-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ dsi-soft-resetn { -+ compatible = "dsi,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>, -+ <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>; -+ }; -+ -+ dsi-clk-enable { -+ compatible = "dsi,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>, -+ <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>; -+ }; -+ -+ dsi-mipi-reset { -+ compatible = "dsi,mipi-reset"; -+ resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; -+ }; -+ }; -+ -+ isi_resets: isi-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ isi-soft-resetn { -+ compatible = "isi,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MN_ISI_PROC_CLK_RESET>, -+ <&dispmix_sft_rstn IMX8MN_ISI_APB_CLK_RESET>; -+ }; -+ -+ isi-clk-enable { -+ compatible = "isi,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MN_ISI_PROC_CLK_EN>, -+ <&dispmix_clk_en IMX8MN_ISI_APB_CLK_EN>; -+ }; -+ -+ }; -+ -+ mipi_csi_resets: mipi-csi-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ csi-soft-resetn { -+ compatible = "csi,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MN_MIPI_CSI_PCLK_RESET>, -+ <&dispmix_sft_rstn IMX8MN_MIPI_CSI_ACLK_RESET>; -+ }; -+ -+ csi-clk-enable { -+ compatible = "csi,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MN_MIPI_CSI_PCLK_EN>, -+ <&dispmix_clk_en IMX8MN_MIPI_CSI_ACLK_EN>; -+ }; -+ -+ csi-mipi-reset { -+ compatible = "csi,mipi-reset"; -+ resets = <&dispmix_mipi_rst IMX8MN_MIPI_S_RESET>; -+ }; -+ }; -+ -+ mipi2csi_gasket: gasket@32e28060 { -+ compatible = "syscon"; -+ reg = <0x0 0x32e28060 0x0 0x28>; -+ }; -+ -+ cameradev: camera { -+ compatible = "fsl,mxc-md", "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ isi_0: isi@0x32e20000 { -+ compatible = "fsl,imx8mn-isi"; -+ reg = <0x0 0x32e20000 0x0 0x2000>; -+ power-domains = <&dispmix_pd>; -+ interrupts = ; -+ interface = <2 0 2>; -+ clocks = <&clk IMX8MN_CLK_DISP_AXI>, -+ <&clk IMX8MN_CLK_DISP_APB>, -+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; -+ assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ assigned-clock-rates = <500000000>, <200000000>; -+ resets = <&isi_resets>; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ mipi_csi_1: csi@32e30000 { -+ compatible = "fsl,imx8mn-mipi-csi"; -+ reg = <0x0 0x32e30000 0x0 0x10000>; -+ interrupts = ; -+ clock-frequency = <333000000>; -+ clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, -+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ clock-names = "mipi_clk", "disp_axi", "disp_apb"; -+ assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; -+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; -+ assigned-clock-rates = <333000000>; -+ bus-width = <4>; -+ csi-gpr = <&mipi2csi_gasket>; -+ power-domains = <&mipi_pd>; -+ resets = <&mipi_csi_resets>; -+ status = "disabled"; -+ }; -+ }; -+ - soc@0 { -- compatible = "simple-bus"; -+ compatible = "fsl,imx8mn-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; -+ nvmem-cells = <&imx8mn_uid>; -+ nvmem-cell-names = "soc_unique_id"; -+ -+ caam_sm: caam-sm@00100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; -@@ -246,6 +483,149 @@ aips1: bus@30000000 { - #size-cells = <1>; - ranges; - -+ spba-bus@30000000 { -+ compatible = "fsl,spba-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x30000000 0x100000>; -+ ranges; -+ -+ easrc: easrc@300C0000 { -+ compatible = "fsl,imx8mn-easrc"; -+ reg = <0x300C0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; -+ clock-names = "mem"; -+ dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, -+ <&sdma2 18 23 0> , <&sdma2 19 23 0>, -+ <&sdma2 20 23 0> , <&sdma2 21 23 0>, -+ <&sdma2 22 23 0> , <&sdma2 23 23 0>; -+ dma-names = "ctx0_rx", "ctx0_tx", -+ "ctx1_rx", "ctx1_tx", -+ "ctx2_rx", "ctx2_tx", -+ "ctx3_rx", "ctx3_tx"; -+ fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; -+ fsl,asrc-rate = <8000>; -+ fsl,asrc-width = <16>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@30020000 { -+ compatible = "fsl,imx8mn-sai", "fsl,imx8mm-sai"; -+ reg = <0x30020000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_SAI2_IPG>, -+ <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI2_ROOT>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@30030000 { -+ compatible = "fsl,imx8mn-sai", "fsl,imx8mm-sai"; -+ reg = <0x30030000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_SAI3_IPG>, -+ <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI3_ROOT>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@30050000 { -+ compatible = "fsl,imx8mn-sai", "fsl,imx8mm-sai"; -+ reg = <0x30050000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_SAI5_IPG>, -+ <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI5_ROOT>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@30060000 { -+ compatible = "fsl,imx8mn-sai", "fsl,imx8mm-sai"; -+ reg = <0x30060000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_SAI6_IPG>, -+ <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI6_ROOT>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai7: sai@300b0000 { -+ compatible = "fsl,imx8mn-sai", "fsl,imx8mm-sai"; -+ reg = <0x300b0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_SAI7_IPG>, -+ <&clk IMX8MN_CLK_DUMMY>, -+ <&clk IMX8MN_CLK_SAI7_ROOT>, -+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ micfil: micfil@30080000 { -+ compatible = "fsl,imx8mm-micfil"; -+ reg = <0x30080000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&clk IMX8MN_CLK_PDM_IPG>, -+ <&clk IMX8MN_CLK_PDM_ROOT>, -+ <&clk IMX8MN_AUDIO_PLL1_OUT>, -+ <&clk IMX8MN_AUDIO_PLL2_OUT>, -+ <&clk IMX8MN_CLK_EXT3>; -+ clock-names = "ipg_clk", "ipg_clk_app", -+ "pll8k", "pll11k", "clkext3"; -+ dmas = <&sdma2 24 25 0x80000000>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ spdif1: spdif@30090000 { -+ compatible = "fsl,imx8mm-spdif"; -+ reg = <0x30090000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ -+ <&clk IMX8MN_CLK_24M>, /* rxtx0 */ -+ <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ -+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ -+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MN_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ }; -+ - gpio1: gpio@30200000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; -@@ -343,7 +723,7 @@ wdog3: watchdog@302a0000 { - }; - - sdma3: dma-controller@302b0000 { -- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; -+ compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, -@@ -354,7 +734,7 @@ sdma3: dma-controller@302b0000 { - }; - - sdma2: dma-controller@302c0000 { -- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; -+ compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, -@@ -381,9 +761,17 @@ ocotp: efuse@30350000 { - #address-cells = <1>; - #size-cells = <1>; - -+ imx8mn_uid: unique-id@410 { -+ reg = <0x4 0x8>; -+ }; -+ - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; -+ -+ fec_mac_address: mac-address@640 { -+ reg = <0x90 6>; -+ }; - }; - - anatop: anatop@30360000 { -@@ -392,6 +780,22 @@ anatop: anatop@30360000 { - reg = <0x30360000 0x10000>; - }; - -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; -+ clock-names = "ipg"; -+ }; -+ - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; -@@ -431,7 +835,9 @@ clk: clock-controller@30380000 { - <&clk IMX8MN_CLK_NOC>, - <&clk IMX8MN_CLK_AUDIO_AHB>, - <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, -- <&clk IMX8MN_SYS_PLL3>; -+ <&clk IMX8MN_SYS_PLL3>, -+ <&clk IMX8MN_AUDIO_PLL1>, -+ <&clk IMX8MN_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, - <&clk IMX8MN_ARM_PLL_OUT>, - <&clk IMX8MN_SYS_PLL3_OUT>, -@@ -439,7 +845,9 @@ clk: clock-controller@30380000 { - assigned-clock-rates = <0>, <0>, <0>, - <400000000>, - <400000000>, -- <600000000>; -+ <600000000>, -+ <393216000>, -+ <361267200>; - }; - - src: reset-controller@30390000 { -@@ -680,11 +1088,12 @@ mu: mailbox@30aa0000 { - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_MU_ROOT>; -+ clock-names = "mu"; - #mbox-cells = <2>; - }; - - usdhc1: mmc@30b40000 { -- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; -+ compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, -@@ -698,7 +1107,7 @@ usdhc1: mmc@30b40000 { - }; - - usdhc2: mmc@30b50000 { -- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; -+ compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, -@@ -712,7 +1121,7 @@ usdhc2: mmc@30b50000 { - }; - - usdhc3: mmc@30b60000 { -- compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; -+ compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, -@@ -725,8 +1134,24 @@ usdhc3: mmc@30b60000 { - status = "disabled"; - }; - -+ flexspi: spi@30bb0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mm-fspi"; -+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, -+ <&clk IMX8MN_CLK_QSPI_ROOT>; -+ clock-names = "fspi", "fspi_en"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MN_CLK_QSPI>; -+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; -+ status = "disabled"; -+ }; -+ - sdma1: dma-controller@30bd0000 { -- compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; -+ compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, -@@ -737,7 +1162,7 @@ sdma1: dma-controller@30bd0000 { - }; - - fec1: ethernet@30be0000 { -- compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; -+ compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , -@@ -753,18 +1178,47 @@ fec1: ethernet@30be0000 { - assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, - <&clk IMX8MN_CLK_ENET_TIMER>, - <&clk IMX8MN_CLK_ENET_REF>, -- <&clk IMX8MN_CLK_ENET_TIMER>; -+ <&clk IMX8MN_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, - <&clk IMX8MN_SYS_PLL2_100M>, -- <&clk IMX8MN_SYS_PLL2_125M>; -- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; -+ <&clk IMX8MN_SYS_PLL2_125M>, -+ <&clk IMX8MN_SYS_PLL2_50M>; -+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; -+ nvmem-cells = <&fec_mac_address>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ fsl,stop-mode = <&gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; - status = "disabled"; - }; - - }; - -+ noc: interconnect@32700000 { -+ compatible = "fsl,imx8mn-noc", "fsl,imx8m-noc"; -+ reg = <0x32700000 0x100000>; -+ clocks = <&clk IMX8MN_CLK_NOC>; -+ fsl,ddrc = <&ddrc>; -+ #interconnect-cells = <1>; -+ operating-points-v2 = <&noc_opp_table>; -+ -+ noc_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-100M { -+ opp-hz = /bits/ 64 <100000000>; -+ }; -+ opp-600M { -+ opp-hz = /bits/ 64 <600000000>; -+ }; -+ opp-800M { -+ opp-hz = /bits/ 64 <800000000>; -+ }; -+ }; -+ }; -+ - aips4: bus@32c00000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; -@@ -772,6 +1226,69 @@ aips4: bus@32c00000 { - #size-cells = <1>; - ranges; - -+ lcdif: lcd-controller@32e00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mn-lcdif"; -+ reg = <0x32e00000 0x10000>; -+ clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, -+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>, -+ <&clk IMX8MN_CLK_DISP_AXI>, -+ <&clk IMX8MN_CLK_DISP_APB>; -+ assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>, -+ <&clk IMX8MN_SYS_PLL2_1000M>, -+ <&clk IMX8MN_SYS_PLL1_800M>; -+ assigned-clock-rate = <594000000>, -+ <500000000>, -+ <200000000>; -+ interrupts = ; -+ resets = <&lcdif_resets>; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ -+ lcdif_disp0: port@0 { -+ reg = <0>; -+ -+ lcdif_to_dsim: endpoint { -+ remote-endpoint = <&dsim_from_lcdif>; -+ }; -+ }; -+ }; -+ -+ mipi_dsi: dsi_controller@32e10000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mn-mipi-dsim"; -+ reg = <0x32e10000 0x400>; -+ clocks = <&clk IMX8MN_CLK_DSI_CORE>, -+ <&clk IMX8MN_CLK_DSI_PHY_REF>; -+ clock-names = "cfg", "pll-ref"; -+ assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, -+ <&clk IMX8MN_CLK_DSI_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, -+ <&clk IMX8MN_CLK_24M>; -+ assigned-clock-rates = <266000000>, -+ <12000000>; -+ interrupts = ; -+ resets = <&mipi_dsi_resets>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ dsim_from_lcdif: endpoint { -+ remote-endpoint = <&lcdif_to_dsim>; -+ }; -+ }; -+ }; -+ -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif_disp0>; -+ }; -+ - usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; - reg = <0x32e40000 0x200>; -@@ -782,6 +1299,7 @@ usbotg1: usb@32e40000 { - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; -+ power-domains = <&usb_otg1_pd>; - status = "disabled"; - }; - -@@ -847,6 +1365,38 @@ ddr-pmu@3d800000 { - }; - }; - -+ gpu: gpu@38000000 { -+ compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ reg = <0x0 0x38000000 0x0 0x40000>, -+ <0x0 0x40000000 0x0 0x80000000>, -+ <0x0 0x0 0x0 0x8000000>; -+ reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; -+ interrupts = ; -+ interrupt-names = "irq_3d"; -+ clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, -+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>, -+ <&clk IMX8MN_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MN_CLK_GPU_AHB>; -+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; -+ assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, -+ <&clk IMX8MN_CLK_GPU_SHADER_SRC>, -+ <&clk IMX8MN_CLK_GPU_AXI>, -+ <&clk IMX8MN_CLK_GPU_AHB>, -+ <&clk IMX8MN_GPU_PLL>, -+ <&clk IMX8MN_CLK_GPU_CORE_DIV>, -+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>; -+ assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, -+ <&clk IMX8MN_GPU_PLL_OUT>, -+ <&clk IMX8MN_SYS_PLL1_800M>, -+ <&clk IMX8MN_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, -+ <600000000>, <600000000>; -+ power-domains = <&gpumix_pd>; -+ status = "disabled"; -+ }; -+ - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; -@@ -854,4 +1404,40 @@ usbphynop1: usbphynop1 { - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; -+ -+ dispmix-reset { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { -+ compatible = "fsl,imx8mn-dispmix-sft-rstn"; -+ reg = <0x0 0x32e28000 0x0 0x4>; -+ clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_clk_en: dispmix-clk-en@32e28004 { -+ compatible = "fsl,imx8mn-dispmix-clk-en"; -+ reg = <0x0 0x32e28004 0x0 0x4>; -+ clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { -+ compatible = "fsl,imx8mn-dispmix-mipi-rst"; -+ reg = <0x0 0x32e28008 0x0 0x4>; -+ clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts -new file mode 100755 -index 000000000..a7667d74b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts -@@ -0,0 +1,865 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8mp.dtsi" -+ -+/ { -+ model = "NXP i.MX8MP SOM on AB2"; -+ compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_led>; -+ -+ status { -+ label = "yellow:status"; -+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x0 0x40000000 0 0xc0000000>, -+ <0x1 0x00000000 0 0xc0000000>; -+ }; -+ -+ ak4458_reset: gpio-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; -+ #reset-cells = <0>; -+ initially-in-reset; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -+ regulator-name = "VSD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr { -+ compatible = "regulator-fixed"; -+ regulator-name = "ab2_ana_pwr"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ab2_vdd_pwr_5v0"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ sound-micfil { -+ compatible = "fsl,imx-audio-micfil"; -+ model = "imx-audio-micfil"; -+ cpu-dai = <&micfil>; -+ }; -+ -+ sound-xcvr { -+ compatible = "fsl,imx-audio-xcvr"; -+ model = "imx-audio-xcvr"; -+ cpu-dai = <&xcvr>; -+ }; -+ -+ sound-ak4458 { -+ compatible = "fsl,imx-audio-ak4458"; -+ model = "ak4458-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&ak4458_1>, <&ak4458_2>; -+ }; -+ -+ sound-ak5552 { -+ compatible = "fsl,imx-audio-ak5552"; -+ model = "ak5552-audio"; -+ audio-cpu = <&sai3>; -+ audio-codec = <&ak5552>; -+ }; -+}; -+ -+&{/busfreq} { -+ status = "disabled"; -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2>; -+}; -+ -+&A53_1 { -+ cpu-supply = <&buck2>; -+}; -+ -+&A53_2 { -+ cpu-supply = <&buck2>; -+}; -+ -+&A53_3 { -+ cpu-supply = <&buck2>; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; -+ status = "okay"; -+}; -+ -+&pwm4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm4>; -+ status = "okay"; -+}; -+ -+&ecspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev1: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&eqos { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_eqos>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ eee-broken-1000t; -+ }; -+ }; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic: pca9450@25 { -+ reg = <0x25>; -+ compatible = "nxp,pca9450c"; -+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ -+ pinctrl-0 = <&pinctrl_pmic>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ -+ regulators { -+ buck1: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <3125>; -+ }; -+ -+ buck2: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <3125>; -+ nxp,dvs-run-voltage = <950000>; -+ nxp,dvs-standby-voltage = <850000>; -+ }; -+ -+ buck4: BUCK4{ -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5: BUCK5{ -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6: BUCK6 { -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo5: LDO5 { -+ regulator-name = "LDO5"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pca6408_2: gpio@20 { -+ compatible = "ti,tca6408"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca6416_2: gpio@21 { -+ compatible = "ti,tca6416"; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ ak4458_1: ak4458@10 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x10>; -+ resets = <&ak4458_reset>; -+ AVDD-supply = <®_ab2_ana_pwr>; -+ DVDD-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ ak4458_2: ak4458@11 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x11>; -+ resets = <&ak4458_reset>; -+ AVDD-supply = <®_ab2_ana_pwr>; -+ DVDD-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ ak4458_3: ak4458@12 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x12>; -+ resets = <&ak4458_reset>; -+ AVDD-supply = <®_ab2_ana_pwr>; -+ DVDD-supply = <®_ab2_ana_pwr>; -+ }; -+ -+ ak5552: ak5552@13 { -+ compatible = "asahi-kasei,ak5552"; -+ reg = <0x13>; -+ reset-gpios = <&pca6416 2 GPIO_ACTIVE_LOW>; -+ AVDD-supply = <®_ab2_ana_pwr>; -+ DVDD-supply = <®_ab2_ana_pwr>; -+ }; -+}; -+ -+&irqsteer_hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_blk_ctrl { -+ status = "okay"; -+}; -+ -+&hdmi_pavi { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmiphy { -+ status = "okay"; -+}; -+ -+&lcdif3 { -+ status = "okay"; -+}; -+ -+&easrc { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pdm>; -+ assigned-clocks = <&clk IMX8MP_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&xcvr { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_xcvr>; -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&sdma2 { -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+&uart2 { -+ /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; -+ assigned-clock-rates = <400000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; -+ assigned-clock-rates = <400000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; -+ assigned-clock-rates = <400000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 -+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 -+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 -+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 -+ >; -+ }; -+ -+ pinctrl_pwm1: pwm1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 -+ >; -+ }; -+ -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 -+ >; -+ }; -+ -+ pinctrl_pwm4: pwm4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 -+ >; -+ }; -+ -+ pinctrl_ecspi2: ecspi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 -+ >; -+ }; -+ -+ pinctrl_ecspi2_cs: ecspi2cs { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 -+ >; -+ }; -+ -+ pinctrl_eqos: eqosgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 -+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 -+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 -+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 -+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 -+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 -+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 -+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 -+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f -+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f -+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f -+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f -+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f -+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f -+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 -+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 -+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 -+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 -+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 -+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 -+ >; -+ }; -+ -+ pinctrl_gpio_led: gpioledgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 -+ >; -+ }; -+ -+ pinctrl_ab2_ana_pwr: ab2anapwrgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 -+ >; -+ }; -+ -+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 -+ >; -+ }; -+ -+ pinctrl_pdm: pdmgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 -+ MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 -+ MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 -+ >; -+ }; -+ -+ pinctrl_xcvr: xcvrgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6 -+ MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 -+ MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 -+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 -+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 -+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 -+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 -+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 -+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 -+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 -+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 -+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 -+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 -+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 -+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 -+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 -+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 -+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 -+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 -+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 -+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 -+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 -+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 -+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 -+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 -+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_vc8000e { -+ status = "okay"; -+}; -+ -+&gpu_3d { -+ status = "okay"; -+}; -+ -+&gpu_2d { -+ status = "okay"; -+}; -+ -+&ml_vipsi { -+ status = "okay"; -+}; -+ -+&mix_gpu_ml { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts -new file mode 100644 -index 000000000..649f08275 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts -@@ -0,0 +1,214 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ model = "NXP i.MX8MPlus DDR4 EVK board"; -+ -+ gpio-leds { -+ status = "disabled"; -+ }; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&clk { -+ assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, -+ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, -+ <&clk IMX8MP_AUDIO_PLL1>, -+ <&clk IMX8MP_AUDIO_PLL2>, -+ <&clk IMX8MP_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL3_OUT>; -+ assigned-clock-rates = <400000000>, -+ <600000000>, -+ <393216000>, -+ <361267200>, -+ <1039500000>; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+ nand-on-flash-bbt; -+}; -+ -+&gpu_2d { -+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>, -+ <&clk IMX8MP_GPU_PLL>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_GPU_PLL_OUT>, -+ <&clk IMX8MP_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <300000000>, <600000000>; -+}; -+ -+&gpu_3d { -+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>, -+ <&clk IMX8MP_GPU_PLL>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_GPU_PLL_OUT>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <800000000>, <800000000>, -+ <600000000>, <300000000>, -+ <600000000>; -+}; -+ -+&ml_vipsi { -+ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, -+ <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <800000000>, <300000000>; -+}; -+ -+&pcie{ -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ assigned-clock-rates = <400000000>, <10000000>; -+}; -+ -+&pcie_ep{ -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ assigned-clock-rates = <400000000>, <10000000>; -+}; -+ -+&usb_dwc3_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&usb_dwc3_1 { -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&vpu_g1 { -+ -+ assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_VPU_PLL_OUT>; -+ assigned-clock-rates = <600000000>, <600000000>, <600000000>; -+}; -+ -+&vpu_g2 { -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_VPU_PLL_OUT>; -+ assigned-clock-rates = <500000000>, <600000000>; -+}; -+ -+&vpu_vc8000e { -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VPU_PLL_OUT>; -+ assigned-clock-rates = <400000000>, <600000000>; -+}; -+ -+&lcdif1 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <400000000>, <200000000>; -+}; -+ -+&lcdif2 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <400000000>, <200000000>; -+}; -+ -+&lcdif3 { -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_APB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_133M>; -+ assigned-clock-rates = <400000000>, <133000000>; -+ thres-low = <2 3>; /* (FIFO * 2 / 3) */ -+ thres-high = <3 3>; /* (FIFO * 3 / 3) */ -+ status = "okay"; -+}; -+ -+&isi_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <400000000>, <200000000>; -+}; -+ -+&isi_1 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <400000000>, <200000000>; -+}; -+ -+&mipi_csi_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&isp_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&isp_1 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&iomuxc { -+ pinctrl_gpmi_nand: gpmi-nand { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x00000096 -+ MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x00000096 -+ MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x00000096 -+ MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x00000096 -+ MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x00000096 -+ MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x00000096 -+ MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x00000096 -+ MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x00000096 -+ MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x00000056 -+ MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x00000096 -+ MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x00000096 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts -new file mode 100644 -index 000000000..671a40a2a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts -@@ -0,0 +1,132 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020-2021 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&iomuxc { -+ pinctrl_csi1_pwn: csi1_pwn_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 -+ >; -+ }; -+ -+ pinctrl_csi1_rst: csi1_rst_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 -+ >; -+ }; -+}; -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ basler_camera@36 { -+ compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; -+ reg = <0x36>; -+ csi_id = <0x00>; -+ status = "okay"; -+ -+ port { -+ basler_ep_0: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ link-frequencies = /bits/ 64 <750000000>; -+ -+ max-lane-frequency = /bits/ 64 <750000000>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ max-data-rate = /bits/ 64 <0>; -+ -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ /delete-node/ov5640_mipi@3c; -+ -+ ov2775_1: ov2775_mipi@36 { -+ compatible = "ovti,ov2775"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ csi_id = <1>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ -+ port { -+ ov2775_mipi_1_ep: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ -+ remote-endpoint = <&mipi_csi1_ep>; -+ }; -+ }; -+ }; -+ -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ port@0 { -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&basler_ep_0>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ status = "okay"; -+ -+ port@1 { -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&ov2775_mipi_1_ep>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&isp_1 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts -new file mode 100644 -index 000000000..996711282 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts -@@ -0,0 +1,81 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ basler_camera@36 { -+ compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; -+ reg = <0x36>; -+ csi_id = <0x00>; -+ status = "okay"; -+ -+ port { -+ basler_ep_0: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ link-frequencies = /bits/ 64 <750000000>; -+ -+ max-lane-frequency = /bits/ 64 <750000000>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ max-data-rate = /bits/ 64 <0>; -+ -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ port@0 { -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&basler_ep_0>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ status = "okay"; -+}; -+ -+&ov5640_1 { -+ powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ csi_id = <1>; -+ -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isi_1 { -+ status = "okay"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts -new file mode 100644 -index 000000000..98c159c26 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2020 Basler AG -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ basler_camera_vvcam@36 { -+ compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; -+ reg = <0x36>; -+ csi_id = <0x00>; -+ status = "okay"; -+ -+ port { -+ basler_ep_0: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ link-frequencies = /bits/ 64 <750000000>; -+ max-lane-frequency = /bits/ 64 <750000000>; -+ max-pixel-frequency = /bits/ 64 <500000000>; -+ max-data-rate = /bits/ 64 <0>; -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ port@0 { -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&basler_ep_0>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ /delete-node/port@1; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -+ -+&i2c3 { -+ /delete-node/ov5640_mipi@3c; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts -new file mode 100644 -index 000000000..80285c457 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts -@@ -0,0 +1,95 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2021 -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000026 -+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000026 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 -+ >; -+ }; -+ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 -+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 -+ >; -+ }; -+}; -+ -+&dsp { -+ compatible = "fsl,imx8mp-hifi4"; -+ reg = <0x0 0x3B6E8000 0x0 0x88000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_i2c3>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, -+ <&clk IMX8MP_CLK_I2C3_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, -+ <&clk IMX8MP_CLK_UART4_ROOT>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3", -+ "per_clk1", "per_clk2", "per_clk3", "per_clk4", "per_clk5", "per_clk6", -+ "per_clk7"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&audiomix_pd>; -+ mbox-names = "tx0", "rx0", "rxdb0"; -+ mboxes = <&mu2 0 0>, -+ <&mu2 1 0>, -+ <&mu2 3 0>; -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ syscon = <&audio_blk_ctrl>; -+ status = "okay"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&easrc { -+ status = "disabled"; -+}; -+ -+&codec { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts -new file mode 100644 -index 000000000..b86e2eca4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020-2021 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ basler_0: basler_camera_vvcam@36 { -+ compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; -+ reg = <0x36>; -+ csi_id = <0x00>; -+ status = "okay"; -+ -+ port { -+ basler_ep_0: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ link-frequencies = /bits/ 64 <750000000>; -+ -+ max-lane-frequency = /bits/ 64 <750000000>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ max-data-rate = /bits/ 64 <0>; -+ -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ /delete-node/ov5640_mipi@3c; -+ -+ basler_1: basler_camera_vvcam@36 { -+ compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; -+ reg = <0x36>; -+ csi_id = <0x01>; -+ status = "okay"; -+ -+ port { -+ basler_ep_1: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ link-frequencies = /bits/ 64 <750000000>; -+ -+ max-lane-frequency = /bits/ 64 <750000000>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ max-data-rate = /bits/ 64 <0>; -+ -+ remote-endpoint = <&mipi_csi1_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&isp_1 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ clock-frequency = <266000000>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; -+ assigned-clock-rates = <266000000>; -+ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&basler_ep_0>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&basler_ep_1>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts -new file mode 100644 -index 000000000..9d7d0f9a5 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts -@@ -0,0 +1,132 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ ov2775_0: ov2775_mipi@36 { -+ compatible = "ovti,ov2775"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ -+ port { -+ ov2775_mipi_0_ep: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ /delete-node/ov5640_mipi@3c; -+ -+ ov2775_1: ov2775_mipi@36 { -+ compatible = "ovti,ov2775"; -+ reg = <0x36>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <1>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ -+ port { -+ ov2775_mipi_1_ep: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ remote-endpoint = <&mipi_csi1_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&isp_1 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ clock-frequency = <266000000>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; -+ assigned-clock-rates = <266000000>; -+ -+ port@0 { -+ endpoint { -+ remote-endpoint = <&ov2775_mipi_0_ep>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&ov2775_mipi_1_ep>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts -new file mode 100644 -index 000000000..800cdbafc ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// Copyright 2020 NXP -+ -+#include "imx8mp-evk.dts" -+ -+/delete-node/&spidev1; -+ -+&ecspi2 { -+ #address-cells = <0>; -+ /delete-property/cs-gpios; -+ spi-slave; -+}; -+ -+&pinctrl_ecspi2_cs { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x82 -+ >; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts -new file mode 100644 -index 000000000..0b778945b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&flexcan2 { -+ status = "okay";/* can2 pin conflict with pdm */ -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts -new file mode 100644 -index 000000000..771609b35 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts -@@ -0,0 +1,93 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ ext_osc_22m: ext-osc-22m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <22579200>; -+ clock-output-names = "sclk0"; -+ }; -+ -+ ext_osc_24m: ext-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ clock-output-names = "sclk1"; -+ }; -+ -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ bitclock-master = <&pcm512x>; -+ frame-master = <&pcm512x>; -+ dac,24db_digital_gain; -+ dac,led_status; -+ }; -+}; -+ -+&i2c3 { -+ pcm512x: pcm512x@4d { -+ compatible = "ti,pcm5122"; -+ reg = <0x4d>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ clocks = <&ext_osc_22m>, <&ext_osc_24m>; -+ clock-names = "sclk0", "sclk1"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts -new file mode 100644 -index 000000000..be538f510 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts -@@ -0,0 +1,175 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+ -+/ { -+ model = "Freescale i.MX8MP EVK"; -+ compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial3 = &uart4; -+ mmc2 = &usdhc3; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ interrupt-affinity = <&A53_2>, <&A53_3>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ clk_dummy: clock@7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ /* The clocks are configured by 1st OS */ -+ clk_400m: clock@8 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "200m"; -+ }; -+ -+ clk_266m: clock@9 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <266000000>; -+ clock-output-names = "266m"; -+ }; -+ -+ osc_24m: clock@1 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ pci@fd700000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 155 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 156 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xfd700000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ -+ aips3: bus@30800000 { -+ compatible = "simple-bus"; -+ reg = <0x30800000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; -+ -+&uart4 { -+ clocks = <&osc_24m>, -+ <&osc_24m>; -+ clock-names = "ipg", "per"; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ clocks = <&clk_dummy>, -+ <&clk_266m>, -+ <&clk_400m>; -+ clock-names = "ipg", "ahb", "per"; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts -new file mode 100644 -index 000000000..b1255ae42 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts -@@ -0,0 +1,74 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ dac,24db_digital_gain; -+ }; -+}; -+ -+&i2c3 { -+ pcm512x: pcm512x@4c { -+ compatible = "ti,pcm5122"; -+ reg = <0x4c>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts -new file mode 100644 -index 000000000..41261147b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts -@@ -0,0 +1,74 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ reg_3v3_vext: regulator-3v3-vext { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3_VEXT"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sound-pcm512x { -+ compatible = "fsl,imx-audio-pcm512x"; -+ model = "pcm512x-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&pcm512x>; -+ format = "i2s"; -+ audio-widgets = -+ "Line", "Left Line Out Jack", -+ "Line", "Right Line Out Jack"; -+ audio-routing = -+ "Left Line Out Jack", "OUTL", -+ "Right Line Out Jack", "OUTR"; -+ dac,24db_digital_gain; -+ }; -+}; -+ -+&i2c3 { -+ pcm512x: pcm512x@4c { -+ compatible = "ti,pcm5142"; -+ reg = <0x4c>; -+ AVDD-supply = <®_3v3_vext>; -+ DVDD-supply = <®_3v3_vext>; -+ CPVDD-supply = <®_3v3_vext>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0xd6 -+ >; -+ }; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts -new file mode 100644 -index 000000000..69fe4aefd ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&lvds_bridge { -+ split-mode; -+}; -+ -+&ldb { -+ fsl,dual-channel; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts -new file mode 100644 -index 000000000..3ea60784b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ lvds0_panel { -+ compatible = "jdi,tx26d202vm0bwa"; -+ backlight = <&lvds_backlight>; -+ -+ port { -+ panel_lvds_in: endpoint { -+ remote-endpoint = <&lvds_out>; -+ }; -+ }; -+ }; -+}; -+ -+/delete-node/ &lvds_bridge; -+ -+&ldb { -+ status = "okay"; -+ fsl,dual-channel; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds_out: endpoint { -+ remote-endpoint = <&panel_lvds_in>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts -new file mode 100644 -index 000000000..ea3870f71 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts -@@ -0,0 +1,170 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ model = "NXP i.MX8MPlus EVK board in Nominal Drive Mode"; -+}; -+ -+&clk { -+ assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, -+ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, -+ <&clk IMX8MP_AUDIO_PLL1>, -+ <&clk IMX8MP_AUDIO_PLL2>, -+ <&clk IMX8MP_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL3_OUT>; -+ assigned-clock-rates = <400000000>, -+ <600000000>, -+ <393216000>, -+ <361267200>, -+ <1039500000>; -+}; -+ -+&gpu_2d { -+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>, -+ <&clk IMX8MP_GPU_PLL>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_GPU_PLL_OUT>, -+ <&clk IMX8MP_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <300000000>, <600000000>; -+}; -+ -+&gpu_3d { -+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>, -+ <&clk IMX8MP_GPU_PLL>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_GPU_PLL_OUT>, -+ <&clk IMX8MP_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <800000000>, -+ <600000000>, <300000000>, -+ <600000000>; -+}; -+ -+&ml_vipsi { -+ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, -+ <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <800000000>, <300000000>; -+}; -+ -+&pcie{ -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ assigned-clock-rates = <400000000>, <10000000>; -+}; -+ -+&pcie_ep{ -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ assigned-clock-rates = <400000000>, <10000000>; -+}; -+ -+&usb_dwc3_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&usb_dwc3_1 { -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&vpu_g1 { -+ -+ assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_VPU_PLL_OUT>; -+ assigned-clock-rates = <600000000>, <600000000>, <600000000>; -+}; -+ -+&vpu_g2 { -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_VPU_PLL_OUT>; -+ assigned-clock-rates = <500000000>, <600000000>; -+}; -+ -+&vpu_vc8000e { -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VPU_PLL_OUT>; -+ assigned-clock-rates = <400000000>, <600000000>; -+}; -+ -+&lcdif1 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <400000000>, <200000000>; -+}; -+ -+&lcdif2 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <400000000>, <200000000>; -+}; -+ -+&lcdif3 { -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_APB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_133M>; -+ assigned-clock-rates = <400000000>, <133000000>; -+ thres-low = <2 3>; /* (FIFO * 2 / 3) */ -+ thres-high = <3 3>; /* (FIFO * 3 / 3) */ -+ status = "okay"; -+}; -+ -+&isi_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <400000000>, <200000000>; -+}; -+ -+&isi_1 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <400000000>, <200000000>; -+}; -+ -+&mipi_csi_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&isp_0 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -+ -+&isp_1 { -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <400000000>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts -new file mode 100644 -index 000000000..46edd382d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts -@@ -0,0 +1,109 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&iomuxc { -+ pinctrl_csi1_pwn: csi1_pwn_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 -+ >; -+ }; -+ -+ pinctrl_csi1_rst: csi1_rst_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 -+ >; -+ }; -+}; -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ ov2775_0: ov2775_mipi@36 { -+ compatible = "ovti,ov2775"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ -+ port { -+ ov2775_mipi_0_ep: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ max-pixel-frequency = /bits/ 64 <266000000>; -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ -+ }; -+}; -+ -+&i2c3 { -+ /delete-node/ov2775_mipi@36; -+}; -+ -+&ov5640_1 { -+ pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; -+ csi_id = <1>; -+ -+ status = "okay"; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isi_1 { -+ status = "okay"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ port@0 { -+ endpoint { -+ remote-endpoint = <&ov2775_mipi_0_ep>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts -new file mode 100644 -index 000000000..e241e3646 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp-evk.dts" -+ -+&i2c2 { -+ /delete-node/ov5640_mipi@3c; -+ -+ ov2775_0: ov2775_mipi@36 { -+ compatible = "ovti,ov2775"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ -+ port { -+ ov2775_mipi_0_ep: endpoint { -+ data-lanes = <1 2 3 4>; -+ clock-lanes = <0>; -+ max-pixel-frequency = /bits/ 64 <500000000>; -+ remote-endpoint = <&mipi_csi0_ep>; -+ }; -+ }; -+ -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ ov5640_1: ov5640_mipi@3c { -+ status = "disabled"; -+ }; -+ -+ ov2775_1: ov2775_mipi@36 { -+ compatible = "ovti,ov2775"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <1>; -+ pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "disabled"; -+ }; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+}; -+ -+&isp_0 { -+ status = "okay"; -+}; -+ -+&dewarp { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ port@0 { -+ endpoint { -+ remote-endpoint = <&ov2775_mipi_0_ep>; -+ data-lanes = <4>; -+ csis-hs-settle = <16>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts -new file mode 100644 -index 000000000..3ed4f2121 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp-evk.dts" -+ -+&pcie{ -+ status = "disabled"; -+}; -+ -+&pcie_ep{ -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts -new file mode 100644 -index 000000000..8110748ab ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019,2021 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+&adv_bridge { -+ status = "disabled"; -+}; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; /* 0: burst mode -+ * 1: non-burst mode with sync event -+ * 2: non-burst mode with sync pulse -+ */ -+ panel-width-mm = <68>; -+ panel-height-mm = <121>; -+ status = "okay"; -+ }; -+}; -+ -+&i2c2 { -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts -new file mode 100644 -index 000000000..fd4d2fb68 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mp-evk-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c2 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts -new file mode 100644 -index 000000000..747805e4c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ interrupt-parent = <&gic>; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ }; -+}; -+ -+&cpu_pd_wait { -+ /delete-property/ compatible; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&{/busfreq} { -+ status = "disabled"; -+}; -+ -+&{/reserved-memory} { -+ jh_reserved: jh@fdc00000 { -+ no-map; -+ reg = <0 0xfdc00000 0x0 0x400000>; -+ }; -+ -+ loader_reserved: loader@fdb00000 { -+ no-map; -+ reg = <0 0xfdb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem_reserved: ivshmem@fda00000 { -+ no-map; -+ reg = <0 0xfda00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem2_reserved: ivshmem2@fd900000 { -+ no-map; -+ reg = <0 0xfd900000 0x0 0x00100000>; -+ }; -+ -+ pci_reserved: pci@fd700000 { -+ no-map; -+ reg = <0 0xfd700000 0x0 0x00200000>; -+ }; -+ -+ inmate_reserved: inmate@c0000000 { -+ no-map; -+ reg = <0 0xc0000000 0x0 0x3d700000>; -+ }; -+}; -+ -+&{/reserved-memory/linux,cma} { -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x60000000>; -+}; -+ -+&iomuxc { -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 -+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 -+ >; -+ }; -+}; -+ -+&usdhc3 { -+ status = "disabled"; -+}; -+ -+&uart4 { -+ /delete-property/ dmas; -+ /delete-property/ dma-names; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ status = "disabled"; -+}; -+ -+&uart2 { -+ /* uart4 is used by the 2nd OS, so configure pin and clk */ -+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+}; -+ -+&usdhc2 { -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts -new file mode 100644 -index 000000000..c25e61f0f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts -@@ -0,0 +1,211 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ aliases { -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c_rpbus_3; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@55000000 { -+ reg = <0 0x55000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@55008000 { -+ reg = <0 0x55008000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@55400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x55400000 0 0x100000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@550ff000 { -+ reg = <0 0x550ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ audio_reserved: audio@0x81000000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0x81000000 0 0x10000000>; -+ }; -+ -+ micfil_reserved: mic_rpmsg@91000000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0x91000000 0 0x100000>; -+ }; -+ }; -+ -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ rpmsg_audio: rpmsg_audio { -+ compatible = "fsl,imx8mp-rpmsg-audio"; -+ model = "wm8960-audio"; -+ fsl,platform = "rpmsg-audio-channel"; -+ fsl,enable-lpa; -+ fsl,rpmsg-out; -+ fsl,rpmsg-in; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, -+ <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ audio-codec = <&codec>; -+ memory-region = <&audio_reserved>; -+ power-domains = <&audiomix_pd>; -+ audio-routing = -+ "LINPUT1", "MICB", -+ "LINPUT3", "MICB"; -+ status = "okay"; -+ }; -+ -+ rpmsg_micfil: rpmsg_micfil { -+ compatible = "fsl,imx8mp-rpmsg-audio"; -+ model = "micfil-audio"; -+ fsl,platform = "rpmsg-micfil-channel"; -+ fsl,rpmsg-in; -+ assigned-clocks = <&clk IMX8MP_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, -+ <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>; -+ clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; -+ memory-region = <&micfil_reserved>; -+ power-domains = <&audiomix_pd>; -+ status = "okay"; -+ }; -+ -+ imx8mp-cm7 { -+ compatible = "fsl,imx8mn-cm7"; -+ rsc-da = <0x55000000>; -+ clocks = <&clk IMX8MP_CLK_M7_DIV>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; -+ status = "okay"; -+ }; -+}; -+ -+/* -+ * ATTENTION: M7 may use IPs like below -+ * ECSPI0/ECSPI2, FLEXCAN, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, -+ * PWM4, SDMA1/SDMA2 -+ */ -+&ecspi2 { -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+/delete-node/ &i2c3; -+ -+&i2c_rpbus_3 { -+ compatible = "fsl,i2c-rpbus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ ov5640_1: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "xclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "disabled"; -+ -+ port { -+ ov5640_mipi_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2>; -+ clock-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ codec: wm8960@1a { -+ compatible = "wlf,wm8960,lpa"; -+ reg = <0x1a>; -+ wlf,shared-lrclk; -+ SPKVDD1-supply = <®_audio_pwr>; -+ }; -+}; -+ -+&pwm4{ -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&sdma3{ -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts -new file mode 100644 -index 000000000..22347b050 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts -@@ -0,0 +1,108 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2020 -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ reserved-memory { -+ /delete-node/ dsp_reserved; -+ /delete-node/ dsp_reserved_heap; -+ /delete-node/ dsp_vdev0vring0; -+ /delete-node/ dsp_vdev0vring1; -+ /delete-node/ dsp_vdev0buffer; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x2000000>; -+ no-map; -+ }; -+ }; -+ -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+ -+ sound-micfil { -+ status = "disabled"; -+ }; -+ -+ sof-sound-wm8960 { -+ compatible = "simple-audio-card"; -+ label = "wm8960-audio"; -+ simple-audio-card,bitclock-master = <&sndcodec>; -+ simple-audio-card,frame-master = <&sndcodec>; -+ simple-audio-card,hp-det-gpio = <&gpio4 28 0>; -+ simple-audio-card,widgets = -+ "Headphone", "Headphones", -+ "Speaker", "Ext Spk", -+ "Microphone", "Mic Jack"; -+ simple-audio-card,routing = -+ "Headphones", "HP_L", -+ "Headphones", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "Mic Jack", "MICB"; -+ simple-audio-card,dai-link { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&dsp 1>; -+ }; -+ sndcodec: codec { -+ sound-dai = <&codec>; -+ }; -+ }; -+ }; -+}; -+ -+&dsp { -+ #sound-dai-cells = <1>; -+ compatible = "fsl,imx8mp-dsp"; -+ reg = <0x0 0x3B6E8000 0x0 0x88000>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ -+ power-domains = <&audiomix_pd>; -+ audiomix-dsp-regmap = <&audio_blk_ctrl>; -+ -+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>; -+ -+ clock-names = "ipg", "ocram", "core", -+ "sai3_bus", "sai3_mclk0", "sai3_mclk1", "sai3_mclk2", "sai3_mclk3", -+ "sdma3_root"; -+ -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&mu2 2 0>, <&mu2 2 1>, -+ <&mu2 3 0>, <&mu2 3 1>; -+ memory-region = <&dsp_reserved>; -+ /delete-property/ firmware-name; -+ -+ tplg-name = "sof-imx8mp-wm8960.tplg"; -+ machine-drv-name = "asoc-simple-card"; -+ status = "okay"; -+}; -+ -+&codec { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts -new file mode 100644 -index 000000000..367aa99a1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts -@@ -0,0 +1,38 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 NXP -+ * -+ * This DTB showcase SPDIF loop back setup on i.MX8MP EVK. -+ * The signal path used to route SPDIF signal in loopback mode is: -+ * -+ * SPDIF_TX -> I2C5_SCL -> I2C5_SCL_3V3 -> J22 pin 3 -> -+ * J22 pin 5 -> I2C5_SDA_3V3 -> I2C5_SDA -> SPDIF_RX -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ /delete-node/ regulator-can1-stby; -+}; -+ -+/delete-node/ &flexcan1; -+ -+&xcvr { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_xcvr>; -+ pinctrl-assert-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; -+}; -+ -+&iomuxc { -+ -+ /delete-node/ flexcan1grp; -+ /delete-node/ flexcan1reggrp; -+ -+ pinctrl_xcvr: xcvrgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 -+ MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 -+ >; -+ }; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts -new file mode 100644 -index 000000000..58c60269a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts -@@ -0,0 +1,83 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8mp-evk.dts" -+ -+/ { -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x19 -+ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x19 -+ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x19 -+ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4 -+ >; -+ }; -+}; -+ -+&pcie { -+ status = "disabled"; -+ /delete-node/ wifi_wake_host; -+}; -+ -+&pcie_phy { -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ keep-power-in-suspend; -+ non-removable; -+ wakeup-source; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ fsl,sdio-interrupt-enabled; -+ status = "okay"; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpio2>; -+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts -old mode 100644 -new mode 100755 -index ad66f1286..66437b659 ---- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts -@@ -5,6 +5,7 @@ - - /dts-v1/; - -+#include - #include "imx8mp.dtsi" - - / { -@@ -33,6 +34,28 @@ memory@40000000 { - <0x1 0x00000000 0 0xc0000000>; - }; - -+ reg_can1_stby: regulator-can1-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can1-stby"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1_reg>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can2_stby: regulator-can2-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-stby"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2_reg>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; -@@ -43,6 +66,199 @@ reg_usdhc2_vmmc: regulator-usdhc2 { - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -+ -+ reg_audio_pwr: regulator-audio-pwr { -+ compatible = "regulator-fixed"; -+ regulator-name = "audio-pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; -+ }; -+ -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx-audio-cdnhdmi"; -+ model = "audio-hdmi"; -+ audio-cpu = <&aud2htx>; -+ hdmi-out; -+ constraint-rate = <44100>, -+ <88200>, -+ <176400>, -+ <32000>, -+ <48000>, -+ <96000>, -+ <192000>; -+ status = "okay"; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ audio-cpu = <&sai3>; -+ audio-codec = <&codec>; -+ audio-asrc = <&easrc>; -+ hp-det-gpio = <&gpio4 28 0>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "Mic Jack", "MICB"; -+ }; -+ -+ sound-micfil { -+ compatible = "fsl,imx-audio-micfil"; -+ model = "imx-audio-micfil"; -+ cpu-dai = <&micfil>; -+ }; -+ -+ sound-xcvr { -+ compatible = "fsl,imx-audio-xcvr"; -+ model = "imx-audio-xcvr"; -+ cpu-dai = <&xcvr>; -+ }; -+ -+ lvds_backlight: lvds_backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm2 0 100000>; -+ status = "okay"; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ cbtl04gp { -+ compatible = "nxp,cbtl04gp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec_mux>; -+ switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; -+ orientation-switch; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2>; -+}; -+ -+&A53_1 { -+ cpu-supply = <&buck2>; -+}; -+ -+&A53_2 { -+ cpu-supply = <&buck2>; -+}; -+ -+&A53_3 { -+ cpu-supply = <&buck2>; -+}; -+ -+&dsp { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; -+ status = "okay"; -+}; -+ -+&pwm4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm4>; -+ status = "okay"; -+}; -+ -+&aud2htx { -+ status = "okay"; -+}; -+ -+&ecspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev1: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&eqos { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_eqos>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ eee-broken-1000t; -+ rtl821x,aldps-disable; -+ rtl821x,clkout-disable; -+ }; -+ }; - }; - - &fec { -@@ -61,7 +277,240 @@ ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; -- reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; -+ rtl821x,clkout-disable; -+ }; -+ }; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can1_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can2_stby>; -+ pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; -+ status = "disabled";/* can2 pin conflict with pdm: gpio low select pdm, gpio high select can2 */ -+}; -+ -+&i2c1 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic: pca9450@25 { -+ reg = <0x25>; -+ compatible = "nxp,pca9450c"; -+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ -+ pinctrl-0 = <&pinctrl_pmic>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ -+ regulators { -+ buck1: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <3125>; -+ }; -+ -+ buck2: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <3125>; -+ nxp,dvs-run-voltage = <950000>; -+ nxp,dvs-standby-voltage = <850000>; -+ }; -+ -+ buck4: BUCK4{ -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5: BUCK5{ -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6: BUCK6 { -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo5: LDO5 { -+ regulator-name = "LDO5"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ adv_bridge: adv7535@3d { -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ status = "okay"; -+ -+ port { -+ adv7535_from_dsim: endpoint { -+ remote-endpoint = <&dsim_to_adv7535>; -+ }; -+ }; -+ }; -+ -+ lvds_bridge: lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; -+ -+ port { -+ it6263_in: endpoint { -+ remote-endpoint = <&lvds_out>; -+ }; -+ }; -+ }; -+ -+ ov5640_0: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "xclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ -+ port { -+ ov5640_mipi_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2>; -+ clock-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ ptn5110: tcpc@50 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x50>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <19 8>; -+ -+ port { -+ typec_dr_sw: endpoint { -+ remote-endpoint = <&usb3_drd_sw>; -+ }; -+ }; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <15000000>; -+ self-powered; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; - }; - }; - }; -@@ -78,12 +527,223 @@ pca6416: gpio@20 { - gpio-controller; - #gpio-cells = <2>; - }; -+ -+ codec: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <3 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ SPKVDD1-supply = <®_audio_pwr>; -+ }; -+ -+ ov5640_1: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "xclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "disabled"; -+ -+ port { -+ ov5640_mipi_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2>; -+ clock-lanes = <0>; -+ }; -+ }; -+ }; -+}; -+ -+&irqsteer_hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_blk_ctrl { -+ status = "okay"; -+}; -+ -+&hdmi_pavi { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmiphy { -+ status = "okay"; -+}; -+ -+&lcdif1 { -+ status = "okay"; -+}; -+ -+&lcdif2 { -+ status = "okay"; -+}; -+ -+&lcdif3 { -+ status = "okay"; -+ -+ thres-low = <1 2>; /* (FIFO * 1 / 2) */ -+ thres-high = <3 4>; /* (FIFO * 3 / 4) */ -+}; -+ -+&ldb { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds_out: endpoint { -+ remote-endpoint = <&it6263_in>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb_phy { -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ dsim_to_adv7535: endpoint { -+ remote-endpoint = <&adv7535_from_dsim>; -+ attach-bridge; -+ }; -+ }; - }; - - &snvs_pwrkey { - status = "okay"; - }; - -+&easrc { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pdm>; -+ assigned-clocks = <&clk IMX8MP_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "okay"; -+}; -+ -+&pcie{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie>; -+ disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, -+ <&clk IMX8MP_CLK_PCIE_AUX>, -+ <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_ROOT>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-rates = <500000000>, <10000000>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ l1ss-disabled; -+ status = "okay"; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpio5>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&pcie_ep{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie>; -+ ext_osc = <1>; -+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, -+ <&clk IMX8MP_CLK_PCIE_AUX>, -+ <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_ROOT>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-rates = <500000000>, <10000000>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ status = "disabled"; -+}; -+ -+&pcie_phy{ -+ ext_osc = <1>; -+ status = "okay"; -+}; -+ -+&sai2 { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI2>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ fsl,sai-mclk-direction-output; -+ status = "okay"; -+}; -+ -+&xcvr { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&sdma2 { -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ - &uart2 { - /* console */ - pinctrl-names = "default"; -@@ -91,6 +751,63 @@ &uart2 { - status = "okay"; - }; - -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ vbus-power-supply = <&ptn5110>; -+ fsl,phy-tx-vref-tune = <0xe>; -+ fsl,phy-tx-preemp-amp-tune = <3>; -+ fsl,phy-tx-vboost-level = <5>; -+ fsl,phy-comp-dis-tune = <7>; -+ fsl,pcs-tx-deemph-3p5db = <0x21>; -+ fsl,phy-pcs-tx-swing-full = <0x7f>; -+ status = "okay"; -+}; -+ -+&usb3_0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ usb-role-switch; -+ role-switch-default-mode = "none"; -+ status = "okay"; -+ -+ port { -+ usb3_drd_sw: endpoint { -+ remote-endpoint = <&typec_dr_sw>; -+ }; -+ }; -+}; -+ -+&usb3_phy1 { -+ fsl,phy-tx-preemp-amp-tune = <3>; -+ fsl,phy-tx-vref-tune = <0xb>; -+ status = "okay"; -+}; -+ -+&usb3_1 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usb1_vbus>; -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; -@@ -124,6 +841,70 @@ &wdog1 { - }; - - &iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 -+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 -+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 -+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 -+ >; -+ }; -+ -+ pinctrl_pwm1: pwm1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 -+ >; -+ }; -+ -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 -+ >; -+ }; -+ -+ pinctrl_pwm4: pwm4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 -+ >; -+ }; -+ -+ pinctrl_ecspi2: ecspi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 -+ >; -+ }; -+ -+ pinctrl_ecspi2_cs: ecspi2cs { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 -+ >; -+ }; -+ -+ pinctrl_eqos: eqosgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 -+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 -+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 -+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 -+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 -+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 -+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 -+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 -+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f -+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f -+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f -+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f -+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f -+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f -+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 -+ >; -+ }; -+ - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 -@@ -144,16 +925,88 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 - >; - }; - -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 -+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 -+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 -+ >; -+ }; -+ -+ pinctrl_flexcan1_reg: flexcan1reggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ -+ >; -+ }; -+ -+ pinctrl_flexcan2_reg: flexcan2reggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 -+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 -+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 -+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 -+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 -+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 -+ >; -+ }; -+ - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 - >; - }; - -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 -+ >; -+ }; -+ - pinctrl_i2c3: i2c3grp { - fsl,pins = < -- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 -- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 -+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 -+ >; -+ }; -+ -+ pinctrl_pcie: pciegrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ -+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 -+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 -+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - >; - }; - -@@ -163,6 +1016,64 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 - >; - }; - -+ pinctrl_pdm: pdmgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 -+ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai2: sai2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 -+ >; -+ }; -+ -+ pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 -+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 -+ >; -+ }; -+ -+ pinctrl_typec: typec1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 -+ >; -+ }; -+ -+ pinctrl_typec_mux: typec1muxgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 -+ >; -+ }; -+ - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 -@@ -170,6 +1081,21 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 - >; - }; - -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 -+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 -+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 -+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 -+ >; -+ }; -+ -+ pinctrl_usb1_vbus: usb1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x19 -+ >; -+ }; -+ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -@@ -265,4 +1191,112 @@ pinctrl_wdog: wdoggrp { - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; -+ -+ pinctrl_csi0_pwn: csi0_pwn_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 -+ >; -+ }; -+ -+ pinctrl_csi0_rst: csi0_rst_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_mclk: csi_mclk_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x59 -+ >; -+ }; -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_vc8000e { -+ status = "okay"; -+}; -+ -+&vpu_v4l2 { -+ status = "okay"; -+}; -+ -+&gpu_3d { -+ status = "okay"; -+}; -+ -+&gpu_2d { -+ status = "okay"; -+}; -+ -+&ml_vipsi { -+ status = "okay"; -+}; -+ -+&mix_gpu_ml { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_0_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ }; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h -index 0fef06647..6e2ba6c7b 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h -+++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h -@@ -13,10 +13,12 @@ - #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 - #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 - #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 - #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 - #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 - #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 -@@ -58,26 +60,26 @@ - #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 - #define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 --#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO10__USB1_ID 0x03C 0x29C 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 - #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 --#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__USB2_ID 0x040 0x2A0 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 - #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 - #define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 - #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 --#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x044 0x2A4 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 --#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x048 0x2A8 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 --#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x04C 0x2AC 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 - #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 - #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 --#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x050 0x2B0 0x000 0x1 0x0 - #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 - #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 - #define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 -@@ -258,10 +260,8 @@ - #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 - #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 - #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 --#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 - #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 - #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 --#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 - #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 - #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 - #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 -@@ -722,7 +722,7 @@ - #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 - #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 - #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 --#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 -+#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x12 0x0 - #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 - #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 - #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 -diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi -old mode 100644 -new mode 100755 -index 03ef0e5f9..50fa10812 ---- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -18,6 +19,7 @@ / { - - aliases { - ethernet0 = &fec; -+ ethernet1 = &eqos; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; -@@ -36,21 +38,45 @@ aliases { - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; -+ isi0 = &isi_0; -+ isi1 = &isi_1; -+ csi0 = &mipi_csi_0; -+ csi1 = &mipi_csi_1; -+ isp0 = &isp_0; -+ isp1 = &isp_1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - -+ idle-states { -+ entry-method = "psci"; -+ -+ cpu_pd_wait: cpu-pd-wait { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0010033>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ wakeup-latency-us = <1500>; -+ }; -+ }; -+ - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; -+ nvmem-cells = <&cpu_speed_grade>; -+ nvmem-cell-names = "speed_grade"; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_1: cpu@1 { -@@ -59,9 +85,11 @@ A53_1: cpu@1 { - reg = <0x1>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_2: cpu@2 { -@@ -70,9 +98,11 @@ A53_2: cpu@2 { - reg = <0x2>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_3: cpu@3 { -@@ -81,9 +111,11 @@ A53_3: cpu@3 { - reg = <0x3>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_L2: l2-cache0 { -@@ -91,6 +123,103 @@ A53_L2: l2-cache0 { - }; - }; - -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif1_disp>, -+ <&lcdif2_disp>, -+ <&lcdif3_disp>; -+ }; -+ -+ a53_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <850000>; -+ opp-supported-hw = <0x8a0>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <950000>; -+ opp-supported-hw = <0xa0>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1000000>; -+ opp-supported-hw = <0x20>, <0x3>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x0 0x40000000 0 0x80000000>; -+ }; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ ocram: ocram@900000 { -+ no-map; -+ reg = <0 0x900000 0 0x70000>; -+ }; -+ -+/* -+ * Memory reserved for optee usage. Please do not use. -+ * This will be automaticky added to dtb if OP-TEE is installed. -+ * optee@56000000 { -+ * reg = <0 0x56000000 0 0x2000000>; -+ * no-map; -+ * }; -+ */ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0x40000000 0 0xC0000000>; -+ linux,cma-default; -+ }; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ -+ /* used only by tuning tool, can be removed for normal case */ -+ isp0_reserved: isp0@94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x10000000>; -+ }; -+ }; -+ - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -133,6 +262,244 @@ clk_ext4: clock-ext4 { - clock-output-names = "clk_ext4"; - }; - -+ sai1_mclk: sai-mclk1 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <0>; -+ clock-output-names = "sai1_mclk"; -+ }; -+ -+ sai2_mclk: sai-mclk2 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <0>; -+ clock-output-names = "sai2_mclk"; -+ }; -+ -+ sai3_mclk: sai-mclk3 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <0>; -+ clock-output-names = "sai3_mclk"; -+ }; -+ -+ sai5_mclk: sai-mclk5 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <0>; -+ clock-output-names = "sai5_mclk"; -+ }; -+ -+ sai6_mclk: sai-mclk6 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <0>; -+ clock-output-names = "sai6_mclk"; -+ }; -+ -+ sai7_mclk: sai-mclk7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <0>; -+ clock-output-names = "sai7_mclk"; -+ }; -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, -+ <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, -+ <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, -+ <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, -+ <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, -+ <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_DRAM_PLL>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", -+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", -+ "sys_pll1_800m", "dram_pll_div"; -+ }; -+ -+ power-domains { -+ compatible = "simple-bus"; -+ -+ /* HSIO SS */ -+ hsiomix_pd: hsiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ active-wakeup; -+ rpm-always-on; -+ #power-domain-cells = <0>; -+ domain-index = <0>; -+ domain-name = "hsiomix"; -+ }; -+ -+ pcie_pd: pcie-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <1>; -+ domain-name = "pcie"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ usb_otg1_pd: usbotg1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <2>; -+ domain-name = "usb_otg1"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ usb_otg2_pd: usbotg2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <3>; -+ domain-name = "usb_otg2"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ /* MLMIX */ -+ mlmix_pd: mlmix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <4>; -+ domain-name = "mlmix"; -+ clocks = <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>, -+ <&clk IMX8MP_CLK_NPU_ROOT>; -+ }; -+ -+ audiomix_pd: audiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <5>; -+ domain-name = "audiomix"; -+ clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>, -+ <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; -+ }; -+ -+ gpumix_pd: gpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <6>; -+ domain-name = "gpumix"; -+ clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>, -+ <&clk IMX8MP_CLK_GPU_AXI>; -+ }; -+ -+ gpu2d_pd: gpu2d-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <7>; -+ domain-name = "gpu2d"; -+ parent-domains = <&gpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; -+ }; -+ -+ gpu3d_pd: gpu3d-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <8>; -+ domain-name = "gpu3d"; -+ parent-domains = <&gpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; -+ }; -+ -+ vpumix_pd: vpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <9>; -+ domain-name = "vpumix"; -+ clocks =<&clk IMX8MP_CLK_VPU_ROOT>; -+ }; -+ -+ vpu_g1_pd: vpug1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <10>; -+ domain-name = "vpu_g1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; -+ }; -+ -+ vpu_g2_pd: vpug2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <11>; -+ domain-name = "vpu_g2"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; -+ }; -+ -+ vpu_h1_pd: vpuh1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <12>; -+ domain-name = "vpu_h1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; -+ }; -+ -+ mediamix_pd: mediamix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <13>; -+ domain-name = "mediamix"; -+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ }; -+ -+ ispdwp_pd: power-domain@14 { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <14>; -+ domain-name = "ispdwp"; -+ parent-domains = <&mediamix_pd>; -+ }; -+ -+ mipi_phy1_pd: mipiphy1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <15>; -+ domain-name = "mipi_phy1"; -+ parent-domains = <&mediamix_pd>; -+ }; -+ -+ mipi_phy2_pd: mipiphy2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <16>; -+ domain-name = "mipi_phy2"; -+ parent-domains = <&mediamix_pd>; -+ }; -+ -+ hdmimix_pd: hdmimix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <17>; -+ domain-name = "hdmimix"; -+ clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, -+ <&clk IMX8MP_CLK_HDMI_APB>, -+ <&clk IMX8MP_CLK_HDMI_REF_266M>; -+ }; -+ -+ hdmi_phy_pd: hdmiphy-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <18>; -+ domain-name = "hdmi_phy"; -+ parent-domains = <&hdmimix_pd>; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; -+ }; -+ - psci { - compatible = "arm,psci-1.0"; - method = "smc"; -@@ -208,13 +575,21 @@ timer { - ; - clock-frequency = <8000000>; - arm,no-tick-in-suspend; -+ interrupt-parent = <&gic>; - }; - - soc@0 { -- compatible = "simple-bus"; -+ compatible = "fsl,imx8mp-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; -+ nvmem-cells = <&imx8mp_uid>; -+ nvmem-cell-names = "soc_unique_id"; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; -@@ -309,7 +684,8 @@ iomuxc: pinctrl@30330000 { - }; - - gpr: iomuxc-gpr@30340000 { -- compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ compatible = "fsl,imx8mp-iomuxc-gpr", -+ "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - -@@ -321,9 +697,21 @@ ocotp: efuse@30350000 { - #address-cells = <1>; - #size-cells = <1>; - -+ imx8mp_uid: unique-id@420 { -+ reg = <0x8 0x8>; -+ }; -+ - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; -+ -+ eth_mac1: mac-address@640 { -+ reg = <0x90 6>; -+ }; -+ -+ eth_mac2: mac-address@650 { -+ reg = <0x96 6>; -+ }; - }; - - anatop: anatop@30360000 { -@@ -332,6 +720,22 @@ anatop: anatop@30360000 { - reg = <0x30360000 0x10000>; - }; - -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; -+ clock-names = "ipg"; -+ }; -+ - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; -@@ -373,9 +777,9 @@ clk: clock-controller@30380000 { - <&clk IMX8MP_CLK_GIC>, - <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, -- <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MP_AUDIO_PLL1>, -- <&clk IMX8MP_AUDIO_PLL2>; -+ <&clk IMX8MP_AUDIO_PLL2>, -+ <&clk IMX8MP_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_ARM_PLL_OUT>, - <&clk IMX8MP_SYS_PLL2_1000M>, -@@ -389,9 +793,9 @@ clk: clock-controller@30380000 { - <500000000>, - <400000000>, - <800000000>, -- <400000000>, - <393216000>, -- <361267200>; -+ <361267200>, -+ <1039500000>; - }; - - src: reset-controller@30390000 { -@@ -404,7 +808,7 @@ src: reset-controller@30390000 { - - aips2: bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; -- reg = <0x30400000 0x400000>; -+ reg = <0x30400000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -464,7 +868,7 @@ system_counter: timer@306a0000 { - - aips3: bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; -- reg = <0x30800000 0x400000>; -+ reg = <0x30800000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -472,12 +876,15 @@ aips3: bus@30800000 { - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; -- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; -+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, - <&clk IMX8MP_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -486,12 +893,15 @@ ecspi1: spi@30820000 { - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; -- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; -+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, - <&clk IMX8MP_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -500,12 +910,15 @@ ecspi2: spi@30830000 { - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; -- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; -+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, - <&clk IMX8MP_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -545,6 +958,36 @@ uart2: serial@30890000 { - status = "disabled"; - }; - -+ flexcan1: can@308c0000 { -+ compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; -+ reg = <0x308c0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>, -+ <&clk IMX8MP_CLK_CAN1_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_CAN1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; -+ assigned-clock-rates = <40000000>; -+ fsl,clk-source= <0>; -+ fsl,stop-mode = <&gpr 0x10 4 0x10 20>; -+ status = "disabled"; -+ }; -+ -+ flexcan2: can@308d0000 { -+ compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; -+ reg = <0x308d0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>, -+ <&clk IMX8MP_CLK_CAN2_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_CAN2>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; -+ assigned-clock-rates = <40000000>; -+ fsl,clk-source= <0>; -+ fsl,stop-mode = <&gpr 0x10 5 0x10 21>; -+ status = "disabled"; -+ }; -+ - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; -@@ -656,7 +1099,7 @@ i2c6: i2c@30ae0000 { - }; - - usdhc1: mmc@30b40000 { -- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; -+ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_DUMMY>, -@@ -670,7 +1113,7 @@ usdhc1: mmc@30b40000 { - }; - - usdhc2: mmc@30b50000 { -- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; -+ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_DUMMY>, -@@ -684,7 +1127,7 @@ usdhc2: mmc@30b50000 { - }; - - usdhc3: mmc@30b60000 { -- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; -+ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_DUMMY>, -@@ -697,8 +1140,24 @@ usdhc3: mmc@30b60000 { - status = "disabled"; - }; - -+ -+ flexspi: spi@30bb0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mm-fspi"; -+ reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, -+ <&clk IMX8MP_CLK_QSPI_ROOT>; -+ clock-names = "fspi", "fspi_en"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>; -+ status = "disabled"; -+ }; -+ - sdma1: dma-controller@30bd0000 { -- compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; -+ compatible = "fsl,imx8mq-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, -@@ -725,13 +1184,821 @@ fec: ethernet@30be0000 { - assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, - <&clk IMX8MP_CLK_ENET_TIMER>, - <&clk IMX8MP_CLK_ENET_REF>, -- <&clk IMX8MP_CLK_ENET_TIMER>; -+ <&clk IMX8MP_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, - <&clk IMX8MP_SYS_PLL2_100M>, -- <&clk IMX8MP_SYS_PLL2_125M>; -- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; -+ <&clk IMX8MP_SYS_PLL2_125M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; -+ nvmem-cells = <ð_mac1>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ fsl,stop-mode = <&gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; -+ status = "disabled"; -+ }; -+ -+ eqos: ethernet@30bf0000 { -+ compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; -+ reg = <0x30bf0000 0x10000>; -+ interrupts = , -+ ; -+ interrupt-names = "eth_wake_irq", "macirq"; -+ clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, -+ <&clk IMX8MP_CLK_QOS_ENET_ROOT>, -+ <&clk IMX8MP_CLK_ENET_QOS_TIMER>, -+ <&clk IMX8MP_CLK_ENET_QOS>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; -+ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, -+ <&clk IMX8MP_CLK_ENET_QOS_TIMER>, -+ <&clk IMX8MP_CLK_ENET_QOS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, -+ <&clk IMX8MP_SYS_PLL2_100M>, -+ <&clk IMX8MP_SYS_PLL2_125M>; -+ assigned-clock-rates = <0>, <100000000>, <125000000>; -+ nvmem-cells = <ð_mac2>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ intf_mode = <&gpr 0x4>; -+ status = "disabled"; -+ }; -+ }; -+ -+ aips4: bus@32c00000 { -+ compatible = "simple-bus"; -+ reg = <0x32c00000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ mipi_dsi: mipi_dsi@32e60000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-mipi-dsim"; -+ reg = <0x32e60000 0x10000>; -+ clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF>; -+ clock-names = "cfg", "pll-ref"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <12000000>; -+ interrupts = ; -+ power-domains = <&mipi_phy1_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ dsim_from_lcdif: endpoint { -+ remote-endpoint = <&lcdif_to_dsim>; -+ }; -+ }; -+ }; -+ -+ lcdif1: lcd-controller@32e80000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-lcdif1"; -+ reg = <0x32e80000 0x10000>; -+ clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <500000000>, <200000000>; -+ interrupts = ; -+ blk-ctl = <&media_blk_ctrl>; -+ resets = <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB>; -+ power-domains = <&mediamix_pd>; -+ status = "disabled"; -+ -+ lcdif1_disp: port@0 { -+ reg = <0>; -+ -+ lcdif_to_dsim: endpoint { -+ remote-endpoint = <&dsim_from_lcdif>; -+ }; -+ }; -+ }; -+ -+ lcdif2: lcd-controller@32e90000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-lcdif2"; -+ reg = <0x32e90000 0x10000>; -+ clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <500000000>, <200000000>; -+ interrupts = ; -+ power-domains = <&mediamix_pd>; -+ status = "disabled"; -+ -+ lcdif2_disp: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ lcdif2_disp_ldb_ch0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&ldb_ch0>; -+ }; -+ -+ lcdif2_disp_ldb_ch1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&ldb_ch1>; -+ }; -+ }; -+ }; -+ -+ media_blk_ctrl: media-blk-ctrl@32ec0000 { -+ compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; -+ reg = <0x32ec0000 0x10000>; -+ power-domains = <&mediamix_pd>; -+ -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ ldb: ldb@32ec005c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-ldb"; -+ clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; -+ clock-names = "ldb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; -+ gpr = <&media_blk_ctrl>; -+ power-domains = <&mediamix_pd>; -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ phys = <&ldb_phy1>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb_ch0: endpoint { -+ remote-endpoint = <&lcdif2_disp_ldb_ch0>; -+ }; -+ }; -+ }; -+ -+ lvds-channel@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ phys = <&ldb_phy2>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb_ch1: endpoint { -+ remote-endpoint = <&lcdif2_disp_ldb_ch1>; -+ }; -+ }; -+ }; -+ }; -+ -+ ldb_phy: phy@32ec0128 { -+ compatible = "fsl,imx8mp-lvds-phy"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ gpr = <&media_blk_ctrl>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ clock-names = "apb"; -+ power-domains = <&mediamix_pd>; -+ status = "disabled"; -+ -+ ldb_phy1: port@0 { -+ reg = <0>; -+ #phy-cells = <0>; -+ }; -+ -+ ldb_phy2: port@1 { -+ reg = <1>; -+ #phy-cells = <0>; -+ }; -+ }; -+ -+ mediamix_gpr: media_gpr@32ec0008 { -+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ reg = <0x32ec0008 0x4>; -+ }; -+ -+ mediamix_gasket0: gasket@32ec0060 { -+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ reg = <0x32ec0060 0x28>; -+ }; -+ -+ mediamix_gasket1: gasket@32ec0090 { -+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ reg = <0x32ec0090 0x28>; -+ }; -+ -+ isi_chain_buf: isi_chain@32e02000{ -+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ reg = <0x32e02000 0x4>; -+ }; -+ -+ cameradev: camera { -+ compatible = "fsl,mxc-md", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ isi_0: isi@32e00000 { -+ compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; -+ reg = <0x32e00000 0x2000>; -+ interrupts = ; -+ interface = <2 0 2>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>, -+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB>; -+ clock-names = "disp_axi", -+ "disp_apb", -+ "disp_axi_root", -+ "disp_apb_root", -+ "media_blk_bus", -+ "media_blk_isi_proc", -+ "media_blk_isi_apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <500000000>, <200000000>; -+ resets = <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC>, -+ <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB>, -+ <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK>; -+ reset-names = "isi_rst_proc", "isi_rst_apb", "isi_rst_bus"; -+ power-domains = <&mediamix_pd>; -+ isi_chain = <&isi_chain_buf>; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ -+ m2m_device{ -+ compatible = "imx-isi-m2m"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_1: isi@32e02000 { -+ compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; -+ reg = <0x32e02000 0x2000>; -+ interrupts = ; -+ interface = <3 0 2>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>, -+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB>; -+ clock-names = "disp_axi", -+ "disp_apb", -+ "disp_axi_root", -+ "disp_apb_root", -+ "media_blk_bus", -+ "media_blk_isi_proc", -+ "media_blk_isi_apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <500000000>, <200000000>; -+ resets = <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC>, -+ <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB>, -+ <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK>; -+ reset-names = "isi_rst_proc", "isi_rst_apb", "isi_rst_bus"; -+ power-domains = <&mediamix_pd>; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ dewarp: dwe@32e30000 { -+ compatible = "fsl,imx8mp-dwe"; -+ clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB>; -+ clock-names = "core", "axi", "ahb"; -+ reg = <0x32e30000 0x10000>; -+ interrupts = ; -+ power-domains = <&ispdwp_pd>; -+ status = "disabled"; -+ }; -+ -+ isp_0: isp@32e10000 { -+ compatible = "fsl,imx8mp-isp"; -+ reg = <0x32e10000 0x10000>; -+ interrupts = ; -+ clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK>; -+ clock-names = "core", "axi", "ahb", "sensor"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; -+ assigned-clock-rates = <500000000>; -+ power-domains = <&ispdwp_pd>; -+ id = <0>; -+ gpr = <&media_blk_ctrl>; -+ memory-region = <&isp0_reserved>; -+ status = "disabled"; -+ }; -+ -+ isp_1: isp@32e20000 { -+ compatible = "fsl,imx8mp-isp"; -+ reg = <0x32e20000 0x10000>; -+ interrupts = ; -+ clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK>; -+ clock-names = "core", "axi", "ahb", "sensor"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; -+ assigned-clock-rates = <500000000>; -+ power-domains = <&ispdwp_pd>; -+ id = <1>; -+ gpr = <&media_blk_ctrl>; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_0: csi@32e40000 { -+ compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; -+ reg = <0x32e40000 0x10000>; -+ interrupts = ; -+ clock-frequency = <500000000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK>; -+ clock-names = "mipi_clk", -+ "disp_axi", -+ "disp_apb", -+ "media_blk_csi_pclk", -+ "media_blk_csi_aclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; -+ assigned-clock-rates = <500000000>; -+ bus-width = <4>; -+ csi-gpr = <&mediamix_gasket0>; -+ gpr = <&media_blk_ctrl>; -+ resets = <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK>, -+ <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK>; -+ reset-names = "csi_rst_pclk", "csi_rst_aclk"; -+ power-domains = <&mipi_phy1_pd>; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: csi@32e50000 { -+ compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; -+ reg = <0x32e50000 0x10000>; -+ interrupts = ; -+ clock-frequency = <266000000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK>, -+ <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK>; -+ clock-names = "mipi_clk", -+ "disp_axi", -+ "disp_apb", -+ "media_blk_csi_pclk", -+ "media_blk_csi_aclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; -+ assigned-clock-rates = <266000000>; -+ bus-width = <4>; -+ csi-gpr = <&mediamix_gasket1>; -+ gpr = <&media_blk_ctrl>; -+ resets = <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK>, -+ <&media_blk_ctrl IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK>; -+ reset-names = "csi_rst_pclk", "csi_rst_aclk"; -+ power-domains = <&mipi_phy2_pd>; -+ status = "disabled"; -+ }; -+ }; -+ -+ pcie_phy: pcie-phy@32f00000 { -+ compatible = "fsl,imx8mp-pcie-phy"; -+ reg = <0x32f00000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ hsio_mix: hsio-mix@32f10000 { -+ compatible = "fsl,imx8mp-hsio-mix"; -+ reg = <0x32f10000 0x8>; -+ }; -+ }; -+ -+ aips5: bus@30c00000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ reg = <0x30c00000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ spba-bus@30c00000 { -+ compatible = "fsl,spba-bus", "simple-bus"; -+ reg = <0x30c00000 0x100000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ sai1: sai@30c10000 { -+ compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; -+ reg = <0x30c10000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xff 0xff>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@30c20000 { -+ compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; -+ reg = <0x30c20000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@30c30000 { -+ compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; -+ reg = <0x30c30000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0x3 0x3>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@30c50000 { -+ compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; -+ reg = <0x30c50000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@30c60000 { -+ compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; -+ reg = <0x30c60000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG>, -+ <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1>, -+ <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai7: sai@30c80000 { -+ compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; -+ reg = <0x30c80000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ easrc: easrc@30c90000 { -+ compatible = "fsl,imx8mn-easrc"; -+ reg = <0x30c90000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG>; -+ clock-names = "mem"; -+ dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, -+ <&sdma2 18 23 0> , <&sdma2 19 23 0>, -+ <&sdma2 20 23 0> , <&sdma2 21 23 0>, -+ <&sdma2 22 23 0> , <&sdma2 23 23 0>; -+ dma-names = "ctx0_rx", "ctx0_tx", -+ "ctx1_rx", "ctx1_tx", -+ "ctx2_rx", "ctx2_tx", -+ "ctx3_rx", "ctx3_tx"; -+ fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; -+ fsl,asrc-rate = <8000>; -+ fsl,asrc-width = <16>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ micfil: micfil@30ca0000 { -+ compatible = "fsl,imx8mp-micfil"; -+ reg = <0x30ca0000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>, -+ <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>, -+ <&clk IMX8MP_CLK_EXT3>; -+ clock-names = "ipg_clk", "ipg_clk_app", -+ "pll8k", "pll11k", "clkext3"; -+ dmas = <&sdma2 24 25 0x80000000>; -+ dma-names = "rx"; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ aud2htx: aud2htx@30cb0000 { -+ compatible = "fsl,imx8mp-aud2htx"; -+ reg = <0x30cb0000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG>; -+ clock-names = "bus"; -+ dmas = <&sdma2 26 2 0>; -+ dma-names = "tx"; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ xcvr: xcvr@30cc0000 { -+ compatible = "fsl,imx8mp-xcvr"; -+ reg = <0x30cc0000 0x800>, -+ <0x30cc0800 0x400>, -+ <0x30cc0c00 0x080>, -+ <0x30cc0e00 0x080>; -+ reg-names = "ram", "regs", "rxfifo", -+ "txfifo"; -+ interrupts = /* XCVR IRQ 0 */ -+ , -+ /* XCVR IRQ 1 */ -+ , -+ /* XCVR PHY - SPDIF wakeup IRQ */ -+ ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT>; -+ clock-names = "ipg", "phy", "spba", "pll_ipg"; -+ dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; -+ dma-names = "rx", "tx"; -+ resets = <&audio_blk_ctrl 0>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ }; -+ -+ sdma3: dma-controller@30e00000 { -+ compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; -+ reg = <0x30e00000 0x10000>; -+ interrupts = ; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ fsl,ratio-1-1; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sdma2: dma-controller@30e10000 { -+ compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; -+ reg = <0x30e10000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>, -+ <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ fsl,ratio-1-1; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ audio_blk_ctrl: audio-blk-ctrl@30e20000 { -+ compatible = "fsl,imx8mp-audio-blk-ctrl", "syscon"; -+ reg = <0x30e20000 0x50C>; -+ power-domains = <&audiomix_pd>; -+ -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ -+ assigned-clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS>; -+ assigned-clock-parents = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL>; -+ }; -+ -+ audiomix_dsp: audiomix_dsp { -+ compatible = "fsl,audiomix-dsp"; -+ power-domains = <&audiomix_pd>; -+ }; -+ -+ mu2: mu2@30e60000 { -+ compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; -+ reg = <0x30E60000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT>; -+ status = "okay"; -+ }; -+ -+ hdmi_blk_ctrl: hdmi-blk-ctrl@32fc0000 { -+ compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; -+ reg = <0x32fc0000 0x1000>; -+ power-domains = <&hdmimix_pd>; -+ -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ irqsteer_hdmi: irqsteer@32fc2000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x32fc2000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ fsl,channel = <1>; -+ fsl,num-irqs = <64>; -+ clocks = <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK>; -+ clock-names = "ipg"; -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_133M>; -+ assigned-clock-rates = <133000000>; -+ resets = <&hdmi_blk_ctrl IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET>; -+ status = "disabled"; -+ }; -+ -+ hdmi_pavi: hdmi-pai-pvi@32fc4000 { -+ compatible = "fsl,imx8mp-hdmi-pavi"; -+ reg = <0x32fc4000 0x1000>; -+ clocks = <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK>; -+ clock-names = "pvi_clk", "pai_clk"; -+ resets = <&hdmi_blk_ctrl IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET>, -+ <&hdmi_blk_ctrl IMX8MP_HDMI_BLK_CTRL_HDMI_PVI_RESET>; -+ reset-names = "pai_rst", "pvi_rst"; -+ status = "disabled"; -+ }; -+ -+ lcdif3: lcd-controller@32fc6000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-lcdif3"; -+ reg = <0x32fc6000 0x10000>; -+ clocks = <&hdmiphy 0>, -+ <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_APB>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK>; -+ clock-names = "pix", "disp-axi", "disp-apb", -+ "mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb", -+ "lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu", -+ "noc_hdmi"; -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_APB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_SYS_PLL1_133M>; -+ assigned-clock-rates = <500000000>, <133000000>; -+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_hdmi>; -+ resets = <&hdmi_blk_ctrl IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET>; -+ power-domains = <&hdmimix_pd>; -+ status = "disabled"; -+ -+ lcdif3_disp: port@0 { -+ reg = <0>; -+ -+ lcdif3_to_hdmi: endpoint { -+ remote-endpoint = <&hdmi_from_lcdif3>; -+ }; -+ }; -+ }; -+ -+ hdmi: hdmi@32fd8000 { -+ compatible = "fsl,imx8mp-hdmi"; -+ reg = <0x32fd8000 0x7eff>; -+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_hdmi>; -+ clocks = <&clk IMX8MP_CLK_HDMI_APB>, -+ <&clk IMX8MP_CLK_HDMI_24M>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL>; -+ clock-names = "iahb", "isfr", -+ "phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk", -+ "cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk"; -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>, -+ <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_24M>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_133M>, -+ <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <133000000>, <500000000>, <24000000>; -+ phys = <&hdmiphy>; -+ phy-names = "hdmi"; -+ resets = <&hdmi_blk_ctrl IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET>; -+ gpr = <&hdmi_blk_ctrl>; -+ power-domains = <&hdmi_phy_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ hdmi_from_lcdif3: endpoint { -+ remote-endpoint = <&lcdif3_to_hdmi>; -+ }; -+ }; -+ }; -+ -+ hdmiphy: hdmiphy@32fdff00 { -+ compatible = "fsl,samsung-hdmi-phy"; -+ reg = <0x32fdff00 0x100>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK>, -+ <&hdmi_blk_ctrl IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK>; -+ clock-names = "apb", "ref"; -+ clock-output-names = "hdmi_phy"; -+ #phy-cells = <0>; -+ resets = <&hdmi_blk_ctrl IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET>; - status = "disabled"; - }; - }; -@@ -746,10 +2013,540 @@ gic: interrupt-controller@38800000 { - interrupt-parent = <&gic>; - }; - -+ usb3_phy0: usb-phy@381f0040 { -+ compatible = "fsl,imx8mp-usb-phy"; -+ reg = <0x381f0040 0x40>; -+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usb3_0: usb@32f10100 { -+ compatible = "fsl,imx8mp-dwc3"; -+ reg = <0x32f10100 0x8>; -+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, -+ <&clk IMX8MP_CLK_USB_ROOT>; -+ clock-names = "hsio", "suspend"; -+ interrupts = ; -+ power-domains = <&hsiomix_pd>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ usb_dwc3_0: dwc3@38100000 { -+ compatible = "snps,dwc3"; -+ reg = <0x38100000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_USB_CORE_REF>, -+ <&clk IMX8MP_CLK_USB_ROOT>; -+ clock-names = "bus_early", "ref", "suspend"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; -+ assigned-clock-rates = <500000000>; -+ interrupts = ; -+ phys = <&usb3_phy0>, <&usb3_phy0>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,usb2-lpm-disable; -+ status = "disabled"; -+ }; -+ -+ }; -+ -+ usb3_phy1: usb-phy@382f0040 { -+ compatible = "fsl,imx8mp-usb-phy"; -+ reg = <0x382f0040 0x40>; -+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usb3_1: usb@32f10108 { -+ compatible = "fsl,imx8mp-dwc3"; -+ reg = <0x32f10108 0x8>; -+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, -+ <&clk IMX8MP_CLK_USB_ROOT>; -+ clock-names = "hsio", "suspend"; -+ interrupts = ; -+ power-domains = <&hsiomix_pd>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ usb_dwc3_1: dwc3@38200000 { -+ compatible = "snps,dwc3"; -+ reg = <0x38200000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>, -+ <&clk IMX8MP_CLK_USB_CORE_REF>, -+ <&clk IMX8MP_CLK_USB_ROOT>; -+ clock-names = "bus_early", "ref", "suspend"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; -+ assigned-clock-rates = <500000000>; -+ interrupts = ; -+ phys = <&usb3_phy1>, <&usb3_phy1>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,usb2-lpm-disable; -+ status = "disabled"; -+ }; -+ }; -+ -+ dma_apbh: dma-apbh@33000000 { -+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; -+ reg = <0x33000000 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ }; -+ -+ gpmi: gpmi-nand@33002000{ -+ compatible = "fsl,imx7d-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&clk IMX8MP_CLK_NAND_ROOT>, -+ <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ clock-names = "gpmi_io", "gpmi_bch_apb"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ status = "disabled"; -+ }; -+ -+ pcie: pcie@33800000 { -+ compatible = "fsl,imx8mp-pcie", "snps,dw-pcie"; -+ reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,max-link-speed = <3>; -+ linux,pci-domain = <0>; -+ power-domains = <&pcie_pd>; -+ resets = <&src IMX8MP_RESET_PCIEPHY>, -+ <&src IMX8MP_RESET_PCIEPHY_PERST>, -+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ fsl,imx8mp-hsio-mix = <&hsio_mix>; -+ status = "disabled"; -+ }; -+ -+ pcie_ep: pcie_ep@33800000 { -+ compatible = "fsl,imx8mp-pcie-ep"; -+ reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; -+ reg-names = "regs", "addr_space"; -+ num-lanes = <1>; -+ interrupts = ; /* eDMA */ -+ interrupt-names = "dma"; -+ fsl,max-link-speed = <3>; -+ power-domains = <&pcie_pd>; -+ resets = <&src IMX8MP_RESET_PCIEPHY>, -+ <&src IMX8MP_RESET_PCIEPHY_PERST>, -+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ fsl,imx8mp-hsio-mix = <&hsio_mix>; -+ num-ib-windows = <4>; -+ num-ob-windows = <4>; -+ status = "disabled"; -+ }; -+ - ddr-pmu@3d800000 { - compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupts = ; - }; -+ -+ edacmc: memory-controller@3d400000 { -+ compatible = "fsl,imx8mp-ddrc"; -+ reg = <0x3d400000 0x400000>; -+ interrupts = ; -+ }; -+ }; -+ -+ vpu_g1: vpu_g1@38300000 { -+ compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; -+ reg = <0x0 0x38300000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <800000000>, <800000000>; -+ power-domains = <&vpu_g1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g2: vpu_g2@38310000 { -+ compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; -+ reg = <0x0 0x38310000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; -+ assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <700000000>, <800000000>, <700000000>; -+ power-domains = <&vpu_g2_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_vc8000e: vpu_vc8000e@38320000 { -+ compatible = "nxp,imx8mp-hantro-vc8000e"; -+ reg = <0x0 0x38320000 0x0 0x10000>; -+ reg-names = "regs_hantro_vc8000e"; -+ interrupts = ; -+ interrupt-names = "irq_hantro_vc8000e"; -+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; -+ clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <500000000>, <800000000>; -+ power-domains = <&vpu_h1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_v4l2: vpu_v4l2 { -+ compatible = "nxp,imx8m-vsiv4l2"; -+ status = "disabled"; -+ }; -+ -+ gpu_3d: gpu3d@38000000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x0 0x38000000 0x0 0x8000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ clock-names = "core", "shader", "axi", "ahb"; -+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, <1000000000>, -+ <800000000>, <400000000>; -+ power-domains = <&gpu3d_pd>; -+ status = "disabled"; -+ }; -+ -+ gpu_2d: gpu2d@38008000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x0 0x38008000 0x0 0x8000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ clock-names = "core", "axi", "ahb"; -+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, <800000000>, <400000000>; -+ power-domains = <&gpu2d_pd>; -+ status = "disabled"; -+ }; -+ -+ ml_vipsi: vipsi@38500000 { -+ compatible = "fsl,imx8-gpu", "fsl,imx8-vipsi"; -+ reg = <0x0 0x38500000 0x0 0x20000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_NPU_ROOT>, -+ <&clk IMX8MP_CLK_NPU_ROOT>, -+ <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>; -+ clock-names = "core", "shader", "axi", "ahb"; -+ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, -+ <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, <800000000>, <400000000>; -+ power-domains = <&mlmix_pd>; -+ status = "disabled"; -+ }; -+ -+ mix_gpu_ml: mix_gpu_ml { -+ compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; -+ cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; -+ reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+ status = "disabled"; -+ }; -+ -+ dsp: dsp@3b6e8000 { -+ compatible = "fsl,imx8mp-hifi4"; -+ reg = <0x0 0x3B6E8000 0x0 0x88000>; -+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, -+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&audiomix_pd>; -+ mbox-names = "tx0", "rx0", "rxdb0"; -+ mboxes = <&mu2 0 0>, -+ <&mu2 1 0>, -+ <&mu2 3 0>; -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ syscon = <&audio_blk_ctrl>; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_3: i2c-rpbus-3 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ etm0: etm@28440000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28440000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_0>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm0_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port0>; -+ }; -+ }; -+ }; -+ }; -+ -+ etm1: etm@28540000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28540000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_1>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm1_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port1>; -+ }; -+ }; -+ }; -+ }; -+ -+ etm2: etm@28640000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28640000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_2>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm2_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port2>; -+ }; -+ }; -+ }; -+ }; -+ -+ etm3: etm@28740000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28740000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_3>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm3_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port3>; -+ }; -+ }; -+ }; -+ }; -+ -+ funnel0: funnel { -+ /* -+ * non-configurable funnel don't show up on the AMBA -+ * bus. As such no need to add "arm,primecell". -+ */ -+ compatible = "arm,coresight-static-funnel"; -+ status = "disabled"; -+ -+ in-ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ ca_funnel_in_port0: endpoint { -+ remote-endpoint = <&etm0_out_port>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ ca_funnel_in_port1: endpoint { -+ remote-endpoint = <&etm1_out_port>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ ca_funnel_in_port2: endpoint { -+ remote-endpoint = <&etm2_out_port>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ ca_funnel_in_port3: endpoint { -+ remote-endpoint = <&etm3_out_port>; -+ }; -+ }; -+ }; -+ -+ out-ports { -+ port { -+ ca_funnel_out_port0: endpoint { -+ remote-endpoint = <&hugo_funnel_in_port0>; -+ }; -+ }; -+ }; -+ -+ }; -+ -+ funnel1: funnel@28c03000 { -+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; -+ reg = <0x0 0x28c03000 0x0 0x1000>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ in-ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ hugo_funnel_in_port0: endpoint { -+ remote-endpoint = <&ca_funnel_out_port0>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ hugo_funnel_in_port1: endpoint { -+ /* M7 input */ -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ hugo_funnel_in_port2: endpoint { -+ /* DSP input */ -+ }; -+ }; -+ /* the other input ports are not connect to anything */ -+ }; -+ -+ out-ports { -+ port { -+ hugo_funnel_out_port0: endpoint { -+ remote-endpoint = <&etf_in_port>; -+ }; -+ }; -+ }; -+ }; -+ -+ etf@28c04000 { -+ compatible = "arm,coresight-tmc", "arm,primecell"; -+ reg = <0x0 0x28c04000 0x0 0x1000>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ in-ports { -+ port { -+ etf_in_port: endpoint { -+ remote-endpoint = <&hugo_funnel_out_port0>; -+ }; -+ }; -+ }; -+ -+ out-ports { -+ port { -+ etf_out_port: endpoint { -+ remote-endpoint = <&etr_in_port>; -+ }; -+ }; -+ }; -+ }; -+ -+ etr@28c06000 { -+ compatible = "arm,coresight-tmc", "arm,primecell"; -+ reg = <0x0 0x28c06000 0x0 0x1000>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ in-ports { -+ port { -+ etr_in_port: endpoint { -+ remote-endpoint = <&etf_out_port>; -+ }; -+ }; -+ }; - }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts -new file mode 100644 -index 000000000..d2845266b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts -@@ -0,0 +1,345 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2017-2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mq.dtsi" -+ -+/ { -+ model = "NXP i.MX8MQ DDR3L ARM2"; -+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; -+ -+ chosen { -+ stdout-path = &uart1; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-vsd-3v3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2>; -+ compatible = "regulator-fixed"; -+ regulator-name = "VSD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ busfreq { -+ status = "disabled"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 -+ MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f -+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 -+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 -+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 -+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 -+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 -+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 -+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f -+ >; -+ }; -+ -+ -+ pinctrl_qspi: qspigrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 -+ MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 -+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 -+ MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 -+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 -+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 -+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 -+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 -+ MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 -+ MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 -+ MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 -+ MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 -+ -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 -+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2: regusdhc2grpgpio { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rmii"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, -+ <&clk IMX8MQ_SYS2_PLL_100M>, -+ <&clk IMX8MQ_SYS2_PLL_50M>; -+ assigned-clock-rates = <0>, <0>, <50000000>, <100000000>; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic@8 { -+ compatible = "fsl,pfuze100"; -+ reg = <0x08>; -+ -+ regulators { -+ sw1a_reg: sw1ab { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-always-on; -+ }; -+ -+ sw1c_reg: sw1c { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-always-on; -+ }; -+ -+ sw2_reg: sw2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sw3a_reg: sw3ab { -+ regulator-min-microvolt = <400000>; -+ regulator-max-microvolt = <1975000>; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: sw4 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ swbst_reg: swbst { -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5150000>; -+ }; -+ -+ snvs_reg: vsnvs { -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ }; -+ -+ vref_reg: vrefddr { -+ regulator-always-on; -+ }; -+ -+ vgen1_reg: vgen1 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ }; -+ -+ vgen2_reg: vgen2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ regulator-always-on; -+ }; -+ -+ vgen3_reg: vgen3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen4_reg: vgen4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen5_reg: vgen5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen6_reg: vgen6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+}; -+ -+&uart1 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts -new file mode 100644 -index 000000000..826ba6eb6 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts -@@ -0,0 +1,36 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2017-2019 NXP -+ */ -+ -+#include "imx8mq-ddr4-val.dts" -+ -+&iomuxc { -+ -+ pinctrl_gpmi_nand_1: gpmi-nand-1 { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 -+ MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 -+ MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 -+ MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 -+ MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 -+ MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 -+ MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 -+ MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 -+ >; -+ }; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand_1>; -+ status = "okay"; -+ nand-on-flash-bbt; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts -new file mode 100644 -index 000000000..7d23d1079 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts -@@ -0,0 +1,351 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2017-2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mq.dtsi" -+ -+/ { -+ model = "NXP i.MX8MQ DDR4 ARM2"; -+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; -+ -+ chosen { -+ stdout-path = &uart1; -+ }; -+ -+ -+ -+ reg_usdhc2_vmmc: regulator-vsd-3v3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2>; -+ compatible = "regulator-fixed"; -+ regulator-name = "VSD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ busfreq { -+ status = "disabled"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 -+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 -+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2: regusdhc2grpgpio { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic@8 { -+ compatible = "fsl,pfuze100"; -+ reg = <0x08>; -+ -+ regulators { -+ sw1a_reg: sw1ab { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-always-on; -+ }; -+ -+ sw1c_reg: sw1c { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-always-on; -+ }; -+ -+ sw2_reg: sw2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sw3a_reg: sw3ab { -+ regulator-min-microvolt = <400000>; -+ regulator-max-microvolt = <1975000>; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: sw4 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ swbst_reg: swbst { -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5150000>; -+ }; -+ -+ snvs_reg: vsnvs { -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ }; -+ -+ vref_reg: vrefddr { -+ regulator-always-on; -+ }; -+ -+ vgen1_reg: vgen1 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ }; -+ -+ vgen2_reg: vgen2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ regulator-always-on; -+ }; -+ -+ vgen3_reg: vgen3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen4_reg: vgen4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen5_reg: vgen5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen6_reg: vgen6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+}; -+ -+&uart1 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ status = "okay"; -+ dr_mode = "otg"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts -new file mode 100644 -index 000000000..61b4bb0b8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts -@@ -0,0 +1,93 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ sound-ak4458 { -+ status = "disabled"; -+ }; -+ -+ sound-ak4497 { -+ status = "okay"; -+ }; -+}; -+ -+&iomuxc { -+ -+ pinctrl_sai1_pcm: sai1grp_pcm { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd512: sai1grp_dsd512 { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd", "dsd512"; -+ pinctrl-0 = <&pinctrl_sai1_pcm>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ pinctrl-2 = <&pinctrl_sai1_dsd512>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ assigned-clock-rates = <45158400>; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0x11>; -+ dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts -new file mode 100644 -index 000000000..3eba0b6bb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts -@@ -0,0 +1,25 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ sound-ak4458 { -+ fsl,tdm; -+ }; -+ -+ sound-ak5558 { -+ fsl,tdm; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts -new file mode 100644 -index 000000000..e992301cd ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts -@@ -0,0 +1,101 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2019 NXP. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ sound-hdmi { -+ status = "disabled"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+/delete-node/ &hdmi; -+ -+&lcdif { -+ status = "disabled"; -+}; -+ -+&dcss { -+ status = "okay"; -+ -+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, -+ <&clk IMX8MQ_CLK_DC_PIXEL>, -+ <&clk IMX8MQ_CLK_DISP_DTRC>; -+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_CLK_DISP_AXI>, -+ <&clk IMX8MQ_CLK_DISP_RTRM>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>; -+ assigned-clock-rates = <600000000>, <0>, <0>, -+ <800000000>, -+ <400000000>; -+ -+ port@0 { -+ dcss_out: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+&adv_bridge { -+ status = "okay"; -+ -+ port@0 { -+ adv7535_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ /delete-node/ panel@0; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ mipi_dsi_in: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&dcss_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&adv7535_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts -new file mode 100644 -index 000000000..a49332ce4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts -@@ -0,0 +1,111 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2019 NXP. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/delete-node/&hdmi; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&lcdif { -+ status = "disabled"; -+}; -+ -+&dcss { -+ status = "okay"; -+ -+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, -+ <&clk IMX8MQ_CLK_DC_PIXEL>, -+ <&clk IMX8MQ_CLK_DISP_DTRC>; -+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_CLK_DISP_AXI>, -+ <&clk IMX8MQ_CLK_DISP_APB>, -+ <&clk IMX8MQ_CLK_DISP_RTRM>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>; -+ assigned-clock-rates = <600000000>, <0>, <0>, -+ <800000000>, -+ <25000000>, -+ <400000000>; -+ -+ port@0 { -+ dcss_out: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ pinctrl-names = "default"; -+ reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ mipi_dsi_in: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&dcss_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 -+ >; -+ }; -+}; -+ -+&synaptics_dsx_ts { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts -new file mode 100644 -index 000000000..d6afe07af ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mq-evk-dcss-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c3 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts -new file mode 100644 -index 000000000..b3eda6661 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts -@@ -0,0 +1,34 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2019 NXP. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+ disp-dev = "hdmi_disp"; -+ -+ port@0 { -+ dcss_out: endpoint { -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+}; -+ -+&hdmi { -+ compatible = "cdn,imx8mq-dp"; -+ lane-mapping = <0xc6>; -+ hdcp-config = <0x2>; -+ status = "okay"; -+ -+ port@1 { -+ hdmi_in: endpoint { -+ remote-endpoint = <&dcss_out>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts -new file mode 100644 -index 000000000..49aadba32 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mq-evk-lcdif-adv7535.dts" -+ -+/ { -+ sound-hdmi { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts -new file mode 100644 -index 000000000..57e0ab2bf ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts -@@ -0,0 +1,187 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+ -+/ { -+ model = "Freescale i.MX8MQ EVK"; -+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial1 = &uart2; -+ mmc2 = &usdhc1; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ interrupt-affinity = <&A53_2>, <&A53_3>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ osc_25m: clock-osc-25m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <25000000>; -+ clock-output-names = "osc_25m"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ clk_dummy: clock@7 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ /* The clocks are configured by 1st OS */ -+ clk_400m: clock@8 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ clock-output-names = "400m"; -+ }; -+ clk_266m: clock@9 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <266000000>; -+ clock-output-names = "266m"; -+ }; -+ clk_80m: clock@10 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <80000000>; -+ clock-output-names = "80m"; -+ }; -+ -+ pci@bfb00000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 54 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xbfb00000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; -+ -+ aips3: bus@30800000 { -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x08000000 0x08000000 0x10000000>; -+ -+ uart2: serial@30890000 { -+ compatible = "fsl,imx8mq-uart", -+ "fsl,imx6q-uart"; -+ reg = <0x30890000 0x10000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usdhc1: mmc@30b40000 { -+ compatible = "fsl,imx8mq-usdhc", -+ "fsl,imx7d-usdhc"; -+ reg = <0x30b40000 0x10000>; -+ interrupts = ; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step = <2>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; -+ -+&uart2 { -+ clocks = <&osc_25m>, -+ <&osc_25m>; -+ clock-names = "ipg", "per"; -+ /delete-property/ dmas; -+ /delete-property/ dmas-names; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ clocks = <&clk_dummy>, -+ <&clk_266m>, -+ <&clk_400m>; -+ /delete-property/assigned-clocks; -+ /delete-property/assigned-clock-rates; -+ clock-names = "ipg", "ahb", "per"; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts -new file mode 100644 -index 000000000..2cbd4752f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts -@@ -0,0 +1,93 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2019 NXP. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ sound-hdmi { -+ status = "disabled"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "disabled"; -+}; -+ -+&dcss { -+ status = "disabled"; -+}; -+ -+&lcdif { -+ status = "okay"; -+ max-memory-bandwidth = <221184000>; /* 1280x720-32@60 */ -+ -+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; -+ -+ port@0 { -+ lcdif_out: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+&adv_bridge { -+ status = "okay"; -+ -+ port@0 { -+ adv7535_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ /delete-node/ panel@0; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ mipi_dsi_in: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&lcdif_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&adv7535_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts -new file mode 100644 -index 000000000..380be2e89 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts -@@ -0,0 +1,97 @@ -+/* -+ * Copyright 2018 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+&lcdif { -+ status = "okay"; -+ max-memory-bandwidth = <497829888>; /* 1920x1080-32@60.02 */ -+ -+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; -+ -+ port@0 { -+ lcdif_mipi_dsi: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ panel@0 { -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ pinctrl-names = "default"; -+ reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ mipi_dsi_in: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&lcdif_mipi_dsi>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 -+ >; -+ }; -+}; -+ -+&synaptics_dsx_ts { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts -new file mode 100644 -index 000000000..d13ef146c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8mq-evk-lcdif-rm67191.dts" -+ -+/delete-node/ &synaptics_dsx_ts; -+ -+&mipi_dsi { -+ panel@0 { -+ compatible = "raydium,rm67199"; -+ }; -+}; -+ -+&i2c3 { -+ touchscreen@14 { -+ compatible = "goodix,gt1151"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; -+ edge-failling-trigger; -+ touchscreen-size-x = <1080>; -+ touchscreen-size-y = <1920>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts -new file mode 100644 -index 000000000..753404149 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mq-evk.dts" -+ -+&pcie0{ -+ status = "disabled"; -+}; -+ -+&pcie1{ -+ status = "disabled"; -+}; -+ -+&pcie1_ep{ -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts -new file mode 100644 -index 000000000..ddc574684 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts -@@ -0,0 +1,29 @@ -+/* -+ * Copyright 2017-2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ modem_reset: modem-reset { -+ reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&pcie0{ -+ status = "disabled"; -+}; -+ -+&gpio5 { -+ /delete-node/ wl-reg-on-hog; /* disable the on-board wifi */ -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts -new file mode 100644 -index 000000000..0f5d7b73d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts -@@ -0,0 +1,44 @@ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ sound-pdm { -+ compatible = "fsl,imx-pdm-mic"; -+ model = "imx-pdm-audio"; -+ audio-cpu = <&sai3>; -+ decimation = <64>; -+ status = "okay"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts -new file mode 100644 -index 000000000..1b6a41ba7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts -@@ -0,0 +1,92 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ interrupt-parent = <&gic>; -+}; -+ -+&CPU_SLEEP { -+ /* We are not using GPC for now, need set 0 to avoid hang */ -+ arm,psci-suspend-param = <0x0>; -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&iomuxc { -+ /* -+ * Used for the 2nd Linux. -+ * TODO: M4 may use these pins. -+ */ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 -+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 -+ >; -+ }; -+}; -+ -+&{/busfreq} { -+ /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ -+ status = "disabled"; -+}; -+ -+&resmem { -+ jh_reserved: jh@fdc00000 { -+ no-map; -+ reg = <0 0xfdc00000 0x0 0x400000>; -+ }; -+ -+ inmate_reserved: inmate@c0000000 { -+ no-map; -+ reg = <0 0xc0000000 0x0 0x3dc00000>; -+ }; -+ -+ loader_reserved: loader@bff00000 { -+ no-map; -+ reg = <0 0xbff00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem_reserved: ivshmem@bfe00000 { -+ no-map; -+ reg = <0 0xbfe00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem2_reserved: ivshmem2@bfd00000 { -+ no-map; -+ reg = <0 0xbfd00000 0x0 0x00100000>; -+ }; -+ -+ pci_reserved: pci@bfc00000 { -+ no-map; -+ reg = <0 0xbfb00000 0x0 0x00200000>; -+ }; -+}; -+ -+&uart1 { -+ /* uart2 is used by the 2nd OS, so configure pin and clk */ -+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>, -+ <&clk IMX8MQ_CLK_UART2>; -+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, -+ <&clk IMX8MQ_CLK_25M>; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ /* sdhc1 is used by 2nd linux, configure the pin */ -+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>; -+ pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts -new file mode 100644 -index 000000000..8f2caf042 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ vdev0vring0: vdev0vring0@b8000000 { -+ reg = <0 0xb8000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@b8008000 { -+ reg = <0 0xb8008000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@b80ff000 { -+ reg = <0 0xb80ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@b8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xb8400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ imx8mq-cm4 { -+ compatible = "fsl,imx8mq-cm4"; -+ rsc-da = <0xb8000000>; -+ clocks = <&clk IMX8MQ_CLK_M4_DIV>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; -+ syscon = <&src>; -+ }; -+}; -+ -+/* -+ * Regarding to the HW conflications, the following module should be disabled -+ * when M4 is running on evk board. -+ * gpt1, i2c2, pwm4, tmu, uart2 -+ */ -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&pwm4 { -+ status = "disabled"; -+}; -+ -+&tmu { -+ status = "disabled"; -+}; -+ -+&uart2 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts -new file mode 100644 -index 000000000..3186f97fa ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts -@@ -0,0 +1,51 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mq-evk.dts" -+ -+&pinctrl_usdhc2 { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 -+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 -+ >; -+}; -+ -+&pinctrl_usdhc2_100mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 -+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 -+ >; -+}; -+ -+&pinctrl_usdhc2_200mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 -+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 -+ >; -+}; -+ -+&usdhc2 { -+ pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; -+ /delete-property/ cd-gpios; -+ keep-power-in-suspend; -+ non-removable; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts -new file mode 100644 -index 000000000..da899f88a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts -@@ -0,0 +1,89 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8mq-evk.dts" -+ -+/ { -+ modem_reset: modem-reset { -+ reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ usdhc2_pwrseq: usdhc2_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pinctrl_usdhc2 { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 -+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 -+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 -+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ >; -+}; -+ -+&pinctrl_usdhc2_100mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 -+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 -+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 -+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ >; -+}; -+ -+&pinctrl_usdhc2_200mhz { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 -+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 -+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 -+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ >; -+}; -+ -+&pcie0{ -+ status = "disabled"; -+}; -+ -+&pcie1{ -+ status = "disabled"; -+ /delete-node/ wifi_wake_host; -+}; -+ -+&usdhc2 { -+ pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; -+ /delete-property/ cd-gpios; -+ keep-power-in-suspend; -+ non-removable; -+ wakeup-source; -+ mmc-pwrseq = <&usdhc2_pwrseq>; -+ fsl,sdio-interrupt-enabled; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpio2>; -+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&gpio5 { -+ /delete-node/ wl-reg-on-hog; /* disable the on-board wifi */ -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts -old mode 100644 -new mode 100755 -index 2418cca00..cb87cd497 ---- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts -@@ -6,6 +6,7 @@ - - /dts-v1/; - -+#include - #include "imx8mq.dtsi" - - / { -@@ -21,12 +22,55 @@ memory@40000000 { - reg = <0x00000000 0x40000000 0 0xc0000000>; - }; - -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x38000000>; -+ alloc-ranges = <0 0x80000000 0 0x38000000>; -+ linux,cma-default; -+ }; -+ }; -+ - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - -+ pcie1_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ ptn36043 { -+ compatible = "nxp,ptn36043"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ss_sel>; -+ switch-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; -+ orientation-switch; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+ - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; -@@ -35,6 +79,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <20000>; - enable-active-high; - }; - -@@ -57,6 +102,12 @@ ir-receiver { - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; -+ linux,autosuspend-period = <125>; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; - }; - - wm8524: audio-codec { -@@ -65,6 +116,25 @@ wm8524: audio-codec { - wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai3>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; -@@ -80,6 +150,8 @@ sound-wm8524 { - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai2>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <32>; - }; - - link_codec: simple-audio-card,codec { -@@ -87,6 +159,60 @@ link_codec: simple-audio-card,codec { - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - }; - }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx8mq-evk-cdnhdmi", -+ "fsl,imx-audio-cdnhdmi"; -+ model = "imx-audio-hdmi"; -+ audio-cpu = <&sai4>; -+ protocol = <1>; -+ hdmi-out; -+ constraint-rate = <44100>, -+ <88200>, -+ <176400>, -+ <32000>, -+ <48000>, -+ <96000>, -+ <192000>; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif1>; -+ spdif-out; -+ spdif-in; -+ }; -+ -+ sound-hdmi-arc { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-hdmi-arc"; -+ spdif-controller = <&spdif2>; -+ spdif-in; -+ }; -+ -+ sound-ak4458 { -+ compatible = "fsl,imx-audio-ak4458-mq"; -+ model = "ak4458-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&ak4458_1>, <&ak4458_2>; -+ reset-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sound-ak5558 { -+ compatible = "fsl,imx-audio-ak5558-mq"; -+ model = "ak5558-audio"; -+ audio-cpu = <&sai5>; -+ audio-codec = <&ak5558>; -+ }; -+ -+ sound-ak4497 { -+ compatible = "fsl,imx-audio-ak4497-mq"; -+ model = "ak4497-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&ak4497>; -+ status = "disabled"; -+ }; - }; - - &A53_0 { -@@ -105,6 +231,30 @@ &A53_3 { - cpu-supply = <&buck2_reg>; - }; - -+&csi1_bridge { -+ fsl,mipi-mode; -+ fsl,two-8bit-sensor-mode; -+ status = "okay"; -+ -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&csi2_bridge { -+ fsl,mipi-mode; -+ fsl,two-8bit-sensor-mode; -+ status = "okay"; -+ -+ port { -+ csi2_ep: endpoint { -+ remote-endpoint = <&csi2_mipi_ep>; -+ }; -+ }; -+}; -+ - &ddrc { - operating-points-v2 = <&ddrc_opp_table>; - -@@ -132,10 +282,6 @@ opp-800M { - }; - }; - --&dphy { -- status = "okay"; --}; -- - &fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; -@@ -151,8 +297,41 @@ mdio { - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; -- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; -- reset-assert-us = <10000>; -+ at803x,eee-disabled; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi1_sensor_ep: endpoint@0 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ -+ csi1_mipi_ep: endpoint@1 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&mipi_csi_2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi2_sensor_ep: endpoint@0 { -+ remote-endpoint = <&ov5640_mipi2_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ -+ csi2_mipi_ep: endpoint@1 { -+ remote-endpoint = <&csi2_ep>; - }; - }; - }; -@@ -174,8 +353,31 @@ &i2c1 { - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - -+ ov5640_mipi2: ov5640_mipi2@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; -+ assigned-clock-rates = <20000000>; -+ csi_id = <1>; -+ pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ mclk = <20000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi2_ep: endpoint { -+ remote-endpoint = <&mipi2_sensor_ep>; -+ }; -+ }; -+ }; -+ - pmic@8 { - compatible = "fsl,pfuze100"; -+ fsl,pfuze-support-disable-sw; - reg = <0x8>; - - regulators { -@@ -257,37 +459,125 @@ vgen6_reg: vgen6 { - }; - }; - }; --}; - --&lcdif { -- status = "okay"; -+ ptn5110: tcpc@50 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x50>; -+ interrupt-parent = <&gpio3>; -+ interrupts = <3 8>; -+ -+ port { -+ typec_dr_sw: endpoint { -+ remote-endpoint = <&usb3_drd_sw>; -+ }; -+ }; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <15000000>; -+ self-powered; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; - }; - --&mipi_dsi { -- #address-cells = <1>; -- #size-cells = <0>; -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - -- panel@0 { -- pinctrl-0 = <&pinctrl_mipi_dsi>; -+ synaptics_dsx_ts: synaptics_dsx_ts@20 { -+ compatible = "synaptics_dsx"; -+ reg = <0x20>; - pinctrl-names = "default"; -- compatible = "raydium,rm67191"; -- reg = <0>; -- reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; -- dsi-lanes = <4>; -+ pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ synaptics,diagonal-rotation; -+ status = "disabled"; -+ }; - -- port { -- panel_in: endpoint { -- remote-endpoint = <&mipi_dsi_out>; -- }; -- }; -+ ak4458_1: ak4458@10 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x10>; -+ }; -+ -+ ak4458_2: ak4458@12 { -+ compatible = "asahi-kasei,ak4458"; -+ reg = <0x12>; - }; - -- ports { -- port@1 { -- reg = <1>; -- mipi_dsi_out: endpoint { -- remote-endpoint = <&panel_in>; -+ ak5558: ak5558@13 { -+ compatible = "asahi-kasei,ak5558"; -+ reg = <0x13>; -+ reset-gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; -+ }; -+ -+ ak4497: ak4497@11 { -+ compatible = "asahi-kasei,ak4497"; -+ reg = <0x11>; -+ reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; -+ dsd-path = <1>; -+ }; -+ -+ adv_bridge: adv7535@3d { -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ status = "disabled"; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi1_pwn>; -+ clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; -+ assigned-clock-rates = <20000000>; -+ csi_id = <0>; -+ pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ mclk = <20000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; - }; - }; - }; -@@ -302,44 +592,223 @@ &pcie0 { - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>, -+ <&clk IMX8MQ_CLK_PCIE1_PHY>, -+ <&clk IMX8MQ_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <100000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, -+ <&clk IMX8MQ_SYS2_PLL_100M>, -+ <&clk IMX8MQ_SYS2_PLL_250M>; -+ hard-wired = <1>; -+ vph-supply = <&vgen5_reg>; -+ l1ss-disabled; -+ status = "okay"; -+}; -+ -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie1>; -+ disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, -+ <&clk IMX8MQ_CLK_PCIE2_AUX>, -+ <&clk IMX8MQ_CLK_PCIE2_PHY>, -+ <&pcie1_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, -+ <&clk IMX8MQ_CLK_PCIE1_PHY>, -+ <&clk IMX8MQ_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <100000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, -+ <&clk IMX8MQ_SYS2_PLL_100M>, -+ <&clk IMX8MQ_SYS2_PLL_250M>; -+ vph-supply = <&vgen5_reg>; -+ l1ss-disabled; - status = "okay"; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpio5>; -+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&pcie1_ep { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie1>; -+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, -+ <&clk IMX8MQ_CLK_PCIE2_AUX>, -+ <&clk IMX8MQ_CLK_PCIE2_PHY>, -+ <&pcie1_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, -+ <&clk IMX8MQ_CLK_PCIE1_PHY>, -+ <&clk IMX8MQ_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <100000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, -+ <&clk IMX8MQ_SYS2_PLL_100M>, -+ <&clk IMX8MQ_SYS2_PLL_250M>; -+ status = "disabled"; - }; - - &pgc_gpu { - power-supply = <&sw1a_reg>; - }; - -+&pgc_vpu { -+ power-supply = <&sw1c_reg>; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "pcm_b2m", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1_pcm>; -+ pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; -+ pinctrl-2 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, -+ <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; -+ status = "okay"; -+}; -+ -+&sai2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai3 { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai4 { -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, -+ <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, -+ <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&snvs_pwrkey { -+ status = "okay"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>, -+ <&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&spdif2 { -+ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ - &qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - -- n25q256a: flash@0 { -+ flash0: n25q256a@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; -- compatible = "micron,n25q256a", "jedec,spi-nor"; -+ compatible = "jedec,spi-nor"; - spi-max-frequency = <29000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ spi-nor,ddr-quad-read-dummy = <6>; - }; - }; - --&sai2 { -+&uart1 { - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_sai2>; -- assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; -- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; -- assigned-clock-rates = <0>, <24576000>; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; - }; - --&snvs_pwrkey { -+&uart3 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; - status = "okay"; - }; - --&uart1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_uart1>; -+&usb3_phy0 { -+ vbus-power-supply = <&ptn5110>; -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ usb-role-switch; -+ role-switch-default-mode = "none"; -+ snps,dis-u1-entry-quirk; -+ snps,dis-u2-entry-quirk; - status = "okay"; -+ -+ port { -+ usb3_drd_sw: endpoint { -+ remote-endpoint = <&typec_dr_sw>; -+ }; -+ }; - }; - - &usb3_phy1 { -@@ -386,6 +855,19 @@ &wdog1 { - }; - - &iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 -+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 -+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 -+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 -+ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x16 -+ >; -+ }; -+ - pinctrl_buck2: vddarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 -@@ -393,6 +875,24 @@ MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - - }; - -+ pinctrl_csi1_pwn: csi1_pwn_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 -+ >; -+ }; -+ pinctrl_csi2_pwn: csi2_pwn_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 -+ >; -+ }; -+ - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -@@ -426,9 +926,23 @@ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f - >; - }; - -- pinctrl_mipi_dsi: mipidsigrp { -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f -+ >; -+ }; -+ -+ pinctrl_i2c1_dsi_ts_int: dsi_ts_int { - fsl,pins = < -- MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 -+ MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 -+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 - >; - }; - -@@ -439,6 +953,15 @@ MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 - >; - }; - -+ pinctrl_pcie1: pcie1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ -+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 -+ MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 -+ MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 -+ >; -+ }; -+ - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 -@@ -463,7 +986,97 @@ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 -- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_pcm: sai1grp_pcm { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 -+ >; -+ }; -+ -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 -+ >; -+ }; -+ -+ pinctrl_ss_sel: usb3ssgrp{ -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 -+ >; -+ }; -+ -+ pinctrl_typec: typecgrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 - >; - }; - -@@ -474,6 +1087,16 @@ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 -+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 -+ MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 -+ MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 -+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 -+ >; -+ }; -+ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 -@@ -573,3 +1196,41 @@ MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 - >; - }; - }; -+ -+&vpu { -+ status = "okay"; -+}; -+ -+&vpu_v4l2 { -+ status = "okay"; -+}; -+ -+&gpu3d { -+ status = "okay"; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+ -+ port@0 { -+ dcss_out: endpoint { -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+}; -+ -+&hdmi { -+ compatible = "cdn,imx8mq-hdmi"; -+ lane-mapping = <0xe4>; -+ hdcp-config = <0x3>; -+ status = "okay"; -+ port@1 { -+ hdmi_in: endpoint { -+ remote-endpoint = <&dcss_out>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h -index 68e8fa172..760321ac5 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h -+++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h -@@ -555,12 +555,12 @@ - #define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 - #define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 - #define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 --#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 - #define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 - #define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 - #define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 - #define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 --#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x12 0x0 - #define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 - #define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 - #define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi -old mode 100644 -new mode 100755 -index c86cf786f..4071063d6 ---- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi -@@ -20,6 +20,8 @@ / { - #size-cells = <2>; - - aliases { -+ csi0 = &mipi_csi_1; -+ csi1 = &mipi_csi_2; - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; -@@ -106,6 +108,7 @@ A53_0: cpu@0 { - #cooling-cells = <2>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; -+ cpu-idle-states = <&CPU_SLEEP>; - }; - - A53_1: cpu@1 { -@@ -118,6 +121,7 @@ A53_1: cpu@1 { - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SLEEP>; - }; - - A53_2: cpu@2 { -@@ -130,6 +134,7 @@ A53_2: cpu@2 { - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SLEEP>; - }; - - A53_3: cpu@3 { -@@ -142,11 +147,27 @@ A53_3: cpu@3 { - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SLEEP>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; -+ -+ idle-states { -+ entry-method = "psci"; -+ -+ CPU_SLEEP: cpu-sleep { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0010033>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ wakeup-latency-us = <1500>; -+ }; -+ }; -+ - }; - - a53_opp_table: opp-table { -@@ -231,48 +252,6 @@ map0 { - }; - }; - }; -- -- gpu-thermal { -- polling-delay-passive = <250>; -- polling-delay = <2000>; -- thermal-sensors = <&tmu 1>; -- -- trips { -- gpu_alert: gpu-alert { -- temperature = <80000>; -- hysteresis = <2000>; -- type = "passive"; -- }; -- -- gpu-crit { -- temperature = <90000>; -- hysteresis = <2000>; -- type = "critical"; -- }; -- }; -- -- cooling-maps { -- map0 { -- trip = <&gpu_alert>; -- cooling-device = -- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -- }; -- }; -- }; -- -- vpu-thermal { -- polling-delay-passive = <250>; -- polling-delay = <2000>; -- thermal-sensors = <&tmu 2>; -- -- trips { -- vpu-crit { -- temperature = <90000>; -- hysteresis = <2000>; -- type = "critical"; -- }; -- }; -- }; - }; - - timer { -@@ -285,12 +264,38 @@ timer { - arm,no-tick-in-suspend; - }; - -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, -+ <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>, -+ <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>, -+ <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>, -+ <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>, -+ <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m", -+ "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src", -+ "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m"; -+ interrupts = , , -+ , ; -+ interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ }; -+ - soc@0 { -- compatible = "simple-bus"; -+ compatible = "fsl,imx8mq-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; -+ nvmem-cells = <&imx8mq_uid>; -+ nvmem-cell-names = "soc_unique_id"; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; - - bus@30000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; -@@ -301,57 +306,70 @@ bus@30000000 { /* AIPS1 */ - - sai1: sai@30010000 { - #sound-dai-cells = <0>; -- compatible = "fsl,imx8mq-sai"; -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, -- <&clk IMX8MQ_CLK_SAI1_ROOT>, -- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -- dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI1_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 1 0>, <&sdma2 9 1 0>; - dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xff 0xff>; - status = "disabled"; - }; - - sai6: sai@30030000 { - #sound-dai-cells = <0>; -- compatible = "fsl,imx8mq-sai"; -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, -- <&clk IMX8MQ_CLK_SAI6_ROOT>, -- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI6_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; - dma-names = "rx", "tx"; -+ fsl,shared-interrupt; - status = "disabled"; - }; - - sai5: sai@30040000 { - #sound-dai-cells = <0>; -- compatible = "fsl,imx8mq-sai"; -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; - reg = <0x30040000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, -- <&clk IMX8MQ_CLK_SAI5_ROOT>, -- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI5_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; - dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; - status = "disabled"; - }; - - sai4: sai@30050000 { - #sound-dai-cells = <0>; -- compatible = "fsl,imx8mq-sai"; -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, -- <&clk IMX8MQ_CLK_SAI4_ROOT>, -- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI4_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; - dma-names = "rx", "tx"; -+ fsl,dataline = <0 0x0 0xf>; - status = "disabled"; - }; - -@@ -470,7 +488,7 @@ tmu: tmu@30260000 { - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; -- #thermal-sensor-cells = <1>; -+ #thermal-sensor-cells = <0>; - }; - - wdog1: watchdog@30280000 { -@@ -497,7 +515,7 @@ wdog3: watchdog@302a0000 { - status = "disabled"; - }; - -- sdma2: sdma@302c0000 { -+ sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; -@@ -555,9 +573,17 @@ ocotp: efuse@30350000 { - #address-cells = <1>; - #size-cells = <1>; - -+ imx8mq_uid: soc-uid@410 { -+ reg = <0x4 0x8>; -+ }; -+ - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; -+ -+ fec_mac_address: mac-address@640 { -+ reg = <0x90 6>; -+ }; - }; - - anatop: syscon@30360000 { -@@ -566,6 +592,22 @@ anatop: syscon@30360000 { - interrupts = ; - }; - -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; -+ clock-names = "ipg"; -+ }; -+ - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; -@@ -606,11 +648,20 @@ clk: clock-controller@30380000 { - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, - <&clk IMX8MQ_CLK_A53_CORE>, -- <&clk IMX8MQ_CLK_NOC>; -- assigned-clock-rates = <0>, <0>, -- <800000000>; -+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MQ_CLK_NOC>, -+ <&clk IMX8MQ_CLK_AUDIO_AHB>, -+ <&clk IMX8MQ_AUDIO_PLL1>, -+ <&clk IMX8MQ_AUDIO_PLL2>; -+ assigned-clock-rates = <0>, <0>, <266000000>, -+ <800000000>, <0>, -+ <786432000>, -+ <722534400>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, -- <&clk IMX8MQ_ARM_PLL_OUT>; -+ <&clk IMX8MQ_ARM_PLL_OUT>, -+ <0>, -+ <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_SYS2_PLL_500M>; - }; - - src: reset-controller@30390000 { -@@ -626,6 +677,7 @@ gpc: gpc@303a0000 { - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; -+ broken-wake-request-signals; - #interrupt-cells = <3>; - - pgc { -@@ -779,6 +831,30 @@ bus@30800000 { /* AIPS3 */ - ranges = <0x30800000 0x30800000 0x400000>, - <0x08000000 0x08000000 0x10000000>; - -+ spdif1: spdif@30810000 { -+ compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; -+ reg = <0x30810000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ -+ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ -+ <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MQ_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; -@@ -834,6 +910,8 @@ uart3: serial@30880000 { - clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, - <&clk IMX8MQ_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; -+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; -+ dma-names = "rx", "tx"; - status = "disabled"; - }; - -@@ -845,6 +923,32 @@ uart2: serial@30890000 { - clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, - <&clk IMX8MQ_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; -+ dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ spdif2: spdif@308a0000 { -+ compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; -+ reg = <0x308a0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ -+ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ -+ <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MQ_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; -+ dma-names = "rx", "tx"; - status = "disabled"; - }; - -@@ -854,9 +958,10 @@ sai2: sai@308b0000 { - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, - <&clk IMX8MQ_CLK_SAI2_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -864,13 +969,15 @@ sai2: sai@308b0000 { - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; -- compatible = "fsl,imx8mq-sai"; -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, -- <&clk IMX8MQ_CLK_SAI3_ROOT>, -- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -- clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI3_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; -@@ -913,14 +1020,20 @@ mipi_dsi: mipi-dsi@30a00000 { - <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>, - <&clk IMX8MQ_CLK_DSI_PHY_REF>, -+ <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>; -- clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; -- assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, -+ clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "video_pll", "lcdif"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_CLK_DSI_CORE>, -+ <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>; -- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, -- <&clk IMX8MQ_SYS1_PLL_266M>; -- assigned-clock-rates = <80000000>, <266000000>, <20000000>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_SYS1_PLL_266M>, -+ <&clk IMX8MQ_SYS1_PLL_80M>; -+ assigned-clock-rates = <27000000>, -+ <266000000>, -+ <80000000>, -+ <20000000>; - interrupts = ; - mux-controls = <&mux 0>; - power-domains = <&pgc_mipi>; -@@ -1010,6 +1123,37 @@ uart4: serial@30a60000 { - clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, - <&clk IMX8MQ_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; -+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: mipi_csi1@30a70000 { -+ compatible = "fsl,mxc-mipi-csi2_yav"; -+ reg = <0x30a70000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, -+ <&clk IMX8MQ_CLK_CSI1_ESC>, -+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>; -+ clock-names = "clk_core", "clk_esc", "clk_pxl"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, -+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>, -+ <&clk IMX8MQ_CLK_CSI1_ESC>; -+ assigned-clock-rates = <133000000>, <100000000>, <66000000>; -+ power-domains = <&pgc_mipi_csi1>; -+ csis-phy-reset = <&src 0x4c 7>; -+ phy-gpr = <&iomuxc_gpr 0x88>; -+ status = "disabled"; -+ }; -+ -+ csi1_bridge: csi1_bridge@30a90000 { -+ compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x30a90000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_CSI1_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; - status = "disabled"; - }; - -@@ -1018,6 +1162,7 @@ mu: mailbox@30aa0000 { - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_MU_ROOT>; -+ clock-names = "mu"; - #mbox-cells = <2>; - }; - -@@ -1051,6 +1196,35 @@ usdhc2: mmc@30b50000 { - status = "disabled"; - }; - -+ mipi_csi_2: mipi_csi2@30b60000 { -+ compatible = "fsl,mxc-mipi-csi2_yav"; -+ reg = <0x30b60000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, -+ <&clk IMX8MQ_CLK_CSI2_ESC>, -+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>; -+ clock-names = "clk_core", "clk_esc", "clk_pxl"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, -+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>, -+ <&clk IMX8MQ_CLK_CSI2_ESC>; -+ assigned-clock-rates = <133000000>, <100000000>, <66000000>; -+ power-domains = <&pgc_mipi_csi2>; -+ csis-phy-reset = <&src 0x50 7>; -+ phy-gpr = <&iomuxc_gpr 0xa4>; -+ status = "disabled"; -+ }; -+ -+ csi2_bridge: csi2_bridge@30b80000 { -+ compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x30b80000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_CSI2_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; -+ status = "disabled"; -+ }; -+ - qspi0: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; -@@ -1065,7 +1239,7 @@ qspi0: spi@30bb0000 { - status = "disabled"; - }; - -- sdma1: sdma@30bd0000 { -+ sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; -@@ -1090,12 +1264,49 @@ fec1: ethernet@30be0000 { - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; -+ assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, -+ <&clk IMX8MQ_CLK_ENET_TIMER>, -+ <&clk IMX8MQ_CLK_ENET_REF>, -+ <&clk IMX8MQ_CLK_ENET_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, -+ <&clk IMX8MQ_SYS2_PLL_100M>, -+ <&clk IMX8MQ_SYS2_PLL_125M>, -+ <&clk IMX8MQ_SYS2_PLL_50M>; -+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; -+ nvmem-cells = <&fec_mac_address>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ fsl,stop-mode = <&iomuxc_gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; - status = "disabled"; - }; - }; - -+ noc: interconnect@32700000 { -+ compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; -+ reg = <0x32700000 0x100000>; -+ clocks = <&clk IMX8MQ_CLK_NOC>; -+ fsl,ddrc = <&ddrc>; -+ #interconnect-cells = <1>; -+ operating-points-v2 = <&noc_opp_table>; -+ -+ noc_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-133M { -+ opp-hz = /bits/ 64 <133333333>; -+ }; -+ opp-400M { -+ opp-hz = /bits/ 64 <400000000>; -+ }; -+ opp-800M { -+ opp-hz = /bits/ 64 <800000000>; -+ }; -+ }; -+ }; -+ - bus@32c00000 { /* AIPS4 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; -@@ -1103,6 +1314,14 @@ bus@32c00000 { /* AIPS4 */ - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - -+ hdmi: hdmi@32c00000 { -+ reg = <0x32c00000 0x100000>, -+ <0x32e40000 0x40000>; -+ interrupts = , -+ ; -+ interrupt-names = "plug_in", "plug_out"; -+ }; -+ - irqsteer: interrupt-controller@32e2d000 { - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; -@@ -1114,6 +1333,35 @@ irqsteer: interrupt-controller@32e2d000 { - interrupt-controller; - #interrupt-cells = <1>; - }; -+ -+ dcss: display-controller@32e00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mq-dcss"; -+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; -+ interrupts = <6>, <8>, <9>, <16>, <17>; -+ interrupt-names = "ctxld", "ctxld_kick", "vblank", -+ "dtrc_ch1", "dtrc_ch2"; -+ interrupt-parent = <&irqsteer>; -+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, -+ <&clk IMX8MQ_VIDEO2_PLL_OUT>, -+ <&clk IMX8MQ_CLK_DISP_DTRC>, -+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, -+ <&clk IMX8MQ_CLK_PHY_27MHZ>; -+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", -+ "pll_phy_ref"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, -+ <&clk IMX8MQ_CLK_DISP_RTRM>, -+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rates = <800000000>, -+ <400000000>; -+ status = "disabled"; -+ }; - }; - - gpu: gpu@38000000 { -@@ -1139,6 +1387,7 @@ gpu: gpu@38000000 { - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>, <0>; - power-domains = <&pgc_gpu>; -+ status = "disabled"; - }; - - usb_dwc3_0: usb@38100000 { -@@ -1158,6 +1407,9 @@ usb_dwc3_0: usb@38100000 { - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg1>; - usb3-resume-missing-cas; -+ snps,power-down-scale = <2>; -+ snps,parkmode-disable-ss-quirk; -+ snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - -@@ -1190,6 +1442,9 @@ usb_dwc3_1: usb@38200000 { - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg2>; - usb3-resume-missing-cas; -+ snps,power-down-scale = <2>; -+ snps,parkmode-disable-ss-quirk; -+ snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - -@@ -1205,30 +1460,33 @@ usb3_phy1: usb-phy@382f0040 { - status = "disabled"; - }; - -- vpu: video-codec@38300000 { -- compatible = "nxp,imx8mq-vpu"; -- reg = <0x38300000 0x10000>, -- <0x38310000 0x10000>, -- <0x38320000 0x10000>; -- reg-names = "g1", "g2", "ctrl"; -- interrupts = , -- ; -- interrupt-names = "g1", "g2"; -- clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, -- <&clk IMX8MQ_CLK_VPU_G2_ROOT>, -- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; -- clock-names = "g1", "g2", "bus"; -- assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, -- <&clk IMX8MQ_CLK_VPU_G2>, -- <&clk IMX8MQ_CLK_VPU_BUS>, -- <&clk IMX8MQ_VPU_PLL_BYPASS>; -- assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, -- <&clk IMX8MQ_VPU_PLL_OUT>, -- <&clk IMX8MQ_SYS1_PLL_800M>, -- <&clk IMX8MQ_VPU_PLL>; -- assigned-clock-rates = <600000000>, <600000000>, -- <800000000>, <0>; -- power-domains = <&pgc_vpu>; -+ dma_apbh: dma-apbh@33000000 { -+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; -+ reg = <0x33000000 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ }; -+ -+ gpmi: gpmi-nand@33002000{ -+ compatible = "fsl,imx7d-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, -+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ clock-names = "gpmi_io", "gpmi_bch_apb"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ status = "disabled"; - }; - - pcie0: pcie@33800000 { -@@ -1244,20 +1502,23 @@ pcie0: pcie@33800000 { - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; -- interrupts = ; -- interrupt-names = "msi"; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; -+ linux,pci-domain = <0>; - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -- <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -- reset-names = "pciephy", "apps", "turnoff"; -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "clkreq", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; -@@ -1281,20 +1542,23 @@ pcie1: pcie@33c00000 { - 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; -- interrupts = ; -- interrupt-names = "msi"; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; -+ linux,pci-domain = <1>; - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY2>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, -- <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; -- reset-names = "pciephy", "apps", "turnoff"; -+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "clkreq", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; -@@ -1306,6 +1570,25 @@ pcie1: pcie@33c00000 { - status = "disabled"; - }; - -+ pcie1_ep: pcie_ep@33c00000 { -+ compatible = "fsl,imx8mq-pcie-ep"; -+ reg = <0x33c00000 0x000400000>, -+ <0x20000000 0x08000000>; -+ reg-names = "regs", "addr_space"; -+ num-lanes = <1>; -+ interrupts = ; /* eDMA */ -+ interrupt-names = "dma"; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pgc_pcie>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY2>, -+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "turnoff"; -+ num-ib-windows = <4>; -+ num-ob-windows = <4>; -+ status = "disabled"; -+ }; -+ - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ -@@ -1335,5 +1618,49 @@ ddr-pmu@3d800000 { - interrupt-parent = <&gic>; - interrupts = ; - }; -+ -+ vpu: vpu@38300000 { -+ compatible = "nxp,imx8mq-hantro"; -+ reg = <0x38300000 0x200000>; -+ reg-names = "regs_hantro"; -+ interrupts = , ; -+ interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; -+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; -+ assigned-clock-rates = <600000000>, <600000000>, <800000000>; -+ power-domains = <&pgc_vpu>; -+ status = "disabled"; -+ }; -+ -+ vpu_v4l2: vpu_v4l2 { -+ compatible = "nxp,imx8m-vsiv4l2"; -+ status = "disabled"; -+ }; -+ }; -+ -+ gpu3d: gpu3d@38000000 { -+ compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; -+ reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; -+ reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; -+ interrupts = ; -+ interrupt-names = "irq_3d"; -+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>; -+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; -+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>; -+ assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; -+ power-domains = <&pgc_gpu>; -+ status = "disabled"; - }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8q-val.dtsi b/arch/arm64/boot/dts/freescale/imx8q-val.dtsi -new file mode 100644 -index 000000000..50f47bd09 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8q-val.dtsi -@@ -0,0 +1,1007 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/ { -+ chosen { -+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; -+ stdout-path = &lpuart0; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ user { -+ label = "heartbeat"; -+ gpios = <&lsio_gpio2 15 0>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ decoder_boot: decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ }; -+ encoder_boot: encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ }; -+ /* -+ * reserved-memory layout -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ decoder_rpc: decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x200000>; -+ }; -+ encoder_rpc: encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x200000>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_reserved: encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0x96000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_audio: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_can_en: regulator-can-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can_stby: regulator-can-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can_en>; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2_vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "sw-3p3-sd1"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; -+ off-on-delay = <3000>; -+ enable-active-high; -+ }; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ audio-cpu = <&esai0>; -+ audio-codec = <&codec>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ }; -+}; -+ -+&acm { -+ status = "okay"; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ imx8qm-val { -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 -+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 -+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 -+ IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 -+ IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 -+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c -+ IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c -+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c -+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lpi2c0: lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c -+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpi2c1: lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c -+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpi2c2: lpi2c2grp { -+ fsl,pins = < -+ IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c -+ IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 -+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 -+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 -+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 -+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 -+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 -+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 -+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 -+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan2grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 -+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledsgrp { -+ fsl,pins = < -+ IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 -+ >; -+ }; -+ -+ pinctrl_pciea: pcieagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 -+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 -+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 -+ >; -+ }; -+ -+ pinctrl_pcieb: pciebgrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 -+ IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 -+ IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lvds0_pwm0: lvds0pwm0grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_lvds1_pwm0: lvds1pwm0grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 -+ IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 -+ IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 -+ >; -+ }; -+ }; -+}; -+ -+&lsio_gpio2 { -+ status = "okay"; -+}; -+ -+&lsio_gpio5 { -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-polarity-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbotg3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&gpio0_mipi_csi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; -+ status = "okay"; -+}; -+ -+&gpio0_mipi_csi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; -+ status = "okay"; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6A>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6A>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ port { -+ max9286_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_hdmi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+}; -+ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ codec: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&pca9557_a 2 1>; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1>; -+ status = "okay"; -+ -+ pca9557_a: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@19 { -+ compatible = "nxp,pca9557"; -+ reg = <0x19>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_c: gpio@1b { -+ compatible = "nxp,pca9557"; -+ reg = <0x1b>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_d: gpio@1f { -+ compatible = "nxp,pca9557"; -+ reg = <0x1f>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ fxas2100x@20 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x20>; -+ }; -+ -+ fxos8700@1d { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1d>; -+ }; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio3>; -+ interrupts = <20 2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ }; -+}; -+ -+&i2c2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c2>; -+ status = "okay"; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&lpuart0 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&lpuart3 { /* GPS */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "disabled"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS1) */ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&max9286_1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+}; -+ -+&isi_1 { -+ status = "okay"; -+}; -+ -+&isi_2 { -+ status = "okay"; -+}; -+ -+&isi_3 { -+ status = "okay"; -+}; -+ -+&gpu_3d0 { -+ status = "okay"; -+}; -+ -+&gpu_3d1 { -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ status = "okay"; -+}; -+ -+&pciea{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&pcieb{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; -+ clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&cm41_intmux { -+ status = "okay"; -+}; -+ -+&ldb1_phy { -+ status = "okay"; -+}; -+ -+&ldb1 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ clock-lanes = <3>; -+ data-lanes = <0 1 2 4>; -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "okay"; -+}; -+ -+&ldb2 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_1_in: endpoint { -+ clock-lanes = <3>; -+ data-lanes = <0 1 2 4>; -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi -new file mode 100644 -index 000000000..6775cad49 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi -@@ -0,0 +1,397 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fec1; -+ mmc1 = &usdhc2; -+ mmc2 = &usdhc3; -+ serial0 = &lpuart0; -+ serial3 = &lpuart3; -+ mu1 = &lsio_mu1; -+ mu8 = &lsio_mu8; -+ can0 = &flexcan1; -+ can1 = &flexcan2; -+ can2 = &flexcan3; -+ dpu0 = &dpu1; -+ ldb0 = &ldb1; -+ i2c0 = &i2c_rpbus_0; -+ i2c1 = &i2c_rpbus_1; -+ dphy0 = &mipi0_dphy; -+ mipi_dsi0 = &mipi0_dsi_host; -+ }; -+ -+ cpus: cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&A53_0>; -+ }; -+ core1 { -+ cpu = <&A53_1>; -+ }; -+ core2 { -+ cpu = <&A53_2>; -+ }; -+ core3 { -+ cpu = <&A53_3>; -+ }; -+ }; -+ }; -+ -+ A53_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x0>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x1>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x2>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x3>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a53_opp_table: a53-opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <900000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-900000000 { -+ opp-hz = /bits/ 64 <900000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1104000000 { -+ opp-hz = /bits/ 64 <1104000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xC0000>, /* GICR */ -+ <0x0 0x52000000 0 0x2000>, /* GICC */ -+ <0x0 0x52010000 0 0x1000>, /* GICH */ -+ <0x0 0x52020000 0 0x20000>; /* GICV */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ smmu: iommu@51400000 { -+ compatible = "arm,mmu-500"; -+ interrupt-parent = <&gic>; -+ reg = <0 0x51400000 0 0x40000>; -+ #global-interrupts = <1>; -+ #iommu-cells = <2>; -+ interrupts = <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; -+ status = "disabled"; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", -+ "rx0", -+ "gip3"; -+ mboxes = <&lsio_mu1 0 0 -+ &lsio_mu1 1 0 -+ &lsio_mu1 3 3>; -+ -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ wakeup-irq = <235 236 237 258 262 267 271 -+ 345 346 347 348>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8qm-iomuxc"; -+ }; -+ -+ ocotp: imx8qm-ocotp { -+ compatible = "fsl,imx8qm-scu-ocotp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ read-only; -+ -+ fec_mac0: mac@1c4 { -+ reg = <0x1c4 6>; -+ }; -+ -+ fec_mac1: mac@1c6 { -+ reg = <0x1c6 6>; -+ }; -+ }; -+ -+ rtc: rtc { -+ compatible = "fsl,imx8qm-sc-rtc"; -+ }; -+ -+ watchdog { -+ compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; -+ timeout-sec = <60>; -+ }; -+ -+ tsens: thermal-sensor { -+ compatible = "fsl,imx8qm-sc-thermal"; -+ tsens-num = <4>; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ thermal_zones: thermal-zones { -+ cpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_A53>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; -+ trips { -+ gpu_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ gpu_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ drc-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_DRC_0>; -+ trips { -+ drc_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ drc_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ -+ imx_shmem_net: imx_shmem_net { -+ compatible = "fsl,imx-shmem-net"; -+ mub-partition = <3>; -+ mbox-names = "tx", "rx"; -+ mboxes = <&lsio_mu8 0 1 -+ &lsio_mu8 1 1>; -+ status = "disabled"; -+ }; -+ -+ sc_pwrkey: sc-powerkey { -+ compatible = "fsl,imx8-pwrkey"; -+ linux,keycode = ; -+ wakeup-source; -+ }; -+ -+ vpu_subsys_dsp: bus@55000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x55000000 0x0 0x55000000 0x1000000>; -+ -+ dsp: dsp@556e8000 { -+ compatible = "fsl,imx8qm-hifi4"; -+ reg = <0x556e8000 0x88000>; -+ clocks = <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>; -+ status = "disabled"; -+ }; -+ }; -+ -+ /* sorted in register address */ -+ #include "imx8-ss-security.dtsi" -+ #include "imx8-ss-cm41.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-ddr.dtsi" -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-hsio.dtsi" -+ #include "imx8-ss-img.dtsi" -+ #include "imx8-ss-dc0.dtsi" -+ #include "imx8-ss-dc1.dtsi" -+ #include "imx8-ss-gpu0.dtsi" -+ #include "imx8-ss-gpu1.dtsi" -+ #include "imx8-ss-vpu.dtsi" -+}; -+ -+#include "imx8qm-ss-audio.dtsi" -+#include "imx8qm-ss-dma.dtsi" -+#include "imx8qm-ss-conn.dtsi" -+#include "imx8qm-ss-ddr.dtsi" -+#include "imx8qm-ss-lsio.dtsi" -+#include "imx8qm-ss-hsio.dtsi" -+#include "imx8qm-ss-dc.dtsi" -+#include "imx8qm-ss-lvds.dtsi" -+#include "imx8qm-ss-mipi.dtsi" -+#include "imx8qm-ss-hdmi.dtsi" -+#include "imx8qm-ss-img.dtsi" -+#include "imx8qm-ss-gpu.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi -new file mode 100644 -index 000000000..1bca8d278 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi -@@ -0,0 +1,369 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet1 = &fec2; -+ mmc0 = &usdhc1; -+ serial2 = &lpuart2; -+ isi0 = &isi_0; -+ isi1 = &isi_1; -+ isi2 = &isi_2; -+ isi3 = &isi_3; -+ isi4 = &isi_4; -+ isi5 = &isi_5; -+ isi6 = &isi_6; -+ isi7 = &isi_7; -+ csi0 = &mipi_csi_0; -+ csi1 = &mipi_csi_1; -+ mu2 = &lsio_mu2; -+ dpu1 = &dpu2; -+ ldb1 = &ldb2; -+ dphy1 = &mipi1_dphy; -+ mipi_dsi1 = &mipi1_dsi_host; -+ }; -+ -+ cpus: cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&A72_0>; -+ }; -+ core1 { -+ cpu = <&A72_1>; -+ }; -+ }; -+ }; -+ -+ A72_0: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72", "arm,armv8"; -+ reg = <0x0 0x100>; -+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A72_L2>; -+ operating-points-v2 = <&a72_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A72_1: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72", "arm,armv8"; -+ reg = <0x0 0x101>; -+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A72_L2>; -+ operating-points-v2 = <&a72_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A72_L2: l2-cache1 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a72_opp_table: a72-opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1296000000 { -+ opp-hz = /bits/ 64 <1296000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1596000000 { -+ opp-hz = /bits/ 64 <1596000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xC0000>, /* GICR */ -+ <0x0 0x52000000 0 0x2000>, /* GICC */ -+ <0x0 0x52010000 0 0x1000>, /* GICH */ -+ <0x0 0x52020000 0 0x20000>; /* GICV */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ smmu: iommu@51400000 { -+ compatible = "arm,mmu-500"; -+ interrupt-parent = <&gic>; -+ reg = <0 0x51400000 0 0x40000>; -+ #global-interrupts = <1>; -+ #iommu-cells = <2>; -+ interrupts = <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; -+ status = "disabled"; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", -+ "rx0", -+ "gip3"; -+ mboxes = <&lsio_mu2 0 0 -+ &lsio_mu2 1 0 -+ &lsio_mu2 3 3>; -+ -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ wakeup-irq = <235 236 237 258 262 267 271 -+ 345 346 347 348>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8qm-iomuxc"; -+ }; -+ -+ ocotp: imx8qm-ocotp { -+ compatible = "fsl,imx8qm-scu-ocotp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ read-only; -+ -+ fec_mac0: mac@1c4 { -+ reg = <0x1c4 6>; -+ }; -+ -+ fec_mac1: mac@1c6 { -+ reg = <0x1c6 6>; -+ }; -+ }; -+ -+ rtc: rtc { -+ compatible = "fsl,imx8qm-sc-rtc"; -+ }; -+ -+ watchdog { -+ compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; -+ timeout-sec = <60>; -+ }; -+ -+ tsens: thermal-sensor { -+ compatible = "fsl,imx8qm-sc-thermal"; -+ tsens-num = <4>; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ thermal_zones: thermal-zones { -+ cpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_A72>; -+ trips { -+ cpu_alert1: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit1: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert1>; -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gpu-thermal1 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; -+ trips { -+ gpu_alert1: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ gpu_crit1: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ drc-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_DRC_0>; -+ trips { -+ drc_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ drc_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ -+ imx_shmem_net: imx_shmem_net { -+ compatible = "fsl,imx-shmem-net"; -+ mub-partition = <1>; -+ mbox-names = "tx", "rx"; -+ mboxes = <&lsio_mu8b 0 1 -+ &lsio_mu8b 1 1>; -+ status = "disabled"; -+ }; -+ -+ sc_pwrkey: sc-powerkey { -+ compatible = "fsl,imx8-pwrkey"; -+ linux,keycode = ; -+ wakeup-source; -+ }; -+ -+ vpu_subsys_dsp: bus@55000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x55000000 0x0 0x55000000 0x1000000>; -+ -+ dsp: dsp@556e8000 { -+ compatible = "fsl,imx8qm-hifi4"; -+ reg = <0x556e8000 0x88000>; -+ clocks = <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>; -+ status = "disabled"; -+ }; -+ }; -+ -+ /* sorted in register address */ -+ #include "imx8-ss-security.dtsi" -+ #include "imx8-ss-cm41.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-ddr.dtsi" -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-hsio.dtsi" -+ #include "imx8-ss-img.dtsi" -+ #include "imx8-ss-dc0.dtsi" -+ #include "imx8-ss-dc1.dtsi" -+ #include "imx8-ss-gpu0.dtsi" -+ #include "imx8-ss-gpu1.dtsi" -+ #include "imx8-ss-vpu.dtsi" -+}; -+ -+#include "imx8qm-ss-audio.dtsi" -+#include "imx8qm-ss-dma.dtsi" -+#include "imx8qm-ss-conn.dtsi" -+#include "imx8qm-ss-ddr.dtsi" -+#include "imx8qm-ss-lsio.dtsi" -+#include "imx8qm-ss-hsio.dtsi" -+#include "imx8qm-ss-dc.dtsi" -+#include "imx8qm-ss-lvds.dtsi" -+#include "imx8qm-ss-mipi.dtsi" -+#include "imx8qm-ss-hdmi.dtsi" -+#include "imx8qm-ss-img.dtsi" -+#include "imx8qm-ss-gpu.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts -new file mode 100644 -index 000000000..a92370a4a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts -@@ -0,0 +1,878 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qm.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QM DDR4 VALIDATION"; -+ compatible = "fsl,imx8qm-val", "fsl,imx8qm"; -+ -+ bcmdhd_wlan_0: bcmdhd_wlan@0 { -+ compatible = "android,bcmdhd_wlan"; -+ bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; -+ bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; -+ stdout-path = &lpuart0; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ user { -+ label = "heartbeat"; -+ gpios = <&lsio_gpio2 15 0>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ decoder_boot: decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ }; -+ encoder_boot: encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ }; -+ /* -+ * reserved-memory layout -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ decoder_rpc: decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x200000>; -+ }; -+ encoder_rpc: encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x200000>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_reserved: encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_audio: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_can_en: regulator-can-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can_stby: regulator-can-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can_en>; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2_vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "sw-3p3-sd1"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&pca9557_b 3 0>; -+ enable-active-high; -+ }; -+ }; -+}; -+ -+&acm { -+ status = "okay"; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&asrc0 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&asrc1 { -+ fsl,asrc-rate = <48000>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ imx8qm-val { -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 -+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 -+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 -+ IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 -+ IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 -+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c -+ IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c -+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c -+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lpi2c0: lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c -+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpi2c1: lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c -+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpi2c2: lpi2c2grp { -+ fsl,pins = < -+ IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c -+ IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 -+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 -+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 -+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc3_gpio: usdhc3grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 -+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 -+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 -+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 -+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 -+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 -+ IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 -+ /* WP */ -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 -+ /* CD */ -+ IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { -+ fsl,pins = < -+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 -+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 -+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 -+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 -+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 -+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 -+ IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 -+ /* WP */ -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 -+ /* CD */ -+ IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { -+ fsl,pins = < -+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 -+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 -+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 -+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 -+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 -+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 -+ IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 -+ /* WP */ -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 -+ /* CD */ -+ IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 -+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan2grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 -+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledsgrp { -+ fsl,pins = < -+ IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 -+ >; -+ }; -+ -+ pinctrl_pciea: pcieagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 -+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 -+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 -+ >; -+ }; -+ -+ pinctrl_pcieb: pciebgrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 -+ IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 -+ IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lvds0_pwm0: lvds0pwm0grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_lvds1_pwm0: lvds1pwm0grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 -+ IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 -+ IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 -+ >; -+ }; -+ }; -+}; -+ -+&lsio_gpio2 { -+ status = "okay"; -+}; -+ -+&lsio_gpio5 { -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; -+ bus-width = <4>; -+ cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; -+ no-1-8-v; -+ status = "okay"; -+ -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-polarity-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbotg3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&i2c0_hdmi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+}; -+ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1>; -+ status = "okay"; -+ -+ pca9557_a: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@19 { -+ compatible = "nxp,pca9557"; -+ reg = <0x19>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_c: gpio@1b { -+ compatible = "nxp,pca9557"; -+ reg = <0x1b>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_d: gpio@1f { -+ compatible = "nxp,pca9557"; -+ reg = <0x1f>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ fxas2100x@20 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x20>; -+ }; -+ -+ fxos8700@1d { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1d>; -+ }; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio3>; -+ interrupts = <20 2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ }; -+}; -+ -+&i2c2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c2>; -+ status = "okay"; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&lpuart0 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "disabled"; -+}; -+ -+&lpuart3 { /* GPS */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "disabled"; -+}; -+ -+&isi_0 { -+ status = "okay"; -+}; -+ -+&isi_1 { -+ status = "okay"; -+}; -+ -+&isi_2 { -+ status = "okay"; -+}; -+ -+&isi_3 { -+ status = "okay"; -+}; -+ -+&gpu_3d0 { -+ status = "okay"; -+}; -+ -+&gpu_3d1 { -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ status = "okay"; -+}; -+ -+&pciea{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; -+ status = "disabled"; -+}; -+ -+&pcieb{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; -+ clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ status = "disabled"; -+}; -+ -+&cm41_intmux { -+ status = "okay"; -+}; -+ -+&ldb1_phy { -+ status = "okay"; -+}; -+ -+&ldb1 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ clock-lanes = <3>; -+ data-lanes = <0 1 2 4>; -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "okay"; -+}; -+ -+&ldb2 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_1_in: endpoint { -+ clock-lanes = <3>; -+ data-lanes = <0 1 2 4>; -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&vpu_decoder { -+ core_type = <2>; -+ status = "okay"; -+}; -+ -+&vpu_encoder { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi -new file mode 100644 -index 000000000..13692cf40 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi -@@ -0,0 +1,70 @@ -+/* -+ * Copyright 2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+/* fec1 cannot attach to ethphy0 since the PHY address -+ * conflict with ethphy2. So eth0 should not work. -+ * There still enable fec1 to share the MDIO bus for fec2 due -+ * to board limitation. -+ */ -+&fec1 { -+ /* PHY address should rework to 3 */ -+ phy-handle = <ðphy3>; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <2>; -+ tja110x,refclk_in; -+ /delete-property/ at803x,eee-disabled; -+ /delete-property/ at803x,vddio-1p8v; -+ }; -+ -+ ethphy3: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-0 = <&pinctrl_fec2_rmii>; -+ clocks = <&enet1_lpcg 4>, -+ <&enet1_lpcg 2>, -+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, -+ <&enet1_lpcg 0>, -+ <&enet1_lpcg 1>; -+ phy-mode = "rmii"; -+ phy-handle = <ðphy2>; -+ /delete-property/ phy-supply; -+}; -+ -+&iomuxc { -+ pinctrl_fec2_rmii: fec2rmiigrp { -+ fsl,pins = < -+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020 -+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 -+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 -+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020 -+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 -+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 -+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 -+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts -new file mode 100644 -index 000000000..53f8bad38 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qm-lpddr4-val.dts" -+ -+&thermal_zones { -+ /delete-node/ cpu-thermal1; -+ -+ pmic-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&cpus { -+ /delete-node/ cpu-map; -+ /delete-node/ cpu@100; -+ /delete-node/ cpu@101; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts -new file mode 100644 -index 000000000..e59fd9cdd ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qm-lpddr4-val.dts" -+ -+&thermal_zones { -+ /delete-node/ cpu-thermal0; -+ -+ pmic-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&cpus { -+ /delete-node/ cpu-map; -+ /delete-node/ cpu@0; -+ /delete-node/ cpu@1; -+ /delete-node/ cpu@2; -+ /delete-node/ cpu@3; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts -new file mode 100644 -index 000000000..b6e26ab23 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts -@@ -0,0 +1,101 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+/* -+ * DP only dts, disable ldb display. -+ */ -+#include "imx8qm-lpddr4-val.dts" -+ -+/ { -+ sound-hdmi { -+ compatible = "fsl,imx-audio-cdnhdmi"; -+ model = "imx-audio-dp"; -+ audio-cpu = <&sai5>; -+ hdmi-out; -+ }; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -+ -+&sai5_lpcg { -+ status = "okay"; -+}; -+ -+&ldb1_phy { -+ status = "disabled"; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -+ -+&i2c1_lvds0 { -+ status = "disabled"; -+}; -+ -+&irqsteer_hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_i2c0 { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_lis_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_pwm_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_i2s { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_gpio_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_msi_hclk { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_pxl { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_phy { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_apb_mux_csr { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_apb_mux_ctrl { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_apb { -+ status = "okay"; -+}; -+ -+&hdmi { -+ compatible = "cdn,imx8qm-dp"; -+ firmware-name = "dpfw.bin"; -+ lane-mapping = <0x1b>; -+ hdcp-config = <0x2>; -+ status = "okay"; -+}; -+ -+&spdif1 { -+ status = "okay"; -+}; -+ -+&spdif1_lpcg { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts -new file mode 100644 -index 000000000..9df779efd ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018~2019 NXP -+ */ -+ -+#include "imx8qm-lpddr4-val-lpspi.dts" -+ -+/delete-node/&spidev0; -+ -+&pinctrl_lpspi3 { -+ fsl,pins = < -+ IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x6000040 -+ IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x6000040 -+ IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x6000040 -+ IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x6000040 -+ >; -+}; -+ -+&lpspi3 { -+ #address-cells = <0>; -+ pinctrl-0 = <&pinctrl_lpspi3>; -+ /delete-property/ cs-gpios; -+ spi-slave; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts -new file mode 100644 -index 000000000..187040bc6 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2017~2019 NXP -+ */ -+ -+#include "imx8qm-lpddr4-val.dts" -+ -+&iomuxc { -+ pinctrl_lpspi0: lpspi0grp { -+ fsl,pins = < -+ IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x6000040 -+ IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x6000040 -+ IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x6000040 -+ >; -+ }; -+ -+ pinctrl_lpspi0_cs: lpspi0cs { -+ fsl,pins = < -+ IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x21 -+ >; -+ }; -+ -+ pinctrl_lpspi3: lpspi3grp { -+ fsl,pins = < -+ IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x6000040 -+ IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x6000040 -+ IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x6000040 -+ IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x6000040 -+ >; -+ }; -+}; -+ -+&lpspi0 { -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; -+ cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ flash: at45db041e@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "atmel,at45", "atmel,dataflash"; -+ spi-max-frequency = <5000000>; -+ reg = <0>; -+ }; -+}; -+ -+&lpspi3 { -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi3>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <30000000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts -new file mode 100644 -index 000000000..13f670f36 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts -@@ -0,0 +1,79 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qm-lpddr4-val.dts" -+ -+/ { -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif0>; -+ spdif-in; -+ spdif-out; -+ status = "disabled"; -+ }; -+ -+ sound-mqs { -+ compatible = "fsl,imx8qm-lpddr4-arm2-mqs", -+ "fsl,imx-audio-mqs"; -+ model = "mqs-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&mqs>; -+ audio-asrc = <&asrc1>; -+ }; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl_spdif0: spdif0grp { -+ fsl,pins = < -+ IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 -+ IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_mqs: mqsgrp { -+ fsl,pins = < -+ IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 -+ IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 -+ >; -+ }; -+}; -+ -+&mqs { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mqs>; -+ status = "okay"; -+}; -+ -+&spdif0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif0>; -+ status = "disabled"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts -new file mode 100644 -index 000000000..75e8fdf17 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts -@@ -0,0 +1,86 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qm-lpddr4-val.dts" -+ -+/ { -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif0>; -+ spdif-in; -+ spdif-out; -+ }; -+ -+ sound-mqs { -+ compatible = "fsl,imx8qm-lpddr4-arm2-mqs", -+ "fsl,imx-audio-mqs"; -+ model = "mqs-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&mqs>; -+ status = "disabled"; -+ }; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl_spdif0: spdif0grp { -+ fsl,pins = < -+ IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 -+ IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_mqs: mqsgrp { -+ fsl,pins = < -+ IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 -+ IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 -+ >; -+ }; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&mqs { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mqs>; -+ status = "disabled"; -+}; -+ -+&spdif0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts -new file mode 100755 -index 000000000..2cc404fce ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts -@@ -0,0 +1,644 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qm.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QM LPDDR4 Validation Board"; -+ compatible = "fsl,imx8qm-lpddr4-val", "fsl,imx8qm"; -+ -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ decoder_boot: decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ }; -+ -+ encoder_boot: encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ }; -+ -+ /* -+ * reserved-memory layout -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ -+ decoder_rpc: decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x200000>; -+ }; -+ -+ encoder_rpc: encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x200000>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_reserved: encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ -+ }; -+ -+ reg_can_en: regulator-can-en { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can_stby: regulator-can-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can_en>; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_audio: regulator@0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ audio-cpu = <&esai0>; -+ audio-codec = <&cs42888>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ }; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&asrc0 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&asrc1 { -+ fsl,asrc-rate = <48000>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>; -+ -+ status = "okay"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; -+ status = "okay"; -+}; -+ -+&dc0_pc { -+ status = "okay"; -+}; -+ -+&dc0_prg1 { -+ status = "okay"; -+}; -+ -+&dc0_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc0_prg3 { -+ status = "okay"; -+}; -+ -+&dc0_prg4 { -+ status = "okay"; -+}; -+ -+&dc0_prg5 { -+ status = "okay"; -+}; -+ -+&dc0_prg6 { -+ status = "okay"; -+}; -+ -+&dc0_prg7 { -+ status = "okay"; -+}; -+ -+&dc0_prg8 { -+ status = "okay"; -+}; -+ -+&dc0_prg9 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu1 { -+ status = "okay"; -+}; -+ -+&dc1_pc { -+ status = "okay"; -+}; -+ -+&dc1_prg1 { -+ status = "okay"; -+}; -+ -+&dc1_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc1_prg3 { -+ status = "okay"; -+}; -+ -+&dc1_prg4 { -+ status = "okay"; -+}; -+ -+&dc1_prg5 { -+ status = "okay"; -+}; -+ -+&dc1_prg6 { -+ status = "okay"; -+}; -+ -+&dc1_prg7 { -+ status = "okay"; -+}; -+ -+&dc1_prg8 { -+ status = "okay"; -+}; -+ -+&dc1_prg9 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu2 { -+ status = "okay"; -+}; -+ -+&sai6 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai6_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai7 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai7_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; -+ status = "okay"; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1>; -+ status = "okay"; -+ -+ pca9557_a: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@19 { -+ compatible = "nxp,pca9557"; -+ reg = <0x19>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_c: gpio@1b { -+ compatible = "nxp,pca9557"; -+ reg = <0x1b>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_d: gpio@1f { -+ compatible = "nxp,pca9557"; -+ reg = <0x1f>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 -+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan2grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 -+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 -+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_lpi2c0: lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c -+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpi2c1: lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c -+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 -+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 -+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts -new file mode 100644 -index 000000000..b37842fd4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qm-mek.dts" -+ -+&thermal_zones { -+ /delete-node/ cpu-thermal1; -+ -+ pmic-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&cpus { -+ /delete-node/ cpu-map; -+ /delete-node/ cpu@100; -+ /delete-node/ cpu@101; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts -new file mode 100644 -index 000000000..357a4ebc4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qm-mek.dts" -+ -+&thermal_zones { -+ /delete-node/ cpu-thermal0; -+ -+ pmic-thermal0 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&cpus { -+ /delete-node/ cpu-map; -+ /delete-node/ cpu@0; -+ /delete-node/ cpu@1; -+ /delete-node/ cpu@2; -+ /delete-node/ cpu@3; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts -new file mode 100644 -index 000000000..334d8b5a2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts -@@ -0,0 +1,1831 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qm-cockpit-ca53.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QM MEK"; -+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; -+ -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x40000000>; -+ }; -+ -+ brcmfmac: brcmfmac { -+ compatible = "cypress,brcmfmac"; -+ pinctrl-names = "init", "idle", "default"; -+ pinctrl-0 = <&pinctrl_wifi_init>; -+ pinctrl-1 = <&pinctrl_wifi_init>; -+ pinctrl-2 = <&pinctrl_wifi>; -+ }; -+ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds0 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ status = "disabled"; -+ }; -+ -+ lvds_backlight1: lvds_backlight@1 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds1 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_modem_reset>; -+ pinctrl-1 = <&pinctrl_modem_reset_sleep>; -+ reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ cbtl04gp { -+ compatible = "nxp,cbtl04gp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec_mux>; -+ switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; -+ reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ orientation-switch; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ decoder_boot: decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ }; -+ encoder_boot: encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ }; -+ /* -+ * reserved-memory layout -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ shmem_dma_reserved:shmem_dma@0x92000000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0x92000000 0 0x400000>; -+ }; -+ decoder_rpc: decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x0>; -+ }; -+ encoder_rpc: encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x0>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_reserved: encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x1e000000>; -+ alloc-ranges = <0 0xa2000000 0 0x1e000000>; -+ linux,cma-default; -+ }; -+ -+ a72_reserved { -+ no-map; -+ reg = <0 0xc0000000 0 0x40000000>; -+ }; -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_wlreg_on>; -+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&lsio_gpio1 13 0>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <4800>; -+ enable-active-high; -+ }; -+ -+ reg_can01_en: regulator-can01-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can01-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_can2_en: regulator-can2-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_can01_stby: regulator-can01-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can01-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can01_en>; -+ status = "disabled"; -+ }; -+ -+ reg_can2_stby: regulator-can2-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can2_en>; -+ status = "disabled"; -+ }; -+ -+ reg_vref_1v8: regulator-adc-vref { -+ compatible = "regulator-fixed"; -+ regulator-name = "vref_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ esai-controller = <&esai0>; -+ audio-codec = <&cs42888>; -+ asrc-controller = <&asrc0>; -+ status = "okay"; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ cpu-dai = <&sai1>; -+ audio-codec = <&wm8960>; -+ codec-master; -+ /* -+ * hp-det = ; -+ * hp-det-pin: JD1 JD2 or JD3 -+ * hp-det-polarity = 0: hp detect high for headphone -+ * hp-det-polarity = 1: hp detect high for speaker -+ */ -+ hp-det = <2 0>; -+ hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; -+ mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "Main MIC", -+ "RINPUT2", "Main MIC", -+ "Mic Jack", "MICB", -+ "Main MIC", "MICB", -+ "Playback", "CPU-Playback", -+ "CPU-Capture", "Capture"; -+ status = "disabled"; -+ }; -+}; -+ -+&adc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_adc0>; -+ vref-supply = <®_vref_1v8>; -+ status = "okay"; -+}; -+ -+&cm41_i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cm41_i2c>; -+ status = "disabled"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; -+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>; -+ power-domain-names = "pd_mclk_out_0", -+ "pd_audio_clk_0", -+ "pd_audio_clk_1", -+ "pd_audio_clk_0", -+ "pd_audio_clk_1"; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ status = "disabled"; -+ }; -+}; -+ -+&cm41_intmux { -+ status = "disabled"; -+}; -+ -+&dc0_pc { -+ status = "okay"; -+}; -+ -+&dc0_prg1 { -+ status = "okay"; -+}; -+ -+&dc0_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc0_prg3 { -+ status = "okay"; -+}; -+ -+&dc0_prg4 { -+ status = "okay"; -+}; -+ -+&dc0_prg5 { -+ status = "okay"; -+}; -+ -+&dc0_prg6 { -+ status = "okay"; -+}; -+ -+&dc0_prg7 { -+ status = "okay"; -+}; -+ -+&dc0_prg8 { -+ status = "okay"; -+}; -+ -+&dc0_prg9 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu1 { -+ status = "okay"; -+}; -+ -+&dsp { -+ compatible = "fsl,imx8qm-hifi4"; -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "disabled"; -+}; -+ -+&amix { -+ status = "disabled"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ status = "disabled"; -+}; -+ -+&sai6 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai6_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&sai7 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai7_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&pwm_lvds0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds0>; -+ status = "okay"; -+}; -+ -+&i2c1_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1_phy { -+ status = "okay"; -+}; -+ -+&ldb1 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ adv_bridge0: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_0_in: endpoint { -+ remote-endpoint = <&mipi0_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi0_adv_out: endpoint { -+ remote-endpoint = <&adv7535_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ adv_bridge1: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_1_in: endpoint { -+ remote-endpoint = <&mipi1_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "disabled"; -+}; -+ -+&mipi1_dsi_host { -+ status = "disabled"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi1_adv_out: endpoint { -+ remote-endpoint = <&adv7535_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dc1_pc { -+ status = "disabled"; -+}; -+ -+&dc1_prg1 { -+ status = "disabled"; -+}; -+ -+&dc1_prg2 { -+ status = "disabled"; -+ -+}; -+ -+&dc1_prg3 { -+ status = "disabled"; -+}; -+ -+&dc1_prg4 { -+ status = "disabled"; -+}; -+ -+&dc1_prg5 { -+ status = "disabled"; -+}; -+ -+&dc1_prg6 { -+ status = "disabled"; -+}; -+ -+&dc1_prg7 { -+ status = "disabled"; -+}; -+ -+&dc1_prg8 { -+ status = "disabled"; -+}; -+ -+&dc1_prg9 { -+ status = "disabled"; -+}; -+ -+&dc1_dpr1_channel1 { -+ status = "disabled"; -+}; -+ -+&dc1_dpr1_channel2 { -+ status = "disabled"; -+}; -+ -+&dc1_dpr1_channel3 { -+ status = "disabled"; -+}; -+ -+&dc1_dpr2_channel1 { -+ status = "disabled"; -+}; -+ -+&dc1_dpr2_channel2 { -+ status = "disabled"; -+}; -+ -+&dc1_dpr2_channel3 { -+ status = "disabled"; -+}; -+ -+&dpu2 { -+ status = "disabled"; -+}; -+ -+&pwm_lvds1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds1>; -+ status = "disabled"; -+}; -+ -+&i2c1_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_1_in: endpoint { -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "disabled"; -+}; -+ -+&ldb2 { -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "disabled"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&lpspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; -+ cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <30000000>; -+ }; -+}; -+ -+&emvsim0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sim0>; -+ status = "okay"; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "disabled"; -+}; -+ -+&lpuart2 { /* Dbg console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ status = "disabled"; -+}; -+ -+&lpuart3 { /* MKbus */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can01_stby>; -+ status = "disabled"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can01_stby>; -+ status = "disabled"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can2_stby>; -+ status = "disabled"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ /delete-property/ iommus; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac1>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&pciea{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ epdev_on-supply = <&epdev_on>; -+ status = "disabled"; -+}; -+ -+&imx_shmem_net { -+ memory-region = <&shmem_dma_reserved>; -+ status = "okay"; -+}; -+ -+&sata { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "disabled"; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&usbotg3 { -+ dr_mode = "otg"; -+ extcon = <&ptn5110>; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; -+ /delete-property/ iommus; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0>; -+ status = "okay"; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <11 2>; -+ }; -+ -+ fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ interrupt-open-drain; -+ }; -+ -+ fxas2100x@20 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x20>; -+ interrupt-open-drain; -+ }; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ interrupt-open-drain; -+ }; -+ -+ ptn5110: tcpc@51 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x51>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ usb_con1: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "source"; -+ data-role = "dual"; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ pinctrl-1 = <&pinctrl_i2c1_gpio>; -+ scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; -+ sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; -+ status = "disabled"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+}; -+ -+&isi_0 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_2 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_3 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_4 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_5 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_6 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_7 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer_csi0 { -+ status = "okay"; -+}; -+ -+&irqsteer_csi1 { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 1 MIPI CSI-2 (CSIS1) */ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&max9286_1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&jpegdec { -+ status = "okay"; -+}; -+ -+&jpegenc { -+ status = "okay"; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "disabled"; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi1>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "disabled"; -+ port { -+ max9286_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+ -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c -+ >; -+ }; -+ -+ pinctrl_cm41_i2c: cm41i2cgrp { -+ fsl,pins = < -+ IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c -+ IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c -+ >; -+ }; -+ -+ pinctrl_adc0: adc0grp { -+ fsl,pins = < -+ IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 -+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 -+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 -+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 -+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c0: i2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 -+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c -+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c -+ >; -+ }; -+ -+ pinctrl_i2c1_gpio: i2c1grp-gpio { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c -+ IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpspi2: lpspi2grp { -+ fsl,pins = < -+ IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c -+ IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c -+ IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c -+ IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c -+ >; -+ }; -+ -+ pinctrl_lpspi2_cs: lpspi2cs { -+ fsl,pins = < -+ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 -+ >; -+ }; -+ -+ pinctrl_sim0: sim0grp { -+ fsl,pins = < -+ IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 -+ IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 -+ IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 -+ IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 -+ IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 -+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 -+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 -+ IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 -+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_pwm_lvds0: pwmlvds0grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_pwm_lvds1: pwmlvds1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_modem_reset: modemresetgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 -+ >; -+ }; -+ -+ pinctrl_modem_reset_sleep: modemreset_sleepgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 -+ >; -+ }; -+ -+ pinctrl_pciea: pcieagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 -+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 -+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 -+ IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 -+ >; -+ }; -+ -+ pinctrl_pcieb: pciebgrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 -+ IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000040 -+ IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040 -+ IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 -+ IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 -+ >; -+ }; -+ -+ pinctrl_typec: typecgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 -+ >; -+ }; -+ -+ pinctrl_typec_mux: typecmuxgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 -+ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 -+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 -+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0: mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 -+ IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 -+ IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_mipi_csi1: mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 -+ IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 -+ IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_wifi: wifigrp{ -+ fsl,pins = < -+ IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 -+ >; -+ }; -+ -+ pinctrl_wifi_init: wifi_initgrp{ -+ fsl,pins = < -+ /* reserve pin init/idle_state to support multiple wlan cards */ -+ >; -+ }; -+ -+ pinctrl_wlreg_on: wlregongrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 -+ >; -+ }; -+ -+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 -+ >; -+ }; -+ -+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 -+ >; -+ }; -+ -+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 -+ >; -+ }; -+ -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&gpu_3d0{ -+ status = "okay"; -+}; -+ -+&gpu_3d1{ -+ status = "disabled"; -+}; -+ -+&imx8_gpu_ss { -+ cores = <&gpu_3d0>; -+ status = "okay"; -+}; -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&dpu1_disp0>, <&dpu1_disp1>; -+ }; -+}; -+ -+&mu_m0{ -+ interrupts = ; -+}; -+ -+&mu1_m0{ -+ interrupts = ; -+}; -+ -+&mu2_m0{ -+ interrupts = ; -+ status = "okay"; -+}; -+ -+&vpu_decoder { -+ compatible = "nxp,imx8qm-b0-vpudec"; -+ boot-region = <&decoder_boot>; -+ rpc-region = <&decoder_rpc>; -+ reg-csr = <0x2d080000>; -+ core_type = <2>; -+ status = "okay"; -+}; -+ -+&vpu_encoder { -+ compatible = "nxp,imx8qm-b0-vpuenc"; -+ boot-region = <&encoder_boot>; -+ rpc-region = <&encoder_rpc>; -+ reserved-region = <&encoder_reserved>; -+ reg-rpc-system = <0x40000000>; -+ resolution-max = <1920 1080>; -+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, -+ <&pd IMX_SC_R_VPU>; -+ power-domain-names = "vpuenc1", "vpuenc2", "vpu"; -+ mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", -+ "enc2_tx0", "enc2_tx1", "enc2_rx"; -+ mboxes = <&mu1_m0 0 0 -+ &mu1_m0 0 1 -+ &mu1_m0 1 0 -+ &mu2_m0 0 0 -+ &mu2_m0 0 1 -+ &mu2_m0 1 0>; -+ status = "okay"; -+ -+ core0@1020000 { -+ compatible = "fsl,imx8-mu1-vpu-m0"; -+ reg = <0x1020000 0x20000>; -+ reg-csr = <0x1090000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <17>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+ -+ core1@1040000 { -+ compatible = "fsl,imx8-mu2-vpu-m0"; -+ reg = <0x1040000 0x20000>; -+ reg-csr = <0x10A0000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <18>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+}; -+ -+&lsio_gpio0 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio1 { -+ status = "okay"; -+}; -+ -+&lsio_gpio2 { -+ status = "okay"; -+}; -+ -+&lsio_gpio3 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio4 { -+ status = "okay"; -+}; -+ -+&lsio_gpio5 { -+ status = "okay"; -+}; -+ -+&lsio_gpio6 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio7 { -+ status = "disabled"; -+}; -+ -+&lsio_mu8 { -+ status = "okay"; -+}; -+ -+&rtc { -+ read-only; -+}; -+ -+&crypto { -+ /delete-property/ interrupts; -+ power-domains = <&pd IMX_SC_R_CAAM_JR2>; -+ /delete-node/ sec_jr3; -+}; -+ -+/delete-node/ &asrc1; -+/delete-node/ &ddr_pmu0; -+/delete-node/ &ddr_pmu1; -+/delete-node/ &dpu2; -+/delete-node/ &dsp; -+/delete-node/ &esai1; -+/delete-node/ &fec2; -+/delete-node/ &gpio0_mipi_csi0; -+/delete-node/ &gpio0_mipi_csi1; -+/delete-node/ &i2c_mipi_csi0; -+/delete-node/ &i2c_mipi_csi1; -+/delete-node/ &i2c1_lvds1; -+/delete-node/ &irqsteer_csi0; -+/delete-node/ &irqsteer_csi1; -+/delete-node/ &isi_0; -+/delete-node/ &isi_1; -+/delete-node/ &isi_2; -+/delete-node/ &isi_3; -+/delete-node/ &isi_4; -+/delete-node/ &isi_5; -+/delete-node/ &isi_6; -+/delete-node/ &isi_7; -+/delete-node/ &jpegdec; -+/delete-node/ &jpegenc; -+/delete-node/ &ldb2; -+/delete-node/ &ldb2_phy; -+/delete-node/ &lpuart1; -+/delete-node/ &lpuart2; -+/delete-node/ &lvds1_region; -+/delete-node/ &mipi_csi_0; -+/delete-node/ &mipi_csi_1; -+/delete-node/ &mqs; -+/delete-node/ &sai0; -+/delete-node/ &sai2; -+/delete-node/ &sai3; -+/delete-node/ &spdif0; -+/delete-node/ &usbotg1; -+/delete-node/ &usbphy1; -+/delete-node/ &usdhc1; -+/delete-node/ &usbmisc1; -+/delete-node/ &mipi1_dsi_host; -+/delete-node/ &i2c0_mipi1; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts -new file mode 100644 -index 000000000..49ab2c2f9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts -@@ -0,0 +1,1896 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qm-cockpit-ca72.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QM MEK"; -+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; -+ -+ chosen { -+ stdout-path = &lpuart2; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x40000000>; -+ }; -+ -+ brcmfmac: brcmfmac { -+ compatible = "cypress,brcmfmac"; -+ pinctrl-names = "init", "idle", "default"; -+ pinctrl-0 = <&pinctrl_wifi_init>; -+ pinctrl-1 = <&pinctrl_wifi_init>; -+ pinctrl-2 = <&pinctrl_wifi>; -+ }; -+ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds0 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ status = "disabled"; -+ }; -+ -+ lvds_backlight1: lvds_backlight@1 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds1 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_modem_reset>; -+ pinctrl-1 = <&pinctrl_modem_reset_sleep>; -+ reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ cbtl04gp { -+ compatible = "nxp,cbtl04gp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec_mux>; -+ switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; -+ reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ orientation-switch; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ decoder_boot: decoder_boot@0xc4000000 { -+ no-map; -+ reg = <0 0xc4000000 0 0x2000000>; -+ }; -+ encoder_boot: encoder_boot@0xc6000000 { -+ no-map; -+ reg = <0 0xc6000000 0 0x400000>; -+ }; -+ /* -+ * reserved-memory layout -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ shmem_dma_reserved:shmem_dma@0x92000000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0x92000000 0 0x400000>; -+ }; -+ decoder_rpc: decoder_rpc@0xd2000000 { -+ no-map; -+ reg = <0 0xd2000000 0 0x200000>; -+ }; -+ encoder_rpc: encoder_rpc@0xd2200000 { -+ no-map; -+ reg = <0 0xd2200000 0 0x200000>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_reserved: encoder_reserved@0xd4400000 { -+ no-map; -+ reg = <0 0xd4400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x1e000000>; -+ alloc-ranges = <0 0xe2000000 0 0x1e000000>; -+ linux,cma-default; -+ }; -+ -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_wlreg_on>; -+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&lsio_gpio1 13 0>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <4800>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_can01_en: regulator-can01-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can01-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_can2_en: regulator-can2-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ reg_can01_stby: regulator-can01-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can01-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can01_en>; -+ status = "disabled"; -+ }; -+ -+ reg_can2_stby: regulator-can2-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can2_en>; -+ status = "disabled"; -+ }; -+ -+ reg_vref_1v8: regulator-adc-vref { -+ compatible = "regulator-fixed"; -+ regulator-name = "vref_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ esai-controller = <&esai0>; -+ audio-codec = <&cs42888>; -+ asrc-controller = <&asrc0>; -+ status = "okay"; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx7d-evk-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ cpu-dai = <&sai1>; -+ audio-codec = <&wm8960>; -+ codec-master; -+ /* -+ * hp-det = ; -+ * hp-det-pin: JD1 JD2 or JD3 -+ * hp-det-polarity = 0: hp detect high for headphone -+ * hp-det-polarity = 1: hp detect high for speaker -+ */ -+ hp-det = <2 0>; -+ hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; -+ mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "Main MIC", -+ "RINPUT2", "Main MIC", -+ "Mic Jack", "MICB", -+ "Main MIC", "MICB", -+ "Playback", "CPU-Playback", -+ "CPU-Capture", "Capture"; -+ }; -+}; -+ -+&adc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_adc0>; -+ vref-supply = <®_vref_1v8>; -+ status = "okay"; -+}; -+ -+&cm41_i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cm41_i2c>; -+ status = "disabled"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; -+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>; -+ power-domain-names = "pd_mclk_out_0", -+ "pd_audio_clk_0", -+ "pd_audio_clk_1", -+ "pd_audio_clk_0", -+ "pd_audio_clk_1"; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ status = "disabled"; -+ }; -+}; -+ -+&cm41_intmux { -+ status = "disabled"; -+}; -+ -+&dc0_pc { -+ status = "disabled"; -+}; -+ -+&dc0_prg1 { -+ status = "disabled"; -+}; -+ -+&dc0_prg2 { -+ status = "disabled"; -+ -+}; -+ -+&dc0_prg3 { -+ status = "disabled"; -+}; -+ -+&dc0_prg4 { -+ status = "disabled"; -+}; -+ -+&dc0_prg5 { -+ status = "disabled"; -+}; -+ -+&dc0_prg6 { -+ status = "disabled"; -+}; -+ -+&dc0_prg7 { -+ status = "disabled"; -+}; -+ -+&dc0_prg8 { -+ status = "disabled"; -+}; -+ -+&dc0_prg9 { -+ status = "disabled"; -+}; -+ -+&dc0_dpr1_channel1 { -+ status = "disabled"; -+}; -+ -+&dc0_dpr1_channel2 { -+ status = "disabled"; -+}; -+ -+&dc0_dpr1_channel3 { -+ status = "disabled"; -+}; -+ -+&dc0_dpr2_channel1 { -+ status = "disabled"; -+}; -+ -+&dc0_dpr2_channel2 { -+ status = "disabled"; -+}; -+ -+&dc0_dpr2_channel3 { -+ status = "disabled"; -+}; -+ -+&dpu1 { -+ status = "disabled"; -+}; -+ -+&dsp { -+ compatible = "fsl,imx8qm-hifi4"; -+ status = "disabled"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+ /delete-property/ dmas; -+}; -+ -+&asrc1 { -+ /delete-property/ dmas; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ fsl,txm-rxs; -+ status = "okay"; -+ /delete-property/ dmas; -+}; -+ -+&esai1 { -+ /delete-property/ dmas; -+}; -+ -+&sai0 { -+ /delete-property/ dmas; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ status = "okay"; -+}; -+ -+&sai2 { -+ /delete-property/ dmas; -+}; -+ -+&sai3 { -+ /delete-property/ dmas; -+}; -+ -+&sai4 { -+ /delete-property/ dmas; -+}; -+ -+&sai5 { -+ /delete-property/ dmas; -+}; -+ -+&sai6 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai6_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+ /delete-property/ dmas; -+}; -+ -+&sai7 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai7_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+ /delete-property/ dmas; -+}; -+ -+&spdif0 { -+ /delete-property/ dmas; -+}; -+ -+&spdif1 { -+ /delete-property/ dmas; -+}; -+ -+ -+ -+&pwm_lvds0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds0>; -+ status = "disabled"; -+}; -+ -+&i2c1_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1_phy { -+ status = "disabled"; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "disabled"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ adv_bridge0: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_0_in: endpoint { -+ remote-endpoint = <&mipi0_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi0_dphy { -+ status = "disabled"; -+}; -+ -+&mipi0_dsi_host { -+ status = "disabled"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi0_adv_out: endpoint { -+ remote-endpoint = <&adv7535_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ adv_bridge1: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+// interrupt-parent = <&lsio_gpio1>; -+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_1_in: endpoint { -+ remote-endpoint = <&mipi1_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi1_adv_out: endpoint { -+ remote-endpoint = <&adv7535_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dc1_pc { -+ status = "okay"; -+}; -+ -+&dc1_prg1 { -+ status = "okay"; -+}; -+ -+&dc1_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc1_prg3 { -+ status = "okay"; -+}; -+ -+&dc1_prg4 { -+ status = "okay"; -+}; -+ -+&dc1_prg5 { -+ status = "okay"; -+}; -+ -+&dc1_prg6 { -+ status = "okay"; -+}; -+ -+&dc1_prg7 { -+ status = "okay"; -+}; -+ -+&dc1_prg8 { -+ status = "okay"; -+}; -+ -+&dc1_prg9 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu2 { -+ status = "okay"; -+}; -+ -+&pwm_lvds1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds1>; -+ status = "okay"; -+}; -+ -+&i2c1_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_1_in: endpoint { -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "okay"; -+}; -+ -+&ldb2 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&lpspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; -+ cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; -+ status = "disabled"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <30000000>; -+ }; -+}; -+ -+&emvsim0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sim0>; -+ status = "disabled"; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "disabled"; -+}; -+ -+&lpuart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "disabled"; -+}; -+ -+&lpuart2 { /* Dbg console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ /delete-property/ dmas; -+ status = "okay"; -+}; -+ -+&lpuart3 { /* MKbus */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can01_stby>; -+ status = "disabled"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can01_stby>; -+ status = "disabled"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can2_stby>; -+ status = "disabled"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ /delete-property/ iommus; -+ status = "disabled"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac1>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ /delete-property/ iommus; -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "disabled"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&pciea{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ epdev_on-supply = <&epdev_on>; -+ status = "disabled"; -+}; -+ -+&lsio_mu1 { -+ status = "disabled"; -+}; -+ -+&lsio_mu2 { -+ status = "okay"; -+}; -+ -+&lsio_mu5 { -+ status = "disabled"; -+}; -+ -+&lsio_mu6 { -+ status = "disabled"; -+}; -+ -+&lsio_mu8b { -+ status = "okay"; -+}; -+ -+&imx_shmem_net { -+ memory-region = <&shmem_dma_reserved>; -+ rxfirst; -+ status = "okay"; -+}; -+ -+&sata { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usb3_phy { -+ status = "disabled"; -+}; -+ -+&usbotg3 { -+ dr_mode = "otg"; -+ extcon = <&ptn5110>; -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <400000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ /delete-property/ iommus; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; -+ /delete-property/ iommus; -+ status = "disabled";}; -+ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0>; -+ status = "disabled"; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <11 2>; -+ }; -+ -+ fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ interrupt-open-drain; -+ }; -+ -+ fxas2100x@20 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x20>; -+ interrupt-open-drain; -+ }; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ interrupt-open-drain; -+ }; -+ -+ ptn5110: tcpc@51 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x51>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; -+ status = "disabled"; -+ -+ usb_con1: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "source"; -+ data-role = "dual"; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ pinctrl-1 = <&pinctrl_i2c1_gpio>; -+ scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; -+ sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_2 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_3 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_4 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_5 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_6 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_7 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer_csi0 { -+ status = "disabled"; -+}; -+ -+&irqsteer_csi1 { -+ status = "disabled"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "disabled"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "disabled"; -+ -+ /* Camera 1 MIPI CSI-2 (CSIS1) */ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&max9286_1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&jpegdec { -+ status = "okay"; -+}; -+ -+&jpegenc { -+ status = "okay"; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "disabled"; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; -+ clock-frequency = <100000>; -+ status = "disabled"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi1>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "disabled"; -+ port { -+ max9286_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+ -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c -+ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c -+ >; -+ }; -+ -+ pinctrl_cm41_i2c: cm41i2cgrp { -+ fsl,pins = < -+ IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c -+ IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c -+ >; -+ }; -+ -+ pinctrl_adc0: adc0grp { -+ fsl,pins = < -+ IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 -+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 -+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 -+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 -+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c0: i2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 -+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c -+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c -+ >; -+ }; -+ -+ pinctrl_i2c1_gpio: i2c1grp-gpio { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c -+ IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpspi2: lpspi2grp { -+ fsl,pins = < -+ IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c -+ IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c -+ IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c -+ IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c -+ >; -+ }; -+ -+ pinctrl_lpspi2_cs: lpspi2cs { -+ fsl,pins = < -+ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 -+ >; -+ }; -+ -+ pinctrl_sim0: sim0grp { -+ fsl,pins = < -+ IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 -+ IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 -+ IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 -+ IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 -+ IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 -+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 -+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 -+ IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 -+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_pwm_lvds0: pwmlvds0grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_pwm_lvds1: pwmlvds1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_modem_reset: modemresetgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 -+ >; -+ }; -+ -+ pinctrl_modem_reset_sleep: modemreset_sleepgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 -+ >; -+ }; -+ -+ pinctrl_pciea: pcieagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 -+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 -+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 -+ IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 -+ >; -+ }; -+ -+ pinctrl_pcieb: pciebgrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 -+ IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000040 -+ IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040 -+ IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 -+ IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 -+ >; -+ }; -+ -+ pinctrl_typec: typecgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 -+ >; -+ }; -+ -+ pinctrl_typec_mux: typecmuxgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 -+ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 -+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 -+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0: mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 -+ IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 -+ IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_mipi_csi1: mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 -+ IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 -+ IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_wifi: wifigrp{ -+ fsl,pins = < -+ IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 -+ >; -+ }; -+ -+ pinctrl_wifi_init: wifi_initgrp{ -+ fsl,pins = < -+ /* reserve pin init/idle_state to support multiple wlan cards */ -+ >; -+ }; -+ -+ pinctrl_wlreg_on: wlregongrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 -+ >; -+ }; -+ -+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 -+ >; -+ }; -+ -+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 -+ >; -+ }; -+ -+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 -+ >; -+ }; -+ -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&gpu_3d0{ -+ status = "disabled"; -+}; -+ -+&gpu_3d1{ -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ cores = <&gpu_3d1>; -+ status = "okay"; -+}; -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&dpu2_disp0>, <&dpu2_disp1>; -+ }; -+}; -+ -+&mu_m0{ -+ interrupts = ; -+}; -+ -+&mu1_m0{ -+ interrupts = ; -+}; -+ -+&mu2_m0{ -+ interrupts = ; -+ status = "okay"; -+}; -+ -+&vpu_decoder { -+ compatible = "nxp,imx8qm-b0-vpudec"; -+ boot-region = <&decoder_boot>; -+ rpc-region = <&decoder_rpc>; -+ reg-csr = <0x2d080000>; -+ core_type = <2>; -+ status = "okay"; -+}; -+ -+&vpu_encoder { -+ compatible = "nxp,imx8qm-b0-vpuenc"; -+ boot-region = <&encoder_boot>; -+ rpc-region = <&encoder_rpc>; -+ reserved-region = <&encoder_reserved>; -+ reg-rpc-system = <0x40000000>; -+ resolution-max = <1920 1080>; -+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, -+ <&pd IMX_SC_R_VPU>; -+ power-domain-names = "vpuenc1", "vpuenc2", "vpu"; -+ mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", -+ "enc2_tx0", "enc2_tx1", "enc2_rx"; -+ mboxes = <&mu1_m0 0 0 -+ &mu1_m0 0 1 -+ &mu1_m0 1 0 -+ &mu2_m0 0 0 -+ &mu2_m0 0 1 -+ &mu2_m0 1 0>; -+ status = "okay"; -+ -+ core0@1020000 { -+ compatible = "fsl,imx8-mu1-vpu-m0"; -+ reg = <0x1020000 0x20000>; -+ reg-csr = <0x1090000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <17>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+ -+ core1@1040000 { -+ compatible = "fsl,imx8-mu2-vpu-m0"; -+ reg = <0x1040000 0x20000>; -+ reg-csr = <0x10A0000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <18>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+}; -+ -+&lsio_gpio0 { -+ status = "okay"; -+}; -+ -+&lsio_gpio1 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio2 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio3 { -+ status = "okay"; -+}; -+ -+&lsio_gpio4 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio5 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio6 { -+ status = "okay"; -+}; -+ -+&lsio_gpio7 { -+ status = "okay"; -+}; -+ -+&crypto { -+ power-domains = <&pd IMX_SC_R_CAAM_JR3>; -+}; -+ -+&sec_jr2 { -+ status = "disabled"; -+}; -+ -+&edma0{ -+ reg = <0x591f0000 0x10000>, -+ <0x592e0000 0x10000>, /* sai1 rx */ -+ <0x592f0000 0x10000>; /* sai1 tx */ -+ dma-channels = <2>; -+ interrupts = , /* sai1 */ -+ ; -+ interrupt-names = "edma2-chan14-rx", "edma2-chan15-tx"; /* sai1 */ -+ power-domains = <&pd IMX_SC_R_DMA_2_CH14>, -+ <&pd IMX_SC_R_DMA_2_CH15>; -+ power-domain-names = "edma2-chan14", "edma2-chan15"; -+ status = "okay"; -+}; -+ -+&edma2 { -+ reg = <0x5a1f0000 0x10000>, -+ <0x5a300000 0x10000>, /* channel16 UART2 rx */ -+ <0x5a310000 0x10000>; /* channel17 UART2 tx */ -+ #dma-cells = <3>; -+ dma-channels = <2>; -+ interrupts = , -+ ; -+ interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx"; -+ power-domains = <&pd IMX_SC_R_DMA_0_CH16>, -+ <&pd IMX_SC_R_DMA_0_CH17>; -+ power-domain-names = "edma0-chan16", "edma0-chan17"; -+ status = "okay"; -+}; -+ -+&crypto { -+ /delete-property/ interrupts; -+ power-domains = <&pd IMX_SC_R_CAAM_JR3>; -+ /delete-node/ sec_jr2; -+}; -+ -+/delete-node/ &edma1; -+ -+/delete-node/ &gpu_3d0; -+ -+/delete-node/ &ddr_pmu0; -+/delete-node/ &ddr_pmu1; -+/delete-node/ &dpu1; -+/delete-node/ &hdmi; -+/delete-node/ &dsp; -+/delete-node/ &i2c1_lvds0; -+/delete-node/ &ldb1; -+/delete-node/ &ldb1_phy; -+/delete-node/ &lpuart0; -+/delete-node/ &lpuart1; -+/delete-node/ &lpuart3; -+/delete-node/ &lvds0_region; -+/delete-node/ &mipi0_dsi_host; -+/delete-node/ &i2c0_mipi0; -+/delete-node/ &mqs; -+/delete-node/ &usdhc2; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts -new file mode 100644 -index 000000000..0e4e12276 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts -@@ -0,0 +1,791 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8qm-mek.dts" -+#include "imx8qm-xen.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QM MEK"; -+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; -+ -+ chosen { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ stdout-path = &lpuart0; -+ -+ /* Could be updated by U-Boot */ -+ module@0 { -+ bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; -+ compatible = "xen,linux-zimage", "xen,multiboot-module"; -+ reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; -+ }; -+ }; -+ -+ domu { -+ /* -+ * There are 5 MUs, 0A is used by Dom0, 1A is used -+ * by ATF, so for DomU, 2A/3A/4A could be used. -+ * SC_R_MU_0A -+ * SC_R_MU_1A -+ * SC_R_MU_2A -+ * SC_R_MU_3A -+ * SC_R_MU_4A -+ * The rsrcs and pads will be configured by uboot scu_rm cmd -+ */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ doma { -+ compatible = "xen,domu"; -+ /* -+ * The name entry in VM configuration file -+ * needs to be same as here. -+ */ -+ domain_name = "DomU"; -+ /* -+ * The reg property will be updated by U-Boot to -+ * reflect the partition id. -+ */ -+ reg = <0>; -+ init_on_rsrcs = < -+ IMX_SC_R_MU_2A -+ >; -+ rsrcs = < -+ IMX_SC_R_MU_2A -+ IMX_SC_R_GPU_0_PID0 -+ IMX_SC_R_GPU_0_PID1 -+ IMX_SC_R_GPU_0_PID2 -+ IMX_SC_R_GPU_0_PID3 -+ IMX_SC_R_LVDS_0 -+ IMX_SC_R_LVDS_0_I2C_0 -+ IMX_SC_R_LVDS_0_PWM_0 -+ IMX_SC_R_DC_0 -+ IMX_SC_R_DC_0_BLIT0 -+ IMX_SC_R_DC_0_BLIT1 -+ IMX_SC_R_DC_0_BLIT2 -+ IMX_SC_R_DC_0_BLIT_OUT -+ IMX_SC_R_DC_0_WARP -+ IMX_SC_R_DC_0_VIDEO0 -+ IMX_SC_R_DC_0_VIDEO1 -+ IMX_SC_R_DC_0_FRAC0 -+ IMX_SC_R_DC_0_PLL_0 -+ IMX_SC_R_DC_0_PLL_1 -+ IMX_SC_R_SDHC_0 -+ /*vpu*/ -+ IMX_SC_R_VPU_PID0 -+ IMX_SC_R_VPU_PID1 -+ IMX_SC_R_VPU_PID2 -+ IMX_SC_R_VPU_PID3 -+ IMX_SC_R_VPU_PID4 -+ IMX_SC_R_VPU_PID5 -+ IMX_SC_R_VPU_PID6 -+ IMX_SC_R_VPU_PID7 -+ IMX_SC_R_VPU -+ IMX_SC_R_VPU_DEC_0 -+ IMX_SC_R_VPU_ENC_0 -+ IMX_SC_R_VPU_ENC_1 -+ IMX_SC_R_VPU_TS_0 -+ IMX_SC_R_VPU_MU_0 -+ IMX_SC_R_VPU_MU_1 -+ IMX_SC_R_VPU_MU_2 -+ IMX_SC_R_VPU_MU_3 -+ IMX_SC_R_MU_13A -+ IMX_SC_R_MU_13B -+ IMX_SC_R_DSP -+ IMX_SC_R_DSP_RAM -+ /* usbotg1 */ -+ IMX_SC_R_USB_0 -+ IMX_SC_R_USB_0_PHY -+ /* usbotg3 */ -+ IMX_SC_R_USB_2 -+ IMX_SC_R_USB_2_PHY -+ -+ /* ASRC0 */ -+ IMX_SC_R_DMA_2_CH0 -+ IMX_SC_R_DMA_2_CH1 -+ IMX_SC_R_DMA_2_CH2 -+ IMX_SC_R_DMA_2_CH3 -+ IMX_SC_R_DMA_2_CH4 -+ IMX_SC_R_DMA_2_CH5 -+ IMX_SC_R_DMA_2_CH6 -+ IMX_SC_R_DMA_2_CH7 -+ IMX_SC_R_DMA_2_CH8 -+ IMX_SC_R_DMA_2_CH9 -+ IMX_SC_R_DMA_2_CH10 -+ IMX_SC_R_DMA_2_CH11 -+ IMX_SC_R_DMA_2_CH12 -+ IMX_SC_R_DMA_2_CH13 -+ IMX_SC_R_DMA_2_CH14 -+ IMX_SC_R_DMA_2_CH15 -+ IMX_SC_R_DMA_2_CH16 -+ IMX_SC_R_DMA_2_CH17 -+ IMX_SC_R_DMA_2_CH18 -+ IMX_SC_R_DMA_2_CH19 -+ IMX_SC_R_DMA_2_CH20 -+ IMX_SC_R_AUDIO_CLK_0 -+ IMX_SC_R_AUDIO_CLK_1 -+ IMX_SC_R_MCLK_OUT_0 -+ IMX_SC_R_MCLK_OUT_1 -+ IMX_SC_R_AUDIO_PLL_0 -+ IMX_SC_R_AUDIO_PLL_1 -+ IMX_SC_R_ASRC_0 -+ IMX_SC_R_ASRC_1 -+ IMX_SC_R_ESAI_0 -+ IMX_SC_R_ESAI_1 -+ IMX_SC_R_SAI_0 -+ IMX_SC_R_SAI_1 -+ IMX_SC_R_SAI_2 -+ IMX_SC_R_SAI_3 -+ IMX_SC_R_SAI_4 -+ IMX_SC_R_SAI_5 -+ IMX_SC_R_SAI_6 -+ IMX_SC_R_SAI_7 -+ IMX_SC_R_SPDIF_0 -+ IMX_SC_R_SPDIF_1 -+ IMX_SC_R_MQS_0 -+ IMX_SC_R_DMA_3_CH0 -+ IMX_SC_R_DMA_3_CH1 -+ IMX_SC_R_DMA_3_CH2 -+ IMX_SC_R_DMA_3_CH3 -+ IMX_SC_R_DMA_3_CH4 -+ IMX_SC_R_DMA_3_CH5 -+ IMX_SC_R_DMA_3_CH6 -+ IMX_SC_R_DMA_3_CH7 -+ IMX_SC_R_DMA_3_CH8 -+ IMX_SC_R_DMA_3_CH9 -+ IMX_SC_R_DMA_3_CH10 -+ -+ IMX_SC_R_SATA_0 -+ IMX_SC_R_PCIE_A -+ IMX_SC_R_PCIE_B -+ IMX_SC_R_SERDES_0 -+ IMX_SC_R_SERDES_1 -+ IMX_SC_R_HSIO_GPIO -+ -+ IMX_SC_R_DMA_0_CH14 -+ IMX_SC_R_DMA_0_CH15 -+ IMX_SC_R_UART_1 -+ -+ IMX_SC_R_MIPI_0 -+ IMX_SC_R_MIPI_0_I2C_0 -+ IMX_SC_R_MIPI_0_I2C_1 -+ IMX_SC_R_MIPI_1 -+ IMX_SC_R_MIPI_1_I2C_0 -+ IMX_SC_R_MIPI_1_I2C_1 -+ -+ IMX_SC_R_HDMI_PLL_0 -+ IMX_SC_R_HDMI_PLL_1 -+ IMX_SC_R_HDMI -+ IMX_SC_R_HDMI_I2C_0 -+ IMX_SC_R_HDMI_I2S -+ -+ IMX_SC_R_CSI_0 -+ IMX_SC_R_CSI_0_I2C_0 -+ IMX_SC_R_CSI_1 -+ IMX_SC_R_CSI_1_I2C_0 -+ IMX_SC_R_ISI_CH0 -+ IMX_SC_R_ISI_CH1 -+ IMX_SC_R_ISI_CH2 -+ IMX_SC_R_ISI_CH3 -+ IMX_SC_R_ISI_CH4 -+ IMX_SC_R_ISI_CH5 -+ IMX_SC_R_ISI_CH6 -+ IMX_SC_R_ISI_CH7 -+ IMX_SC_R_MJPEG_DEC_MP -+ IMX_SC_R_MJPEG_DEC_S0 -+ IMX_SC_R_MJPEG_DEC_S1 -+ IMX_SC_R_MJPEG_DEC_S2 -+ IMX_SC_R_MJPEG_DEC_S3 -+ IMX_SC_R_MJPEG_ENC_MP -+ IMX_SC_R_MJPEG_ENC_S0 -+ IMX_SC_R_MJPEG_ENC_S1 -+ IMX_SC_R_MJPEG_ENC_S2 -+ IMX_SC_R_MJPEG_ENC_S3 -+ >; -+ pads = < -+ /* i2c1_lvds1 */ -+ IMX8QM_LVDS0_I2C1_SCL -+ IMX8QM_LVDS0_I2C1_SDA -+ /* emmc */ -+ IMX8QM_EMMC0_CLK -+ IMX8QM_EMMC0_CMD -+ IMX8QM_EMMC0_DATA0 -+ IMX8QM_EMMC0_DATA1 -+ IMX8QM_EMMC0_DATA2 -+ IMX8QM_EMMC0_DATA3 -+ IMX8QM_EMMC0_DATA4 -+ IMX8QM_EMMC0_DATA5 -+ IMX8QM_EMMC0_DATA6 -+ IMX8QM_EMMC0_DATA7 -+ IMX8QM_EMMC0_STROBE -+ IMX8QM_EMMC0_RESET_B -+ -+ /* lvds pwm */ -+ IMX8QM_LVDS0_GPIO00 -+ -+ /* usbotg1/3 */ -+ IMX8QM_USB_SS3_TC0 -+ IMX8QM_QSPI1A_SS0_B -+ IMX8QM_USB_SS3_TC3 -+ IMX8QM_QSPI1A_DATA0 -+ -+ /* ESAI0 */ -+ IMX8QM_ESAI0_FSR -+ IMX8QM_ESAI0_FST -+ IMX8QM_ESAI0_SCKR -+ IMX8QM_ESAI0_SCKT -+ IMX8QM_ESAI0_TX0 -+ IMX8QM_ESAI0_TX1 -+ IMX8QM_ESAI0_TX2_RX3 -+ IMX8QM_ESAI0_TX3_RX2 -+ IMX8QM_ESAI0_TX4_RX1 -+ IMX8QM_ESAI0_TX5_RX0 -+ /* SAI1 */ -+ IMX8QM_SAI1_RXD -+ IMX8QM_SAI1_RXC -+ IMX8QM_SAI1_RXFS -+ IMX8QM_SAI1_TXD -+ IMX8QM_SAI1_TXC -+ -+ IMX8QM_PCIE_CTRL0_CLKREQ_B -+ IMX8QM_PCIE_CTRL0_WAKE_B -+ IMX8QM_PCIE_CTRL0_PERST_B -+ IMX8QM_LVDS1_I2C0_SDA -+ IMX8QM_USDHC2_RESET_B -+ -+ IMX8QM_QSPI1A_DQS -+ IMX8QM_UART1_RX -+ IMX8QM_UART1_TX -+ IMX8QM_UART1_CTS_B -+ IMX8QM_UART1_RTS_B -+ -+ IMX8QM_MIPI_CSI0_I2C0_SCL -+ IMX8QM_MIPI_CSI0_I2C0_SDA -+ IMX8QM_MIPI_CSI1_I2C0_SCL -+ IMX8QM_MIPI_CSI1_I2C0_SDA -+ IMX8QM_MIPI_CSI1_GPIO0_00 -+ -+ IMX8QM_MIPI_CSI0_GPIO0_00 -+ IMX8QM_MIPI_CSI0_GPIO0_01 -+ IMX8QM_MIPI_CSI0_MCLK_OUT -+ -+ IMX8QM_USDHC2_WP -+ -+ IMX8QM_MIPI_DSI0_I2C0_SCL -+ IMX8QM_MIPI_DSI0_I2C0_SDA -+ IMX8QM_MIPI_DSI0_GPIO0_01 -+ -+ IMX8QM_MIPI_DSI1_I2C0_SCL -+ IMX8QM_MIPI_DSI1_I2C0_SDA -+ IMX8QM_MIPI_DSI1_GPIO0_01 -+ -+ IMX8QM_SCU_GPIO0_07 -+ -+ IMX8QM_SPI0_CS1 -+ IMX8QM_SPI2_CS1 -+ IMX8QM_SAI1_RXFS -+ IMX8QM_SAI1_RXC -+ >; -+ -+ gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio1 19 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio1 27 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio1 28 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio1 30 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 1 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 3 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 6 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 9 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>, -+ <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>, -+ <&lsio_gpio4 22 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 25 GPIO_ACTIVE_HIGH>, -+ <&lsio_gpio4 26 GPIO_ACTIVE_HIGH>, -+ <&lsio_gpio4 27 GPIO_ACTIVE_LOW>, -+ <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ /* Interrupt 33 is not used, use it virtual PL031 */ -+ rtc0: rtc@23000000 { -+ interrupts = ; -+ xen,passthrough; -+ }; -+ -+ gpio4_dummy: gpio4_dummy@0{ -+ /* Passthrough gpio4 interrupt to DomU */ -+ interrupts = ; -+ xen,passthrough; -+ }; -+ -+ gpio1_dummy: gpio1_dummy@0{ -+ /* Passthrough gpio1 interrupt to DomU */ -+ interrupts = ; -+ xen,passthrough; -+ }; -+ -+ reserved-device-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ xen,passthrough; -+ }; -+ encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ xen,passthrough; -+ }; -+ m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ xen,passthrough; -+ }; -+ decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x200000>; -+ xen,passthrough; -+ }; -+ encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x200000>; -+ xen,passthrough; -+ }; -+ dsp@0x92400000 { -+ no-map; -+ reg = <0 0x92400000 0 0x2000000>; -+ xen,passthrough; -+ }; -+ encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ xen,passthrough; -+ }; -+ ts_boot@0x95000000 { -+ no-map; -+ reg = <0 0x95000000 0 0x400000>; -+ xen,passthrough; -+ }; -+ }; -+}; -+ -+&{/reserved-memory} { -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x58000000>; -+ linux,cma-default; -+ }; -+}; -+ -+&smmu { -+ mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, <&usdhc1 0x12>, <&edma0 0x14>, -+ <&vpu_decoder 0x7>, <&usbotg1 0x11>, <&usbotg3 0x4>, -+ <&pciea 0x8>, <&edma214 0x10>, <&isi_0 0x5>; -+}; -+ -+&edma0 { -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+ xen,passthrough; -+}; -+ -+&gpu_3d0{ -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+ xen,passthrough; -+}; -+ -+&gpu_3d1{ -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ cores = <&gpu_3d1>; -+ reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; -+ status = "okay"; -+}; -+ -+&lsio_mu1 { -+ /* not map for dom0, dom0 will mmio trap to xen */ -+ xen,no-map; -+}; -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&dpu2_disp0>, <&dpu2_disp1>; -+ }; -+}; -+ -+&dc0_irqsteer { -+ reg = <0x56000000 0x20000>; -+ xen,passthrough; -+}; -+ -+&dc0_pc { -+ xen,passthrough; -+}; -+ -+&dc0_prg1 { -+ xen,passthrough; -+}; -+ -+&dc0_prg2 { -+ xen,passthrough; -+}; -+ -+&dc0_prg3 { -+ xen,passthrough; -+}; -+ -+&dc0_prg4 { -+ xen,passthrough; -+}; -+ -+&dc0_prg5 { -+ xen,passthrough; -+}; -+ -+&dc0_prg6 { -+ xen,passthrough; -+}; -+ -+&dc0_prg7 { -+ xen,passthrough; -+}; -+ -+&dc0_prg8 { -+ xen,passthrough; -+}; -+ -+&dc0_prg9 { -+ xen,passthrough; -+}; -+ -+&dc0_dpr1_channel1 { -+ xen,passthrough; -+}; -+ -+&dc0_dpr1_channel2 { -+ xen,passthrough; -+}; -+ -+&dc0_dpr1_channel3 { -+ xen,passthrough; -+}; -+ -+&dc0_dpr2_channel1 { -+ xen,passthrough; -+}; -+ -+&dc0_dpr2_channel2 { -+ xen,passthrough; -+}; -+ -+&dc0_dpr2_channel3 { -+ xen,passthrough; -+}; -+ -+&dpu1 { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+}; -+ -+&irqsteer_lvds0 { -+ reg = <0x56240000 0x10000>; -+ xen,passthrough; -+}; -+ -+&lvds0_region { -+ xen,passthrough; -+}; -+ -+&i2c1_lvds0 { -+ xen,passthrough; -+}; -+ -+&ldb1_phy { -+ xen,passthrough; -+}; -+ -+&ldb1 { -+ xen,passthrough; -+}; -+ -+&usdhc1 { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+}; -+ -+&sdhc0_lpcg { -+ xen,passthrough; -+}; -+ -+&lsio_mu2 { -+ xen,passthrough; -+}; -+ -+&lsio_gpio1 { -+ /* -+ * Use GPT1 interrupt for hack -+ * This could be removed when interrupt sharing be supported. -+ */ -+ interrupts = ; -+ xen,domu-irq; -+ xen,shared; -+}; -+ -+/* -+&gpt0 { -+ /delete-property/ interrupts; -+ status = "disabled"; -+}; -+*/ -+ -+&lsio_gpio4 { -+ /* -+ * Use GPT0 interrupt for hack -+ * This could be removed when interrupt sharing be supported. -+ */ -+ interrupts = ; -+ xen,domu-irq; -+ xen,shared; -+}; -+ -+&gpio0_mipi_csi0 { -+ xen,passthrough; -+}; -+ -+&gpio0_mipi_csi1 { -+ xen,passthrough; -+}; -+ -+/* vpu_subsys */ -+&vpu_lpcg { -+ xen,passthrough; -+}; -+ -+&vpu_decoder { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+ fsl,sc_rsrc_id = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+&vpu_encoder { -+ xen,passthrough; -+}; -+ -+/* -+&vpu_ts { -+ xen,passthrough; -+}; -+*/ -+ -+&dsp { -+ xen,passthrough; -+}; -+ -+&lsio_mu13 { -+ xen,passthrough; -+}; -+ -+&mu_m0 { -+ xen,passthrough; -+}; -+ -+&mu1_m0 { -+ xen,passthrough; -+}; -+ -+&mu2_m0 { -+ xen,passthrough; -+}; -+ -+/* -+&mu3_m0 { -+ xen,passthrough; -+}; -+*/ -+ -+&vpu_enc_core0 { -+ xen,passthrough; -+}; -+ -+&vpu_enc_core1 { -+ xen,passthrough; -+}; -+ -+&usbotg1 { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+}; -+ -+&usbmisc1 { -+ xen,passthrough; -+}; -+ -+&usbphy1 { -+ xen,passthrough; -+}; -+ -+&usb2_lpcg { -+ xen,passthrough; -+}; -+ -+&usbotg3 { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+}; -+ -+/* -+&usb3phynop1 { -+ status = "disabled"; -+}; -+*/ -+ -+&usb3_lpcg { -+ xen,passthrough; -+}; -+ -+&ptn5110 { -+ status = "disabled"; -+}; -+ -+&{/cbtl04gp} { -+ status = "disabled"; -+}; -+ -+&audio_subsys { -+ reg = <0 0x59000000 0 0x1000000>; -+ xen,passthrough; -+}; -+ -+/* Passthrough baseboard audio to DomU */ -+&cs42888 { -+ xen,passthrough; -+}; -+ -+®_audio { -+ xen,passthrough; -+}; -+ -+&{/sound-cs42888} { -+ xen,passthrough; -+}; -+ -+&esai0 { -+ xen,passthrough; -+}; -+ -+&wm8960 { -+ xen,passthrough; -+}; -+ -+&hsio_subsys { -+ xen,passthrough; -+}; -+ -+&pciea { -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+ xen,passthrough; -+ fsl,sc_rsrc_id = ; -+}; -+ -+&pcieb { -+ xen,passthrough; -+}; -+ -+&epdev_on { -+ status = "disabled"; -+}; -+ -+&lpuart1 { -+ xen,passthrough; -+}; -+ -+&modem_reset { -+ status = "disabled"; -+}; -+ -+&edma214 { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+}; -+ -+&hdmi_subsys { -+ xen,passthrough; -+ reg = <0 0x56260000 0 0x10000>; -+}; -+ -+&img_subsys { -+ xen,passthrough; -+ reg = <0 0x58000000 0 0x1000000>; -+}; -+ -+&mipi0_subsys { -+ xen,passthrough; -+ reg = <0 0x56220000 0 0x10000>; -+}; -+ -+&mipi1_subsys { -+ xen,passthrough; -+ reg = <0 0x57220000 0 0x10000>; -+}; -+ -+&isi_0 { -+ xen,passthrough; -+ #stream-id-cells = <1>; -+ iommus = <&smmu>; -+ fsl,sc_rsrc_id = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+&sc_pwrkey { -+ status = "disabled"; -+}; -+ -+&pwm_lvds0 { -+ status = "disabled"; -+}; -+ -+&uart0_lpcg { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts -new file mode 100644 -index 000000000..bf499f482 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts -@@ -0,0 +1,1474 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * At current stage, M41 is not ready to communicate with XEN, so we -+ * we need a way to tell XEN uboot is running or linux is running. -+ * XEN will check the contents of this area. -+ * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux -+ * touch this area. -+ */ -+/memreserve/ 0x80000000 0x1000; -+ -+/ { -+ model = "Freescale i.MX8QM DOMU"; -+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <0x2>; -+ #size-cells = <0x2>; -+ -+ aliases { -+ mmc0 = &usdhc1; -+ dpu0 = &dpu1; -+ ldb0 = &ldb1; -+ serial1 = &lpuart1; -+ isi0 = &isi_0; -+ isi1 = &isi_1; -+ isi2 = &isi_2; -+ isi3 = &isi_3; -+ isi4 = &isi_4; -+ isi5 = &isi_5; -+ isi6 = &isi_6; -+ isi7 = &isi_7; -+ csi0 = &mipi_csi_0; -+ csi1 = &mipi_csi_1; -+ mu1 = &lsio_mu1; -+ mu2 = &lsio_mu2; -+ dphy0 = &mipi0_dphy; -+ dphy1 = &mipi1_dphy; -+ mipi_dsi0 = &mipi0_dsi_host; -+ mipi_dsi1 = &mipi1_dsi_host; -+ }; -+ -+ cpus { -+ #address-cells = <0x2>; -+ #size-cells = <0x0>; -+ -+ cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x0>; -+ }; -+ -+ cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x1>; -+ }; -+ -+ cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x2>; -+ }; -+ -+ cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x3>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "hvc"; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ /* Will be updated by U-Boot or XEN TOOL */ -+ reg = <0x00000000 0x80000000 0 0x80000000>; -+ }; -+ -+ /* -+ * The reserved memory will be used when using U-Boot loading android -+ * image. For booting kernel using xl tool, pass args: -+ * cma=960M@2400M-3584M -+ */ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ passthrough; -+ -+ decoder_boot: decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_boot: encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ }; -+ decoder_rpc: decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x200000>; -+ }; -+ encoder_rpc: encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x200000>; -+ }; -+ encoder_reserved: encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ ts_boot: ts_boot@0x95000000 { -+ no-map; -+ reg = <0 0x95000000 0 0x400000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ -+ }; -+ -+ gic: interrupt-controller@3001000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ #address-cells = <0x0>; -+ interrupt-controller; -+ redistributor-stride = <0x20000>; -+ #redistributor-regions = <0x1>; -+ reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x3020000 0 0x1000000>; /* GICR */ -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ linux,phandle = <0xfde8>; -+ phandle = <0xfde8>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ ; -+ interrupt-parent = <&gic>; -+ clock-frequency = <8000000>; -+ }; -+ -+ hypervisor { -+ compatible = "xen,xen-4.11", "xen,xen"; -+ reg = <0x0 0x38000000 0x0 0x1000000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clk0: clock@0 { -+ compatible = "fixed-clock"; -+ reg = <0>; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ }; -+ }; -+ -+ rtc0: rtc@23000000 { -+ compatible = "arm,pl031", "arm,primecell"; -+ reg = <0x0 0x23000000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clk0>; -+ clock-names = "apb_pclk"; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_modem_reset>; -+ pinctrl-1 = <&pinctrl_modem_reset_sleep>; -+ reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ xen,passthrough; -+ }; -+ -+ passthrough { -+ compatible = "simple-bus"; -+ ranges; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", "tx1", "tx2", "tx3", -+ "rx0", "rx1", "rx2", "rx3", -+ "gip3"; -+ mboxes = <&lsio_mu2 0 0 -+ &lsio_mu2 0 1 -+ &lsio_mu2 0 2 -+ &lsio_mu2 0 3 -+ &lsio_mu2 1 0 -+ &lsio_mu2 1 1 -+ &lsio_mu2 1 2 -+ &lsio_mu2 1 3 -+ &lsio_mu2 3 3>; -+ -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8qm-iomuxc"; -+ }; -+ -+ }; -+ -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-gpu0.dtsi" -+ #include "imx8-ss-gpu1.dtsi" -+ #include "imx8-ss-vpu.dtsi" -+ -+ brcmfmac: brcmfmac { -+ compatible = "cypress,brcmfmac"; -+ pinctrl-names = "init", "idle", "default"; -+ pinctrl-0 = <&pinctrl_wifi_init>; -+ pinctrl-1 = <&pinctrl_wifi_init>; -+ pinctrl-2 = <&pinctrl_wifi>; -+ }; -+ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds0 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ }; -+ -+ #include "imx8-ss-dc0.dtsi" -+ #include "imx8-ss-dc1.dtsi" -+ #include "imx8-ss-audio.dtsi" -+ #include "imx8-ss-hsio.dtsi" -+ #include "imx8-ss-dma.dtsi" -+ #include "imx8-ss-img.dtsi" -+ -+ sc_pwrkey: sc-powerkey { -+ compatible = "fsl,imx8-pwrkey"; -+ linux,keycode = ; -+ xen,passthrough; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ xen,passthrough; -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_wlreg_on>; -+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&lsio_gpio1 13 0>; -+ enable-active-high; -+ xen,passthrough; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ esai-controller = <&esai0>; -+ audio-codec = <&cs42888>; -+ audio-asrc = <&asrc0>; -+ status = "okay"; -+ xen,passthrough; -+ }; -+ -+ xen_i2c0: xen_i2c@0 { -+ compatible = "xen,i2c"; -+ be-adapter = "5a800000.i2c"; -+ status = "okay"; -+ xen,passthrough; -+ }; -+ -+ xen_i2c1: xen_i2c@1 { -+ compatible = "xen,i2c"; -+ be-adapter = "3b230000.i2c"; -+ xen,passthrough; -+ status = "okay"; -+ }; -+ -+ cbtl04gp { -+ compatible = "nxp,cbtl04gp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec_mux>; -+ switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; -+ reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ orientation-switch; -+ xen,passthrough; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+ -+ vpu_subsys_dsp: bus@55000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x55000000 0x0 0x55000000 0x1000000>; -+ xen,passthrough; -+ -+ dsp: dsp@556e8000 { -+ compatible = "fsl,imx8qm-hifi4"; -+ reg = <0x556e8000 0x88000>; -+ clocks = <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>; -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ status = "disabled"; -+ }; -+ }; -+ -+}; -+ -+#include "imx8qm-ss-conn.dtsi" -+#include "imx8qm-ss-lsio.dtsi" -+#include "imx8qm-ss-dc.dtsi" -+#include "imx8qm-ss-gpu.dtsi" -+#include "imx8qm-ss-lvds.dtsi" -+#include "imx8qm-ss-mipi.dtsi" -+#include "imx8qm-ss-hdmi.dtsi" -+#include "imx8qm-ss-audio.dtsi" -+#include "imx8qm-ss-hsio.dtsi" -+#include "imx8qm-ss-dma.dtsi" -+#include "imx8qm-ss-mipi.dtsi" -+#include "imx8qm-ss-hdmi.dtsi" -+#include "imx8qm-ss-img.dtsi" -+ -+/ { -+ display-subsystem { -+ xen,passthrough; -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&dpu1_disp0>, <&dpu1_disp1>; -+ }; -+}; -+ -+&lsio_mu13 { -+ xen,passthrough; -+}; -+ -+&dc0_subsys { -+ xen,passthrough; -+}; -+ -+&dma_subsys { -+ xen,passthrough; -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; -+ -+ -+ edma214: dma-controller@5a2e0000 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x5a1f0000 0x10000>, -+ <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ -+ <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ -+ #dma-cells = <3>; -+ dma-channels = <2>; -+ interrupts = , -+ ; -+ interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; -+ power-domains = <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>; -+ power-domain-names = "edma0-chan14", "edma0-chan15"; -+ status = "okay"; -+ }; -+}; -+ -+&audio_subsys { -+ xen,passthrough; -+}; -+ -+&hsio_subsys { -+ xen,passthrough; -+}; -+ -+&lvds1_subsys { -+ xen,passthrough; -+}; -+ -+&hdmi_subsys { -+ xen,passthrough; -+}; -+ -+&lsio_mu1 { -+ status = "disabled"; -+}; -+ -+&lsio_mu2 { -+ status = "okay"; -+}; -+ -+&pwm_lvds0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds0>; -+ status = "okay"; -+}; -+ -+&i2c1_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1_phy { -+ status="okay"; -+}; -+ -+&ldb1 { -+ status="okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dc0_pc { -+ status="okay"; -+}; -+ -+&dc0_prg1 { -+ status="okay"; -+}; -+ -+&dc0_prg2 { -+ status="okay"; -+}; -+ -+&dc0_prg3 { -+ status="okay"; -+}; -+ -+&dc0_prg4 { -+ status="okay"; -+}; -+ -+&dc0_prg5 { -+ status="okay"; -+}; -+ -+&dc0_prg6 { -+ status="okay"; -+}; -+ -+&dc0_prg7 { -+ status="okay"; -+}; -+ -+&dc0_prg8 { -+ status="okay"; -+}; -+ -+&dc0_prg9 { -+ status="okay"; -+}; -+ -+&dc0_dpr1_channel1 { -+ status="okay"; -+}; -+ -+&dc0_dpr1_channel2 { -+ status="okay"; -+}; -+ -+&dc0_dpr1_channel3 { -+ status="okay"; -+}; -+ -+&dc0_dpr2_channel1 { -+ status="okay"; -+}; -+ -+&dc0_dpr2_channel2 { -+ status="okay"; -+}; -+ -+&dc0_dpr2_channel3 { -+ status="okay"; -+}; -+ -+&dpu1 { -+ status="okay"; -+}; -+ -+&gpu_3d0 { -+ status = "okay"; -+}; -+ -+&gpu_3d1 { -+ status = "disabled"; -+}; -+ -+&imx8_gpu_ss { -+ /* xen guests have 2GB of low RAM @ 2GB */ -+ reg = <0x80000000 0x80000000>, <0x0 0x10000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+ cores = <&gpu_3d0>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ -+ pinctrl_wifi: wifigrp{ -+ fsl,pins = < -+ IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 -+ >; -+ }; -+ -+ pinctrl_wifi_init: wifi_initgrp{ -+ fsl,pins = < -+ /* reserve pin init/idle_state to support multiple wlan cards */ -+ >; -+ }; -+ -+ pinctrl_pwm_lvds0: pwmlvds0grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_typec: typecgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 -+ >; -+ }; -+ -+ pinctrl_typec_mux: typecmuxgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 -+ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_pciea: pcieagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 -+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 -+ IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 -+ >; -+ }; -+ -+ pinctrl_wlreg_on: wlregongrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 -+ >; -+ }; -+ -+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 -+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 -+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_modem_reset: modemresetgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 -+ >; -+ }; -+ -+ pinctrl_modem_reset_sleep: modemreset_sleepgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0: mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 -+ IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 -+ IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_mipi_csi1: mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 -+ IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 -+ IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 -+ >; -+ }; -+ -+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 -+ >; -+ }; -+}; -+ -+&usdhc1 { -+ /delete-property/ iommus; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&usdhc3 { -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&fec1 { -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&fec2 { -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+/* -+&usb3phynop1 { -+ status = "okay"; -+}; -+*/ -+ -+&usbotg3 { -+ dr_mode = "otg"; -+ extcon = <&ptn5110>; -+ status = "okay"; -+ /delete-property/ iommus; -+}; -+ -+&xen_i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <11 2>; -+ }; -+ -+ fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ interrupt-open-drain; -+ }; -+ -+ fxas2100x@20 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x20>; -+ interrupt-open-drain; -+ }; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ interrupt-open-drain; -+ }; -+ -+ ptn5110: tcpc@51 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x51>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ usb_con1: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "source"; -+ data-role = "dual"; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&mu_m0{ -+ interrupts = ; -+}; -+ -+&mu1_m0{ -+ interrupts = ; -+}; -+ -+&mu2_m0{ -+ interrupts = ; -+ status = "okay"; -+}; -+ -+/* -+&mu3_m0{ -+ interrupts = ; -+ status = "okay"; -+}; -+*/ -+ -+&vpu_decoder { -+ compatible = "nxp,imx8qm-b0-vpudec"; -+ boot-region = <&decoder_boot>; -+ rpc-region = <&decoder_rpc>; -+ reg-csr = <0x2d080000>; -+ core_type = <2>; -+ status = "okay"; -+}; -+ -+/* -+&vpu_ts { -+ compatible = "nxp,imx8qm-b0-vpu-ts"; -+ boot-region = <&ts_boot>; -+ reg-csr = <0x2d0b0000>; -+ status = "okay"; -+}; -+*/ -+ -+&vpu_encoder { -+ compatible = "nxp,imx8qm-b0-vpuenc"; -+ boot-region = <&encoder_boot>; -+ rpc-region = <&encoder_rpc>; -+ reserved-region = <&encoder_reserved>; -+ reg-rpc-system = <0x40000000>; -+ resolution-max = <1920 1920>; -+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, -+ <&pd IMX_SC_R_VPU>; -+ power-domain-names = "vpuenc1", "vpuenc2", "vpu"; -+ mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", -+ "enc2_tx0", "enc2_tx1", "enc2_rx"; -+ mboxes = <&mu1_m0 0 0 -+ &mu1_m0 0 1 -+ &mu1_m0 1 0 -+ &mu2_m0 0 0 -+ &mu2_m0 0 1 -+ &mu2_m0 1 0>; -+ status = "okay"; -+ -+ vpu_enc_core0: core0@1020000 { -+ compatible = "fsl,imx8-mu1-vpu-m0"; -+ reg = <0x1020000 0x20000>; -+ reg-csr = <0x1090000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <17>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+ -+ vpu_enc_core1: core1@1040000 { -+ compatible = "fsl,imx8-mu2-vpu-m0"; -+ reg = <0x1040000 0x20000>; -+ reg-csr = <0x10A0000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <18>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+}; -+ -+&lsio_gpio4 { -+ /delete-property/ power-domains; -+}; -+ -+&lsio_gpio1 { -+ /delete-property/ power-domains; -+}; -+ -+/* Audio */ -+&dsp { -+ compatible = "fsl,imx8qm-hifi4"; -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ /*pinctrl-0 = <&pinctrl_sai1>;*/ -+ status = "disabled"; -+}; -+ -+&sai6 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai6_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&usbotg3_cdns3 { -+ /delete-property/ iommus; -+ status = "disabled"; -+}; -+&sai7 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai7_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&xen_i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ status = "okay"; -+ }; -+}; -+ -+&sai6 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai6_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&sai7 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai7_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "disabled"; -+}; -+ -+&sata { -+ /delete-property/ iommus; -+}; -+ -+&pciea{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ epdev_on-supply = <&epdev_on>; -+ status = "okay"; -+}; -+ -+&pcieb{ -+ status = "disabled"; -+}; -+ -+&edma2 { -+ status = "disabled"; -+}; -+ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "okay"; -+ dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; -+}; -+ -+&img_subsys { -+ xen,passthrough; -+}; -+ -+&hdmi_subsys { -+ xen,passthrough; -+}; -+ -+&mipi0_subsys { -+ xen,passthrough; -+}; -+ -+&mipi1_subsys { -+ xen,passthrough; -+}; -+ -+&dsi_ipg_clk { -+ xen,passthrough; -+}; -+ -+&mipi_pll_div2_clk { -+ xen,passthrough; -+}; -+ -+&i2c0_mipi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ adv_bridge0: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_0_in: endpoint { -+ remote-endpoint = <&mipi0_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi0_adv_out: endpoint { -+ remote-endpoint = <&adv7535_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ adv_bridge1: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_1_in: endpoint { -+ remote-endpoint = <&mipi1_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi1_adv_out: endpoint { -+ remote-endpoint = <&adv7535_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_2 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_3 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_4 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_5 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_6 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_7 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer_csi0 { -+ status = "okay"; -+}; -+ -+&irqsteer_csi1 { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 1 MIPI CSI-2 (CSIS1) */ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&max9286_1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&jpegdec { -+ status = "okay"; -+}; -+ -+&jpegenc { -+ status = "okay"; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "okay"; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi1>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "okay"; -+ port { -+ max9286_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+ -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts -new file mode 100644 -index 000000000..32ac9ca1b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts -@@ -0,0 +1,101 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qm-mek.dts" -+ -+/delete-node/ &adv_bridge0; -+/delete-node/ &adv_bridge1; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ -+ panel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; -+ pinctrl-names = "default"; -+ reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ -+ port@0 { -+ reg = <0>; -+ panel0_in: endpoint { -+ remote-endpoint = <&mipi0_panel_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ mipi0_panel_out: endpoint { -+ remote-endpoint = <&panel0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ -+ panel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ -+ port@0 { -+ reg = <0>; -+ panel1_in: endpoint { -+ remote-endpoint = <&mipi1_panel_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ mipi1_panel_out: endpoint { -+ remote-endpoint = <&panel1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts -new file mode 100644 -index 000000000..61e7c4b64 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts -@@ -0,0 +1,16 @@ -+/* -+ * Copyright 2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qm-mek.dts" -+#include "imx8qm-enet2-tja1100.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts -new file mode 100644 -index 000000000..bd3558911 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+#include "imx8qm-mek-rpmsg.dts" -+ -+/ { -+ esai_client0: esai_client@0 { -+ compatible = "fsl,esai-client"; -+ fsl,client-id = <0>; -+ }; -+ -+ esai_client1: esai_client@1 { -+ compatible = "fsl,esai-client"; -+ fsl,client-id = <1>; -+ }; -+}; -+ -+&esai0 { -+ client-dais = <&esai_client0>, <&esai_client1>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts -new file mode 100644 -index 000000000..582b6f336 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ * Sandor Yu -+ */ -+/* -+ * HDMI RX only dts. -+ */ -+ -+#include "imx8qm-mek-hdmi.dts" -+ -+/ { -+ sound-hdmi-rx { -+ compatible = "fsl,imx-audio-cdnhdmi"; -+ model = "imx-audio-hdmi-rx"; -+ audio-cpu = <&sai4>; -+ protocol = <1>; -+ hdmi-in; -+ }; -+}; -+ -+&sai4 { -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&sai4_lpcg { -+ status = "okay"; -+}; -+ -+/* HDMI RX */ -+&isi_2 { -+ interface = <4 0 2>; /* -+ Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM -+ VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only -+ Output: 0-DC0, 1-DC1, 2-MEM */ -+ status = "okay"; -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_3 { -+ /* For HDMI RX 4K chain buf */ -+ interface = <4 0 2>; -+ status = "okay"; -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&mipi_csi_0 { -+ status = "disabled"; -+}; -+ -+&i2c_mipi_csi0 { -+ status = "disabled"; -+}; -+ -+&hdmi_rx_lpcg_gpio_ipg_s { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_pwm_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_pwm_ipg_s { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_pwm { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_i2c0 { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_i2c0_div { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_i2c0_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_i2c0_ipg_s { -+ status = "okay"; -+}; -+&hdmi_rx_lpcg_sink_p { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_sink_s { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_hd_core { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_pxl { -+ status = "okay"; -+}; -+ -+&hdmi_rx_lpcg_enc { -+ status = "okay"; -+}; -+ -+&irqsteer_hdmi_rx { -+ status = "okay"; -+}; -+ -+&hdmi_rx { -+ fsl,cec; -+ firmware-name = "hdmirxfw.bin"; -+ assigned-clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC1>, -+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>; -+ assigned-clock-parents = <&hdmi_rx_dig_pll>, -+ <&clk IMX_SC_R_HDMI_RX_BYPASS IMX_SC_PM_CLK_MISC2>; -+ assigned-clock-rates = <400000000>, <0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts -new file mode 100644 -index 000000000..75d0ebf5c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts -@@ -0,0 +1,132 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Sandor Yu -+ */ -+ /* HDMI Only driver, LVDS is disabled */ -+ -+/dts-v1/; -+ -+#include "imx8qm-mek-rpmsg.dts" -+ -+/ { -+ sound-hdmi-tx { -+ compatible = "fsl,imx-audio-cdnhdmi"; -+ model = "imx-audio-hdmi-tx"; -+ audio-cpu = <&sai5>; -+ protocol = <1>; -+ hdmi-out; -+ }; -+ -+ sound-hdmi-arc { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-hdmi-arc"; -+ spdif-controller = <&spdif1>; -+ spdif-in; -+ spdif-out; -+ }; -+}; -+ -+&sai5 { -+ status = "okay"; -+}; -+ -+&sai5_lpcg { -+ status = "okay"; -+}; -+ -+&ldb1_phy { -+ status = "disabled"; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -+ -+&ldb2_phy { -+ status = "disabled"; -+}; -+ -+&ldb2 { -+ status = "disabled"; -+}; -+ -+&mipi0_dsi_host { -+ status = "disabled"; -+}; -+ -+&mipi1_dphy { -+ status = "disabled"; -+}; -+ -+&mipi1_dsi_host { -+ status = "disabled"; -+}; -+ -+&mipi1_dphy { -+ status = "disabled"; -+}; -+ -+&irqsteer_hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_i2c0 { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_lis_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_pwm_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_i2s { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_gpio_ipg { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_msi_hclk { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_pxl { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_phy { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_apb_mux_csr { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_apb_mux_ctrl { -+ status = "okay"; -+}; -+ -+&hdmi_lpcg_apb { -+ status = "okay"; -+}; -+ -+&hdmi { -+ compatible = "cdn,imx8qm-hdmi"; -+ firmware-name = "hdmitxfw.bin"; -+ lane-mapping = <0x93>; -+ hdcp-config = <0x3>; -+ status = "okay"; -+}; -+ -+&spdif1 { -+ status = "okay"; -+}; -+ -+&spdif1_lpcg { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts -new file mode 100644 -index 000000000..e1b9e53b3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts -@@ -0,0 +1,284 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ model = "Freescale i.MX8QM MEK inmate"; -+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <0x2>; -+ #size-cells = <0x2>; -+ -+ aliases { -+ mmc0 = &usdhc1; -+ serial2 = &lpuart2; -+ }; -+ -+ cpus { -+ #address-cells = <0x2>; -+ #size-cells = <0x0>; -+ -+ cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x2>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ }; -+ -+ cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x3>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", "tx1", "tx2", "tx3", -+ "rx0", "rx1", "rx2", "rx3", -+ "gip3"; -+ mboxes = <&lsio_mu2 0 0 -+ &lsio_mu2 0 1 -+ &lsio_mu2 0 2 -+ &lsio_mu2 0 3 -+ &lsio_mu2 1 0 -+ &lsio_mu2 1 1 -+ &lsio_mu2 1 2 -+ &lsio_mu2 1 3 -+ &lsio_mu2 3 3>; -+ -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8qm-iomuxc"; -+ }; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ pci@fd700000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xfd700000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ /* For early console */ -+ serial@5a060000 { -+ compatible = "fsl,imx8qm-lpuart"; -+ reg = <0x0 0x5a060000 0x0 0x1000>; -+ }; -+ -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+}; -+ -+#include "imx8qm-ss-lsio.dtsi" -+#include "imx8qm-ss-dma.dtsi" -+#include "imx8qm-ss-conn.dtsi" -+ -+&edma0 { -+ status = "disabled"; -+}; -+ -+&edma1 { -+ status = "disabled"; -+}; -+ -+&edma2 { -+ status = "disabled"; -+}; -+ -+&acm { -+ status = "disabled"; -+}; -+ -+&lsio_mu1 { -+ status = "disabled"; -+}; -+ -+&lsio_mu2 { -+ status = "okay"; -+}; -+ -+&lsio_gpio0 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio1 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio2 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio3 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio4 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio5 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio6 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio7 { -+ status = "disabled"; -+}; -+ -+&fec1 { -+ /delete-property/ iommus; -+}; -+ -+&fec2 { -+ /delete-property/ iommus; -+}; -+ -+&usdhc1 { -+ /delete-property/ iommus; -+}; -+ -+&usdhc2 { -+ /delete-property/ iommus; -+}; -+ -+&usdhc3 { -+ /delete-property/ iommus; -+}; -+ -+&usbotg3 { -+ /delete-property/ iommus; -+}; -+ -+&usbotg3_cdns3 { -+ /delete-property/ iommus; -+}; -+ -+&iomuxc { -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 -+ IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+}; -+ -+&lpuart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ status = "okay"; -+ /delete-property/ dma-names; -+ /delete-property/ dmas; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts -new file mode 100644 -index 000000000..b57423235 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qm-mek-rpmsg.dts" -+#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts -new file mode 100644 -index 000000000..821f37d50 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+#include "imx8qm-mek.dts" -+#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi -new file mode 100644 -index 000000000..68e96d811 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi -@@ -0,0 +1,53 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/ { -+ lvds1_panel { -+ compatible = "jdi,tx26d202vm0bwa"; -+ backlight = <&lvds_backlight1>; -+ -+ port { -+ panel_lvds1_in: endpoint { -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1_phy { -+ status = "disabled"; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -+ -+&i2c1_lvds0 { -+ lvds-to-hdmi-bridge@4c { -+ status = "disabled"; -+ }; -+}; -+ -+/delete-node/ &it6263_1_in; -+ -+&ldb2 { -+ status = "okay"; -+ fsl,dual-channel; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&panel_lvds1_in>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts -new file mode 100644 -index 000000000..e58913258 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts -@@ -0,0 +1,154 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+#include "imx8qm-mek.dts" -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_2 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_3 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_4 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_5 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_6 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_7 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&mipi_csi_0 { -+ /delete-property/virtual-channel; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_0_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ /delete-property/virtual-channel; -+ -+ /* Camera 1 MIPI CSI-2 (CSIS0) */ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_1_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi0 { -+ ov5640_mipi_0: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&xtal24m>; -+ clock-names = "xclk"; -+ csi_id = <0>; -+ powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ port { -+ ov5640_mipi_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2>; -+ clocks-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ /delete-node/max9286_mipi@6a; -+}; -+ -+&i2c_mipi_csi1 { -+ ov5640_mipi_1: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi1>; -+ clocks = <&xtal24m>; -+ clock-names = "xclk"; -+ csi_id = <0>; -+ powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ port { -+ ov5640_mipi_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2>; -+ clocks-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ /delete-node/max9286_mipi@6a; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts -new file mode 100644 -index 000000000..5127d82ff ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qm-mek-rpmsg.dts" -+ -+&pciea{ -+ status = "disabled"; -+}; -+ -+&pcieb{ -+ status = "disabled"; -+}; -+ -+&pciea_ep{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts -new file mode 100644 -index 000000000..55cb2af80 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts -@@ -0,0 +1,108 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8qm-mek.dts" -+ -+/ { -+ domu { -+ /* -+ * There are 5 MUs, 0A is used by root cell, 1A is used -+ * by ATF, so for non-root cell, 2A/3A/4A could be used. -+ * SC_R_MU_0A -+ * SC_R_MU_1A -+ * SC_R_MU_2A -+ * SC_R_MU_3A -+ * SC_R_MU_4A -+ * The rsrcs and pads will be configured by uboot scu_rm cmd -+ */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ doma { -+ /* -+ * This is not for domu, this is just reuse -+ * the method for jailhouse inmate non root cell -+ * Linux. -+ */ -+ compatible = "xen,domu"; -+ /* -+ * The reg property will be updated by U-Boot to -+ * reflect the partition id. -+ */ -+ reg = <0>; -+ init_on_rsrcs = < -+ IMX_SC_R_MU_2A -+ >; -+ rsrcs = < -+ IMX_SC_R_SDHC_0 -+ IMX_SC_R_UART_2 -+ IMX_SC_R_MU_2A -+ >; -+ pads = < -+ /* emmc */ -+ IMX8QM_EMMC0_CLK -+ IMX8QM_EMMC0_CMD -+ IMX8QM_EMMC0_DATA0 -+ IMX8QM_EMMC0_DATA1 -+ IMX8QM_EMMC0_DATA2 -+ IMX8QM_EMMC0_DATA3 -+ IMX8QM_EMMC0_DATA4 -+ IMX8QM_EMMC0_DATA5 -+ IMX8QM_EMMC0_DATA6 -+ IMX8QM_EMMC0_DATA7 -+ IMX8QM_EMMC0_STROBE -+ IMX8QM_EMMC0_RESET_B -+ /* lpuart2 */ -+ IMX8QM_UART0_RTS_B -+ IMX8QM_UART0_CTS_B -+ >; -+ }; -+ }; -+ -+}; -+ -+&{/reserved-memory} { -+ -+ jh_reserved: jh@0xfdc00000 { -+ no-map; -+ reg = <0x0 0xfdc00000 0x0 0x400000>; -+ }; -+ -+ loader_reserved: loader@0xfdb00000 { -+ no-map; -+ reg = <0x0 0xfdb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem_reserved: ivshmem@0xfd900000 { -+ no-map; -+ reg = <0x0 0xfd900000 0x0 0x00200000>; -+ }; -+ -+ pci_reserved: pci@0xfd700000 { -+ no-map; -+ reg = <0x0 0xfd700000 0x0 0x00200000>; -+ }; -+ -+ /* Decrease if no need such big memory */ -+ inmate_reserved: inmate@0xdf7000000 { -+ no-map; -+ reg = <0x0 0xdf700000 0x0 0x1e000000>; -+ }; -+}; -+ -+&smmu { -+ /* Jailhouse hypervisor will initialize SMMU and use it. */ -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ /* Let U-Boot program SID */ -+ iommus = <&smmu 0x10 0x7f80>; -+ /delete-property/ compatible; -+}; -+ -+&lpuart2 { -+ /* Let inmate linux use this for console */ -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts -new file mode 100644 -index 000000000..5639b0a84 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts -@@ -0,0 +1,108 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+#include "imx8qm-mek.dts" -+ -+/delete-node/ &cm41_i2c; -+ -+&i2c_rpbus_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ status = "okay"; -+ }; -+}; -+ -+&cm41_i2c_lpcg { -+ status = "disabled"; -+}; -+ -+®_can01_en { -+ status = "disabled"; -+}; -+ -+®_can2_en { -+ status = "disabled"; -+}; -+ -+®_can01_stby { -+ status = "disabled"; -+}; -+ -+®_can2_stby { -+ status = "disabled"; -+}; -+ -+&cm41_intmux { -+ status = "disabled"; -+}; -+ -+&can0_lpcg { -+ status = "disabled"; -+}; -+ -+&can1_lpcg { -+ status = "disabled"; -+}; -+ -+&can2_lpcg { -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ status = "disabled"; -+}; -+ -+&flexcan2 { -+ status = "disabled"; -+}; -+ -+&flexcan3 { -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ status = "disabled"; -+}; -+ -+&lpuart2 { -+ status = "disabled"; -+}; -+ -+&uart2_lpcg { -+ status = "disabled"; -+}; -+ -+&imx8qm_cm40 { -+ /* Assume you have partitioned M4, so M4 is ont controled by Linux */ -+ /delete-property/ power-domains; -+}; -+ -+&imx8qm_cm41 { -+ /* Assume you have partitioned M4, so M4 is ont controled by Linux */ -+ /delete-property/ power-domains; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts -new file mode 100644 -index 000000000..1296cc17b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts -@@ -0,0 +1,175 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2020 -+ -+#include "imx8qm-mek-rpmsg.dts" -+ -+/ { -+ reserved-memory { -+ /delete-node/ dsp_reserved; -+ /delete-node/ dsp_reserved_heap; -+ /delete-node/ dsp_vdev0vring0; -+ /delete-node/ dsp_vdev0vring1; -+ /delete-node/ dsp_vdev0buffer; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x2000000>; -+ no-map; -+ }; -+ }; -+ -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+ -+ sof-audio-cs42888 { -+ compatible = "simple-audio-card"; -+ label = "imx-cs42888"; -+ simple-audio-card,widgets = -+ "Line", "Line Out Jack", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ status = "okay"; -+ simple-audio-card,dai-link { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&dsp 0>; -+ }; -+ codec { -+ sound-dai = <&cs42888>; -+ }; -+ }; -+ }; -+}; -+ -+&edma0 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x5a1f0000 0x10000>, -+ <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x592e0000 0x10000>, /* sai1 rx */ -+ <0x592f0000 0x10000>, /* sai1 tx */ -+ <0x59350000 0x10000>, -+ <0x59370000 0x10000>; -+ #dma-cells = <3>; -+ shared-interrupt; -+ dma-channels = <8>; -+ interrupts = , /* spdif0 */ -+ , -+ , /* sai0 */ -+ , -+ , /* sai1 */ -+ , -+ , -+ ; -+ interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ -+ "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ -+ "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ -+ "edma2-chan21-tx", /* gpt5 */ -+ "edma2-chan23-rx"; /* gpt7 */ -+ power-domains = <&pd IMX_SC_R_DMA_2_CH8>, -+ <&pd IMX_SC_R_DMA_2_CH9>, -+ <&pd IMX_SC_R_DMA_2_CH12>, -+ <&pd IMX_SC_R_DMA_2_CH13>, -+ <&pd IMX_SC_R_DMA_2_CH14>, -+ <&pd IMX_SC_R_DMA_2_CH15>, -+ <&pd IMX_SC_R_DMA_2_CH21>, -+ <&pd IMX_SC_R_DMA_2_CH23>; -+ power-domain-names = "edma2-chan8", "edma2-chan9", -+ "edma2-chan12", "edma2-chan13", -+ "edma2-chan14", "edma2-chan15", -+ "edma2-chan21", "edma2-chan23"; -+ status = "okay"; -+}; -+ -+&dsp { -+ compatible = "fsl,imx8qm-dsp"; -+ #sound-dai-cells = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ -+ clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, -+ <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>; -+ clock-names = "ipg", "ocram", "core", -+ "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba"; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>, -+ <&pd IMX_SC_R_IRQSTR_DSP>, -+ <&pd IMX_SC_R_DMA_2_CH6>, -+ <&pd IMX_SC_R_DMA_2_CH7>, -+ <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>; -+ -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&lsio_mu13 2 0>, -+ <&lsio_mu13 2 1>, -+ <&lsio_mu13 3 0>, -+ <&lsio_mu13 3 1>; -+ memory-region = <&dsp_reserved>; -+ /delete-property/ firmware-name; -+ -+ tplg-name = "sof-imx8-cs42888.tplg"; -+ machine-drv-name = "asoc-simple-card"; -+ -+ status = "okay"; -+}; -+ -+&amix { -+ status = "disabled"; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&asrc0 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&wm8960 { -+ status = "disabled"; -+}; -+ -+&cs42888 { -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts -new file mode 100644 -index 000000000..faf476e4b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts -@@ -0,0 +1,168 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2018 -+ -+#include "imx8qm-mek-rpmsg.dts" -+ -+/ { -+ reserved-memory { -+ /delete-node/ dsp_reserved; -+ /delete-node/ dsp_reserved_heap; -+ /delete-node/ dsp_vdev0vring0; -+ /delete-node/ dsp_vdev0vring1; -+ /delete-node/ dsp_vdev0buffer; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x2000000>; -+ no-map; -+ }; -+ }; -+ -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+ -+ sof-sound-wm8960 { -+ compatible = "simple-audio-card"; -+ label = "wm8960-audio"; -+ simple-audio-card,bitclock-master = <&sndcodec>; -+ simple-audio-card,frame-master = <&sndcodec>; -+ hp-det-gpio = <&lsio_gpio1 0 0>; -+ mic-det-gpio = <&lsio_gpio1 0 0>; -+ simple-audio-card,widgets = -+ "Headphone", "Headphones", -+ "Speaker", "Ext Spk", -+ "Microphone", "Mic Jack"; -+ simple-audio-card,routing = -+ "Headphones", "HP_L", -+ "Headphones", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "Mic Jack", -+ "RINPUT2", "Mic Jack", -+ "Mic Jack", "MICB"; -+ simple-audio-card,dai-link { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&dsp 1>; -+ }; -+ sndcodec: codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+ }; -+}; -+ -+&edma0 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x591f0000 0x10000>, -+ <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x59350000 0x10000>, -+ <0x59370000 0x10000>; -+ #dma-cells = <3>; -+ shared-interrupt; -+ dma-channels = <6>; -+ interrupts = , /* spdif0 */ -+ , -+ , /* sai0 */ -+ , -+ , -+ ; -+ interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ -+ "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ -+ "edma2-chan21-tx", /* gpt5 */ -+ "edma2-chan23-rx"; /* gpt7 */ -+ -+ power-domains = <&pd IMX_SC_R_DMA_2_CH8>, -+ <&pd IMX_SC_R_DMA_2_CH9>, -+ <&pd IMX_SC_R_DMA_2_CH12>, -+ <&pd IMX_SC_R_DMA_2_CH13>, -+ <&pd IMX_SC_R_DMA_2_CH21>, -+ <&pd IMX_SC_R_DMA_2_CH23>; -+ power-domain-names = "edma2-chan8", "edma2-chan9", -+ "edma2-chan12", "edma2-chan13", -+ "edma2-chan21", "edma2-chan23"; -+ status = "okay"; -+}; -+ -+&dsp { -+ compatible = "fsl,imx8qm-dsp"; -+ #sound-dai-cells = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>, -+ <&pd IMX_SC_R_IRQSTR_DSP>, -+ <&pd IMX_SC_R_SAI_1>, -+ <&pd IMX_SC_R_DMA_2_CH14>, -+ <&pd IMX_SC_R_DMA_2_CH15>, -+ <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>; -+ -+ clock-names = "ipg", "ocram", "core", -+ "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; -+ clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, -+ <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, -+ <&clk_dummy>, <&clk_dummy>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&lsio_mu13 2 0>, -+ <&lsio_mu13 2 1>, -+ <&lsio_mu13 3 0>, -+ <&lsio_mu13 3 1>; -+ memory-region = <&dsp_reserved>; -+ /delete-property/ firmware-name; -+ -+ tplg-name = "sof-imx8-wm8960.tplg"; -+ machine-drv-name = "asoc-simple-card"; -+ -+ status = "okay"; -+}; -+ -+&wm8960 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "disabled"; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&asrc0 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&cs42888 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts -new file mode 100644 -index 000000000..4d688997d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts -@@ -0,0 +1,27 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+#include "imx8qm-mek-rpmsg.dts" -+ -+&pinctrl_usdhc2 { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000021 -+ >; -+}; -+ -+&usdhc2 { -+ pinctrl-assert-gpios = <&lsio_gpio4 8 GPIO_ACTIVE_HIGH>; -+ /delete-property/ cd-gpios; -+ /delete-property/ wp-gpios; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ cap-power-off-card; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts -new file mode 100644 -index 000000000..a44dd8a25 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts -@@ -0,0 +1,53 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+#include "imx8qm-mek-rpmsg.dts" -+ -+/ { -+ reg_usdhc3_vmmc: usdhc3-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD3_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ power-domains = <&pd IMX_SC_R_BOARD_R3>; -+ }; -+}; -+ -+&epdev_on { -+ regulator-always-on; -+}; -+ -+&iomuxc { -+ pinctrl_usdhc3_gpio: usdhc3grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 -+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 -+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 -+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 -+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 -+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 -+ >; -+ }; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; -+ bus-width = <4>; -+ pinctrl-assert-gpios = <&lsio_gpio4 10 GPIO_ACTIVE_HIGH>; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ cap-power-off-card; -+ vmmc-supply = <®_usdhc3_vmmc>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts -new file mode 100755 -index 000000000..be83f4959 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts -@@ -0,0 +1,1892 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qm.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QM MEK"; -+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; -+ -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x40000000>; -+ }; -+ -+ brcmfmac: brcmfmac { -+ compatible = "cypress,brcmfmac"; -+ pinctrl-names = "init", "idle", "default"; -+ pinctrl-0 = <&pinctrl_wifi_init>; -+ pinctrl-1 = <&pinctrl_wifi_init>; -+ pinctrl-2 = <&pinctrl_wifi>; -+ }; -+ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds0 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ lvds_backlight1: lvds_backlight@1 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_lvds1 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_modem_reset>; -+ pinctrl-1 = <&pinctrl_modem_reset_sleep>; -+ reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ cbtl04gp { -+ compatible = "nxp,cbtl04gp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec_mux>; -+ switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; -+ reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ orientation-switch; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ gpu_reserved: gpu_reserved@0x8800000000 { -+ no-map; -+ reg = <0x8 0x80000000 0 0x10000000>; -+ }; -+ -+ decoder_boot: decoder_boot@0x84000000 { -+ no-map; -+ reg = <0 0x84000000 0 0x2000000>; -+ }; -+ encoder_boot: encoder_boot@0x86000000 { -+ no-map; -+ reg = <0 0x86000000 0 0x400000>; -+ }; -+ /* -+ * reserved-memory layout -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ decoder_rpc: decoder_rpc@0x92000000 { -+ no-map; -+ reg = <0 0x92000000 0 0x200000>; -+ }; -+ encoder_rpc: encoder_rpc@0x92200000 { -+ no-map; -+ reg = <0 0x92200000 0 0x200000>; -+ }; -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ encoder_reserved: encoder_reserved@0x94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ -+ }; -+ -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_wlreg_on>; -+ pinctrl-1 = <&pinctrl_wlreg_on_sleep>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&lsio_gpio1 13 0>; -+ enable-active-high; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usb_otg1_vbus: regulator-usbotg1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <4800>; -+ enable-active-high; -+ }; -+ -+ reg_can01_en: regulator-can01-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can01-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can2_en: regulator-can2-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can01_stby: regulator-can01-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can01-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can01_en>; -+ }; -+ -+ reg_can2_stby: regulator-can2-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can2_en>; -+ }; -+ -+ reg_vref_1v8: regulator-adc-vref { -+ compatible = "regulator-fixed"; -+ regulator-name = "vref_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; -+ }; -+ -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai0>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-mek-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ audio-cpu = <&esai0>; -+ audio-codec = <&cs42888>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ status = "okay"; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx8qm-mek-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&wm8960>; -+ hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "AMIC", -+ "RINPUT2", "AMIC", -+ "Mic Jack", "MICB", -+ "AMIC", "MICB"; -+ }; -+ -+ imx8qm_cm40: imx8qm_cm4@0 { -+ compatible = "fsl,imx8qm-cm4"; -+ rsc-da = <0x90000000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&lsio_mu5 0 1 -+ &lsio_mu5 1 1 -+ &lsio_mu5 3 1>; -+ mub-partition = <3>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, -+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; -+ core-index = <0>; -+ core-id = ; -+ status = "okay"; -+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, -+ <&pd IMX_SC_R_M4_0_MU_1A>; -+ }; -+ -+ imx8qm_cm41: imx8x_cm4@1 { -+ compatible = "fsl,imx8qm-cm4"; -+ rsc-da = <0x90100000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&lsio_mu6 0 1 -+ &lsio_mu6 1 1 -+ &lsio_mu6 3 1>; -+ mub-partition = <4>; -+ memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, -+ <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; -+ core-index = <1>; -+ core-id = ; -+ status = "okay"; -+ power-domains = <&pd IMX_SC_R_M4_1_PID0>, -+ <&pd IMX_SC_R_M4_1_MU_1A>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ vdev0vring0: vdev0vring0@90000000 { -+ reg = <0 0x90000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@90008000 { -+ reg = <0 0x90008000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring0: vdev1vring0@90010000 { -+ reg = <0 0x90010000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring1: vdev1vring1@90018000 { -+ reg = <0 0x90018000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table0: rsc_table0@900ff000 { -+ reg = <0 0x900ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90400000 0 0x100000>; -+ no-map; -+ }; -+ -+ vdev2vring0: vdev0vring0@90100000 { -+ reg = <0 0x90100000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev2vring1: vdev0vring1@90108000 { -+ reg = <0 0x90108000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev3vring0: vdev1vring0@90110000 { -+ reg = <0 0x90110000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev3vring1: vdev1vring1@90118000 { -+ reg = <0 0x90118000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table1: rsc_table1@901ff000 { -+ reg = <0 0x901ff000 0 0x1000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&adc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_adc0>; -+ vref-supply = <®_vref_1v8>; -+ status = "okay"; -+}; -+ -+&cm41_i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cm41_i2c>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ status = "okay"; -+ }; -+}; -+ -+&cm41_intmux { -+ status = "okay"; -+}; -+ -+&dc0_pc { -+ status = "okay"; -+}; -+ -+&dc0_prg1 { -+ status = "okay"; -+}; -+ -+&dc0_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc0_prg3 { -+ status = "okay"; -+}; -+ -+&dc0_prg4 { -+ status = "okay"; -+}; -+ -+&dc0_prg5 { -+ status = "okay"; -+}; -+ -+&dc0_prg6 { -+ status = "okay"; -+}; -+ -+&dc0_prg7 { -+ status = "okay"; -+}; -+ -+&dc0_prg8 { -+ status = "okay"; -+}; -+ -+&dc0_prg9 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu1 { -+ status = "okay"; -+}; -+ -+&dsp { -+ compatible = "fsl,imx8qm-hifi4"; -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai0 { -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai0>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ status = "okay"; -+}; -+ -+&sai6 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai6_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai7 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai7_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&pwm_lvds0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds0>; -+ status = "okay"; -+}; -+ -+&i2c1_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1_phy { -+ status = "okay"; -+}; -+ -+&ldb1 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ adv_bridge0: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_0_in: endpoint { -+ remote-endpoint = <&mipi0_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi0_adv_out: endpoint { -+ remote-endpoint = <&adv7535_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ adv_bridge1: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_1_in: endpoint { -+ remote-endpoint = <&mipi1_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi1_adv_out: endpoint { -+ remote-endpoint = <&adv7535_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dc1_pc { -+ status = "okay"; -+}; -+ -+&dc1_prg1 { -+ status = "okay"; -+}; -+ -+&dc1_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc1_prg3 { -+ status = "okay"; -+}; -+ -+&dc1_prg4 { -+ status = "okay"; -+}; -+ -+&dc1_prg5 { -+ status = "okay"; -+}; -+ -+&dc1_prg6 { -+ status = "okay"; -+}; -+ -+&dc1_prg7 { -+ status = "okay"; -+}; -+ -+&dc1_prg8 { -+ status = "okay"; -+}; -+ -+&dc1_prg9 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc1_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc1_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu2 { -+ status = "okay"; -+}; -+ -+&pwm_lvds1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_lvds1>; -+ status = "okay"; -+}; -+ -+&i2c1_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_1_in: endpoint { -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "okay"; -+}; -+ -+&ldb2 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&lpspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; -+ cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <30000000>; -+ }; -+}; -+ -+&emvsim0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sim0>; -+ status = "okay"; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&lpuart2 { /* Dbg console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ status = "disabled"; -+}; -+ -+&lpuart3 { /* MKbus */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can01_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can01_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can2_stby>; -+ status = "okay"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac1>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ nxp,fspi-dll-slvdly = <4>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <8>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&pciea{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ epdev_on-supply = <&epdev_on>; -+ status = "okay"; -+}; -+ -+&pcieb{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -+ -+&sata { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sata>; -+ clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ vbus-supply = <®_usb_otg1_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&usbotg3 { -+ status = "okay"; -+}; -+ -+&usbotg3_cdns3 { -+ dr_mode = "otg"; -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ usb3_drd_sw: endpoint { -+ remote-endpoint = <&typec_dr_sw>; -+ }; -+ }; -+}; -+ -+&usdhc1 { -+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <400000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0>; -+ status = "okay"; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <11 2>; -+ }; -+ -+ fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ interrupt-open-drain; -+ }; -+ -+ fxas2100x@20 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x20>; -+ interrupt-open-drain; -+ }; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ interrupt-open-drain; -+ }; -+ -+ ptn5110: tcpc@51 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x51>; -+ interrupt-parent = <&lsio_gpio4>; -+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port { -+ typec_dr_sw: endpoint { -+ remote-endpoint = <&usb3_drd_sw>; -+ }; -+ }; -+ -+ usb_con1: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "source"; -+ data-role = "dual"; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ pinctrl-1 = <&pinctrl_i2c1_gpio>; -+ scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; -+ sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_2 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_3 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_4 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_5 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_6 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_7 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer_csi0 { -+ status = "okay"; -+}; -+ -+&irqsteer_csi1 { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 1 MIPI CSI-2 (CSIS1) */ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&max9286_1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&jpegdec { -+ status = "okay"; -+}; -+ -+&jpegenc { -+ status = "okay"; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "okay"; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi1>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "okay"; -+ port { -+ max9286_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+ -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c -+ IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c -+ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c -+ >; -+ }; -+ -+ pinctrl_cm41_i2c: cm41i2cgrp { -+ fsl,pins = < -+ IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c -+ IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c -+ >; -+ }; -+ -+ pinctrl_adc0: adc0grp { -+ fsl,pins = < -+ IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 -+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 -+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 -+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 -+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 -+ IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 -+ IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 -+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 -+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 -+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 -+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c0: i2c0grp { -+ fsl,pins = < -+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 -+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c -+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c -+ >; -+ }; -+ -+ pinctrl_i2c1_gpio: i2c1grp-gpio { -+ fsl,pins = < -+ IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c -+ IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lpspi2: lpspi2grp { -+ fsl,pins = < -+ IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 -+ IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 -+ IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 -+ >; -+ }; -+ -+ pinctrl_lpspi2_cs: lpspi2cs { -+ fsl,pins = < -+ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 -+ >; -+ }; -+ -+ pinctrl_sim0: sim0grp { -+ fsl,pins = < -+ IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 -+ IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 -+ IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 -+ IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 -+ IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 -+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 -+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 -+ IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 -+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_pwm_lvds0: pwmlvds0grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_pwm_lvds1: pwmlvds1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_modem_reset: modemresetgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 -+ >; -+ }; -+ -+ pinctrl_modem_reset_sleep: modemreset_sleepgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 -+ >; -+ }; -+ -+ pinctrl_pciea: pcieagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 -+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 -+ IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 -+ >; -+ }; -+ -+ pinctrl_pcieb: pciebgrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 -+ IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 -+ >; -+ }; -+ -+ pinctrl_sata: satagrp{ -+ fsl,pins = < -+ IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 -+ >; -+ }; -+ -+ pinctrl_sai0: sai0grp { -+ fsl,pins = < -+ IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c -+ IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c -+ IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c -+ IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 -+ IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 -+ IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 -+ IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 -+ >; -+ }; -+ -+ pinctrl_typec: typecgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 -+ >; -+ }; -+ -+ pinctrl_typec_mux: typecmuxgrp { -+ fsl,pins = < -+ IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 -+ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 -+ IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 -+ IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 -+ IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0: mipi_csi0 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 -+ IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 -+ IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_mipi_csi1: mipi_csi1 { -+ fsl,pins = < -+ IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 -+ IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 -+ IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c -+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c -+ >; -+ }; -+ -+ pinctrl_wifi: wifigrp{ -+ fsl,pins = < -+ IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 -+ >; -+ }; -+ -+ pinctrl_wifi_init: wifi_initgrp{ -+ fsl,pins = < -+ /* reserve pin init/idle_state to support multiple wlan cards */ -+ >; -+ }; -+ -+ pinctrl_wlreg_on: wlregongrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 -+ >; -+ }; -+ -+ pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ -+ fsl,pins = < -+ IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 -+ >; -+ }; -+ -+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 -+ >; -+ }; -+ -+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { -+ fsl,pins = < -+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 -+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 -+ IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 -+ >; -+ }; -+ -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&gpu_3d0{ -+ status = "okay"; -+}; -+ -+&gpu_3d1{ -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ memory-region=<&gpu_reserved>; -+ status = "okay"; -+}; -+ -+&mu_m0{ -+ interrupts = ; -+}; -+ -+&mu1_m0{ -+ interrupts = ; -+}; -+ -+&mu2_m0{ -+ interrupts = ; -+ status = "okay"; -+}; -+ -+&vpu_decoder { -+ compatible = "nxp,imx8qm-b0-vpudec"; -+ boot-region = <&decoder_boot>; -+ rpc-region = <&decoder_rpc>; -+ reg-csr = <0x2d080000>; -+ core_type = <2>; -+ status = "okay"; -+}; -+ -+&vpu_encoder { -+ compatible = "nxp,imx8qm-b0-vpuenc"; -+ boot-region = <&encoder_boot>; -+ rpc-region = <&encoder_rpc>; -+ reserved-region = <&encoder_reserved>; -+ reg-rpc-system = <0x40000000>; -+ resolution-max = <1920 1920>; -+ fps-max = <120>; -+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>, -+ <&pd IMX_SC_R_VPU>; -+ power-domain-names = "vpuenc1", "vpuenc2", "vpu"; -+ mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx", -+ "enc2_tx0", "enc2_tx1", "enc2_rx"; -+ mboxes = <&mu1_m0 0 0 -+ &mu1_m0 0 1 -+ &mu1_m0 1 0 -+ &mu2_m0 0 0 -+ &mu2_m0 0 1 -+ &mu2_m0 1 0>; -+ status = "okay"; -+ -+ vpu_enc_core0: core0@1020000 { -+ compatible = "fsl,imx8-mu1-vpu-m0"; -+ reg = <0x1020000 0x20000>; -+ reg-csr = <0x1090000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <17>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+ -+ vpu_enc_core1: core1@1040000 { -+ compatible = "fsl,imx8-mu2-vpu-m0"; -+ reg = <0x1040000 0x20000>; -+ reg-csr = <0x10A0000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <18>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts -new file mode 100644 -index 000000000..22738c546 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qm-mek.dts" -+ -+/* -+ * Add the PCIeA x2 lanes and PCIeB x1 lane usecase -+ * hsio-cfg = -+ * NOTE: In this case, the HSIO nodes contained -+ * hsio-cfg = would be re-configured. -+ */ -+&pciea{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pciea>; -+ disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; -+ epdev_on-supply = <&epdev_on>; -+ num-lanes = <2>; -+ clocks = <&pciea_lpcg 0>, -+ <&pciea_lpcg 1>, -+ <&pciea_lpcg 2>, -+ <&phyx2_lpcg 0>, -+ <&phyx2_crr0_lpcg 0>, -+ <&pciea_crr2_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "phy_per","pcie_per", "misc_per"; -+ hsio-cfg = ; -+ status = "okay"; -+}; -+ -+&pcieb{ -+ ext_osc = <1>; -+ clocks = <&pcieb_lpcg 0>, -+ <&pcieb_lpcg 1>, -+ <&pcieb_lpcg 2>, -+ <&phyx1_lpcg 0>, -+ <&phyx2_lpcg 0>, -+ <&phyx1_crr1_lpcg 0>, -+ <&pcieb_crr3_lpcg 0>, -+ <&pciea_crr2_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "pcie_phy_pclk", "phy_per", -+ "pcie_per", "pciex2_per", "misc_per"; -+ power-domains = <&pd IMX_SC_R_PCIE_B>, -+ <&pd IMX_SC_R_PCIE_A>, -+ <&pd IMX_SC_R_SERDES_0>, -+ <&pd IMX_SC_R_SERDES_1>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ power-domain-names = "pcie", "pcie_per", "pcie_phy", -+ "pcie_serdes", "hsio_gpio"; -+ hsio-cfg = ; -+ status = "okay"; -+}; -+ -+&sata { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi -new file mode 100644 -index 000000000..bdf0166fc ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi -@@ -0,0 +1,462 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+/delete-node/ &acm; -+/delete-node/ &sai4; -+/delete-node/ &sai5; -+/delete-node/ &sai4_lpcg; -+/delete-node/ &sai5_lpcg; -+ -+/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ -+&edma0{ -+ reg = <0x591f0000 0x10000>, -+ <0x59200000 0x10000>, /* asrc0 */ -+ <0x59210000 0x10000>, -+ <0x59220000 0x10000>, -+ <0x59230000 0x10000>, -+ <0x59240000 0x10000>, -+ <0x59250000 0x10000>, -+ <0x59260000 0x10000>, /* esai0 rx */ -+ <0x59270000 0x10000>, /* esai0 tx */ -+ <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592A0000 0x10000>, /* spdif1 rx */ -+ <0x592B0000 0x10000>, /* spdif1 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x592e0000 0x10000>, /* sai1 rx */ -+ <0x592f0000 0x10000>, /* sai1 tx */ -+ <0x59300000 0x10000>, /* sai2 rx */ -+ <0x59310000 0x10000>, /* sai3 rx */ -+ <0x59320000 0x10000>, /* sai4 rx */ -+ <0x59330000 0x10000>; /* sai5 tx */ -+ dma-channels = <20>; -+ interrupts = , /* asrc0 */ -+ , -+ , -+ , -+ , -+ , -+ , /* esai0 */ -+ , -+ , /* spdif0 */ -+ , -+ , /* spdif1 */ -+ , -+ , /* sai0 */ -+ , -+ , /* sai1 */ -+ , -+ , /* sai2 */ -+ , /* sai3 */ -+ , /* sai4 */ -+ ; /* sai5 */ -+ interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ -+ "edma2-chan2-rx", "edma2-chan3-tx", -+ "edma2-chan4-tx", "edma2-chan5-tx", -+ "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ -+ "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ -+ "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ -+ "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ -+ "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ -+ "edma2-chan16-rx", "edma2-chan17-tx", /* sai2, dai3 */ -+ "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ -+ power-domains = <&pd IMX_SC_R_DMA_2_CH0>, -+ <&pd IMX_SC_R_DMA_2_CH1>, -+ <&pd IMX_SC_R_DMA_2_CH2>, -+ <&pd IMX_SC_R_DMA_2_CH3>, -+ <&pd IMX_SC_R_DMA_2_CH4>, -+ <&pd IMX_SC_R_DMA_2_CH5>, -+ <&pd IMX_SC_R_DMA_2_CH6>, -+ <&pd IMX_SC_R_DMA_2_CH7>, -+ <&pd IMX_SC_R_DMA_2_CH8>, -+ <&pd IMX_SC_R_DMA_2_CH9>, -+ <&pd IMX_SC_R_DMA_2_CH10>, -+ <&pd IMX_SC_R_DMA_2_CH11>, -+ <&pd IMX_SC_R_DMA_2_CH12>, -+ <&pd IMX_SC_R_DMA_2_CH13>, -+ <&pd IMX_SC_R_DMA_2_CH14>, -+ <&pd IMX_SC_R_DMA_2_CH15>, -+ <&pd IMX_SC_R_DMA_2_CH16>, -+ <&pd IMX_SC_R_DMA_2_CH17>, -+ <&pd IMX_SC_R_DMA_2_CH18>, -+ <&pd IMX_SC_R_DMA_2_CH19>; -+ power-domain-names = "edma2-chan0", "edma2-chan1", -+ "edma2-chan2", "edma2-chan3", -+ "edma2-chan4", "edma2-chan5", -+ "edma2-chan6", "edma2-chan7", -+ "edma2-chan8", "edma2-chan9", -+ "edma2-chan10", "edma2-chan11", -+ "edma2-chan12", "edma2-chan13", -+ "edma2-chan14", "edma2-chan15", -+ "edma2-chan16", "edma2-chan17", -+ "edma2-chan18", "edma2-chan19"; -+}; -+ -+/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ -+&edma1{ -+ reg = <0x599F0000 0x10000>, -+ <0x59A00000 0x10000>, /* asrc1 */ -+ <0x59A10000 0x10000>, -+ <0x59A20000 0x10000>, -+ <0x59A30000 0x10000>, -+ <0x59A40000 0x10000>, -+ <0x59A50000 0x10000>, -+ <0x59A80000 0x10000>, /* sai6 rx */ -+ <0x59A90000 0x10000>, /* sai6 tx */ -+ <0x59AA0000 0x10000>; /* sai7 tx */ -+ dma-channels = <9>; -+ interrupts = , /* asrc1 */ -+ , -+ , -+ , -+ , -+ , -+ , /* sai6 */ -+ , -+ ; /* sai7 */ -+ interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ -+ "edma3-chan2-rx", "edma3-chan3-tx", -+ "edma3-chan4-tx", "edma3-chan5-tx", -+ "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ -+ "edma3-chan10-tx"; /* sai7 */ -+ power-domains = <&pd IMX_SC_R_DMA_3_CH0>, -+ <&pd IMX_SC_R_DMA_3_CH1>, -+ <&pd IMX_SC_R_DMA_3_CH2>, -+ <&pd IMX_SC_R_DMA_3_CH3>, -+ <&pd IMX_SC_R_DMA_3_CH4>, -+ <&pd IMX_SC_R_DMA_3_CH5>, -+ <&pd IMX_SC_R_DMA_3_CH8>, -+ <&pd IMX_SC_R_DMA_3_CH9>, -+ <&pd IMX_SC_R_DMA_3_CH10>; -+ power-domain-names = "edma3-chan0", "edma3-chan1", -+ "edma3-chan2", "edma3-chan3", -+ "edma3-chan4", "edma3-chan5", -+ "edma3-chan8", "edma3-chan9", -+ "edma3-chan10"; -+}; -+ -+&asrc0 { -+ clocks = <&asrc0_lpcg 0>, -+ <&asrc0_lpcg 1>, -+ <&aud_pll_div0_lpcg 0>, -+ <&aud_pll_div1_lpcg 0>, -+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, -+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ power-domains = <&pd IMX_SC_R_ASRC_0>; -+}; -+ -+&esai0 { -+ power-domains = <&pd IMX_SC_R_ESAI_0>; -+}; -+ -+&spdif0 { -+ power-domains = <&pd IMX_SC_R_SPDIF_0>; -+}; -+ -+&spdif1 { -+ power-domains = <&pd IMX_SC_R_SPDIF_1>; -+}; -+ -+&sai0 { -+ power-domains = <&pd IMX_SC_R_SAI_0>; -+}; -+ -+&sai1 { -+ power-domains = <&pd IMX_SC_R_SAI_1>; -+}; -+ -+&sai2 { -+ power-domains = <&pd IMX_SC_R_SAI_2>; -+}; -+ -+&sai3 { -+ power-domains = <&pd IMX_SC_R_SAI_3>; -+}; -+ -+&asrc1 { -+ clocks = <&asrc1_lpcg 0>, -+ <&asrc1_lpcg 1>, -+ <&aud_pll_div0_lpcg 0>, -+ <&aud_pll_div1_lpcg 0>, -+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, -+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ power-domains = <&pd IMX_SC_R_ASRC_1>; -+}; -+ -+&amix { -+ dais = <&sai6>, <&sai7>; -+}; -+ -+&asrc0_lpcg { -+ clocks = <&audio_ipg_clk>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 8>; -+ clock-output-names = "asrc0_lpcg_ipg_clk", -+ "asrc0_lpcg_mem_clk"; -+}; -+ -+&esai0_lpcg { -+ bit-offset = <16 0>; -+ clock-output-names = "esai0_lpcg_extal_clk", -+ "esai0_lpcg_ipg_clk"; -+}; -+ -+&spdif0_lpcg { -+ bit-offset = <20 16>; -+ clock-output-names = "spdif0_lpcg_tx_clk", -+ "spdif0_lpcg_gclkw"; -+}; -+ -+&spdif1_lpcg { -+ bit-offset = <20 16>; -+ clock-output-names = "spdif1_lpcg_tx_clk", -+ "spdif1_lpcg_gclkw"; -+}; -+ -+&sai0_lpcg { -+ bit-offset = <16 0>; -+ clock-output-names = "sai0_lpcg_mclk", -+ "sai0_lpcg_ipg_clk"; -+}; -+ -+&sai1_lpcg { -+ bit-offset = <16 0>; -+ clock-output-names = "sai1_lpcg_mclk", -+ "sai1_lpcg_ipg_clk"; -+}; -+ -+&sai2_lpcg { -+ bit-offset = <16 0>; -+ clock-output-names = "sai2_lpcg_mclk", -+ "sai2_lpcg_ipg_clk"; -+}; -+ -+&sai3_lpcg { -+ bit-offset = <16 0>; -+ clock-output-names = "sai3_lpcg_mclk", -+ "sai3_lpcg_ipg_clk"; -+}; -+ -+&asrc1_lpcg { -+ clocks = <&audio_ipg_clk>, -+ <&audio_ipg_clk>; -+ bit-offset = <0 8>; -+ clock-output-names = "asrc1_lpcg_ipg_clk", -+ "asrc1_lpcg_mem_clk"; -+}; -+ -+&mqs0_lpcg { -+ bit-offset = <16 0>; -+ clock-output-names = "mqs0_lpcg_mclk", -+ "mqs0_lpcg_ipg_clk"; -+}; -+ -+&dsp_lpcg { -+ status = "disabled"; -+}; -+ -+&dsp_ram_lpcg { -+ status = "disabled"; -+}; -+ -+&audio_subsys { -+ acm: acm@59e00000 { -+ compatible = "nxp,imx8qm-acm"; -+ reg = <0x59e00000 0x1D0000>; -+ #clock-cells = <1>; -+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_MCLK_OUT_0>, -+ <&pd IMX_SC_R_MCLK_OUT_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>, -+ <&pd IMX_SC_R_ASRC_0>, -+ <&pd IMX_SC_R_ASRC_1>, -+ <&pd IMX_SC_R_ESAI_0>, -+ <&pd IMX_SC_R_ESAI_1>, -+ <&pd IMX_SC_R_SAI_0>, -+ <&pd IMX_SC_R_SAI_1>, -+ <&pd IMX_SC_R_SAI_2>, -+ <&pd IMX_SC_R_SAI_3>, -+ <&pd IMX_SC_R_SAI_4>, -+ <&pd IMX_SC_R_SAI_5>, -+ <&pd IMX_SC_R_SAI_6>, -+ <&pd IMX_SC_R_SAI_7>, -+ <&pd IMX_SC_R_SPDIF_0>, -+ <&pd IMX_SC_R_SPDIF_1>, -+ <&pd IMX_SC_R_MQS_0>; -+ }; -+ -+ sai4: sai@59080000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59080000 0x10000>; -+ interrupts = ; -+ clocks = <&sai4_lpcg 1>, -+ <&clk_dummy>, -+ <&sai4_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx"; -+ dmas = <&edma0 18 0 1>; -+ fsl,dataline = <0 0xf 0x0>; -+ power-domains = <&pd IMX_SC_R_SAI_4>; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@59090000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59090000 0x10000>; -+ interrupts = ; -+ clocks = <&sai5_lpcg 1>, -+ <&clk_dummy>, -+ <&sai5_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx"; -+ dmas = <&edma0 19 0 0>; -+ fsl,dataline = <0 0x0 0xf>; -+ power-domains = <&pd IMX_SC_R_SAI_5>; -+ status = "disabled"; -+ }; -+ -+ esai1: esai@59810000 { -+ compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; -+ reg = <0x59810000 0x10000>; -+ interrupts = ; -+ clocks = <&esai1_lpcg 1>, -+ <&esai1_lpcg 0>, -+ <&esai1_lpcg 1>, -+ <&clk_dummy>; -+ clock-names = "core", "extal", "fsys", "spba"; -+ dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd IMX_SC_R_ESAI_1>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@59820000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59820000 0x10000>; -+ interrupts = ; -+ clocks = <&sai6_lpcg 1>, -+ <&clk_dummy>, -+ <&sai6_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "rx", "tx"; -+ dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; -+ power-domains = <&pd IMX_SC_R_SAI_6>; -+ status = "disabled"; -+ }; -+ -+ sai7: sai@59830000 { -+ compatible = "fsl,imx8qm-sai"; -+ reg = <0x59830000 0x10000>; -+ interrupts = ; -+ clocks = <&sai7_lpcg 1>, -+ <&clk_dummy>, -+ <&sai7_lpcg 0>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx"; -+ dmas = <&edma1 10 0 0>; -+ power-domains = <&pd IMX_SC_R_SAI_7>; -+ status = "disabled"; -+ }; -+ -+ sai4_lpcg: clock-controller@59480000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59480000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <16 0>; -+ clock-output-names = "sai4_lpcg_mclk", -+ "sai4_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_4>; -+ status = "disabled"; -+ }; -+ -+ sai5_lpcg: clock-controller@59490000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59490000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <16 0>; -+ clock-output-names = "sai5_lpcg_mclk", -+ "sai5_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_5>; -+ status = "disabled"; -+ }; -+ -+ esai1_lpcg: clock-controller@59c10000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c10000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <16 0>; -+ clock-output-names = "esai1_lpcg_extal_clk", -+ "esai1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_ESAI_1>; -+ }; -+ -+ sai6_lpcg: clock-controller@59c20000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c20000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <16 0>; -+ clock-output-names = "sai6_lpcg_mclk", -+ "sai6_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_6>; -+ }; -+ -+ sai7_lpcg: clock-controller@59c30000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x59c30000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, -+ <&audio_ipg_clk>; -+ bit-offset = <16 0>; -+ clock-output-names = "sai7_lpcg_mclk", -+ "sai7_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_SAI_7>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi -new file mode 100644 -index 000000000..d50856d38 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi -@@ -0,0 +1,73 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+&conn_subsys { -+ usbh1: usb@5b0e0000 { -+ compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", -+ "fsl,imx27-usb"; -+ reg = <0x5b0e0000 0x200>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ phy_type = "hsic"; -+ dr_mode = "host"; -+ fsl,usbphy = <&usbphynop2>; -+ fsl,usbmisc = <&usbmisc2 0>; -+ clocks = <&usb2_lpcg 0>; -+ ahb-burst-config = <0x0>; -+ tx-burst-size-dword = <0x10>; -+ rx-burst-size-dword = <0x10>; -+ #stream-id-cells = <1>; -+ power-domains = <&pd IMX_SC_R_USB_1>; -+ status = "disabled"; -+ }; -+ -+ usbmisc2: usbmisc@5b0e0200 { -+ #index-cells = <1>; -+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; -+ reg = <0x5b0e0200 0x200>; -+ }; -+ -+ usbphynop2: usbphynop2 { -+ compatible = "usb-nop-xceiv"; -+ clocks = <&usb2_lpcg 1>; -+ clock-names = "main_clk"; -+ power-domains = <&pd IMX_SC_R_USB_0_PHY>; -+ status = "disabled"; -+ }; -+}; -+ -+&fec1 { -+ compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; -+ iommus = <&smmu 0x12 0x7f80>; -+}; -+ -+&fec2 { -+ compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; -+ iommus = <&smmu 0x12 0x7f80>; -+}; -+ -+&usdhc1 { -+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; -+ iommus = <&smmu 0x11 0x7f80>; -+}; -+ -+&usdhc2 { -+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; -+ iommus = <&smmu 0x11 0x7f80>; -+}; -+ -+&usdhc3 { -+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; -+ iommus = <&smmu 0x11 0x7f80>; -+}; -+ -+&usbotg3 { -+ iommus = <&smmu 0x4 0x7f80>; -+}; -+ -+&usbotg3_cdns3 { -+ iommus = <&smmu 0x4 0x7f80>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi -new file mode 100644 -index 000000000..e0c93f2ae ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+&dpu1 { -+ compatible = "fsl,imx8qm-dpu"; -+ -+ dpu1_disp0: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ dpu1_disp0_hdmi: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&hdmi_disp>; -+ }; -+ -+ dpu1_disp0_mipi0: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&mipi0_dsi_in>; -+ }; -+ }; -+ -+ dpu1_disp1: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ -+ dpu1_disp1_ldb1_ch0: endpoint@0 { -+ remote-endpoint = <&ldb1_ch0>; -+ }; -+ -+ dpu1_disp1_ldb1_ch1: endpoint@1 { -+ remote-endpoint = <&ldb1_ch1>; -+ }; -+ }; -+}; -+ -+&dpu2 { -+ compatible = "fsl,imx8qm-dpu"; -+ -+ dpu2_disp0: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ dpu2_disp0_mipi1: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&mipi1_dsi_in>; -+ }; -+ -+ }; -+ -+ dpu2_disp1: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ -+ dpu2_disp1_ldb2_ch0: endpoint@0 { -+ remote-endpoint = <&ldb2_ch0>; -+ }; -+ -+ dpu2_disp1_ldb2_ch1: endpoint@1 { -+ remote-endpoint = <&ldb2_ch1>; -+ }; -+ }; -+}; -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&dpu1_disp0>, <&dpu1_disp1>, -+ <&dpu2_disp0>, <&dpu2_disp1>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi -new file mode 100644 -index 000000000..e47b12a76 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+&ddr_subsys { -+ ddr_pmu1: ddr-pmu@5c120000 { -+ compatible = "fsl,imx8-ddr-pmu"; -+ reg = <0x5c120000 0x10000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+}; -+ -+&ddr_pmu0 { -+ interrupts = ; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi -new file mode 100644 -index 000000000..2925d6195 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi -@@ -0,0 +1,228 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Dong Aisheng -+ */ -+ -+&dma_subsys { -+ lpuart4: serial@5a0a0000 { -+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; -+ reg = <0x5a0a0000 0x1000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>; -+ clock-names = "ipg", "baud"; -+ assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd IMX_SC_R_UART_4>; -+ power-domain-names = "uart"; -+ dma-names = "tx","rx"; -+ dmas = <&edma2 21 0 0>, -+ <&edma2 20 0 1>; -+ status = "disabled"; -+ }; -+ -+ uart4_lpcg: clock-controller@5a4a0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5a4a0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "uart4_lpcg_baud_clk", -+ "uart4_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_UART_4>; -+ }; -+ -+ i2c4: i2c@5a840000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x5a840000 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&i2c4_lpcg 0>, -+ <&i2c4_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_I2C_4>; -+ status = "disabled"; -+ }; -+ -+ i2c4_lpcg: clock-controller@5ac40000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ac40000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "i2c4_lpcg_clk", -+ "i2c4_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_I2C_4>; -+ }; -+ -+ can1_lpcg: clock-controller@5ace0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5ace0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>, <&dma_ipg_clk>; -+ bit-offset = <0 16 20>; -+ clock-output-names = "can1_lpcg_pe_clk", -+ "can1_lpcg_ipg_clk", -+ "can1_lpcg_chi_clk"; -+ power-domains = <&pd IMX_SC_R_CAN_1>; -+ }; -+ -+ can2_lpcg: clock-controller@5acf0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5acf0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, -+ <&dma_ipg_clk>, <&dma_ipg_clk>; -+ bit-offset = <0 16 20>; -+ clock-output-names = "can2_lpcg_pe_clk", -+ "can2_lpcg_ipg_clk", -+ "can2_lpcg_chi_clk"; -+ power-domains = <&pd IMX_SC_R_CAN_2>; -+ }; -+}; -+ -+&flexcan1 { -+ fsl,clk-source = <1>; -+}; -+ -+&flexcan2 { -+ clocks = <&can1_lpcg 1>, -+ <&can1_lpcg 0>; -+ assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; -+ fsl,clk-source = <1>; -+}; -+ -+&flexcan3 { -+ clocks = <&can2_lpcg 1>, -+ <&can2_lpcg 0>; -+ assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; -+ fsl,clk-source = <1>; -+}; -+ -+&lpspi2 { -+ compatible = "fsl,imx8qm-lpspi", "fsl,imx7ulp-spi"; -+}; -+ -+/* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ -+&edma2 { -+ reg = <0x5a1f0000 0x10000>, -+ <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ -+ <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ -+ <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ -+ <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ -+ <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ -+ <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ -+ <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ -+ <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ -+ <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ -+ <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ -+ <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ -+ <0x5a2f0000 0x10000>, /* channel15 UART1 tx */ -+ <0x5a300000 0x10000>, /* channel16 UART2 rx */ -+ <0x5a310000 0x10000>, /* channel17 UART2 tx */ -+ <0x5a320000 0x10000>, /* channel18 UART3 rx */ -+ <0x5a330000 0x10000>, /* channel19 UART3 tx */ -+ <0x5a340000 0x10000>, /* channel20 UART4 rx */ -+ <0x5a350000 0x10000>; /* channel21 UART4 tx */ -+ #dma-cells = <3>; -+ dma-channels = <18>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", -+ "edma0-chan2-rx", "edma0-chan3-tx", -+ "edma0-chan4-rx", "edma0-chan5-tx", -+ "edma0-chan6-rx", "edma0-chan7-tx", -+ "edma0-chan12-rx", "edma0-chan13-tx", -+ "edma0-chan14-rx", "edma0-chan15-tx", -+ "edma0-chan16-rx", "edma0-chan17-tx", -+ "edma0-chan18-rx", "edma0-chan19-tx", -+ "edma0-chan20-rx", "edma0-chan21-tx"; -+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>, -+ <&pd IMX_SC_R_DMA_0_CH1>, -+ <&pd IMX_SC_R_DMA_0_CH2>, -+ <&pd IMX_SC_R_DMA_0_CH3>, -+ <&pd IMX_SC_R_DMA_0_CH4>, -+ <&pd IMX_SC_R_DMA_0_CH5>, -+ <&pd IMX_SC_R_DMA_0_CH6>, -+ <&pd IMX_SC_R_DMA_0_CH7>, -+ <&pd IMX_SC_R_DMA_0_CH12>, -+ <&pd IMX_SC_R_DMA_0_CH13>, -+ <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>, -+ <&pd IMX_SC_R_DMA_0_CH16>, -+ <&pd IMX_SC_R_DMA_0_CH17>, -+ <&pd IMX_SC_R_DMA_0_CH18>, -+ <&pd IMX_SC_R_DMA_0_CH19>, -+ <&pd IMX_SC_R_DMA_0_CH20>, -+ <&pd IMX_SC_R_DMA_0_CH21>; -+ power-domain-names = "edma0-chan0", "edma0-chan1", -+ "edma0-chan2", "edma0-chan3", -+ "edma0-chan4", "edma0-chan5", -+ "edma0-chan6", "edma0-chan7", -+ "edma0-chan12", "edma0-chan13", -+ "edma0-chan14", "edma0-chan15", -+ "edma0-chan16", "edma0-chan17", -+ "edma0-chan18", "edma0-chan19", -+ "edma0-chan20", "edma0-chan21"; -+ status = "okay"; -+}; -+ -+&lpuart0 { -+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; -+}; -+ -+&lpuart1 { -+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; -+ dmas = <&edma2 15 0 0>, -+ <&edma2 14 0 1>; -+}; -+ -+&lpuart2 { -+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; -+ dmas = <&edma2 17 0 0>, -+ <&edma2 16 0 1>; -+}; -+ -+&lpuart3 { -+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; -+ dmas = <&edma2 19 0 0>, -+ <&edma2 18 0 1>; -+}; -+ -+&i2c0 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&i2c1 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&i2c2 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&i2c3 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi -new file mode 100644 -index 000000000..90b670b15 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+&gpu_3d0 { -+ assigned-clock-rates = <800000000>, <1000000000>; -+ fsl,sc_gpu_pid = ; -+}; -+ -+&gpu1_subsys { -+ imx8_gpu_ss: imx8_gpu1_ss { -+ compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; -+ cores = <&gpu_3d0>, <&gpu_3d1>; -+ reg = <0x80000000 0x80000000>, <0x0 0x10000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+ depth-compression = <0>; -+ /**/ -+ operating-points = < -+ /*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/ -+ 1000000 0 /*The second tuple is for shader clock frequency*/ -+ /*nominal*/ 650000 0 -+ 700000 0 -+ /*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ -+ >; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi -new file mode 100644 -index 000000000..02db56800 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi -@@ -0,0 +1,224 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ * Sandor Yu -+ */ -+ -+#include -+ -+&img_subsys { -+ irqsteer_hdmi_rx: irqsteer@58260000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x58260000 0x1000>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ interrupts = ; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&hdmi_rx_ipg>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_ipg: clock-hdmi-rx-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ clock-output-names = "hdmi_rx_ipg_clk"; -+ }; -+ -+ hdmi_rx_dig_pll: clock-hdmi-rx-dig-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <800000000>; -+ clock-output-names = "hdmi_rx_dig_pll_clk"; -+ }; -+ -+ hdmi_rx_lpcg_gpio_ipg_s: clock-controller@58263000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_ipg>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_gpio_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_pwm_ipg: clock-controller@58263004 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263004 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_lpcg_pwm_ipg_s 0>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_pwm_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_pwm_ipg_s: clock-controller@58263008 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263008 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_ipg>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_lpcg_pwm_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_pwm: clock-controller@5826300c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5826300c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI_RX_PWM_0 IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_pwm_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_i2c0: clock-controller@58263010 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263010 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_lpcg_i2c0_div 0>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_i2c0_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_i2c0_div: clock-controller@58263014 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263014 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI_RX_I2C_0 IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_i2c0_div_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_i2c0_ipg: clock-controller@58263018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_lpcg_i2c0_ipg_s 0>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_i2c0_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_i2c0_ipg_s: clock-controller@5826301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5826301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_ipg>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_i2c0_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_sink_p: clock-controller@58263020 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263020 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_ipg>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_sink_p_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_sink_s: clock-controller@58263024 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263024 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_ipg>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_sink_s_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_hd_core: clock-controller@58263028 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263028 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_hd_core_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_pxl: clock-controller@5826302c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5826302c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_pxl_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ hdmi_rx_lpcg_enc: clock-controller@58263030 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x58263030 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_rx_lpcg_pxl 0>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_rx_lpcg_enc_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ status = "disabled"; -+ }; -+ -+ i2c0_hdmi_rx: i2c@58266000 { -+ compatible = "fsl,imx8qm-lpi2c"; -+ reg = <0x58266000 0x1000>; -+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_hdmi_rx>; -+ clocks = <&hdmi_rx_lpcg_i2c0>, -+ <&hdmi_rx_lpcg_i2c0_ipg>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_HDMI_RX_I2C_0 IMX_SC_PM_CLK_MISC2>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; -+ status = "disabled"; -+ }; -+}; -+ -+&cameradev { -+ hdmi_rx: hdmi_rx@58268000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "cdn,imx8qm-hdmirx"; -+ reg = <0x58268000 0x10000>, /* HDP Controller */ -+ <0x58261000 0x1000>; /* HDP SubSystem CSR */ -+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, -+ <13 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "plug_in", "plug_out"; -+ interrupt-parent = <&irqsteer_hdmi_rx>; -+ clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC1>, -+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>, -+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC4>, -+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC0>, -+ <&hdmi_rx_lpcg_sink_p 0>, -+ <&hdmi_rx_lpcg_sink_s 0>, -+ <&hdmi_rx_lpcg_enc 0>, -+ <&hdmi_rx_pxl_link_lpcg 0>; -+ clock-names = "ref_clk", -+ "pxl_clk", "i2s_clk", "spdif_clk", -+ "lpcg_pclk", "lpcg_sclk", "lpcg_enc_clk", -+ "lpcg_pxl_link_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_RX>; -+ power-domain-names = "hdmi_rx"; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi -new file mode 100644 -index 000000000..3f0ca0616 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi -@@ -0,0 +1,226 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Sandor Yu -+ */ -+ -+#include -+ -+/ { -+ hdmi_subsys: bus@56260000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x56260000 0x0 0x56260000 0x10000>; -+ -+ irqsteer_hdmi: irqsteer@56260000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x56260000 0x1000>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ interrupts = ; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&hdmi_lpcg_lis_ipg 0>; -+ clock-names = "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ assigned-clock-rates = <800000000>, <84375000>; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_i2c0: clock-controller@56263000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <0 16>; -+ clock-output-names = "hdmi_lpcg_i2c0_clk", -+ "hdmi_lpcg_i2c0_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_lis_ipg: clock-controller@56263004 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263004 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <16>; -+ clock-output-names = "hdmi_lpcg_lis_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_pwm_ipg: clock-controller@56263008 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263008 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <16>; -+ clock-output-names = "hdmi_lpcg_pwm_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_i2s: clock-controller@5626300c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5626300c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_MISC0>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_lpcg_i2s_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI_I2S>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_gpio_ipg: clock-controller@56263010 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263010 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <16>; -+ clock-output-names = "hdmi_lpcg_gpio_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_msi_hclk: clock-controller@56263014 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263014 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_lpcg_msi_hclk_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_pxl: clock-controller@56263018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>; -+ bit-offset = <0>; -+ clock-output-names = "hdmi_lpcg_pxl_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_phy: clock-controller@5626301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5626301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <0 16>; -+ clock-output-names = "hdmi_lpcg_phy_vif_clk", -+ "hdmi_lpcg_phy_pclk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_apb_mux_csr: clock-controller@56263020 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263020 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_lpcg_apb 0>; -+ bit-offset = <16>; -+ clock-output-names = "hdmi_lpcg_apb_mux_csr_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_apb_mux_ctrl: clock-controller@56263024 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263024 0x4>; -+ #clock-cells = <1>; -+ clocks = <&hdmi_lpcg_apb 0>; -+ bit-offset = <16>; -+ clock-output-names = "hdmi_lpcg_apb_mux_ctrl_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ hdmi_lpcg_apb: clock-controller@56263028 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56263028 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; -+ bit-offset = <16>; -+ clock-output-names = "hdmi_lpcg_apb_clk"; -+ power-domains = <&pd IMX_SC_R_HDMI>; -+ status = "disabled"; -+ }; -+ -+ i2c0_hdmi: i2c@56266000 { -+ compatible = "fsl,imx8qm-lpi2c"; -+ reg = <0x56266000 0x1000>; -+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_hdmi>; -+ clocks = <&hdmi_lpcg_i2c0 0>, -+ <&hdmi_lpcg_i2c0 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ hdmi:hdmi@56268000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x56268000 0x1000>, -+ <0x56261000 0x1000>; -+ interrupt-parent = <&irqsteer_hdmi>; -+ interrupts = <10>, <13>; -+ interrupt-names = "plug_in", "plug_out"; -+ firmware-name = "hdmitxfw.bin"; -+ status = "disabled"; -+ -+ clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>, -+ <&hdmi_lpcg_phy 1>, -+ <&hdmi_lpcg_msi_hclk 0>, -+ <&hdmi_lpcg_pxl 0>, -+ <&hdmi_lpcg_phy 0>, -+ <&hdmi_lpcg_lis_ipg 0>, -+ <&hdmi_lpcg_apb 0>, -+ <&hdmi_lpcg_apb_mux_csr 0>, -+ <&hdmi_lpcg_apb_mux_ctrl 0>, -+ <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_BYPASS>, -+ <&hdmi_lpcg_i2s 0>; -+ clock-names = "dig_pll", "av_pll", "clk_ipg", -+ "clk_core", "clk_pxl", "clk_pxl_mux", -+ "clk_pxl_link", "lpcg_hdp", "lpcg_msi", -+ "lpcg_pxl", "lpcg_vif", "lpcg_lis", -+ "lpcg_apb", "lpcg_apb_csr", "lpcg_apb_ctrl", -+ "clk_i2s_bypass", "lpcg_i2s"; -+ assigned-clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>; -+ assigned-clock-parents = <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>; -+ power-domains = <&pd IMX_SC_R_HDMI>, -+ <&pd IMX_SC_R_HDMI_PLL_0>, -+ <&pd IMX_SC_R_HDMI_PLL_1>; -+ power-domain-names = "hdmi", "pll0", "pll1"; -+ -+ port@0 { -+ reg = <0>; -+ hdmi_disp: endpoint { -+ remote-endpoint = <&dpu1_disp0_hdmi>; -+ }; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi -new file mode 100644 -index 000000000..09fde1445 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi -@@ -0,0 +1,253 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Richard Zhu -+ */ -+ -+&hsio_subsys { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ pciea_lpcg: clock-controller@5f050000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f050000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; -+ bit-offset = <16 20 24>; -+ clock-output-names = "hsio_pciea_mstr_axi_clk", -+ "hsio_pciea_slv_axi_clk", -+ "hsio_pciea_dbi_axi_clk"; -+ power-domains = <&pd IMX_SC_R_PCIE_A>; -+ }; -+ -+ sata_lpcg: clock-controller@5f070000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f070000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_axi_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_sata_clk"; -+ power-domains = <&pd IMX_SC_R_SATA_0>; -+ }; -+ -+ phyx2_lpcg: clock-controller@5f080000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f080000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_refa_clk>, <&hsio_per_clk>, -+ <&hsio_refa_clk>, <&hsio_per_clk>; -+ bit-offset = <0 4 16 20>; -+ clock-output-names = "hsio_phyx2_pclk_0", -+ "hsio_phyx2_pclk_1", -+ "hsio_phyx2_apbclk_0", -+ "hsio_phyx2_apbclk_1"; -+ power-domains = <&pd IMX_SC_R_SERDES_0>; -+ }; -+ -+ phyx1_lpcg: clock-controller@5f090000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f090000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_refa_clk>, <&hsio_per_clk>, -+ <&hsio_per_clk>, <&hsio_per_clk>; -+ bit-offset = <0 4 8 16>; -+ clock-output-names = "hsio_phyx1_pclk", -+ "hsio_phyx1_epcs_tx_clk", -+ "hsio_phyx1_epcs_rx_clk", -+ "hsio_phyx1_apb_clk"; -+ power-domains = <&pd IMX_SC_R_SERDES_1>; -+ }; -+ -+ phyx2_crr0_lpcg: clock-controller@5f0a0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f0a0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_per_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_phyx2_per_clk"; -+ power-domains = <&pd IMX_SC_R_SERDES_0>; -+ }; -+ -+ pciea_crr2_lpcg: clock-controller@5f0c0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f0c0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_per_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_pciea_per_clk"; -+ power-domains = <&pd IMX_SC_R_PCIE_A>; -+ }; -+ -+ sata_crr4_lpcg: clock-controller@5f0e0000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f0e0000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_per_clk>; -+ bit-offset = <16>; -+ clock-output-names = "hsio_sata_per_clk"; -+ power-domains = <&pd IMX_SC_R_SATA_0>; -+ }; -+ -+ pciea: pcie@0x5f000000 { -+ compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; -+ reg = <0x5f000000 0x10000>, /* Controller reg */ -+ <0x6ff00000 0x80000>, /* PCI cfg space */ -+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ -+ reg-names = "dbi", "config", "hsio"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */ -+ 0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic 0 73 4>, -+ <0 0 0 2 &gic 0 74 4>, -+ <0 0 0 3 &gic 0 75 4>, -+ <0 0 0 4 &gic 0 76 4>; -+ /* -+ * Set these clocks in default, then clocks should be -+ * refined for exact hw design of imx8 pcie. -+ */ -+ clocks = <&pciea_lpcg 0>, -+ <&pciea_lpcg 1>, -+ <&pciea_lpcg 2>, -+ <&phyx2_lpcg 0>, -+ <&phyx2_crr0_lpcg 0>, -+ <&pciea_crr2_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "phy_per", "pcie_per", "misc_per"; -+ power-domains = <&pd IMX_SC_R_PCIE_A>, -+ <&pd IMX_SC_R_SERDES_0>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; -+ fsl,max-link-speed = <3>; -+ hsio-cfg = ; -+ local-addr = <0x40000000>; -+ status = "disabled"; -+ }; -+ -+ pciea_ep: pcie_ep@0x5f000000 { -+ compatible = "fsl,imx8qm-pcie-ep"; -+ reg = <0x5f000000 0x00010000>, -+ <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */ -+ <0x60000000 0x10000000>; -+ reg-names = "regs", "hsio", "addr_space"; -+ num-lanes = <1>; -+ interrupts = ; /* eDMA */ -+ interrupt-names = "dma"; -+ /* -+ * Set these clocks in default, then clocks should be -+ * refined for exact hw design of imx8 pcie. -+ */ -+ clocks = <&pciea_lpcg 0>, -+ <&pciea_lpcg 1>, -+ <&pciea_lpcg 2>, -+ <&phyx2_lpcg 0>, -+ <&phyx2_crr0_lpcg 0>, -+ <&pciea_crr2_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "phy_per", "pcie_per", "misc_per"; -+ power-domains = <&pd IMX_SC_R_PCIE_A>, -+ <&pd IMX_SC_R_SERDES_0>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; -+ fsl,max-link-speed = <3>; -+ hsio-cfg = ; -+ local-addr = <0x40000000>; -+ num-ib-windows = <6>; -+ num-ob-windows = <6>; -+ status = "disabled"; -+ }; -+ -+ pcieb: pcie@0x5f010000 { -+ compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; -+ reg = <0x5f010000 0x10000>, /* Controller reg */ -+ <0x7ff00000 0x80000>, /* PCI cfg space */ -+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ -+ reg-names = "dbi", "config", "hsio"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ -+ 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic 0 105 4>, -+ <0 0 0 2 &gic 0 106 4>, -+ <0 0 0 3 &gic 0 107 4>, -+ <0 0 0 4 &gic 0 108 4>; -+ clocks = <&pcieb_lpcg 0>, -+ <&pcieb_lpcg 1>, -+ <&pcieb_lpcg 2>, -+ <&phyx2_lpcg 1>, -+ <&phyx2_lpcg 0>, -+ <&phyx2_crr0_lpcg 0>, -+ <&pcieb_crr3_lpcg 0>, -+ <&pciea_crr2_lpcg 0>, -+ <&misc_crr5_lpcg 0>; -+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", -+ "pcie_phy", "pcie_phy_pclk", "phy_per", -+ "pcie_per", "pciex2_per", "misc_per"; -+ power-domains = <&pd IMX_SC_R_PCIE_B>, -+ <&pd IMX_SC_R_PCIE_A>, -+ <&pd IMX_SC_R_SERDES_0>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ power-domain-names = "pcie", "pcie_per", "pcie_phy", -+ "hsio_gpio"; -+ fsl,max-link-speed = <3>; -+ hsio-cfg = ; -+ local-addr = <0x80000000>; -+ status = "disabled"; -+ }; -+ -+ sata: sata@5f020000 { -+ compatible = "fsl,imx8qm-ahci"; -+ reg = <0x5f020000 0x10000>, /* Controller reg */ -+ <0x5f1a0000 0x10000>, /* PHY reg */ -+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ -+ reg-names = "ctl", "phy", "hsio"; -+ interrupts = ; -+ clocks = <&sata_lpcg 0>, -+ <&phyx1_lpcg 0>, -+ <&phyx1_lpcg 1>, -+ <&phyx1_lpcg 2>, -+ <&phyx2_crr0_lpcg 0>, -+ <&phyx1_crr1_lpcg 0>, -+ <&pciea_crr2_lpcg 0>, -+ <&pcieb_crr3_lpcg 0>, -+ <&sata_crr4_lpcg 0>, -+ <&misc_crr5_lpcg 0>, -+ <&phyx2_lpcg 0>, -+ <&phyx2_lpcg 1>, -+ <&phyx1_lpcg 3>; -+ clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", -+ "per_clk0", "per_clk1", "per_clk2", -+ "per_clk3", "per_clk4", "per_clk5", -+ "phy_pclk0", "phy_pclk1", "phy_apbclk"; -+ power-domains = <&pd IMX_SC_R_SATA_0>, -+ <&pd IMX_SC_R_PCIE_A>, -+ <&pd IMX_SC_R_PCIE_B>, -+ <&pd IMX_SC_R_SERDES_0>, -+ <&pd IMX_SC_R_SERDES_1>, -+ <&pd IMX_SC_R_HSIO_GPIO>; -+ fsl,sc_rsrc_id = ; -+ iommus = <&smmu 0x13 0x7f80>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi -new file mode 100644 -index 000000000..a1baeeac0 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+&pi0_pxl_lpcg { -+ status = "disabled"; -+}; -+ -+&pi0_ipg_lpcg { -+ status = "disabled"; -+}; -+ -+&pi0_misc_lpcg { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi -new file mode 100644 -index 000000000..6b7843316 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+&lsio_subsys { -+ lsio_mu6: mailbox@5d210000 { -+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+ reg = <0x5d210000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_MU_6A>; -+ }; -+ -+ lsio_mu8: mailbox@5d230000 { -+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+ reg = <0x5d230000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ power-domains = <&pd IMX_SC_R_MU_8A>; -+ status = "disabled"; -+ }; -+ -+ lsio_mu8b: mailbox@5d2c0000 { -+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+ reg = <0x5d2c0000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ fsl,mu-side-b; -+ power-domains = <&pd IMX_SC_R_MU_8B>; -+ status = "disabled"; -+ }; -+ -+}; -+ -+&lsio_gpio0 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio1 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio2 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio3 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio4 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio5 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio6 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio7 { -+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_mu0 { -+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu1 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu2 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu3 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu4 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi -new file mode 100644 -index 000000000..8986f52e5 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi -@@ -0,0 +1,388 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/ { -+ lvds_ipg_clk: clock-lvds-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "lvds_ipg_clk"; -+ }; -+ -+ lvds1_subsys: bus@56240000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x56240000 0x0 0x56240000 0x10000>; -+ -+ lvds0_ipg_clk: clock-lvds-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "lvds0_ipg_clk"; -+ }; -+ -+ lvds0_lis_lpcg: clock-controller@56243000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56243000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&lvds0_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "lvds0_lis_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_0>; -+ }; -+ -+ lvds0_pwm_lpcg: clock-controller@5624300c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5624300c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&lvds0_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lvds0_pwm_lpcg_clk", -+ "lvds0_pwm_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; -+ }; -+ -+ lvds0_i2c0_lpcg: clock-controller@56243010 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56243010 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&lvds0_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lvds0_i2c0_lpcg_clk", -+ "lvds0_i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; -+ }; -+ -+ lvds0_i2c1_lpcg: clock-controller@56243014 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56243014 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&lvds0_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lvds0_i2c1_lpcg_clk", -+ "lvds0_i2c1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; -+ }; -+ -+ irqsteer_lvds0: irqsteer@56240000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x56240000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&lvds0_lis_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_LVDS_0>; -+ }; -+ -+ lvds0_region: lvds_region@56241000 { -+ compatible = "syscon"; -+ reg = <0x56241000 0xf0>; -+ }; -+ -+ ldb1_phy: ldb_phy@56241000 { -+ compatible = "mixel,lvds-phy"; -+ reg = <0x56241000 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; -+ clock-names = "phy"; -+ power-domains = <&pd IMX_SC_R_LVDS_0>; -+ status = "disabled"; -+ -+ ldb1_phy1: port@0 { -+ reg = <0>; -+ #phy-cells = <0>; -+ }; -+ -+ ldb1_phy2: port@1 { -+ reg = <1>; -+ #phy-cells = <0>; -+ }; -+ }; -+ -+ ldb1: ldb@562410e0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qm-ldb"; -+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; -+ clock-names = "pixel", "bypass"; -+ power-domains = <&pd IMX_SC_R_LVDS_0>; -+ gpr = <&lvds0_region>; -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ phys = <&ldb1_phy1>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb1_ch0: endpoint { -+ remote-endpoint = <&dpu1_disp1_ldb1_ch0>; -+ }; -+ }; -+ }; -+ -+ lvds-channel@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ phys = <&ldb1_phy2>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb1_ch1: endpoint { -+ remote-endpoint = <&dpu1_disp1_ldb1_ch1>; -+ }; -+ }; -+ }; -+ }; -+ -+ pwm_lvds0: pwm@56244000 { -+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; -+ reg = <0x56244000 0x1000>; -+ clocks = <&lvds0_pwm_lpcg 0>, -+ <&lvds0_pwm_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ i2c0_lvds0: i2c@56246000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x56246000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_lvds0>; -+ clocks = <&lvds0_i2c0_lpcg 0>, -+ <&lvds0_i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ i2c1_lvds0: i2c@56247000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x56247000 0x1000>; -+ interrupts = <9>; -+ interrupt-parent = <&irqsteer_lvds0>; -+ clocks = <&lvds0_i2c0_lpcg 0>, -+ <&lvds0_i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ lvds2_subsys: bus@57240000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x57240000 0x0 0x57240000 0x10000>; -+ -+ lvds1_ipg_clk: clock-lvds-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "lvds1_ipg_clk"; -+ }; -+ -+ lvds1_lis_lpcg: clock-controller@57243000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57243000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&lvds1_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "lvds1_lis_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_1>; -+ }; -+ -+ lvds1_pwm_lpcg: clock-controller@5724300c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5724300c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&lvds1_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lvds1_pwm_lpcg_clk", -+ "lvds1_pwm_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; -+ }; -+ -+ lvds1_i2c0_lpcg: clock-controller@57243010 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57243010 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&lvds1_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lvds1_i2c0_lpcg_clk", -+ "lvds1_i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; -+ }; -+ -+ lvds1_i2c1_lpcg: clock-controller@57243014 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57243014 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&lvds1_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "lvds1_i2c1_lpcg_clk", -+ "lvds1_i2c1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; -+ }; -+ -+ irqsteer_lvds1: irqsteer@57240000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x57240000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&lvds1_lis_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_LVDS_1>; -+ }; -+ -+ lvds1_region: lvds_region@57241000 { -+ compatible = "syscon"; -+ reg = <0x57241000 0xf0>; -+ }; -+ -+ ldb2_phy: ldb_phy@57241000 { -+ compatible = "mixel,lvds-phy"; -+ reg = <0x57241000 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; -+ clock-names = "phy"; -+ power-domains = <&pd IMX_SC_R_LVDS_1>; -+ status = "disabled"; -+ -+ ldb2_phy1: port@0 { -+ reg = <0>; -+ #phy-cells = <0>; -+ }; -+ -+ ldb2_phy2: port@1 { -+ reg = <1>; -+ #phy-cells = <0>; -+ }; -+ }; -+ -+ ldb2: ldb@572410e0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qm-ldb"; -+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; -+ clock-names = "pixel", "bypass"; -+ power-domains = <&pd IMX_SC_R_LVDS_1>; -+ gpr = <&lvds1_region>; -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ phys = <&ldb2_phy1>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb2_ch0: endpoint { -+ remote-endpoint = <&dpu2_disp1_ldb2_ch0>; -+ }; -+ }; -+ }; -+ -+ lvds-channel@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ phys = <&ldb2_phy2>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb2_ch1: endpoint { -+ remote-endpoint = <&dpu2_disp1_ldb2_ch1>; -+ }; -+ }; -+ }; -+ }; -+ -+ pwm_lvds1: pwm@57244000 { -+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; -+ reg = <0x57244000 0x1000>; -+ clocks = <&lvds1_pwm_lpcg 0>, -+ <&lvds1_pwm_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ i2c0_lvds1: i2c@57246000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x57246000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_lvds1>; -+ clocks = <&lvds1_i2c0_lpcg 0>, -+ <&lvds1_i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ i2c1_lvds1: i2c@57247000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x57247000 0x1000>; -+ interrupts = <9>; -+ interrupt-parent = <&irqsteer_lvds1>; -+ clocks = <&lvds1_i2c0_lpcg 0>, -+ <&lvds1_i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; -+ status = "disabled"; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi -new file mode 100644 -index 000000000..ba166abba ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi -@@ -0,0 +1,352 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/ { -+ dsi_ipg_clk: clock-dsi-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <120000000>; -+ clock-output-names = "dsi_ipg_clk"; -+ }; -+ -+ mipi_pll_div2_clk: clock-mipi-div2-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <432000000>; -+ clock-output-names = "mipi_pll_div2_clk"; -+ }; -+ -+ mipi0_subsys: bus@56220000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x56220000 0x0 0x56220000 0x10000>; -+ -+ mipi0_lis_lpcg: clock-controller@56223000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dsi_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_lis_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ }; -+ -+ mipi0_i2c0_lpcg_clk: clock-controller@5622301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5622301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_i2c0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; -+ }; -+ -+ mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dsi_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; -+ }; -+ -+ mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223014 0x4>; -+ #clock-cells = <1>; -+ clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; -+ }; -+ -+ mipi0_i2c1_lpcg_clk: clock-controller@5622302c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5622302c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_i2c1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; -+ }; -+ -+ mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223028 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dsi_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; -+ }; -+ -+ mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223024 0x4>; -+ #clock-cells = <1>; -+ clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>; -+ bit-offset = <0>; -+ clock-output-names = "mipi0_i2c1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; -+ }; -+ -+ irqsteer_mipi0: irqsteer@56220000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x56220000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&mipi0_lis_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ }; -+ -+ i2c0_mipi0: i2c@56226000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x56226000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_mipi0>; -+ clocks = <&mipi0_i2c0_lpcg_clk 0>, -+ <&mipi0_i2c0_lpcg_ipg_clk 0>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ mipi0_csr: csr@56221000 { -+ compatible = "syscon"; -+ reg = <0x56221000 0x240>; -+ }; -+ -+ mipi0_dphy: dphy@56228300 { -+ compatible = "fsl,imx8qm-mipi-dphy"; -+ reg = <0x56228300 0x100>; -+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; -+ clock-names = "phy_ref"; -+ #phy-cells = <0>; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ status = "disabled"; -+ }; -+ -+ mipi0_dsi_host: dsi_host@56228000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qm-nwl-dsi"; -+ reg = <0x56228000 0x300>; -+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&mipi_pll_div2_clk>; -+ clock-names = "pixel", -+ "bypass", -+ "phy_ref", -+ "tx_esc", -+ "rx_esc", -+ "phy_parent"; -+ interrupts = <16>; -+ interrupt-parent = <&irqsteer_mipi0>; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ phys = <&mipi0_dphy>; -+ phy-names = "dphy"; -+ csr = <&mipi0_csr>; -+ use-disp-ss; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mipi0_in: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg = <0>; -+ mipi0_dsi_in: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&dpu1_disp0_mipi0>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ mipi1_subsys: bus@57220000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x57220000 0x0 0x57220000 0x10000>; -+ -+ mipi1_lis_lpcg: clock-controller@57223000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57223000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dsi_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_lis_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ }; -+ -+ mipi1_i2c0_lpcg_clk: clock-controller@5722301c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5722301c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_i2c0_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; -+ }; -+ -+ mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57223018 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dsi_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; -+ }; -+ -+ mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57223014 0x4>; -+ #clock-cells = <1>; -+ clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; -+ }; -+ -+ mipi1_i2c1_lpcg_clk: clock-controller@5722302c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5722302c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_i2c1_lpcg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; -+ }; -+ -+ mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57223028 0x4>; -+ #clock-cells = <1>; -+ clocks = <&dsi_ipg_clk>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; -+ }; -+ -+ mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x57223024 0x4>; -+ #clock-cells = <1>; -+ clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>; -+ bit-offset = <0>; -+ clock-output-names = "mipi1_i2c1_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; -+ }; -+ -+ irqsteer_mipi1: irqsteer@57220000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x57220000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&mipi1_lis_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ }; -+ -+ i2c0_mipi1: i2c@57226000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x57226000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_mipi1>; -+ clocks = <&mipi1_i2c0_lpcg_clk 0>, -+ <&mipi1_i2c0_lpcg_ipg_clk 0>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ mipi1_csr: csr@57221000 { -+ compatible = "syscon"; -+ reg = <0x57221000 0x240>; -+ }; -+ -+ mipi1_dphy: dphy@57228300 { -+ compatible = "fsl,imx8qm-mipi-dphy"; -+ reg = <0x57228300 0x100>; -+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; -+ clock-names = "phy_ref"; -+ #phy-cells = <0>; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ status = "disabled"; -+ }; -+ -+ mipi1_dsi_host: dsi_host@57228000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qm-nwl-dsi"; -+ reg = <0x57228000 0x300>; -+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&mipi_pll_div2_clk>; -+ clock-names = "pixel", -+ "bypass", -+ "phy_ref", -+ "tx_esc", -+ "rx_esc", -+ "phy_parent"; -+ interrupts = <16>; -+ interrupt-parent = <&irqsteer_mipi1>; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ phys = <&mipi1_dphy>; -+ phy-names = "dphy"; -+ csr = <&mipi1_csr>; -+ use-disp-ss; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mipi1_in: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg = <0>; -+ mipi1_dsi_in: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&dpu2_disp0_mipi1>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi -new file mode 100644 -index 000000000..248952335 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi -@@ -0,0 +1,347 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+&usdhc1 { -+ /delete-property/ iommus; -+}; -+ -+&usdhc2 { -+ /delete-property/ iommus; -+}; -+ -+&usdhc3 { -+ /delete-property/ iommus; -+}; -+ -+&fec1 { -+ /delete-property/ iommus; -+}; -+ -+&fec2 { -+ /delete-property/ iommus; -+}; -+ -+&sata { -+ /delete-property/ iommus; -+}; -+ -+&usbotg3 { -+ /delete-property/ iommus; -+}; -+ -+&usbotg3_cdns3 { -+ /delete-property/ iommus; -+}; -+ -+&smmu { -+ /* xen only supports legacy bindings for now */ -+ #iommu-cells = <0>; -+}; -+ -+&dpu1 { -+ fsl,sc_rsrc_id = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+&dpu2 { -+ fsl,sc_rsrc_id = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ -+&edma0{ -+ fsl,sc_rsrc_id = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+}; -+ -+&edma1 { -+ xen,passthrough; -+}; -+ -+&acm { -+ xen,passthrough; -+}; -+ -+&asrc0 { -+ xen,passthrough; -+}; -+ -+&esai0 { -+ xen,passthrough; -+}; -+ -+&spdif0 { -+ xen,passthrough; -+}; -+ -+&spdif1 { -+ xen,passthrough; -+}; -+ -+&sai0 { -+ xen,passthrough; -+}; -+ -+&sai1 { -+ xen,passthrough; -+}; -+ -+&sai2 { -+ xen,passthrough; -+}; -+ -+&sai3 { -+ xen,passthrough; -+}; -+ -+&asrc1 { -+ xen,passthrough; -+}; -+ -+&amix { -+ xen,passthrough; -+}; -+ -+&asrc0_lpcg { -+ xen,passthrough; -+}; -+ -+&esai0_lpcg { -+ xen,passthrough; -+}; -+ -+&spdif0_lpcg { -+ xen,passthrough; -+}; -+ -+&spdif1_lpcg { -+ xen,passthrough; -+}; -+ -+&sai0_lpcg { -+ xen,passthrough; -+}; -+ -+&sai1_lpcg { -+ xen,passthrough; -+}; -+ -+&sai2_lpcg { -+ xen,passthrough; -+}; -+ -+&sai3_lpcg { -+ xen,passthrough; -+}; -+ -+&asrc1_lpcg { -+ xen,passthrough; -+}; -+ -+&mqs0_lpcg { -+ xen,passthrough; -+}; -+ -+&dsp_lpcg { -+ xen,passthrough; -+}; -+ -+&dsp_ram_lpcg { -+ xen,passthrough; -+}; -+ -+&sai4 { -+ xen,passthrough; -+}; -+ -+&sai5 { -+ xen,passthrough; -+}; -+ -+&esai1 { -+ xen,passthrough; -+}; -+ -+&sai6 { -+ xen,passthrough; -+}; -+ -+&sai7 { -+ xen,passthrough; -+}; -+ -+&sai4_lpcg { -+ xen,passthrough; -+}; -+ -+&sai5_lpcg { -+ xen,passthrough; -+}; -+ -+&esai1_lpcg { -+ xen,passthrough; -+}; -+ -+&sai6_lpcg { -+ xen,passthrough; -+}; -+ -+&sai7_lpcg { -+ xen,passthrough; -+}; -+ -+&amix_lpcg { -+ xen,passthrough; -+}; -+ -+&aud_rec0_lpcg { -+ xen,passthrough; -+}; -+ -+&aud_rec1_lpcg { -+ xen,passthrough; -+}; -+ -+&aud_pll_div0_lpcg { -+ xen,passthrough; -+}; -+ -+&aud_pll_div1_lpcg { -+ xen,passthrough; -+}; -+ -+&mclkout0_lpcg { -+ xen,passthrough; -+}; -+ -+&mclkout1_lpcg { -+ xen,passthrough; -+}; -+ -+/ { -+ -+dma_subsys: bus@5a000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; -+ -+ /* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ -+ edma214: dma-controller@5a2e0000 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x5a1f0000 0x10000>, -+ <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ -+ <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ -+ #dma-cells = <3>; -+ dma-channels = <2>; -+ interrupts = , -+ ; -+ interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; -+ power-domains = <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>; -+ power-domain-names = "edma0-chan14", "edma0-chan15"; -+ status = "okay"; -+ fsl,sc_rsrc_id = , -+ ; -+ }; -+}; -+}; -+ -+&edma2 { -+ reg = <0x5a1f0000 0x10000>, -+ <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ -+ <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ -+ <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ -+ <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ -+ <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ -+ <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ -+ <0x5a300000 0x10000>, /* channel16 UART2 rx */ -+ <0x5a310000 0x10000>, /* channel17 UART2 tx */ -+ <0x5a320000 0x10000>, /* channel18 UART3 rx */ -+ <0x5a330000 0x10000>, /* channel19 UART3 tx */ -+ <0x5a340000 0x10000>, /* channel20 UART4 rx */ -+ <0x5a350000 0x10000>; /* channel21 UART4 tx */ -+ #dma-cells = <3>; -+ dma-channels = <12>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", -+ "edma0-chan6-rx", "edma0-chan7-tx", -+ "edma0-chan12-rx", "edma0-chan13-tx", -+ "edma0-chan16-rx", "edma0-chan17-tx", -+ "edma0-chan18-rx", "edma0-chan19-tx", -+ "edma0-chan20-rx", "edma0-chan21-tx"; -+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>, -+ <&pd IMX_SC_R_DMA_0_CH1>, -+ <&pd IMX_SC_R_DMA_0_CH6>, -+ <&pd IMX_SC_R_DMA_0_CH7>, -+ <&pd IMX_SC_R_DMA_0_CH12>, -+ <&pd IMX_SC_R_DMA_0_CH13>, -+ <&pd IMX_SC_R_DMA_0_CH16>, -+ <&pd IMX_SC_R_DMA_0_CH17>, -+ <&pd IMX_SC_R_DMA_0_CH18>, -+ <&pd IMX_SC_R_DMA_0_CH19>, -+ <&pd IMX_SC_R_DMA_0_CH20>, -+ <&pd IMX_SC_R_DMA_0_CH21>; -+ power-domain-names = "edma0-chan0", "edma0-chan1", -+ "edma0-chan6", "edma0-chan7", -+ "edma0-chan12", "edma0-chan13", -+ "edma0-chan16", "edma0-chan17", -+ "edma0-chan18", "edma0-chan19", -+ "edma0-chan20", "edma0-chan21"; -+ status = "okay"; -+}; -+ -+&lpspi0 { -+}; -+ -+&lpuart1 { -+ dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; -+}; -+ -+&lpuart2 { -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi -new file mode 100755 -index 000000000..cc7b597f9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi -@@ -0,0 +1,528 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ * Dong Aisheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fec1; -+ ethernet1 = &fec2; -+ mmc0 = &usdhc1; -+ mmc1 = &usdhc2; -+ mmc2 = &usdhc3; -+ serial0 = &lpuart0; -+ serial1 = &lpuart1; -+ serial2 = &lpuart2; -+ serial3 = &lpuart3; -+ serial4 = &lpuart4; -+ isi0 = &isi_0; -+ isi1 = &isi_1; -+ isi2 = &isi_2; -+ isi3 = &isi_3; -+ isi4 = &isi_4; -+ isi5 = &isi_5; -+ isi6 = &isi_6; -+ isi7 = &isi_7; -+ csi0 = &mipi_csi_0; -+ csi1 = &mipi_csi_1; -+ mu0 = &lsio_mu0; -+ mu1 = &lsio_mu1; -+ mu2 = &lsio_mu2; -+ mu3 = &lsio_mu3; -+ mu4 = &lsio_mu4; -+ can0 = &flexcan1; -+ can1 = &flexcan2; -+ can2 = &flexcan3; -+ dpu0 = &dpu1; -+ dpu1 = &dpu2; -+ ldb0 = &ldb1; -+ ldb1 = &ldb2; -+ i2c0 = &i2c_rpbus_0; -+ i2c1 = &i2c_rpbus_1; -+ dphy0 = &mipi0_dphy; -+ dphy1 = &mipi1_dphy; -+ mipi_dsi0 = &mipi0_dsi_host; -+ mipi_dsi1 = &mipi1_dsi_host; -+ }; -+ -+ cpus: cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&A53_0>; -+ }; -+ core1 { -+ cpu = <&A53_1>; -+ }; -+ core2 { -+ cpu = <&A53_2>; -+ }; -+ core3 { -+ cpu = <&A53_3>; -+ }; -+ }; -+ -+ cluster1 { -+ core0 { -+ cpu = <&A72_0>; -+ }; -+ core1 { -+ cpu = <&A72_1>; -+ }; -+ }; -+ }; -+ -+ A53_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x0>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x1>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x2>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53", "arm,armv8"; -+ reg = <0x0 0x3>; -+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A72_0: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72", "arm,armv8"; -+ reg = <0x0 0x100>; -+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A72_L2>; -+ operating-points-v2 = <&a72_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A72_1: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72", "arm,armv8"; -+ reg = <0x0 0x101>; -+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; -+ enable-method = "psci"; -+ next-level-cache = <&A72_L2>; -+ operating-points-v2 = <&a72_opp_table>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ -+ A72_L2: l2-cache1 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a53_opp_table: a53-opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <900000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-896000000 { -+ opp-hz = /bits/ 64 <896000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1104000000 { -+ opp-hz = /bits/ 64 <1104000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ a72_opp_table: a72-opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1000000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1296000000 { -+ opp-hz = /bits/ 64 <1296000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ }; -+ -+ opp-1596000000 { -+ opp-hz = /bits/ 64 <1596000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xC0000>, /* GICR */ -+ <0x0 0x52000000 0 0x2000>, /* GICC */ -+ <0x0 0x52010000 0 0x1000>, /* GICH */ -+ <0x0 0x52020000 0 0x20000>; /* GICV */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ smmu: iommu@51400000 { -+ compatible = "arm,mmu-500"; -+ interrupt-parent = <&gic>; -+ reg = <0 0x51400000 0 0x40000>; -+ #global-interrupts = <1>; -+ #iommu-cells = <2>; -+ interrupts = <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, -+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", -+ "rx0", -+ "gip3"; -+ mboxes = <&lsio_mu1 0 0 -+ &lsio_mu1 1 0 -+ &lsio_mu1 3 3>; -+ -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ wakeup-irq = <235 236 237 258 262 267 271 -+ 345 346 347 348>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8qm-iomuxc"; -+ }; -+ -+ ocotp: imx8qm-ocotp { -+ compatible = "fsl,imx8qm-scu-ocotp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ read-only; -+ -+ fec_mac0: mac@1c4 { -+ reg = <0x1c4 6>; -+ }; -+ -+ fec_mac1: mac@1c6 { -+ reg = <0x1c6 6>; -+ }; -+ }; -+ -+ rtc: rtc { -+ compatible = "fsl,imx8qm-sc-rtc"; -+ }; -+ -+ watchdog { -+ compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; -+ timeout-sec = <60>; -+ }; -+ -+ tsens: thermal-sensor { -+ compatible = "fsl,imx-sc-thermal"; -+ tsens-num = <6>; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ secvio: secvio { -+ compatible = "fsl,imx-sc-secvio"; -+ nvmem = <&ocotp>; -+ }; -+ }; -+ -+ thermal_zones: thermal-zones { -+ cpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_A53>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ cpu-thermal1 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_A72>; -+ trips { -+ cpu_alert1: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit1: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert1>; -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; -+ trips { -+ gpu_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ gpu_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu-thermal1 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; -+ trips { -+ gpu_alert1: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ gpu_crit1: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ drc-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_DRC_0>; -+ trips { -+ drc_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ drc_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ -+ sc_pwrkey: sc-powerkey { -+ compatible = "fsl,imx8-pwrkey"; -+ linux,keycode = ; -+ wakeup-source; -+ }; -+ -+ vpu_subsys_dsp: bus@55000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x55000000 0x0 0x55000000 0x1000000>; -+ -+ dsp: dsp@556e8000 { -+ compatible = "fsl,imx8qm-hifi4"; -+ reg = <0x556e8000 0x88000>; -+ clocks = <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>; -+ mbox-names = "tx0", "rx0", "rxdb0"; -+ mboxes = <&lsio_mu13 0 0>, -+ <&lsio_mu13 1 0>, -+ <&lsio_mu13 3 0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ /* sorted in register address */ -+ #include "imx8-ss-security.dtsi" -+ #include "imx8-ss-cm41.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-ddr.dtsi" -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-hsio.dtsi" -+ #include "imx8-ss-img.dtsi" -+ #include "imx8-ss-dc0.dtsi" -+ #include "imx8-ss-dc1.dtsi" -+ #include "imx8-ss-gpu0.dtsi" -+ #include "imx8-ss-gpu1.dtsi" -+ #include "imx8-ss-vpu.dtsi" -+}; -+ -+#include "imx8qm-ss-audio.dtsi" -+#include "imx8qm-ss-dma.dtsi" -+#include "imx8qm-ss-conn.dtsi" -+#include "imx8qm-ss-ddr.dtsi" -+#include "imx8qm-ss-lsio.dtsi" -+#include "imx8qm-ss-hsio.dtsi" -+#include "imx8qm-ss-dc.dtsi" -+#include "imx8qm-ss-lvds.dtsi" -+#include "imx8qm-ss-mipi.dtsi" -+#include "imx8qm-ss-hdmi.dtsi" -+#include "imx8qm-ss-hdmi-rx.dtsi" -+#include "imx8qm-ss-img.dtsi" -+#include "imx8qm-ss-gpu.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts -new file mode 100644 -index 000000000..882b52adc ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qp.dtsi" -+#include "imx8q-val.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QP Validation Board"; -+ compatible = "fsl,imx8qp-val", "fsl,imx8qp", "fsl,imx8qm"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qp.dtsi b/arch/arm64/boot/dts/freescale/imx8qp.dtsi -new file mode 100644 -index 000000000..ab657da22 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qp.dtsi -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8qm.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QP"; -+ compatible = "fsl,imx8qp", "fsl,imx8qm"; -+}; -+ -+&cpus { -+ cpu-map { -+ cluster1 { -+ /delete-node/ core1; -+ }; -+ }; -+ /delete-node/ cpu@101; -+}; -+ -+&gpu_3d0 { -+ assigned-clock-rates = <625000000>, <625000000>; -+}; -+ -+&gpu_3d1 { -+ assigned-clock-rates = <625000000>, <625000000>; -+}; -+ -+&imx8_gpu_ss {/**/ -+ operating-points = < -+ /*nominal*/ 625000 0 -+ 625000 0 -+/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ -+ >; -+}; -+ -+&thermal_zones { -+ cpu-thermal1 { -+ cooling-maps { -+ map0 { -+ cooling-device = -+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts -new file mode 100644 -index 000000000..4587edd5d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts -@@ -0,0 +1,15 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp.dtsi" -+#include "imx8x-17x17-val.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QXP 17x17 Validation Board"; -+ compatible = "fsl,imx8qxp-17x17-val", "fsl,imx8qxp"; -+}; -+ -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts -index a3f8cf195..47bb68823 100644 ---- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts -@@ -13,13 +13,13 @@ / { - compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; - - aliases { -- serial1 = &adma_lpuart1; -- serial2 = &adma_lpuart2; -- serial3 = &adma_lpuart3; -+ serial1 = &lpuart1; -+ serial2 = &lpuart2; -+ serial3 = &lpuart3; - }; - - chosen { -- stdout-path = &adma_lpuart2; -+ stdout-path = &lpuart2; - }; - - memory@80000000 { -@@ -82,7 +82,7 @@ sdio_pwrseq: sdio-pwrseq { - }; - - /* BT */ --&adma_lpuart0 { -+&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - uart-has-rtscts; -@@ -90,21 +90,21 @@ &adma_lpuart0 { - }; - - /* LS-UART0 */ --&adma_lpuart1 { -+&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; - }; - - /* Debug */ --&adma_lpuart2 { -+&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; - status = "okay"; - }; - - /* PCI-E UART */ --&adma_lpuart3 { -+&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>; - status = "okay"; -@@ -133,7 +133,7 @@ ethphy0: ethernet-phy@0 { - &usdhc1 { - #address-cells = <1>; - #size-cells = <0>; -- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; -+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; -@@ -151,7 +151,7 @@ brcmf: wifi@1 { - - /* SD */ - &usdhc2 { -- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; -+ assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi -index c7336f387..144fc9e82 100644 ---- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi -@@ -26,7 +26,7 @@ wakeup { - }; - }; - --&adma_i2c1 { -+&i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ -@@ -37,17 +37,17 @@ rtc_i2c: rtc@68 { - }; - - /* Colibri UART_B */ --&adma_lpuart0 { -+&lpuart0 { - status= "okay"; - }; - - /* Colibri UART_C */ --&adma_lpuart2 { -+&lpuart2 { - status= "okay"; - }; - - /* Colibri UART_A */ --&adma_lpuart3 { -+&lpuart3 { - status= "okay"; - }; - -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi -index f38acff0d..89d70e030 100644 ---- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi -@@ -10,7 +10,7 @@ / { - compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; - - chosen { -- stdout-path = &adma_lpuart3; -+ stdout-path = &lpuart3; - }; - - reg_module_3v3: regulator-module-3v3 { -@@ -22,7 +22,7 @@ reg_module_3v3: regulator-module-3v3 { - }; - - /* On-module I2C */ --&adma_i2c0 { -+&i2c0 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; -@@ -49,7 +49,7 @@ touchscreen@2c { - }; - - /* Colibri I2C */ --&adma_i2c1 { -+&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; -@@ -58,19 +58,19 @@ &adma_i2c1 { - }; - - /* Colibri UART_B */ --&adma_lpuart0 { -+&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - }; - - /* Colibri UART_C */ --&adma_lpuart2 { -+&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; - }; - - /* Colibri UART_A */ --&adma_lpuart3 { -+&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts -new file mode 100644 -index 000000000..98787df35 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-lpddr4-val.dts" -+ -+/ { -+ model = "Freescale i.MX8QXP DDR3L VALIDATION"; -+ compatible = "fsl,imx8qxp-ddr3l-val", "fsl,imx8qxp"; -+ -+ reserved-memory { -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x14000000>; -+ alloc-ranges = <0 0xc0000000 0 0x14000000>; -+ linux,cma-default; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi -new file mode 100644 -index 000000000..d8d5b3719 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi -@@ -0,0 +1,57 @@ -+/* -+ * Copyright 2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+&fec1 { -+ status = "disabled"; -+}; -+ -+&fec2 { -+ pinctrl-0 = <&pinctrl_fec2_rmii>; -+ clocks = <&enet1_lpcg 4>, -+ <&enet1_lpcg 2>, -+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_DISABLE_50>, -+ <&enet1_lpcg 0>, -+ <&enet1_lpcg 1>; -+ phy-mode = "rmii"; -+ phy-handle = <ðphy2>; -+ /delete-property/ phy-supply; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy2: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <2>; -+ tja110x,refclk_in; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_fec2_rmii: fec2rmiigrp { -+ fsl,pins = < -+ IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 -+ IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 -+ IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT 0x06000020 -+ IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 -+ IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 -+ IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x06000020 -+ IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 -+ IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 -+ IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 -+ IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts -new file mode 100644 -index 000000000..74695fd4a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-lpddr4-val.dts" -+ -+&vpu_encoder { -+ status = "disabled"; -+}; -+ -+&vpu_decoder { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts -new file mode 100644 -index 000000000..369c94269 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2017 NXP -+ */ -+ -+#include "imx8qxp-lpddr4-val.dts" -+ -+&iomuxc { -+ pinctrl_gpmi_nand_1: gpmi-nand-1 { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c -+ IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c -+ IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c -+ IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c -+ IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c -+ IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c -+ IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c -+ IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c -+ IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c -+ IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c -+ IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c -+ -+ IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c -+ IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c -+ IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c -+ IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c -+ -+ /* i.MX8QXP NAND use nand_re_dqs_pins */ -+ IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c -+ IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c -+ -+ >; -+ }; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand_1>; -+ status = "okay"; -+ nand-on-flash-bbt; -+}; -+ -+/* Disabled the usdhc1/usdhc2 since pin conflict */ -+&usdhc1 { -+ status = "disabled"; -+}; -+ -+&usdhc2 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts -new file mode 100644 -index 000000000..7bbd5b6d4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2017~2019 NXP -+ */ -+ -+#include "imx8qxp-lpddr4-val-lpspi.dts" -+ -+/delete-node/&spidev0; -+ -+&pinctrl_lpspi2 { -+ fsl,pins = < -+ IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x6000040 -+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x6000040 -+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x6000040 -+ IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x6000040 -+ >; -+}; -+ -+&lpspi2 { -+ #address-cells = <0>; -+ pinctrl-0 = <&pinctrl_lpspi2>; -+ /delete-property/ cs-gpios; -+ spi-slave; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts -new file mode 100644 -index 000000000..c7bfeae30 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2017~2019 NXP -+ */ -+ -+#include "imx8qxp-lpddr4-val.dts" -+ -+&iomuxc { -+ pinctrl_lpspi0: lpspi0grp { -+ fsl,pins = < -+ IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x6000040 -+ IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x6000040 -+ IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x6000040 -+ >; -+ }; -+ -+ pinctrl_lpspi0_cs: lpspi0cs { -+ fsl,pins = < -+ IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x21 -+ >; -+ }; -+ -+ pinctrl_lpspi2: lpspi2grp { -+ fsl,pins = < -+ IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x6000040 -+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x6000040 -+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x6000040 -+ IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x6000040 -+ >; -+ }; -+}; -+ -+&lpspi0 { -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; -+ cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ flash: at45db041e@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "atmel,at45", "atmel,dataflash"; -+ spi-max-frequency = <5000000>; -+ reg = <0>; -+ }; -+}; -+ -+&lpspi2 { -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpspi2>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <10000000>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts -new file mode 100644 -index 000000000..8225ce66c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts -@@ -0,0 +1,60 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qxp-lpddr4-val.dts" -+ -+/ { -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-mqs { -+ compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", -+ "fsl,imx-audio-mqs"; -+ model = "mqs-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&mqs>; -+ audio-asrc = <&asrc1>; -+ }; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl_mqs: mqsgrp { -+ fsl,pins = < -+ IMX8QXP_SPDIF0_TX_ADMA_MQS_L 0xc6000061 -+ IMX8QXP_SPDIF0_RX_ADMA_MQS_R 0xc6000061 -+ >; -+ }; -+}; -+ -+&mqs { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mqs>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts -new file mode 100644 -index 000000000..81ec0d0e9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qxp-lpddr4-val.dts" -+ -+/ { -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif0>; -+ spdif-in; -+ spdif-out; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_spdif0: spdif0grp { -+ fsl,pins = < -+ IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 -+ IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 -+ >; -+ }; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&spdif0 { -+ compatible = "fsl,imx8qm-spdif"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&spdif0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts -new file mode 100755 -index 000000000..1380a14b4 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts -@@ -0,0 +1,534 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2017~2018 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "imx8qxp.dtsi" -+ -+/ { -+ model = "Freescale i.MX8QXP LPDDR4 Validation Board"; -+ compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp"; -+ -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ -+ decoder_boot: decoder-boot@84000000 { -+ reg = <0 0x84000000 0 0x2000000>; -+ no-map; -+ }; -+ -+ encoder_boot: encoder-boot@86000000 { -+ reg = <0 0x86000000 0 0x200000>; -+ no-map; -+ }; -+ -+ decoder_rpc: decoder-rpc@0x92000000 { -+ reg = <0 0x92000000 0 0x200000>; -+ no-map; -+ }; -+ -+ encoder_rpc: encoder-rpc@0x92200000 { -+ reg = <0 0x92200000 0 0x200000>; -+ no-map; -+ }; -+ -+ encoder_reserved: encoder_reserved@94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ reg_can_en: regulator-can-en { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can_stby: regulator-can-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can_en>; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usb_otg1_vbus: regulator-usbotg1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ audio-cpu = <&esai0>; -+ audio-codec = <&cs42888>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ status = "okay"; -+ }; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&asrc1 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; -+ status = "okay"; -+}; -+ -+&sai4 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai4_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai5 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai5_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ vbus-supply = <®_usb_otg1_vbus>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&usbotg3 { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbotg3_cdns3 { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens 497>; -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&irqsteer_csi0 { -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ mt35xu512aba0:flash@0 { -+ reg = <0>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-nor,ddr-quad-read-dummy = <8>; -+ }; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; -+ }; -+}; -+ -+&i2c3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c3>; -+ status = "okay"; -+ -+ pca9557_a: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@19 { -+ compatible = "nxp,pca9557"; -+ reg = <0x19>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ -+ pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { -+ fsl,pins = < -+ IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 -+ IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 -+ IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 -+ IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 -+ IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 -+ IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 -+ IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 -+ IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 -+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan2grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 -+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan3grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 -+ IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+}; -+ -+ pinctrl_lpi2c3: lpi2cgrp { -+ fsl,pins = < -+ IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 -+ IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 -+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 -+ IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 -+ IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 -+ >; -+ }; -+ -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts -new file mode 100644 -index 000000000..16b0261de ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-mek.dts" -+ -+&vpu_encoder { -+ status = "disabled"; -+}; -+ -+&vpu_decoder { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts -new file mode 100644 -index 000000000..770b12cab ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts -@@ -0,0 +1,51 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-mek-rpmsg.dts" -+ -+/ { -+ chosen { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ stdout-path = &lpuart0; -+ -+ module@0 { -+ bootargs = "earlycon=xen console=hvc0 root=/dev/mmcblk1p2 rootwait rw"; -+ compatible = "xen,linux-zimage", "xen,multiboot-module"; -+ /* The size will be override by uboot command */ -+ reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; -+ }; -+ -+ }; -+ -+ reserved-memory { -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x30000000>; -+ alloc-ranges = <0 0xc0000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ rtc0: rtc@23000000 { -+ interrupts = ; -+ xen,passthrough; -+ }; -+}; -+ -+&imx8_gpu_ss { -+ reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; -+ status = "okay"; -+}; -+ -+&lsio_mu1 { -+ /* not map for dom0, dom0 will mmio trap to xen */ -+ xen,no-map; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts -new file mode 100644 -index 000000000..24a370642 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8x-mek-dpu-lcdif.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts -new file mode 100644 -index 000000000..2d3bd4eb2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-dpu-lcdif.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts -new file mode 100644 -index 000000000..498c65c48 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8qxp-mek-dsi-rm67191.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts -new file mode 100644 -index 000000000..33427aef7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-mek.dts" -+#include "imx8qxp-mek-dsi-rm67191.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi -new file mode 100644 -index 000000000..5fb7da451 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi -@@ -0,0 +1,111 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/delete-node/ &adv_bridge0; -+/delete-node/ &adv_bridge1; -+ -+&ldb1_phy { -+ status = "disabled"; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -+ -+&ldb2_phy { -+ status = "disabled"; -+}; -+ -+&ldb2 { -+ status = "disabled"; -+}; -+ -+&lvds_bridge0 { -+ status = "disabled"; -+}; -+ -+&lvds_bridge1 { -+ status = "disabled"; -+}; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ -+ panel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ -+ port@0 { -+ reg = <0>; -+ panel0_in: endpoint { -+ remote-endpoint = <&mipi0_panel_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ mipi0_panel_out: endpoint { -+ remote-endpoint = <&panel0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ fsl,clock-drop-level = <2>; -+ -+ panel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "raydium,rm67191"; -+ reg = <0>; -+ reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; -+ dsi-lanes = <4>; -+ video-mode = <2>; -+ width-mm = <68>; -+ height-mm = <121>; -+ -+ port@0 { -+ reg = <0>; -+ panel1_in: endpoint { -+ remote-endpoint = <&mipi1_panel_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ /delete-node/ port@1; -+ -+ port@1 { -+ reg = <1>; -+ mipi1_panel_out: endpoint { -+ remote-endpoint = <&panel1_in>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts -new file mode 100644 -index 000000000..7651dc6fa ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts -@@ -0,0 +1,16 @@ -+/* -+ * Copyright 2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qxp-mek-enet2.dts" -+#include "imx8qxp-enet2-tja1100.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts -new file mode 100644 -index 000000000..2a77456c7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts -@@ -0,0 +1,27 @@ -+/* -+ * Copyright 2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "imx8qxp-mek.dts" -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+ðphy1 { -+ status = "okay"; -+}; -+ -+&fec2 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts -new file mode 100644 -index 000000000..89669251f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts -@@ -0,0 +1,253 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ model = "Freescale i.MX8QXP MEK Inmate"; -+ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; -+ interrupt-parent = <&gic>; -+ #address-cells = <0x2>; -+ #size-cells = <0x2>; -+ -+ aliases { -+ mmc0 = &usdhc1; -+ serial2 = &lpuart2; -+ }; -+ -+ cpus { -+ #address-cells = <0x2>; -+ #size-cells = <0x0>; -+ -+ cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x2>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; -+ }; -+ -+ cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ enable-method = "psci"; -+ reg = <0x0 0x3>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ scu { -+ compatible = "fsl,imx-scu"; -+ mbox-names = "tx0", "tx1", "tx2", "tx3", -+ "rx0", "rx1", "rx2", "rx3", -+ "gip3"; -+ mboxes = <&lsio_mu2 0 0 -+ &lsio_mu2 0 1 -+ &lsio_mu2 0 2 -+ &lsio_mu2 0 3 -+ &lsio_mu2 1 0 -+ &lsio_mu2 1 1 -+ &lsio_mu2 1 2 -+ &lsio_mu2 1 3 -+ &lsio_mu2 3 3>; -+ -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ }; -+ -+ clk: clock-controller { -+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; -+ clocks = <&xtal32k &xtal24m>; -+ clock-names = "xtal_32KHz", "xtal_24Mhz"; -+ }; -+ -+ iomuxc: pinctrl { -+ compatible = "fsl,imx8qxp-iomuxc"; -+ }; -+ }; -+ -+ soc { -+ compatible = "fsl,imx8qxp-soc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8333333>; -+ }; -+ -+ gic: interrupt-controller@51a00000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ -+ xtal32k: clock-xtal32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xtal_32KHz"; -+ }; -+ -+ xtal24m: clock-xtal24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "xtal_24MHz"; -+ }; -+ -+ pci@fd700000 { -+ compatible = "pci-host-ecam-generic"; -+ device_type = "pci"; -+ bus-range = <0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 2 &gic GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 3 &gic GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, -+ <0 0 0 4 &gic GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; -+ reg = <0x0 0xfd700000 0x0 0x100000>; -+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; -+ }; -+ -+ /* For early console */ -+ serial@5a060000 { -+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+ reg = <0x0 0x5a060000 0x0 0x1000>; -+ }; -+ -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+}; -+ -+#include "imx8qxp-ss-lsio.dtsi" -+#include "imx8qxp-ss-adma.dtsi" -+#include "imx8qxp-ss-conn.dtsi" -+ -+&edma0 { -+ status = "disabled"; -+}; -+ -+&edma1 { -+ status = "disabled"; -+}; -+ -+&acm { -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 -+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&lsio_mu1 { -+ status = "disabled"; -+}; -+ -+&lsio_mu2 { -+ status = "okay"; -+}; -+ -+&lsio_gpio0 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio1 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio2 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio3 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio4 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio5 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio6 { -+ status = "disabled"; -+}; -+ -+&lsio_gpio7 { -+ status = "disabled"; -+}; -+ -+&lpuart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ status = "okay"; -+ /delete-property/ dma-names; -+ /delete-property/ dmas; -+}; -+ -+/delete-node/ &lpuart0; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts -new file mode 100644 -index 000000000..8debd8261 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts -new file mode 100644 -index 000000000..07bb468e2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts -new file mode 100644 -index 000000000..26cead50b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts -new file mode 100644 -index 000000000..406047eb5 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts -new file mode 100644 -index 000000000..8903d2d99 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts -new file mode 100644 -index 000000000..5027beb1c ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts -new file mode 100644 -index 000000000..01560ad50 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts -new file mode 100644 -index 000000000..1982c4afa ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019,2020 NXP -+ */ -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts -new file mode 100644 -index 000000000..20adc45ec ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8x-mek-lcdif.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts -new file mode 100644 -index 000000000..cc65560a7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-lcdif.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts -new file mode 100644 -index 000000000..a403b9da2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2020 -+ -+/dts-v1/; -+ -+#include "imx8qxp-mek-rpmsg.dts" -+#include "imx8qxp-mek-ov5640.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts -new file mode 100644 -index 000000000..54c768ac0 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+/dts-v1/; -+#include "imx8qxp-mek.dts" -+#include "imx8qxp-mek-ov5640.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi -new file mode 100644 -index 000000000..5b204e228 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+&isi_1 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_2 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&isi_3 { -+ status = "disabled"; -+ -+ cap_device { -+ status = "disabled"; -+ }; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ /delete-property/virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_ep>; -+ data-lanes = <1 2>; -+ }; -+ }; -+}; -+ -+&i2c_mipi_csi0 { -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&xtal24m>; -+ clock-names = "xclk"; -+ csi_id = <0>; -+ powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ port { -+ ov5640_mipi_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2>; -+ clocks-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ /delete-node/max9286_mipi@6a; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts -new file mode 100644 -index 000000000..3651ec1d3 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8qxp-mek-rpmsg.dts" -+ -+&pcieb{ -+ status = "disabled"; -+}; -+ -+&pcieb_ep{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts -new file mode 100644 -index 000000000..5f4ee5adb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts -@@ -0,0 +1,98 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+#include "imx8qxp-mek-rpmsg.dts" -+ -+/ { -+ domu { -+ /* -+ * There are 5 MUs, 0A is used by root cell, 1A is used -+ * by ATF, so for non-root cell, 2A/3A/4A could be used. -+ * SC_R_MU_0A -+ * SC_R_MU_1A -+ * SC_R_MU_2A -+ * SC_R_MU_3A -+ * SC_R_MU_4A -+ * The rsrcs and pads will be configured by uboot scu_rm cmd -+ */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ doma { -+ /* -+ * This is not for domu, this is just reuse -+ * the method for jailhouse inmate non root cell -+ * Linux. -+ */ -+ compatible = "xen,domu"; -+ /* -+ * The reg property will be updated by U-Boot to -+ * reflect the partition id. -+ */ -+ reg = <0>; -+ init_on_rsrcs = < -+ IMX_SC_R_MU_2A -+ >; -+ rsrcs = < -+ IMX_SC_R_SDHC_0 -+ IMX_SC_R_UART_2 -+ IMX_SC_R_MU_2A -+ >; -+ pads = < -+ /* emmc */ -+ IMX8QXP_EMMC0_CLK -+ IMX8QXP_EMMC0_CMD -+ IMX8QXP_EMMC0_DATA0 -+ IMX8QXP_EMMC0_DATA1 -+ IMX8QXP_EMMC0_DATA2 -+ IMX8QXP_EMMC0_DATA3 -+ IMX8QXP_EMMC0_DATA4 -+ IMX8QXP_EMMC0_DATA5 -+ IMX8QXP_EMMC0_DATA6 -+ IMX8QXP_EMMC0_DATA7 -+ IMX8QXP_EMMC0_STROBE -+ /* lpuart2 */ -+ IMX8QXP_UART2_TX -+ IMX8QXP_UART2_RX -+ >; -+ }; -+ }; -+ -+}; -+ -+&{/reserved-memory} { -+ -+ jh_reserved: jh@fdc00000 { -+ no-map; -+ reg = <0x0 0xfdc00000 0x0 0x400000>; -+ }; -+ -+ loader_reserved: loader@fdb00000 { -+ no-map; -+ reg = <0x0 0xfdb00000 0x0 0x00100000>; -+ }; -+ -+ ivshmem_reserved: ivshmem@fd900000 { -+ no-map; -+ reg = <0x0 0xfd900000 0x0 0x00200000>; -+ }; -+ -+ pci_reserved: pci@fd700000 { -+ no-map; -+ reg = <0x0 0xfd700000 0x0 0x00200000>; -+ }; -+ -+ /* Decrease if no need such big memory */ -+ inmate_reserved: inmate@df7000000 { -+ no-map; -+ reg = <0x0 0xdf700000 0x0 0x1e000000>; -+ }; -+}; -+ -+&usdhc1 { -+ /delete-property/ compatible; -+}; -+ -+&lpuart2 { -+ /* Let inmate linux use this for console */ -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts -new file mode 100644 -index 000000000..412f32a4b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts -@@ -0,0 +1,5 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+#include "imx8qxp-mek.dts" -+#include "imx8x-mek-rpmsg.dtsi" -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts -new file mode 100644 -index 000000000..2f7675eb8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2018 -+ -+#include "imx8qxp-mek-rpmsg.dts" -+ -+/ { -+ reserved-memory { -+ /delete-node/ dsp_reserved; -+ /delete-node/ dsp_reserved_heap; -+ /delete-node/ dsp_vdev0vring0; -+ /delete-node/ dsp_vdev0vring1; -+ /delete-node/ dsp_vdev0buffer; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x2000000>; -+ no-map; -+ }; -+ }; -+ -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+ -+ sof-audio-cs42888 { -+ compatible = "simple-audio-card"; -+ label = "imx-cs42888"; -+ simple-audio-card,widgets = -+ "Line", "Line Out Jack", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ status = "okay"; -+ simple-audio-card,dai-link { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&dsp 0>; -+ }; -+ codec { -+ sound-dai = <&cs42888>; -+ }; -+ }; -+ }; -+}; -+ -+&edma0 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x592e0000 0x10000>, /* sai1 rx */ -+ <0x592f0000 0x10000>, /* sai1 tx */ -+ <0x59350000 0x10000>, -+ <0x59370000 0x10000>; -+ #dma-cells = <3>; -+ shared-interrupt; -+ dma-channels = <8>; -+ interrupts = , /* spdif0 */ -+ , -+ , /* sai0 */ -+ , -+ , /* sai1 */ -+ , -+ , -+ ; -+ interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ -+ "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ -+ "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ -+ "edma0-chan21-tx", /* gpt5 */ -+ "edma0-chan23-rx"; /* gpt7 */ -+ power-domains = <&pd IMX_SC_R_DMA_0_CH8>, -+ <&pd IMX_SC_R_DMA_0_CH9>, -+ <&pd IMX_SC_R_DMA_0_CH12>, -+ <&pd IMX_SC_R_DMA_0_CH13>, -+ <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>, -+ <&pd IMX_SC_R_DMA_0_CH21>, -+ <&pd IMX_SC_R_DMA_0_CH23>; -+ power-domain-names = "edma0-chan8", "edma0-chan9", -+ "edma0-chan12", "edma0-chan13", -+ "edma0-chan14", "edma0-chan15", -+ "edma0-chan21", "edma0-chan23"; -+ status = "okay"; -+}; -+ -+&dsp { -+ #sound-dai-cells = <1>; -+ compatible = "fsl,imx8qxp-dsp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>, -+ <&pd IMX_SC_R_IRQSTR_DSP>, -+ <&pd IMX_SC_R_ESAI_0>, -+ <&pd IMX_SC_R_DMA_0_CH6>, -+ <&pd IMX_SC_R_DMA_0_CH7>, -+ <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>; -+ -+ clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, -+ <&clk_dummy>; -+ clock-names = "ipg", "ocram", "core", "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba"; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&lsio_mu13 2 0>, -+ <&lsio_mu13 2 1>, -+ <&lsio_mu13 3 0>, -+ <&lsio_mu13 3 1>; -+ memory-region = <&dsp_reserved>; -+ /delete-property/ firmware-name; -+ -+ reg = <0x596e8000 0x88000>; -+ tplg-name = "sof-imx8-cs42888.tplg"; -+ machine-drv-name = "asoc-simple-card"; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "disabled"; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&asrc0 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&wm8960 { -+ status = "disabled"; -+}; -+ -+&cs42888 { -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts -new file mode 100644 -index 000000000..c616c6dd9 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts -@@ -0,0 +1,168 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2018 -+ -+#include "imx8qxp-mek-rpmsg.dts" -+ -+/ { -+ reserved-memory { -+ /delete-node/ dsp_reserved; -+ /delete-node/ dsp_reserved_heap; -+ /delete-node/ dsp_vdev0vring0; -+ /delete-node/ dsp_vdev0vring1; -+ /delete-node/ dsp_vdev0buffer; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x2000000>; -+ no-map; -+ }; -+ }; -+ -+ sound-cs42888 { -+ status = "disabled"; -+ }; -+ -+ sound-wm8960 { -+ status = "disabled"; -+ }; -+ -+ sof-sound-wm8960 { -+ compatible = "simple-audio-card"; -+ label = "wm8960-audio"; -+ simple-audio-card,bitclock-master = <&sndcodec>; -+ simple-audio-card,frame-master = <&sndcodec>; -+ hp-det-gpio = <&lsio_gpio1 0 0>; -+ mic-det-gpio = <&lsio_gpio1 0 0>; -+ simple-audio-card,widgets = -+ "Headphone", "Headphones", -+ "Speaker", "Ext Spk", -+ "Microphone", "Mic Jack"; -+ simple-audio-card,routing = -+ "Headphones", "HP_L", -+ "Headphones", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "Mic Jack", -+ "RINPUT2", "Mic Jack", -+ "Mic Jack", "MICB"; -+ simple-audio-card,dai-link { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&dsp 1>; -+ }; -+ sndcodec: codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+ }; -+}; -+ -+&edma0 { -+ compatible = "fsl,imx8qm-edma"; -+ reg = <0x5a1f0000 0x10000>, -+ <0x59280000 0x10000>, /* spdif0 rx */ -+ <0x59290000 0x10000>, /* spdif0 tx */ -+ <0x592c0000 0x10000>, /* sai0 rx */ -+ <0x592d0000 0x10000>, /* sai0 tx */ -+ <0x59350000 0x10000>, -+ <0x59370000 0x10000>; -+ #dma-cells = <3>; -+ shared-interrupt; -+ dma-channels = <6>; -+ interrupts = , /* spdif0 */ -+ , -+ , /* sai0 */ -+ , -+ , -+ ; -+ interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ -+ "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ -+ "edma0-chan21-tx", /* gpt5 */ -+ "edma0-chan23-rx"; /* gpt7 */ -+ -+ power-domains = <&pd IMX_SC_R_DMA_0_CH8>, -+ <&pd IMX_SC_R_DMA_0_CH9>, -+ <&pd IMX_SC_R_DMA_0_CH12>, -+ <&pd IMX_SC_R_DMA_0_CH13>, -+ <&pd IMX_SC_R_DMA_0_CH21>, -+ <&pd IMX_SC_R_DMA_0_CH23>; -+ power-domain-names = "edma0-chan8", "edma0-chan9", -+ "edma0-chan12", "edma0-chan13", -+ "edma0-chan21", "edma0-chan23"; -+ status = "okay"; -+}; -+ -+&dsp { -+ #sound-dai-cells = <1>; -+ compatible = "fsl,imx8qxp-dsp"; -+ reg = <0x596e8000 0x88000>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ -+ power-domains = <&pd IMX_SC_R_MU_13A>, -+ <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>, -+ <&pd IMX_SC_R_IRQSTR_DSP>, -+ <&pd IMX_SC_R_SAI_1>, -+ <&pd IMX_SC_R_DMA_0_CH14>, -+ <&pd IMX_SC_R_DMA_0_CH15>, -+ <&pd IMX_SC_R_AUDIO_CLK_0>, -+ <&pd IMX_SC_R_AUDIO_CLK_1>, -+ <&pd IMX_SC_R_AUDIO_PLL_0>, -+ <&pd IMX_SC_R_AUDIO_PLL_1>; -+ -+ clock-names = "ipg", "ocram", "core", -+ "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; -+ clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, -+ <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, -+ <&clk_dummy>, <&clk_dummy>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&lsio_mu13 2 0>, -+ <&lsio_mu13 2 1>, -+ <&lsio_mu13 3 0>, -+ <&lsio_mu13 3 1>; -+ memory-region = <&dsp_reserved>; -+ /delete-property/ firmware-name; -+ -+ tplg-name = "sof-imx8-wm8960.tplg"; -+ machine-drv-name = "asoc-simple-card"; -+ status = "okay"; -+}; -+ -+&wm8960 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "disabled"; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&asrc0 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&cs42888 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts -index 46437d3c7..715a52a5a 100644 ---- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts -@@ -1,272 +1,14 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * Copyright 2017~2018 NXP -+ * Copyright 2017-2020 NXP - */ - - /dts-v1/; - - #include "imx8qxp.dtsi" -+#include "imx8x-mek.dtsi" - - / { - model = "Freescale i.MX8QXP MEK"; - compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; -- -- chosen { -- stdout-path = &adma_lpuart0; -- }; -- -- memory@80000000 { -- device_type = "memory"; -- reg = <0x00000000 0x80000000 0 0x40000000>; -- }; -- -- reg_usdhc2_vmmc: usdhc2-vmmc { -- compatible = "regulator-fixed"; -- regulator-name = "SD1_SPWR"; -- regulator-min-microvolt = <3000000>; -- regulator-max-microvolt = <3000000>; -- gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- }; --}; -- --&adma_dsp { -- status = "okay"; --}; -- --&adma_i2c1 { -- #address-cells = <1>; -- #size-cells = <0>; -- clock-frequency = <100000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; -- status = "okay"; -- -- i2c-switch@71 { -- compatible = "nxp,pca9646", "nxp,pca9546"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x71>; -- reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; -- -- i2c@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0>; -- -- max7322: gpio@68 { -- compatible = "maxim,max7322"; -- reg = <0x68>; -- gpio-controller; -- #gpio-cells = <2>; -- }; -- }; -- -- i2c@1 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <1>; -- }; -- -- i2c@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- -- pressure-sensor@60 { -- compatible = "fsl,mpl3115"; -- reg = <0x60>; -- }; -- }; -- -- i2c@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- -- pca9557_a: gpio@1a { -- compatible = "nxp,pca9557"; -- reg = <0x1a>; -- gpio-controller; -- #gpio-cells = <2>; -- }; -- -- pca9557_b: gpio@1d { -- compatible = "nxp,pca9557"; -- reg = <0x1d>; -- gpio-controller; -- #gpio-cells = <2>; -- }; -- -- light-sensor@44 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_isl29023>; -- compatible = "isil,isl29023"; -- reg = <0x44>; -- interrupt-parent = <&lsio_gpio1>; -- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; -- }; -- }; -- }; --}; -- --&adma_lpuart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_lpuart0>; -- status = "okay"; --}; -- --&fec1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_fec1>; -- phy-mode = "rgmii-id"; -- phy-handle = <ðphy0>; -- fsl,magic-packet; -- status = "okay"; -- -- mdio { -- #address-cells = <1>; -- #size-cells = <0>; -- -- ethphy0: ethernet-phy@0 { -- compatible = "ethernet-phy-ieee802.3-c22"; -- reg = <0>; -- }; -- }; --}; -- --&scu_key { -- status = "okay"; --}; -- --&thermal_zones { -- pmic-thermal0 { -- polling-delay-passive = <250>; -- polling-delay = <2000>; -- thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -- -- trips { -- pmic_alert0: trip0 { -- temperature = <110000>; -- hysteresis = <2000>; -- type = "passive"; -- }; -- -- pmic_crit0: trip1 { -- temperature = <125000>; -- hysteresis = <2000>; -- type = "critical"; -- }; -- }; -- -- cooling-maps { -- map0 { -- trip = <&pmic_alert0>; -- cooling-device = -- <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -- }; -- }; -- }; --}; -- --&usdhc1 { -- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; -- assigned-clock-rates = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_usdhc1>; -- bus-width = <8>; -- no-sd; -- no-sdio; -- non-removable; -- status = "okay"; --}; -- --&usdhc2 { -- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; -- assigned-clock-rates = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_usdhc2>; -- bus-width = <4>; -- vmmc-supply = <®_usdhc2_vmmc>; -- cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -- wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; -- status = "okay"; --}; -- --&iomuxc { -- pinctrl_fec1: fec1grp { -- fsl,pins = < -- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -- IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -- IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -- IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -- IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -- >; -- }; -- -- pinctrl_ioexp_rst: ioexprstgrp { -- fsl,pins = < -- IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 -- >; -- }; -- -- pinctrl_isl29023: isl29023grp { -- fsl,pins = < -- IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 -- >; -- }; -- -- pinctrl_lpi2c1: lpi2c1grp { -- fsl,pins = < -- IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 -- IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 -- >; -- }; -- -- pinctrl_lpuart0: lpuart0grp { -- fsl,pins = < -- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 -- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 -- >; -- }; -- -- pinctrl_usdhc1: usdhc1grp { -- fsl,pins = < -- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -- >; -- }; -- -- pinctrl_usdhc2: usdhc2grp { -- fsl,pins = < -- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -- >; -- }; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi -new file mode 100644 -index 000000000..8b6f0fc00 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi -@@ -0,0 +1,82 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Dong Aisheng -+ */ -+ -+&dma_ipg_clk { -+ clock-frequency = <160000000>; -+}; -+ -+&audio_ipg_clk { -+ clock-frequency = <160000000>; -+}; -+ -+&lpuart0 { -+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+}; -+ -+&lpuart1 { -+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+}; -+ -+&lpuart2 { -+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+}; -+ -+&lpuart3 { -+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -+}; -+ -+&i2c0 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&i2c1 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&i2c2 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&i2c3 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+}; -+ -+&asrc0 { -+ compatible = "fsl,imx8qxp-asrc"; -+}; -+ -+&asrc1 { -+ compatible = "fsl,imx8qxp-asrc"; -+}; -+ -+&audio_subsys { -+ -+ dsp: dsp@596e8000 { -+ compatible = "fsl,imx8qxp-hifi4"; -+ reg = <0x596e8000 0x88000>; -+ clocks = <&clk_dummy>, -+ <&clk_dummy>, -+ <&clk_dummy>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ power-domains = <&pd IMX_SC_R_MU_13B>, -+ <&pd IMX_SC_R_DSP>, -+ <&pd IMX_SC_R_DSP_RAM>, -+ <&pd IMX_SC_R_IRQSTR_DSP>; -+ mbox-names = "tx0", "rx0", "rxdb0"; -+ mboxes = <&lsio_mu13 0 0>, -+ <&lsio_mu13 1 0>, -+ <&lsio_mu13 3 0>; -+ status = "disabled"; -+ }; -+}; -+ -+&dma_subsys { -+ lcdif_mux_regs: mux-regs@5a170000 { -+ compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon"; -+ reg = <0x5a170000 0x4>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi -new file mode 100644 -index 000000000..f8ad22a7d ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Dong Aisheng -+ */ -+ -+&usdhc1 { -+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; -+}; -+ -+&usdhc2 { -+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; -+}; -+ -+&fec1 { -+ compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; -+}; -+ -+&fec2 { -+ compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi -new file mode 100644 -index 000000000..a929c3a23 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi -@@ -0,0 +1,51 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+&dpu1 { -+ compatible = "fsl,imx8qxp-dpu"; -+ -+ dpu_disp0: port@0 { -+ reg = <0>; -+ -+ dpu_disp0_ldb1_ch0: endpoint@0 { -+ remote-endpoint = <&ldb1_ch0>; -+ }; -+ -+ dpu_disp0_ldb1_ch1: endpoint@1 { -+ remote-endpoint = <&ldb1_ch1>; -+ }; -+ -+ dpu_disp0_mipi_dsi: endpoint@2 { -+ remote-endpoint = <&mipi0_dsi_in>; -+ }; -+ }; -+ -+ dpu_disp1: port@1 { -+ reg = <1>; -+ -+ dpu_disp1_ldb2_ch0: endpoint@0 { -+ remote-endpoint = <&ldb2_ch0>; -+ }; -+ -+ dpu_disp1_ldb2_ch1: endpoint@1 { -+ remote-endpoint = <&ldb2_ch1>; -+ }; -+ -+ dpu_disp1_mipi_dsi: endpoint@2 { -+ remote-endpoint = <&mipi1_dsi_in>; -+ }; -+ -+ dpu_disp1_lcdif: endpoint@3 { -+ }; -+ }; -+}; -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&dpu_disp0>, <&dpu_disp1>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi -new file mode 100644 -index 000000000..424a25582 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi -@@ -0,0 +1,15 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+&gpu0_subsys { -+ imx8_gpu_ss: imx8_gpu0_ss { -+ compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; -+ cores = <&gpu_3d0>; -+ reg = <0x80000000 0x80000000>, <0x0 0x10000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi -new file mode 100644 -index 000000000..4fae19e5e ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Richard Zhu -+ */ -+ -+&hsio_subsys { -+ phyx1_lpcg: clock-controller@5f090000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5f090000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&hsio_refb_clk>, <&hsio_per_clk>, -+ <&hsio_per_clk>, <&hsio_per_clk>; -+ bit-offset = <0 4 8 16>; -+ clock-output-names = "hsio_phyx1_pclk", -+ "hsio_phyx1_epcs_tx_clk", -+ "hsio_phyx1_epcs_rx_clk", -+ "hsio_phyx1_apb_clk"; -+ power-domains = <&pd IMX_SC_R_SERDES_1>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi -new file mode 100644 -index 000000000..b455ed6fc ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi -@@ -0,0 +1,33 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ * Dong Aisheng -+ */ -+ -+&csi1_pxl_lpcg { -+ status = "disabled"; -+}; -+ -+&csi1_core_lpcg { -+ status = "disabled"; -+}; -+ -+&csi1_esc_lpcg { -+ status = "disabled"; -+}; -+ -+&irqsteer_csi1 { -+ status = "disabled"; -+}; -+ -+&i2c_mipi_csi1 { -+ status = "disabled"; -+}; -+ -+&gpio0_mipi_csi1 { -+ status = "disabled"; -+}; -+ -+&mipi_csi_1 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi -new file mode 100644 -index 000000000..3f31e833e ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi -@@ -0,0 +1,73 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018-2019 NXP -+ * Dong Aisheng -+ */ -+ -+&lsio_gpio0 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio1 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio2 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio3 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio4 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio5 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio6 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_gpio7 { -+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -+}; -+ -+&lsio_mu0 { -+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu1 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu2 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu3 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+}; -+ -+&lsio_mu4 { -+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -+}; -+ -+&pwm0 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+}; -+ -+&pwm1 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+}; -+ -+&pwm2 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+}; -+ -+&pwm3 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi -new file mode 100644 -index 000000000..c8b5468f2 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi -@@ -0,0 +1,425 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/ { -+ lvds_subsys: bus@56220000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x56220000 0x0 0x56220000 0x30000>; -+ -+ mipi_ipg_clk: clock-mipi-ipg { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <120000000>; -+ clock-output-names = "mipi_ipg_clk"; -+ }; -+ -+ mipi_pll_div2_clk: clock-mipi-div2-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <432000000>; -+ clock-output-names = "mipi_pll_div2_clk"; -+ }; -+ -+ mipi0_lis_lpcg: clock-controller@56223000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&mipi_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "mipi0_lis_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ }; -+ -+ mipi0_pwm_lpcg: clock-controller@5622300c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5622300c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&mipi_ipg_clk>, -+ <&mipi_ipg_clk>; -+ bit-offset = <0 16 4>; -+ clock-output-names = "mipi0_pwm_lpcg_clk", -+ "mipi0_pwm_lpcg_ipg_clk", -+ "mipi0_pwm_lpcg_32k_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; -+ }; -+ -+ mipi0_i2c0_lpcg: clock-controller@56223010 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56223010 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&mipi_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "mipi0_i2c0_lpcg_clk", -+ "mipi0_i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; -+ }; -+ -+ mipi1_lis_lpcg: clock-controller@56243000 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56243000 0x4>; -+ #clock-cells = <1>; -+ clocks = <&mipi_ipg_clk>; -+ bit-offset = <16>; -+ clock-output-names = "mipi1_lis_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ }; -+ -+ mipi1_pwm_lpcg: clock-controller@5624300c { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x5624300c 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, -+ <&mipi_ipg_clk>, -+ <&mipi_ipg_clk>; -+ bit-offset = <0 16 4>; -+ clock-output-names = "mipi1_pwm_lpcg_clk", -+ "mipi1_pwm_lpcg_ipg_clk", -+ "mipi1_pwm_lpcg_32k_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; -+ }; -+ -+ mipi1_i2c0_lpcg: clock-controller@56243010 { -+ compatible = "fsl,imx8qxp-lpcg"; -+ reg = <0x56243010 0x4>; -+ #clock-cells = <1>; -+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, -+ <&mipi_ipg_clk>; -+ bit-offset = <0 16>; -+ clock-output-names = "mipi1_i2c0_lpcg_clk", -+ "mipi1_i2c0_lpcg_ipg_clk"; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; -+ }; -+ -+ irqsteer_mipi_lvds0: irqsteer@56220000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x56220000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&mipi0_lis_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ }; -+ -+ lvds_region1: lvds_region@56221000 { -+ compatible = "syscon"; -+ reg = <0x56221000 0xf0>; -+ }; -+ -+ ldb1_phy: ldb_phy@56221000 { -+ compatible = "mixel,lvds-combo-phy"; -+ reg = <0x56221000 0x100>, <0x56228000 0x1000>; -+ #phy-cells = <0>; -+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; -+ clock-names = "phy"; -+ power-domains = <&pd IMX_SC_R_LVDS_0>; -+ status = "disabled"; -+ }; -+ -+ ldb1: ldb@562210e0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qxp-ldb"; -+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; -+ clock-names = "pixel", "bypass", -+ "aux_pixel", "aux_bypass"; -+ power-domains = <&pd IMX_SC_R_LVDS_0>, -+ <&pd IMX_SC_R_LVDS_1>; -+ power-domain-names = "main", "aux"; -+ gpr = <&lvds_region1>; -+ fsl,auxldb = <&ldb2>; -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ phys = <&ldb1_phy>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb1_ch0: endpoint { -+ remote-endpoint = <&dpu_disp0_ldb1_ch0>; -+ }; -+ }; -+ }; -+ -+ lvds-channel@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ phys = <&ldb1_phy>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb1_ch1: endpoint { -+ remote-endpoint = <&dpu_disp0_ldb1_ch1>; -+ }; -+ }; -+ }; -+ }; -+ -+ pwm_mipi_lvds0: pwm@56224000 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+ reg = <0x56224000 0x1000>; -+ clocks = <&mipi0_pwm_lpcg 0>, -+ <&mipi0_pwm_lpcg 1>, -+ <&mipi0_pwm_lpcg 2>; -+ clock-names = "per", "ipg", "32k"; -+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ i2c0_mipi_lvds0: i2c@56226000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x56226000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_mipi_lvds0>; -+ clocks = <&mipi0_i2c0_lpcg 0>, -+ <&mipi0_i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ mipi0_dphy: dphy@56228300 { -+ compatible = "fsl,imx8qm-mipi-dphy"; -+ reg = <0x56228300 0x100>; -+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; -+ clock-names = "phy_ref"; -+ #phy-cells = <0>; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ status = "disabled"; -+ }; -+ -+ mipi0_dsi_host: dsi_host@56228000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qx-nwl-dsi"; -+ reg = <0x56228000 0x300>; -+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&mipi_pll_div2_clk>; -+ clock-names = "pixel", -+ "bypass", -+ "phy_ref", -+ "tx_esc", -+ "rx_esc", -+ "phy_parent"; -+ interrupts = <16>; -+ interrupt-parent = <&irqsteer_mipi_lvds0>; -+ power-domains = <&pd IMX_SC_R_MIPI_0>; -+ phys = <&mipi0_dphy>; -+ phy-names = "dphy"; -+ csr = <&lvds_region1>; -+ use-disp-ss; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mipi0_in: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg = <0>; -+ mipi0_dsi_in: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&dpu_disp0_mipi_dsi>; -+ }; -+ }; -+ }; -+ }; -+ -+ irqsteer_mipi_lvds1: irqsteer@56240000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x56240000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ #interrupt-cells = <1>; -+ fsl,channel = <0>; -+ fsl,num-irqs = <32>; -+ clocks = <&mipi1_lis_lpcg 0>; -+ clock-names = "ipg"; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ }; -+ -+ lvds_region2: lvds_region@56241000 { -+ compatible = "syscon"; -+ reg = <0x56241000 0xf0>; -+ }; -+ -+ ldb2_phy: ldb_phy@56241000 { -+ compatible = "mixel,lvds-combo-phy"; -+ reg = <0x56241000 0x100>, <0x56248000 0x1000>; -+ #phy-cells = <0>; -+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; -+ clock-names = "phy"; -+ power-domains = <&pd IMX_SC_R_LVDS_1>; -+ status = "disabled"; -+ }; -+ -+ ldb2: ldb@562410e0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qxp-ldb"; -+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, -+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; -+ clock-names = "pixel", "bypass", -+ "aux_pixel", "aux_bypass"; -+ power-domains = <&pd IMX_SC_R_LVDS_1>, -+ <&pd IMX_SC_R_LVDS_0>; -+ power-domain-names = "main", "aux"; -+ gpr = <&lvds_region2>; -+ fsl,auxldb = <&ldb1>; -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ phys = <&ldb2_phy>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb2_ch0: endpoint { -+ remote-endpoint = <&dpu_disp1_ldb2_ch0>; -+ }; -+ }; -+ }; -+ -+ lvds-channel@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ phys = <&ldb2_phy>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb2_ch1: endpoint { -+ remote-endpoint = <&dpu_disp1_ldb2_ch1>; -+ }; -+ }; -+ }; -+ }; -+ -+ pwm_mipi_lvds1: pwm@56244000 { -+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; -+ reg = <0x56244000 0x1000>; -+ clocks = <&mipi1_pwm_lpcg 0>, -+ <&mipi1_pwm_lpcg 1>, -+ <&mipi1_pwm_lpcg 2>; -+ clock-names = "per", "ipg", "32k"; -+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ #pwm-cells = <2>; -+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; -+ status = "disabled"; -+ }; -+ -+ i2c0_mipi_lvds1: i2c@56246000 { -+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x56246000 0x1000>; -+ interrupts = <8>; -+ interrupt-parent = <&irqsteer_mipi_lvds1>; -+ clocks = <&mipi1_i2c0_lpcg 0>, -+ <&mipi1_i2c0_lpcg 1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; -+ status = "disabled"; -+ }; -+ -+ mipi1_dphy: dphy@56248300 { -+ compatible = "fsl,imx8qx-mipi-dphy"; -+ reg = <0x56248300 0x100>; -+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; -+ clock-names = "phy_ref"; -+ #phy-cells = <0>; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ status = "disabled"; -+ }; -+ -+ mipi1_dsi_host: dsi_host@56248000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8qx-nwl-dsi"; -+ reg = <0x56248000 0x300>; -+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&mipi_pll_div2_clk>; -+ clock-names = "pixel", -+ "bypass", -+ "phy_ref", -+ "tx_esc", -+ "rx_esc", -+ "phy_parent"; -+ interrupts = <16>; -+ interrupt-parent = <&irqsteer_mipi_lvds1>; -+ power-domains = <&pd IMX_SC_R_MIPI_1>; -+ phys = <&mipi1_dphy>; -+ phy-names = "dphy"; -+ csr = <&lvds_region2>; -+ use-disp-ss; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mipi1_in: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg = <0>; -+ mipi1_dsi_in: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&dpu_disp1_mipi_dsi>; -+ }; -+ }; -+ }; -+ }; -+ -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi -index e46faac1f..084e62d71 100644 ---- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* - * Copyright (C) 2016 Freescale Semiconductor, Inc. -- * Copyright 2017-2018 NXP -+ * Copyright 2017-2019 NXP - * Dong Aisheng - */ - -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -19,6 +20,7 @@ / { - #size-cells = <2>; - - aliases { -+ dpu0 = &dpu1; - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &lsio_gpio0; -@@ -29,10 +31,12 @@ aliases { - gpio5 = &lsio_gpio5; - gpio6 = &lsio_gpio6; - gpio7 = &lsio_gpio7; -- i2c0 = &adma_i2c0; -- i2c1 = &adma_i2c1; -- i2c2 = &adma_i2c2; -- i2c3 = &adma_i2c3; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ ldb0 = &ldb1; -+ ldb1 = &ldb2; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; -@@ -41,13 +45,32 @@ aliases { - mu2 = &lsio_mu2; - mu3 = &lsio_mu3; - mu4 = &lsio_mu4; -- serial0 = &adma_lpuart0; -- serial1 = &adma_lpuart1; -- serial2 = &adma_lpuart2; -- serial3 = &adma_lpuart3; -+ serial0 = &lpuart0; -+ serial1 = &lpuart1; -+ serial2 = &lpuart2; -+ serial3 = &lpuart3; -+ isi0 = &isi_0; -+ isi1 = &isi_1; -+ isi2 = &isi_2; -+ isi3 = &isi_3; -+ isi4 = &isi_4; -+ isi5 = &isi_5; -+ isi6 = &isi_6; -+ isi7 = &isi_7; -+ csi0 = &mipi_csi_0; -+ can0 = &flexcan1; -+ can1 = &flexcan2; -+ can2 = &flexcan3; -+ i2c5 = &i2c_rpbus_5; -+ i2c12 = &i2c_rpbus_12; -+ i2c13 = &i2c_rpbus_13; -+ i2c14 = &i2c_rpbus_14; -+ i2c15 = &i2c_rpbus_15; -+ mipi_dsi0 = &mipi0_dsi_host; -+ mipi_dsi1 = &mipi1_dsi_host; - }; - -- cpus { -+ cpus: cpus { - #address-cells = <2>; - #size-cells = <0>; - -@@ -58,7 +81,7 @@ A35_0: cpu@0 { - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; -- clocks = <&clk IMX_A35_CLK>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; -@@ -69,7 +92,7 @@ A35_1: cpu@1 { - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; -- clocks = <&clk IMX_A35_CLK>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; -@@ -80,7 +103,7 @@ A35_2: cpu@2 { - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; -- clocks = <&clk IMX_A35_CLK>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; -@@ -91,7 +114,7 @@ A35_3: cpu@3 { - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; -- clocks = <&clk IMX_A35_CLK>; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; -@@ -128,17 +151,6 @@ gic: interrupt-controller@51a00000 { - interrupts = ; - }; - -- reserved-memory { -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- -- dsp_reserved: dsp@92400000 { -- reg = <0 0x92400000 0 0x2000000>; -- no-map; -- }; -- }; -- - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; -@@ -158,9 +170,16 @@ scu { - &lsio_mu1 1 0 - &lsio_mu1 3 3>; - -+ pd: imx8qx-pd { -+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; -+ #power-domain-cells = <1>; -+ wakeup-irq = <235 236 237 258 262 267 271 -+ 345 346 347 348>; -+ }; -+ - clk: clock-controller { -- compatible = "fsl,imx8qxp-clk"; -- #clock-cells = <1>; -+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; -+ #clock-cells = <2>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; - }; -@@ -173,11 +192,15 @@ ocotp: imx8qx-ocotp { - compatible = "fsl,imx8qxp-scu-ocotp"; - #address-cells = <1>; - #size-cells = <1>; -- }; -+ read-only; - -- pd: imx8qx-pd { -- compatible = "fsl,imx8qxp-scu-pd"; -- #power-domain-cells = <1>; -+ fec_mac0: mac@2c4 { -+ reg = <0x2c4 6>; -+ }; -+ -+ fec_mac1: mac@2c6 { -+ reg = <0x2c6 6>; -+ }; - }; - - scu_key: scu-key { -@@ -190,6 +213,11 @@ rtc: rtc { - compatible = "fsl,imx8qxp-sc-rtc"; - }; - -+ secvio: secvio { -+ compatible = "fsl,imx-sc-secvio"; -+ nvmem = <&ocotp>; -+ }; -+ - watchdog { - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; - timeout-sec = <60>; -@@ -201,6 +229,10 @@ tsens: thermal-sensor { - }; - }; - -+ soc { -+ compatible = "fsl,imx8qxp-soc"; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ -@@ -209,6 +241,13 @@ timer { - ; /* Hypervisor */ - }; - -+ clk_dummy: clock-dummy { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <0>; -+ clock-output-names = "clk_dummy"; -+ }; -+ - xtal32k: clock-xtal32k { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -223,380 +262,6 @@ xtal24m: clock-xtal24m { - clock-output-names = "xtal_24MHz"; - }; - -- adma_subsys: bus@59000000 { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x59000000 0x0 0x59000000 0x2000000>; -- -- adma_lpcg: clock-controller@59000000 { -- compatible = "fsl,imx8qxp-lpcg-adma"; -- reg = <0x59000000 0x2000000>; -- #clock-cells = <1>; -- }; -- -- adma_dsp: dsp@596e8000 { -- compatible = "fsl,imx8qxp-dsp"; -- reg = <0x596e8000 0x88000>; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, -- <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, -- <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; -- clock-names = "ipg", "ocram", "core"; -- power-domains = <&pd IMX_SC_R_MU_13A>, -- <&pd IMX_SC_R_MU_13B>, -- <&pd IMX_SC_R_DSP>, -- <&pd IMX_SC_R_DSP_RAM>; -- mbox-names = "txdb0", "txdb1", -- "rxdb0", "rxdb1"; -- mboxes = <&lsio_mu13 2 0>, -- <&lsio_mu13 2 1>, -- <&lsio_mu13 3 0>, -- <&lsio_mu13 3 1>; -- memory-region = <&dsp_reserved>; -- status = "disabled"; -- }; -- -- adma_lpuart0: serial@5a060000 { -- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -- reg = <0x5a060000 0x1000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, -- <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; -- clock-names = "ipg", "baud"; -- power-domains = <&pd IMX_SC_R_UART_0>; -- status = "disabled"; -- }; -- -- adma_lpuart1: serial@5a070000 { -- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -- reg = <0x5a070000 0x1000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, -- <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; -- clock-names = "ipg", "baud"; -- power-domains = <&pd IMX_SC_R_UART_1>; -- status = "disabled"; -- }; -- -- adma_lpuart2: serial@5a080000 { -- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -- reg = <0x5a080000 0x1000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, -- <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; -- clock-names = "ipg", "baud"; -- power-domains = <&pd IMX_SC_R_UART_2>; -- status = "disabled"; -- }; -- -- adma_lpuart3: serial@5a090000 { -- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; -- reg = <0x5a090000 0x1000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, -- <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; -- clock-names = "ipg", "baud"; -- power-domains = <&pd IMX_SC_R_UART_3>; -- status = "disabled"; -- }; -- -- adma_i2c0: i2c@5a800000 { -- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -- reg = <0x5a800000 0x4000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; -- clock-names = "per"; -- assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; -- assigned-clock-rates = <24000000>; -- power-domains = <&pd IMX_SC_R_I2C_0>; -- status = "disabled"; -- }; -- -- adma_i2c1: i2c@5a810000 { -- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -- reg = <0x5a810000 0x4000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; -- clock-names = "per"; -- assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; -- assigned-clock-rates = <24000000>; -- power-domains = <&pd IMX_SC_R_I2C_1>; -- status = "disabled"; -- }; -- -- adma_i2c2: i2c@5a820000 { -- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -- reg = <0x5a820000 0x4000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; -- clock-names = "per"; -- assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; -- assigned-clock-rates = <24000000>; -- power-domains = <&pd IMX_SC_R_I2C_2>; -- status = "disabled"; -- }; -- -- adma_i2c3: i2c@5a830000 { -- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; -- reg = <0x5a830000 0x4000>; -- interrupts = ; -- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; -- clock-names = "per"; -- assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; -- assigned-clock-rates = <24000000>; -- power-domains = <&pd IMX_SC_R_I2C_3>; -- status = "disabled"; -- }; -- }; -- -- conn_subsys: bus@5b000000 { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; -- -- conn_lpcg: clock-controller@5b200000 { -- compatible = "fsl,imx8qxp-lpcg-conn"; -- reg = <0x5b200000 0xb0000>; -- #clock-cells = <1>; -- }; -- -- usdhc1: mmc@5b010000 { -- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; -- interrupts = ; -- reg = <0x5b010000 0x10000>; -- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; -- clock-names = "ipg", "per", "ahb"; -- power-domains = <&pd IMX_SC_R_SDHC_0>; -- status = "disabled"; -- }; -- -- usdhc2: mmc@5b020000 { -- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; -- interrupts = ; -- reg = <0x5b020000 0x10000>; -- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; -- clock-names = "ipg", "per", "ahb"; -- power-domains = <&pd IMX_SC_R_SDHC_1>; -- fsl,tuning-start-tap = <20>; -- fsl,tuning-step= <2>; -- status = "disabled"; -- }; -- -- usdhc3: mmc@5b030000 { -- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; -- interrupts = ; -- reg = <0x5b030000 0x10000>; -- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; -- clock-names = "ipg", "per", "ahb"; -- power-domains = <&pd IMX_SC_R_SDHC_2>; -- status = "disabled"; -- }; -- -- fec1: ethernet@5b040000 { -- compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; -- reg = <0x5b040000 0x10000>; -- interrupts = , -- , -- , -- ; -- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; -- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; -- fsl,num-tx-queues=<3>; -- fsl,num-rx-queues=<3>; -- power-domains = <&pd IMX_SC_R_ENET_0>; -- status = "disabled"; -- }; -- -- fec2: ethernet@5b050000 { -- compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; -- reg = <0x5b050000 0x10000>; -- interrupts = , -- , -- , -- ; -- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, -- <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; -- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; -- fsl,num-tx-queues=<3>; -- fsl,num-rx-queues=<3>; -- power-domains = <&pd IMX_SC_R_ENET_1>; -- status = "disabled"; -- }; -- }; -- -- ddr_subsyss: bus@5c000000 { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; -- -- ddr-pmu@5c020000 { -- compatible = "fsl,imx8-ddr-pmu"; -- reg = <0x5c020000 0x10000>; -- interrupts = ; -- }; -- }; -- -- lsio_subsys: bus@5d000000 { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; -- -- lsio_gpio0: gpio@5d080000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d080000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_0>; -- }; -- -- lsio_gpio1: gpio@5d090000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d090000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_1>; -- }; -- -- lsio_gpio2: gpio@5d0a0000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d0a0000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_2>; -- }; -- -- lsio_gpio3: gpio@5d0b0000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d0b0000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_3>; -- }; -- -- lsio_gpio4: gpio@5d0c0000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d0c0000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_4>; -- }; -- -- lsio_gpio5: gpio@5d0d0000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d0d0000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_5>; -- }; -- -- lsio_gpio6: gpio@5d0e0000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d0e0000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_6>; -- }; -- -- lsio_gpio7: gpio@5d0f0000 { -- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; -- reg = <0x5d0f0000 0x10000>; -- interrupts = ; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- power-domains = <&pd IMX_SC_R_GPIO_7>; -- }; -- -- lsio_mu0: mailbox@5d1b0000 { -- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -- reg = <0x5d1b0000 0x10000>; -- interrupts = ; -- #mbox-cells = <2>; -- status = "disabled"; -- }; -- -- lsio_mu1: mailbox@5d1c0000 { -- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -- reg = <0x5d1c0000 0x10000>; -- interrupts = ; -- #mbox-cells = <2>; -- }; -- -- lsio_mu2: mailbox@5d1d0000 { -- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -- reg = <0x5d1d0000 0x10000>; -- interrupts = ; -- #mbox-cells = <2>; -- status = "disabled"; -- }; -- -- lsio_mu3: mailbox@5d1e0000 { -- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -- reg = <0x5d1e0000 0x10000>; -- interrupts = ; -- #mbox-cells = <2>; -- status = "disabled"; -- }; -- -- lsio_mu4: mailbox@5d1f0000 { -- compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -- reg = <0x5d1f0000 0x10000>; -- interrupts = ; -- #mbox-cells = <2>; -- status = "disabled"; -- }; -- -- lsio_mu13: mailbox@5d280000 { -- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -- reg = <0x5d280000 0x10000>; -- interrupts = ; -- #mbox-cells = <2>; -- power-domains = <&pd IMX_SC_R_MU_13A>; -- }; -- -- lsio_lpcg: clock-controller@5d400000 { -- compatible = "fsl,imx8qxp-lpcg-lsio"; -- reg = <0x5d400000 0x400000>; -- #clock-cells = <1>; -- }; -- }; -- - thermal_zones: thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; -@@ -629,4 +294,54 @@ map0 { - }; - }; - }; -+ -+ imx_ion { -+ compatible = "fsl,mxc-ion"; -+ fsl,heap-id = <0>; -+ }; -+ -+ sc_pwrkey: sc-powerkey { -+ compatible = "fsl,imx8-pwrkey"; -+ linux,keycode = ; -+ wakeup-source; -+ }; -+ -+ /* sorted in register address */ -+ #include "imx8-ss-security.dtsi" -+ #include "imx8-ss-cm40.dtsi" -+ #include "imx8-ss-vpu.dtsi" -+ #include "imx8-ss-dc0.dtsi" -+ #include "imx8-ss-adma.dtsi" -+ #include "imx8-ss-conn.dtsi" -+ #include "imx8-ss-ddr.dtsi" -+ #include "imx8-ss-lsio.dtsi" -+ #include "imx8-ss-hsio.dtsi" -+ #include "imx8-ss-img.dtsi" -+ #include "imx8-ss-gpu0.dtsi" -+ #include "imx8-ss-lcdif.dtsi" -+}; -+ -+#include "imx8qxp-ss-adma.dtsi" -+#include "imx8qxp-ss-conn.dtsi" -+#include "imx8qxp-ss-lsio.dtsi" -+#include "imx8qxp-ss-hsio.dtsi" -+#include "imx8qxp-ss-img.dtsi" -+#include "imx8qxp-ss-dc.dtsi" -+#include "imx8qxp-ss-lvds.dtsi" -+#include "imx8qxp-ss-gpu.dtsi" -+ -+&edma2 { -+ status = "okay"; -+}; -+ -+&A35_0 { -+ operating-points = < -+ /* kHz uV*/ -+ /* voltage is maintained by SCFW, so no need here */ -+ 1200000 0 -+ 900000 0 -+ >; -+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; -+ clock-latency = <61036>; -+ #cooling-cells = <2>; - }; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts -new file mode 100644 -index 000000000..92860fa6a ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts -@@ -0,0 +1,162 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk-rk055hdmipi4m.dts" -+ -+/ { -+ sound-spdif { -+ status = "disabled"; -+ }; -+}; -+ -+&i2c_rpbus_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ fp9931: fp9931@18 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pf9931>; -+ compatible = "fitipower,fp9931"; -+ reg = <0x18>; -+ status = "okay"; -+ -+ /* power up and down timings in mseconds */ -+ vgl-pwrup = <1>; -+ vneg-pwrup = <1>; -+ vgh-pwrup = <1>; -+ vpos-pwrup = <1>; -+ ss-time = <3>; -+ gpio-pmic-pwrgood = <&gpioe 17 0>; -+ gpio-pmic-wakeup = <&gpioe 18 0>; -+ -+ /* enable sequence for panel VB3300: -+ * -+ * V3P3->VGL->VNEG->VGH->VPOS->VCOM -+ */ -+ regulators { -+#if 0 /* could use EPDC_GPIO */ -+ en_reg: DISPLAY { -+ regulator-name = "DISPLAY"; -+ regulator-soft-start; -+ }; -+#endif -+ -+ /* fifth enabe VPOS */ -+ vpos_reg: VPOS-LDO { -+ regulator-name = "VPOS"; -+ regulator-min-microvolt = <7040000>; -+ regulator-max-microvolt = <15060000>; -+ }; -+ -+ /* third enable VNEG */ -+ vneg_reg: VNEG-LDO { -+ regulator-name = "VNEG"; -+ /* Real max value: -7040000 uV */ -+ regulator-min-microvolt = <7040000>; -+ /* Real min value: -15060000 uV */ -+ regulator-max-microvolt = <15060000>; -+ }; -+ -+ /* fourth enable VGH */ -+ vgh_reg: VGH-CHARGE-PUMP { -+ /* 15V to 30V with External Dividual Resistor */ -+ regulator-name = "VGH"; -+ }; -+ -+ /* second enable VGL */ -+ vgl_reg: VGL-CHARGE-PUMP { -+ /* -15V to -25V with External Dividual Resistor */ -+ regulator-name = "VGL"; -+ }; -+ -+ /* last enable VCOM */ -+ vcom_reg: VCOM { -+ regulator-name = "VCOM"; -+ /* Real max value: -19608 uV */ -+ regulator-min-microvolt = <19608>; -+ /* Real min value: -5000000 uV */ -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ /* V3P3 is the first power need to be enabled -+ * according to VB3300 panel spec. -+ */ -+ v3p3_reg: V3P3 { -+ regulator-name = "V3P3"; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc1 { -+ pinctrl_pf9931: pf9931grp-1 { -+ fsl,pins = < -+ MX8ULP_PAD_PTE17__PTE17 0x80000000 /* pwrgood */ -+ MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x80000000 /* wakeup */ -+ >; -+ }; -+ -+ pinctrl_epdc0: epdcgrp0 { -+ fsl,pins = < -+ MX8ULP_PAD_PTF23__EPDC0_D0 0x43 -+ MX8ULP_PAD_PTF22__EPDC0_D1 0x43 -+ MX8ULP_PAD_PTF21__EPDC0_D2 0x43 -+ MX8ULP_PAD_PTF20__EPDC0_D3 0x43 -+ MX8ULP_PAD_PTF19__EPDC0_D4 0x43 -+ MX8ULP_PAD_PTF18__EPDC0_D5 0x43 -+ MX8ULP_PAD_PTF17__EPDC0_D6 0x43 -+ MX8ULP_PAD_PTF16__EPDC0_D7 0x43 -+ MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x43 -+ MX8ULP_PAD_PTF25__EPDC0_GDSP 0x43 -+ MX8ULP_PAD_PTF26__EPDC0_SDLE 0x43 -+ MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x43 -+ -+ MX8ULP_PAD_PTF0__EPDC0_SDOE 0x43 -+ MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x43 -+ MX8ULP_PAD_PTE20__EPDC0_GDOE 0x43 -+ MX8ULP_PAD_PTE21__EPDC0_GDRL 0x43 -+ -+ >; -+ }; -+}; -+ -+&epdc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_epdc0>; -+ en-gpios = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; /* switch */ -+ V3P3-supply = <&v3p3_reg>; -+ VCOM-supply = <&vcom_reg>; -+ VPOS-supply = <&vpos_reg>; -+ VNEG-supply = <&vneg_reg>; -+#if 0 -+ DISPLAY-supply = <&en_reg>; -+#endif -+ status = "okay"; -+}; -+ -+&epxp { -+ status = "okay"; -+}; -+ -+&fec { -+ status = "disabled"; -+}; -+ -+&sai5 { /* conflict PAD_PTF23 */ -+ status = "disabled"; -+}; -+ -+&spdif {/* conflict PAD_PTF25 */ -+ status = "disabled"; -+}; -+ -+&lpspi5 {/* conflict PAD_PTF19 */ -+ status = "disabled"; -+}; -+ -+&lpuart7 {/* conflict PAD_PTF23 */ -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts -new file mode 100644 -index 000000000..41eccbe2b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts -@@ -0,0 +1,46 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk.dts" -+ -+/{ -+ aliases { -+ i2c8 = &flexio_i2c_master; -+ }; -+}; -+ -+&lpi2c7 { -+ status = "disabled"; -+ /delete-node/ gpio@21; -+}; -+ -+&flexio_i2c_master { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_flexio_i2c_master>; -+ pinctrl-1 = <&pinctrl_flexio_i2c_master>; -+ sda = /bits/ 8 <0xa>; -+ scl = /bits/ 8 <0xb>; -+ status = "okay"; -+ -+ pcal6408: gpio@21 { -+ compatible = "nxp,pcal9554b"; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ status = "okay"; -+ }; -+}; -+ -+&iomuxc1 { -+ pinctrl_flexio_i2c_master: flexiogrp { -+ fsl,pins = < -+ MX8ULP_PAD_PTE12__FXIO1_D11 0x20 -+ MX8ULP_PAD_PTE13__FXIO1_D10 0x20 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts -new file mode 100644 -index 000000000..ffc0dd197 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk.dts" -+ -+&fec { -+ status = "disabled"; -+}; -+ -+&lpspi5 { -+ status = "disabled"; -+}; -+ -+&i2c_rpbus_0 { -+ /delete-node/lsm6dsm@6a; -+}; -+ -+&i3c2 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_i3c2>; -+ pinctrl-1 = <&pinctrl_i3c2>; -+ pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; -+ i2c-scl-hz = <400000>; -+ status = "okay"; -+ -+ lsm6dso_i3c: imu@6a,208006c0000 { -+ reg = <0x6a 0x208 0x6c0000>; -+ assigned-address = <0x6a>; -+ }; -+}; -+ -+&iomuxc1 { -+ pinctrl_i3c2: i3c2grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTE15__I3C2_PUR 0x3 -+ MX8ULP_PAD_PTE22__I3C2_SCL 0x3 -+ MX8ULP_PAD_PTE23__I3C2_SDA 0x3 -+ >; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts -new file mode 100644 -index 000000000..2f1a8f691 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk.dts" -+ -+/delete-node/&spidev0; -+ -+&pinctrl_lpspi5 { -+ fsl,pins = < -+ MX8ULP_PAD_PTF16__LPSPI5_SIN 0x3 -+ MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x3 -+ MX8ULP_PAD_PTF18__LPSPI5_SCK 0x3 -+ MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x3 -+ >; -+}; -+ -+&lpspi5 { -+ #address-cells = <0>; -+ pinctrl-0 = <&pinctrl_lpspi5>; -+ pinctrl-1 = <&pinctrl_lpspi5>; -+ /delete-property/ cs-gpios; -+ -+ spi-slave; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts -new file mode 100644 -index 000000000..23d655bcf ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk.dts" -+ -+&gpu3d { -+ assigned-clock-rates = <200000000>, <200000000>, <200000000>; -+}; -+ -+&gpu2d { -+ assigned-clock-rates = <200000000>, <200000000>, <200000000>; -+}; -+ -+&dcnano { -+ /* Place Holder */ -+}; -+ -+&mipi_csi0 { -+ assigned-clock-rates = <396000000>, -+ <176000000>, -+ <132000000>, -+ <396000000>, -+ <176000000>, -+ <132000000>, -+ <79200000>; -+}; -+ -+&epdc { -+ /* Place Holder */ -+}; -+ -+&dsp { -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>; -+ assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>; -+ assigned-clock-rates = <0>, <260000000>; -+}; -+ -+&i3c2 { -+ assigned-clock-rates = <24000000>; -+}; -+ -+&usdhc0 { -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC0>; -+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; -+ assigned-clock-rates = <198000000>, <198000000>; -+}; -+ -+&usdhc1 { -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC1>; -+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; -+ assigned-clock-rates = <198000000>, <198000000>; -+}; -+ -+&usdhc2 { -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC2>; -+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; -+ assigned-clock-rates = <198000000>, <198000000>; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts -new file mode 100644 -index 000000000..e9629e6ad ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk.dts" -+ -+/ { -+ pwm_backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&tpm_rpchip_0 2 50000 0>; -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <100>; -+ }; -+}; -+ -+/delete-node/ &ite_bridge; -+ -+&dsi { -+ panel@0 { -+ compatible = "raydium,rm68200"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_dsi>; -+ enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; -+ power-supply = <®_5v>; -+ backlight = <&pwm_backlight>; -+ -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_rpbus_1 { -+ goodix@14 { -+ compatible = "goodix,gt911"; -+ reg = <0x14>; -+ interrupt-parent = <&rpmsg_gpiob>; -+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; -+ irq-gpios = <&rpmsg_gpiob 5 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; -+ touchscreen-size-x = <720>; -+ touchscreen-size-y = <1280>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts -new file mode 100644 -index 000000000..26c4692d7 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts -@@ -0,0 +1,111 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "imx8ulp-evk.dts" -+ -+/ { -+ reserved-memory { -+ /delete-node/ dsp_reserved; -+ /delete-node/ dsp_reserved_heap; -+ /delete-node/ dsp_vdev0vring0; -+ /delete-node/ dsp_vdev0vring1; -+ /delete-node/ dsp_vdev0buffer; -+ dsp_reserved0: dsp@8e000000 { -+ reg = <0 0x8e000000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved1: dsp@8f000000 { -+ compatible = "shared-dma-pool"; -+ memory-region-names = "dsp_mem"; -+ reg = <0 0x8f000000 0 0x1000000>; -+ no-map; -+ }; -+ }; -+ -+ sound-bt-sco { -+ status = "disabled"; -+ }; -+ -+ sof-sound-btsco { -+ compatible = "simple-audio-card"; -+ label = "btsco-audio"; -+ simple-audio-card,name = "bt-dsp-a"; -+ simple-audio-card,bitclock-master = <&cpudai>; -+ simple-audio-card,frame-master = <&cpudai>; -+ -+ simple-audio-card,dai-link { -+ format = "i2s"; -+ cpudai: cpu { -+ sound-dai = <&dsp>; -+ }; -+ sndcodec: codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ }; -+}; -+ -+&rpmsg_audio { -+ status = "okay"; -+}; -+ -+&sai5 { -+ status = "disabled"; -+}; -+ -+&sai6 { -+ status = "disabled"; -+}; -+ -+&edma2 { -+ status = "disabled"; -+}; -+ -+&mu3 { -+ status = "okay"; -+}; -+ -+&dsp { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,imx8ulp-dsp"; -+ memory-reserved = <&dsp_reserved0>; -+ memory-region = <&dsp_reserved1>; -+ reg = <0x21170000 0x20000>; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ pinctrl-1 = <&pinctrl_sai5>; -+ -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc1 IMX8ULP_CLK_SAI5_SEL>; -+ assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; -+ -+ clocks = <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, -+ <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, -+ <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>, -+ <&pcc5 IMX8ULP_CLK_MU3_B>, -+ <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_SAI5_SEL>, -+ <&pcc5 IMX8ULP_CLK_DMA2_MP>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>; -+ clock-names = "core", "pbclk", "nic", "mu_b", -+ "bus", "mclk0", "mclk1", -+ "edma-mp-clk", -+ "edma2-chan0-clk", "edma2-chan1-clk", -+ "edma2-chan2-clk", "edma2-chan3-clk", -+ "edma2-chan4-clk", "edma2-chan5-clk", -+ "edma2-chan6-clk", "edma2-chan7-clk"; -+ -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&mu3 2 0>, -+ <&mu3 2 1>, -+ <&mu3 3 0>, -+ <&mu3 3 1>; -+ /delete-property/ firmware-name; -+ tplg-name = "sof-imx8ulp-btsco.tplg"; -+ machine-drv-name = "asoc-simple-card"; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts -new file mode 100644 -index 000000000..82bc2a85b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts -@@ -0,0 +1,669 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "imx8ulp.dtsi" -+#include "imx8ulp-rpmsg.dtsi" -+#include -+ -+/ { -+ model = "NXP i.MX8ULP EVK"; -+ compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; -+ -+ chosen { -+ stdout-path = &lpuart5; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_keys>; -+ -+ power-on { -+ label = "PowerOn"; -+ gpios = <&gpiof 31 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ }; -+ -+ rpmsg_keys: rpmsg-keys { -+ compatible = "fsl,rpmsg-keys"; -+ -+ volume-up { -+ label = "VolumeUp"; -+ linux,code = ; -+ rpmsg-key,wakeup; -+ }; -+ -+ volume-down { -+ label = "VolumeDown"; -+ linux,code = ; -+ rpmsg-key,wakeup; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ linux,cma-default; -+ }; -+ -+ rsc_table: rsc_table@1fff8000{ -+ reg = <0 0x1fff8000 0 0x1000>; -+ no-map; -+ }; -+ -+ dsp_reserved: dsp_reserved@8e000000 { -+ reg = <0 0x8e000000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x8f000000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@8fef0000 { -+ reg = <0 0x8fef0000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0vring1: vdev0vring1@8fef8000 { -+ reg = <0 0x8fef8000 0 0x8000>; -+ no-map; -+ }; -+ dsp_vdev0buffer: vdev0buffer@8ff00000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x8ff00000 0 0x100000>; -+ no-map; -+ }; -+ -+ vdev0vring0: vdev0vring0@aff00000 { -+ reg = <0 0xaff00000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@aff08000 { -+ reg = <0 0xaff08000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring0: vdev1vring0@aff10000 { -+ reg = <0 0xaff10000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring1: vdev1vring1@aff18000 { -+ reg = <0 0xaff18000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer@a8400000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0xa8400000 0 0x100000>; -+ no-map; -+ }; -+ -+ audio_reserved: audio@0xa8500000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0xa8500000 0 0x100000>; -+ }; -+ }; -+ -+ reg_5v: regulator-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ usdhc2_pwrseq: usdhc2_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; -+ }; -+ -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai5>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif>; -+ spdif-out; -+ fsl,constraint-rate = <16000>, <32000>, <48000>, -+ <64000>, <96000>, <192000>; -+ }; -+ -+ rpmsg_audio: rpmsg-audio { -+ compatible = "fsl,imx8ulp-rpmsg-audio"; -+ model = "wm8960-audio"; -+ fsl,rpmsg-out; -+ fsl,rpmsg-in; -+ audio-codec = <&wm8960>; -+ memory-region = <&audio_reserved>; -+ audio-routing = -+ "LINPUT1", "MICB", -+ "LINPUT3", "MICB"; -+ status = "okay"; -+ }; -+}; -+ -+&dcnano { -+ status = "okay"; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&dsi { -+ status = "okay"; -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&it6161_from_dsim>; -+ }; -+ }; -+ }; -+}; -+ -+&dsp { -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>; -+ assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4>; -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ status = "okay"; -+}; -+ -+&clock_ext_ts { -+ /* External ts clock is 50MHZ from PHY on EVK board. */ -+ clock-frequency = <50000000>; -+}; -+ -+&fec { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_enet>; -+ pinctrl-1 = <&pinctrl_enet>; -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; -+ assigned-clock-parents = <&clock_ext_ts>; -+ phy-mode = "rmii"; -+ phy-handle = <ðphy>; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy: ethernet-phy { -+ reg = <1>; -+ micrel,led-mode = <1>; -+ }; -+ }; -+}; -+ -+&flexspi2 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_flexspi2_ptd>; -+ pinctrl-1 = <&pinctrl_flexspi2_ptd>; -+ status = "okay"; -+ -+ mx25uw51345gxdi00: flash@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <200000000>; -+ spi-tx-bus-width = <8>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&i2c_rpbus_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pca6416_1: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ mpl3115@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ }; -+ -+ lsm6dsm@6a { -+ compatible = "st,lsm6dso"; -+ reg = <0x6a>; -+ }; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960,lpa"; -+ reg = <0x1a>; -+ wlf,shared-lrclk; -+ clocks = <&wm8960_mclk>; -+ clock-names = "mclk"; -+ }; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>; -+ clock-names = "xclk"; -+ powerdown-gpios = <&pca6416_1 8 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ port { -+ ov5640_mipi_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2>; -+ clocks-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ ite_bridge: it6161@6c { -+ compatible = "ite,it6161"; -+ reg = <0x6c>; -+ it6161-addr-hdmi-tx = <0x4c>; -+ enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_LOW>; -+ interrupt-parent = <&rpmsg_gpioa>; -+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port { -+ it6161_from_dsim: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_rpbus_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+}; -+ -+&imx8ulp_cm33 { -+ ipc-only; -+ rsc-da=<0x1fff8000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, -+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; -+ status = "okay"; -+}; -+ -+&lpspi5 { -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_lpspi5>; -+ pinctrl-1 = <&pinctrl_lpspi5>; -+ cs-gpios = <&gpiof 19 GPIO_ACTIVE_LOW>; -+ pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ reg = <0>; -+ compatible = "lwn,bk4"; -+ spi-max-frequency = <1000000>; -+ }; -+}; -+ -+&lpuart5 { -+ /* console */ -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_lpuart5>; -+ pinctrl-1 = <&pinctrl_lpuart5>; -+ status = "okay"; -+}; -+ -+&lpuart6 { -+ /* BT */ -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_lpuart6>; -+ pinctrl-1 = <&pinctrl_lpuart6>; -+ status = "okay"; -+}; -+ -+&lpuart7 { -+ /* FT4232 PortD: need to connect J25/J26 2-3 */ -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_lpuart7>; -+ pinctrl-1 = <&pinctrl_lpuart7>; -+ status = "okay"; -+}; -+ -+&lpi2c7 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <400000>; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_lpi2c7>; -+ pinctrl-1 = <&pinctrl_lpi2c7>; -+ status = "okay"; -+ -+ pcal6408: gpio@21 { -+ compatible = "nxp,pcal9554b"; -+ reg = <0x21>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&mu { -+ status = "okay"; -+}; -+ -+&mu3 { -+ status = "okay"; -+}; -+ -+&tpm_rpchip_0 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_otgid1>; -+ pinctrl-1 = <&pinctrl_otgid1>; -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ over-current-active-low; -+ status = "okay"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbmisc1 { -+ status = "okay"; -+}; -+ -+&usbotg2 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_otgid2>; -+ pinctrl-1 = <&pinctrl_otgid2>; -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ over-current-active-low; -+ status = "okay"; -+}; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usbmisc2 { -+ status = "okay"; -+}; -+ -+&usdhc0 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; -+ pinctrl-0 = <&pinctrl_usdhc0>; -+ pinctrl-1 = <&pinctrl_usdhc0>; -+ pinctrl-2 = <&pinctrl_usdhc0>; -+ pinctrl-3 = <&pinctrl_usdhc0>; -+ non-removable; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; -+ pinctrl-0 = <&pinctrl_usdhc2_pte>; -+ pinctrl-1 = <&pinctrl_usdhc2_pte>; -+ pinctrl-2 = <&pinctrl_usdhc2_pte>; -+ pinctrl-3 = <&pinctrl_usdhc2_pte>; -+ mmc-pwrseq = <&usdhc2_pwrseq>; -+ max-frequency = <100000000>; -+ bus-width = <4>; -+ keep-power-in-suspend; -+ non-removable; -+ fsl,sdio-interrupt-enabled; -+ wakeup-source; -+ status = "okay"; -+ -+ wifi_wake_host { -+ compatible = "nxp,wifi-wake-host"; -+ interrupt-parent = <&gpioe>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&iomuxc1 { -+ pinctrl_dsi: dsigrp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF8__PTF8 0x3 -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX8ULP_PAD_PTE15__ENET0_MDC 0x43 -+ MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 -+ MX8ULP_PAD_PTE17__ENET0_RXER 0x43 -+ MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 -+ MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 -+ MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 -+ MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 -+ MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 -+ MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 -+ MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 -+ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 -+ >; -+ }; -+ -+ pinctrl_flexspi2_ptd: flexspi2ptdgrp { -+ fsl,pins = < -+ -+ MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 -+ MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 -+ MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 -+ MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 -+ MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 -+ MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 -+ MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 -+ MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 -+ MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 -+ MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 -+ MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 -+ >; -+ }; -+ -+ pinctrl_gpio_keys: gpiokeys { -+ fsl,pins = < -+ MX8ULP_PAD_PTF31__PTF31 0x3 -+ >; -+ }; -+ -+ pinctrl_lpspi5: lpspi5grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF16__LPSPI5_SIN 0x3 -+ MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x3 -+ MX8ULP_PAD_PTF18__LPSPI5_SCK 0x3 -+ MX8ULP_PAD_PTF19__PTF19 0x3 -+ >; -+ }; -+ -+ pinctrl_lpuart5: lpuart5grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF14__LPUART5_TX 0x3 -+ MX8ULP_PAD_PTF15__LPUART5_RX 0x3 -+ >; -+ }; -+ -+ pinctrl_lpuart6: lpuart6grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTE10__LPUART6_TX 0x3 -+ MX8ULP_PAD_PTE11__LPUART6_RX 0x3 -+ MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x3 -+ MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3 -+ >; -+ }; -+ -+ pinctrl_lpuart7: lpuart7grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF22__LPUART7_TX 0x3 -+ MX8ULP_PAD_PTF23__LPUART7_RX 0x3 -+ >; -+ }; -+ -+ pinctrl_lpi2c7: lpi2c7grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 -+ MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 -+ >; -+ }; -+ -+ pinctrl_otgid1: usb1grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF2__USB0_ID 0x10003 -+ MX8ULP_PAD_PTF4__USB0_OC 0x10003 -+ >; -+ }; -+ -+ pinctrl_otgid2: usb2grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTD23__USB1_ID 0x10003 -+ MX8ULP_PAD_PTF6__USB1_OC 0x10003 -+ >; -+ }; -+ -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43 -+ MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43 -+ MX8ULP_PAD_PTF28__I2S5_TXD0 0x43 -+ MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 -+ >; -+ }; -+ -+ pinctrl_spdif: spdifgrp { -+ fsl,pins = < -+ MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43 -+ >; -+ }; -+ -+ pinctrl_usdhc0: usdhc0grp { -+ fsl,pins = < -+ MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 -+ MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 -+ MX8ULP_PAD_PTD10__SDHC0_D0 0x3 -+ MX8ULP_PAD_PTD9__SDHC0_D1 0x3 -+ MX8ULP_PAD_PTD8__SDHC0_D2 0x3 -+ MX8ULP_PAD_PTD7__SDHC0_D3 0x3 -+ MX8ULP_PAD_PTD6__SDHC0_D4 0x3 -+ MX8ULP_PAD_PTD5__SDHC0_D5 0x3 -+ MX8ULP_PAD_PTD4__SDHC0_D6 0x3 -+ MX8ULP_PAD_PTD3__SDHC0_D7 0x3 -+ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 -+ >; -+ }; -+ -+ pinctrl_usdhc2_pte: usdhc2ptegrp { -+ fsl,pins = < -+ MX8ULP_PAD_PTE1__SDHC2_D0 0x3 -+ MX8ULP_PAD_PTE0__SDHC2_D1 0x3 -+ MX8ULP_PAD_PTE5__SDHC2_D2 0x3 -+ MX8ULP_PAD_PTE4__SDHC2_D3 0x3 -+ MX8ULP_PAD_PTE2__SDHC2_CLK 0x10002 -+ MX8ULP_PAD_PTE3__SDHC2_CMD 0x3 -+ MX8ULP_PAD_PTE7__PTE7 0x10003 -+ >; -+ }; -+ -+}; -+ -+&sai5 { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ pinctrl-1 = <&pinctrl_sai5>; -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; -+ fsl,dataline = <0 0x08 0x01>; -+ status = "okay"; -+}; -+ -+&spdif { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&pinctrl_spdif>; -+ pinctrl-1 = <&pinctrl_spdif>; -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; -+ status = "okay"; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "okay"; -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ }; -+}; -+ -+&epxp { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h -new file mode 100755 -index 000000000..faa702634 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h -@@ -0,0 +1,978 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#ifndef __DTS_IMX8ULP_PINFUNC_H -+#define __DTS_IMX8ULP_PINFUNC_H -+ -+/* -+ * The pin function ID is a tuple of -+ * -+ */ -+#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 -+#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 -+#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 -+#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 -+#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 -+#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 -+#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 -+#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1 -+#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 -+#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1 -+#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1 -+#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1 -+#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1 -+#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1 -+#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1 -+#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1 -+#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1 -+#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1 -+#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1 -+#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1 -+#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1 -+#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1 -+#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1 -+#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1 -+#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2 -+#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1 -+#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1 -+#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1 -+#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1 -+#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1 -+#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1 -+#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1 -+#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1 -+#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1 -+#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1 -+#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1 -+#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1 -+#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1 -+#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1 -+#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1 -+#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1 -+#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1 -+#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 -+#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1 -+#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1 -+#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1 -+#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1 -+#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1 -+#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 -+#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2 -+#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1 -+#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1 -+#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1 -+#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1 -+#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 -+#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 -+#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2 -+#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1 -+#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1 -+#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1 -+#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2 -+#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1 -+#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1 -+#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1 -+#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 -+#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2 -+#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1 -+#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1 -+#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1 -+#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 -+#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1 -+#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2 -+#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1 -+#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1 -+#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 -+#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1 -+#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2 -+#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1 -+#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1 -+#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 -+#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1 -+#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2 -+#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1 -+#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1 -+#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 -+#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1 -+#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1 -+#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 -+#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1 -+#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2 -+#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2 -+#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1 -+#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1 -+#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1 -+#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3 -+#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1 -+#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2 -+#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2 -+#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1 -+#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1 -+#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2 -+#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1 -+#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1 -+#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3 -+#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4 -+#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2 -+#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2 -+#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1 -+#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1 -+#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3 -+#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2 -+#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2 -+#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1 -+#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1 -+#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1 -+#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1 -+#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3 -+#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2 -+#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2 -+#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2 -+#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1 -+#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2 -+#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1 -+#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3 -+#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2 -+#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2 -+#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1 -+#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1 -+#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1 -+#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3 -+#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2 -+#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1 -+#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2 -+#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1 -+#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1 -+#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2 -+#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1 -+#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1 -+#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1 -+#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2 -+#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1 -+#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2 -+#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1 -+#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1 -+#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2 -+#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1 -+#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1 -+#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1 -+#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2 -+#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1 -+#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2 -+#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1 -+#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1 -+#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2 -+#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1 -+#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1 -+#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2 -+#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1 -+#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2 -+#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1 -+#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1 -+#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2 -+#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1 -+#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1 -+#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1 -+#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2 -+#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1 -+#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2 -+#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1 -+#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1 -+#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1 -+#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1 -+#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1 -+#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2 -+#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1 -+#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1 -+#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2 -+#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1 -+#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1 -+#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1 -+#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1 -+#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1 -+#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2 -+#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1 -+#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1 -+#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2 -+#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1 -+#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1 -+#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2 -+#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1 -+#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1 -+#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1 -+#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2 -+#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1 -+#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1 -+#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2 -+#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1 -+#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1 -+#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1 -+#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1 -+#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2 -+#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2 -+#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1 -+#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2 -+#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1 -+#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1 -+#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2 -+#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1 -+#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1 -+#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1 -+#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2 -+#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2 -+#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2 -+#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2 -+#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1 -+#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1 -+#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2 -+#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2 -+#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0 -+#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2 -+#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1 -+#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1 -+#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1 -+#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2 -+#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2 -+#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2 -+#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1 -+#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1 -+#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1 -+#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2 -+#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1 -+#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2 -+#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1 -+#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1 -+#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1 -+#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2 -+#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2 -+#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1 -+#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5 -+#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1 -+#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1 -+#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2 -+#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2 -+#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1 -+#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1 -+#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2 -+#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2 -+#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2 -+#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2 -+#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2 -+#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2 -+#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3 -+#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2 -+#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2 -+#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2 -+#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2 -+#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2 -+#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2 -+#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2 -+#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2 -+#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2 -+#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2 -+#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3 -+#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2 -+#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2 -+#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2 -+#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2 -+#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2 -+#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2 -+#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3 -+#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2 -+#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2 -+#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1 -+#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2 -+#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2 -+#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3 -+#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2 -+#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3 -+#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2 -+#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1 -+#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2 -+#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2 -+#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2 -+#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0 -+#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2 -+#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3 -+#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2 -+#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3 -+#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1 -+#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2 -+#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2 -+#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3 -+#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2 -+#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2 -+#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3 -+#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1 -+#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2 -+#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2 -+#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2 -+#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3 -+#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3 -+#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3 -+#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1 -+#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2 -+#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2 -+#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2 -+#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3 -+#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3 -+#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1 -+#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2 -+#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2 -+#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0 -+#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2 -+#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3 -+#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3 -+#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3 -+#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1 -+#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2 -+#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2 -+#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2 -+#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3 -+#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3 -+#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2 -+#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2 -+#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2 -+#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2 -+#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3 -+#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3 -+#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2 -+#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1 -+#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2 -+#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2 -+#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2 -+#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3 -+#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2 -+#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1 -+#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2 -+#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2 -+#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2 -+#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3 -+#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3 -+#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2 -+#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2 -+#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2 -+#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3 -+#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2 -+#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3 -+#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2 -+#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2 -+#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2 -+#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3 -+#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3 -+#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2 -+#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3 -+#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2 -+#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2 -+#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2 -+#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3 -+#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2 -+#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3 -+#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2 -+#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0 -+#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2 -+#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2 -+#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3 -+#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3 -+#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2 -+#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3 -+#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2 -+#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2 -+#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3 -+#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2 -+#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3 -+#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2 -+#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3 -+#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3 -+#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2 -+#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3 -+#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2 -+#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2 -+#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0 -+#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3 -+#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2 -+#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2 -+#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2 -+#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2 -+#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3 -+#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3 -+#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3 -+#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2 -+#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2 -+#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2 -+#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2 -+#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3 -+#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0 -+#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2 -+#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2 -+#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0 -+#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2 -+#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3 -+#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4 -+#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2 -+#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0 -+#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2 -+#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4 -+#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2 -+#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2 -+#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3 -+#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2 -+#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3 -+#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2 -+#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2 -+#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2 -+#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2 -+#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0 -+#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2 -+#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3 -+#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2 -+#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2 -+#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2 -+#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0 -+#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2 -+#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2 -+#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2 -+#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0 -+#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0 -+#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2 -+#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2 -+#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0 -+#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0 -+#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0 -+#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0 -+#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0 -+#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0 -+#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0 -+ -+#endif /* __DTS_IMX8ULP_PINFUNC_H */ -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi -new file mode 100644 -index 000000000..abb27b805 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+/ { -+ aliases { -+ gpio0 = &rpmsg_gpioa; -+ gpio1 = &rpmsg_gpiob; -+ i2c0 = &i2c_rpbus_0; -+ i2c1 = &i2c_rpbus_1; -+ pwm0 = &tpm_rpchip_0; -+ }; -+ -+ wm8960_mclk: wm8960-mclk { -+ compatible = "fixed-clock"; -+ clock-frequency = <12288000>; -+ clock-output-names = "wm8960_mclk"; -+ #clock-cells = <0>; -+ }; -+ -+ imx8ulp_cm33: imx8ulp-cm33 { -+ compatible = "fsl,imx8ulp-cm33", "fsl,imx7ulp-cm4"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_0: i2c-rpbus-0 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ i2c_rpbus_1: i2c-rpbus-1 { -+ compatible = "fsl,i2c-rpbus"; -+ status = "disabled"; -+ }; -+ -+ rpmsg_gpioa: gpio@0 { -+ compatible = "fsl,imx-rpmsg-gpio"; -+ port_idx = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&rpmsg_gpioa>; -+ status = "okay"; -+ }; -+ -+ rpmsg_gpiob: gpio@1 { -+ compatible = "fsl,imx-rpmsg-gpio"; -+ port_idx = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ interrupt-parent = <&rpmsg_gpiob>; -+ status = "okay"; -+ }; -+ -+ tpm_rpchip_0: pwm { -+ compatible = "fsl,pwm-rpchip"; -+ #pwm-cells = <3>; -+ fsl,pwm-channel-number = <6>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi -new file mode 100644 -index 000000000..0b6227da6 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi -@@ -0,0 +1,1309 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "imx8ulp-pinfunc.h" -+ -+/ { -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fec; -+ gpio4 = &gpiod; -+ gpio5 = &gpioe; -+ gpio6 = &gpiof; -+ i2c4 = &lpi2c4; -+ i2c5 = &lpi2c5; -+ i2c6 = &lpi2c6; -+ i2c7 = &lpi2c7; -+ mmc0 = &usdhc0; -+ mmc1 = &usdhc1; -+ mmc2 = &usdhc2; -+ serial0 = &lpuart4; -+ serial1 = &lpuart5; -+ serial2 = &lpuart6; -+ serial3 = &lpuart7; -+ usbphy0 = &usbphy1; -+ usbphy1 = &usbphy2; -+ isi0 = &isi_0; -+ csi0 = &mipi_csi0; -+ }; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ A35_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35"; -+ reg = <0x0 0x0>; -+ enable-method = "psci"; -+ next-level-cache = <&A35_L2>; -+ cpu-idle-states = <&cpu_sleep>; -+ }; -+ -+ A35_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35"; -+ reg = <0x0 0x1>; -+ enable-method = "psci"; -+ next-level-cache = <&A35_L2>; -+ cpu-idle-states = <&cpu_sleep>; -+ }; -+ -+ A35_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ -+ idle-states { -+ entry-method = "psci"; -+ -+ cpu_sleep: cpu-sleep { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ }; -+ }; -+ }; -+ -+ gic: interrupt-controller@2d400000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ -+ gpu: gpu { -+ compatible = "fsl,imx8-gpu-ss"; -+ cores = <&gpu3d>, <&gpu2d>; -+ reg = <0x0 0x80000000 0x0 0x80000000>, -+ <0x0 0x0 0x0 0x08000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a35-pmu"; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ interrupt-affinity = <&A35_0>, <&A35_1>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&scmi_sensor>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit0: trip1 { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ }; -+ -+ frosc: clock-frosc { -+ compatible = "fixed-clock"; -+ clock-frequency = <192000000>; -+ clock-output-names = "frosc"; -+ #clock-cells = <0>; -+ }; -+ -+ lposc: clock-lposc { -+ compatible = "fixed-clock"; -+ clock-frequency = <1000000>; -+ clock-output-names = "lposc"; -+ #clock-cells = <0>; -+ }; -+ -+ rosc: clock-rosc { -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "rosc"; -+ #clock-cells = <0>; -+ }; -+ -+ sosc: clock-sosc { -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "sosc"; -+ #clock-cells = <0>; -+ }; -+ -+ clock_ext_rmii: clock-ext-rmii { -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+ #clock-cells = <0>; -+ clock-output-names = "ext_rmii_clk"; -+ }; -+ -+ clock_ext_ts: clock-ext-ts { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-output-names = "ext_ts_clk"; -+ }; -+ -+ sram@2201f000 { -+ compatible = "mmio-sram"; -+ reg = <0x0 0x2201f000 0x0 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x2201f000 0x1000>; -+ -+ scmi_buf: scmi_buf@0 { -+ compatible = "arm,scmi-shmem"; -+ reg = <0x0 0x400>; -+ }; -+ }; -+ -+ firmware { -+ scmi { -+ compatible = "arm,scmi-smc"; -+ arm,smc-id = <0xc20000fe>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ shmem = <&scmi_buf>; -+ -+ scmi_devpd: protocol@11 { -+ reg = <0x11>; -+ #power-domain-cells = <1>; -+ }; -+ -+ scmi_sensor: protocol@15 { -+ reg = <0x15>; -+ #thermal-sensor-cells = <0>; -+ }; -+ }; -+ }; -+ -+ rtc-rpmsg { -+ compatible = "fsl,imx-rpmsg-rtc"; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x40000000>, -+ <0x60000000 0x0 0x60000000 0x1000000>; -+ -+ dsp: dsp@21170000 { -+ compatible = "fsl,imx8ulp-hifi4"; -+ reg = <0x21170000 0x20000>; -+ clocks = <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, -+ <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, -+ <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>, -+ <&pcc5 IMX8ULP_CLK_MU3_B>; -+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3", "mu_b"; -+ firmware-name = "imx/dsp/hifi4.bin"; -+ mbox-names = "tx0", "rx0", "rxdb0"; -+ mboxes = <&mu3 0 0>, -+ <&mu3 1 0>, -+ <&mu3 3 0>; -+ syscon = <&avd_sim>; -+ status = "disabled"; -+ }; -+ -+ caam_sm: caam-sm@26000000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x26000000 0x8000>; -+ }; -+ -+ ocotp: efuse@27010000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,imx8ulp-ocotp", "syscon"; -+ reg = <0x27010000 0x1000>; -+ status = "okay"; -+ }; -+ -+ s4muap: s4muap@27020000 { -+ compatible = "fsl,imx8ulp-mu-s4"; -+ reg = <0x27020000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ status = "okay"; -+ }; -+ -+ sentnl_mu: sentinel-mu { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,imx-sentinel"; -+ mboxes = <&s4muap 0 0 &s4muap 1 0>; -+ mbox-names = "tx", "rx"; -+ fsl,sentnl_mu_id = <2>; -+ fsl,sentnl_mu_max_users = <4>; -+ status = "okay"; -+ dma-ranges = <0x80000000 0x80000000 0x20000000>; -+ }; -+ -+ per_bridge3: bus@29000000 { -+ compatible = "simple-bus"; -+ reg = <0x29000000 0x800000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ edma1: dma-controller@29010000 { -+ compatible = "fsl,imx8ulp-edma"; -+ reg = <0x29010000 0x10000>, -+ <0x29020000 0x10000>, <0x29030000 0x10000>, -+ <0x29040000 0x10000>, <0x29050000 0x10000>, -+ <0x29060000 0x10000>, <0x29070000 0x10000>, -+ <0x29080000 0x10000>, <0x29090000 0x10000>, -+ <0x290a0000 0x10000>, <0x290b0000 0x10000>, -+ <0x290c0000 0x10000>, <0x290d0000 0x10000>, -+ <0x290e0000 0x10000>, <0x290f0000 0x10000>, -+ <0x29100000 0x10000>, <0x29110000 0x10000>, -+ <0x29120000 0x10000>, <0x29130000 0x10000>, -+ <0x29140000 0x10000>, <0x29150000 0x10000>, -+ <0x29160000 0x10000>, <0x29170000 0x10000>, -+ <0x29180000 0x10000>, <0x29190000 0x10000>, -+ <0x291a0000 0x10000>, <0x291b0000 0x10000>, -+ <0x291c0000 0x10000>, <0x291d0000 0x10000>, -+ <0x291e0000 0x10000>, <0x291f0000 0x10000>, -+ <0x29200000 0x10000>, <0x29210000 0x10000>; -+ #dma-cells = <3>; -+ dma-channels = <32>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", -+ "edma1-chan2-tx", "edma1-chan3-tx", -+ "edma1-chan4-tx", "edma1-chan5-tx", -+ "edma1-chan6-tx", "edma1-chan7-tx", -+ "edma1-chan8-tx", "edma1-chan9-tx", -+ "edma1-chan10-tx", "edma1-chan11-tx", -+ "edma1-chan12-tx", "edma1-chan13-tx", -+ "edma1-chan14-tx", "edma1-chan15-tx", -+ "edma1-chan16-tx", "edma1-chan17-tx", -+ "edma1-chan18-tx", "edma1-chan19-tx", -+ "edma1-chan20-tx", "edma1-chan21-tx", -+ "edma1-chan22-tx", "edma1-chan23-tx", -+ "edma1-chan24-tx", "edma1-chan25-tx", -+ "edma1-chan26-tx", "edma1-chan27-tx", -+ "edma1-chan28-tx", "edma1-chan29-tx", -+ "edma1-chan30-tx", "edma1-chan31-tx"; -+ clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, -+ <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; -+ clock-names = "edma-mp-clk", -+ "edma1-chan0-clk", "edma1-chan1-clk", -+ "edma1-chan2-clk", "edma1-chan3-clk", -+ "edma1-chan4-clk", "edma1-chan5-clk", -+ "edma1-chan6-clk", "edma1-chan7-clk", -+ "edma1-chan8-clk", "edma1-chan9-clk", -+ "edma1-chan10-clk", "edma1-chan11-clk", -+ "edma1-chan12-clk", "edma1-chan13-clk", -+ "edma1-chan14-clk", "edma1-chan15-clk", -+ "edma1-chan16-clk", "edma1-chan17-clk", -+ "edma1-chan18-clk", "edma1-chan19-clk", -+ "edma1-chan20-clk", "edma1-chan21-clk", -+ "edma1-chan22-clk", "edma1-chan23-clk", -+ "edma1-chan24-clk", "edma1-chan25-clk", -+ "edma1-chan26-clk", "edma1-chan27-clk", -+ "edma1-chan28-clk", "edma1-chan29-clk", -+ "edma1-chan30-clk", "edma1-chan31-clk"; -+ status = "okay"; -+ }; -+ -+ mu: mailbox@29220000 { -+ compatible = "fsl,imx8ulp-mu"; -+ reg = <0x29220000 0x10000>; -+ interrupts = ; -+ #mbox-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ mu3: mailbox@29230000 { -+ compatible = "fsl,imx8ulp-mu"; -+ reg = <0x29230000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; -+ #mbox-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ wdog3: watchdog@292a0000 { -+ compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; -+ reg = <0x292a0000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; -+ assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; -+ timeout-sec = <40>; -+ }; -+ -+ cgc1: clock-controller@292c0000 { -+ compatible = "fsl,imx8ulp-cgc1"; -+ reg = <0x292c0000 0x10000>; -+ clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; -+ clock-names = "rosc", "sosc", "frosc", "lposc"; -+ #clock-cells = <1>; -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; -+ assigned-clock-rates = <12288000>; -+ }; -+ -+ pcc3: clock-controller@292d0000 { -+ compatible = "fsl,imx8ulp-pcc3"; -+ reg = <0x292d0000 0x10000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ crypto: crypto@292e0000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x292e0000 0x10000>; -+ ranges = <0 0x292e0000 0x10000>; -+ -+ sec_jr0: jr@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr1: jr@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr2: jr@3000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x3000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr3: jr@4000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x4000 0x1000>; -+ interrupts = ; -+ }; -+ }; -+ -+ tpm5: tpm@29340000 { -+ compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; -+ reg = <0x29340000 0x1000>; -+ interrupts = ; -+ clocks = <&sosc>, <&sosc>; -+ clock-names = "ipg", "per"; -+ status = "okay"; -+ }; -+ -+ flexio_i2c_master: flexio@29350000 { -+ compatible = "imx,flexio_i2c_master"; -+ reg = <0x29350000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_FLEXIO1>, -+ <&pcc3 IMX8ULP_CLK_FLEXIO1>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_FLEXIO1>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; -+ assigned-clock-rates = <24000000>; -+ status = "disabled"; -+ }; -+ -+ i3c2: i3c-master@29360000 { -+ #address-cells = <3>; -+ #size-cells = <0>; -+ compatible = "silvaco,i3c-master"; -+ reg = <0x29360000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_I3C2>, -+ <&pcc3 IMX8ULP_CLK_I3C2>, -+ <&cgc1 IMX8ULP_CLK_DUMMY>; -+ clock-names = "pclk", "fast_clk", "slow_clk"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; -+ assigned-clock-rates = <24000000>; -+ status = "disabled"; -+ }; -+ -+ lpi2c4: i2c@29370000 { -+ compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x29370000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, -+ <&pcc3 IMX8ULP_CLK_LPI2C4>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 46 0 0>, <&edma1 45 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpi2c5: i2c@29380000 { -+ compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x29380000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, -+ <&pcc3 IMX8ULP_CLK_LPI2C5>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 48 0 0>, <&edma1 47 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpuart4: serial@29390000 { -+ compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; -+ reg = <0x29390000 0x1000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; -+ clock-names = "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 56 0 0>, <&edma1 55 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpuart5: serial@293a0000 { -+ compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; -+ reg = <0x293a0000 0x1000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; -+ clock-names = "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; -+ assigned-clock-rates = <24000000>; -+ status = "disabled"; -+ }; -+ -+ lpspi4: spi@293b0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; -+ reg = <0x293b0000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, -+ <&pcc3 IMX8ULP_CLK_LPSPI4>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 64 0 0>, <&edma1 63 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpspi5: spi@293c0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; -+ reg = <0x293c0000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, -+ <&pcc3 IMX8ULP_CLK_LPSPI5>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 66 0 0>, <&edma1 65 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ }; -+ -+ per_bridge4: bus@29800000 { -+ compatible = "simple-bus"; -+ reg = <0x29800000 0x800000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ pcc4: clock-controller@29800000 { -+ compatible = "fsl,imx8ulp-pcc4"; -+ reg = <0x29800000 0x10000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ flexspi2: spi@29810000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mm-fspi"; -+ reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, -+ <&pcc4 IMX8ULP_CLK_FLEXSPI2>; -+ clock-names = "fspi", "fspi_en"; -+ status = "disabled"; -+ }; -+ -+ lpi2c6: i2c@29840000 { -+ compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x29840000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, -+ <&pcc4 IMX8ULP_CLK_LPI2C6>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 50 0 0>, <&edma1 49 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpi2c7: i2c@29850000 { -+ compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x29850000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, -+ <&pcc4 IMX8ULP_CLK_LPI2C7>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 52 0 0>, <&edma1 51 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpuart6: serial@29860000 { -+ compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; -+ reg = <0x29860000 0x1000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; -+ clock-names = "ipg"; -+ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 60 0 0>, <&edma1 59 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ lpuart7: serial@29870000 { -+ compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; -+ reg = <0x29870000 0x1000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; -+ clock-names = "ipg"; -+ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; -+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; -+ assigned-clock-rates = <48000000>; -+ dmas = <&edma1 62 0 0>, <&edma1 61 0 1>; -+ dma-names = "tx","rx"; -+ status = "disabled"; -+ }; -+ -+ sai4: sai@29880000 { -+ compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; -+ reg = <0x29880000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0x03 0x03>; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@29890000 { -+ compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; -+ reg = <0x29890000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0x0f 0x0f>; -+ status = "disabled"; -+ }; -+ -+ iomuxc1: pinctrl@298c0000 { -+ compatible = "fsl,imx8ulp-iomuxc1"; -+ reg = <0x298c0000 0x10000>; -+ }; -+ -+ usdhc0: mmc@298d0000 { -+ compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; -+ reg = <0x298d0000 0x10000>; -+ interrupts = ; -+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, -+ <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, -+ <&pcc4 IMX8ULP_CLK_USDHC0>; -+ clock-names = "ipg", "ahb", "per"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC0>; -+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; -+ assigned-clock-rates = <396000000>, <396000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc1: mmc@298e0000 { -+ compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; -+ reg = <0x298e0000 0x10000>; -+ interrupts = ; -+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, -+ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, -+ <&pcc4 IMX8ULP_CLK_USDHC1>; -+ clock-names = "ipg", "ahb", "per"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC1>; -+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; -+ assigned-clock-rates = <396000000>, <396000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc2: mmc@298f0000 { -+ compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; -+ reg = <0x298f0000 0x10000>; -+ interrupts = ; -+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, -+ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, -+ <&pcc4 IMX8ULP_CLK_USDHC2>; -+ clock-names = "ipg", "ahb", "per"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; -+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>; -+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; -+ assigned-clock-rates = <396000000>, <396000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usbotg1: usb@29900000 { -+ compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; -+ reg = <0x29900000 0x200>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_USB0>; -+ power-domains = <&scmi_devpd IMX8ULP_PD_USB0>; -+ phys = <&usbphy1>; -+ fsl,usbmisc = <&usbmisc1 0>; -+ ahb-burst-config = <0x0>; -+ tx-burst-size-dword = <0x8>; -+ rx-burst-size-dword = <0x8>; -+ status = "disabled"; -+ }; -+ -+ usbmisc1: usbmisc@29900200 { -+ compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; -+ #index-cells = <1>; -+ reg = <0x29900200 0x200>; -+ status = "disabled"; -+ }; -+ -+ usbphy1: usb-phy@29910000 { -+ compatible = "fsl,imx7ulp-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; -+ reg = <0x29910000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usbotg2: usb@29920000 { -+ compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; -+ reg = <0x29920000 0x200>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_USB1>; -+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; -+ phys = <&usbphy2>; -+ fsl,usbmisc = <&usbmisc2 0>; -+ ahb-burst-config = <0x0>; -+ tx-burst-size-dword = <0x8>; -+ rx-burst-size-dword = <0x8>; -+ status = "disabled"; -+ }; -+ -+ usbmisc2: usbmisc@29920200 { -+ compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; -+ #index-cells = <1>; -+ reg = <0x29920200 0x200>; -+ status = "disabled"; -+ }; -+ -+ usbphy2: usb-phy@29930000 { -+ compatible = "fsl,imx7ulp-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; -+ reg = <0x29930000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ fec: ethernet@29950000 { -+ compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec"; -+ reg = <0x29950000 0x10000>; -+ interrupts = ; -+ interrupt-names = "int0"; -+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, -+ <&pcc4 IMX8ULP_CLK_ENET>, -+ <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, -+ <&clock_ext_rmii>; -+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; -+ fsl,num-tx-queues = <1>; -+ fsl,num-rx-queues = <1>; -+ status = "disabled"; -+ }; -+ }; -+ -+ gpioe: gpio@2d000000 { -+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; -+ reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, -+ <&pcc4 IMX8ULP_CLK_PCTLE>; -+ clock-names = "gpio", "port"; -+ gpio-ranges = <&iomuxc1 0 32 24>; -+ }; -+ -+ gpiof: gpio@2d010000 { -+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; -+ reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, -+ <&pcc4 IMX8ULP_CLK_PCTLF>; -+ clock-names = "gpio", "port"; -+ gpio-ranges = <&iomuxc1 0 64 32>; -+ }; -+ -+ per_bridge5: bus@2d800000 { -+ compatible = "simple-bus"; -+ reg = <0x2d800000 0x800000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ edma2: dma-controller@2d800000 { -+ compatible = "fsl,imx8ulp-edma"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_DMA2>; -+ reg = <0x2d800000 0x10000>, -+ <0x2d810000 0x10000>, <0x2d820000 0x10000>, -+ <0x2d830000 0x10000>, <0x2d840000 0x10000>, -+ <0x2d850000 0x10000>, <0x2d860000 0x10000>, -+ <0x2d870000 0x10000>, <0x2d880000 0x10000>, -+ <0x2d890000 0x10000>, <0x2d8a0000 0x10000>, -+ <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>, -+ <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>, -+ <0x2d8f0000 0x10000>, <0x2d900000 0x10000>, -+ <0x2d910000 0x10000>, <0x2d920000 0x10000>, -+ <0x2d930000 0x10000>, <0x2d940000 0x10000>, -+ <0x2d950000 0x10000>, <0x2d960000 0x10000>, -+ <0x2d970000 0x10000>, <0x2d980000 0x10000>, -+ <0x2d990000 0x10000>, <0x2d9a0000 0x10000>, -+ <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>, -+ <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>, -+ <0x2d9f0000 0x10000>, <0x2da00000 0x10000>; -+ #dma-cells = <3>; -+ dma-channels = <32>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", -+ "edma2-chan2-tx", "edma2-chan3-tx", -+ "edma2-chan4-tx", "edma2-chan5-tx", -+ "edma2-chan6-tx", "edma2-chan7-tx", -+ "edma2-chan8-tx", "edma2-chan9-tx", -+ "edma2-chan10-tx", "edma2-chan11-tx", -+ "edma2-chan12-tx", "edma2-chan13-tx", -+ "edma2-chan14-tx", "edma2-chan15-tx", -+ "edma2-chan16-tx", "edma2-chan17-tx", -+ "edma2-chan18-tx", "edma2-chan19-tx", -+ "edma2-chan20-tx", "edma2-chan21-tx", -+ "edma2-chan22-tx", "edma2-chan23-tx", -+ "edma2-chan24-tx", "edma2-chan25-tx", -+ "edma2-chan26-tx", "edma2-chan27-tx", -+ "edma2-chan28-tx", "edma2-chan29-tx", -+ "edma2-chan30-tx", "edma2-chan31-tx"; -+ clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, -+ <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; -+ clock-names = "edma-mp-clk", -+ "edma2-chan0-clk", "edma2-chan1-clk", -+ "edma2-chan2-clk", "edma2-chan3-clk", -+ "edma2-chan4-clk", "edma2-chan5-clk", -+ "edma2-chan6-clk", "edma2-chan7-clk", -+ "edma2-chan8-clk", "edma2-chan9-clk", -+ "edma2-chan10-clk", "edma2-chan11-clk", -+ "edma2-chan12-clk", "edma2-chan13-clk", -+ "edma2-chan14-clk", "edma2-chan15-clk", -+ "edma2-chan16-clk", "edma2-chan17-clk", -+ "edma2-chan18-clk", "edma2-chan19-clk", -+ "edma2-chan20-clk", "edma2-chan21-clk", -+ "edma2-chan22-clk", "edma2-chan23-clk", -+ "edma2-chan24-clk", "edma2-chan25-clk", -+ "edma2-chan26-clk", "edma2-chan27-clk", -+ "edma2-chan28-clk", "edma2-chan29-clk", -+ "edma2-chan30-clk", "edma2-chan31-clk"; -+ status = "okay"; -+ }; -+ -+ avd_sim: syscon@2da50000 { -+ compatible = "nxp,imx8ulp-avd-sim", "syscon", "simple-mfd"; -+ reg = <0x2da50000 0x38>; -+ clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; -+ -+ mux: mux-controller { -+ compatible = "mmio-mux"; -+ #mux-control-cells = <1>; -+ mux-reg-masks = <0x8 0x00000200>; /* DSI_DPI2_EPDC_DCNANO_MUX_SEL */ -+ }; -+ -+ avd_sim_rst: reset-controller { -+ compatible = "nxp,imx8ulp-avd-sim-reset"; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ cgc2: clock-controller@2da60000 { -+ compatible = "fsl,imx8ulp-cgc2"; -+ reg = <0x2da60000 0x10000>; -+ clocks = <&sosc>, <&frosc>; -+ clock-names = "sosc", "frosc"; -+ #clock-cells = <1>; -+ }; -+ -+ pcc5: clock-controller@2da70000 { -+ compatible = "fsl,imx8ulp-pcc5"; -+ reg = <0x2da70000 0x10000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ sai6: sai@2da90000 { -+ compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; -+ reg = <0x2da90000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0x0f 0x0f>; -+ status = "disabled"; -+ }; -+ -+ sai7: sai@2daa0000 { -+ compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; -+ reg = <0x2daa0000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, -+ <&cgc1 IMX8ULP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0x0f 0x0f>; -+ status = "disabled"; -+ }; -+ -+ spdif: spdif@2dab0000 { -+ compatible = "fsl,imx8ulp-spdif"; -+ reg = <0x2dab0000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ -+ <&sosc>, /* 0, extal */ -+ <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ -+ <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ -+ <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ -+ <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ -+ <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ -+ <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ -+ <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ -+ <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ cameradev: camera { -+ compatible = "fsl,mxc-md", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ isi_0: isi@2dac0000 { -+ compatible = "fsl,imx8ulp-isi", "fsl,imx8-isi"; -+ reg = <0x2dac0000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc5 IMX8ULP_CLK_ISI>; -+ power-domains = <&scmi_devpd IMX8ULP_PD_ISI>; -+ clock-names = "per"; -+ interface = <2 0 2>; -+ no-reset-control; -+ statu = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ mipi_csi0: csi@2dad0000 { -+ compatible = "fsl,imx8ulp-mipi-csi2", "fsl,mxc-mipi-csi2"; -+ reg = <0x2daf0000 0x10000>, -+ <0x2dad0000 0x10000>; -+ clocks = <&pcc5 IMX8ULP_CLK_CSI>, -+ <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, -+ <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>, -+ <&pcc5 IMX8ULP_CLK_CSI_REGS>; -+ clock-names = "clk_core", "clk_ui", "clk_esc", "clk_regs"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>; -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_PLL4_PFD1>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD3>, -+ <&pcc5 IMX8ULP_CLK_CSI>, -+ <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, -+ <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>; -+ assigned-clock-parents = <0>, <0>, <0>, <0>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD3_DIV2>; -+ assigned-clock-rates = <528000000>, -+ <176000000>, -+ <132000000>, -+ <396000000>, -+ <176000000>, -+ <132000000>, -+ <79200000>; -+ status = "disabled"; -+ }; -+ }; -+ -+ dsi: dsi@2db00000 { -+ compatible = "fsl,imx8ulp-nwl-dsi"; -+ reg = <0x2db00000 0x300>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, -+ <&pcc5 IMX8ULP_CLK_DSI>, -+ <&pcc5 IMX8ULP_CLK_DSI_TX_ESC>, -+ <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>; -+ clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_DSI>; -+ assigned-clocks = <&pcc5 IMX8ULP_CLK_DSI>; -+ assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD3_DIV2>; -+ assigned-clock-rates = <79200000>; -+ interrupts = ; -+ mux-controls = <&mux 0>; -+ csr = <&avd_sim>; -+ phys = <&dphy>; -+ phy-names = "dphy"; -+ resets = <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N>, -+ <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N>, -+ <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N>, -+ <&pcc5 PCC5_DSI_SWRST>; -+ reset-names = "byte", "dpi", "esc", "pclk"; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ mipi_dsi_to_dcnano_dpi: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&dcnano_dpi_to_mipi_dsi>; -+ }; -+ -+ mipi_dsi_to_epdc_dpi: endpoint@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ }; -+ -+ dphy: phy@2db00300 { -+ compatible = "fsl,imx8ulp-mipi-dphy"; -+ reg = <0x2db00300 0x100>; -+ clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>; -+ clock-names = "phy_ref"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ epdc: epdc@2db30000 { -+ compatible = "fsl,imx7d-epdc"; -+ reg = <0x2db30000 0x10000>; -+ clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, -+ <&pcc5 IMX8ULP_CLK_EPDC>, -+ <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>; -+ clock-names = "epdc_axi", "epdc_pix", "epdc_ahb"; -+ assigned-clocks = <&pcc5 IMX8ULP_CLK_EPDC>, <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV2>; -+ assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV2>; -+ assigned-clock-rates = <0>, <40000000>; -+ interrupts = ; -+ power-domains = <&scmi_devpd IMX8ULP_PD_PXP>; -+ status = "disabled"; -+ }; -+ -+ epxp: epxp@2db40000 { -+ compatible = "fsl,imx8ulp-pxp-dma", "fsl,imx7d-pxp-dma"; -+ reg = <0x2db40000 0x10000>; -+ clocks = <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>, -+ <&pcc5 IMX8ULP_CLK_PXP>; -+ clock-names = "pxp_ipg", "pxp_axi"; -+ interrupts = ; -+ power-domains = <&scmi_devpd IMX8ULP_PD_PXP>; -+ status = "disabled"; -+ }; -+ }; -+ -+ gpu3d: gpu3d@2e000000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x2e000000 0x10000>; -+ interrupts = ; -+ clocks = <&pcc5 IMX8ULP_CLK_GPU3D>, -+ <&cgc1 IMX8ULP_CLK_DUMMY>; -+ clock-names = "core", "shader"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_GPU3D>; -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_PLL4_PFD2>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>, -+ <&pcc5 IMX8ULP_CLK_GPU3D>; -+ assigned-clock-parents = <0>, -+ <0>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>; -+ assigned-clock-rates = <316800000>, -+ <316800000>, -+ <316800000>; -+ }; -+ -+ gpu2d: gpu2d@2e010000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x2e010000 0x40000>; -+ interrupts = ; -+ clocks = <&pcc5 IMX8ULP_CLK_GPU2D>; -+ clock-names = "core"; -+ power-domains = <&scmi_devpd IMX8ULP_PD_GPU2D>; -+ assigned-clocks = <&cgc2 IMX8ULP_CLK_PLL4_PFD2>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>, -+ <&pcc5 IMX8ULP_CLK_GPU2D>; -+ assigned-clock-parents = <0>, -+ <0>, -+ <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>; -+ assigned-clock-rates = <316800000>, -+ <316800000>, -+ <316800000>; -+ }; -+ -+ dcnano: display-controller@2e050000 { -+ compatible = "nxp,imx8ulp-dcnano"; -+ reg = <0x2e050000 0x10000>; -+ interrupts = ; -+ clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, -+ <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>, -+ <&pcc5 IMX8ULP_CLK_DC_NANO>; -+ clock-names = "axi", "ahb", "pixel"; -+ resets = <&pcc5 PCC5_DC_NANO_SWRST>; -+ power-domains = <&scmi_devpd IMX8ULP_PD_DCNANO>; -+ assigned-clocks = <&pcc5 IMX8ULP_CLK_DC_NANO>; -+ assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dcnano_dpi: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ dcnano_dpi_to_mipi_dsi: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&mipi_dsi_to_dcnano_dpi>; -+ }; -+ -+ dcnano_dpi_to_disp: endpoint@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ dcnano_dbi: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ -+ dcnano_dbi_to_mipi_dsi: endpoint@0 { -+ reg = <0>; -+ }; -+ -+ dcnano_dbi_to_disp: endpoint@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ }; -+ -+ gpiod: gpio@2e200000 { -+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; -+ reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, -+ <&pcc5 IMX8ULP_CLK_RGPIOD>; -+ clock-names = "gpio", "port"; -+ gpio-ranges = <&iomuxc1 0 0 24>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi -new file mode 100644 -index 000000000..050f17118 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi -@@ -0,0 +1,147 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include "imx8x-val.dtsi" -+ -+/ { -+ reserved-memory { -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x14000000>; -+ alloc-ranges = <0 0xc0000000 0 0x14000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ regulators { -+ epdev_on: fixedregulator@100 { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "epdev_on"; -+ gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ imx8qxp-lpddr4-arm2 { -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ >; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1>; -+ status = "okay"; -+ -+ /delete-node/ gpio@68; -+ /delete-node/ typec@3d; -+ -+ pca9557_a: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@19 { -+ compatible = "nxp,pca9557"; -+ reg = <0x19>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c3>; -+ status = "okay"; -+ -+ /delete-node/ gpio@18; -+ /delete-node/ gpio@19; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&i2c_mipi_csi0 { -+ status = "disabled"; -+}; -+ -+&mipi_csi_0 { -+ status = "disabled"; -+}; -+ -+&gpio0_mipi_csi0 { -+ status = "disabled"; -+}; -+ -+&pcieb{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ disable-gpio = <&pca9557_a 5 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; -+ epdev_on-supply = <&epdev_on>; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ /delete-node/ mt35xu512aba@0; -+ -+ flash0: mt25qu512abb@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&adc0 { -+ status = "disabled"; -+}; -+ -+&usbotg1 { -+ /delete-property/ pinctrl-names; -+ /delete-property/ pinctrl-0; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi -new file mode 100644 -index 000000000..d4fe033cb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi -@@ -0,0 +1,99 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/ { -+ panel { -+ compatible = "sii,43wvf1g"; -+ backlight = <&lcdif_backlight>; -+ status = "okay"; -+ -+ port { -+ lcd_panel_in: endpoint { -+ remote-endpoint = <&lcd_display_out>; -+ }; -+ }; -+ }; -+ -+ display@disp1 { -+ compatible = "fsl,imx-lcdif-mux-display"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lcdif>; -+ clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, -+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; -+ clock-names = "bypass_div", "pixel"; -+ assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; -+ assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; -+ fsl,lcdif-mux-regs = <&lcdif_mux_regs>; -+ fsl,interface-pix-fmt = "rgb666"; -+ power-domains = <&pd IMX_SC_R_LCD_0>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ -+ lcd_display_in: endpoint { -+ remote-endpoint = <&dpu_disp1_lcdif>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ lcd_display_out: endpoint { -+ remote-endpoint = <&lcd_panel_in>; -+ }; -+ }; -+ }; -+ -+ lcdif_backlight: lcdif-backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&adma_pwm 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+&dpu_disp1_lcdif { -+ remote-endpoint = <&lcd_display_in>; -+}; -+ -+&iomuxc { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000 -+ >; -+ }; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&lpuart1 { -+ status = "disabled"; -+}; -+ -+&adma_pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lcdifpwm>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi -new file mode 100644 -index 000000000..fc09e0f65 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+&i2c0_mipi_lvds0 { -+ lvds-to-hdmi-bridge@4c { -+ split-mode; -+ }; -+}; -+ -+&ldb1 { -+ fsl,dual-channel; -+}; -+ -+&ldb2 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi -new file mode 100644 -index 000000000..77e32fd28 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+&i2c0_mipi_lvds1 { -+ lvds-to-hdmi-bridge@4c { -+ split-mode; -+ }; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -+ -+&ldb2 { -+ fsl,dual-channel; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi -new file mode 100644 -index 000000000..51a744ed8 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi -@@ -0,0 +1,41 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/ { -+ lvds0_panel { -+ compatible = "jdi,tx26d202vm0bwa"; -+ backlight = <&lvds_backlight1>; -+ -+ port { -+ panel_lvds0_in: endpoint { -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+/delete-node/ &it6263_0_in; -+ -+&ldb1 { -+ fsl,dual-channel; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <24>; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&panel_lvds0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi -new file mode 100644 -index 000000000..58255c03b ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi -@@ -0,0 +1,41 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/ { -+ lvds1_panel { -+ compatible = "jdi,tx26d202vm0bwa"; -+ backlight = <&lvds_backlight0>; -+ -+ port { -+ panel_lvds1_in: endpoint { -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+/delete-node/ &it6263_1_in; -+ -+&ldb2 { -+ fsl,dual-channel; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <24>; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&panel_lvds1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi -new file mode 100644 -index 000000000..73d5cd433 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi -@@ -0,0 +1,105 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2020 NXP. -+ */ -+ -+/ { -+ display-subsystem { -+ status = "disabled"; -+ }; -+ -+ panel { -+ compatible = "sii,43wvf1g"; -+ backlight = <&lcdif_backlight>; -+ -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&adapter_out>; -+ }; -+ }; -+ }; -+ -+ seiko_adapter: seiko-adapter { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,seiko-43wvfig"; -+ bus_mode = <18>; -+ -+ port@0 { -+ reg = <0>; -+ adapter_in: endpoint { -+ remote-endpoint = <&lcdif_out>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ adapter_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+ }; -+ -+ lcdif_backlight: lcdif-backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&adma_pwm 0 100000 0>; -+ status = "okay"; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+&iomuxc { -+ /delete-node/ pinctrl_hog; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ >; -+ }; -+}; -+ -+&esai0 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&lpuart1 { -+ status = "disabled"; -+}; -+ -+&adma_pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lcdifpwm>; -+ status = "okay"; -+}; -+ -+&adma_pwm_lpcg { -+ status = "okay"; -+}; -+ -+ -+&adma_lcdif { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lcdif>; -+ status = "okay"; -+ -+ port@0 { -+ lcdif_out: endpoint { -+ remote-endpoint = <&adapter_in>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi -new file mode 100644 -index 000000000..694737512 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi -@@ -0,0 +1,243 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright NXP 2019 -+ -+ -+/delete-node/ &cm40_i2c; -+/delete-node/ &i2c1; -+ -+/ { -+ aliases { -+ i2c1 = &i2c_rpbus_1; -+ }; -+}; -+ -+&i2c_rpbus_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ ptn5110: tcpc@50 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x50>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port { -+ typec_dr_sw: endpoint { -+ remote-endpoint = <&usb3_drd_sw>; -+ }; -+ }; -+ -+ usb_con1: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "source"; -+ data-role = "dual"; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_rpbus_5 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ }; -+ -+ ov5640: ov5640@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_parallel_csi>; -+ clocks = <&pi0_misc_lpcg 0>; -+ assigned-clocks = <&pi0_misc_lpcg 0>; -+ assigned-clock-rates = <24000000>; -+ clock-names = "xclk"; -+ powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; -+ csi_id = <0>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ port { -+ ov5640_ep: endpoint { -+ remote-endpoint = <¶llel_csi_ep>; -+ bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ -+ bus-width = <8>; -+ vsync-active = <0>; -+ hsync-active = <1>; -+ pclk-sample = <1>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c_rpbus_12 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&i2c_rpbus_14 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ interrupt-open-drain; -+ }; -+ -+ fxas2100x@21 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x21>; -+ interrupt-open-drain; -+ }; -+ -+ pressure-sensor@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ interrupt-open-drain; -+ }; -+}; -+ -+&i2c_rpbus_15 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pca9557_a: gpio@1a { -+ compatible = "nxp,pca9557"; -+ reg = <0x1a>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@1d { -+ compatible = "nxp,pca9557"; -+ reg = <0x1d>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <2 2>; -+ }; -+}; -+ -+&cm40_i2c_lpcg { -+ status = "disabled"; -+}; -+ -+&i2c1_lpcg { -+ status = "disabled"; -+}; -+ -+&can0_lpcg { -+ status = "disabled"; -+}; -+ -+®_can_en { -+ status = "disabled"; -+}; -+ -+®_can_stby { -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ status = "disabled"; -+}; -+ -+&flexcan2 { -+ status = "disabled"; -+}; -+ -+&cm40_intmux { -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ status = "disabled"; -+}; -+ -+&lpuart3 { -+ status = "disabled"; -+}; -+ -+&uart3_lpcg { -+ status = "disabled"; -+}; -+ -+&imx8x_cm4 { -+ /* Assume you have partitioned M4, so M4 is ont controled by Linux */ -+ /delete-property/ power-domains; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi -new file mode 100644 -index 000000000..7dfea4603 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi -@@ -0,0 +1,1585 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2017-2020 NXP -+ */ -+ -+#include -+/ { -+ chosen { -+ stdout-path = &lpuart0; -+ }; -+ -+ brcmfmac: brcmfmac { -+ compatible = "cypress,brcmfmac"; -+ pinctrl-names = "init", "idle", "default"; -+ pinctrl-0 = <&pinctrl_wifi_init>; -+ pinctrl-1 = <&pinctrl_wifi_init>; -+ pinctrl-2 = <&pinctrl_wifi>; -+ }; -+ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_mipi_lvds0 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ lvds_backlight1: lvds_backlight@1 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm_mipi_lvds1 0 100000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x40000000>; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ cbtl04gp { -+ compatible = "nxp,cbtl04gp"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec_mux>; -+ switch-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_LOW>; -+ reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; -+ orientation-switch; -+ -+ port { -+ usb3_data_ss: endpoint { -+ remote-endpoint = <&typec_con_ss>; -+ }; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 -+ * Shouldn't be used at A core and Linux side. -+ * -+ */ -+ m4_reserved: m4@0x88000000 { -+ no-map; -+ reg = <0 0x88000000 0 0x8000000>; -+ }; -+ -+ decoder_boot: decoder-boot@84000000 { -+ reg = <0 0x84000000 0 0x2000000>; -+ no-map; -+ }; -+ -+ encoder_boot: encoder-boot@86000000 { -+ reg = <0 0x86000000 0 0x200000>; -+ no-map; -+ }; -+ -+ decoder_rpc: decoder-rpc@0x92000000 { -+ reg = <0 0x92000000 0 0x200000>; -+ no-map; -+ }; -+ -+ encoder_rpc: encoder-rpc@0x92200000 { -+ reg = <0 0x92200000 0 0x200000>; -+ no-map; -+ }; -+ -+ dsp_reserved: dsp@92400000 { -+ reg = <0 0x92400000 0 0x1000000>; -+ no-map; -+ }; -+ dsp_reserved_heap: dsp_reserved_heap { -+ reg = <0 0x93400000 0 0xef0000>; -+ no-map; -+ }; -+ dsp_vdev0vring0: vdev0vring0@942f0000 { -+ reg = <0 0x942f0000 0 0x8000>; -+ no-map; -+ }; -+ -+ dsp_vdev0vring1: vdev0vring1@942f8000 { -+ reg = <0 0x942f8000 0 0x8000>; -+ no-map; -+ }; -+ -+ dsp_vdev0buffer: vdev0buffer@94300000 { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x94300000 0 0x100000>; -+ no-map; -+ }; -+ -+ encoder_reserved: encoder_reserved@94400000 { -+ no-map; -+ reg = <0 0x94400000 0 0x800000>; -+ }; -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0xc0000000 0 0x3c000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ reg_usdhc2_vmmc: usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <3480>; -+ enable-active-high; -+ }; -+ -+ reg_can_en: regulator-can-en { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can_stby: regulator-can-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can_en>; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usb_otg1_vbus: regulator-usbotg1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_audio: fixedregulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ bt_sco_codec: bt_sco_codec { -+ #sound-dai-cells = <1>; -+ compatible = "linux,bt-sco"; -+ }; -+ -+ sound-bt-sco { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "bt-sco-audio"; -+ simple-audio-card,format = "dsp_a"; -+ simple-audio-card,bitclock-inversion; -+ simple-audio-card,frame-master = <&btcpu>; -+ simple-audio-card,bitclock-master = <&btcpu>; -+ -+ btcpu: simple-audio-card,cpu { -+ sound-dai = <&sai0>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <16>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&bt_sco_codec 1>; -+ }; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ audio-cpu = <&esai0>; -+ audio-codec = <&cs42888>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ status = "okay"; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx8x-mek-wm8960", -+ "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ audio-cpu = <&sai1>; -+ audio-codec = <&wm8960>; -+ hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT2", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "RINPUT1", "AMIC", -+ "RINPUT2", "AMIC", -+ "Mic Jack", "MICB", -+ "AMIC", "MICB"; -+ }; -+ -+ imx8x_cm4: imx8x_cm4@0 { -+ compatible = "fsl,imx8qxp-cm4"; -+ rsc-da = <0x90000000>; -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&lsio_mu5 0 1 -+ &lsio_mu5 1 1 -+ &lsio_mu5 3 1>; -+ mub-partition = <3>; -+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, -+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; -+ core-index = <0>; -+ core-id = ; -+ status = "okay"; -+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, -+ <&pd IMX_SC_R_M4_0_MU_1A>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ vdev0vring0: vdev0vring0@90000000 { -+ reg = <0 0x90000000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@90008000 { -+ reg = <0 0x90008000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring0: vdev1vring0@90010000 { -+ reg = <0 0x90010000 0 0x8000>; -+ no-map; -+ }; -+ -+ vdev1vring1: vdev1vring1@90018000 { -+ reg = <0 0x90018000 0 0x8000>; -+ no-map; -+ }; -+ -+ rsc_table: rsc_table@900ff000 { -+ reg = <0 0x900ff000 0 0x1000>; -+ no-map; -+ }; -+ -+ vdevbuffer: vdevbuffer { -+ compatible = "shared-dma-pool"; -+ reg = <0 0x90400000 0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+}; -+ -+&cm40_i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default", "gpio"; -+ pinctrl-0 = <&pinctrl_cm40_i2c>; -+ pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; -+ scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; -+ sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ pca6416: gpio@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ wlf,hp-cfg = <2 2 3>; -+ wlf,gpio-cfg = <1 3>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ }; -+ -+ cs42888: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&mclkout0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; -+ fsl,txs-rxm; -+ }; -+ -+ ov5640: ov5640@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_parallel_csi>; -+ clocks = <&pi0_misc_lpcg 0>; -+ assigned-clocks = <&pi0_misc_lpcg 0>; -+ assigned-clock-rates = <24000000>; -+ clock-names = "xclk"; -+ powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; -+ csi_id = <0>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ status = "okay"; -+ port { -+ ov5640_ep: endpoint { -+ remote-endpoint = <¶llel_csi_ep>; -+ bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ -+ bus-width = <8>; -+ vsync-active = <0>; -+ hsync-active = <1>; -+ pclk-sample = <1>; -+ }; -+ }; -+ }; -+}; -+ -+&cm40_intmux { -+ status = "okay"; -+}; -+ -+&dc0_pc { -+ status = "okay"; -+}; -+ -+&dc0_prg1 { -+ status = "okay"; -+}; -+ -+&dc0_prg2 { -+ status = "okay"; -+ -+}; -+ -+&dc0_prg3 { -+ status = "okay"; -+}; -+ -+&dc0_prg4 { -+ status = "okay"; -+}; -+ -+&dc0_prg5 { -+ status = "okay"; -+}; -+ -+&dc0_prg6 { -+ status = "okay"; -+}; -+ -+&dc0_prg7 { -+ status = "okay"; -+}; -+ -+&dc0_prg8 { -+ status = "okay"; -+}; -+ -+&dc0_prg9 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr1_channel3 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel1 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel2 { -+ status = "okay"; -+}; -+ -+&dc0_dpr2_channel3 { -+ status = "okay"; -+}; -+ -+&dpu1 { -+ status = "okay"; -+}; -+ -+&pwm_mipi_lvds0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; -+ status = "okay"; -+}; -+ -+&i2c0_mipi_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds_bridge0: lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; -+ -+ port { -+ it6263_0_in: endpoint { -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+ -+ adv_bridge0: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_0_in: endpoint { -+ remote-endpoint = <&mipi0_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb1_phy { -+ status = "okay"; -+}; -+ -+&ldb1 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi0_dphy { -+ status = "okay"; -+}; -+ -+&mipi0_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi0_adv_out: endpoint { -+ remote-endpoint = <&adv7535_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&pwm_mipi_lvds1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; -+ status = "okay"; -+}; -+ -+&i2c0_mipi_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds_bridge1: lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; -+ -+ port { -+ it6263_1_in: endpoint { -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+ -+ adv_bridge1: adv7535@3d { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "adi,adv7535"; -+ reg = <0x3d>; -+ adi,addr-cec = <0x3b>; -+ adi,dsi-lanes = <4>; -+ adi,dsi-channel = <1>; -+ interrupt-parent = <&lsio_gpio2>; -+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ adv7535_1_in: endpoint { -+ remote-endpoint = <&mipi1_adv_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "okay"; -+}; -+ -+&ldb2 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi1_dphy { -+ status = "okay"; -+}; -+ -+&mipi1_dsi_host { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ mipi1_adv_out: endpoint { -+ remote-endpoint = <&adv7535_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&lpuart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ status = "okay"; -+}; -+ -+&lpuart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "okay"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&dsp { -+ memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, -+ <&dsp_vdev0vring1>, <&dsp_reserved>; -+ status = "okay"; -+}; -+ -+&esai0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai0 { -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai0_lpcg 0>; -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai0>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ -+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ status = "okay"; -+}; -+ -+&sai4 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai4_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai5 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai5_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac0>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ nvmem-cells = <&fec_mac1>; -+ nvmem-cell-names = "mac-address"; -+ fsl,rgmii_rxc_dly; -+ status = "disabled"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ nxp,fspi-dll-slvdly = <4>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <8>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; -+ status = "okay"; -+ -+ i2c-switch@71 { -+ compatible = "nxp,pca9646", "nxp,pca9546"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x71>; -+ reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; -+ -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ }; -+ -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ -+ fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ interrupt-open-drain; -+ }; -+ -+ fxas2100x@21 { -+ compatible = "fsl,fxas2100x"; -+ reg = <0x21>; -+ interrupt-open-drain; -+ }; -+ -+ pressure-sensor@60 { -+ compatible = "fsl,mpl3115"; -+ reg = <0x60>; -+ interrupt-open-drain; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <3>; -+ -+ pca9557_a: gpio@1a { -+ compatible = "nxp,pca9557"; -+ reg = <0x1a>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@1d { -+ compatible = "nxp,pca9557"; -+ reg = <0x1d>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ isl29023@44 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_isl29023>; -+ compatible = "fsl,isl29023"; -+ reg = <0x44>; -+ rext = <499>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>; -+ }; -+ }; -+ -+ }; -+ -+ ptn5110: tcpc@50 { -+ compatible = "nxp,ptn5110"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_typec>; -+ reg = <0x50>; -+ interrupt-parent = <&lsio_gpio1>; -+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; -+ status = "okay"; -+ -+ port { -+ typec_dr_sw: endpoint { -+ remote-endpoint = <&usb3_drd_sw>; -+ }; -+ }; -+ -+ usb_con1: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "source"; -+ data-role = "dual"; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ typec_con_ss: endpoint { -+ remote-endpoint = <&usb3_data_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&thermal_zones { -+ pmic-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; -+ -+ trips { -+ pmic_alert0: trip0 { -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ pmic_crit0: trip1 { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&pmic_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+}; -+ -+&pcieb{ -+ compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; -+ ext_osc = <1>; -+ status = "okay"; -+}; -+ -+&usbphy1 { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ vbus-supply = <®_usb_otg1_vbus>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&usbotg3 { -+ status = "okay"; -+}; -+ -+&usbotg3_cdns3 { -+ dr_mode = "otg"; -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ usb3_drd_sw: endpoint { -+ remote-endpoint = <&typec_dr_sw>; -+ }; -+ }; -+}; -+ -+&usdhc1 { -+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <400000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1>; -+ pinctrl-2 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; -+ assigned-clock-rates = <200000000>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&vpu_decoder { -+ boot-region = <&decoder_boot>; -+ rpc-region = <&decoder_rpc>; -+ reg-csr = <0x2d040000>; -+ core_type = <1>; -+ status = "okay"; -+}; -+ -+&vpu_encoder { -+ boot-region = <&encoder_boot>; -+ rpc-region = <&encoder_rpc>; -+ reserved-region = <&encoder_reserved>; -+ reg-rpc-system = <0x40000000>; -+ resolution-max = <1920 1920>; -+ fps-max = <120>; -+ mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; -+ mboxes = <&mu1_m0 0 0 -+ &mu1_m0 0 1 -+ &mu1_m0 1 0>; -+ status = "okay"; -+ -+ core0@1020000 { -+ compatible = "fsl,imx8-mu1-vpu-m0"; -+ reg = <0x1020000 0x20000>; -+ reg-csr = <0x1050000 0x10000>; -+ interrupts = ; -+ fsl,vpu_ap_mu_id = <17>; -+ fw-buf-size = <0x200000>; -+ rpc-buf-size = <0x80000>; -+ print-buf-size = <0x80000>; -+ }; -+}; -+ -+&gpu_3d0 { -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ m2m_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_1 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_2 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_3 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&isi_4 { -+ interface = <6 0 2>; -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer_csi0 { -+ status = "okay"; -+}; -+ -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&cameradev { -+ parallel_csi; -+ status = "okay"; -+}; -+ -+¶llel_csi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port@0 { -+ reg = <0>; -+ parallel_csi_ep: endpoint { -+ remote-endpoint = <&ov5640_ep>; -+ }; -+ }; -+}; -+ -+&jpegdec { -+ status = "okay"; -+}; -+ -+&jpegenc { -+ status = "okay"; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6a>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "okay"; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ >; -+ }; -+ -+ pinctrl_cm40_i2c: cm40i2cgrp { -+ fsl,pins = < -+ IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c -+ IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c -+ >; -+ }; -+ -+ pinctrl_cm40_i2c_gpio: cm40i2cgrp-gpio { -+ fsl,pins = < -+ IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c -+ IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c -+ >; -+ }; -+ -+ pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 -+ IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 -+ IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 -+ >; -+ }; -+ -+ pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 -+ IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 -+ IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 -+ IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 -+ IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 -+ IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 -+ IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 -+ IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 -+ IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_ioexp_rst: ioexprstgrp { -+ fsl,pins = < -+ IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 -+ >; -+ }; -+ -+ pinctrl_isl29023: isl29023grp { -+ fsl,pins = < -+ IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lpi2c1: lpi2c1grp { -+ fsl,pins = < -+ IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 -+ IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 -+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 -+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 -+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 -+ IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 -+ IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 -+ IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 -+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 -+ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_pcieb: pcieagrp{ -+ fsl,pins = < -+ IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 -+ IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 -+ IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 -+ >; -+ }; -+ -+ pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_sai0: sai0grp { -+ fsl,pins = < -+ IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 -+ IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 -+ IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 -+ IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 -+ IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 -+ IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 -+ IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 -+ IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 -+ >; -+ }; -+ -+ pinctrl_typec: typecgrp { -+ fsl,pins = < -+ IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 -+ >; -+ }; -+ -+ pinctrl_typec_mux: typecmuxgrp { -+ fsl,pins = < -+ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 -+ IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 -+ IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 -+ >; -+ }; -+ -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { -+ fsl,pins = < -+ IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0: mipi_csi0 { -+ fsl,pins = < -+ IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 -+ IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 -+ IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_parallel_csi: parallelcsigrp { -+ fsl,pins = < -+ IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 -+ IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 -+ IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 -+ IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 -+ IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 -+ IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 -+ IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 -+ IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 -+ -+ IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 -+ IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 -+ IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 -+ IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 -+ IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 -+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 -+ >; -+ }; -+ -+ pinctrl_wifi: wifigrp{ -+ fsl,pins = < -+ IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 -+ >; -+ }; -+ -+ pinctrl_wifi_init: wifi_initgrp{ -+ fsl,pins = < -+ /* reserve pin init/idle_state to support multiple wlan cards */ -+ >; -+ }; -+ -+ pinctrl_lcdif: lcdifgrp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 -+ IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 -+ IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 -+ IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 -+ IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 -+ IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 -+ IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 -+ IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 -+ IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 -+ IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 -+ IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 -+ IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 -+ IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 -+ IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 -+ IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 -+ IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 -+ IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 -+ IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 -+ IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 -+ IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 -+ IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 -+ IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 -+ IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 -+ >; -+ }; -+ -+ pinctrl_lcdifpwm: lcdifpwmgrp { -+ fsl,pins = < -+ IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 -+ >; -+ }; -+}; -+ -+&scu_key { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/imx8x-val.dtsi b/arch/arm64/boot/dts/freescale/imx8x-val.dtsi -new file mode 100644 -index 000000000..500c969f1 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8x-val.dtsi -@@ -0,0 +1,837 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2019 NXP -+ */ -+ -+/ { -+ chosen { -+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; -+ stdout-path = &lpuart0; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_usdhc2_vmmc: usdhc2_vmmc { -+ compatible = "regulator-fixed"; -+ regulator-name = "SD1_SPWR"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay = <2720>; -+ enable-active-high; -+ }; -+ -+ reg_can_en: regulator-can-gen { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can_stby: regulator-can-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can-stby"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_can_en>; -+ }; -+ -+ reg_audio: fixedregulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "cs42888_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_baseboard: fixedregulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "baseboard_supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_fec2_supply: fec2_nvcc { -+ compatible = "regulator-fixed"; -+ regulator-name = "fec2_nvcc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_adc_vref_1v8: adc_vref_1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vref_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ }; -+ -+ sound-cs42888 { -+ compatible = "fsl,imx8qm-sabreauto-cs42888", -+ "fsl,imx-audio-cs42888"; -+ model = "imx-cs42888"; -+ audio-cpu = <&esai0>; -+ audio-codec = <&codec>; -+ audio-asrc = <&asrc0>; -+ audio-routing = -+ "Line Out Jack", "AOUT1L", -+ "Line Out Jack", "AOUT1R", -+ "Line Out Jack", "AOUT2L", -+ "Line Out Jack", "AOUT2R", -+ "Line Out Jack", "AOUT3L", -+ "Line Out Jack", "AOUT3R", -+ "Line Out Jack", "AOUT4L", -+ "Line Out Jack", "AOUT4R", -+ "AIN1L", "Line In Jack", -+ "AIN1R", "Line In Jack", -+ "AIN2L", "Line In Jack", -+ "AIN2R", "Line In Jack"; -+ status = "okay"; -+ }; -+}; -+ -+&acm { -+ status = "okay"; -+}; -+ -+&adc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_adc0>; -+ vref-supply = <®_adc_vref_1v8>; -+ status = "okay"; -+}; -+ -+&amix { -+ status = "okay"; -+}; -+ -+&asrc0 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&asrc1 { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&esai0 { -+ compatible = "fsl,imx8qm-esai"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_esai0>; -+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, -+ <&esai0_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; -+ status = "okay"; -+}; -+ -+&sai4 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai4_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&sai5 { -+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, -+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, -+ <&sai5_lpcg 0>; -+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>; -+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; -+ fsl,sai-asynchronous; -+ fsl,txm-rxs; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ imx8qxp-lpddr4-arm2 { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0xc600004c -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 -+ >; -+ }; -+ -+ pinctrl_adc0: adc0grp { -+ fsl,pins = < -+ IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 -+ IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 -+ >; -+ }; -+ -+ pinctrl_csi0_lpi2c0: csi0lpi2c0grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 -+ IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 -+ >; -+ }; -+ -+ pinctrl_esai0: esai0grp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 -+ IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 -+ IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 -+ IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 -+ IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 -+ IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 -+ IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 -+ IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 -+ IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 -+ IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 -+ IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 -+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 -+ IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 -+ IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 -+ IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 -+ IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 -+ IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 -+ IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 -+ IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 -+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 -+ IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 -+ IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 -+ IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 -+ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_fec2: fec2grp { -+ fsl,pins = < -+ IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 -+ IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 -+ IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 -+ IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 -+ IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 -+ IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 -+ IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 -+ IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 -+ IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 -+ IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 -+ IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 -+ IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan0grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 -+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan1grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 -+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_flexcan3: flexcan2grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 -+ IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 -+ >; -+ }; -+ -+ pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 -+ IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 -+ >; -+ }; -+ -+ pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { -+ fsl,pins = < -+ IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 -+ IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 -+ >; -+ }; -+ -+ pinctrl_ptn5150: ptn5150 { -+ fsl,pins = < -+ IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 0x00000021 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 -+ IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 -+ IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 -+ IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 -+ IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 -+ IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 -+ IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 -+ IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 -+ IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 -+ IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 -+ IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 -+ IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 -+ IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 -+ IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 -+ IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 -+ >; -+ }; -+ -+ pinctrl_lpi2c1: lpi1cgrp { -+ fsl,pins = < -+ IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 -+ IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 -+ >; -+ }; -+ -+ pinctrl_lpi2c3: lpi2cgrp { -+ fsl,pins = < -+ IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 -+ IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x0600002c -+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x0600002c -+ >; -+ }; -+ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ IMX8QXP_UART1_TX_ADMA_UART1_TX 0x0600002c -+ IMX8QXP_UART1_RX_ADMA_UART1_RX 0x0600002c -+ IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600002c -+ IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600002c -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x0600002c -+ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x0600002c -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 -+ IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 -+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 -+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 -+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 -+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 -+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 -+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 -+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 -+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 -+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 -+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 -+ IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 -+ IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 -+ IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 -+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 -+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 -+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 -+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 -+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 -+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 -+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 -+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 -+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 -+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 -+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 -+ >; -+ }; -+ -+ pinctrl_pcieb: pciebgrp{ -+ fsl,pins = < -+ IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 -+ IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 -+ IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 -+ >; -+ }; -+ -+ pinctrl_usbotg1: usbotg1 { -+ fsl,pins = < -+ IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ -+ fsl,pins = < -+ IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 -+ IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 -+ >; -+ }; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&fec2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec2>; -+ phy-mode = "rgmii-txid"; -+ phy-handle = <ðphy1>; -+ phy-supply = <®_fec2_supply>; -+ fsl,magic-packet; -+ fsl,rgmii_rxc_dly; -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&flexcan3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan3>; -+ xceiver-supply = <®_can_stby>; -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ virtual-channel; -+ status = "okay"; -+ -+ /* Camera 0 MIPI CSI-2 (CSIS0) */ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&max9286_0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+}; -+ -+&gpio0_mipi_csi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; -+}; -+ -+&isi_0 { -+ status = "okay"; -+}; -+ -+&isi_1 { -+ status = "okay"; -+}; -+ -+&isi_2 { -+ status = "okay"; -+}; -+ -+&isi_3 { -+ status = "okay"; -+}; -+ -+&flexspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt35xu512aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <133000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <8>; -+ }; -+}; -+ -+&i2c_mipi_csi0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ codec: cs42888@48 { -+ compatible = "cirrus,cs42888"; -+ reg = <0x48>; -+ clocks = <&mclkout0_lpcg 0>; -+ clock-names = "mclk"; -+ VA-supply = <®_audio>; -+ VD-supply = <®_audio>; -+ VLS-supply = <®_audio>; -+ VLC-supply = <®_audio>; -+ reset-gpio = <&pca9557_a 2 1>; -+ status = "okay"; -+ }; -+ -+ max9286_mipi@6a { -+ compatible = "maxim,max9286_mipi"; -+ reg = <0x6A>; -+ clocks = <&clk_dummy>; -+ clock-names = "capture_mclk"; -+ mclk = <27000000>; -+ mclk_source = <0>; -+ pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; -+ virtual-channel; -+ status = "okay"; -+ port { -+ max9286_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2 3 4>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1>; -+ status = "okay"; -+ -+ max7322: gpio@68 { -+ compatible = "maxim,max7322"; -+ reg = <0x68>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ typec_ptn5150: typec@3d { -+ compatible = "nxp,ptn5150"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ptn5150>; -+ reg = <0x3d>; -+ connect-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&i2c3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c3>; -+ status = "okay"; -+ -+ pca9557_a: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ pca9557_b: gpio@19 { -+ compatible = "nxp,pca9557"; -+ reg = <0x19>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ status = "okay"; -+}; -+ -+&lpuart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ bus-width = <4>; -+ cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; -+ wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&gpu_3d0 { -+ status = "okay"; -+}; -+ -+&imx8_gpu_ss { -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg1>; -+ srp-disable; -+ hnp-disable; -+ adp-disable; -+ power-polarity-active-high; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&dpu1 { -+ status = "okay"; -+}; -+ -+&pcieb{ -+ ext_osc = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcieb>; -+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; -+ clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&cm40_intmux { -+ status = "okay"; -+}; -+ -+&ldb1_phy { -+ status = "okay"; -+}; -+ -+&ldb1 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds0_out: endpoint { -+ remote-endpoint = <&it6263_0_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi_lvds0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_0_in: endpoint { -+ clock-lanes = <3>; -+ data-lanes = <0 1 2 4>; -+ remote-endpoint = <&lvds0_out>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb2_phy { -+ status = "okay"; -+}; -+ -+&ldb2 { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "jeida"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds1_out: endpoint { -+ remote-endpoint = <&it6263_1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c0_mipi_lvds1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; -+ clock-frequency = <100000>; -+ status = "okay"; -+ -+ lvds-to-hdmi-bridge@4c { -+ compatible = "ite,it6263"; -+ reg = <0x4c>; -+ -+ port { -+ it6263_1_in: endpoint { -+ clock-lanes = <3>; -+ data-lanes = <0 1 2 4>; -+ remote-endpoint = <&lvds1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&vpu_encoder { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/myir-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/myir-imx8mm.dtsi -new file mode 100755 -index 000000000..a4f09c90f ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/myir-imx8mm.dtsi -@@ -0,0 +1,1483 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "imx8mm-pinfunc.h" -+ -+/ { -+ compatible = "fsl,imx8mm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fec1; -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ i2c3 = &i2c4; -+ serial0 = &uart1; -+ serial1 = &uart2; -+ serial2 = &uart3; -+ serial3 = &uart4; -+ spi0 = &ecspi1; -+ spi1 = &ecspi2; -+ spi2 = &ecspi3; -+ mmc0 = &usdhc1; -+ mmc1 = &usdhc2; -+ mmc2 = &usdhc3; -+ gpio0 = &gpio1; -+ gpio1 = &gpio2; -+ gpio2 = &gpio3; -+ gpio3 = &gpio4; -+ gpio4 = &gpio5; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ idle-states { -+ entry-method = "psci"; -+ -+ cpu_pd_wait: cpu-pd-wait { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0010033>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ }; -+ }; -+ -+ A53_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ nvmem-cells = <&cpu_speed_grade>; -+ nvmem-cell-names = "speed_grade"; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a53_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <850000>; -+ opp-supported-hw = <0xe>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <900000>; -+ opp-supported-hw = <0xc>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1000000>; -+ opp-supported-hw = <0x8>, <0x3>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x0 0x40000000 0 0x80000000>; -+ }; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x60000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ -+ osc_32k: clock-osc-32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "osc_32k"; -+ }; -+ -+ osc_24m: clock-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ clk_ext1: clock-ext1 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext1"; -+ }; -+ -+ clk_ext2: clock-ext2 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext2"; -+ }; -+ -+ clk_ext3: clock-ext3 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext3"; -+ }; -+ -+ clk_ext4: clock-ext4 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <133000000>; -+ clock-output-names = "clk_ext4"; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; -+ }; -+ -+ power-domains { -+ compatible = "simple-bus"; -+ /* HSIO SS */ -+ hsiomix_pd: hsiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <0>; -+ domain-name = "hsiomix"; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ }; -+ -+ pcie_pd: pcie-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <1>; -+ domain-name = "pcie"; -+ parent-domains = <&hsiomix_pd>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; -+ }; -+ -+ usb_otg1_pd: usbotg1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <2>; -+ domain-name = "usb_otg1"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ usb_otg2_pd: usbotg2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <3>; -+ domain-name = "usb_otg2"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ /* GPU SS */ -+ gpumix_pd: gpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <4>; -+ domain-name = "gpumix"; -+ clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_CLK_GPU2D_ROOT>, -+ <&clk IMX8MM_CLK_GPU3D_ROOT>; -+ }; -+ -+ /* VPU SS */ -+ vpumix_pd: vpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <5>; -+ domain-name = "vpumix"; -+ clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ }; -+ -+ vpu_g1_pd: vpug1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <6>; -+ domain-name = "vpu_g1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; -+ }; -+ -+ vpu_g2_pd: vpug2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <7>; -+ domain-name = "vpu_g2"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; -+ }; -+ -+ vpu_h1_pd: vpuh1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <8>; -+ domain-name = "vpu_h1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; -+ }; -+ -+ /* DISP SS */ -+ dispmix_pd: dispmix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <9>; -+ domain-name = "dispmix"; -+ clocks = <&clk IMX8MM_CLK_DISP_ROOT>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ }; -+ -+ mipi_pd: mipi-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <10>; -+ domain-name = "mipi"; -+ parent-domains = <&dispmix_pd>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8000000>; -+ arm,no-tick-in-suspend; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tmu>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit0: trip1 { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ usbphynop1: usbphynop1 { -+ compatible = "usb-nop-xceiv"; -+ clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; -+ clock-names = "main_clk"; -+ }; -+ -+ usbphynop2: usbphynop2 { -+ compatible = "usb-nop-xceiv"; -+ clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; -+ clock-names = "main_clk"; -+ }; -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT>, -+ <&clk IMX8MM_CLK_DRAM_APB>, <&clk IMX8MM_CLK_DRAM_APB>, -+ <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, -+ <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, -+ <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, -+ <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, -+ <&clk IMX8MM_DRAM_PLL>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", -+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", -+ "sys_pll1_800m", "dram_pll_div"; -+ interrupts = , , -+ , ; -+ interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; -+ -+ aips1: bus@30000000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30000000 0x30000000 0x400000>; -+ -+ sai1: sai@30010000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30010000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xff 0xff>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@30020000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30020000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>, -+ <&clk IMX8MM_CLK_SAI2_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@30030000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30030000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>, -+ <&clk IMX8MM_CLK_SAI3_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@30050000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30050000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xf 0xf>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@30060000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30060000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI6_IPG>, -+ <&clk IMX8MM_CLK_SAI6_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ micfil: micfil@30080000 { -+ compatible = "fsl,imx8mm-micfil"; -+ reg = <0x30080000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&clk IMX8MM_CLK_PDM_IPG>, -+ <&clk IMX8MM_CLK_PDM_ROOT>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>, -+ <&clk IMX8MM_CLK_EXT3>; -+ clock-names = "ipg_clk", "ipg_clk_app", -+ "pll8k", "pll11k", "clkext3"; -+ dmas = <&sdma2 24 25 0x80000000>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ spdif1: spdif@30090000 { -+ compatible = "fsl,imx8mm-spdif"; -+ reg = <0x30090000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ -+ <&clk IMX8MM_CLK_24M>, /* rxtx0 */ -+ <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MM_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ gpio1: gpio@30200000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30200000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 10 30>; -+ }; -+ -+ gpio2: gpio@30210000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30210000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 40 21>; -+ }; -+ -+ gpio3: gpio@30220000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30220000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 61 26>; -+ }; -+ -+ gpio4: gpio@30230000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30230000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 87 32>; -+ }; -+ -+ gpio5: gpio@30240000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30240000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 119 30>; -+ }; -+ -+ tmu: tmu@30260000 { -+ compatible = "fsl,imx8mm-tmu"; -+ reg = <0x30260000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_TMU_ROOT>; -+ #thermal-sensor-cells = <0>; -+ }; -+ -+ wdog1: watchdog@30280000 { -+ compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; -+ reg = <0x30280000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ wdog2: watchdog@30290000 { -+ compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; -+ reg = <0x30290000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; -+ status = "disabled"; -+ }; -+ -+ wdog3: watchdog@302a0000 { -+ compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; -+ reg = <0x302a0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; -+ status = "disabled"; -+ }; -+ -+ sdma2: dma-controller@302c0000 { -+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; -+ reg = <0x302c0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, -+ <&clk IMX8MM_CLK_SDMA2_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ }; -+ -+ sdma3: dma-controller@302b0000 { -+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; -+ reg = <0x302b0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, -+ <&clk IMX8MM_CLK_SDMA3_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ }; -+ -+ iomuxc: pinctrl@30330000 { -+ compatible = "fsl,imx8mm-iomuxc"; -+ reg = <0x30330000 0x10000>; -+ }; -+ -+ gpr: iomuxc-gpr@30340000 { -+ compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; -+ reg = <0x30340000 0x10000>; -+ }; -+ -+ ocotp: ocotp-ctrl@30350000 { -+ compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; -+ reg = <0x30350000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; -+ /* For nvmem subnodes */ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_speed_grade: speed-grade@10 { -+ reg = <0x10 4>; -+ }; -+ -+ fec_mac_address: mac-address@640 { -+ reg = <0x90 6>; -+ }; -+ }; -+ -+ anatop: anatop@30360000 { -+ compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; -+ reg = <0x30360000 0x10000>; -+ }; -+ -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ }; -+ -+ snvs: snvs@30370000 { -+ compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; -+ reg = <0x30370000 0x10000>; -+ -+ snvs_rtc: snvs-rtc-lp { -+ compatible = "fsl,sec-v4.0-mon-rtc-lp"; -+ regmap = <&snvs>; -+ offset = <0x34>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; -+ clock-names = "snvs-rtc"; -+ }; -+ -+ snvs_pwrkey: snvs-powerkey { -+ compatible = "fsl,sec-v4.0-pwrkey"; -+ regmap = <&snvs>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; -+ clock-names = "snvs"; -+ linux,keycode = ; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ }; -+ -+ clk: clock-controller@30380000 { -+ compatible = "fsl,imx8mm-ccm"; -+ reg = <0x30380000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, -+ <&clk_ext3>, <&clk_ext4>; -+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", -+ "clk_ext3", "clk_ext4"; -+ assigned-clocks = <&clk IMX8MM_CLK_NOC>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, -+ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, -+ <&clk IMX8MM_SYS_PLL3>, -+ <&clk IMX8MM_VIDEO_PLL1>, -+ <&clk IMX8MM_AUDIO_PLL1>, -+ <&clk IMX8MM_AUDIO_PLL2>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, -+ <400000000>, -+ <400000000>, -+ <750000000>, -+ <594000000>, -+ <393216000>, -+ <361267200>; -+ }; -+ -+ src: reset-controller@30390000 { -+ compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; -+ reg = <0x30390000 0x10000>; -+ interrupts = ; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ aips2: bus@30400000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30400000 0x30400000 0x400000>; -+ -+ pwm1: pwm@30660000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30660000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, -+ <&clk IMX8MM_CLK_PWM1_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@30670000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30670000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, -+ <&clk IMX8MM_CLK_PWM2_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@30680000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30680000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, -+ <&clk IMX8MM_CLK_PWM3_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@30690000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30690000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, -+ <&clk IMX8MM_CLK_PWM4_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ system_counter: timer@306a0000 { -+ compatible = "nxp,sysctr-timer"; -+ reg = <0x306a0000 0x20000>; -+ interrupts = ; -+ clocks = <&osc_24m>; -+ clock-names = "per"; -+ }; -+ }; -+ -+ aips3: bus@30800000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x8000000 0x8000000 0x10000000>; -+ -+ flexspi: spi@30bb0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mm-fspi"; -+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, -+ <&clk IMX8MM_CLK_QSPI_ROOT>; -+ clock-names = "fspi", "fspi_en"; -+ status = "disabled"; -+ }; -+ -+ ecspi1: spi@30820000 { -+ compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30820000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, -+ <&clk IMX8MM_CLK_ECSPI1_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi2: spi@30830000 { -+ compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30830000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, -+ <&clk IMX8MM_CLK_ECSPI2_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi3: spi@30840000 { -+ compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30840000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, -+ <&clk IMX8MM_CLK_ECSPI3_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@30860000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30860000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART1_ROOT>, -+ <&clk IMX8MM_CLK_UART1_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@30880000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30880000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART3_ROOT>, -+ <&clk IMX8MM_CLK_UART3_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@30890000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30890000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART2_ROOT>, -+ <&clk IMX8MM_CLK_UART2_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ crypto: crypto@30900000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ reg = <0x30900000 0x40000>; -+ ranges = <0 0x30900000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_AHB>, -+ <&clk IMX8MM_CLK_IPG_ROOT>; -+ clock-names = "aclk", "ipg"; -+ -+ sec_jr0: jr@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr1: jr@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr2: jr@3000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x3000 0x1000>; -+ interrupts = ; -+ }; -+ }; -+ -+ i2c1: i2c@30a20000 { -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30a20000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@30a30000 { -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30a30000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@30a40000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@30a50000 { -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30a50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART4_ROOT>, -+ <&clk IMX8MM_CLK_UART4_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ mu: mu@30aa0000 { -+ compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; -+ reg = <0x30aa0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_MU_ROOT>; -+ clock-names = "mu"; -+ #mbox-cells = <2>; -+ }; -+ -+ usdhc1: mmc@30b40000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MM_CLK_USDHC1_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc2: mmc@30b50000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MM_CLK_USDHC2_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MM_CLK_USDHC3_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ sdma1: dma-controller@30bd0000 { -+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; -+ reg = <0x30bd0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, -+ <&clk IMX8MM_CLK_AHB>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ }; -+ -+ fec1: ethernet@30be0000 { -+ compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; -+ reg = <0x30be0000 0x10000>; -+ interrupts = , -+ , -+ ; -+ clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, -+ <&clk IMX8MM_CLK_ENET1_ROOT>, -+ <&clk IMX8MM_CLK_ENET_TIMER>, -+ <&clk IMX8MM_CLK_ENET_REF>, -+ <&clk IMX8MM_CLK_ENET_PHY_REF>; -+ clock-names = "ipg", "ahb", "ptp", -+ "enet_clk_ref", "enet_out"; -+ assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, -+ <&clk IMX8MM_CLK_ENET_TIMER>, -+ <&clk IMX8MM_CLK_ENET_REF>, -+ <&clk IMX8MM_CLK_ENET_TIMER>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, -+ <&clk IMX8MM_SYS_PLL2_100M>, -+ <&clk IMX8MM_SYS_PLL2_125M>; -+ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; -+ fsl,num-tx-queues = <3>; -+ fsl,num-rx-queues = <3>; -+ nvmem-cells = <&fec_mac_address>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ stop-mode = <&gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; -+ status = "disabled"; -+ }; -+ -+ }; -+ -+ aips4: bus@32c00000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x32c00000 0x32c00000 0x400000>; -+ -+ lcdif: lcdif@32e00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-lcdif"; -+ reg = <0x32e00000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MM_CLK_DISP_AXI>, -+ <&clk IMX8MM_CLK_DISP_APB>; -+ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, -+ <&clk IMX8MM_SYS_PLL2_1000M>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rate = <594000000>, <500000000>, <200000000>; -+ interrupts = ; -+ lcdif-gpr = <&dispmix_gpr>; -+ resets = <&lcdif_resets>; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ -+ lcdif_disp0: port@0 { -+ reg = <0>; -+ -+ lcdif_to_dsim: endpoint { -+ remote-endpoint = <&dsim_from_lcdif>; -+ }; -+ }; -+ }; -+ -+ mipi_dsi: mipi_dsi@32e10000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-mipi-dsim"; -+ reg = <0x32e10000 0x400>; -+ clocks = <&clk IMX8MM_CLK_DSI_CORE>, -+ <&clk IMX8MM_CLK_DSI_PHY_REF>; -+ clock-names = "cfg", "pll-ref"; -+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, -+ <&clk IMX8MM_CLK_DSI_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, -+ <&clk IMX8MM_VIDEO_PLL1_OUT>; -+ assigned-clock-rates = <266000000>, <594000000>; -+ interrupts = ; -+ dsi-gpr = <&dispmix_gpr>; -+ resets = <&mipi_dsi_resets>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ dsim_from_lcdif: endpoint { -+ remote-endpoint = <&lcdif_to_dsim>; -+ }; -+ }; -+ }; -+ -+ csi1_bridge: csi1_bridge@32e20000 { -+ compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x32e20000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_CSI1_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: mipi_csi@32e30000 { -+ compatible = "fsl,imx8mm-mipi-csi"; -+ reg = <0x32e30000 0x1000>; -+ interrupts = ; -+ clock-frequency = <333000000>; -+ clocks = <&clk IMX8MM_CLK_CSI1_CORE>, -+ <&clk IMX8MM_CLK_CSI1_PHY_REF>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; -+ bus-width = <4>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ }; -+ -+ dispmix_gpr: display-gpr@32e28000 { -+ compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; -+ reg = <0x32e28000 0x100>; -+ }; -+ -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif_disp0>; -+ }; -+ -+ usbotg1: usb@32e40000 { -+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; -+ reg = <0x32e40000 0x200>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ clock-names = "usb1_ctrl_root_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; -+ fsl,usbphy = <&usbphynop1>; -+ fsl,usbmisc = <&usbmisc1 0>; -+ power-domains = <&usb_otg1_pd>; -+ status = "disabled"; -+ }; -+ -+ usbmisc1: usbmisc@32e40200 { -+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; -+ #index-cells = <1>; -+ reg = <0x32e40200 0x200>; -+ }; -+ -+ usbotg2: usb@32e50000 { -+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; -+ reg = <0x32e50000 0x200>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ clock-names = "usb1_ctrl_root_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; -+ fsl,usbphy = <&usbphynop2>; -+ fsl,usbmisc = <&usbmisc2 0>; -+ power-domains = <&usb_otg2_pd>; -+ status = "disabled"; -+ }; -+ -+ usbmisc2: usbmisc@32e50200 { -+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; -+ #index-cells = <1>; -+ reg = <0x32e50200 0x200>; -+ }; -+ -+ pcie_phy: pcie-phy@32f00000 { -+ compatible = "fsl,imx7d-pcie-phy"; -+ reg = <0x32f00000 0x10000>; -+ }; -+ }; -+ -+ dma_apbh: dma-controller@33000000 { -+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; -+ reg = <0x33000000 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ }; -+ -+ gpmi: nand-controller@33002000{ -+ compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&clk IMX8MM_CLK_NAND_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ clock-names = "gpmi_io", "gpmi_bch_apb"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ status = "disabled"; -+ }; -+ -+ pcie0: pcie@33800000 { -+ compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; -+ reg = <0x33800000 0x400000>, -+ <0x1ff00000 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pcie_pd>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "clkreq", "turnoff"; -+ fsl,imx7d-pcie-phy = <&pcie_phy>; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x38800000 0x10000>, /* GIC Dist */ -+ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ -+ ddr-pmu@3d800000 { -+ compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; -+ reg = <0x3d800000 0x400000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ dispmix-reset { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { -+ compatible = "fsl,imx8mm-dispmix-sft-rstn"; -+ reg = <0x0 0x32e28000 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_clk_en: dispmix-clk-en@32e28004 { -+ compatible = "fsl,imx8mm-dispmix-clk-en"; -+ reg = <0x0 0x32e28004 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { -+ compatible = "fsl,imx8mm-dispmix-mipi-rst"; -+ reg = <0x0 0x32e28008 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ lcdif_resets: lcdif-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ lcdif-clk-enable { -+ compatible = "lcdif,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, -+ <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; -+ }; -+ }; -+ -+ mipi_dsi_resets: mipi-dsi-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ dsi-soft-resetn { -+ compatible = "dsi,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; -+ }; -+ -+ dsi-clk-enable { -+ compatible = "dsi,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, -+ <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; -+ }; -+ -+ dsi-mipi-reset { -+ compatible = "dsi,mipi-reset"; -+ resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; -+ }; -+ }; -+ -+ rpmsg: rpmsg{ -+ compatible = "fsl,imx8mq-rpmsg"; -+ /* up to now, the following channels are used in imx rpmsg -+ * - tx1/rx1: messages channel. -+ * - general interrupt1: remote proc finish re-init rpmsg stack -+ * when A core is partition reset. -+ */ -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ status = "disabled"; -+ }; -+ -+ vpu_h1: vpu_h1@38320000 { -+ compatible = "nxp,imx8mm-hantro-h1"; -+ reg = <0x0 0x38320000 0x0 0x10000>; -+ reg-names = "regs_hantro_h1"; -+ interrupts = ; -+ interrupt-names = "irq_hantro_h1"; -+ clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_h1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g1: vpu_g1@38300000 { -+ compatible = "nxp,imx8mm-hantro"; -+ reg = <0x0 0x38300000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_g1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g2: vpu_g2@38310000 { -+ compatible = "nxp,imx8mm-hantro"; -+ reg = <0x0 0x38310000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_g2_pd>; -+ status = "disabled"; -+ }; -+ -+ gpu: gpu@38000000 { -+ compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; -+ reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, -+ <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "phys_baseaddr", "contiguous_mem"; -+ interrupts = , -+ ; -+ interrupt-names = "irq_3d", "irq_2d"; -+ clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_CLK_GPU2D_ROOT>, -+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>; -+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", -+ "gpu3d_axi_clk", "gpu3d_ahb_clk", -+ "gpu2d_clk", "gpu2d_axi_clk", -+ "gpu2d_ahb_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, -+ <&clk IMX8MM_CLK_GPU2D_SRC>, -+ <&clk IMX8MM_CLK_GPU_AXI>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_GPU_PLL_OUT>; -+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, -+ <&clk IMX8MM_GPU_PLL_OUT>, -+ <&clk IMX8MM_SYS_PLL1_800M>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; -+ -+ power-domains = <&gpumix_pd>; -+ -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi -new file mode 100644 -index 000000000..0a68ec4c0 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi -@@ -0,0 +1,55 @@ -+/* -+ * QorIQ BMan SDK Portals device tree nodes -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * Copyright 2017 NXP -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+ */ -+ -+&bportals { -+ bman-portal@0 { -+ cell-index = <0>; -+ }; -+ -+ bman-portal@10000 { -+ cell-index = <1>; -+ }; -+ -+ bman-portal@20000 { -+ cell-index = <2>; -+ }; -+ -+ bman-portal@30000 { -+ cell-index = <3>; -+ }; -+ -+ bman-portal@40000 { -+ cell-index = <4>; -+ }; -+ -+ bman-portal@50000 { -+ cell-index = <5>; -+ }; -+ -+ bman-portal@60000 { -+ cell-index = <6>; -+ }; -+ -+ bman-portal@70000 { -+ cell-index = <7>; -+ }; -+ -+ bman-portal@80000 { -+ cell-index = <8>; -+ }; -+ -+ bman-portal@90000 { -+ cell-index = <9>; -+ }; -+ -+ bman-bpids@0 { -+ compatible = "fsl,bpid-range"; -+ fsl,bpid-range = <32 32>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi -new file mode 100644 -index 000000000..d3ae39944 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi -@@ -0,0 +1,72 @@ -+/* -+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ] -+ * -+ * Copyright 2012 - 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+fsldpaa: fsl,dpaa { -+ compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet0>; -+ dma-coherent; -+ }; -+ ethernet@1 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet1>; -+ dma-coherent; -+ }; -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet2>; -+ dma-coherent; -+ }; -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet3>; -+ dma-coherent; -+ }; -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet4>; -+ dma-coherent; -+ }; -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet5>; -+ dma-coherent; -+ }; -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet6>; -+ dma-coherent; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi -index dbd2fc3ba..801b6d095 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi -@@ -9,16 +9,17 @@ - fman@1a00000 { - fman0_rx_0x10: port@90000 { - cell-index = <0x10>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; - reg = <0x90000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x30: port@b0000 { - cell-index = <0x30>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; - reg = <0xb0000 0x1000>; - fsl,fman-10g-port; -+ fsl,qman-channel-id = <0x800>; - }; - - ethernet@f0000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi -index 6fc5d2560..dad547c44 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi -@@ -9,16 +9,17 @@ - fman@1a00000 { - fman0_rx_0x11: port@91000 { - cell-index = <0x11>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; - reg = <0x91000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x31: port@b1000 { - cell-index = <0x31>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; - reg = <0xb1000 0x1000>; - fsl,fman-10g-port; -+ fsl,qman-channel-id = <0x801>; - }; - - ethernet@f2000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi -index 4e02276fc..60ed4473e 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi -@@ -9,14 +9,15 @@ - fman@1a00000 { - fman0_rx_0x08: port@88000 { - cell-index = <0x8>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; - reg = <0x88000 0x1000>; - }; - - fman0_tx_0x28: port@a8000 { - cell-index = <0x28>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; - reg = <0xa8000 0x1000>; -+ fsl,qman-channel-id = <0x802>; - }; - - ethernet@e0000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi -index 0312fa43f..69de2c1ff 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi -@@ -9,14 +9,15 @@ - fman@1a00000 { - fman0_rx_0x09: port@89000 { - cell-index = <0x9>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; - reg = <0x89000 0x1000>; - }; - - fman0_tx_0x29: port@a9000 { - cell-index = <0x29>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; - reg = <0xa9000 0x1000>; -+ fsl,qman-channel-id = <0x803>; - }; - - ethernet@e2000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi -index af2df0797..981bbfcaa 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi -@@ -9,14 +9,15 @@ - fman@1a00000 { - fman0_rx_0x0a: port@8a000 { - cell-index = <0xa>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; - reg = <0x8a000 0x1000>; - }; - - fman0_tx_0x2a: port@aa000 { - cell-index = <0x2a>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; - reg = <0xaa000 0x1000>; -+ fsl,qman-channel-id = <0x804>; - }; - - ethernet@e4000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi -index 4ac98dc8b..956b1b9df 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi -@@ -9,14 +9,15 @@ - fman@1a00000 { - fman0_rx_0x0b: port@8b000 { - cell-index = <0xb>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; - reg = <0x8b000 0x1000>; - }; - - fman0_tx_0x2b: port@ab000 { - cell-index = <0x2b>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; - reg = <0xab000 0x1000>; -+ fsl,qman-channel-id = <0x805>; - }; - - ethernet@e6000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi -index bd932d8b0..52899ce69 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi -@@ -9,14 +9,15 @@ - fman@1a00000 { - fman0_rx_0x0c: port@8c000 { - cell-index = <0xc>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; - reg = <0x8c000 0x1000>; - }; - - fman0_tx_0x2c: port@ac000 { - cell-index = <0x2c>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; - reg = <0xac000 0x1000>; -+ fsl,qman-channel-id = <0x806>; - }; - - ethernet@e8000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi -index 7de1c5203..fe8c4c29b 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi -@@ -9,14 +9,15 @@ - fman@1a00000 { - fman0_rx_0x0d: port@8d000 { - cell-index = <0xd>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; - reg = <0x8d000 0x1000>; - }; - - fman0_tx_0x2d: port@ad000 { - cell-index = <0x2d>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; - reg = <0xad000 0x1000>; -+ fsl,qman-channel-id = <0x807>; - }; - - ethernet@ea000 { -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi -new file mode 100644 -index 000000000..2d0df20db ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi -@@ -0,0 +1,47 @@ -+/* -+ * QorIQ FMan v3 OH ports device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+ */ -+ -+fman@1a00000 { -+ -+ fman0_oh1: port@82000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x82000 0x1000>; -+ }; -+ -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+ -+ fman0_oh3: port@84000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x84000 0x1000>; -+ }; -+ -+ fman0_oh4: port@85000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x85000 0x1000>; -+ }; -+ -+ fman0_oh5: port@86000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x86000 0x1000>; -+ }; -+ -+ fman0_oh6: port@87000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x87000 0x1000>; -+ }; -+ -+}; -diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi -index 4338db14c..1fb902246 100644 ---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi -@@ -21,45 +21,95 @@ fman0: fman@1a00000 { - ptimer-handle = <&ptp_timer0>; - dma-coherent; - -+ cc { -+ compatible = "fsl,fman-cc"; -+ }; -+ - muram@0 { - compatible = "fsl,fman-muram"; - reg = <0x0 0x60000>; - }; - -+ bmi@80000 { -+ compatible = "fsl,fman-bmi"; -+ reg = <0x80000 0x400>; -+ }; -+ -+ qmi@80400 { -+ compatible = "fsl,fman-qmi"; -+ reg = <0x80400 0x400>; -+ }; -+ - fman0_oh_0x2: port@82000 { - cell-index = <0x2>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x82000 0x1000>; -+ fsl,qman-channel-id = <0x809>; - }; - - fman0_oh_0x3: port@83000 { - cell-index = <0x3>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x83000 0x1000>; -+ fsl,qman-channel-id = <0x80a>; - }; - - fman0_oh_0x4: port@84000 { - cell-index = <0x4>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x84000 0x1000>; -+ fsl,qman-channel-id = <0x80b>; - }; - - fman0_oh_0x5: port@85000 { - cell-index = <0x5>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x85000 0x1000>; -+ fsl,qman-channel-id = <0x80c>; - }; - - fman0_oh_0x6: port@86000 { - cell-index = <0x6>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x86000 0x1000>; -+ fsl,qman-channel-id = <0x80d>; - }; - - fman0_oh_0x7: port@87000 { - cell-index = <0x7>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x87000 0x1000>; -+ fsl,qman-channel-id = <0x80e>; -+ }; -+ -+ policer@c0000 { -+ compatible = "fsl,fman-policer"; -+ reg = <0xc0000 0x1000>; -+ }; -+ -+ keygen@c1000 { -+ compatible = "fsl,fman-keygen"; -+ reg = <0xc1000 0x1000>; -+ }; -+ -+ dma@c2000 { -+ compatible = "fsl,fman-dma"; -+ reg = <0xc2000 0x1000>; -+ }; -+ -+ fpm@c3000 { -+ compatible = "fsl,fman-fpm"; -+ reg = <0xc3000 0x1000>; -+ }; -+ -+ parser@c7000 { -+ compatible = "fsl,fman-parser"; -+ reg = <0xc7000 0x1000>; -+ }; -+ -+ vsps@dc000 { -+ compatible = "fsl,fman-vsps"; -+ reg = <0xdc000 0x1000>; - }; - - mdio0: mdio@fc000 { -@@ -78,7 +128,7 @@ xmdio0: mdio@fd000 { - }; - - ptp_timer0: ptp-timer@1afe000 { -- compatible = "fsl,fman-ptp-timer"; -+ compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc"; - reg = <0x0 0x1afe000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 3 0>; -diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi -new file mode 100644 -index 000000000..d3abfaf6e ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi -@@ -0,0 +1,38 @@ -+/* -+ * QorIQ QMan SDK Portals device tree nodes -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * Copyright 2017 NXP -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+ */ -+ -+&qportals { -+ qman-fqids@0 { -+ compatible = "fsl,fqid-range"; -+ fsl,fqid-range = <256 256>; -+ }; -+ -+ qman-fqids@1 { -+ compatible = "fsl,fqid-range"; -+ fsl,fqid-range = <32768 32768>; -+ }; -+ -+ qman-pools@0 { -+ compatible = "fsl,pool-channel-range"; -+ fsl,pool-channel-range = <0x401 0xf>; -+ }; -+ -+ qman-cgrids@0 { -+ compatible = "fsl,cgrid-range"; -+ fsl,cgrid-range = <0 256>; -+ }; -+ -+ qman-ceetm@0 { -+ compatible = "fsl,qman-ceetm"; -+ fsl,ceetm-lfqid-range = <0xf00000 0x1000>; -+ fsl,ceetm-sp-range = <0 16>; -+ fsl,ceetm-lni-range = <0 8>; -+ fsl,ceetm-channel-range = <0 32>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boot/dts/freescale/s32v234-evb.dts -index 4b802518c..70dfa31d9 100644 ---- a/arch/arm64/boot/dts/freescale/s32v234-evb.dts -+++ b/arch/arm64/boot/dts/freescale/s32v234-evb.dts -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-or-later - /* - * Copyright 2015-2016 Freescale Semiconductor, Inc. -- * Copyright 2016-2017 NXP -+ * Copyright 2016-2017,2019 NXP - */ - - /dts-v1/; -@@ -16,10 +16,105 @@ chosen { - }; - }; - -+&can0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can0>; -+ status = "okay"; -+}; -+ -+&can1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can1>; -+ status = "okay"; -+}; -+ -+&edma { -+ status = "okay"; -+}; -+ -+&siul2 { -+ status = "okay"; -+ s32v234-evb { -+ -+ /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the -+ * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference -+ * Manual states. -+ */ -+ -+ pinctrl_can0: can0grp { -+ fsl,pins = < -+ S32V234_PAD_PA2__CAN_FD0_TXD -+ S32V234_PAD_PA3__CAN_FD0_RXD_OUT -+ S32V234_PAD_PA3__CAN_FD0_RXD_IN -+ >; -+ }; -+ -+ pinctrl_can1: can1grp { -+ fsl,pins = < -+ S32V234_PAD_PA4__CAN_FD1_TXD -+ S32V234_PAD_PA5__CAN_FD1_RXD_OUT -+ S32V234_PAD_PA5__CAN_FD1_RXD_IN -+ >; -+ }; -+ -+ pinctrl_uart0: uart0grp { -+ fsl,pins = < -+ S32V234_PAD_PA12__UART0_TXD -+ S32V234_PAD_PA11__UART0_RXD_OUT -+ S32V234_PAD_PA11__UART0_RXD_IN -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ S32V234_PAD_PA14__UART1_TXD -+ S32V234_PAD_PA13__UART1_RXD_OUT -+ S32V234_PAD_PA13__UART1_RXD_IN -+ >; -+ }; -+ -+ pinctrl_usdhc0: usdhc0grp { -+ fsl,pins = < -+ S32V234_PAD_PK6__USDHC_CLK_OUT -+ S32V234_PAD_PK6__USDHC_CLK_IN -+ S32V234_PAD_PK7__USDHC_CMD_OUT -+ S32V234_PAD_PK7__USDHC_CMD_IN -+ S32V234_PAD_PK8__USDHC_DAT0_OUT -+ S32V234_PAD_PK8__USDHC_DAT0_IN -+ S32V234_PAD_PK9__USDHC_DAT1_OUT -+ S32V234_PAD_PK9__USDHC_DAT1_IN -+ S32V234_PAD_PK10__USDHC_DAT2_OUT -+ S32V234_PAD_PK10__USDHC_DAT2_IN -+ S32V234_PAD_PK11__USDHC_DAT3_OUT -+ S32V234_PAD_PK11__USDHC_DAT3_IN -+ S32V234_PAD_PK15__USDHC_DAT4_OUT -+ S32V234_PAD_PK15__USDHC_DAT4_IN -+ S32V234_PAD_PL0__USDHC_DAT5_OUT -+ S32V234_PAD_PL0__USDHC_DAT5_IN -+ S32V234_PAD_PL1__USDHC_DAT6_OUT -+ S32V234_PAD_PL1__USDHC_DAT6_IN -+ S32V234_PAD_PL2__USDHC_DAT7_OUT -+ S32V234_PAD_PL2__USDHC_DAT7_IN -+ >; -+ }; -+ }; -+}; -+ - &uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; - }; - - &uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&usdhc0 { -+ no-1-8-v; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc0>; - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts -new file mode 100644 -index 000000000..2b5b1e305 ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts -@@ -0,0 +1,187 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 MicroSys Electronics GmbH -+ * Copyright 2018-2019 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+/dts-v1/; -+ -+#include "s32v234.dtsi" -+ -+/ { -+ model = "Freescale S32V234"; -+ compatible = "fsl,s32v234-sbc", "fsl,s32v234"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&can0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can0>; -+ status = "okay"; -+}; -+ -+&can1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can1>; -+ status = "okay"; -+}; -+ -+&edma { -+ status = "okay"; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy0>; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ }; -+}; -+ -+&siul2 { -+ status = "okay"; -+ -+ s32v234-sbc { -+ /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the -+ * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference -+ * Manual states. -+ */ -+ -+ pinctrl_can0: can0grp { -+ fsl,pins = < -+ S32V234_PAD_PA2__CAN_FD0_TXD -+ S32V234_PAD_PA3__CAN_FD0_RXD_OUT -+ S32V234_PAD_PA3__CAN_FD0_RXD_IN -+ /* -+ * Configure pin C12 as GPIO[6] in MSCR#6. -+ * Effect: the S-pin at CAN is not longer -+ * flowting at ~0.75V, but driven to low ~0.0V. -+ */ -+ S32V234_MSCR_PA6 (PAD_CTL_MUX_MODE_ALT0 \ -+ | PAD_CTL_OBE \ -+ | PAD_CTL_DSE_34 \ -+ | PAD_CTL_PUS_33K_UP) -+ >; -+ }; -+ -+ pinctrl_can1: can1grp { -+ fsl,pins = < -+ S32V234_PAD_PA4__CAN_FD1_TXD -+ S32V234_PAD_PA5__CAN_FD1_RXD_OUT -+ S32V234_PAD_PA5__CAN_FD1_RXD_IN -+ /* -+ * Configure pin C11 as GPIO[7] in MSCR#7. -+ * Effect: the S-pin at CAN is not longer -+ * flowting at ~0.39V, but driven to low ~0.0V. -+ */ -+ S32V234_MSCR_PA7 (PAD_CTL_MUX_MODE_ALT0 \ -+ | PAD_CTL_OBE \ -+ | PAD_CTL_DSE_34 \ -+ | PAD_CTL_PUS_33K_UP) -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ S32V234_PAD_PC13__MDC -+ S32V234_PAD_PC14__MDIO_OUT -+ S32v234_PAD_PC14__MDIO_IN -+ S32V234_PAD_PC15__TXCLK_OUT -+ S32V234_PAD_PC15__TXCLK_IN -+ S32V234_PAD_PD0__RXCLK_OUT -+ S32V234_PAD_PD0__RXCLK_IN -+ S32V234_PAD_PD1__RX_D0_OUT -+ S32V234_PAD_PD1__RX_D0_IN -+ S32V234_PAD_PD2__RX_D1_OUT -+ S32V234_PAD_PD2__RX_D1_IN -+ S32V234_PAD_PD3__RX_D2_OUT -+ S32V234_PAD_PD3__RX_D2_IN -+ S32V234_PAD_PD4__RX_D3_OUT -+ S32V234_PAD_PD4__RX_D3_IN -+ S32V234_PAD_PD4__RX_DV_OUT -+ S32V234_PAD_PD4__RX_DV_IN -+ S32V234_PAD_PD7__TX_D0_OUT -+ S32V234_PAD_PD8__TX_D1_OUT -+ S32V234_PAD_PD9__TX_D2_OUT -+ S32V234_PAD_PD10__TX_D3_OUT -+ S32V234_PAD_PD11__TX_EN_OUT -+ >; -+ }; -+ -+ pinctrl_uart0: uart0grp { -+ fsl,pins = < -+ S32V234_PAD_PA12__UART0_TXD -+ S32V234_PAD_PA11__UART0_RXD_OUT -+ S32V234_PAD_PA11__UART0_RXD_IN -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ S32V234_PAD_PA14__UART1_TXD -+ S32V234_PAD_PA13__UART1_RXD_OUT -+ S32V234_PAD_PA13__UART1_RXD_IN -+ >; -+ }; -+ -+ pinctrl_usdhc0: usdhc0grp { -+ fsl,pins = < -+ S32V234_PAD_PK6__USDHC_CLK_OUT -+ S32V234_PAD_PK6__USDHC_CLK_IN -+ S32V234_PAD_PK7__USDHC_CMD_OUT -+ S32V234_PAD_PK7__USDHC_CMD_IN -+ S32V234_PAD_PK8__USDHC_DAT0_OUT -+ S32V234_PAD_PK8__USDHC_DAT0_IN -+ S32V234_PAD_PK9__USDHC_DAT1_OUT -+ S32V234_PAD_PK9__USDHC_DAT1_IN -+ S32V234_PAD_PK10__USDHC_DAT2_OUT -+ S32V234_PAD_PK10__USDHC_DAT2_IN -+ S32V234_PAD_PK11__USDHC_DAT3_OUT -+ S32V234_PAD_PK11__USDHC_DAT3_IN -+ S32V234_PAD_PK15__USDHC_DAT4_OUT -+ S32V234_PAD_PK15__USDHC_DAT4_IN -+ S32V234_PAD_PL0__USDHC_DAT5_OUT -+ S32V234_PAD_PL0__USDHC_DAT5_IN -+ S32V234_PAD_PL1__USDHC_DAT6_OUT -+ S32V234_PAD_PL1__USDHC_DAT6_IN -+ S32V234_PAD_PL2__USDHC_DAT7_OUT -+ S32V234_PAD_PL2__USDHC_DAT7_IN -+ >; -+ }; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart0>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&usdhc0 { -+ no-1-8-v; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc0>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi -index ba0b5305d..c162b3049 100644 ---- a/arch/arm64/boot/dts/freescale/s32v234.dtsi -+++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi -@@ -5,6 +5,8 @@ - */ - - #include -+#include -+#include - - /memreserve/ 0x80000000 0x00010000; - -@@ -15,10 +17,28 @@ / { - #size-cells = <2>; - - aliases { -+ can0 = &can0; -+ can1 = &can1; - serial0 = &uart0; - serial1 = &uart1; - }; - -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ firc { -+ compatible = "fixed-clock"; -+ clock-frequency = <48000000>; -+ #clock-cells = <0>; -+ }; -+ fxosc { -+ compatible = "fixed-clock"; -+ clock-frequency = <40000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ - cpus { - #address-cells = <2>; - #size-cells = <0>; -@@ -112,12 +132,117 @@ aips0: bus@40000000 { - reg = <0x0 0x40000000 0x0 0x7d000>; - ranges; - -+ edma: dma-controller@40002000 { -+ #dma-cells = <2>; -+ compatible = "fsl,s32v234-edma"; -+ reg = <0x0 0x40002000 0x0 0x2000>, -+ <0x0 0x40031000 0x0 0x1000>, -+ <0x0 0x400A1000 0x0 0x1000>; -+ dma-channels = <32>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "edma-tx_0-15", -+ "edma-tx_16-31", -+ "edma-err"; -+ clock-names = "dmamux0", "dmamux1"; -+ clocks = <&clks S32V234_CLK_SYS6>, -+ <&clks S32V234_CLK_SYS6>; -+ status = "disabled"; -+ }; -+ -+ fec: ethernet@40032000 { -+ compatible = "fsl,s32v234-fec"; -+ reg = <0x0 0x40032000 0x0 0x1000>; -+ interrupt-names = "int0", "int1", "int2", "pps"; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&clks S32V234_CLK_SYS6>, -+ <&clks S32V234_CLK_SYS3>, -+ <&clks S32V234_CLK_ENET_TIME>, -+ <&clks S32V234_CLK_ENET>, -+ <&clks S32V234_CLK_ENET_TIME>; -+ clock-names = "ipg", "ahb", "ptp", -+ "enet_clk_ref", -+ "enet_out"; -+ fsl,num-tx-queues = <3>; -+ fsl,num-rx-queues = <3>; -+ status = "disabled"; -+ }; -+ -+ clks: mc_cgm0@4003c000 { -+ compatible = "fsl,s32v234-mc_cgm0"; -+ reg = <0x0 0x4003C000 0x0 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ mc_cgm1: mc_cgm1@4003F000 { -+ compatible = "fsl,s32v234-mc_cgm1"; -+ reg = <0x0 0x4003F000 0x0 0x1000>; -+ }; -+ -+ mc_cgm2: mc_cgm2@40042000 { -+ compatible = "fsl,s32v234-mc_cgm2"; -+ reg = <0x0 0x40042000 0x0 0x1000>; -+ }; -+ -+ mc_cgm3: mc_cgm3@40045000 { -+ compatible = "fsl,s32v234-mc_cgm3"; -+ reg = <0x0 0x40045000 0x0 0x1000>; -+ }; -+ -+ mc_me: mc_me@4004a000 { -+ compatible = "fsl,s32v234-mc_me"; -+ reg = <0x0 0x4004A000 0x0 0x1000>; -+ }; -+ - uart0: serial@40053000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x40053000 0x0 0x1000>; - interrupts = ; -+ clocks = <&clks S32V234_CLK_LIN>; -+ clock-names = "lin"; -+ dmas = <&edma 0 20>, -+ <&edma 0 19>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ can0: flexcan@40055000 { -+ compatible = "fsl,s32v234-flexcan"; -+ reg = <0x0 0x40055000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clks S32V234_CLK_CAN>, -+ <&clks S32V234_CLK_CAN>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ usdhc0: usdhc@4005d000 { -+ compatible = "fsl,s32v234-usdhc"; -+ reg = <0x0 0x4005D000 0x0 0x1000>; -+ interrupts = <0 28 4>; -+ clocks = <&clks S32V234_CLK_SDHC>, -+ <&clks S32V234_CLK_SDHC>, -+ <&clks S32V234_CLK_SDHC>; -+ clock-names = "ipg", "ahb", "per"; -+ bus-width = <8>; - status = "disabled"; - }; -+ -+ siul2: siul@4006c000 { -+ compatible = "fsl,s32v234-siul2"; -+ reg = <0x0 0x4006C000 0x0 0x1794>; -+ status = "disabled"; -+ }; -+ -+ src: src@4007c000 { -+ compatible = "fsl,s32v234-src"; -+ reg = <0x0 0x4007C000 0x0 0x1000>; -+ #reset-cells = <1>; -+ }; - }; - - aips1: bus@40080000 { -@@ -132,6 +257,21 @@ uart1: serial@400bc000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x400bc000 0x0 0x1000>; - interrupts = ; -+ clocks = <&clks S32V234_CLK_LIN>; -+ clock-names = "lin"; -+ dmas = <&edma 1 13>, -+ <&edma 1 12>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ can1: flexcan@400be000 { -+ compatible = "fsl,s32v234-flexcan"; -+ reg = <0x0 0x400be000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clks S32V234_CLK_CAN>, -+ <&clks S32V234_CLK_CAN>; -+ clock-names = "ipg", "per"; - status = "disabled"; - }; - }; -diff --git a/arch/arm64/boot/dts/myir/Makefile b/arch/arm64/boot/dts/myir/Makefile -new file mode 100755 -index 000000000..24b3e4a25 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/Makefile -@@ -0,0 +1,12 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+# required for overlay support -+ -+dtb-$(CONFIG_ARCH_MXC) += myb-imx8mm-base.dtb \ -+ myb-imx8mm-lcd-atk-10-1.dtb \ -+ myb-imx8mm-rpmsg-m4.dtb \ -+ myb-imx8mm-lcd-me190etn01.dtb \ -+ myb-imx8mm-lcd-hontron-7.dtb \ -+ mys-imx8mm-evk-rpmsg.dtb \ -+ mys-imx8mm-lt8912-atk-10-1.dtb \ -+ mys-imx8mm-lt8912-hontron-7.dtb -diff --git a/arch/arm64/boot/dts/myir/imx8mm-pinfunc.h b/arch/arm64/boot/dts/myir/imx8mm-pinfunc.h -new file mode 100644 -index 000000000..cffa89918 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/imx8mm-pinfunc.h -@@ -0,0 +1,629 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2017-2018 NXP -+ */ -+ -+#ifndef __DTS_IMX8MM_PINFUNC_H -+#define __DTS_IMX8MM_PINFUNC_H -+ -+/* -+ * The pin function ID is a tuple of -+ * -+ */ -+ -+#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -+#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 -+#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 -+#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -+#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -+#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -+#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -+#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -+#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -+#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -+#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -+#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -+#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 -+#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -+#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -+#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -+#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -+#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -+#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -+#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -+#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -+#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -+#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -+#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -+#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -+#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -+#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -+#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 -+#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -+#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -+#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -+#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -+#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -+#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -+#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -+#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -+#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -+#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -+#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -+#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -+#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -+#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -+#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -+#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -+#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -+#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -+#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -+#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -+ -+#endif /* __DTS_IMX8MM_PINFUNC_H */ -diff --git a/arch/arm64/boot/dts/myir/imx8mp-pinfunc.h b/arch/arm64/boot/dts/myir/imx8mp-pinfunc.h -new file mode 100755 -index 000000000..319ab34ca ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/imx8mp-pinfunc.h -@@ -0,0 +1,931 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#ifndef __DTS_IMX8MP_PINFUNC_H -+#define __DTS_IMX8MP_PINFUNC_H -+ -+/* -+ * The pin function ID is a tuple of -+ * -+ */ -+#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL 0x014 0x274 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE 0x018 0x278 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x020 0x280 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE 0x020 0x280 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x024 0x284 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG 0x024 0x284 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x028 0x288 0x554 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x028 0x288 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG 0x028 0x288 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG 0x02C 0x28C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG 0x030 0x290 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x034 0x294 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG 0x034 0x294 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x038 0x298 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG 0x038 0x298 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED 0x03C 0x29C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 -+#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x040 0x2A0 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS 0x040 0x2A0 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x044 0x2A4 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00 0x044 0x2A4 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x048 0x2A8 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01 0x048 0x2A8 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02 0x04C 0x2AC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x050 0x2B0 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB 0x050 0x2B0 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15 0x054 0x2B4 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 -+#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16 0x058 0x2B8 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17 0x05C 0x2BC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18 0x060 0x2C0 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 -+#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19 0x064 0x2C4 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 -+#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20 0x068 0x2C8 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT 0x06C 0x2CC 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21 0x06C 0x2CC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 -+#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 -+#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 -+#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 -+#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK 0x084 0x2E4 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27 0x084 0x2E4 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 -+#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN 0x088 0x2E8 0x544 0x3 0x0 -+#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 -+#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28 0x088 0x2E8 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29 0x08C 0x2EC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 -+#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30 0x090 0x2F0 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31 0x094 0x2F4 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 -+#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00 0x098 0x2F8 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01 0x09C 0x2FC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 -+#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02 0x0A0 0x300 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP 0x0A4 0x304 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 -+#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05 0x0A8 0x308 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06 0x0AC 0x30C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 -+#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07 0x0B0 0x310 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG 0x0B4 0x314 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 -+#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 -+#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG 0x0B8 0x318 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0BC 0x31C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0C0 0x320 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00 0x0C0 0x320 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 -+#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK 0x0C4 0x324 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0C4 0x324 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01 0x0C4 0x324 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 -+#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 -+#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 -+#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 -+#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 -+#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x1 -+#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0CC 0x32C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03 0x0CC 0x32C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 -+#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT 0x0D0 0x330 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x1 -+#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0D0 0x330 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04 0x0D0 0x330 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 -+#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1 -+#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 -+#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK 0x0DC 0x33C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE 0x0E0 0x340 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 -+#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 -+#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00 0x0E0 0x340 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 -+#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 -+#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01 0x0E4 0x344 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 -+#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02 0x0E8 0x348 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 -+#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03 0x0EC 0x34C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 -+#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00 0x0F0 0x350 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0F4 0x354 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 -+#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01 0x0F4 0x354 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 -+#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02 0x0F8 0x358 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 -+#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03 0x0FC 0x35C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x100 0x360 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 -+#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 -+#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04 0x100 0x360 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x104 0x364 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 -+#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 -+#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 -+#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05 0x104 0x364 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x108 0x368 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 -+#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06 0x108 0x368 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07 0x10C 0x36C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x110 0x370 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08 0x110 0x370 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x114 0x374 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09 0x114 0x374 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS 0x118 0x378 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 -+#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10 0x118 0x378 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 -+#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11 0x11C 0x37C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x120 0x380 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 -+#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12 0x120 0x380 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x124 0x384 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 -+#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13 0x124 0x384 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x128 0x388 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 -+#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 -+#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14 0x128 0x388 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 -+#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 -+#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0x130 0x390 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 -+#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 -+#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 -+#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 -+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 -+#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 -+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 -+#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 -+#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 -+#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 -+#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 -+#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x148 0x3A8 0x508 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK 0x14C 0x3AC 0x4F4 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK 0x14C 0x3AC 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 -+#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 -+#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 -+#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 -+#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 -+#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 -+#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC 0x170 0x3D0 0x510 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 -+#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 -+#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK 0x174 0x3D4 0x50C 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 0x178 0x3D8 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 0x17C 0x3DC 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 0x180 0x3E0 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 0x184 0x3E4 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 -+#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 -+#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 -+#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 -+#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 -+#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 -+#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 -+#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK 0x194 0x3F4 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK 0x198 0x3F8 0x4F0 0x1 0x1 -+#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 -+#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 -+#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 -+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 -+#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 -+#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 -+#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 -+#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 -+#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 -+#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 -+#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 -+#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 -+#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 -+#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 -+#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 -+#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 0x1B0 0x410 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK 0x1B0 0x410 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 -+#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 -+#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 -+#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR 0x1B4 0x414 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 -+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 -+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2 -+#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 -+#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 -+#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 -+#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK 0x1BC 0x41C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01 0x1BC 0x41C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 -+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 -+#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 -+#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 -+#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 -+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 -+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 -+#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 -+#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 -+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 -+#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 -+#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 -+#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 -+#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 -+#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 0x1CC 0x42C 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03 0x1CC 0x42C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 -+#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 -+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT 0x1D0 0x430 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN 0x1D0 0x430 0x544 0x6 0x3 -+#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04 0x1D0 0x430 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0x1D4 0x434 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 -+#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0x1D8 0x438 0x544 0x0 0x4 -+#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 -+#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 -+#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 -+#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08 0x1E0 0x440 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09 0x1E4 0x444 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 -+#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 -+#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 -+#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10 0x1E8 0x448 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 -+#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 -+#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 -+#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11 0x1EC 0x44C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12 0x1F0 0x450 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13 0x1F4 0x454 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14 0x1F8 0x458 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 -+#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 -+#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 -+#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 -+#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 0x1F8 0x458 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 -+#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 -+#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 -+#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15 0x1FC 0x45C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 -+#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 -+#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16 0x200 0x460 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 -+#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 -+#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 -+#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17 0x204 0x464 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 -+#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 -+#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 -+#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18 0x208 0x468 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 -+#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 -+#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 -+#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19 0x20C 0x46C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 -+#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 -+#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20 0x210 0x470 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 -+#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 -+#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21 0x214 0x474 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 -+#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 -+#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 -+#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22 0x218 0x478 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 -+#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 -+#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23 0x21C 0x47C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 -+#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24 0x220 0x480 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 -+#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25 0x224 0x484 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 -+#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26 0x228 0x488 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 -+#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27 0x22C 0x48C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 -+#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 -+#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 -+#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28 0x230 0x490 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 -+#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 -+#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 -+#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 -+#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 -+#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29 0x234 0x494 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 -+#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 -+#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 -+#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 -+#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 -+#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30 0x238 0x498 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 -+#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 -+#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 -+#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 -+#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31 0x23C 0x49C 0x000 0x7 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x240 0x4A0 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 -+#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00 0x240 0x4A0 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x244 0x4A4 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 -+#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 -+#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01 0x244 0x4A4 0x000 0x6 0x0 -+#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x248 0x4A8 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 -+#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 -+#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 -+#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x24C 0x4AC 0x000 0x0 0x0 -+#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 -+#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 -+#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 -+#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 -+ -+#endif /* __DTS_IMX8MP_PINFUNC_H */ -diff --git a/arch/arm64/boot/dts/myir/imx8mq-pinfunc.h b/arch/arm64/boot/dts/myir/imx8mq-pinfunc.h -new file mode 100755 -index 000000000..b94b02080 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/imx8mq-pinfunc.h -@@ -0,0 +1,623 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef __DTS_IMX8MQ_PINFUNC_H -+#define __DTS_IMX8MQ_PINFUNC_H -+ -+/* -+ * The pin function ID is a tuple of -+ * -+ */ -+ -+#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -+#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -+#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -+#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -+#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -+#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -+#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -+#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -+#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -+#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -+#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -+#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -+#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -+#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -+#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -+#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -+#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -+#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -+#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -+#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -+#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -+#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -+#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -+#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -+#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -+#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -+#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 -+#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 -+ -+#endif /* __DTS_IMX8MQ_PINFUNC_H */ -diff --git a/arch/arm64/boot/dts/myir/myb-imx8mm-base.dts b/arch/arm64/boot/dts/myir/myb-imx8mm-base.dts -new file mode 100755 -index 000000000..eb3b33f72 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myb-imx8mm-base.dts -@@ -0,0 +1,1019 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 MYiR -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "myb-imx8mm.dtsi" -+ -+/ { -+ model = "MYD-C8MMX-V2.0 i.MX8MM board"; -+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ rpmsg_reserved: rpmsg@0xb8000000 { -+ no-map; -+ reg = <0 0xb8000000 0 0x400000>; -+ }; -+ }; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_led>; -+ -+ led0: cpu { -+ label = "cpu"; -+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user1 { -+ label = "user1"; -+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led2: user2 { -+ label = "user2"; -+ gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ -+ user { -+ label = "User"; -+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -+ gpio-key,wakeup; -+ linux,code = ; -+ }; -+ -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ reg_vmmc: _regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "WLAN_EN"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; -+ // off-on-delay-us = <20000>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_gpio_wifi: regulator@1 { -+ compatible = "regulator-fixed"; -+ regulator-name = "wifi-pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; -+ regulator-boot-on; -+ enable-active-low; -+ regulator-always-on; -+ }; -+ -+ reg_usb_ltemodule: regulator@2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ltemodule-pwr"; -+ regulator-min-microvolt = <3800000>; -+ regulator-max-microvolt = <3800000>; -+ gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_lte_rst: regulator@3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "ltemodule-rst"; -+ regulator-min-microvolt = <3800000>; -+ regulator-max-microvolt = <3800000>; -+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ enable-active-low; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_m2_power_pad: regulator-m2-power-pad { -+ compatible = "regulator-fixed"; -+ regulator-name = "M2_POWER_PAD"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ startup-delay-us = <70000>; -+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ -+ sound { -+ compatible = "fsl,imx-audio-wm8904"; -+ model = "wm8904-audio"; -+ cpu-dai = <&sai3>; -+ audio-codec = <&codec>; -+ // asrc-controller = <&asrc>; -+ asrc-controller; -+ gpr = <&gpr>; -+ audio-routing = -+ "Headphone Jack", "HPOUTL", -+ "Headphone Jack", "HPOUTR", -+ "IN2L", "Line In Jack", -+ "IN2R", "Line In Jack", -+ "Mic Jack", "MICBIAS", -+ "IN1L", "Mic Jack"; -+ }; -+ -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&csi1_bridge { -+ fsl,mipi-mode; -+ status = "okay"; -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&ecspi2{ -+ fsl,spi-num-chipselects= < 1 >; -+ cs-gpios = <&gpio5 13 0 > ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi2>; -+ status = "okay"; -+ #address-cells=<1>; -+ #size-cells=<0>; -+ -+ spidev@0{ -+ #address-cellss=<1>; -+ #size-cells=<1>; -+ compatible = "spidev","rohm,dh2228fv"; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <4>; -+ // at803x,eee-disabled; -+ at803x,led-act-blind-workaround; -+ at803x,eee-okay; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&pcie0{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ disable-gpio = <&gpio2 20 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ ext_osc = <1>; -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, -+ <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", -+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "disabled"; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pdm>; -+ assigned-clocks = <&clk IMX8MM_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "disabled"; -+}; -+ -+&snvs_pwrkey { -+ status = "okay"; -+}; -+ -+/* BT */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+/* console */ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ // fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART4>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+ status = "okay"; -+}; -+ -+ -+&usbotg1 { -+ dr_mode = "otg"; -+ picophy,pre-emp-curr-control = <3>; -+ picophy,dc-vol-level-adjust = <7>; -+ status = "okay"; -+}; -+ -+&usbotg2 { -+ dr_mode = "host"; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+/* WiFi SDIO */ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ vmmc-supply = <®_vmmc>; -+ bus-width = <4>; -+ // cd-post; -+ // no-1-8-v; -+ wifi-host; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ // enable-sdio-wakeup; -+ non-removable; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+/* eMMC */ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic@4b { -+ compatible = "rohm,bd71847"; -+ reg = <0x4b>; -+ pinctrl-0 = <&pinctrl_pmic>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ rohm,reset-snvs-powered; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ // BUCK5 in datasheet -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck4_reg: BUCK4 { -+ // BUCK6 in datasheet -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: BUCK5 { -+ // BUCK7 in datasheet -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ // BUCK8 in datasheet -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <1900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "LDO6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ codec: wm8904@1a { -+ compatible = "wlf,wm8904"; -+ reg = <0x1a>; -+ clocks = <&clk IMX8MM_CLK_SAI3>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ }; -+ -+ rtc: rtc@32 { -+ compatible = "epson,rx8025"; -+ reg = <0x32>; -+ }; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MM_CLK_CLKO1>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ gate-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; -+ pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx8mm-evk { -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00000116 -+ >; -+ }; -+ -+ pinctrl_ecspi2: ecspi2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x16 -+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16 -+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16 -+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x1816 -+ >; -+ }; -+ -+ pinctrl_csi_pwn: csi_pwn_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 -+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 -+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 -+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 -+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 -+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 -+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 -+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 -+ >; -+ }; -+ -+ pinctrl_gpio_led: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x00000116 -+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x00000116 -+ >; -+ }; -+ -+ pinctrl_gpio_key: keygrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x116 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ -+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ // MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ // MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -+ >; -+ }; -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ /*MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6*/ -+ MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 -+ >; -+ }; -+ -+ pinctrl_pdm: pdmgrp { -+ fsl,pins = < -+ /*MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6*/ -+ MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 -+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 -+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 -+ MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 -+ /* MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 -+ MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 */ -+ >; -+ }; -+ -+ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 -+ >; -+ }; -+ -+ pinctrl_usdhc1_gpio: usdhc1grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+ -+ }; -+}; -+ -+&lcdif { -+ status = "okay"; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ port { -+ mipi1_sensor_ep: endpoint@1 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ -+ csi1_mipi_ep: endpoint@2 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ reset-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; -+ powergpio-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ }; -+ -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_h1 { -+ status = "okay"; -+}; -+ -+&gpu { -+ status = "okay"; -+}; -+ -+&snvs_rtc{ -+ status= "disabled"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&pwm3 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-atk-10-1.dts b/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-atk-10-1.dts -new file mode 100755 -index 000000000..f0101b048 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-atk-10-1.dts -@@ -0,0 +1,20 @@ -+/* -+ * Copyright 2020 MYiR -+ */ -+ -+#include "myb-imx8mm-base.dts" -+#include "panel-atk-10-1.dtsi" -+ -+&lcdif{ -+ max-res = <1280>, <800>; -+ status = "okay"; -+ // status = "disabled"; -+}; -+ -+&i2c2 { -+ tc358775:tc358775@f{ -+ compatible = "toshiba,tc358775"; -+ reg = <0x0f>; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-hontron-7.dts b/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-hontron-7.dts -new file mode 100755 -index 000000000..904fc8941 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-hontron-7.dts -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2019 MYiR Devices -+ */ -+ -+#include "myb-imx8mm-base.dts" -+#include "panel-hontron-7.dtsi" -+ -+/{ -+ display-subsystem { -+ status = "okay"; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1024>, <600>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ imx8mm-evk { -+ edt_ft5x06_pins:pinctrl_ft5xgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 -+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 -+ >; -+ }; -+ }; -+}; -+ -+/* touch */ -+&i2c3 { -+ clock_frequency = <100000>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ ft5x06: ft5x06@38 { -+ compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; -+ reg = <0x38>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&edt_ft5x06_pins>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; -+ touchscreen-size-x=<1024>; -+ touchscreen-size-y=<600>; -+ }; -+ -+}; -+ -+&i2c2 { -+ tc358775:tc358775@f{ -+ compatible = "toshiba,tc358775"; -+ reg = <0x0f>; -+ status = "okay"; -+ }; -+}; -+ -diff --git a/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-me190etn01.dts b/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-me190etn01.dts -new file mode 100755 -index 000000000..30aba5338 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myb-imx8mm-lcd-me190etn01.dts -@@ -0,0 +1,25 @@ -+/* -+ * Copyright 2020 MYiR Devices -+ */ -+ -+#include "myb-imx8mm-base.dts" -+#include "panel-me190etn01.dtsi" -+ -+/{ -+ display-subsystem { -+ status = "okay"; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1280>, <1024>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ tc358775:tc358775@f{ -+ compatible = "toshiba,tc358775"; -+ reg = <0x0f>; -+ status = "okay"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/myir/myb-imx8mm-rpmsg-m4.dts b/arch/arm64/boot/dts/myir/myb-imx8mm-rpmsg-m4.dts -new file mode 100755 -index 000000000..e66dba140 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myb-imx8mm-rpmsg-m4.dts -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 MYiR -+ */ -+ -+/dts-v1/; -+ -+#include "myb-imx8mm-base.dts" -+ -+/ { -+ model = "MYD rpmsg-M4 i.MX8MM board"; -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ rpmsg_dma_reserved:rpmsg_dma@0xb8400000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0xb8400000 0 0x100000>; -+ }; -+ }; -+ -+ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+/* -+ * ATTENTION: M4 may use IPs like below -+ * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 -+ */ -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&rpmsg{ -+ /* -+ * 64K for one rpmsg instance: -+ * --0xb8000000~0xb800ffff: pingpong -+ */ -+ vdev-nums = <1>; -+ reg = <0x0 0xb8000000 0x0 0x10000>; -+ memory-region = <&rpmsg_dma_reserved>; -+ status = "okay"; -+}; -+ -+&sdma1{ -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myb-imx8mm.dtsi b/arch/arm64/boot/dts/myir/myb-imx8mm.dtsi -new file mode 100755 -index 000000000..8d814afb8 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myb-imx8mm.dtsi -@@ -0,0 +1,1489 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 MYiR -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "imx8mm-pinfunc.h" -+ -+/ { -+ compatible = "fsl,imx8mm"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fec1; -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ i2c3 = &i2c4; -+ serial0 = &uart1; -+ serial1 = &uart2; -+ serial2 = &uart3; -+ serial3 = &uart4; -+ spi0 = &ecspi1; -+ spi1 = &ecspi2; -+ spi2 = &ecspi3; -+ mmc0 = &usdhc1; -+ mmc1 = &usdhc2; -+ mmc2 = &usdhc3; -+ gpio0 = &gpio1; -+ gpio1 = &gpio2; -+ gpio2 = &gpio3; -+ gpio3 = &gpio4; -+ gpio4 = &gpio5; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ idle-states { -+ entry-method = "psci"; -+ -+ cpu_pd_wait: cpu-pd-wait { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0010033>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ }; -+ }; -+ -+ A53_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ nvmem-cells = <&cpu_speed_grade>; -+ nvmem-cell-names = "speed_grade"; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MM_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ #cooling-cells = <2>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a53_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <850000>; -+ opp-supported-hw = <0xe>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <900000>; -+ opp-supported-hw = <0xc>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1000000>; -+ opp-supported-hw = <0x8>, <0x3>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x0 0x40000000 0 0x80000000>; -+ }; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x28000000>; -+ alloc-ranges = <0 0x40000000 0 0x60000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ -+ osc_32k: clock-osc-32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "osc_32k"; -+ }; -+ -+ osc_24m: clock-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ clk_ext1: clock-ext1 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext1"; -+ }; -+ -+ clk_ext2: clock-ext2 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext2"; -+ }; -+ -+ clk_ext3: clock-ext3 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext3"; -+ }; -+ -+ clk_ext4: clock-ext4 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <133000000>; -+ clock-output-names = "clk_ext4"; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; -+ }; -+ -+ power-domains { -+ compatible = "simple-bus"; -+ /* HSIO SS */ -+ hsiomix_pd: hsiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <0>; -+ domain-name = "hsiomix"; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ }; -+ -+ pcie_pd: pcie-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <1>; -+ domain-name = "pcie"; -+ parent-domains = <&hsiomix_pd>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; -+ }; -+ -+ usb_otg1_pd: usbotg1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <2>; -+ domain-name = "usb_otg1"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ usb_otg2_pd: usbotg2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <3>; -+ domain-name = "usb_otg2"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ /* GPU SS */ -+ gpumix_pd: gpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <4>; -+ domain-name = "gpumix"; -+ clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_CLK_GPU2D_ROOT>, -+ <&clk IMX8MM_CLK_GPU3D_ROOT>; -+ }; -+ -+ /* VPU SS */ -+ vpumix_pd: vpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <5>; -+ domain-name = "vpumix"; -+ clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ }; -+ -+ vpu_g1_pd: vpug1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <6>; -+ domain-name = "vpu_g1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; -+ }; -+ -+ vpu_g2_pd: vpug2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <7>; -+ domain-name = "vpu_g2"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; -+ }; -+ -+ vpu_h1_pd: vpuh1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <8>; -+ domain-name = "vpu_h1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; -+ }; -+ -+ /* DISP SS */ -+ dispmix_pd: dispmix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <9>; -+ domain-name = "dispmix"; -+ clocks = <&clk IMX8MM_CLK_DISP_ROOT>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ }; -+ -+ mipi_pd: mipi-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <10>; -+ domain-name = "mipi"; -+ parent-domains = <&dispmix_pd>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ clock-frequency = <8000000>; -+ arm,no-tick-in-suspend; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tmu>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit0: trip1 { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ usbphynop1: usbphynop1 { -+ compatible = "usb-nop-xceiv"; -+ clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; -+ clock-names = "main_clk"; -+ }; -+ -+ usbphynop2: usbphynop2 { -+ compatible = "usb-nop-xceiv"; -+ clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; -+ clock-names = "main_clk"; -+ }; -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT>, -+ <&clk IMX8MM_CLK_DRAM_APB>, <&clk IMX8MM_CLK_DRAM_APB>, -+ <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, -+ <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, -+ <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, -+ <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, -+ <&clk IMX8MM_DRAM_PLL>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", -+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", -+ "sys_pll1_800m", "dram_pll_div"; -+ interrupts = , , -+ , ; -+ interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; -+ -+ aips1: bus@30000000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30000000 0x30000000 0x400000>; -+ -+ sai1: sai@30010000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30010000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>,<&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus","mclk0","mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xff 0xff>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@30020000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30020000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>, -+ <&clk IMX8MM_CLK_SAI2_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@30030000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30030000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>, -+ <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI3_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus","mclk0","mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@30050000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30050000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xf 0xf>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@30060000 { -+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; -+ reg = <0x30060000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SAI6_IPG>, -+ <&clk IMX8MM_CLK_SAI6_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ micfil: micfil@30080000 { -+ compatible = "fsl,imx8mm-micfil"; -+ reg = <0x30080000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&clk IMX8MM_CLK_PDM_IPG>, -+ <&clk IMX8MM_CLK_PDM_ROOT>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>, -+ <&clk IMX8MM_CLK_EXT3>; -+ clock-names = "ipg_clk", "ipg_clk_app", -+ "pll8k", "pll11k", "clkext3"; -+ dmas = <&sdma2 24 25 0x80000000>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ spdif1: spdif@30090000 { -+ compatible = "fsl,imx8mm-spdif"; -+ reg = <0x30090000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ -+ <&clk IMX8MM_CLK_24M>, /* rxtx0 */ -+ <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MM_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ gpio1: gpio@30200000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30200000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 10 30>; -+ }; -+ -+ gpio2: gpio@30210000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30210000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 40 21>; -+ }; -+ -+ gpio3: gpio@30220000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30220000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 61 26>; -+ }; -+ -+ gpio4: gpio@30230000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30230000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 87 32>; -+ }; -+ -+ gpio5: gpio@30240000 { -+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; -+ reg = <0x30240000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 119 30>; -+ }; -+ -+ tmu: tmu@30260000 { -+ compatible = "fsl,imx8mm-tmu"; -+ reg = <0x30260000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_TMU_ROOT>; -+ #thermal-sensor-cells = <0>; -+ }; -+ -+ wdog1: watchdog@30280000 { -+ compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; -+ reg = <0x30280000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ wdog2: watchdog@30290000 { -+ compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; -+ reg = <0x30290000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; -+ status = "disabled"; -+ }; -+ -+ wdog3: watchdog@302a0000 { -+ compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; -+ reg = <0x302a0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; -+ status = "disabled"; -+ }; -+ -+ sdma2: dma-controller@302c0000 { -+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; -+ reg = <0x302c0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, -+ <&clk IMX8MM_CLK_SDMA2_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "sdma-imx7d.bin"; -+ }; -+ -+ sdma3: dma-controller@302b0000 { -+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; -+ reg = <0x302b0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, -+ <&clk IMX8MM_CLK_SDMA3_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "sdma-imx7d.bin"; -+ }; -+ -+ iomuxc: pinctrl@30330000 { -+ compatible = "fsl,imx8mm-iomuxc"; -+ reg = <0x30330000 0x10000>; -+ }; -+ -+ gpr: iomuxc-gpr@30340000 { -+ compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; -+ reg = <0x30340000 0x10000>; -+ }; -+ -+ ocotp: ocotp-ctrl@30350000 { -+ compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; -+ reg = <0x30350000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; -+ /* For nvmem subnodes */ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_speed_grade: speed-grade@10 { -+ reg = <0x10 4>; -+ }; -+ -+ fec_mac_address: mac-address@640 { -+ reg = <0x90 6>; -+ }; -+ }; -+ -+ anatop: anatop@30360000 { -+ compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; -+ reg = <0x30360000 0x10000>; -+ }; -+ -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ }; -+ -+ snvs: snvs@30370000 { -+ compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; -+ reg = <0x30370000 0x10000>; -+ -+ snvs_rtc: snvs-rtc-lp { -+ compatible = "fsl,sec-v4.0-mon-rtc-lp"; -+ regmap = <&snvs>; -+ offset = <0x34>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; -+ clock-names = "snvs-rtc"; -+ }; -+ -+ snvs_pwrkey: snvs-powerkey { -+ compatible = "fsl,sec-v4.0-pwrkey"; -+ regmap = <&snvs>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; -+ clock-names = "snvs"; -+ linux,keycode = ; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ }; -+ -+ clk: clock-controller@30380000 { -+ compatible = "fsl,imx8mm-ccm"; -+ reg = <0x30380000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, -+ <&clk_ext3>, <&clk_ext4>; -+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", -+ "clk_ext3", "clk_ext4"; -+ assigned-clocks = <&clk IMX8MM_CLK_NOC>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, -+ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, -+ <&clk IMX8MM_SYS_PLL3>, -+ <&clk IMX8MM_VIDEO_PLL1>, -+ <&clk IMX8MM_AUDIO_PLL1>, -+ <&clk IMX8MM_AUDIO_PLL2>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, -+ <400000000>, -+ <400000000>, -+ <750000000>, -+ <594000000>, -+ <393216000>, -+ <361267200>; -+ }; -+ -+ src: reset-controller@30390000 { -+ compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; -+ reg = <0x30390000 0x10000>; -+ interrupts = ; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ aips2: bus@30400000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30400000 0x30400000 0x400000>; -+ -+ pwm1: pwm@30660000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30660000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, -+ <&clk IMX8MM_CLK_PWM1_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@30670000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30670000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, -+ <&clk IMX8MM_CLK_PWM2_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@30680000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30680000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, -+ <&clk IMX8MM_CLK_PWM3_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@30690000 { -+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; -+ reg = <0x30690000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, -+ <&clk IMX8MM_CLK_PWM4_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ system_counter: timer@306a0000 { -+ compatible = "nxp,sysctr-timer"; -+ reg = <0x306a0000 0x20000>; -+ interrupts = ; -+ clocks = <&osc_24m>; -+ clock-names = "per"; -+ }; -+ }; -+ -+ aips3: bus@30800000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x8000000 0x8000000 0x10000000>; -+ -+ flexspi: spi@30bb0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mm-fspi"; -+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, -+ <&clk IMX8MM_CLK_QSPI_ROOT>; -+ clock-names = "fspi", "fspi_en"; -+ status = "disabled"; -+ }; -+ -+ ecspi1: spi@30820000 { -+ compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30820000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, -+ <&clk IMX8MM_CLK_ECSPI1_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi2: spi@30830000 { -+ compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30830000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, -+ <&clk IMX8MM_CLK_ECSPI2_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi3: spi@30840000 { -+ compatible = "fsl,imx8mm-ecspi", "fsl,imx6ul-ecspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30840000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, -+ <&clk IMX8MM_CLK_ECSPI3_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@30860000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30860000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART1_ROOT>, -+ <&clk IMX8MM_CLK_UART1_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@30880000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30880000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART3_ROOT>, -+ <&clk IMX8MM_CLK_UART3_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@30890000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30890000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART2_ROOT>, -+ <&clk IMX8MM_CLK_UART2_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ crypto: crypto@30900000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ reg = <0x30900000 0x40000>; -+ ranges = <0 0x30900000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_AHB>, -+ <&clk IMX8MM_CLK_IPG_ROOT>; -+ clock-names = "aclk", "ipg"; -+ -+ sec_jr0: jr@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupts = ; -+ status = "disabled"; -+ -+ }; -+ -+ sec_jr1: jr@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ sec_jr2: jr@3000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x3000 0x1000>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ }; -+ -+ i2c1: i2c@30a20000 { -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30a20000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@30a30000 { -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30a30000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@30a40000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@30a50000 { -+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x30a50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_UART4_ROOT>, -+ <&clk IMX8MM_CLK_UART4_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ mu: mu@30aa0000 { -+ compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; -+ reg = <0x30aa0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_MU_ROOT>; -+ clock-names = "mu"; -+ #mbox-cells = <2>; -+ }; -+ -+ usdhc1: mmc@30b40000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MM_CLK_USDHC1_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc2: mmc@30b50000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MM_CLK_USDHC2_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MM_CLK_USDHC3_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ sdma1: dma-controller@30bd0000 { -+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; -+ reg = <0x30bd0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, -+ <&clk IMX8MM_CLK_AHB>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "sdma-imx7d.bin"; -+ }; -+ -+ fec1: ethernet@30be0000 { -+ compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; -+ reg = <0x30be0000 0x10000>; -+ interrupts = , -+ , -+ ; -+ clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, -+ <&clk IMX8MM_CLK_ENET1_ROOT>, -+ <&clk IMX8MM_CLK_ENET_TIMER>, -+ <&clk IMX8MM_CLK_ENET_REF>, -+ <&clk IMX8MM_CLK_ENET_PHY_REF>; -+ clock-names = "ipg", "ahb", "ptp", -+ "enet_clk_ref", "enet_out"; -+ assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, -+ <&clk IMX8MM_CLK_ENET_TIMER>, -+ <&clk IMX8MM_CLK_ENET_REF>, -+ <&clk IMX8MM_CLK_ENET_TIMER>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, -+ <&clk IMX8MM_SYS_PLL2_100M>, -+ <&clk IMX8MM_SYS_PLL2_125M>; -+ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; -+ fsl,num-tx-queues = <3>; -+ fsl,num-rx-queues = <3>; -+ nvmem-cells = <&fec_mac_address>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ stop-mode = <&gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; -+ status = "disabled"; -+ }; -+ -+ }; -+ -+ aips4: bus@32c00000 { -+ compatible = "fsl,aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x32c00000 0x32c00000 0x400000>; -+ -+ lcdif: lcdif@32e00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-lcdif"; -+ reg = <0x32e00000 0x10000>; -+ clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MM_CLK_DISP_AXI>, -+ <&clk IMX8MM_CLK_DISP_APB>; -+ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, -+ <&clk IMX8MM_SYS_PLL2_1000M>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rate = <594000000>, <500000000>, <200000000>; -+ interrupts = ; -+ lcdif-gpr = <&dispmix_gpr>; -+ resets = <&lcdif_resets>; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ -+ lcdif_disp0: port@0 { -+ reg = <0>; -+ -+ lcdif_to_dsim: endpoint { -+ remote-endpoint = <&dsim_from_lcdif>; -+ }; -+ }; -+ }; -+ -+ mipi_dsi: mipi_dsi@32e10000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mm-mipi-dsim"; -+ reg = <0x32e10000 0x400>; -+ clocks = <&clk IMX8MM_CLK_DSI_CORE>, -+ <&clk IMX8MM_CLK_DSI_PHY_REF>; -+ clock-names = "cfg", "pll-ref"; -+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, -+ <&clk IMX8MM_CLK_DSI_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, -+ <&clk IMX8MM_VIDEO_PLL1_OUT>; -+ assigned-clock-rates = <266000000>, <594000000>; -+ interrupts = ; -+ dsi-gpr = <&dispmix_gpr>; -+ resets = <&mipi_dsi_resets>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ dsim_from_lcdif: endpoint { -+ remote-endpoint = <&lcdif_to_dsim>; -+ }; -+ }; -+ }; -+ -+ csi1_bridge: csi1_bridge@32e20000 { -+ compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x32e20000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_CSI1_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; -+ power-domains = <&dispmix_pd>; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: mipi_csi@32e30000 { -+ compatible = "fsl,imx8mm-mipi-csi"; -+ reg = <0x32e30000 0x1000>; -+ interrupts = ; -+ clock-frequency = <333000000>; -+ clocks = <&clk IMX8MM_CLK_CSI1_CORE>, -+ <&clk IMX8MM_CLK_CSI1_PHY_REF>, -+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; -+ bus-width = <4>; -+ power-domains = <&mipi_pd>; -+ status = "disabled"; -+ }; -+ -+ dispmix_gpr: display-gpr@32e28000 { -+ compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; -+ reg = <0x32e28000 0x100>; -+ }; -+ -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif_disp0>; -+ }; -+ -+ usbotg1: usb@32e40000 { -+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; -+ reg = <0x32e40000 0x200>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ clock-names = "usb1_ctrl_root_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; -+ fsl,usbphy = <&usbphynop1>; -+ fsl,usbmisc = <&usbmisc1 0>; -+ power-domains = <&usb_otg1_pd>; -+ status = "disabled"; -+ }; -+ -+ usbmisc1: usbmisc@32e40200 { -+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; -+ #index-cells = <1>; -+ reg = <0x32e40200 0x200>; -+ }; -+ -+ usbotg2: usb@32e50000 { -+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; -+ reg = <0x32e50000 0x200>; -+ interrupts = ; -+ clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; -+ clock-names = "usb1_ctrl_root_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; -+ fsl,usbphy = <&usbphynop2>; -+ fsl,usbmisc = <&usbmisc2 0>; -+ power-domains = <&usb_otg2_pd>; -+ status = "disabled"; -+ }; -+ -+ usbmisc2: usbmisc@32e50200 { -+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; -+ #index-cells = <1>; -+ reg = <0x32e50200 0x200>; -+ }; -+ -+ pcie_phy: pcie-phy@32f00000 { -+ compatible = "fsl,imx7d-pcie-phy"; -+ reg = <0x32f00000 0x10000>; -+ }; -+ }; -+ -+ dma_apbh: dma-controller@33000000 { -+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; -+ reg = <0x33000000 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ }; -+ -+ gpmi: nand-controller@33002000{ -+ compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&clk IMX8MM_CLK_NAND_ROOT>, -+ <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ clock-names = "gpmi_io", "gpmi_bch_apb"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ status = "disabled"; -+ }; -+ -+ pcie0: pcie@33800000 { -+ compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; -+ reg = <0x33800000 0x400000>, -+ <0x1ff00000 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pcie_pd>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "clkreq", "turnoff"; -+ fsl,imx7d-pcie-phy = <&pcie_phy>; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x38800000 0x10000>, /* GIC Dist */ -+ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ }; -+ -+ ddr-pmu@3d800000 { -+ compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; -+ reg = <0x3d800000 0x400000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ dispmix-reset { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { -+ compatible = "fsl,imx8mm-dispmix-sft-rstn"; -+ reg = <0x0 0x32e28000 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_clk_en: dispmix-clk-en@32e28004 { -+ compatible = "fsl,imx8mm-dispmix-clk-en"; -+ reg = <0x0 0x32e28004 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { -+ compatible = "fsl,imx8mm-dispmix-mipi-rst"; -+ reg = <0x0 0x32e28008 0x0 0x4>; -+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; -+ clock-names = "disp_apb_root_clk"; -+ active_low; -+ power-domains = <&dispmix_pd>; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ lcdif_resets: lcdif-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ lcdif-clk-enable { -+ compatible = "lcdif,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, -+ <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; -+ }; -+ }; -+ -+ mipi_dsi_resets: mipi-dsi-resets { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #reset-cells = <0>; -+ -+ dsi-soft-resetn { -+ compatible = "dsi,soft-resetn"; -+ resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; -+ }; -+ -+ dsi-clk-enable { -+ compatible = "dsi,clk-enable"; -+ resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, -+ <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; -+ }; -+ -+ dsi-mipi-reset { -+ compatible = "dsi,mipi-reset"; -+ resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; -+ }; -+ }; -+ -+ rpmsg: rpmsg{ -+ compatible = "fsl,imx8mq-rpmsg"; -+ /* up to now, the following channels are used in imx rpmsg -+ * - tx1/rx1: messages channel. -+ * - general interrupt1: remote proc finish re-init rpmsg stack -+ * when A core is partition reset. -+ */ -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ status = "disabled"; -+ }; -+ -+ vpu_h1: vpu_h1@38320000 { -+ compatible = "nxp,imx8mm-hantro-h1"; -+ reg = <0x0 0x38320000 0x0 0x10000>; -+ reg-names = "regs_hantro_h1"; -+ interrupts = ; -+ interrupt-names = "irq_hantro_h1"; -+ clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_h1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g1: vpu_g1@38300000 { -+ compatible = "nxp,imx8mm-hantro"; -+ reg = <0x0 0x38300000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_g1_pd>; -+ status = "disabled"; -+ }; -+ -+ vpu_g2: vpu_g2@38310000 { -+ compatible = "nxp,imx8mm-hantro"; -+ reg = <0x0 0x38310000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <600000000>, <800000000>; -+ power-domains = <&vpu_g2_pd>; -+ status = "disabled"; -+ }; -+ -+ gpu: gpu@38000000 { -+ compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; -+ reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, -+ <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "phys_baseaddr", "contiguous_mem"; -+ interrupts = , -+ ; -+ interrupt-names = "irq_3d", "irq_2d"; -+ clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, -+ <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_CLK_GPU2D_ROOT>, -+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>, -+ <&clk IMX8MM_CLK_GPU_AHB>; -+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", -+ "gpu3d_axi_clk", "gpu3d_ahb_clk", -+ "gpu2d_clk", "gpu2d_axi_clk", -+ "gpu2d_ahb_clk"; -+ assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, -+ <&clk IMX8MM_CLK_GPU2D_SRC>, -+ <&clk IMX8MM_CLK_GPU_AXI>, -+ <&clk IMX8MM_CLK_GPU_AHB>, -+ <&clk IMX8MM_GPU_PLL_OUT>; -+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, -+ <&clk IMX8MM_GPU_PLL_OUT>, -+ <&clk IMX8MM_SYS_PLL1_800M>, -+ <&clk IMX8MM_SYS_PLL1_800M>; -+ assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; -+ -+ power-domains = <&gpumix_pd>; -+ -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp-base.dts b/arch/arm64/boot/dts/myir/myd-jx8mp-base.dts -new file mode 100755 -index 000000000..4cc3229df ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp-base.dts -@@ -0,0 +1,1215 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+ -+/dts-v1/; -+ -+#include -+#include "myd-jx8mp.dtsi" -+ -+/ { -+ model = "MYIR i.MX8MP BASE"; -+ compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ -+ user { -+ label = "User"; -+ gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; -+ gpio-key,wakeup; -+ linux,code = ; -+ }; -+ -+ }; -+ -+ reg_can1_stby: regulator-can1-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can1-stby"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1_reg>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_can2_stby: regulator-can2-stby { -+ compatible = "regulator-fixed"; -+ regulator-name = "can2-stby"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2_reg>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ -+ -+ reg_usdhc2_vmmc: regulator-usdhc2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "VSD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ startup-delay-us = <100>; -+ off-on-delay-us = <12000>; -+ }; -+ reg_audio_pwr: regulator-audio-pwr { -+ compatible = "regulator-fixed"; -+ regulator-name = "audio-pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ /* -+ reg_usb1_typec_en_vmmc: regulator-usb_typec_en { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb1_typec_en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ startup-delay-us = <100>; -+ off-on-delay-us = <12000>; -+ };*/ -+ -+ reg_m2_en_vmmc: regulator-m2_en { -+ compatible = "regulator-fixed"; -+ regulator-name = "m2_en_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ startup-delay-us = <100>; -+ off-on-delay-us = <12000>; -+ }; -+ -+ reg_m2_keyb_en_vmmc: regulator-m2_keyb_en { -+ compatible = "regulator-fixed"; -+ regulator-name = "m2_keyb_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ startup-delay-us = <100>; -+ off-on-delay-us = <12000>; -+ }; -+ -+ csi1_io: csi1-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "csi1_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ csi2_io: csi2-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "csi2_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ -+ -+ -+ sound-hdmi { -+ compatible = "fsl,imx-audio-cdnhdmi"; -+ model = "audio-hdmi"; -+ audio-cpu = <&aud2htx>; -+ hdmi-out; -+ constraint-rate = <44100>, -+ <88200>, -+ <176400>, -+ <32000>, -+ <48000>, -+ <96000>, -+ <192000>; -+ status = "disabled"; -+ }; -+ -+ sound-wm8960 { -+ compatible = "fsl,imx7d-evk-wm8960", "fsl,imx-audio-wm8960"; -+ model = "wm8960-audio"; -+ cpu-dai = <&sai3>; -+ audio-codec = <&codec>; -+ asrc-controller = <&easrc>; -+ codec-master; -+ /* JD2: hp detect high for headphone*/ -+ hp-det = <3 0>; -+ hp-det-gpios = <&gpio4 28 0>; -+ mic-det-gpios = <&gpio4 28 0>; -+ audio-routing = -+ "Headphone Jack", "HP_L", -+ "Headphone Jack", "HP_R", -+ "Ext Spk", "SPK_LP", -+ "Ext Spk", "SPK_LN", -+ "Ext Spk", "SPK_RP", -+ "Ext Spk", "SPK_RN", -+ "LINPUT1", "Mic Jack", -+ "LINPUT3", "Mic Jack", -+ "Mic Jack", "MICB", -+ "CPU-Playback", "ASRC-Playback", -+ "Playback", "CPU-Playback", -+ "ASRC-Capture", "CPU-Capture", -+ "CPU-Capture", "Capture"; -+ }; -+ -+ sound-micfil { -+ compatible = "fsl,imx-audio-micfil"; -+ model = "imx-audio-micfil"; -+ cpu-dai = <&micfil>; -+ }; -+ -+ sound-xcvr { -+ compatible = "fsl,imx-audio-xcvr"; -+ model = "imx-audio-xcvr"; -+ cpu-dai = <&xcvr>; -+ }; -+ -+ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "disabled"; -+}; -+ -+&pwm4 { -+ -+ status = "disabled"; -+}; -+ -+&ecspi2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ fsl,spi-num-chipselects = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ spidev1: spi@0 { -+ reg = <0>; -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&eqos { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_eqos>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ reset-assert-us = <10000>; -+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; -+ reset-deassert-us = <30000>; -+ eee-broken-1000t; -+ }; -+ }; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy1>; -+ fsl,magic-packet; -+ status = "okay"; -+ phy-reset-duration = <20>; -+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; -+ phy-reset-post-delay=<20>; -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ eee-broken-1000t; -+ }; -+ }; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic: pca9450@25 { -+ reg = <0x25>; -+ compatible = "nxp,pca9450"; -+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ -+ pinctrl-0 = <&pinctrl_pmic>; -+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; -+ -+ regulators { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pca9450,pmic-buck2-uses-i2c-dvs; -+ /* Run/Standby voltage */ -+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; -+ -+ buck1_reg: regulator@0 { -+ reg = <0>; -+ regulator-compatible = "buck1"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <3125>; -+ }; -+ -+ buck2_reg: regulator@1 { -+ reg = <1>; -+ regulator-compatible = "buck2"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <2187500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <3125>; -+ }; -+ -+ buck4_reg: regulator@3 { -+ reg = <3>; -+ regulator-compatible = "buck4"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: regulator@4 { -+ reg = <4>; -+ regulator-compatible = "buck5"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: regulator@5 { -+ reg = <5>; -+ regulator-compatible = "buck6"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: regulator@6 { -+ reg = <6>; -+ regulator-compatible = "ldo1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: regulator@7 { -+ reg = <7>; -+ regulator-compatible = "ldo2"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: regulator@8 { -+ reg = <8>; -+ regulator-compatible = "ldo3"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: regulator@9 { -+ reg = <9>; -+ regulator-compatible = "ldo4"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo5_reg: regulator@10 { -+ reg = <10>; -+ regulator-compatible = "ldo5"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ -+ -+ -+ -+ ov5640_0: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>,<&pinctrl_io0_pwn>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "xclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ -+ port { -+ ov5640_mipi_0_ep: endpoint { -+ remote-endpoint = <&mipi_csi0_ep>; -+ data-lanes = <1 2>; -+ clock-lanes = <0>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ rtc: rtc@32 { -+ compatible = "epson,rx8025"; -+ reg = <0x32>; -+ }; -+ -+ -+ ov5640_1: ov5640_mipi@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>,<&pinctrl_io1_pwn>; -+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ clock-names = "xclk"; -+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ powerdown-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ mipi_csi; -+ status = "okay"; -+ -+ port { -+ ov5640_mipi_1_ep: endpoint { -+ remote-endpoint = <&mipi_csi1_ep>; -+ data-lanes = <1 2>; -+ clock-lanes = <0>; -+ }; -+ }; -+ }; -+ -+ codec: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ SPKVDD1-supply = <®_audio_pwr>; -+ }; -+ -+ -+ typec: stusb1600@28 { -+ compatible = "st,stusb1600"; -+ reg = <0x28>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&stusb1600_pins_a>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>; -+ status = "okay"; -+ -+ -+ -+ typec1_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ power-opmode = "1.5A"; -+ data-role = "dual"; -+ port { -+ typec_dr_sw: endpoint { -+ remote-endpoint = <&usb3_drd_sw>; -+ }; -+ }; -+ -+ }; -+ }; -+ -+}; -+&i2c4 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c4>; -+ status = "okay"; -+ -+ pcf8575: gpio@20 { -+ compatible = "nxp,pcf8575"; -+ reg = <0x20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcf8575_pins_a>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ xceiver-supply = <®_can1_stby>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan2>; -+ xceiver-supply = <®_can2_stby>; -+ status = "okay"; -+}; -+ -+&lcdif1 { -+ status = "disabled"; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+ -+ -+}; -+ -+&easrc { -+ fsl,asrc-rate = <48000>; -+ status = "okay"; -+}; -+ -+&micfil { -+ status = "disabled"; -+}; -+ -+&pcie{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie>; -+ disable-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; -+ ext_osc = <0>; -+ clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, -+ <&clk IMX8MP_CLK_PCIE_AUX>, -+ <&clk IMX8MP_CLK_PCIE_PHY>, -+ <&clk IMX8MP_CLK_PCIE_ROOT>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, -+ <&clk IMX8MP_CLK_PCIE_AUX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_SYS_PLL2_50M>; -+ status = "okay"; -+ -+}; -+ -+&pcie_phy{ -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ fsl,sai-mclk-direction-output; -+ status = "okay"; -+}; -+ -+&xcvr { -+ /** -+ * Bit 0: TX enabled -+ * Bit 1: RX enabled -+ * Bits 3..2: 0=SPDIF, 1=ARC, 2=EARC, 3=RESERVED -+ */ -+ fsl,xcvr-mode = <0xa>; /* EARC, RX */ -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&sdma2 { -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MP_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; -+ -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb3_0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ usb3_drd_sw: endpoint { -+ remote-endpoint = <&typec_dr_sw>; -+ }; -+ }; -+}; -+ -+&usb3_phy1 { -+ status = "okay"; -+}; -+ -+&usb3_1 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ wifi-host; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x400001c3 -+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x400001c3 -+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x40000019 -+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x40000019 -+ -+ MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x19 /*WIFI_EN */ -+ MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 /*BT_EN*/ -+ /*MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x19*/ /*WIFI_WKE*/ -+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19 -+ MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /*5G_RST*/ -+ MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x59 -+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /*VFAN_EN*/ -+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /*USB1_TYPEC_SEL*/ -+ >; -+ }; -+ -+ pinctrl_pwm1: pwm1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 -+ >; -+ }; -+ pinctrl_gpio_key: gpiokey { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x116 -+ >; -+ }; -+ -+ -+ -+ pinctrl_ecspi2: ecspi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 -+ >; -+ }; -+ -+ pinctrl_ecspi2_cs: ecspi2cs { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 -+ >; -+ }; -+ -+ pinctrl_eqos: eqosgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 -+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 -+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 -+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 -+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 -+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 -+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 -+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 -+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f -+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f -+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f -+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f -+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f -+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f -+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 -+ >; -+ }; -+ -+ pinctrl_fec: fecgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 -+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 -+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 -+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 -+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 -+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 -+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 -+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 -+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f -+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f -+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f -+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f -+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f -+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f -+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 -+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 -+ >; -+ }; -+ -+ pinctrl_flexcan2: flexcan2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 -+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 -+ >; -+ }; -+ -+ pinctrl_flexcan1_reg: flexcan1reggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ -+ >; -+ }; -+ -+ pinctrl_flexcan2_reg: flexcan2reggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 -+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 -+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 -+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 -+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 -+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 -+ >; -+ }; -+ -+ -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 -+ >; -+ }; -+ pinctrl_i2c4: i2c4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 -+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 -+ >; -+ }; -+ -+ -+ -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 -+ >; -+ }; -+ -+ -+ -+ -+ -+ pinctrl_pcie: pciegrp{ -+ fsl,pins = < -+ -+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x41 /*PCIe_nWake */ -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x41 /*PCie_nRST */ -+ -+ >; -+ -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 -+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 -+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 /*VAUD_5V */ -+ >; -+ }; -+ -+ -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 -+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 -+ -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 -+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 -+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 -+ -+ >; -+ }; -+ -+ -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grp-gpio { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 -+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 -+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 -+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 -+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 -+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 -+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 -+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 -+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 -+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 -+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 -+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 -+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 -+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 -+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { -+ fsl,pins = < -+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 -+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 -+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 -+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 -+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 -+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 -+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 -+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+ -+ pinctrl_io0_pwn:csi0_io_pwn_grp{ -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 -+ >; -+ }; -+ pinctrl_io1_pwn:csi1_io_pwn_grp{ -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 -+ >; -+ }; -+ pinctrl_csi0_pwn: csi0_pwn_grp { -+ fsl,pins = < -+ -+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 -+ >; -+ }; -+ -+ pinctrl_csi0_rst: csi0_rst_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 -+ -+ >; -+ }; -+ pinctrl_csi1_pwn: csi1_pwn_grp { -+ fsl,pins = < -+ -+ MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x19 -+ >; -+ }; -+ -+ pinctrl_csi1_rst: csi1_rst_grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x19 -+ -+ >; -+ }; -+ stusb1600_pins_a:studb1600grp{ -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1d6 -+ >; -+ }; -+ pcf8575_pins_a:pcf8575grp{ -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x1d6 -+ >; -+ }; -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_vc8000e { -+ status = "okay"; -+}; -+ -+&gpu_3d { -+ status = "okay"; -+}; -+ -+&gpu_2d { -+ status = "okay"; -+}; -+ -+&ml_vipsi { -+ status = "okay"; -+}; -+ -+&mix_gpu_ml { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ mipi_csi0_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_0_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ mipi_csi1_ep: endpoint { -+ remote-endpoint = <&ov5640_mipi_1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ }; -+}; -+ -+&cameradev { -+ status = "okay"; -+}; -+ -+&isi_0 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+ -+ -+}; -+ -+&isi_1 { -+ status = "okay"; -+ -+ cap_device { -+ status = "okay"; -+ }; -+}; -+ -+&dsp { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp-hdmi.dts b/arch/arm64/boot/dts/myir/myd-jx8mp-hdmi.dts -new file mode 100755 -index 000000000..123e02f5f ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp-hdmi.dts -@@ -0,0 +1,59 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 MYIR -+ */ -+ -+/dts-v1/; -+ -+#include "myd-jx8mp-base.dts" -+ -+/ { -+ sound-hdmi { -+ status = "okay"; -+ }; -+ -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif3_disp>; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+}; -+ -+&lcdif1 { -+ status = "disabled"; -+}; -+ -+&lcdif3 { -+ status = "okay"; -+}; -+ -+&irqsteer_hdmi { -+ status = "okay"; -+}; -+ -+&hdmimix_clk { -+ status = "okay"; -+}; -+ -+&hdmimix_reset { -+ status = "okay"; -+}; -+ -+&hdmi_pavi { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmiphy { -+ status = "okay"; -+}; -+ -+&aud2htx { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp-hontron-7.dts b/arch/arm64/boot/dts/myir/myd-jx8mp-hontron-7.dts -new file mode 100755 -index 000000000..c4f4d3a79 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp-hontron-7.dts -@@ -0,0 +1,127 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 MYIR -+ */ -+ -+#include "myd-jx8mp-base.dts" -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif2_disp>; -+ }; -+ -+ -+ panel: panel-lvds0 { -+ compatible = "panel-lvds"; -+ backlight = <&lvds_backlight>; -+ -+ width-mm = <154>; -+ height-mm = <85>; -+ data-mapping = "vesa-24"; -+ panel-timing { -+ clock-frequency = <38000000>; -+ hactive = <1024>; -+ hfront-porch = <88>; -+ hsync-len = <6>; -+ hback-porch = <176>; -+ -+ vactive = <600>; -+ vfront-porch = <25>; -+ vsync-len = <5>; -+ vback-porch = <20>; -+ -+ -+ }; -+ -+ port { -+ panel_in_lvds0: endpoint { -+ remote-endpoint = <&lvds_out>; -+ }; -+ }; -+ }; -+ -+ lvds_backlight: lvds_backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm2 0 100000>; -+ status = "okay"; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+}; -+ -+&i2c2 { -+ -+ ft5x06: ft5x06@38 { -+ compatible = "edt,edt-ft5406"; -+ reg = <0x38>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&edt_ft5x06_pins>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>; -+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; -+ touchscreen-size-x=<1024>; -+ touchscreen-size-y=<600>; -+ status = "okay"; -+ }; -+}; -+ -+&lcdif2 { -+ status = "okay"; -+}; -+ -+&ldb { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds_out: endpoint { -+ remote-endpoint = <&panel_in_lvds0>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb_phy { -+ status = "okay"; -+}; -+ -+ -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ edt_ft5x06_pins:pinctrl_ft5xgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x19 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 -+ >; -+ }; -+ -+ pinctrl_pwm2: lvds0pwm2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 -+ >; -+ }; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp-lt8912.dts b/arch/arm64/boot/dts/myir/myd-jx8mp-lt8912.dts -new file mode 100755 -index 000000000..128a8733d ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp-lt8912.dts -@@ -0,0 +1,91 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 NXP -+ */ -+ -+#include "myd-jx8mp-base.dts" -+ -+ -+ -+&lcdif1{ -+ status = "okay"; -+}; -+&mipi_dsi { -+ status = "okay"; -+ port@1 { -+ compatible = "lontium,lt8912"; -+ -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ pinctrl-names = "default"; -+ -+ powergpio-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; -+ -+ mipi_dsi_bridge1_out: endpoint { -+ remote-endpoint = <<8912_1_in>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ /* MIPI-DSI to HDMI and LVDS adapter */ -+ hdmi@48 { -+ compatible = "lontium,lt8912"; -+ pinctrl-0 = <&pinctrl_lt9182_hdmi>; -+ pinctrl-names = "default"; -+ -+ ddc-i2c-bus = <&i2c2>; -+ hpd-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ reg = <0x48>; -+ reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; -+ lvds-enabled = <0>; -+ status = "okay"; -+ -+ display-timings { -+ -+ native-mode = <&timing0>; -+ -+ timing0: timing0 { -+ clock-frequency = <148500000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <36>; -+ vsync-len = <5>; -+ vback-porch = <4>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <0>; -+ pixelclk-active = <0>; -+ }; -+ -+ -+ -+ }; -+ -+ port { -+ lt8912_1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_bridge1_out>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc{ -+ -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x19 -+ >; -+ }; -+ -+ pinctrl_lt9182_hdmi: lt8912_int_iogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1d6 -+ MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x19 -+ >; -+ }; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp-m190etn01-19.dts b/arch/arm64/boot/dts/myir/myd-jx8mp-m190etn01-19.dts -new file mode 100755 -index 000000000..487ca3a8b ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp-m190etn01-19.dts -@@ -0,0 +1,109 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2021 MYIR -+ */ -+ -+#include "myd-jx8mp-base.dts" -+ -+/ { -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif2_disp>; -+ }; -+ -+ -+ panel: panel-lvds0 { -+ compatible = "panel-lvds"; -+ backlight = <&lvds_backlight>; -+ -+ width-mm = <154>; -+ height-mm = <85>; -+ data-mapping = "vesa-24"; -+ panel-timing { -+ clock-frequency = <90000000>; -+ hactive = <1280>; -+ hfront-porch = <180>; -+ hsync-len = <28>; -+ hback-porch = <200>; -+ -+ vactive = <1024>; -+ vfront-porch = <5>; -+ vsync-len = <6>; -+ vback-porch = <39>; -+ -+ -+ }; -+ -+ port { -+ panel_in_lvds0: endpoint { -+ remote-endpoint = <&lvds_out>; -+ }; -+ }; -+ }; -+ -+ lvds_backlight: lvds_backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm2 0 100000>; -+ status = "okay"; -+ enable-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+ -+}; -+ -+ -+ -+&lcdif2 { -+ status = "okay"; -+}; -+ -+&ldb { -+ status = "okay"; -+ fsl,dual-channel; -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <24>; -+ status = "okay"; -+ -+ port@1 { -+ reg = <1>; -+ -+ lvds_out: endpoint { -+ remote-endpoint = <&panel_in_lvds0>; -+ }; -+ }; -+ }; -+}; -+ -+&ldb_phy { -+ status = "okay"; -+}; -+ -+ -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ -+ -+ pinctrl_pwm2: lvds0pwm2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 -+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 -+ >; -+ }; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp-rpmsg.dts b/arch/arm64/boot/dts/myir/myd-jx8mp-rpmsg.dts -new file mode 100755 -index 000000000..29431ef5f ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp-rpmsg.dts -@@ -0,0 +1,84 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "myd-jx8mp-base.dts" -+ -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ rpmsg_reserved:rpmsg@0xb8000000 { -+ no-map; -+ reg = <0 0xb8000000 0 0x400000>; -+ }; -+ -+ rpmsg_dma_reserved:rpmsg_dma@0xb8400000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0xb8400000 0 0x100000>; -+ }; -+ }; -+}; -+ -+/* -+ * ATTENTION: M7 may use IPs like below -+ * ECSPI0/ECSPI2, FLEXCAN, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, -+ * PWM4, SDMA1/SDMA2 -+ */ -+&ecspi2 { -+ status = "disabled"; -+}; -+ -+&flexcan1 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&pwm4{ -+ status = "disabled"; -+}; -+ -+&rpmsg{ -+ /* -+ * 64K for one rpmsg instance: -+ * --0xb8000000~0xb800ffff: pingpong -+ */ -+ vdev-nums = <1>; -+ reg = <0x0 0xb8000000 0x0 0x10000>; -+ memory-region = <&rpmsg_dma_reserved>; -+ status = "okay"; -+}; -+ -+&sdma1{ -+ status = "disabled"; -+}; -+ -+&sdma2{ -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&wdog1 { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mp.dtsi b/arch/arm64/boot/dts/myir/myd-jx8mp.dtsi -new file mode 100755 -index 000000000..28fedb210 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mp.dtsi -@@ -0,0 +1,2316 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "imx8mp-pinfunc.h" -+ -+/ { -+ compatible = "fsl,imx8mp"; -+ interrupt-parent = <&gpc>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fec; -+ ethernet1 = &eqos; -+ serial0 = &uart1; -+ serial1 = &uart2; -+ serial2 = &uart3; -+ serial3 = &uart4; -+ gpio0 = &gpio1; -+ gpio1 = &gpio2; -+ gpio2 = &gpio3; -+ gpio3 = &gpio4; -+ gpio4 = &gpio5; -+ mmc0 = &usdhc1; -+ mmc1 = &usdhc2; -+ mmc2 = &usdhc3; -+ isi0 = &isi_0; -+ isi1 = &isi_1; -+ csi0 = &mipi_csi_0; -+ csi1 = &mipi_csi_1; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ idle-states { -+ entry-method = "psci"; -+ -+ cpu_pd_wait: cpu-pd-wait { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0010033>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ wakeup-latency-us = <1500>; -+ }; -+ }; -+ -+ A53_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; -+ enable-method = "psci"; -+ nvmem-cells = <&cpu_speed_grade>; -+ nvmem-cell-names = "speed_grade"; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ }; -+ -+ A53_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ }; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ next-level-cache = <&A53_L2>; -+ clocks = <&clk IMX8MP_CLK_ARM>; -+ operating-points-v2 = <&a53_opp_table>; -+ enable-method = "psci"; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&cpu_pd_wait>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ a53_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <850000>; -+ opp-supported-hw = <0x8a0>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <950000>; -+ opp-supported-hw = <0xa0>, <0x7>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1000000>; -+ opp-supported-hw = <0x20>, <0x3>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ ddr_pmu0: ddr_pmu@3d800000 { -+ compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; -+ reg = <0x0 0x3d800000 0x0 0x400000>; -+ interrupts = ; -+ }; -+ -+ edacmc: memory-controller@3d400000 { -+ compatible = "fsl,imx8mp-ddrc"; -+ reg = <0x0 0x3d400000 0x0 0x400000>; -+ interrupts = ; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x0 0x40000000 0 0x80000000>; -+ }; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+/* -+ * Memory reserved for optee usage. Please do not use. -+ * This will be automaticky added to dtb if OP-TEE is installed. -+ * optee@56000000 { -+ * reg = <0 0x56000000 0 0x2000000>; -+ * no-map; -+ * }; -+ */ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0x40000000 0 0xC0000000>; -+ linux,cma-default; -+ }; -+ -+ dsp_reserved: dsp@92400000 { -+ no-map; -+ reg = <0 0x92400000 0 0x2000000>; -+ }; -+ }; -+ -+ osc_32k: clock-osc-32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "osc_32k"; -+ }; -+ -+ osc_24m: clock-osc-24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc_24m"; -+ }; -+ -+ clk_ext1: clock-ext1 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext1"; -+ }; -+ -+ clk_ext2: clock-ext2 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext2"; -+ }; -+ -+ clk_ext3: clock-ext3 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext3"; -+ }; -+ -+ clk_ext4: clock-ext4 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <133000000>; -+ clock-output-names = "clk_ext4"; -+ }; -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, -+ <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, -+ <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, -+ <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, -+ <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, -+ <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_DRAM_PLL>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", -+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", -+ "sys_pll1_800m", "dram_pll_div"; -+ }; -+ -+ power-domains { -+ compatible = "simple-bus"; -+ -+ /* HSIO SS */ -+ hsiomix_pd: hsiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <0>; -+ domain-name = "hsiomix"; -+ clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, -+ <&clk IMX8MP_CLK_HSIO_ROOT>; -+ }; -+ -+ pcie_pd: pcie-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <1>; -+ domain-name = "pcie"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ usb_otg1_pd: usbotg1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <2>; -+ domain-name = "usb_otg1"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ -+ usb_otg2_pd: usbotg2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <3>; -+ domain-name = "usb_otg2"; -+ parent-domains = <&hsiomix_pd>; -+ }; -+ -+ /* MLMIX */ -+ mlmix_pd: mlmix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <4>; -+ domain-name = "mlmix"; -+ clocks = <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_NPU_ROOT>; -+ }; -+ -+ audiomix_pd: audiomix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <5>; -+ domain-name = "audiomix"; -+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, -+ <&clk IMX8MP_CLK_AUDIO_AXI_DIV>; -+ }; -+ -+ gpumix_pd: gpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <6>; -+ domain-name = "gpumix"; -+ clocks = <&clk IMX8MP_CLK_GPU_ROOT>; -+ }; -+ -+ gpu2d_pd: gpu2d-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <7>; -+ domain-name = "gpu2d"; -+ parent-domains = <&gpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; -+ }; -+ -+ gpu3d_pd: gpu3d-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <8>; -+ domain-name = "gpu3d"; -+ parent-domains = <&gpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>; -+ }; -+ -+ vpumix_pd: vpumix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <9>; -+ domain-name = "vpumix"; -+ clocks =<&clk IMX8MP_CLK_VPU_ROOT>; -+ }; -+ -+ vpu_g1_pd: vpug1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <10>; -+ domain-name = "vpu_g1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; -+ }; -+ -+ vpu_g2_pd: vpug2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <11>; -+ domain-name = "vpu_g2"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; -+ }; -+ -+ vpu_h1_pd: vpuh1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <12>; -+ domain-name = "vpu_h1"; -+ parent-domains = <&vpumix_pd>; -+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; -+ }; -+ -+ mediamix_pd: mediamix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <13>; -+ domain-name = "mediamix"; -+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ }; -+ -+ ispdwp_pd: power-domain@14 { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <14>; -+ domain-name = "ispdwp"; -+ parent-domains = <&mediamix_pd>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; -+ }; -+ -+ mipi_phy1_pd: mipiphy1-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <15>; -+ domain-name = "mipi_phy1"; -+ parent-domains = <&mediamix_pd>; -+ }; -+ -+ mipi_phy2_pd: mipiphy2-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <16>; -+ domain-name = "mipi_phy2"; -+ parent-domains = <&mediamix_pd>; -+ }; -+ -+ hdmimix_pd: hdmimix-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <17>; -+ domain-name = "hdmimix"; -+ clocks = <&clk IMX8MP_CLK_HDMI_ROOT>; -+ }; -+ -+ hdmi_phy_pd: hdmiphy-pd { -+ compatible = "fsl,imx8m-pm-domain"; -+ #power-domain-cells = <0>; -+ domain-index = <18>; -+ domain-name = "hdmi_phy"; -+ parent-domains = <&hdmimix_pd>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ clock-frequency = <8000000>; -+ arm,no-tick-in-suspend; -+ interrupt-parent = <&gic>; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tmu 0x0>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit0: trip1 { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ soc-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tmu 0x1>; -+ trips { -+ soc_alert0: trip0 { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ soc_crit0: trip1 { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; -+ -+ aips1: bus@30000000 { -+ compatible = "simple-bus"; -+ reg = <0x30000000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ gpio1: gpio@30200000 { -+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; -+ reg = <0x30200000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@30210000 { -+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; -+ reg = <0x30210000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@30220000 { -+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; -+ reg = <0x30220000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio4: gpio@30230000 { -+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; -+ reg = <0x30230000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio5: gpio@30240000 { -+ compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; -+ reg = <0x30240000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ tmu: tmu@30260000 { -+ compatible = "fsl,imx8mp-tmu"; -+ reg = <0x30260000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ wdog1: watchdog@30280000 { -+ compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; -+ reg = <0x30280000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ iomuxc: pinctrl@30330000 { -+ compatible = "fsl,imx8mp-iomuxc"; -+ reg = <0x30330000 0x10000>; -+ }; -+ -+ gpr: iomuxc-gpr@30340000 { -+ compatible = "fsl,imx8mp-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", -+ "fsl,imx6q-iomuxc-gpr", "syscon"; -+ reg = <0x30340000 0x10000>; -+ }; -+ -+ ocotp: ocotp-ctrl@30350000 { -+ compatible = "fsl,imx8mp-ocotp", "syscon"; -+ reg = <0x30350000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; -+ /* For nvmem subnodes */ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_speed_grade: speed-grade@10 { -+ reg = <0x10 4>; -+ }; -+ -+ eth_mac1: mac-address@640 { -+ reg = <0x90 6>; -+ }; -+ -+ eth_mac2: mac-address@650 { -+ reg = <0x96 6>; -+ }; -+ }; -+ -+ anatop: anatop@30360000 { -+ compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", -+ "syscon"; -+ reg = <0x30360000 0x10000>; -+ }; -+ -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; -+ clock-names = "ipg"; -+ }; -+ -+ snvs: snvs@30370000 { -+ compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; -+ reg = <0x30370000 0x10000>; -+ -+ snvs_rtc: snvs-rtc-lp{ -+ compatible = "fsl,sec-v4.0-mon-rtc-lp"; -+ regmap =<&snvs>; -+ offset = <0x34>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; -+ clock-names = "snvs-rtc"; -+ }; -+ -+ snvs_pwrkey: snvs-powerkey { -+ compatible = "fsl,sec-v4.0-pwrkey"; -+ regmap = <&snvs>; -+ interrupts = ; -+ linux,keycode = ; -+ wakeup-source; -+ }; -+ }; -+ -+ clk: clock-controller@30380000 { -+ compatible = "fsl,imx8mp-ccm"; -+ reg = <0x30380000 0x10000>; -+ #clock-cells = <1>; -+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, -+ <&clk_ext3>, <&clk_ext4>; -+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", -+ "clk_ext3", "clk_ext4"; -+ assigned-clocks = <&clk IMX8MP_CLK_NOC>, -+ <&clk IMX8MP_CLK_NOC_IO>, -+ <&clk IMX8MP_CLK_GIC>, -+ <&clk IMX8MP_CLK_AUDIO_AHB>, -+ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, -+ <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, -+ <&clk IMX8MP_AUDIO_PLL1>, -+ <&clk IMX8MP_AUDIO_PLL2>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, -+ <800000000>, -+ <500000000>, -+ <400000000>, -+ <800000000>, -+ <400000000>, -+ <393216000>, -+ <361267200>; -+ }; -+ -+ src: src@30390000 { -+ compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; -+ reg = <0x30390000 0x10000>; -+ interrupts = ; -+ #reset-cells = <1>; -+ }; -+ -+ gpc: gpc@303a0000 { -+ compatible = "fsl,imx8mp-gpc"; -+ reg = <0x303a0000 0x10000>; -+ interrupt-parent = <&gic>; -+ interrupt-controller; -+ broken-wake-request-signals; -+ #interrupt-cells = <3>; -+ }; -+ }; -+ -+ aips2: bus@30400000 { -+ compatible = "simple-bus"; -+ reg = <0x30400000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ pwm1: pwm@30660000 { -+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; -+ reg = <0x30660000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, -+ <&clk IMX8MP_CLK_PWM1_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@30670000 { -+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; -+ reg = <0x30670000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, -+ <&clk IMX8MP_CLK_PWM2_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@30680000 { -+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; -+ reg = <0x30680000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, -+ <&clk IMX8MP_CLK_PWM3_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@30690000 { -+ compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; -+ reg = <0x30690000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, -+ <&clk IMX8MP_CLK_PWM4_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ system_counter: timer@306a0000 { -+ compatible = "nxp,sysctr-timer"; -+ reg = <0x306a0000 0x20000>; -+ interrupts = ; -+ clocks = <&osc_24m>; -+ clock-names = "per"; -+ }; -+ }; -+ -+ aips3: bus@30800000 { -+ compatible = "simple-bus"; -+ reg = <0x30800000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ ecspi1: spi@30820000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; -+ reg = <0x30820000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, -+ <&clk IMX8MP_CLK_ECSPI1_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi2: spi@30830000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; -+ reg = <0x30830000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, -+ <&clk IMX8MP_CLK_ECSPI2_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi3: spi@30840000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; -+ reg = <0x30840000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, -+ <&clk IMX8MP_CLK_ECSPI3_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@30860000 { -+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; -+ reg = <0x30860000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_UART1_ROOT>, -+ <&clk IMX8MP_CLK_UART1_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@30880000 { -+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; -+ reg = <0x30880000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_UART3_ROOT>, -+ <&clk IMX8MP_CLK_UART3_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@30890000 { -+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; -+ reg = <0x30890000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_UART2_ROOT>, -+ <&clk IMX8MP_CLK_UART2_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ flexcan1: can@308c0000 { -+ compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; -+ reg = <0x308c0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>, -+ <&clk IMX8MP_CLK_CAN1_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_CAN1>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; -+ assigned-clock-rates = <40000000>; -+ fsl,clk-source= <0>; -+ fsl,stop-mode = <&gpr 0x10 4 0x10 20>; -+ status = "disabled"; -+ }; -+ -+ flexcan2: can@308d0000 { -+ compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; -+ reg = <0x308d0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>, -+ <&clk IMX8MP_CLK_CAN2_ROOT>; -+ clock-names = "ipg", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_CAN2>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; -+ assigned-clock-rates = <40000000>; -+ fsl,clk-source= <0>; -+ fsl,stop-mode = <&gpr 0x10 5 0x10 21>; -+ status = "disabled"; -+ }; -+ -+ crypto: crypto@30900000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x30900000 0x40000>; -+ ranges = <0 0x30900000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_AHB>, -+ <&clk IMX8MP_CLK_IPG_ROOT>; -+ clock-names = "aclk", "ipg"; -+ -+ sec_jr0: jr@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr1: jr@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr2: jr@3000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x3000 0x1000>; -+ interrupts = ; -+ }; -+ }; -+ -+ i2c1: i2c@30a20000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a20000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@30a30000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a30000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@30a40000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@30a50000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_UART4_ROOT>, -+ <&clk IMX8MP_CLK_UART4_ROOT>; -+ clock-names = "ipg", "per"; -+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ mu: mu@30aa0000 { -+ compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; -+ reg = <0x30aa0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_MU_ROOT>; -+ clock-names = "mu"; -+ #mbox-cells = <2>; -+ }; -+ -+ i2c5: i2c@30ad0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; -+ reg = <0x30ad0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; -+ status = "disabled"; -+ }; -+ -+ i2c6: i2c@30ae0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; -+ reg = <0x30ae0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; -+ status = "disabled"; -+ }; -+ -+ usdhc1: mmc@30b40000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MP_CLK_USDHC1_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc2: mmc@30b50000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MP_CLK_USDHC2_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc3: mmc@30b60000 { -+ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; -+ reg = <0x30b60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MP_CLK_USDHC3_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step= <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ flexspi: spi@30bb0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mm-fspi"; -+ reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; -+ reg-names = "fspi_base", "fspi_mmap"; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, -+ <&clk IMX8MP_CLK_QSPI_ROOT>; -+ clock-names = "fspi", "fspi_en"; -+ assigned-clock-rates = <80000000>; -+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>; -+ status = "disabled"; -+ }; -+ -+ sdma1: dma-controller@30bd0000 { -+ compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; -+ reg = <0x30bd0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, -+ <&clk IMX8MP_CLK_AHB>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ }; -+ -+ fec: ethernet@30be0000 { -+ compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; -+ reg = <0x30be0000 0x10000>; -+ interrupts = , -+ , -+ ; -+ clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, -+ <&clk IMX8MP_CLK_SIM_ENET_ROOT>, -+ <&clk IMX8MP_CLK_ENET_TIMER>, -+ <&clk IMX8MP_CLK_ENET_REF>, -+ <&clk IMX8MP_CLK_ENET_PHY_REF>; -+ clock-names = "ipg", "ahb", "ptp", -+ "enet_clk_ref", "enet_out"; -+ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, -+ <&clk IMX8MP_CLK_ENET_TIMER>, -+ <&clk IMX8MP_CLK_ENET_REF>, -+ <&clk IMX8MP_CLK_ENET_TIMER>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, -+ <&clk IMX8MP_SYS_PLL2_100M>, -+ <&clk IMX8MP_SYS_PLL2_125M>; -+ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; -+ fsl,num-tx-queues = <3>; -+ fsl,num-rx-queues = <3>; -+ nvmem-cells = <ð_mac1>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ stop-mode = <&gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; -+ status = "disabled"; -+ }; -+ -+ eqos: ethernet@30bf0000 { -+ compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; -+ reg = <0x30bf0000 0x10000>; -+ interrupts = , -+ ; -+ interrupt-names = "eth_wake_irq", "macirq"; -+ clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, -+ <&clk IMX8MP_CLK_QOS_ENET_ROOT>, -+ <&clk IMX8MP_CLK_ENET_QOS_TIMER>, -+ <&clk IMX8MP_CLK_ENET_QOS>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; -+ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, -+ <&clk IMX8MP_CLK_ENET_QOS_TIMER>, -+ <&clk IMX8MP_CLK_ENET_QOS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, -+ <&clk IMX8MP_SYS_PLL2_100M>, -+ <&clk IMX8MP_SYS_PLL2_125M>; -+ assigned-clock-rates = <0>, <100000000>, <125000000>; -+ nvmem-cells = <ð_mac2>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ intf_mode = <&gpr 0x4>; -+ status = "disabled"; -+ }; -+ }; -+ -+ aips5: bus@30c00000 { -+ compatible = "simple-bus"; -+ reg = <0x30c00000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ spba-bus@30c00000 { -+ compatible = "fsl,spba-bus", "simple-bus"; -+ reg = <0x30c00000 0x100000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ sai1: sai@30c10000 { -+ compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; -+ reg = <0x30c10000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xff 0xff>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@30c20000 { -+ compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; -+ reg = <0x30c20000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@30c30000 { -+ compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; -+ reg = <0x30c30000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0x3 0x3>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@30c50000 { -+ compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; -+ reg = <0x30c50000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@30c60000 { -+ compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; -+ reg = <0x30c60000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, -+ <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, -+ <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sai7: sai@30c80000 { -+ compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai"; -+ reg = <0x30c80000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, -+ <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ easrc: easrc@30c90000 { -+ compatible = "fsl,imx8mn-easrc"; -+ reg = <0x30c90000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; -+ clock-names = "mem"; -+ dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, -+ <&sdma2 18 23 0> , <&sdma2 19 23 0>, -+ <&sdma2 20 23 0> , <&sdma2 21 23 0>, -+ <&sdma2 22 23 0> , <&sdma2 23 23 0>; -+ dma-names = "ctx0_rx", "ctx0_tx", -+ "ctx1_rx", "ctx1_tx", -+ "ctx2_rx", "ctx2_tx", -+ "ctx3_rx", "ctx3_tx"; -+ fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; -+ fsl,asrc-rate = <8000>; -+ fsl,asrc-width = <16>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ micfil: micfil@30ca0000 { -+ compatible = "fsl,imx8mp-micfil"; -+ reg = <0x30ca0000 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_IPG>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_ROOT>, -+ <&clk IMX8MP_AUDIO_PLL1_OUT>, -+ <&clk IMX8MP_AUDIO_PLL2_OUT>, -+ <&clk IMX8MP_CLK_EXT3>; -+ clock-names = "ipg_clk", "ipg_clk_app", -+ "pll8k", "pll11k", "clkext3"; -+ dmas = <&sdma2 24 25 0x80000000>; -+ dma-names = "rx"; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ aud2htx: aud2htx@30cb0000 { -+ compatible = "fsl,imx8mp-aud2htx"; -+ reg = <0x30cb0000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; -+ clock-names = "bus"; -+ dmas = <&sdma2 26 2 0>; -+ dma-names = "tx"; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ xcvr: xcvr@30cc0000 { -+ compatible = "fsl,imx8mp-xcvr"; -+ reg = <0x30cc0000 0x10000>; -+ interrupts = /* XCVR IRQ 0 */ -+ , -+ /* XCVR IRQ 1 */ -+ , -+ /* XCVR PHY - SPDIF wakeup IRQ */ -+ ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>; -+ clock-names = "ipg", "phy", "spba"; -+ dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; -+ dma-names = "rx", "tx"; -+ fsl,xcvr-fw = "imx/xcvr/xcvr-imx8mp.bin"; -+ resets = <&audiomix_reset 0>; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ }; -+ -+ sdma3: dma-controller@30e00000 { -+ compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; -+ reg = <0x30e00000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ fsl,ratio-1-1; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ sdma2: dma-controller@30e10000 { -+ compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; -+ reg = <0x30e10000 0x10000>; -+ interrupts = ; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ fsl,ratio-1-1; -+ power-domains = <&audiomix_pd>; -+ status = "disabled"; -+ }; -+ -+ audiomix: audiomix@30e20000 { -+ compatible = "fsl,imx8mp-audiomix"; -+ reg = <0x30e20000 0x10000>; -+ -+ audiomix_clk: clock-controller { -+ compatible = "fsl,imx8mp-audiomix-clk"; -+ #clock-cells = <1>; -+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>; -+ clock-names = "audio_root"; -+ power-domains = <&audiomix_pd>; -+ }; -+ -+ audiomix_reset: reset-controller { -+ compatible = "fsl,imx8mp-audiomix-reset"; -+ power-domains = <&audiomix_pd>; -+ #reset-cells = <1>; -+ }; -+ -+ audiomix_dsp: audiomix_dsp { -+ compatible = "fsl,audiomix-dsp"; -+ }; -+ }; -+ -+ mu2: mu2@30e60000 { -+ compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; -+ reg = <0x30E60000 0x10000>; -+ interrupts = ; -+ fsl,dsp_ap_mu_id = <2>; -+ #mbox-cells = <2>; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; -+ status = "okay"; -+ }; -+ }; -+ -+ aips4: bus@32c00000 { -+ compatible = "simple-bus"; -+ reg = <0x32c00000 0x400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ mipi_dsi: mipi_dsi@32e60000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-mipi-dsim"; -+ reg = <0x32e60000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; -+ clock-names = "cfg", "pll-ref"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; -+ assigned-clock-rates = <594000000>; -+ interrupts = ; -+ status = "disabled"; -+ -+ port@0 { -+ dsim_from_lcdif: endpoint { -+ remote-endpoint = <&lcdif_to_dsim>; -+ }; -+ }; -+ }; -+ -+ lcdif1: lcd-controller@32e80000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-lcdif1"; -+ reg = <0x32e80000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <594000000>, <500000000>, <200000000>; -+ interrupts = ; -+ blk-ctl = <&mediamix_blk_ctl>; -+ status = "disabled"; -+ -+ lcdif_disp0: port@0 { -+ reg = <0>; -+ -+ lcdif_to_dsim: endpoint { -+ remote-endpoint = <&dsim_from_lcdif>; -+ }; -+ }; -+ }; -+ -+ lcdif2: lcd-controller@32e90000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-lcdif2"; -+ reg = <0x32e90000 0x10000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ clock-names = "pix", "disp-axi", "disp-apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, -+ <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1039500000>, <500000000>, <200000000>; -+ interrupts = ; -+ status = "disabled"; -+ -+ lcdif2_disp: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ lcdif2_disp_ldb_ch0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&ldb_ch0>; -+ }; -+ -+ lcdif2_disp_ldb_ch1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&ldb_ch1>; -+ }; -+ }; -+ }; -+ -+ mediamix_blk_ctl: blk-ctl@32ec0000 { -+ compatible = "fsl,imx8mp-mediamix-blk-ctl", -+ "syscon"; -+ reg = <0x32ec0000 0x10000>; -+ }; -+ -+ ldb: ldb@32ec005c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-ldb"; -+ clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; -+ clock-names = "ldb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; -+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; -+ gpr = <&mediamix_blk_ctl>; -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ phys = <&ldb_phy1>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb_ch0: endpoint { -+ remote-endpoint = <&lcdif2_disp_ldb_ch0>; -+ }; -+ }; -+ }; -+ -+ lvds-channel@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ phys = <&ldb_phy2>; -+ phy-names = "ldb_phy"; -+ status = "disabled"; -+ -+ port@0 { -+ reg = <0>; -+ -+ ldb_ch1: endpoint { -+ remote-endpoint = <&lcdif2_disp_ldb_ch1>; -+ }; -+ }; -+ }; -+ }; -+ -+ /* TODO for HDMI PHY power on */ -+ hdmi_blk: hdmi-blk@32fc0000 { -+ compatible = "syscon"; -+ reg = <0x32fc0000 0x1000>; -+ }; -+ -+ hdmimix: hdmimix@32fc0000 { -+ compatible = "fsl,imx8mp-audiomix", "fsl,imx8mp-hdmimix"; -+ reg = <0x32fc0000 0x1000>; -+ -+ hdmimix_clk: clock-controller { -+ compatible = "fsl,imx8mp-hdmimix-clk"; -+ #clock-cells = <1>; -+ clocks = <&clk IMX8MP_CLK_DUMMY>; -+ clock-names = "dummy"; -+ status = "disabled"; -+ }; -+ -+ hdmimix_reset: reset-controller { -+ compatible = "fsl,imx8mp-hdmimix-reset"; -+ #reset-cells = <1>; -+ status = "disabled"; -+ }; -+ }; -+ -+ irqsteer_hdmi: irqsteer@32fc2000 { -+ compatible = "fsl,imx-irqsteer"; -+ reg = <0x32fc2000 0x1000>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ fsl,channel = <1>; -+ fsl,num-irqs = <64>; -+ clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK>; -+ clock-names = "ipg"; -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <200000000>; -+ resets = <&hdmimix_reset IMX_HDMIMIX_IRQ_STEER_RESET>; -+ status = "disabled"; -+ }; -+ -+ hdmi_pavi: hdmi-pai-pvi@32fc4000 { -+ compatible = "fsl,imx8mp-hdmi-pavi"; -+ reg = <0x32fc4000 0x1000>; -+ clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_GPA_CLK>; -+ clock-names = "pvi_clk", "pai_clk"; -+ resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PAI_RESET>, -+ <&hdmimix_reset IMX_HDMIMIX_HDMI_PVI_RESET>; -+ reset-names = "pai_rst", "pvi_rst"; -+ status = "disabled"; -+ }; -+ -+ lcdif3: lcd-controller@32fc6000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mp-lcdif3"; -+ reg = <0x32fc6000 0x10000>; -+ clocks = <&hdmiphy 0>, -+ <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_APB>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK>; -+ clock-names = "pix", "disp-axi", "disp-apb", -+ "mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb", -+ "lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu", -+ "noc_hdmi"; -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_APB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <500000000>, <200000000>; -+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_hdmi>; -+ resets = <&hdmimix_reset IMX_HDMIMIX_LCDIF_RESET>; -+ status = "disabled"; -+ -+ lcdif3_disp: port@0 { -+ reg = <0>; -+ -+ lcdif3_to_hdmi: endpoint { -+ remote-endpoint = <&hdmi_from_lcdif3>; -+ }; -+ }; -+ }; -+ -+ hdmi: hdmi@32fd8000 { -+ compatible = "fsl,imx8mp-hdmi"; -+ reg = <0x32fd8000 0x7eff>; -+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&irqsteer_hdmi>; -+ clocks = <&clk IMX8MP_CLK_HDMI_APB>, -+ <&clk IMX8MP_CLK_HDMI_24M>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PREP_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SKP_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SFR_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_CEC_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_APB_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_HPI_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL>; -+ clock-names = "iahb", "isfr", -+ "phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk", -+ "cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk"; -+ assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>, -+ <&clk IMX8MP_CLK_HDMI_AXI>, -+ <&clk IMX8MP_CLK_HDMI_24M>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL2_500M>, -+ <&clk IMX8MP_CLK_24M>; -+ assigned-clock-rates = <200000000>, <500000000>, <24000000>; -+ phys = <&hdmiphy>; -+ phy-names = "hdmi"; -+ resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_TX_RESET>; -+ gpr = <&hdmi_blk>; -+ power-domains = <&hdmi_phy_pd>; -+ status = "disabled"; -+ -+ port@0 { -+ hdmi_from_lcdif3: endpoint { -+ remote-endpoint = <&lcdif3_to_hdmi>; -+ }; -+ }; -+ }; -+ -+ hdmiphy: hdmiphy@32fdff00 { -+ compatible = "fsl,samsung-hdmi-phy"; -+ reg = <0x32fdff00 0x100>; -+ #clock-cells = <1>; -+ clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>, -+ <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>; -+ clock-names = "apb", "ref"; -+ clock-output-names = "hdmi_phy"; -+ #phy-cells = <0>; -+ resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>; -+ status = "disabled"; -+ }; -+ -+ mediamix_gasket0: gasket@32ec0060 { -+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ reg = <0x32ec0060 0x28>; -+ }; -+ -+ mediamix_gasket1: gasket@32ec0090 { -+ compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; -+ reg = <0x32ec0090 0x28>; -+ }; -+ -+ ldb_phy: phy@32ec0128 { -+ compatible = "fsl,imx8mp-lvds-phy"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ gpr = <&mediamix_blk_ctl>; -+ status = "disabled"; -+ -+ ldb_phy1: port@0 { -+ reg = <0>; -+ #phy-cells = <0>; -+ }; -+ -+ ldb_phy2: port@1 { -+ reg = <1>; -+ #phy-cells = <0>; -+ }; -+ }; -+ -+ cameradev: camera { -+ compatible = "fsl,mxc-md", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ isi_0: isi@32e00000 { -+ compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; -+ reg = <0x32e00000 0x2000>; -+ interrupts = ; -+ interface = <2 0 2>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>, -+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <500000000>, <200000000>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ isi_1: isi@32e02000 { -+ compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; -+ reg = <0x32e02000 0x2000>; -+ interrupts = ; -+ interface = <3 0 2>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>, -+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, -+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; -+ assigned-clock-rates = <500000000>, <200000000>; -+ no-reset-control; -+ status = "disabled"; -+ -+ cap_device { -+ compatible = "imx-isi-capture"; -+ status = "disabled"; -+ }; -+ }; -+ -+ mipi_csi_0: csi@32e40000 { -+ compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; -+ reg = <0x32e40000 0x10000>; -+ interrupts = ; -+ clock-frequency = <500000000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ clock-names = "mipi_clk", "disp_axi", "disp_apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; -+ assigned-clock-rates = <500000000>; -+ bus-width = <4>; -+ csi-gpr = <&mediamix_gasket0>; -+ no-reset-control; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: csi@32e50000 { -+ compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; -+ reg = <0x32e50000 0x10000>; -+ interrupts = ; -+ clock-frequency = <266000000>; -+ clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, -+ <&clk IMX8MP_CLK_MEDIA_AXI>, -+ <&clk IMX8MP_CLK_MEDIA_APB>; -+ clock-names = "mipi_clk", "disp_axi", "disp_apb"; -+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; -+ assigned-clock-rates = <266000000>; -+ bus-width = <4>; -+ csi-gpr = <&mediamix_gasket1>; -+ no-reset-control; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ }; -+ -+ pcie_phy: pcie-phy@32f00000 { -+ compatible = "fsl,imx8mp-pcie-phy"; -+ reg = <0x0 0x32f00000 0x0 0x10000>; -+ clocks = <&clk IMX8MP_CLK_PCIE_PHY>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ hsio_mix: hsio-mix@32f10000 { -+ compatible = "fsl,imx8mp-hsio-mix"; -+ reg = <0x0 0x32f10000 0x0 0x8>; -+ }; -+ -+ dma_apbh: dma-apbh@33000000 { -+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; -+ reg = <0 0x33000000 0 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ }; -+ -+ gpmi: gpmi-nand@33002000{ -+ compatible = "fsl,imx7d-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&clk IMX8MP_CLK_NAND_ROOT>, -+ <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ clock-names = "gpmi_io", "gpmi_bch_apb"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ status = "disabled"; -+ }; -+ -+ pcie: pcie@33800000 { -+ compatible = "fsl,imx8mp-pcie", "snps,dw-pcie"; -+ reg = <0x0 0x33800000 0x0 0x400000>, -+ <0x0 0x1ff00000 0x0 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,max-link-speed = <3>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY>, -+ <&src IMX8MQ_RESET_PCIEPHY_PERST>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; -+ phys = <&pcie_phy>; -+ phy-names = "pcie-phy"; -+ fsl,imx8mp-hsio-mix = <&hsio_mix>; -+ status = "disabled"; -+ }; -+ -+ gpu_3d: gpu3d@38000000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x0 0x38000000 0x0 0x8000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_DIV>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ clock-names = "core", "shader", "axi", "ahb"; -+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, -+ <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, <1000000000>, -+ <800000000>, <400000000>; -+ status = "disabled"; -+ }; -+ -+ gpu_2d: gpu2d@38008000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x0 0x38008000 0x0 0x8000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ clock-names = "core", "axi", "ahb"; -+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, -+ <&clk IMX8MP_CLK_GPU_AXI>, -+ <&clk IMX8MP_CLK_GPU_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, <800000000>, <400000000>; -+ status = "disabled"; -+ }; -+ -+ usb3_phy0: usb-phy@381f0040 { -+ compatible = "fsl,imx8mp-usb-phy"; -+ reg = <0 0x381f0040 0 0x40>; -+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usb3_0: usb@32f10100 { -+ compatible = "fsl,imx8mp-dwc3"; -+ reg = <0 0x32f10100 0 0x8>; -+ clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, -+ <&clk IMX8MP_CLK_USB_ROOT>; -+ clock-names = "bus", "sleep"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; -+ assigned-clock-rates = <500000000>; -+ interrupts = ; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ usb_dwc3_0: dwc3@38100000 { -+ compatible = "snps,dwc3"; -+ reg = <0 0x38100000 0 0x10000>; -+ interrupts = ; -+ phys = <&usb3_phy0>, <&usb3_phy0>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ xhci-no-64bit-support; -+ usb3-resume-missing-cas; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u3_susphy_quirk; -+ status = "disabled"; -+ }; -+ -+ }; -+ -+ usb3_phy1: usb-phy@382f0040 { -+ compatible = "fsl,imx8mp-usb-phy"; -+ reg = <0 0x382f0040 0 0x40>; -+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usb3_1: usb@32f10108 { -+ compatible = "fsl,imx8mp-dwc3"; -+ reg = <0 0x32f10108 0 0x8>; -+ clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, -+ <&clk IMX8MP_CLK_USB_ROOT>; -+ clock-names = "bus", "sleep"; -+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; -+ assigned-clock-rates = <500000000>; -+ interrupts = ; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ usb_dwc3_1: dwc3@38200000 { -+ compatible = "snps,dwc3"; -+ reg = <0 0x38200000 0 0x10000>; -+ interrupts = ; -+ phys = <&usb3_phy1>, <&usb3_phy1>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ xhci-no-64bit-support; -+ usb3-resume-missing-cas; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u3_susphy_quirk; -+ status = "disabled"; -+ }; -+ }; -+ -+ vpu_g1: vpu_g1@38300000 { -+ compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; -+ reg = <0x0 0x38300000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>; -+ assigned-clock-rates = <600000000>, <600000000>; -+ status = "disabled"; -+ }; -+ -+ vpu_g2: vpu_g2@38310000 { -+ compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; -+ reg = <0x0 0x38310000 0x0 0x100000>; -+ reg-names = "regs_hantro"; -+ interrupts = ; -+ interrupt-names = "irq_hantro"; -+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; -+ clock-names = "clk_hantro", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>; -+ assigned-clock-rates = <400000000>, <600000000>; -+ status = "disabled"; -+ }; -+ -+ vpu_vc8000e: vpu_vc8000e@38320000 { -+ compatible = "nxp,imx8mp-hantro-vc8000e"; -+ reg = <0x0 0x38320000 0x0 0x10000>; -+ reg-names = "regs_hantro_vc8000e"; -+ interrupts = ; -+ interrupt-names = "irq_hantro_vc8000e"; -+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; -+ clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; -+ assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>; -+ assigned-clock-rates = <400000000>, <600000000>; -+ status = "disabled"; -+ }; -+ -+ ml_vipsi: vipsi@38500000 { -+ compatible = "fsl,imx8-gpu"; -+ reg = <0x0 0x38500000 0x0 0x20000>; -+ interrupts = ; -+ clocks = <&clk IMX8MP_CLK_NPU_ROOT>, -+ <&clk IMX8MP_CLK_NPU_ROOT>, -+ <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>; -+ clock-names = "core", "shader", "axi", "ahb"; -+ assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>, -+ <&clk IMX8MP_CLK_ML_AXI>, -+ <&clk IMX8MP_CLK_ML_AHB>; -+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, -+ <&clk IMX8MP_SYS_PLL1_800M>, -+ <&clk IMX8MP_SYS_PLL1_800M>; -+ assigned-clock-rates = <1000000000>, <800000000>, <400000000>; -+ status = "disabled"; -+ }; -+ -+ dsp: dsp@3b6e8000 { -+ compatible = "fsl,imx8mp-dsp-v1"; -+ memory-region = <&dsp_reserved>; -+ reg = <0x0 0x3B6E8000 0x0 0x88000>; -+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>, -+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; -+ clock-names = "ocram", "core", "debug", "mu2"; -+ fsl,dsp-firmware = "imx/dsp/hifi4.bin"; -+ power-domains = <&audiomix_pd>; -+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; -+ mboxes = <&mu2 2 0>, -+ <&mu2 2 1>, -+ <&mu2 3 0>, -+ <&mu2 3 1>; -+ status = "disabled"; -+ }; -+ -+ display-subsystem { -+ compatible = "fsl,imx-display-subsystem"; -+ ports = <&lcdif_disp0>; -+ }; -+ -+ imx_ion: imx_ion { -+ compatible = "fsl,mxc-ion"; -+ fsl,heap-id = <0>; -+ }; -+ -+ mix_gpu_ml: mix_gpu_ml { -+ compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; -+ cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; -+ reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; -+ reg-names = "phys_baseaddr", "contiguous_mem"; -+ status = "disabled"; -+ }; -+ -+ rpmsg: rpmsg{ -+ compatible = "fsl,imx8mq-rpmsg"; -+ /* up to now, the following channels are used in imx rpmsg -+ * - tx1/rx1: messages channel. -+ * - general interrupt1: remote proc finish re-init rpmsg stack -+ * when A core is partition reset. -+ */ -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ status = "disabled"; -+ }; -+ -+ etm0: etm@28440000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28440000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_0>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm0_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port0>; -+ }; -+ }; -+ }; -+ }; -+ -+ etm1: etm@28540000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28540000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_1>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm1_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port1>; -+ }; -+ }; -+ }; -+ }; -+ -+ etm2: etm@28640000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28640000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_2>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm2_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port2>; -+ }; -+ }; -+ }; -+ }; -+ -+ etm3: etm@28740000 { -+ compatible = "arm,coresight-etm4x", "arm,primecell"; -+ reg = <0x0 0x28740000 0x0 0x10000>; -+ arm,primecell-periphid = <0xbb95d>; -+ cpu = <&A53_3>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ out-ports { -+ port { -+ etm3_out_port: endpoint { -+ remote-endpoint = <&ca_funnel_in_port3>; -+ }; -+ }; -+ }; -+ }; -+ -+ funnel0: funnel { -+ /* -+ * non-configurable funnel don't show up on the AMBA -+ * bus. As such no need to add "arm,primecell". -+ */ -+ compatible = "arm,coresight-static-funnel"; -+ status = "disabled"; -+ -+ in-ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ ca_funnel_in_port0: endpoint { -+ remote-endpoint = <&etm0_out_port>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ ca_funnel_in_port1: endpoint { -+ remote-endpoint = <&etm1_out_port>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ ca_funnel_in_port2: endpoint { -+ remote-endpoint = <&etm2_out_port>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ ca_funnel_in_port3: endpoint { -+ remote-endpoint = <&etm3_out_port>; -+ }; -+ }; -+ }; -+ -+ out-ports { -+ port { -+ ca_funnel_out_port0: endpoint { -+ remote-endpoint = <&hugo_funnel_in_port0>; -+ }; -+ }; -+ }; -+ -+ }; -+ -+ funnel1: funnel@28c03000 { -+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; -+ reg = <0x0 0x28c03000 0x0 0x1000>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ in-ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ hugo_funnel_in_port0: endpoint { -+ remote-endpoint = <&ca_funnel_out_port0>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ hugo_funnel_in_port1: endpoint { -+ /* M7 input */ -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ hugo_funnel_in_port2: endpoint { -+ /* DSP input */ -+ }; -+ }; -+ /* the other input ports are not connect to anything */ -+ }; -+ -+ out-ports { -+ port { -+ hugo_funnel_out_port0: endpoint { -+ remote-endpoint = <&etf_in_port>; -+ }; -+ }; -+ }; -+ }; -+ -+ etf@28c04000 { -+ compatible = "arm,coresight-tmc", "arm,primecell"; -+ reg = <0x0 0x28c04000 0x0 0x1000>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ in-ports { -+ port { -+ etf_in_port: endpoint { -+ remote-endpoint = <&hugo_funnel_out_port0>; -+ }; -+ }; -+ }; -+ -+ out-ports { -+ port { -+ etf_out_port: endpoint { -+ remote-endpoint = <&etr_in_port>; -+ }; -+ }; -+ }; -+ }; -+ -+ etr@28c06000 { -+ compatible = "arm,coresight-tmc", "arm,primecell"; -+ reg = <0x0 0x28c06000 0x0 0x1000>; -+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>; -+ clock-names = "apb_pclk"; -+ status = "disabled"; -+ -+ in-ports { -+ port { -+ etr_in_port: endpoint { -+ remote-endpoint = <&etf_out_port>; -+ }; -+ }; -+ }; -+ }; -+ -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-base.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-base.dts -new file mode 100755 -index 000000000..5d169652f ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-base.dts -@@ -0,0 +1,1142 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2017 NXP -+ * Copyright (C) 2017-2018 Pengutronix, Lucas Stach -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "myd-jx8mx.dtsi" -+ -+/ { -+ model = "MYIR MYD-JX8MX BASE"; -+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; -+ -+ chosen { -+ stdout-path = &uart1; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x40000000 0 0xc0000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ rpmsg_reserved: rpmsg@0xb8000000 { -+ no-map; -+ reg = <0 0xb8000000 0 0x400000>; -+ }; -+ }; -+ -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ resmem: reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* global autoconfigured region for contiguous allocations */ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0 0x3c000000>; -+ alloc-ranges = <0 0x40000000 0 0x40000000>; -+ linux,cma-default; -+ }; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pcie1_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pmic_osc: clock-pmic { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "pmic_osc"; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-vsd-3v3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2>; -+ compatible = "regulator-fixed"; -+ regulator-name = "VSD_3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <20000>; -+ enable-active-high; -+ }; -+ -+ -+ csi1_io: csi1-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "csi1_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ csi2_io: csi2-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "csi2_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 0 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ m2_io: m2-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "m2_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ lte_io: lte-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "lte_pwr"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-always-on; -+ }; -+ -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_leds>; -+ -+ led0: user { -+ label = "user"; -+ gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ -+ led1: cpu { -+ label = "cpu"; -+ gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ -+ user { -+ label = "User k3 Button"; -+ gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; -+ gpio-key,wakeup; -+ linux,code = ; -+ }; -+ -+ }; -+ sound { -+ compatible = "fsl,imx8mq-evk-wm8904", -+ "fsl,imx-audio-wm8904"; -+ model = "wm8904-audio"; -+ cpu-dai = <&sai2>; -+ audio-codec = <&codec>; -+ asrc-controller ; -+ gpr = <&iomuxc_gpr>; -+ audio-routing = -+ "Headphone Jack", "HPOUTL", -+ "Headphone Jack", "HPOUTR", -+ "IN2L", "Line In Jack", -+ "IN2R", "Line In Jack", -+ "Mic Jack", "MICBIAS", -+ "IN1L", "Mic Jack"; -+ }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx8mq-evk-cdnhdmi", -+ "fsl,imx-audio-cdnhdmi"; -+ model = "imx-audio-hdmi"; -+ audio-cpu = <&sai4>; -+ protocol = <1>; -+ hdmi-out; -+ constraint-rate = <44100>, -+ <88200>, -+ <176400>, -+ <32000>, -+ <48000>, -+ <96000>, -+ <192000>; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif1>; -+ spdif-out; -+ spdif-in; -+ }; -+ -+ sound-hdmi-arc { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-hdmi-arc"; -+ spdif-controller = <&spdif2>; -+ spdif-in; -+ }; -+ -+ -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&A53_1 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&A53_2 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&A53_3 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&csi1_bridge { -+ fsl,mipi-mode; -+ fsl,two-8bit-sensor-mode; -+ status = "okay"; -+ -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&csi2_bridge { -+ fsl,mipi-mode; -+ fsl,two-8bit-sensor-mode; -+ status = "okay"; -+ -+ port { -+ csi2_ep: endpoint { -+ remote-endpoint = <&csi2_mipi_ep>; -+ }; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ status = "okay"; -+ -+ phy-reset-duration = <20>; -+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; -+ phy-reset-post-delay=<20>; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <4>; -+ at803x,eee-disabled; -+ }; -+ }; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi1_sensor_ep: endpoint@0 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ -+ csi1_mipi_ep: endpoint@1 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&mipi_csi_2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi2_sensor_ep: endpoint@0 { -+ remote-endpoint = <&ov5640_mipi2_ep>; -+ data-lanes = <1 2>; -+ bus-type = <4>; -+ }; -+ -+ csi2_mipi_ep: endpoint@1 { -+ remote-endpoint = <&csi2_ep>; -+ }; -+ }; -+}; -+ -+&sai2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai2>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "pcm_b2m", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1_pcm>; -+ pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; -+ pinctrl-2 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, -+ <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; -+ status = "okay"; -+}; -+ -+&sai4 { -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, -+ <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai5>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, -+ <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "okay"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>, -+ <&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&spdif2 { -+ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; -+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+ -+&gpio5 { -+ pinctrl-names = "default"; -+ -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ ov5640_mipi1: ov5640_mipi1@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>,<&pinctrl_io1_pwn>; -+ clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; -+ assigned-clock-rates = <20000000>; -+ csi_id = <0>; -+ pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <20000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ }; -+ }; -+ }; -+ -+ pmic: pmic@4b { -+ reg = <0x4b>; -+ compatible = "rohm,bd71837"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pmic>; -+ clocks = <&pmic_osc>; -+ clock-names = "osc"; -+ clock-output-names = "pmic_clk"; -+ interrupt-parent = <&gpio1>; -+ interrupts = <7 GPIO_ACTIVE_LOW>; -+ interrupt-names = "irq"; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "buck1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <900000>; -+ rohm,dvs-idle-voltage = <850000>; -+ rohm,dvs-suspend-voltage = <800000>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "buck2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ regulator-name = "buck3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ rohm,dvs-run-voltage = <1000000>; -+ }; -+ -+ buck4_reg: BUCK4 { -+ regulator-name = "buck4"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ rohm,dvs-run-voltage = <1000000>; -+ }; -+ -+ buck5_reg: BUCK5 { -+ regulator-name = "buck5"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ regulator-name = "buck6"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ -+ buck7_reg: BUCK7 { -+ regulator-name = "buck7"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ }; -+ -+ buck8_reg: BUCK8 { -+ regulator-name = "buck8"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "ldo1"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "ldo2"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "ldo3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "ldo4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ ldo5_reg: LDO5 { -+ regulator-name = "ldo5"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "ldo6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ ldo7_reg: LDO7 { -+ regulator-name = "ldo7"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+ typec_ptn5150: typec@3d { -+ compatible = "nxp,ptn5150"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ptn5150>; -+ reg = <0x3d>; -+ int-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; -+ vbus-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ -+ -+ -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ -+ codec: wm8904@1a { -+ compatible = "wlf,wm8904"; -+ reg = <0x1a>; -+ clocks = <&clk IMX8MQ_CLK_SAI2>; -+ clock-names = "mclk"; -+ wlf,shared-lrclk; -+ }; -+ -+ rtc: rtc@32 { -+ compatible = "epson,rx8025"; -+ reg = <0x32>; -+ }; -+ -+ -+ -+ ov5640_mipi2: ov5640_mipi2@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi2_rst>,<&pinctrl_io2_pwn>; -+ clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; -+ assigned-clock-rates = <20000000>; -+ csi_id = <1>; -+ pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; -+ mclk = <20000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi2_ep: endpoint { -+ remote-endpoint = <&mipi2_sensor_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ disable-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, -+ <&clk IMX8MQ_CLK_PCIE1_AUX>, -+ <&clk IMX8MQ_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ hard-wired = <1>; -+ status = "okay"; -+}; -+ -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie1>; -+ disable-gpio = <&gpio3 17 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, -+ <&clk IMX8MQ_CLK_PCIE2_AUX>, -+ <&clk IMX8MQ_CLK_PCIE2_PHY>, -+ <&pcie1_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ reserved-region = <&rpmsg_reserved>; -+ status = "okay"; -+}; -+ -+&pgc_gpu { -+ power-supply = <&buck3_reg>; -+}; -+ -+&pgc_vpu { -+ power-supply = <&buck4_reg>; -+}; -+ -+&snvs_pwrkey { -+ status = "okay"; -+}; -+ -+&qspi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_qspi>; -+ status = "okay"; -+ -+ flash0: n25q256a@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <29000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ spi-nor,ddr-quad-read-dummy = <6>; -+ }; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; -+ status = "okay"; -+}; -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; -+ status = "okay"; -+}; -+&uart3 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ assigned-clocks = <&clk IMX8MQ_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ extcon = <&typec_ptn5150>; -+ status = "okay"; -+ -+ -+}; -+ -+&usb3_phy1 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&snvs_rtc{ -+ status = "disabled"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* 4G_WAKE_IN*/ -+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* ME_EN*/ -+ MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 /* LTE_PWR_EN*/ -+ -+ >; -+ }; -+ -+ pinctrl_csi1_pwn: csi1_pwn_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 -+ >; -+ }; -+ -+ pinctrl_csi1_rst: csi_rst1_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ >; -+ }; -+ pinctrl_io1_pwn:csi_io1_grp{ -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 -+ >; -+ }; -+ -+ -+ pinctrl_csi2_pwn: csi2_pwn_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 -+ >; -+ }; -+ -+ pinctrl_csi2_rst: csi_rst2_grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 -+ >; -+ }; -+ pinctrl_io2_pwn:csi_io2_grp{ -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x19 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 -+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f -+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f -+ >; -+ }; -+ -+ -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 -+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 -+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 -+ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 -+ >; -+ }; -+ -+ pinctrl_pcie1: pcie1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ -+ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 -+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16 /* PCIE_nWAKE */ -+ >; -+ }; -+ -+ pinctrl_qspi: qspigrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 -+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 -+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 -+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 -+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 -+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 -+ -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2: regusdhc2grpgpio { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 -+ >; -+ }; -+ -+ pinctrl_sai2: sai2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_pcm: sai1grp_pcm { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai5: sai5grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 -+ MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 -+ >; -+ }; -+ -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 -+ >; -+ }; -+ -+ pinctrl_ptn5150: ptncgrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 -+ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x17059 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 -+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 -+ >; -+ }; -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 /* UART2_RXD */ -+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 /* UART2_TXD */ -+ >; -+ }; -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 -+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 -+ MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 -+ MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 -+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /*BT_EN*/ -+ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14 -+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /*BT_WAKEUP_HOST*/ -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1-100grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1-200grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f -+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf -+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf -+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf -+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf -+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf -+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf -+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf -+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf -+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf -+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f -+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 -+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 -+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 -+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_wdog: wdog1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+ -+ pinctrl_leds: ledgrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 -+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 -+ >; -+ }; -+ -+ pinctrl_gpio_key: keygrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 /*0x17059*/ -+ >; -+ }; -+ -+}; -+ -+&vpu { -+ status = "okay"; -+}; -+ -+&gpu3d { -+ status = "okay"; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+ -+ port@0 { -+ dcss_out: endpoint { -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+}; -+ -+&hdmi { -+ compatible = "cdn,imx8mq-hdmi"; -+ lane-mapping = <0xe4>; -+ status = "okay"; -+ port@1 { -+ hdmi_in: endpoint { -+ remote-endpoint = <&dcss_out>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-dual-atk-10-1.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-dual-atk-10-1.dts -new file mode 100755 -index 000000000..a6edda370 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-dual-atk-10-1.dts -@@ -0,0 +1,21 @@ -+ -+#include "myd-jx8mx-lcdif-atk-10-1.dts" -+ -+/ { -+ model = "MYIR MYD-JX8MX DUAL ATK-10"; -+ sound-hdmi { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-dual-hontron-7.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-dual-hontron-7.dts -new file mode 100755 -index 000000000..32e553ed2 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-dual-hontron-7.dts -@@ -0,0 +1,21 @@ -+ -+#include "myd-jx8mx-lcdif-hontron-7.dts" -+ -+/ { -+ model = "MYIR MYD-JX8MX DUAL HONTRON-10"; -+ sound-hdmi { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-dual-m190etn01-19.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-dual-m190etn01-19.dts -new file mode 100755 -index 000000000..dcecd66ef ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-dual-m190etn01-19.dts -@@ -0,0 +1,21 @@ -+ -+#include "myd-jx8mx-lcdif-m190etn01-19.dts" -+ -+/ { -+ model = "MYIR MYD-JX8MX DUAL M190ETN01"; -+ sound-hdmi { -+ status = "okay"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&dcss { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-atk-10-1.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-atk-10-1.dts -new file mode 100755 -index 000000000..f419b6aea ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-atk-10-1.dts -@@ -0,0 +1,90 @@ -+ -+#include "myd-jx8mx-base.dts" -+#include "myd-jx8mx-panel-atk-10-1.dtsi" -+/ { -+ model = "MYIR MYD-JX8MX LCDIF ATK-10"; -+ sound-hdmi { -+ status = "disabled"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "disabled"; -+}; -+ -+&dcss { -+ status = "disabled"; -+}; -+ -+&lcdif { -+ status = "okay"; -+ -+ -+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; -+ -+ port@0 { -+ lcdif_out: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+ -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ mipi_dsi_in: endpoint { -+ remote-endpoint = <&lcdif_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&panel1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 -+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 -+ -+ >; -+ }; -+ -+}; -+ -+&i2c1 { -+ tc358775:tc358775@f{ -+ compatible = "toshiba,tc358775"; -+ reg = <0x0f>; -+ status = "okay"; -+ }; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-hontron-7.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-hontron-7.dts -new file mode 100755 -index 000000000..b69abcfad ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-hontron-7.dts -@@ -0,0 +1,90 @@ -+ -+#include "myd-jx8mx-base.dts" -+#include "myd-jx8mx-panel-hontron-7.dtsi" -+/ { -+ model = "MYIR MYD-JX8MX LCDIF HONTRON-7"; -+ sound-hdmi { -+ status = "disabled"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "disabled"; -+}; -+ -+&dcss { -+ status = "disabled"; -+}; -+ -+&lcdif { -+ status = "okay"; -+ -+ -+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; -+ -+ port@0 { -+ lcdif_out: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+ -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ mipi_dsi_in: endpoint { -+ remote-endpoint = <&lcdif_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&panel1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 -+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 -+ -+ >; -+ }; -+ -+}; -+ -+&i2c1 { -+ tc358775:tc358775@f{ -+ compatible = "toshiba,tc358775"; -+ reg = <0x0f>; -+ status = "okay"; -+ }; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-m190etn01-19.dts b/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-m190etn01-19.dts -new file mode 100755 -index 000000000..6d92d6fbb ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-lcdif-m190etn01-19.dts -@@ -0,0 +1,90 @@ -+ -+#include "myd-jx8mx-base.dts" -+#include "myd-jx8mx-panel-m190etn01-19.dtsi" -+/ { -+ model = "MYIR MYD-JX8MX LCDIF M190ETN01-19"; -+ sound-hdmi { -+ status = "disabled"; -+ }; -+}; -+ -+&irqsteer { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "disabled"; -+}; -+ -+&dcss { -+ status = "disabled"; -+}; -+ -+&lcdif { -+ status = "okay"; -+ -+ -+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, -+ <&clk IMX8MQ_VIDEO_PLL1>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; -+ -+ port@0 { -+ lcdif_out: endpoint { -+ remote-endpoint = <&mipi_dsi_in>; -+ }; -+ }; -+}; -+ -+ -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ mipi_dsi_in: endpoint { -+ remote-endpoint = <&lcdif_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ mipi_dsi_out: endpoint { -+ remote-endpoint = <&panel1_in>; -+ }; -+ }; -+ }; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&iomuxc { -+ -+ pinctrl_mipi_dsi_en: mipi_dsi_en { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 -+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 -+ -+ >; -+ }; -+ -+}; -+ -+&i2c1 { -+ tc358775:tc358775@f{ -+ compatible = "toshiba,tc358775"; -+ reg = <0x0f>; -+ status = "okay"; -+ }; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-panel-atk-10-1.dtsi b/arch/arm64/boot/dts/myir/myd-jx8mx-panel-atk-10-1.dtsi -new file mode 100755 -index 000000000..61416300c ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-panel-atk-10-1.dtsi -@@ -0,0 +1,147 @@ -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 >; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+ -+&lcdif{ -+ -+ max-memory-bandwidth = <245760000>; /* 1280x800-32@60 */ -+}; -+&mipi_dsi{ -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ stby-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ video-mode = <0>; -+ panel-width-mm = <230>; -+ panel-height-mm = <150>; -+ -+ toshiba,debug = <0>; -+ toshiba,ppi_tx_rx_ta = <0x00030005>; -+ toshiba,ppi_lptxtimecnt = <0x00000003>; -+ toshiba,ppi_d0s_clrsipocount = <0x00000004>; -+ toshiba,ppi_d1s_clrsipocount = <0x00000004>; -+ toshiba,ppi_d2s_clrsipocount = <0x00000004>; -+ toshiba,ppi_d3s_clrsipocount = <0x00000004>; -+ toshiba,ppi_laneenable = <0x0000001f>; -+ toshiba,dsi_laneenable = <0x0000001f>; -+ toshiba,ppi_sartppi = <0x00000001>; -+ toshiba,dsi_sartppi = <0x00000001>; -+ -+ toshiba,vpctrl = <0x03200100>; -+ toshiba,htim1 = <0x003c000a>; -+ toshiba,htim2 = <0x005a0500>; -+ toshiba,vtim1 = <0x000A0003>; -+ toshiba,vtim2 = <0x000A0320>; -+ toshiba,vfuen = <0x00000001>; -+ toshiba,lvphy0 = <0x00448006>; -+ toshiba,lvphy0_1 = <0x00048006>; -+ toshiba,sysrst = <0x00000004>; -+ -+ -+ toshiba,lvmx0003 = <0x03020100>; -+ toshiba,lvmx0407 = <0x08050704>; -+ toshiba,lvmx0811 = <0x0f0e0a09>; -+ toshiba,lvmx1215 = <0x100d0c0b>; -+ toshiba,lvmx1619 = <0x12111716>; -+ toshiba,lvmx2023 = <0x1b151413>; -+ toshiba,lvmx2427 = <0x061a1918>; -+ -+ toshiba,lvcfg = <0x00000031>; -+ -+ backlight = <&lvds_backlight0>; -+ client-device = <&tc358775>; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0:timing0{ -+ clock-frequency = <71000000>; -+ hactive = <1280>; -+ hsync-len = <10>; -+ hback-porch = <70>; -+ hfront-porch = <90>; -+ vactive = <799>; -+ vsync-len = <3>; -+ vback-porch = <10>; -+ vfront-porch = <10>; -+ -+ -+ -+ -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ }; -+ port { -+ panel1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+ -+}; -+&iomuxc { -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c1_gt9271_io: gt9271_iogrp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 -+ MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 -+ >; -+ }; -+ -+ -+}; -+ -+ -+&i2c1 { -+ gt9271@14 { -+ compatible = "goodix,gt9271"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1_gt9271_io>; -+ -+ interrupt-parent = <&gpio1>; -+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; -+ -+ synaptics,x-rotation; -+ synaptics,y-rotation; -+ irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ }; -+ -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-panel-hontron-7.dtsi b/arch/arm64/boot/dts/myir/myd-jx8mx-panel-hontron-7.dtsi -new file mode 100755 -index 000000000..331dfc4ed ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-panel-hontron-7.dtsi -@@ -0,0 +1,145 @@ -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 >; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+ -+&lcdif{ -+ -+ max-memory-bandwidth = <245760000>; /* 1280x800-32@60 */ -+}; -+&mipi_dsi{ -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ stby-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ video-mode = <0>; -+ panel-width-mm = <154>; -+ panel-height-mm = <85>; -+ -+ toshiba,debug = <0>; -+ toshiba,ppi_tx_rx_ta = <0x00020005>; -+ toshiba,ppi_lptxtimecnt = <0x00000002>; -+ toshiba,ppi_d0s_clrsipocount = <0x00000002>; -+ toshiba,ppi_d1s_clrsipocount = <0x00000002>; -+ toshiba,ppi_d2s_clrsipocount = <0x00000002>; -+ toshiba,ppi_d3s_clrsipocount = <0x00000002>; -+ toshiba,ppi_laneenable = <0x0000001f>; -+ toshiba,dsi_laneenable = <0x0000001f>; -+ toshiba,ppi_sartppi = <0x00000001>; -+ toshiba,dsi_sartppi = <0x00000001>; -+ -+ toshiba,vpctrl = <0x03F00100>; -+ toshiba,htim1 = <0x009C0008>; -+ toshiba,htim2 = <0x009C0400>; -+ toshiba,vtim1 = <0x00100006>; -+ toshiba,vtim2 = <0x00100258>; -+ toshiba,vfuen = <0x00000001>; -+ toshiba,lvphy0 = <0x0044802d>; -+ toshiba,lvphy0_1 = <0x0004802d>; -+ toshiba,sysrst = <0x00000004>; -+ -+ -+ toshiba,lvmx0003 = <0x03020100>; -+ toshiba,lvmx0407 = <0x08050704>; -+ toshiba,lvmx0811 = <0x0f0e0a09>; -+ toshiba,lvmx1215 = <0x100d0c0b>; -+ toshiba,lvmx1619 = <0x12111716>; -+ toshiba,lvmx2023 = <0x1b151413>; -+ toshiba,lvmx2427 = <0x061a1918>; -+ -+ toshiba,lvcfg = <0x00000031>; -+ -+ backlight = <&lvds_backlight0>; -+ client-device = <&tc358775>; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0:timing0{ -+ clock-frequency = <51450000>; -+ hactive = <1024>; -+ hsync-len = <8>; -+ hback-porch = <156>; -+ hfront-porch = <156>; -+ vactive = <599>; -+ vsync-len = <6>; -+ vback-porch = <16>; -+ vfront-porch = <16>; -+ -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ }; -+ port { -+ panel1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+ -+}; -+&iomuxc { -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+ -+ pinctrl_edt_ft5x06: edt-ft5x06grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 -+ MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 -+ >; -+ }; -+ -+ -+}; -+ -+ -+&i2c1 { -+ polytouch: edt-ft5x06@38 { -+ compatible = "edt,edt-ft5x06"; -+ reg = <0x38>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_edt_ft5x06>; -+ -+ interrupt-parent = <&gpio1>; -+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; -+ -+ -+ irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; -+ linux,wakeup; -+ -+ touchscreen-size-x= <1024>; -+ touchscreen-size-y= <600>; -+ }; -+ -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx-panel-m190etn01-19.dtsi b/arch/arm64/boot/dts/myir/myd-jx8mx-panel-m190etn01-19.dtsi -new file mode 100755 -index 000000000..8954ab869 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx-panel-m190etn01-19.dtsi -@@ -0,0 +1,127 @@ -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 >; -+ pinctrl-0 = <&pinctrl_lvds0_pwm1>; -+ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+ -+&lcdif{ -+ -+ max-memory-bandwidth = <317572800>; /* 1280x1024-32@60 */ -+}; -+&mipi_dsi{ -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ stby-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ video-mode = <0>; -+ panel-width-mm = <396>; -+ panel-height-mm = <324>; -+ -+ toshiba,debug = <0>; -+ toshiba,ppi_tx_rx_ta = <0x00060008>; -+ toshiba,ppi_lptxtimecnt = <0x00000005>; -+ toshiba,ppi_d0s_clrsipocount = <0x00000008>; -+ toshiba,ppi_d1s_clrsipocount = <0x00000008>; -+ toshiba,ppi_d2s_clrsipocount = <0x00000008>; -+ toshiba,ppi_d3s_clrsipocount = <0x00000008>; -+ toshiba,ppi_laneenable = <0x0000001f>; -+ toshiba,dsi_laneenable = <0x0000001f>; -+ toshiba,ppi_sartppi = <0x00000001>; -+ toshiba,dsi_sartppi = <0x00000001>; -+ -+ toshiba,vpctrl = <0x03F00100>; -+ toshiba,htim1 = <0x00f0001c>; -+ toshiba,htim2 = <0x008c0500>; -+ toshiba,vtim1 = <0x00190007>; -+ toshiba,vtim2 = <0x000a0400>; -+ toshiba,vfuen = <0x00000001>; -+ toshiba,lvphy0 = <0x0044802D>; -+ toshiba,lvphy0_1 = <0x0004802D>; -+ toshiba,sysrst = <0x00000004>; -+ -+ -+ toshiba,lvmx0003 = <0x03020100>; -+ toshiba,lvmx0407 = <0x08050704>; -+ toshiba,lvmx0811 = <0x0f0e0a09>; -+ toshiba,lvmx1215 = <0x100d0c0b>; -+ toshiba,lvmx1619 = <0x12111716>; -+ toshiba,lvmx2023 = <0x1b151413>; -+ toshiba,lvmx2427 = <0x061a1918>; -+ -+ toshiba,lvcfg = <0x00000433>; -+ -+ backlight = <&lvds_backlight0>; -+ client-device = <&tc358775>; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0:timing0{ -+ clock-frequency = <108000000>; -+ hactive = <1280>; -+ hsync-len = <28>; -+ hback-porch = <240>; -+ hfront-porch = <140>; -+ vactive = <1023>; -+ vsync-len = <7>; -+ vback-porch = <25>; -+ vfront-porch = <10>; -+ -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ }; -+ port { -+ panel1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_out>; -+ }; -+ }; -+ }; -+ -+}; -+&iomuxc { -+ pinctrl_lvds0_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 -+ -+ >; -+ }; -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+ -+ -+ -+ -+}; -+ -+ -+ -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/myir/myd-jx8mx.dtsi b/arch/arm64/boot/dts/myir/myd-jx8mx.dtsi -new file mode 100755 -index 000000000..4e8375456 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/myd-jx8mx.dtsi -@@ -0,0 +1,1540 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2017 NXP -+ * Copyright (C) 2017-2018 Pengutronix, Lucas Stach -+ */ -+ -+#include -+#include -+#include -+#include -+#include "dt-bindings/input/input.h" -+#include -+#include -+#include "imx8mq-pinfunc.h" -+ -+/ { -+ interrupt-parent = <&gpc>; -+ -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ csi0 = &mipi_csi_1; -+ csi1 = &mipi_csi_2; -+ ethernet0 = &fec1; -+ gpio0 = &gpio1; -+ gpio1 = &gpio2; -+ gpio2 = &gpio3; -+ gpio3 = &gpio4; -+ gpio4 = &gpio5; -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ i2c3 = &i2c4; -+ serial0 = &uart1; -+ serial1 = &uart2; -+ serial2 = &uart3; -+ serial3 = &uart4; -+ spi0 = &ecspi1; -+ spi1 = &ecspi2; -+ spi2 = &ecspi3; -+ }; -+ -+ ckil: clock-ckil { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "ckil"; -+ }; -+ -+ osc_25m: clock-osc-25m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <25000000>; -+ clock-output-names = "osc_25m"; -+ }; -+ -+ osc_27m: clock-osc-27m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <27000000>; -+ clock-output-names = "osc_27m"; -+ }; -+ -+ clk_ext1: clock-ext1 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext1"; -+ }; -+ -+ clk_ext2: clock-ext2 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext2"; -+ }; -+ -+ clk_ext3: clock-ext3 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <133000000>; -+ clock-output-names = "clk_ext3"; -+ }; -+ -+ clk_ext4: clock-ext4 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency= <133000000>; -+ clock-output-names = "clk_ext4"; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ A53_0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MQ_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ nvmem-cells = <&cpu_speed_grade>; -+ nvmem-cell-names = "speed_grade"; -+ cpu-idle-states = <&CPU_SLEEP>; -+ }; -+ -+ A53_1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MQ_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ }; -+ -+ A53_2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MQ_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ }; -+ -+ A53_3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clk IMX8MQ_CLK_ARM>; -+ enable-method = "psci"; -+ next-level-cache = <&A53_L2>; -+ operating-points-v2 = <&a53_opp_table>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SLEEP>; -+ }; -+ -+ A53_L2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ -+ idle-states { -+ entry-method = "psci"; -+ -+ CPU_SLEEP: cpu-sleep { -+ compatible = "arm,idle-state"; -+ arm,psci-suspend-param = <0x0010033>; -+ local-timer-stop; -+ entry-latency-us = <1000>; -+ exit-latency-us = <700>; -+ min-residency-us = <2700>; -+ wakeup-latency-us = <1500>; -+ }; -+ }; -+ -+ }; -+ -+ a53_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <900000>; -+ /* Industrial only */ -+ opp-supported-hw = <0xf>, <0x4>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <900000>; -+ /* Consumer only */ -+ opp-supported-hw = <0xe>, <0x3>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1300000000 { -+ opp-hz = /bits/ 64 <1300000000>; -+ opp-microvolt = <1000000>; -+ opp-supported-hw = <0xc>, <0x4>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ -+ opp-1500000000 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <1000000>; -+ opp-supported-hw = <0x8>, <0x3>; -+ clock-latency-ns = <150000>; -+ opp-suspend; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tmu 0>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <80000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu-crit { -+ temperature = <90000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , /* Physical Secure */ -+ , /* Physical Non-Secure */ -+ , /* Virtual */ -+ ; /* Hypervisor */ -+ interrupt-parent = <&gic>; -+ arm,no-tick-in-suspend; -+ }; -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx_busfreq"; -+ clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, -+ <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>, -+ <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>, -+ <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>, -+ <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>, -+ <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>, -+ <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>; -+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", -+ "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m", -+ "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src", -+ "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m"; -+ interrupts = , , -+ , ; -+ interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ }; -+ -+ soc@0 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x0 0x3e000000>; -+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; -+ -+ caam_sm: caam-sm@100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x100000 0x8000>; -+ }; -+ -+ bus@30000000 { /* AIPS1 */ -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30000000 0x30000000 0x400000>; -+ -+ sai1: sai@30010000 { -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; -+ reg = <0x30010000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI1_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 8 1 0>, <&sdma2 9 1 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0xff 0xff>; -+ status = "disabled"; -+ }; -+ -+ sai6: sai@30030000 { -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; -+ reg = <0x30030000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI6_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ status = "disabled"; -+ }; -+ -+ sai5: sai@30040000 { -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; -+ reg = <0x30040000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI5_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; -+ dma-names = "rx", "tx"; -+ fsl,shared-interrupt; -+ fsl,dataline = <0 0xf 0xf>; -+ status = "disabled"; -+ }; -+ -+ sai4: sai@30050000 { -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; -+ reg = <0x30050000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI4_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; -+ dma-names = "rx", "tx"; -+ fsl,dataline = <0 0x0 0xf>; -+ status = "disabled"; -+ }; -+ -+ gpio1: gpio@30200000 { -+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; -+ reg = <0x30200000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 10 30>; -+ }; -+ -+ gpio2: gpio@30210000 { -+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; -+ reg = <0x30210000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 40 21>; -+ }; -+ -+ gpio3: gpio@30220000 { -+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; -+ reg = <0x30220000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 61 26>; -+ }; -+ -+ gpio4: gpio@30230000 { -+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; -+ reg = <0x30230000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 87 32>; -+ }; -+ -+ gpio5: gpio@30240000 { -+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; -+ reg = <0x30240000 0x10000>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&iomuxc 0 119 30>; -+ }; -+ -+ tmu: tmu@30260000 { -+ compatible = "fsl,imx8mq-tmu"; -+ reg = <0x30260000 0x10000>; -+ interrupt = ; -+ clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; -+ little-endian; -+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; -+ fsl,tmu-calibration = <0x00000000 0x00000023 -+ 0x00000001 0x00000029 -+ 0x00000002 0x0000002f -+ 0x00000003 0x00000035 -+ 0x00000004 0x0000003d -+ 0x00000005 0x00000043 -+ 0x00000006 0x0000004b -+ 0x00000007 0x00000051 -+ 0x00000008 0x00000057 -+ 0x00000009 0x0000005f -+ 0x0000000a 0x00000067 -+ 0x0000000b 0x0000006f -+ -+ 0x00010000 0x0000001b -+ 0x00010001 0x00000023 -+ 0x00010002 0x0000002b -+ 0x00010003 0x00000033 -+ 0x00010004 0x0000003b -+ 0x00010005 0x00000043 -+ 0x00010006 0x0000004b -+ 0x00010007 0x00000055 -+ 0x00010008 0x0000005d -+ 0x00010009 0x00000067 -+ 0x0001000a 0x00000070 -+ -+ 0x00020000 0x00000017 -+ 0x00020001 0x00000023 -+ 0x00020002 0x0000002d -+ 0x00020003 0x00000037 -+ 0x00020004 0x00000041 -+ 0x00020005 0x0000004b -+ 0x00020006 0x00000057 -+ 0x00020007 0x00000063 -+ 0x00020008 0x0000006f -+ -+ 0x00030000 0x00000015 -+ 0x00030001 0x00000021 -+ 0x00030002 0x0000002d -+ 0x00030003 0x00000039 -+ 0x00030004 0x00000045 -+ 0x00030005 0x00000053 -+ 0x00030006 0x0000005f -+ 0x00030007 0x00000071>; -+ #thermal-sensor-cells = <0>; -+ }; -+ -+ wdog1: watchdog@30280000 { -+ compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; -+ reg = <0x30280000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; -+ status = "disabled"; -+ }; -+ -+ wdog2: watchdog@30290000 { -+ compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; -+ reg = <0x30290000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; -+ status = "disabled"; -+ }; -+ -+ wdog3: watchdog@302a0000 { -+ compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; -+ reg = <0x302a0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; -+ status = "disabled"; -+ }; -+ -+ sdma2: sdma@302c0000 { -+ compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; -+ reg = <0x302c0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, -+ <&clk IMX8MQ_CLK_SDMA2_ROOT>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ }; -+ -+ lcdif: lcdif@30320000 { -+ compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; -+ reg = <0x30320000 0x10000>; -+ clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; -+ clock-names = "pix"; -+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, -+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_27M>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ iomuxc: iomuxc@30330000 { -+ compatible = "fsl,imx8mq-iomuxc"; -+ reg = <0x30330000 0x10000>; -+ }; -+ -+ iomuxc_gpr: syscon@30340000 { -+ compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", -+ "syscon", "simple-mfd"; -+ reg = <0x30340000 0x10000>; -+ -+ mux: mux-controller { -+ compatible = "mmio-mux"; -+ #mux-control-cells = <1>; -+ mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ -+ }; -+ }; -+ -+ ocotp: ocotp-ctrl@30350000 { -+ compatible = "fsl,imx8mq-ocotp", "syscon"; -+ reg = <0x30350000 0x10000>; -+ clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_speed_grade: speed-grade@10 { -+ reg = <0x10 4>; -+ }; -+ -+ fec_mac_address: mac-address@640 { -+ reg = <0x90 6>; -+ }; -+ }; -+ -+ anatop: syscon@30360000 { -+ compatible = "fsl,imx8mq-anatop", "syscon"; -+ reg = <0x30360000 0x10000>; -+ interrupts = ; -+ }; -+ -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = ; -+ jtag-tamper = "disabled"; -+ watchdog-tamper = "enabled"; -+ internal-boot-tamper = "enabled"; -+ external-pin-tamper = "disabled"; -+ }; -+ -+ caam_snvs: caam-snvs@30370000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x30370000 0x10000>; -+ }; -+ -+ snvs: snvs@30370000 { -+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; -+ reg = <0x30370000 0x10000>; -+ -+ snvs_rtc: snvs-rtc-lp{ -+ compatible = "fsl,sec-v4.0-mon-rtc-lp"; -+ regmap =<&snvs>; -+ offset = <0x34>; -+ interrupts = , -+ ; -+ clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; -+ clock-names = "snvs-rtc"; -+ }; -+ -+ snvs_pwrkey: snvs-powerkey { -+ compatible = "fsl,sec-v4.0-pwrkey"; -+ regmap = <&snvs>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; -+ clock-names = "snvs"; -+ linux,keycode = ; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ }; -+ -+ clk: clock-controller@30380000 { -+ compatible = "fsl,imx8mq-ccm"; -+ reg = <0x30380000 0x10000>; -+ interrupts = , -+ ; -+ #clock-cells = <1>; -+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>, -+ <&clk_ext1>, <&clk_ext2>, -+ <&clk_ext3>, <&clk_ext4>; -+ clock-names = "ckil", "osc_25m", "osc_27m", -+ "clk_ext1", "clk_ext2", -+ "clk_ext3", "clk_ext4"; -+ assigned-clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MQ_CLK_AUDIO_AHB>, -+ <&clk IMX8MQ_AUDIO_PLL1>, -+ <&clk IMX8MQ_AUDIO_PLL2>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, -+ <&clk IMX8MQ_SYS2_PLL_500M>; -+ assigned-clock-rates = <0>, -+ <0>, -+ <786432000>, -+ <722534400>; -+ }; -+ -+ src: reset-controller@30390000 { -+ compatible = "fsl,imx8mq-src", "syscon"; -+ reg = <0x30390000 0x10000>; -+ #reset-cells = <1>; -+ }; -+ -+ gpc: gpc@303a0000 { -+ compatible = "fsl,imx8mq-gpc"; -+ reg = <0x303a0000 0x10000>; -+ interrupt-parent = <&gic>; -+ interrupt-controller; -+ broken-wake-request-signals; -+ #interrupt-cells = <3>; -+ -+ pgc { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pgc_mipi: power-domain@0 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ /* -+ * As per comment in ATF source code: -+ * -+ * PCIE1 and PCIE2 share the -+ * same reset signal, if we -+ * power down PCIE2, PCIE1 -+ * will be held in reset too. -+ * -+ * So instead of creating two -+ * separate power domains for -+ * PCIE1 and PCIE2 we create a -+ * link between both and use -+ * it as a shared PCIE power -+ * domain. -+ */ -+ pgc_pcie: power-domain@1 { -+ #power-domain-cells = <0>; -+ reg = ; -+ power-domains = <&pgc_pcie2>; -+ }; -+ -+ pgc_otg1: power-domain@2 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_otg2: power-domain@3 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_ddr1: power-domain@4 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_gpu: power-domain@5 { -+ #power-domain-cells = <0>; -+ reg = ; -+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>; -+ }; -+ -+ pgc_vpu: power-domain@6 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_disp: power-domain@7 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_mipi_csi1: power-domain@8 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_mipi_csi2: power-domain@9 { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ -+ pgc_pcie2: power-domain@a { -+ #power-domain-cells = <0>; -+ reg = ; -+ }; -+ }; -+ }; -+ }; -+ -+ bus@30400000 { /* AIPS2 */ -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30400000 0x30400000 0x400000>; -+ -+ pwm1: pwm@30660000 { -+ compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; -+ reg = <0x30660000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, -+ <&clk IMX8MQ_CLK_PWM1_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@30670000 { -+ compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; -+ reg = <0x30670000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, -+ <&clk IMX8MQ_CLK_PWM2_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@30680000 { -+ compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; -+ reg = <0x30680000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, -+ <&clk IMX8MQ_CLK_PWM3_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@30690000 { -+ compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; -+ reg = <0x30690000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, -+ <&clk IMX8MQ_CLK_PWM4_ROOT>; -+ clock-names = "ipg", "per"; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ system_counter: timer@306a0000 { -+ compatible = "nxp,sysctr-timer"; -+ reg = <0x306a0000 0x20000>; -+ interrupts = ; -+ clocks = <&osc_25m>; -+ clock-names = "per"; -+ }; -+ }; -+ -+ bus@30800000 { /* AIPS3 */ -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x30800000 0x30800000 0x400000>, -+ <0x08000000 0x08000000 0x10000000>; -+ -+ spdif1: spdif@30810000 { -+ compatible = "fsl,imx8mq-spdif", "fsl,imx35-spdif"; -+ reg = <0x30810000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ -+ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ -+ <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MQ_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ ecspi1: spi@30820000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi"; -+ reg = <0x30820000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, -+ <&clk IMX8MQ_CLK_ECSPI1_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ ecspi2: spi@30830000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi"; -+ reg = <0x30830000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, -+ <&clk IMX8MQ_CLK_ECSPI2_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ ecspi3: spi@30840000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi"; -+ reg = <0x30840000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, -+ <&clk IMX8MQ_CLK_ECSPI3_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@30860000 { -+ compatible = "fsl,imx8mq-uart", -+ "fsl,imx6q-uart"; -+ reg = <0x30860000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, -+ <&clk IMX8MQ_CLK_UART1_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@30880000 { -+ compatible = "fsl,imx8mq-uart", -+ "fsl,imx6q-uart"; -+ reg = <0x30880000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, -+ <&clk IMX8MQ_CLK_UART3_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@30890000 { -+ compatible = "fsl,imx8mq-uart", -+ "fsl,imx6q-uart"; -+ reg = <0x30890000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, -+ <&clk IMX8MQ_CLK_UART2_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ spdif2: spdif@308a0000 { -+ compatible = "fsl,imx8mq-spdif", "fsl,imx35-spdif"; -+ reg = <0x308a0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ -+ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ -+ <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ -+ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ -+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ -+ <&clk IMX8MQ_CLK_DUMMY>; /* spba */ -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7", "spba"; -+ dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@308b0000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,imx8mq-sai"; -+ reg = <0x308b0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI2_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ sai3: sai@308c0000 { -+ compatible = "fsl,imx8mq-sai", -+ "fsl,imx6sx-sai"; -+ reg = <0x308c0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, -+ <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_SAI3_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; -+ dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ crypto: crypto@30900000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x30900000 0x40000>; -+ ranges = <0 0x30900000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_AHB>, -+ <&clk IMX8MQ_CLK_IPG_ROOT>; -+ clock-names = "aclk", "ipg"; -+ -+ sec_jr0: jr@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr1: jr@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupts = ; -+ }; -+ -+ sec_jr2: jr@3000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x3000 0x1000>; -+ interrupts = ; -+ }; -+ }; -+ -+ dphy: dphy@30a00300 { -+ compatible = "fsl,imx8mq-mipi-dphy"; -+ reg = <0x30a00300 0x100>; -+ clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; -+ clock-names = "phy_ref"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; -+ assigned-clock-rates = <24000000>; -+ #phy-cells = <0>; -+ power-domains = <&pgc_mipi>; -+ status = "disabled"; -+ }; -+ -+ mipi_dsi: mipi_dsi@30a00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mq-nwl-dsi"; -+ reg = <0x30a00000 0x300>; -+ clocks = <&clk IMX8MQ_CLK_DSI_CORE>, -+ <&clk IMX8MQ_CLK_DSI_AHB>, -+ <&clk IMX8MQ_CLK_DSI_IPG_DIV>, -+ <&clk IMX8MQ_CLK_DSI_PHY_REF>, -+ <&clk IMX8MQ_VIDEO_PLL1>, -+ <&clk IMX8MQ_CLK_LCDIF_PIXEL>; -+ clock-names = "core", -+ "rx_esc", -+ "tx_esc", -+ "phy_ref", -+ "video_pll", -+ "lcdif"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, -+ <&clk IMX8MQ_CLK_DSI_CORE>, -+ <&clk IMX8MQ_CLK_DSI_AHB>, -+ <&clk IMX8MQ_CLK_DSI_IPG_DIV>; -+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, -+ <&clk IMX8MQ_SYS1_PLL_266M>, -+ <&clk IMX8MQ_SYS1_PLL_80M>; -+ assigned-clock-rates = <27000000>, -+ <266000000>, -+ <80000000>, -+ <20000000>; -+ interrupts = ; -+ power-domains = <&pgc_mipi>; -+ resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, -+ <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, -+ <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, -+ <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; -+ reset-names = "byte", "dpi", "esc", "pclk"; -+ mux-controls = <&mux 0>; -+ phys = <&dphy>; -+ phy-names = "dphy"; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@30a20000 { -+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a20000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@30a30000 { -+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a30000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@30a40000 { -+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@30a50000 { -+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; -+ reg = <0x30a50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@30a60000 { -+ compatible = "fsl,imx8mq-uart", -+ "fsl,imx6q-uart"; -+ reg = <0x30a60000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, -+ <&clk IMX8MQ_CLK_UART4_ROOT>; -+ clock-names = "ipg", "per"; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_1: mipi_csi1@30a70000 { -+ compatible = "fsl,mxc-mipi-csi2_yav"; -+ reg = <0x30a70000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, -+ <&clk IMX8MQ_CLK_CSI1_ESC>, -+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>; -+ clock-names = "clk_core", "clk_esc", "clk_pxl"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, -+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>, -+ <&clk IMX8MQ_CLK_CSI1_ESC>; -+ assigned-clock-rates = <133000000>, <100000000>, <66000000>; -+ power-domains = <&pgc_mipi_csi1>; -+ csis-phy-reset = <&src 0x4c 7>; -+ phy-gpr = <&iomuxc_gpr 0x88>; -+ status = "disabled"; -+ }; -+ -+ csi1_bridge: csi1_bridge@30a90000 { -+ compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x30a90000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_CSI1_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; -+ status = "disabled"; -+ }; -+ -+ mu: mu@30aa0000 { -+ compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; -+ reg = <0x30aa0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_MU_ROOT>; -+ clock-names = "mu"; -+ #mbox-cells = <2>; -+ }; -+ -+ usdhc1: mmc@30b40000 { -+ compatible = "fsl,imx8mq-usdhc", -+ "fsl,imx7d-usdhc"; -+ reg = <0x30b40000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, -+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MQ_CLK_USDHC1_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; -+ assigned-clock-rates = <400000000>; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step = <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usdhc2: mmc@30b50000 { -+ compatible = "fsl,imx8mq-usdhc", -+ "fsl,imx7d-usdhc"; -+ reg = <0x30b50000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, -+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, -+ <&clk IMX8MQ_CLK_USDHC2_ROOT>; -+ clock-names = "ipg", "ahb", "per"; -+ fsl,tuning-start-tap = <20>; -+ fsl,tuning-step = <2>; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ mipi_csi_2: mipi_csi2@30b60000 { -+ compatible = "fsl,mxc-mipi-csi2_yav"; -+ reg = <0x30b60000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, -+ <&clk IMX8MQ_CLK_CSI2_ESC>, -+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>; -+ clock-names = "clk_core", "clk_esc", "clk_pxl"; -+ assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, -+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>, -+ <&clk IMX8MQ_CLK_CSI2_ESC>; -+ assigned-clock-rates = <133000000>, <100000000>, <66000000>; -+ power-domains = <&pgc_mipi_csi2>; -+ csis-phy-reset = <&src 0x50 7>; -+ phy-gpr = <&iomuxc_gpr 0xa4>; -+ status = "disabled"; -+ }; -+ -+ csi2_bridge: csi2_bridge@30b80000 { -+ compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; -+ reg = <0x30b80000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_DUMMY>, -+ <&clk IMX8MQ_CLK_CSI2_ROOT>, -+ <&clk IMX8MQ_CLK_DUMMY>; -+ clock-names = "disp-axi", "csi_mclk", "disp_dcic"; -+ status = "disabled"; -+ }; -+ -+ qspi0: spi@30bb0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; -+ reg = <0x30bb0000 0x10000>, -+ <0x08000000 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, -+ <&clk IMX8MQ_CLK_QSPI_ROOT>; -+ clock-names = "qspi_en", "qspi"; -+ status = "disabled"; -+ }; -+ -+ sdma1: sdma@30bd0000 { -+ compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; -+ reg = <0x30bd0000 0x10000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, -+ <&clk IMX8MQ_CLK_AHB>; -+ clock-names = "ipg", "ahb"; -+ #dma-cells = <3>; -+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -+ }; -+ -+ fec1: ethernet@30be0000 { -+ compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; -+ reg = <0x30be0000 0x10000>; -+ interrupts = , -+ , -+ ; -+ clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, -+ <&clk IMX8MQ_CLK_ENET1_ROOT>, -+ <&clk IMX8MQ_CLK_ENET_TIMER>, -+ <&clk IMX8MQ_CLK_ENET_REF>, -+ <&clk IMX8MQ_CLK_ENET_PHY_REF>; -+ clock-names = "ipg", "ahb", "ptp", -+ "enet_clk_ref", "enet_out"; -+ fsl,num-tx-queues = <3>; -+ fsl,num-rx-queues = <3>; -+ nvmem-cells = <&fec_mac_address>; -+ nvmem-cell-names = "mac-address"; -+ nvmem_macaddr_swap; -+ stop-mode = <&iomuxc_gpr 0x10 3>; -+ fsl,wakeup_irq = <2>; -+ status = "disabled"; -+ }; -+ }; -+ -+ bus@32c00000 { /* AIPS4 */ -+ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x32c00000 0x32c00000 0x400000>; -+ -+ hdmi: hdmi@32c00000 { -+ reg = <0x32c00000 0x100000>, -+ <0x32e40000 0x40000>; -+ interrupts = , -+ ; -+ interrupt-names = "plug_in", "plug_out"; -+ }; -+ -+ irqsteer: interrupt-controller@32e2d000 { -+ compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; -+ reg = <0x32e2d000 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; -+ clock-names = "ipg"; -+ fsl,channel = <0>; -+ fsl,num-irqs = <64>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ dcss: display-controller@32e00000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "nxp,imx8mq-dcss"; -+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; -+ interrupts = <6>, <8>, <9>, <16>, <17>; -+ interrupt-names = "ctx_ld", "ctxld_kick", "vblank", -+ "dtrc_ch1", "dtrc_ch2"; -+ interrupt-parent = <&irqsteer>; -+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, -+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, -+ <&clk IMX8MQ_VIDEO2_PLL_OUT>, -+ <&clk IMX8MQ_CLK_DISP_DTRC>, -+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, -+ <&clk IMX8MQ_CLK_PHY_27MHZ>; -+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", -+ "pll_phy_ref"; -+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, -+ <&clk IMX8MQ_CLK_DISP_RTRM>, -+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_SYS1_PLL_800M>, -+ <&clk IMX8MQ_CLK_27M>; -+ assigned-clock-rates = <800000000>, -+ <400000000>; -+ status = "disabled"; -+ }; -+ }; -+ -+ gpu: gpu@38000000 { -+ compatible = "vivante,gc"; -+ reg = <0x38000000 0x40000>; -+ interrupts = ; -+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>; -+ clock-names = "core", "shader", "bus", "reg"; -+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>, -+ <&clk IMX8MQ_GPU_PLL_BYPASS>; -+ assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL>; -+ assigned-clock-rates = <800000000>, <800000000>, -+ <800000000>, <800000000>, <0>; -+ power-domains = <&pgc_gpu>; -+ status = "disabled"; -+ }; -+ -+ usb_dwc3_0: usb@38100000 { -+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; -+ reg = <0x38100000 0x10000>; -+ clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, -+ <&clk IMX8MQ_CLK_USB_CORE_REF>, -+ <&clk IMX8MQ_CLK_32K>; -+ clock-names = "bus_early", "ref", "suspend"; -+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, -+ <&clk IMX8MQ_CLK_USB_CORE_REF>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, -+ <&clk IMX8MQ_SYS1_PLL_100M>; -+ assigned-clock-rates = <500000000>, <100000000>; -+ interrupts = ; -+ phys = <&usb3_phy0>, <&usb3_phy0>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ power-domains = <&pgc_otg1>; -+ usb3-resume-missing-cas; -+ snps,power-down-scale = <2>; -+ status = "disabled"; -+ }; -+ -+ usb3_phy0: usb-phy@381f0040 { -+ compatible = "fsl,imx8mq-usb-phy"; -+ reg = <0x381f0040 0x40>; -+ clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usb_dwc3_1: usb@38200000 { -+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; -+ reg = <0x38200000 0x10000>; -+ clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, -+ <&clk IMX8MQ_CLK_USB_CORE_REF>, -+ <&clk IMX8MQ_CLK_32K>; -+ clock-names = "bus_early", "ref", "suspend"; -+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, -+ <&clk IMX8MQ_CLK_USB_CORE_REF>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, -+ <&clk IMX8MQ_SYS1_PLL_100M>; -+ assigned-clock-rates = <500000000>, <100000000>; -+ interrupts = ; -+ phys = <&usb3_phy1>, <&usb3_phy1>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ power-domains = <&pgc_otg2>; -+ usb3-resume-missing-cas; -+ snps,power-down-scale = <2>; -+ status = "disabled"; -+ }; -+ -+ usb3_phy1: usb-phy@382f0040 { -+ compatible = "fsl,imx8mq-usb-phy"; -+ reg = <0x382f0040 0x40>; -+ clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; -+ clock-names = "phy"; -+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; -+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ dma_apbh: dma-apbh@33000000 { -+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; -+ reg = <0x33000000 0x2000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; -+ #dma-cells = <1>; -+ dma-channels = <4>; -+ clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ }; -+ -+ gpmi: gpmi-nand@33002000{ -+ compatible = "fsl,imx7d-gpmi-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>; -+ reg-names = "gpmi-nand", "bch"; -+ interrupts = ; -+ interrupt-names = "bch"; -+ clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, -+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; -+ clock-names = "gpmi_io", "gpmi_bch_apb"; -+ dmas = <&dma_apbh 0>; -+ dma-names = "rx-tx"; -+ status = "disabled"; -+ }; -+ -+ pcie0: pcie@33800000 { -+ compatible = "fsl,imx8mq-pcie"; -+ reg = <0x33800000 0x400000>, -+ <0x1ff00000 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pgc_pcie>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "turnoff"; -+ status = "disabled"; -+ }; -+ -+ pcie1: pcie@33c00000 { -+ compatible = "fsl,imx8mq-pcie"; -+ reg = <0x33c00000 0x400000>, -+ <0x27f00000 0x80000>; -+ reg-names = "dbi", "config"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ -+ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ num-viewport = <4>; -+ interrupts = , -+ ; /* eDMA */ -+ interrupt-names = "msi", "dma"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,max-link-speed = <2>; -+ power-domains = <&pgc_pcie>; -+ resets = <&src IMX8MQ_RESET_PCIEPHY2>, -+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, -+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; -+ reset-names = "pciephy", "apps", "turnoff"; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@38800000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x38800000 0x10000>, /* GIC Dist */ -+ <0x38880000 0xc0000>, /* GICR */ -+ <0x31000000 0x2000>, /* GICC */ -+ <0x31010000 0x2000>, /* GICV */ -+ <0x31020000 0x2000>; /* GICH */ -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ }; -+ -+ ddr-pmu@3d800000 { -+ compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; -+ reg = <0x3d800000 0x400000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ vpu: vpu@38300000 { -+ compatible = "nxp,imx8mq-hantro"; -+ reg = <0x38300000 0x200000>; -+ reg-names = "regs_hantro"; -+ interrupts = , ; -+ interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; -+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; -+ clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; -+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>; -+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; -+ assigned-clock-rates = <600000000>, <600000000>, <800000000>; -+ power-domains = <&pgc_vpu>; -+ status = "disabled"; -+ }; -+ }; -+ -+ gpu3d: gpu3d@38000000 { -+ compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; -+ reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; -+ reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; -+ interrupts = ; -+ interrupt-names = "irq_3d"; -+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>; -+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; -+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, -+ <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, -+ <&clk IMX8MQ_CLK_GPU_AXI>, -+ <&clk IMX8MQ_CLK_GPU_AHB>; -+ assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>, -+ <&clk IMX8MQ_GPU_PLL_OUT>; -+ assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; -+ power-domains = <&pgc_gpu>; -+ status = "disabled"; -+ }; -+ -+ rpmsg: rpmsg{ -+ compatible = "fsl,imx8mq-rpmsg"; -+ /* up to now, the following channels are used in imx rpmsg -+ * - tx1/rx1: messages channel. -+ * - general interrupt1: remote proc finish re-init rpmsg stack -+ * when A core is partition reset. -+ */ -+ mbox-names = "tx", "rx", "rxdb"; -+ mboxes = <&mu 0 1 -+ &mu 1 1 -+ &mu 3 1>; -+ status = "disabled"; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-evk-rpmsg-v20.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-rpmsg-v20.dts -new file mode 100755 -index 000000000..96e0cc985 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-rpmsg-v20.dts -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "mys-imx8mm-evk-v20.dts" -+ -+/ { -+ model = "MYS rpmsg i.MX8MM EVK board"; -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ rpmsg_dma_reserved:rpmsg_dma@0xb8400000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0xb8400000 0 0x100000>; -+ }; -+ }; -+ -+ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+/* -+ * ATTENTION: M4 may use IPs like below -+ * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 -+ */ -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&rpmsg{ -+ /* -+ * 64K for one rpmsg instance: -+ * --0xb8000000~0xb800ffff: pingpong -+ */ -+ vdev-nums = <1>; -+ reg = <0x0 0xb8000000 0x0 0x10000>; -+ memory-region = <&rpmsg_dma_reserved>; -+ status = "okay"; -+}; -+ -+&sdma1{ -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-evk-rpmsg.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-rpmsg.dts -new file mode 100755 -index 000000000..740d1bd79 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-rpmsg.dts -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include "mys-imx8mm-evk.dts" -+ -+/ { -+ model = "MYS rpmsg i.MX8MM EVK board"; -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ m4_reserved: m4@0x80000000 { -+ no-map; -+ reg = <0 0x80000000 0 0x1000000>; -+ }; -+ -+ rpmsg_dma_reserved:rpmsg_dma@0xb8400000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0 0xb8400000 0 0x100000>; -+ }; -+ }; -+ -+ -+}; -+ -+&clk { -+ init-on-array = ; -+}; -+ -+/* -+ * ATTENTION: M4 may use IPs like below -+ * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 -+ */ -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&rpmsg{ -+ /* -+ * 64K for one rpmsg instance: -+ * --0xb8000000~0xb800ffff: pingpong -+ */ -+ vdev-nums = <1>; -+ reg = <0x0 0xb8000000 0x0 0x10000>; -+ memory-region = <&rpmsg_dma_reserved>; -+ status = "okay"; -+}; -+ -+&sdma1{ -+ status = "disabled"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+}; -+ -+&sdma3 { -+ status = "disabled"; -+}; -+ -+&sai3 { -+ status = "disabled"; -+}; -+ -+&sai1 { -+ status = "disabled"; -+}; -+ -+&flexspi { -+ status = "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-evk-v13.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-v13.dts -new file mode 100755 -index 000000000..4b8e5ad3c ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-v13.dts -@@ -0,0 +1,899 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "myb-imx8mm.dtsi" -+ -+/ { -+ model = "MYS i.MX8MM EVK board"; -+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ rpmsg_reserved: rpmsg@0xb8000000 { -+ no-map; -+ reg = <0 0xb8000000 0 0x400000>; -+ }; -+ }; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_led>; -+ -+ -+ led0: cpu { -+ label = "cpu"; -+ gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user { -+ label = "user"; -+ gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ -+ }; -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ -+ user { -+ label = "User"; -+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -+ gpio-key,wakeup; -+ linux,code = ; -+ }; -+ -+ }; -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ reg_sd1_vmmc: sd1_regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "WLAN_EN"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <20000>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ -+ reg_m2_power_pad: regulator-m2-power-pad { -+ compatible = "regulator-fixed"; -+ regulator-name = "M2_POWER_PAD"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ startup-delay-us = <70000>; -+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif1>; -+ spdif-out; -+ }; -+ -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&csi1_bridge { -+ fsl,mipi-mode; -+ status = "okay"; -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <4>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&pcie0{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ disable-gpio = <&gpio2 20 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ ext_osc = <1>; -+ -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ /*pinctrl-0 = <&pinctrl_sai3>;*/ -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "disabled"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_sai5>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, -+ <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", -+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_pdm>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "disabled"; -+}; -+ -+&snvs_pwrkey { -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&uart2 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_uart3>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "disabled"; -+}; -+ -+&usbotg1 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ usb-role-switch; -+ picophy,pre-emp-curr-control = <3>; -+ picophy,dc-vol-level-adjust = <7>; -+ status = "okay"; -+ -+ port { -+ usbotg_hs_ep: endpoint { -+ remote-endpoint = <&con_usbotg_hs_ep>; -+ }; -+ }; -+}; -+&usbotg2 { -+ dr_mode = "host"; -+ disable-over-current; -+ status = "okay"; -+}; -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ vmmc-supply = <®_sd1_vmmc>; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ wifi-host; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic@4b { -+ compatible = "rohm,bd71847"; -+ reg = <0x4b>; -+ pinctrl-0 = <&pinctrl_pmic>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ rohm,reset-snvs-powered; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ // BUCK5 in datasheet -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck4_reg: BUCK4 { -+ // BUCK6 in datasheet -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: BUCK5 { -+ // BUCK7 in datasheet -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ // BUCK8 in datasheet -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <1900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "LDO6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ -+ rtc: rtc@32 { -+ compatible = "epson,rx8025"; -+ reg = <0x32>; -+ }; -+ -+ typec: stusb1600@28 { -+ compatible = "st,stusb1600"; -+ reg = <0x28>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&stusb1600_pins_a>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>; -+ status = "okay"; -+ -+ -+ -+ typec1_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ power-opmode = "1.5A"; -+ data-role = "dual"; -+ -+ port { -+ con_usbotg_hs_ep: endpoint { -+ remote-endpoint = <&usbotg_hs_ep>; -+ }; -+ }; -+ -+ }; -+ }; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MM_CLK_CLKO1>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ gate-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; -+ pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ -+ -+ -+}; -+ -+ -+ -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_pwn: csi_pwn_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 -+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 -+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 -+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 -+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 -+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 -+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 -+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 -+ >; -+ }; -+ -+ pinctrl_gpio_led: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x00000116 -+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x00000116 -+ >; -+ }; -+ pinctrl_gpio_key: keygrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x116 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ -+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -+ >; -+ }; -+ -+ -+ -+ -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ /* MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 */ -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 -+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 -+ >; -+ }; -+ -+ -+ -+ pinctrl_usdhc1_gpio: usdhc1grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+ stusb1600_pins_a:studb1600grp{ -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1d6 -+ >; -+ }; -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ >; -+ }; -+}; -+ -+&lcdif { -+ status = "okay"; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi1_sensor_ep: endpoint@1 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ -+ csi1_mipi_ep: endpoint@2 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+ -+ -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_h1 { -+ status = "okay"; -+}; -+ -+&gpu { -+ status = "okay"; -+}; -+&snvs_rtc{ -+ status= "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-evk-v20.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-v20.dts -new file mode 100755 -index 000000000..01fc59b78 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-evk-v20.dts -@@ -0,0 +1,897 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "myb-imx8mm.dtsi" -+ -+/ { -+ model = "MYS i.MX8MM EVK board V2.0"; -+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ rpmsg_reserved: rpmsg@0xb8000000 { -+ no-map; -+ reg = <0 0xb8000000 0 0x400000>; -+ }; -+ }; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_led>; -+ -+ -+ led0: cpu { -+ label = "cpu"; -+ gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user { -+ label = "user"; -+ gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ -+ }; -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ -+ user { -+ label = "User"; -+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -+ gpio-key,wakeup; -+ linux,code = ; -+ }; -+ -+ }; -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ reg_sd1_vmmc: sd1_regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "WLAN_EN"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <20000>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ -+ reg_m2_power_pad: regulator-m2-power-pad { -+ compatible = "regulator-fixed"; -+ regulator-name = "M2_POWER_PAD"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ startup-delay-us = <70000>; -+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif1>; -+ spdif-out; -+ }; -+ -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&csi1_bridge { -+ fsl,mipi-mode; -+ status = "okay"; -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <4>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&pcie0{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ disable-gpio = <&gpio2 20 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ ext_osc = <1>; -+ -+ status = "disabled"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ /*pinctrl-0 = <&pinctrl_sai3>;*/ -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "disabled"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_sai5>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif1>; -+ assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, -+ <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", -+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "okay"; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_pdm>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "disabled"; -+}; -+ -+&snvs_pwrkey { -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&uart2 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_uart3>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "disabled"; -+}; -+ -+&usbotg1 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ usb-role-switch; -+ picophy,pre-emp-curr-control = <3>; -+ picophy,dc-vol-level-adjust = <7>; -+ status = "okay"; -+ -+ port { -+ usbotg_hs_ep: endpoint { -+ remote-endpoint = <&con_usbotg_hs_ep>; -+ }; -+ }; -+}; -+&usbotg2 { -+ dr_mode = "host"; -+ disable-over-current; -+ status = "okay"; -+}; -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ vmmc-supply = <®_sd1_vmmc>; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ wifi-host; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic@4b { -+ compatible = "rohm,bd71847"; -+ reg = <0x4b>; -+ pinctrl-0 = <&pinctrl_pmic>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ rohm,reset-snvs-powered; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ // BUCK5 in datasheet -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck4_reg: BUCK4 { -+ // BUCK6 in datasheet -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: BUCK5 { -+ // BUCK7 in datasheet -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ // BUCK8 in datasheet -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <1900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "LDO6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ -+ rtc: rtc@32 { -+ compatible = "epson,rx8025"; -+ reg = <0x32>; -+ }; -+ -+ -+ typec_ptn5150: typec@3d { -+ compatible = "nxp,ptn5150"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ptn5150>; -+ reg = <0x3d>; -+ connect-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ -+ -+ typec1_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ -+ -+ port { -+ con_usbotg_hs_ep: endpoint { -+ remote-endpoint = <&usbotg_hs_ep>; -+ }; -+ }; -+ -+ }; -+ }; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MM_CLK_CLKO1>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ gate-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; -+ pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ -+ -+ -+}; -+ -+ -+ -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_pwn: csi_pwn_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 -+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 -+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 -+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 -+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 -+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 -+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 -+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 -+ >; -+ }; -+ -+ pinctrl_gpio_led: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x00000116 -+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x00000116 -+ >; -+ }; -+ pinctrl_gpio_key: keygrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x116 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ -+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -+ >; -+ }; -+ -+ -+ -+ -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ /* MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 */ -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 -+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 -+ >; -+ }; -+ -+ -+ -+ pinctrl_usdhc1_gpio: usdhc1grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+ pinctrl_ptn5150: ptncgrp{ -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1d6 -+ >; -+ }; -+ pinctrl_spdif1: spdif1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -+ >; -+ }; -+}; -+ -+&lcdif { -+ status = "okay"; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi1_sensor_ep: endpoint@1 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ -+ csi1_mipi_ep: endpoint@2 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+ -+ -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_h1 { -+ status = "okay"; -+}; -+ -+&gpu { -+ status = "okay"; -+}; -+&snvs_rtc{ -+ status= "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-evk.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-evk.dts -new file mode 100755 -index 000000000..47388163b ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-evk.dts -@@ -0,0 +1,887 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2019 NXP -+ */ -+ -+/dts-v1/; -+ -+#include -+#include "myb-imx8mm.dtsi" -+ -+/ { -+ model = "MYS i.MX8MM EVK board"; -+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ rpmsg_reserved: rpmsg@0xb8000000 { -+ no-map; -+ reg = <0 0xb8000000 0 0x400000>; -+ }; -+ }; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_led>; -+ -+ -+ led0: cpu { -+ label = "cpu"; -+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user { -+ label = "user"; -+ gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ -+ }; -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ -+ user { -+ label = "User"; -+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -+ gpio-key,wakeup; -+ linux,code = ; -+ }; -+ -+ }; -+ modem_reset: modem-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <2000>; -+ reset-post-delay-ms = <40>; -+ #reset-cells = <0>; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ reg_sd1_vmmc: sd1_regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "WLAN_EN"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; -+ off-on-delay-us = <20000>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ -+ reg_m2_power_pad: regulator-m2-power-pad { -+ compatible = "regulator-fixed"; -+ regulator-name = "M2_POWER_PAD"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ startup-delay-us = <70000>; -+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ }; -+ -+}; -+ -+&A53_0 { -+ cpu-supply = <&buck2_reg>; -+}; -+ -+&csi1_bridge { -+ fsl,mipi-mode; -+ status = "okay"; -+ port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&csi1_mipi_ep>; -+ }; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <ðphy0>; -+ fsl,magic-packet; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <4>; -+ at803x,eee-disabled; -+ at803x,vddio-1p8v; -+ }; -+ }; -+}; -+ -+&pcie0{ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ disable-gpio = <&gpio2 20 GPIO_ACTIVE_LOW>; -+ reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_PHY>, -+ <&pcie0_refclk>; -+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; -+ ext_osc = <1>; -+ -+ status = "okay"; -+}; -+ -+&sai3 { -+ pinctrl-names = "default"; -+ /*pinctrl-0 = <&pinctrl_sai3>;*/ -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "disabled"; -+}; -+ -+&sai1 { -+ pinctrl-names = "default", "dsd"; -+ pinctrl-0 = <&pinctrl_sai1>; -+ pinctrl-1 = <&pinctrl_sai1_dsd>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-multi-lane; -+ fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; -+ dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; -+ status = "disabled"; -+}; -+ -+&sai5 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_sai5>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <49152000>; -+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, -+ <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; -+ fsl,sai-asynchronous; -+ status = "disabled"; -+}; -+ -+&spdif1 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_spdif1>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, -+ <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, -+ <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; -+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", -+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; -+ status = "disabled"; -+}; -+ -+&micfil { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_pdm>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_PDM>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <196608000>; -+ status = "disabled"; -+}; -+ -+&snvs_pwrkey { -+ status = "okay"; -+}; -+ -+&uart1 { /* BT */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ assigned-clocks = <&clk IMX8MM_CLK_UART1>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ resets = <&modem_reset>; -+ status = "okay"; -+}; -+ -+&uart2 { /* console */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+/* pinctrl-0 = <&pinctrl_uart3>; */ -+ assigned-clocks = <&clk IMX8MM_CLK_UART3>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; -+ fsl,uart-has-rtscts; -+ status = "disabled"; -+}; -+ -+&usbotg1 { -+ dr_mode = "otg"; -+ hnp-disable; -+ srp-disable; -+ adp-disable; -+ usb-role-switch; -+ picophy,pre-emp-curr-control = <3>; -+ picophy,dc-vol-level-adjust = <7>; -+ status = "okay"; -+ -+ port { -+ usbotg_hs_ep: endpoint { -+ remote-endpoint = <&con_usbotg_hs_ep>; -+ }; -+ }; -+}; -+&usbotg2 { -+ dr_mode = "host"; -+ disable-over-current; -+ status = "okay"; -+}; -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ vmmc-supply = <®_sd1_vmmc>; -+ pm-ignore-notify; -+ keep-power-in-suspend; -+ non-removable; -+ wifi-host; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&wdog1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_wdog>; -+ fsl,ext-reset-output; -+ status = "okay"; -+}; -+ -+&flexspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexspi0>; -+ status = "okay"; -+ -+ flash0: mt25qu256aba@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ spi-max-frequency = <80000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ pmic@4b { -+ compatible = "rohm,bd71847"; -+ reg = <0x4b>; -+ pinctrl-0 = <&pinctrl_pmic>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <3 GPIO_ACTIVE_LOW>; -+ rohm,reset-snvs-powered; -+ -+ regulators { -+ buck1_reg: BUCK1 { -+ regulator-name = "BUCK1"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ }; -+ -+ buck2_reg: BUCK2 { -+ regulator-name = "BUCK2"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <1250>; -+ rohm,dvs-run-voltage = <1000000>; -+ rohm,dvs-idle-voltage = <900000>; -+ }; -+ -+ buck3_reg: BUCK3 { -+ // BUCK5 in datasheet -+ regulator-name = "BUCK3"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck4_reg: BUCK4 { -+ // BUCK6 in datasheet -+ regulator-name = "BUCK4"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck5_reg: BUCK5 { -+ // BUCK7 in datasheet -+ regulator-name = "BUCK5"; -+ regulator-min-microvolt = <1605000>; -+ regulator-max-microvolt = <1995000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ buck6_reg: BUCK6 { -+ // BUCK8 in datasheet -+ regulator-name = "BUCK6"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo1_reg: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1600000>; -+ regulator-max-microvolt = <1900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: LDO3 { -+ regulator-name = "LDO3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: LDO4 { -+ regulator-name = "LDO4"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo6_reg: LDO6 { -+ regulator-name = "LDO6"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ -+ rtc: rtc@32 { -+ compatible = "epson,rx8025"; -+ reg = <0x32>; -+ }; -+ -+ typec: stusb1600@28 { -+ compatible = "st,stusb1600"; -+ reg = <0x28>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&stusb1600_pins_a>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>; -+ status = "okay"; -+ -+ -+ -+ typec1_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ power-opmode = "1.5A"; -+ data-role = "dual"; -+ -+ port { -+ con_usbotg_hs_ep: endpoint { -+ remote-endpoint = <&usbotg_hs_ep>; -+ }; -+ }; -+ -+ }; -+ }; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; -+ clocks = <&clk IMX8MM_CLK_CLKO1>; -+ clock-names = "csi_mclk"; -+ assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; -+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>; -+ assigned-clock-rates = <24000000>; -+ csi_id = <0>; -+ gate-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; -+ pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ port { -+ ov5640_mipi1_ep: endpoint { -+ remote-endpoint = <&mipi1_sensor_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ -+ -+ -+}; -+ -+ -+ -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_pwn: csi_pwn_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 -+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 -+ >; -+ }; -+ -+ pinctrl_csi_rst: csi_rst_grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 -+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 -+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f -+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f -+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f -+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f -+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 -+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 -+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 -+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 -+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f -+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 -+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 -+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f -+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 -+ >; -+ }; -+ -+ pinctrl_flexspi0: flexspi0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 -+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 -+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 -+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 -+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 -+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 -+ >; -+ }; -+ -+ pinctrl_gpio_led: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x00000116 -+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x00000116 -+ >; -+ }; -+ pinctrl_gpio_key: keygrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x116 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ -+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 -+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x41 -+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 -+ >; -+ }; -+ -+ pinctrl_pmic: pmicirq { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -+ >; -+ }; -+ -+ -+ -+ -+ -+ pinctrl_sai1: sai1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai1_dsd: sai1grp_dsd { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 -+ MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ /* MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 */ -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 -+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 -+ >; -+ }; -+ -+ -+ -+ pinctrl_usdhc1_gpio: usdhc1grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2grpgpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1c4 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { -+ fsl,pins = < -+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 -+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 -+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 -+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 -+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 -+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 -+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 -+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 -+ >; -+ }; -+ -+ pinctrl_wdog: wdoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 -+ >; -+ }; -+ stusb1600_pins_a:studb1600grp{ -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1d6 -+ >; -+ }; -+}; -+ -+&lcdif { -+ status = "okay"; -+}; -+ -+&mipi_csi_1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ port { -+ mipi1_sensor_ep: endpoint@1 { -+ remote-endpoint = <&ov5640_mipi1_ep>; -+ data-lanes = <2>; -+ csis-hs-settle = <13>; -+ csis-clk-settle = <2>; -+ csis-wclk; -+ }; -+ -+ csi1_mipi_ep: endpoint@2 { -+ remote-endpoint = <&csi1_ep>; -+ }; -+ }; -+}; -+ -+&mipi_dsi { -+ status = "disabled"; -+ -+ -+}; -+ -+&vpu_g1 { -+ status = "okay"; -+}; -+ -+&vpu_g2 { -+ status = "okay"; -+}; -+ -+&vpu_h1 { -+ status = "okay"; -+}; -+ -+&gpu { -+ status = "okay"; -+}; -+&snvs_rtc{ -+ status= "disabled"; -+}; -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-atk-10-1-v20.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-atk-10-1-v20.dts -new file mode 100755 -index 000000000..baa6a3205 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-atk-10-1-v20.dts -@@ -0,0 +1,148 @@ -+/* -+ * Copyright 2019 MYiR Devices -+ */ -+ -+#include "mys-imx8mm-evk-v20.dts" -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+&iomuxc { -+ -+ pinctrl_dsi_lvds_bridge: lvds_bridge_gpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000116 -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x00000116 -+ >; -+ }; -+ atk_pins:pinctrl_atk { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 -+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 -+ >; -+ }; -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1280>, <800>; -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ compatible = "lontium,lt8912"; -+ mipi_dsi_bridge1_out: endpoint { -+ remote-endpoint = <<8912_1_in>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ -+ -+ -+ /* MIPI-DSI to HDMI and LVDS adapter */ -+ hdmi@48 { -+ compatible = "lontium,lt8912"; -+ reg = <0x48>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_dsi_lvds_bridge>; -+ ddc-i2c-bus = <&i2c2>; -+ hpd-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ dsi-lanes = <4>; -+ hdmi_mode = <0>; -+ lvds-enabled = <1>; -+ debug =<1>; -+ bypass=<0>; -+ -+ display-timings { -+ -+ native-mode = <&timing0>; -+ -+ /* LVDS atk 10.1*/ -+ timing0:timing0{ -+ clock-frequency = <71000000>; -+ hactive = <1280>; -+ hsync-len = <32>; -+ hback-porch = <80>; -+ hfront-porch = <48>; -+ vactive = <800>; -+ vsync-len = <6>; -+ vback-porch = <14>; -+ vfront-porch = <3>; -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ -+ }; -+ -+ port { -+ lt8912_1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_bridge1_out>; -+ }; -+ }; -+ }; -+ -+ -+}; -+ -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ /* 10.1-inch , touch */ -+ gt9271@14 { -+ compatible = "goodix,gt9271"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&atk_pins>; -+ -+ interrupt-parent = <&gpio4>; -+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -+ -+ -+ esd-recovery-timeout-ms = <2000>; -+ irq-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+}; -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-atk-10-1.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-atk-10-1.dts -new file mode 100755 -index 000000000..4d1249c9c ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-atk-10-1.dts -@@ -0,0 +1,148 @@ -+/* -+ * Copyright 2019 MYiR Devices -+ */ -+ -+#include "mys-imx8mm-evk.dts" -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+&iomuxc { -+ -+ pinctrl_dsi_lvds_bridge: lvds_bridge_gpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000116 -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x00000116 -+ >; -+ }; -+ atk_pins:pinctrl_atk { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 -+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 -+ >; -+ }; -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1280>, <800>; -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ compatible = "lontium,lt8912"; -+ mipi_dsi_bridge1_out: endpoint { -+ remote-endpoint = <<8912_1_in>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ -+ -+ -+ /* MIPI-DSI to HDMI and LVDS adapter */ -+ hdmi@48 { -+ compatible = "lontium,lt8912"; -+ reg = <0x48>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_dsi_lvds_bridge>; -+ ddc-i2c-bus = <&i2c2>; -+ hpd-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ dsi-lanes = <4>; -+ hdmi_mode = <0>; -+ lvds-enabled = <1>; -+ debug =<1>; -+ bypass=<0>; -+ -+ display-timings { -+ -+ native-mode = <&timing0>; -+ -+ /* LVDS atk 10.1*/ -+ timing0:timing0{ -+ clock-frequency = <71000000>; -+ hactive = <1280>; -+ hsync-len = <32>; -+ hback-porch = <80>; -+ hfront-porch = <48>; -+ vactive = <800>; -+ vsync-len = <6>; -+ vback-porch = <14>; -+ vfront-porch = <3>; -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ -+ }; -+ -+ port { -+ lt8912_1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_bridge1_out>; -+ }; -+ }; -+ }; -+ -+ -+}; -+ -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ /* 10.1-inch , touch */ -+ gt9271@14 { -+ compatible = "goodix,gt9271"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&atk_pins>; -+ -+ interrupt-parent = <&gpio4>; -+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -+ -+ -+ esd-recovery-timeout-ms = <2000>; -+ irq-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+}; -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-hontron-7-v20.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-hontron-7-v20.dts -new file mode 100755 -index 000000000..26af4eb2a ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-hontron-7-v20.dts -@@ -0,0 +1,152 @@ -+/* -+ * Copyright 2019 MYiR Devices -+ */ -+ -+#include "mys-imx8mm-evk-v20.dts" -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+&iomuxc { -+ -+ pinctrl_dsi_lvds_bridge: lvds_bridge_gpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000116 -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x00000116 -+ >; -+ }; -+ edt_ft5x06_pins:pinctrl_ft5xgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00000116 -+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x00000116 -+ >; -+ }; -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1024>, <600>; -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ compatible = "lontium,lt8912"; -+ mipi_dsi_bridge1_out: endpoint { -+ remote-endpoint = <<8912_1_in>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ -+ -+ -+ /* MIPI-DSI to HDMI and LVDS adapter */ -+ hdmi@48 { -+ compatible = "lontium,lt8912"; -+ reg = <0x48>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_dsi_lvds_bridge>; -+ ddc-i2c-bus = <&i2c2>; -+ hpd-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ dsi-lanes = <4>; -+ hdmi_mode = <0>; -+ lvds-enabled = <1>; -+ debug =<1>; -+ bypass=<0>; -+ -+ -+ -+ display-timings { -+ -+ native-mode = <&timing0>; -+ -+ -+ -+ /*7-inch lvds */ -+ timing0:timing0{ -+ clock-frequency = <51200000>; -+ -+ hactive = <1024>; -+ hsync-len = <20>; -+ hback-porch = <162>; -+ hfront-porch = <140>; -+ vactive = <600>; -+ vsync-len = <3>; -+ vback-porch = <20>; -+ vfront-porch = <12>; -+ -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ -+ -+ -+ }; -+ -+ port { -+ lt8912_1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_bridge1_out>; -+ }; -+ }; -+ }; -+ -+ -+}; -+ -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ /* 7-inch ,touch */ -+ ft5x06: ft5x06@38 { -+ compatible = "edt,edt-ft5406"; -+ reg = <0x38>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&edt_ft5x06_pins>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; -+ touchscreen-size-x=<1024>; -+ touchscreen-size-y=<600>; -+ status = "okay"; -+ }; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-hontron-7.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-hontron-7.dts -new file mode 100755 -index 000000000..02ba75841 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912-hontron-7.dts -@@ -0,0 +1,152 @@ -+/* -+ * Copyright 2019 MYiR Devices -+ */ -+ -+#include "mys-imx8mm-evk.dts" -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 5000000 0>; -+ -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+&iomuxc { -+ -+ pinctrl_dsi_lvds_bridge: lvds_bridge_gpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000116 -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x00000116 -+ >; -+ }; -+ edt_ft5x06_pins:pinctrl_ft5xgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00000116 -+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x00000116 -+ >; -+ }; -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1024>, <600>; -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ compatible = "lontium,lt8912"; -+ mipi_dsi_bridge1_out: endpoint { -+ remote-endpoint = <<8912_1_in>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ -+ -+ -+ /* MIPI-DSI to HDMI and LVDS adapter */ -+ hdmi@48 { -+ compatible = "lontium,lt8912"; -+ reg = <0x48>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_dsi_lvds_bridge>; -+ ddc-i2c-bus = <&i2c2>; -+ hpd-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ dsi-lanes = <4>; -+ hdmi_mode = <0>; -+ lvds-enabled = <1>; -+ debug =<1>; -+ bypass=<0>; -+ -+ -+ -+ display-timings { -+ -+ native-mode = <&timing0>; -+ -+ -+ -+ /*7-inch lvds */ -+ timing0:timing0{ -+ clock-frequency = <51200000>; -+ -+ hactive = <1024>; -+ hsync-len = <20>; -+ hback-porch = <162>; -+ hfront-porch = <140>; -+ vactive = <600>; -+ vsync-len = <3>; -+ vback-porch = <20>; -+ vfront-porch = <12>; -+ -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ -+ -+ -+ }; -+ -+ port { -+ lt8912_1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_bridge1_out>; -+ }; -+ }; -+ }; -+ -+ -+}; -+ -+ -+&i2c3 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ /* 7-inch ,touch */ -+ ft5x06: ft5x06@38 { -+ compatible = "edt,edt-ft5406"; -+ reg = <0x38>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&edt_ft5x06_pins>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; -+ touchscreen-size-x=<1024>; -+ touchscreen-size-y=<600>; -+ status = "okay"; -+ }; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -\ No newline at end of file -diff --git a/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912.dts b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912.dts -new file mode 100755 -index 000000000..b5b35fa9b ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/mys-imx8mm-lt8912.dts -@@ -0,0 +1,189 @@ -+/* -+ * Copyright 2019 MYiR Devices -+ */ -+ -+#include "mys-imx8mm-evk.dts" -+ -+ -+ -+&iomuxc { -+ imx8mm-evk { -+ pinctrl_dsi_lvds_bridge: lvds_bridge_gpio { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000116 -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x00000116 -+ >; -+ }; -+ -+ }; -+ -+}; -+ -+&lcdif{ -+ max-res = <1920>, <1080>; -+ status = "okay"; -+}; -+ -+&mipi_dsi { -+ status = "okay"; -+ -+ port@1 { -+ compatible = "lontium,lt8912"; -+ mipi_dsi_bridge1_out: endpoint { -+ remote-endpoint = <<8912_1_in>; -+ attach-bridge; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ -+ -+ -+ /* MIPI-DSI to HDMI and LVDS adapter */ -+ hdmi@48 { -+ compatible = "lontium,lt8912"; -+ pinctrl-names = "default"; -+ -+ ddc-i2c-bus = <&i2c2>; -+ hpd-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ reg = <0x48>; -+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ lvds-enabled = <1>; -+ status = "okay"; -+ -+ display-timings { -+ -+ native-mode = <&timing1>; -+ -+ timing0: timing0 { -+ clock-frequency = <148500000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <36>; -+ vsync-len = <5>; -+ vback-porch = <4>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <0>; -+ pixelclk-active = <0>; -+ }; -+ -+ timing1: timing1 { -+ clock-frequency = <74250000>; -+ hactive = <1280>; -+ vactive = <720>; -+ hfront-porch = <110>; -+ hsync-len = <40>; -+ hback-porch = <220>; -+ vfront-porch = <5>; -+ vsync-len = <5>; -+ vback-porch = <20>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <0>; -+ pixelclk-active = <0>; -+ }; -+ -+ timing2: timing2 { -+ clock-frequency = <60000000>; -+ hactive = <1280>; -+ vactive = <6500>; -+ hfront-porch = <80>; -+ hsync-len = <56>; -+ hback-porch = <64>; -+ vfront-porch = <28>; -+ vsync-len = <3>; -+ vback-porch = <4>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <0>; -+ pixelclk-active = <0>; -+ }; -+ -+ timing6: timing6{ -+ clock-frequency = <74250000>; -+ hactive = <1300>; -+ vactive = <730>; -+ hfront-porch = <70>; -+ hsync-len = <56>; -+ hback-porch = <64>; -+ vfront-porch = <28>; -+ vsync-len = <3>; -+ vback-porch = <4>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <0>; -+ pixelclk-active = <0>; -+ }; -+ -+ timing3: timing3{ -+ clock-frequency = <74250000>; -+ hactive = <1366>; -+ vactive = <768>; -+ hfront-porch = <100>; -+ hsync-len = <56>; -+ hback-porch = <64>; -+ vfront-porch = <28>; -+ vsync-len = <3>; -+ vback-porch = <4>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <0>; -+ pixelclk-active = <0>; -+ }; -+ -+ /*7-inch lvds */ -+ timing4:timing4{ -+ clock-frequency = <70000000>; -+ hactive = <1024>; -+ hsync-len = <60>; -+ hback-porch = <130>; -+ hfront-porch = <136>; -+ vactive = <600>; -+ vsync-len = <10>; -+ vback-porch = <103>; -+ vfront-porch = <25>; -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ -+ /* LVDS atk 10.1*/ -+ timing5:timing5{ -+ clock-frequency = <70000000>; -+ hactive = <1280>; -+ hsync-len = <17>; -+ hback-porch = <60>; -+ hfront-porch = <60>; -+ vactive = <800>; -+ vsync-len = <3>; -+ vback-porch = <10>; -+ vfront-porch = <10>; -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ -+ }; -+ -+ port { -+ lt8912_1_in: endpoint { -+ remote-endpoint = <&mipi_dsi_bridge1_out>; -+ }; -+ }; -+ }; -+ -+ -+}; -+ -+ -diff --git a/arch/arm64/boot/dts/myir/panel-atk-10-1.dtsi b/arch/arm64/boot/dts/myir/panel-atk-10-1.dtsi -new file mode 100755 -index 000000000..4c6a23acf ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/panel-atk-10-1.dtsi -@@ -0,0 +1,136 @@ -+/* -+ * Copyright 2020 MYiR Devices -+ */ -+ -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 1000000 >; /*1KHZ*/ -+ enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1280>, <800>; -+ status = "okay"; -+}; -+ -+&mipi_dsi{ -+ status = "okay"; -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ reg = <0>; -+ -+ panel-width-mm = <230>; -+ panel-height-mm = <150>; -+ -+ toshiba,debug = <0>; -+ toshiba,ppi_tx_rx_ta = <0x00030005>; -+ toshiba,ppi_lptxtimecnt = <0x00000003>; -+ toshiba,ppi_d0s_clrsipocount = <0x00000004>; -+ toshiba,ppi_d1s_clrsipocount = <0x00000004>; -+ toshiba,ppi_d2s_clrsipocount = <0x00000004>; -+ toshiba,ppi_d3s_clrsipocount = <0x00000004>; -+ toshiba,ppi_laneenable = <0x0000001f>; -+ toshiba,dsi_laneenable = <0x0000001f>; -+ toshiba,ppi_sartppi = <0x00000001>; -+ toshiba,dsi_sartppi = <0x00000001>; -+ -+ toshiba,vpctrl = <0x03F00100>; -+ toshiba,htim1 = <0x003c0011>; -+ toshiba,htim2 = <0x003c0500>; -+ toshiba,vtim1 = <0x000A0003>; -+ toshiba,vtim2 = <0x000A0320>; -+ toshiba,vfuen = <0x00000001>; -+ toshiba,lvphy0 = <0x00448006>; -+ toshiba,lvphy0_1 = <0x00048006>; -+ toshiba,sysrst = <0x00000004>; -+ -+ toshiba,lvmx0003 = <0x03020100>; -+ toshiba,lvmx0407 = <0x08050704>; -+ toshiba,lvmx0811 = <0x0f0e0a09>; -+ toshiba,lvmx1215 = <0x100d0c0b>; -+ toshiba,lvmx2023 = <0x1b151413>; -+ toshiba,lvmx2427 = <0x061a1918>; -+ toshiba,lvmx1619 = <0x12111716>; -+ toshiba,lvcfg = <0x00000031>; -+ -+ // backlight = <&lvds_backlight0>; -+ client-device = <&tc358775>; -+ display-timings { -+ native-mode = <&timing0>; -+ timing0:timing0{ -+ clock-frequency = <70000000>; -+ hactive = <1280>; -+ hsync-len = <17>; -+ hback-porch = <60>; -+ hfront-porch = <60>; -+ vactive = <799>; -+ vsync-len = <3>; -+ vback-porch = <10>; -+ vfront-porch = <10>; -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ }; -+ -+ }; -+}; -+ -+&iomuxc { -+ imx8mm-evk { -+ -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c_synaptics_dsx_io: synaptics_dsx_iogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 -+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 -+ >; -+ }; -+ -+ }; -+ -+}; -+ -+&i2c3 { -+ gt9271@14 { -+ compatible = "goodix,gt9271"; -+ reg = <0x14>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c_synaptics_dsx_io>; -+ -+ interrupt-parent = <&gpio4>; -+ interrupts = <1 IRQ_TYPE_EDGE_RISING>; -+ /*synaptics,y-rotation;*/ -+ esd-recovery-timeout-ms = <2000>; -+ irq-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -+ -diff --git a/arch/arm64/boot/dts/myir/panel-hontron-7.dtsi b/arch/arm64/boot/dts/myir/panel-hontron-7.dtsi -new file mode 100755 -index 000000000..2bdd039ce ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/panel-hontron-7.dtsi -@@ -0,0 +1,113 @@ -+/* -+ * Copyright 2020 MYiR Devices -+ */ -+ /*hontron a4-cm1 7.0 inch */ -+ -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 1000000 >; /*1KHZ*/ -+ enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+&lcdif{ -+ max-res = <1024>, <600>; -+ status = "okay"; -+}; -+ -+&mipi_dsi{ -+ -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ reg = <0>; -+ -+ panel-width-mm = <154>; -+ panel-height-mm = <85>; -+ -+ toshiba,debug = <0>; -+ toshiba,ppi_tx_rx_ta = <0x00020003>; -+ toshiba,ppi_lptxtimecnt = <0x00000002>; -+ toshiba,ppi_d0s_clrsipocount = <0x00000001>; -+ toshiba,ppi_d1s_clrsipocount = <0x00000001>; -+ toshiba,ppi_d2s_clrsipocount = <0x00000001>; -+ toshiba,ppi_d3s_clrsipocount = <0x00000001>; -+ toshiba,ppi_laneenable = <0x0000001f>; -+ toshiba,dsi_laneenable = <0x0000001f>; -+ toshiba,ppi_sartppi = <0x00000001>; -+ toshiba,dsi_sartppi = <0x00000001>; -+ -+ toshiba,vpctrl = <0x03F00100>; -+ toshiba,htim1 = <0x00a00074>; -+ toshiba,htim2 = <0x00180400>; -+ toshiba,vtim1 = <0x00180003>; -+ toshiba,vtim2 = <0x00020258>; -+ toshiba,vfuen = <0x00000001>; -+ toshiba,lvphy0 = <0x0044802d>; -+ toshiba,lvphy0_1 = <0x0004802d>; -+ toshiba,sysrst = <0x00000004>; -+ -+ toshiba,lvmx0003 = <0x03020100>; -+ toshiba,lvmx0407 = <0x08050704>; -+ toshiba,lvmx0811 = <0x0f0e0a09>; -+ toshiba,lvmx1215 = <0x100d0c0b>; -+ toshiba,lvmx2023 = <0x1b151413>; -+ toshiba,lvmx2427 = <0x061a1918>; -+ toshiba,lvmx1619 = <0x12111716>; -+ toshiba,lvcfg = <0x00000031>; -+ -+ client-device = <&tc358775>; -+ display-timings { -+ native-mode = <&timing0>; -+ timing0:timing0{ -+ clock-frequency = <50000000>; -+ hactive = <1024>; -+ hsync-len = <116>; -+ hback-porch = <160>; -+ hfront-porch = <24>; -+ vactive = <599>; -+ vsync-len = <3>; -+ vback-porch = <24>; -+ vfront-porch = <2>; -+ -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ }; -+ -+ }; -+ -+}; -+ -+&iomuxc { -+ imx8mm-evk { -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+ -+ }; -+ -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -+ -diff --git a/arch/arm64/boot/dts/myir/panel-me190etn01.dtsi b/arch/arm64/boot/dts/myir/panel-me190etn01.dtsi -new file mode 100755 -index 000000000..e6c1422a9 ---- /dev/null -+++ b/arch/arm64/boot/dts/myir/panel-me190etn01.dtsi -@@ -0,0 +1,111 @@ -+/* -+ * Copyright 2020 MYiR Devices -+ */ -+ -+/{ -+ lvds_backlight0: lvds_backlight@0 { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm1 0 1000000 >; /*1KHZ*/ -+ enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 -+ 10 11 12 13 14 15 16 17 18 19 -+ 20 21 22 23 24 25 26 27 28 29 -+ 30 31 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 48 49 -+ 50 51 52 53 54 55 56 57 58 59 -+ 60 61 62 63 64 65 66 67 68 69 -+ 70 71 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 88 89 -+ 90 91 92 93 94 95 96 97 98 99 -+ 100>; -+ default-brightness-level = <80>; -+ }; -+}; -+ -+ -+&lcdif{ -+ status = "okay"; -+ max-res = <1280>, <1024>; -+}; -+ -+&mipi_dsi{ -+ panel@0 { -+ compatible = "toshiba,panel-tc358775"; -+ reg = <0>; -+ pinctrl-0 = <&pinctrl_mipi_dsi_en>; -+ stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ reset-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; -+ dsi-lanes = <4>; -+ panel-width-mm = <396>; -+ panel-height-mm = <324>; -+ -+ toshiba,debug = <0>; -+ toshiba,ppi_tx_rx_ta = <0x00050006>; -+ toshiba,ppi_lptxtimecnt = <0x00000004>; -+ toshiba,ppi_d0s_clrsipocount = <0x00000006>; -+ toshiba,ppi_d1s_clrsipocount = <0x00000006>; -+ toshiba,ppi_d2s_clrsipocount = <0x00000006>; -+ toshiba,ppi_d3s_clrsipocount = <0x00000006>; -+ toshiba,ppi_laneenable = <0x0000001f>; -+ toshiba,dsi_laneenable = <0x0000001f>; -+ toshiba,ppi_sartppi = <0x00000001>; -+ toshiba,dsi_sartppi = <0x00000001>; -+ -+ toshiba,vpctrl = <0x03F00100>; -+ toshiba,htim1 = <0x00A00020>; -+ toshiba,htim2 = <0x00300500>; -+ toshiba,vtim1 = <0x001E0007>; -+ toshiba,vtim2 = <0x00030400>; -+ toshiba,vfuen = <0x00000001>; -+ toshiba,lvphy0 = <0x0044802D>; -+ toshiba,lvphy0_1 = <0x0004802D>; -+ toshiba,sysrst = <0x00000004>; -+ -+ -+ toshiba,lvmx0003 = <0x03020100>; -+ toshiba,lvmx0407 = <0x08050704>; -+ toshiba,lvmx0811 = <0x0f0e0a09>; -+ toshiba,lvmx1215 = <0x100d0c0b>; -+ toshiba,lvmx1619 = <0x12111716>; -+ toshiba,lvmx2023 = <0x1b151413>; -+ toshiba,lvmx2427 = <0x061a1918>; -+ toshiba,lvcfg = <0x00000433>; -+ -+ client-device = <&tc358775>; -+ display-timings { -+ native-mode = <&timing0>; -+ timing0:timing0{ -+ clock-frequency = <91000000>; -+ hactive = <1280>; -+ hsync-len = <32>; -+ hback-porch = <160>; -+ hfront-porch = <48>; -+ vactive = <1024>; -+ vsync-len = <7>; -+ vback-porch = <30>; -+ vfront-porch = <3>; -+ vsync-active = <0>; -+ hsync-active =<0>; -+ de-active =<0>; -+ pixelclk-active =<0>; -+ }; -+ }; -+ }; -+ -+}; -+&iomuxc { -+ imx8mm-evk { -+ pinctrl_pwm1: lvds0pwm1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x19 -+ >; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; -+ status = "okay"; -+}; -+ -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 5cfe3cf6f..396ac92bc 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -13,7 +13,6 @@ CONFIG_IKCONFIG=y - CONFIG_IKCONFIG_PROC=y - CONFIG_NUMA_BALANCING=y - CONFIG_MEMCG=y --CONFIG_MEMCG_SWAP=y - CONFIG_BLK_CGROUP=y - CONFIG_CGROUP_PIDS=y - CONFIG_CGROUP_HUGETLB=y -@@ -23,6 +22,7 @@ CONFIG_CGROUP_CPUACCT=y - CONFIG_CGROUP_PERF=y - CONFIG_USER_NS=y - CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y - CONFIG_BLK_DEV_INITRD=y - CONFIG_KALLSYMS_ALL=y - # CONFIG_COMPAT_BRK is not set -@@ -48,6 +48,7 @@ CONFIG_ARCH_QCOM=y - CONFIG_ARCH_RENESAS=y - CONFIG_ARCH_ROCKCHIP=y - CONFIG_ARCH_S32=y -+CONFIG_SOC_S32V234=y - CONFIG_ARCH_SEATTLE=y - CONFIG_ARCH_STRATIX10=y - CONFIG_ARCH_SYNQUACER=y -@@ -65,31 +66,30 @@ CONFIG_ARM64_VA_BITS_48=y - CONFIG_SCHED_MC=y - CONFIG_SCHED_SMT=y - CONFIG_NUMA=y --CONFIG_SECCOMP=y - CONFIG_KEXEC=y - CONFIG_KEXEC_FILE=y - CONFIG_CRASH_DUMP=y - CONFIG_XEN=y - CONFIG_COMPAT=y - CONFIG_RANDOMIZE_BASE=y --CONFIG_HIBERNATION=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y - CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y - CONFIG_ENERGY_MODEL=y - CONFIG_ARM_CPUIDLE=y - CONFIG_ARM_PSCI_CPUIDLE=y - CONFIG_CPU_FREQ=y - CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y - CONFIG_CPU_FREQ_GOV_POWERSAVE=m - CONFIG_CPU_FREQ_GOV_USERSPACE=y --CONFIG_CPU_FREQ_GOV_ONDEMAND=y - CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m --CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y - CONFIG_CPUFREQ_DT=y - CONFIG_ACPI_CPPC_CPUFREQ=m - CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m - CONFIG_ARM_ARMADA_37XX_CPUFREQ=y - CONFIG_ARM_SCPI_CPUFREQ=y --CONFIG_ARM_IMX_CPUFREQ_DT=m -+CONFIG_ARM_IMX_CPUFREQ_DT=y - CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y - CONFIG_ARM_QCOM_CPUFREQ_HW=y - CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -@@ -100,12 +100,12 @@ CONFIG_RASPBERRYPI_FIRMWARE=y - CONFIG_INTEL_STRATIX10_SERVICE=y - CONFIG_INTEL_STRATIX10_RSU=m - CONFIG_EFI_CAPSULE_LOADER=y -+CONFIG_IMX_DSP=y - CONFIG_IMX_SCU=y - CONFIG_IMX_SCU_PD=y - CONFIG_ACPI=y - CONFIG_ACPI_APEI=y - CONFIG_ACPI_APEI_GHES=y --CONFIG_ACPI_APEI_PCIEAER=y - CONFIG_ACPI_APEI_MEMORY_FAILURE=y - CONFIG_ACPI_APEI_EINJ=y - CONFIG_VIRTUALIZATION=y -@@ -137,7 +137,7 @@ CONFIG_IP_MULTICAST=y - CONFIG_IP_PNP=y - CONFIG_IP_PNP_DHCP=y - CONFIG_IP_PNP_BOOTP=y --CONFIG_IPV6=m -+CONFIG_IPV6_SIT=m - CONFIG_NETFILTER=y - CONFIG_NF_CONNTRACK=m - CONFIG_NF_CONNTRACK_EVENTS=y -@@ -164,6 +164,7 @@ CONFIG_VLAN_8021Q=m - CONFIG_VLAN_8021Q_GVRP=y - CONFIG_VLAN_8021Q_MVRP=y - CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_MULTIQ=m - CONFIG_NET_SCH_CBS=m - CONFIG_NET_SCH_ETF=m - CONFIG_NET_SCH_TAPRIO=m -@@ -172,32 +173,45 @@ CONFIG_NET_SCH_INGRESS=m - CONFIG_NET_CLS_BASIC=m - CONFIG_NET_CLS_FLOWER=m - CONFIG_NET_CLS_ACT=y -+CONFIG_NET_CLS_TCINDEX=m - CONFIG_NET_ACT_GACT=m - CONFIG_NET_ACT_MIRRED=m - CONFIG_NET_ACT_GATE=m -+CONFIG_LLC2=y -+CONFIG_TSN=y -+CONFIG_NET_SWITCHDEV=y - CONFIG_QRTR=m - CONFIG_QRTR_SMD=m - CONFIG_QRTR_TUN=m - CONFIG_BPF_JIT=y -+CONFIG_NET_PKTGEN=m - CONFIG_CAN=m -+CONFIG_CAN_FLEXCAN=m - CONFIG_CAN_RCAR=m - CONFIG_CAN_RCAR_CANFD=m --CONFIG_CAN_FLEXCAN=m --CONFIG_BT=m --CONFIG_BT_HIDP=m --# CONFIG_BT_HS is not set --# CONFIG_BT_LE is not set -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y - CONFIG_BT_LEDS=y - # CONFIG_BT_DEBUGFS is not set - CONFIG_BT_HCIBTUSB=m --CONFIG_BT_HCIUART=m -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y - CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y - CONFIG_BT_HCIUART_BCM=y - CONFIG_BT_HCIUART_QCA=y --CONFIG_CFG80211=m --CONFIG_MAC80211=m -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=y -+CONFIG_NL80211_TESTMODE=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y - CONFIG_MAC80211_LEDS=y --CONFIG_RFKILL=m - CONFIG_NET_9P=y - CONFIG_NET_9P_VIRTIO=y - CONFIG_NFC=m -@@ -219,28 +233,32 @@ CONFIG_PCIE_ALTERA=y - CONFIG_PCIE_ALTERA_MSI=y - CONFIG_PCI_HOST_THUNDER_PEM=y - CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCI_IMX6_HOST=y -+CONFIG_PCI_IMX6_EP=y - CONFIG_PCIE_ROCKCHIP_HOST=m - CONFIG_PCIE_BRCMSTB=m - CONFIG_PCI_LAYERSCAPE=y --CONFIG_PCIE_LAYERSCAPE_GEN4=y - CONFIG_PCI_HISI=y - CONFIG_PCIE_QCOM=y - CONFIG_PCIE_ARMADA_8K=y - CONFIG_PCIE_KIRIN=y - CONFIG_PCIE_HISI_STB=y - CONFIG_PCIE_TEGRA194_HOST=m -+CONFIG_PCIE_LAYERSCAPE_GEN4=y - CONFIG_PCI_ENDPOINT=y - CONFIG_PCI_ENDPOINT_CONFIGFS=y --CONFIG_PCI_EPF_TEST=m -+CONFIG_PCI_EPF_TEST=y - CONFIG_DEVTMPFS=y - CONFIG_DEVTMPFS_MOUNT=y - CONFIG_FW_LOADER_USER_HELPER=y - CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y - CONFIG_HISILICON_LPC=y - CONFIG_SIMPLE_PM_BUS=y --CONFIG_FSL_MC_BUS=y - CONFIG_TEGRA_ACONNECT=m -+CONFIG_FSL_MC_UAPI_SUPPORT=y -+CONFIG_FSL_RCPM=y - CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y - CONFIG_MTD_BLOCK=y - CONFIG_MTD_CFI=y - CONFIG_MTD_CFI_ADV_OPTIONS=y -@@ -255,15 +273,20 @@ CONFIG_MTD_RAW_NAND=y - CONFIG_MTD_NAND_DENALI_DT=y - CONFIG_MTD_NAND_MARVELL=y - CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_NAND_GPMI_NAND=y - CONFIG_MTD_NAND_QCOM=y - CONFIG_MTD_SPI_NOR=y --CONFIG_SPI_CADENCE_QUADSPI=y -+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -+CONFIG_MTD_UBI=y - CONFIG_BLK_DEV_LOOP=y - CONFIG_BLK_DEV_NBD=m -+CONFIG_XEN_BLKDEV_BACKEND=m - CONFIG_VIRTIO_BLK=y --CONFIG_BLK_DEV_NVME=m -+CONFIG_BLK_DEV_NVME=y -+CONFIG_SENSORS_FXOS8700=y -+CONFIG_SENSORS_FXAS2100X=y - CONFIG_SRAM=y --CONFIG_PCI_ENDPOINT_TEST=m -+CONFIG_PCI_ENDPOINT_TEST=y - CONFIG_EEPROM_AT24=m - CONFIG_EEPROM_AT25=m - CONFIG_UACCE=m -@@ -281,6 +304,7 @@ CONFIG_SCSI_UFS_HISI=y - CONFIG_ATA=y - CONFIG_SATA_AHCI=y - CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y - CONFIG_AHCI_CEVA=y - CONFIG_AHCI_MVEBU=y - CONFIG_AHCI_XGENE=y -@@ -315,6 +339,8 @@ CONFIG_FSL_DPAA2_ETH=y - CONFIG_FSL_ENETC=y - CONFIG_FSL_ENETC_VF=y - CONFIG_FSL_ENETC_QOS=y -+CONFIG_FSL_ENETC_MDIO=y -+CONFIG_ENETC_TSN=y - CONFIG_HIX5HD2_GMAC=y - CONFIG_HNS_DSAF=y - CONFIG_HNS_ENET=y -@@ -331,6 +357,7 @@ CONFIG_SKY2=y - CONFIG_MLX4_EN=m - CONFIG_MLX5_CORE=m - CONFIG_MLX5_CORE_EN=y -+CONFIG_MSCC_OCELOT_SWITCH=y - CONFIG_QCOM_EMAC=m - CONFIG_RMNET=m - CONFIG_SH_ETH=y -@@ -342,18 +369,20 @@ CONFIG_SNI_NETSEC=y - CONFIG_STMMAC_ETH=m - CONFIG_TI_K3_AM65_CPSW_NUSS=y - CONFIG_QCOM_IPA=m --CONFIG_MDIO_BUS_MUX_MMIOREG=y --CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_MESON_GXL_PHY=m - CONFIG_AQUANTIA_PHY=y -+CONFIG_INPHI_PHY=y - CONFIG_MARVELL_PHY=m - CONFIG_MARVELL_10G_PHY=m --CONFIG_MESON_GXL_PHY=m - CONFIG_MICREL_PHY=y - CONFIG_MICROSEMI_PHY=y - CONFIG_AT803X_PHY=y --CONFIG_REALTEK_PHY=m -+CONFIG_NXP_TJA11XX_PHY=y -+CONFIG_REALTEK_PHY=y - CONFIG_ROCKCHIP_PHY=y - CONFIG_VITESSE_PHY=y -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_MDIO_BUS_MUX_MMIOREG=y - CONFIG_USB_PEGASUS=m - CONFIG_USB_RTL8150=m - CONFIG_USB_RTL8152=m -@@ -365,26 +394,28 @@ CONFIG_USB_NET_SMSC75XX=m - CONFIG_USB_NET_SMSC95XX=m - CONFIG_USB_NET_PLUSB=m - CONFIG_USB_NET_MCS7830=m --CONFIG_ATH10K=m --CONFIG_ATH10K_PCI=m --CONFIG_ATH10K_SNOC=m - CONFIG_BRCMFMAC=m --CONFIG_MWIFIEX=m --CONFIG_MWIFIEX_PCIE=m -+CONFIG_BRCMFMAC_PCIE=y -+CONFIG_HOSTAP=y - CONFIG_WL18XX=m - CONFIG_WLCORE_SDIO=m -+CONFIG_IVSHMEM_NET=y - CONFIG_INPUT_EVDEV=y - CONFIG_KEYBOARD_ADC=m - CONFIG_KEYBOARD_GPIO=y --CONFIG_KEYBOARD_SNVS_PWRKEY=m --CONFIG_KEYBOARD_IMX_SC_KEY=m -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y - CONFIG_KEYBOARD_CROS_EC=y - CONFIG_INPUT_TOUCHSCREEN=y - CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_GOODIX=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m - CONFIG_INPUT_MISC=y - CONFIG_INPUT_PM8941_PWRKEY=y - CONFIG_INPUT_PM8XXX_VIBRATOR=m - CONFIG_INPUT_HISI_POWERKEY=y -+CONFIG_INPUT_MPL3115=y -+CONFIG_INPUT_ISL29023=y - # CONFIG_SERIO_SERPORT is not set - CONFIG_SERIO_AMBAKMI=y - CONFIG_LEGACY_PTY_COUNT=16 -@@ -444,6 +475,7 @@ CONFIG_I2C_QCOM_CCI=m - CONFIG_I2C_QCOM_GENI=m - CONFIG_I2C_QUP=y - CONFIG_I2C_RK3X=y -+CONFIG_I2C_RPBUS=y - CONFIG_I2C_SH_MOBILE=y - CONFIG_I2C_TEGRA=y - CONFIG_I2C_UNIPHIER_F=y -@@ -453,10 +485,11 @@ CONFIG_SPI=y - CONFIG_SPI_ARMADA_3700=y - CONFIG_SPI_BCM2835=m - CONFIG_SPI_BCM2835AUX=m -+CONFIG_SPI_CADENCE_QUADSPI=y - CONFIG_SPI_FSL_LPSPI=y - CONFIG_SPI_FSL_QUADSPI=y - CONFIG_SPI_NXP_FLEXSPI=y --CONFIG_SPI_IMX=m -+CONFIG_SPI_IMX=y - CONFIG_SPI_FSL_DSPI=y - CONFIG_SPI_MESON_SPICC=m - CONFIG_SPI_MESON_SPIFC=m -@@ -470,7 +503,10 @@ CONFIG_SPI_QCOM_GENI=m - CONFIG_SPI_S3C64XX=y - CONFIG_SPI_SH_MSIOF=m - CONFIG_SPI_SUN6I=y --CONFIG_SPI_SPIDEV=m -+CONFIG_SPI_SPIDEV=y -+CONFIG_SPI_SLAVE=y -+CONFIG_SPI_SLAVE_TIME=y -+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y - CONFIG_SPMI=y - CONFIG_PINCTRL_SINGLE=y - CONFIG_PINCTRL_MAX77620=y -@@ -481,11 +517,13 @@ CONFIG_PINCTRL_IMX8MM=y - CONFIG_PINCTRL_IMX8MN=y - CONFIG_PINCTRL_IMX8MP=y - CONFIG_PINCTRL_IMX8MQ=y -+CONFIG_PINCTRL_IMX8QM=y - CONFIG_PINCTRL_IMX8QXP=y - CONFIG_PINCTRL_IMX8DXL=y - CONFIG_PINCTRL_IPQ8074=y - CONFIG_PINCTRL_IPQ6018=y - CONFIG_PINCTRL_MSM8916=y -+CONFIG_PINCTRL_S32V234=y - CONFIG_PINCTRL_MSM8994=y - CONFIG_PINCTRL_MSM8996=y - CONFIG_PINCTRL_MSM8998=y -@@ -497,6 +535,7 @@ CONFIG_PINCTRL_SDM845=y - CONFIG_PINCTRL_SM8150=y - CONFIG_PINCTRL_SM8250=y - CONFIG_GPIO_ALTERA=m -+CONFIG_GPIO_SYSFS=y - CONFIG_GPIO_DWAPB=y - CONFIG_GPIO_MB86S7X=y - CONFIG_GPIO_MPC8XXX=y -@@ -529,13 +568,15 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=m - CONFIG_SENSORS_SL28CPLD=m - CONFIG_SENSORS_INA2XX=m - CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_WRITABLE_TRIPS=y - CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y - CONFIG_CPU_THERMAL=y - CONFIG_THERMAL_EMULATION=y --CONFIG_QORIQ_THERMAL=m -+CONFIG_IMX_SC_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_IMX8MM_THERMAL=y -+CONFIG_QORIQ_THERMAL=y - CONFIG_SUN8I_THERMAL=y --CONFIG_IMX_SC_THERMAL=m --CONFIG_IMX8MM_THERMAL=m - CONFIG_ROCKCHIP_THERMAL=m - CONFIG_RCAR_THERMAL=y - CONFIG_RCAR_GEN3_THERMAL=y -@@ -552,15 +593,15 @@ CONFIG_WATCHDOG=y - CONFIG_SL28CPLD_WATCHDOG=m - CONFIG_ARM_SP805_WATCHDOG=y - CONFIG_ARM_SBSA_WATCHDOG=y --CONFIG_ARM_SMC_WATCHDOG=y - CONFIG_S3C2410_WATCHDOG=y - CONFIG_DW_WATCHDOG=y - CONFIG_SUNXI_WATCHDOG=m - CONFIG_IMX2_WDT=y --CONFIG_IMX_SC_WDT=m -+CONFIG_IMX_SC_WDT=y - CONFIG_QCOM_WDT=m - CONFIG_MESON_GXBB_WATCHDOG=m - CONFIG_MESON_WATCHDOG=m -+CONFIG_ARM_SMC_WATCHDOG=y - CONFIG_RENESAS_WDT=y - CONFIG_UNIPHIER_WATCHDOG=y - CONFIG_BCM2835_WDT=y -@@ -571,6 +612,7 @@ CONFIG_MFD_AXP20X_RSB=y - CONFIG_MFD_EXYNOS_LPASS=m - CONFIG_MFD_HI6421_PMIC=y - CONFIG_MFD_HI655X_PMIC=y -+CONFIG_MFD_IMX_MIX=y - CONFIG_MFD_MAX77620=y - CONFIG_MFD_SPMI_PMIC=y - CONFIG_MFD_RK808=y -@@ -599,23 +641,39 @@ CONFIG_REGULATOR_S2MPS11=y - CONFIG_REGULATOR_VCTRL=m - CONFIG_RC_CORE=m - CONFIG_RC_DECODERS=y -+CONFIG_IR_NEC_DECODER=m -+CONFIG_IR_RC5_DECODER=m -+CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m -+CONFIG_IR_SANYO_DECODER=m -+CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m -+CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m -+CONFIG_IR_RCMM_DECODER=m - CONFIG_RC_DEVICES=y -+CONFIG_IR_GPIO_CIR=m - CONFIG_IR_MESON=m - CONFIG_IR_SUNXI=m --CONFIG_MEDIA_SUPPORT=m -+CONFIG_MEDIA_SUPPORT=y - CONFIG_MEDIA_CAMERA_SUPPORT=y - CONFIG_MEDIA_ANALOG_TV_SUPPORT=y - CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y - CONFIG_MEDIA_SDR_SUPPORT=y --CONFIG_MEDIA_CONTROLLER=y --CONFIG_VIDEO_V4L2_SUBDEV_API=y - CONFIG_MEDIA_PLATFORM_SUPPORT=y - # CONFIG_DVB_NET is not set - CONFIG_MEDIA_USB_SUPPORT=y - CONFIG_USB_VIDEO_CLASS=m - CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_QCOM_CAMSS=m - CONFIG_VIDEO_RCAR_CSI2=m - CONFIG_VIDEO_RCAR_VIN=m -+CONFIG_VIDEO_MX8_CAPTURE=y -+CONFIG_VIDEO_MXC_CAPTURE=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=y -+CONFIG_MXC_MIPI_CSI=y -+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y - CONFIG_VIDEO_SUN6I_CSI=m - CONFIG_V4L_MEM2MEM_DRIVERS=y - CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -@@ -628,8 +686,11 @@ CONFIG_SDR_PLATFORM_DRIVERS=y - CONFIG_VIDEO_RCAR_DRIF=m - CONFIG_VIDEO_IMX219=m - CONFIG_VIDEO_OV5645=m --CONFIG_VIDEO_QCOM_CAMSS=m --CONFIG_DRM=m -+CONFIG_VIDEO_OV5640=y -+CONFIG_IMX_DPU_CORE=y -+CONFIG_IMX_LCDIF_CORE=y -+CONFIG_IMX_LCDIFV3_CORE=y -+CONFIG_DRM=y - CONFIG_DRM_I2C_NXP_TDA998X=m - CONFIG_DRM_MALI_DISPLAY=m - CONFIG_DRM_NOUVEAU=m -@@ -653,37 +714,56 @@ CONFIG_DRM_SUN6I_DSI=m - CONFIG_DRM_SUN8I_DW_HDMI=m - CONFIG_DRM_SUN8I_MIXER=m - CONFIG_DRM_MSM=m --CONFIG_DRM_TEGRA=m - CONFIG_DRM_PANEL_LVDS=m --CONFIG_DRM_PANEL_SIMPLE=m -+CONFIG_DRM_PANEL_SIMPLE=y - CONFIG_DRM_PANEL_RAYDIUM_RM67191=m - CONFIG_DRM_PANEL_SITRONIX_ST7703=m - CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m - CONFIG_DRM_DISPLAY_CONNECTOR=m --CONFIG_DRM_NWL_MIPI_DSI=m - CONFIG_DRM_LONTIUM_LT9611=m -+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y -+CONFIG_DRM_PANEL_SEIKO_43WVF1G=y -+CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y -+CONFIG_DRM_PANEL_WKS_101WX001=y -+CONFIG_DRM_NXP_SEIKO_43WVFIG=y - CONFIG_DRM_SII902X=m - CONFIG_DRM_SIMPLE_BRIDGE=m - CONFIG_DRM_THINE_THC63LVD1024=m - CONFIG_DRM_TI_SN65DSI86=m --CONFIG_DRM_I2C_ADV7511=m -+CONFIG_DRM_I2C_ADV7511=y - CONFIG_DRM_I2C_ADV7511_AUDIO=y - CONFIG_DRM_DW_HDMI_AHB_AUDIO=m --CONFIG_DRM_DW_HDMI_CEC=m -+CONFIG_DRM_DW_HDMI_GP_AUDIO=y -+CONFIG_DRM_DW_HDMI_CEC=y -+CONFIG_DRM_NWL_MIPI_DSI=y -+CONFIG_DRM_CDNS_HDMI_CEC=y -+CONFIG_DRM_ITE_IT6263=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_TVE=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX8QM_LDB=y -+CONFIG_DRM_IMX8QXP_LDB=y -+CONFIG_DRM_IMX8MP_LDB=y -+CONFIG_DRM_IMX_HDMI=y -+CONFIG_DRM_IMX_SEC_DSIM=y -+CONFIG_DRM_IMX_CDNS_MHDP=y -+CONFIG_DRM_IMX_DCSS=y - CONFIG_DRM_VC4=m - CONFIG_DRM_ETNAVIV=m - CONFIG_DRM_HISI_HIBMC=m - CONFIG_DRM_HISI_KIRIN=m --CONFIG_DRM_MXSFB=m -+CONFIG_DRM_MXSFB=y - CONFIG_DRM_MESON=m - CONFIG_DRM_PL111=m - CONFIG_DRM_LIMA=m - CONFIG_DRM_PANFROST=m - CONFIG_FB=y - CONFIG_FB_MODE_HELPERS=y -+CONFIG_FB_ARMCLCD=y - CONFIG_FB_EFI=y --CONFIG_BACKLIGHT_GENERIC=m --CONFIG_BACKLIGHT_PWM=m -+CONFIG_BACKLIGHT_PWM=y - CONFIG_BACKLIGHT_LP855X=m - CONFIG_LOGO=y - # CONFIG_LOGO_LINUX_MONO is not set -@@ -692,9 +772,29 @@ CONFIG_SOUND=y - CONFIG_SND=y - CONFIG_SND_HDA_TEGRA=m - CONFIG_SND_HDA_CODEC_HDMI=m -+CONFIG_SND_USB_AUDIO=m - CONFIG_SND_SOC=y - CONFIG_SND_BCM2835_SOC_I2S=m - CONFIG_SND_SOC_FSL_SAI=m -+CONFIG_SND_SOC_FSL_ASRC=y -+CONFIG_SND_SOC_FSL_EASRC=y -+CONFIG_SND_SOC_FSL_ESAI_CLIENT=y -+CONFIG_SND_SOC_FSL_DAI=m -+CONFIG_SND_SOC_FSL_MQS=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_AK4458=y -+CONFIG_SND_SOC_IMX_AK5558=y -+CONFIG_SND_SOC_IMX_AK4497=y -+CONFIG_SND_SOC_FSL_ASOC_CARD=y -+CONFIG_SND_SOC_IMX_MICFIL=y -+CONFIG_SND_SOC_IMX_RPMSG=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_AUDMIX=y -+CONFIG_SND_SOC_IMX_PDM_MIC=y -+CONFIG_SND_SOC_IMX_DSP=y -+CONFIG_SND_SOC_IMX_CDNHDMI=y -+CONFIG_SND_SOC_IMX_XCVR=y -+CONFIG_SND_SOC_IMX_PCM512X=y - CONFIG_SND_MESON_AXG_SOUND_CARD=m - CONFIG_SND_MESON_GX_SOUND_CARD=m - CONFIG_SND_SOC_QCOM=m -@@ -707,6 +807,11 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m - CONFIG_SND_SOC_RK3399_GRU_SOUND=m - CONFIG_SND_SOC_SAMSUNG=y - CONFIG_SND_SOC_RCAR=m -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=m -+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y -+CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=y - CONFIG_SND_SUN4I_SPDIF=m - CONFIG_SND_SOC_TEGRA=m - CONFIG_SND_SOC_TEGRA210_AHUB=m -@@ -714,19 +819,24 @@ CONFIG_SND_SOC_TEGRA210_DMIC=m - CONFIG_SND_SOC_TEGRA210_I2S=m - CONFIG_SND_SOC_TEGRA186_DSPK=m - CONFIG_SND_SOC_TEGRA210_ADMAIF=m -+CONFIG_SND_SOC_CS42XX8=y -+CONFIG_SND_SOC_CS42XX8_I2C=y - CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_BT_SCO=y - CONFIG_SND_SOC_ES7134=m - CONFIG_SND_SOC_ES7241=m - CONFIG_SND_SOC_PCM3168A_I2C=m - CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -+CONFIG_SND_SOC_SGTL5000=m - CONFIG_SND_SOC_TAS571X=m - CONFIG_SND_SOC_WCD934X=m -+CONFIG_SND_SOC_WM8524=y - CONFIG_SND_SOC_WM8904=m -+CONFIG_SND_SOC_WM8960=y - CONFIG_SND_SOC_WSA881X=m --CONFIG_SND_SIMPLE_CARD=m --CONFIG_SND_AUDIO_GRAPH_CARD=m -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_SND_AUDIO_GRAPH_CARD=y - CONFIG_I2C_HID=m --CONFIG_USB_CONN_GPIO=m - CONFIG_USB=y - CONFIG_USB_OTG=y - CONFIG_USB_XHCI_HCD=y -@@ -741,6 +851,11 @@ CONFIG_USB_RENESAS_USBHS_HCD=m - CONFIG_USB_RENESAS_USBHS=m - CONFIG_USB_ACM=m - CONFIG_USB_STORAGE=y -+CONFIG_USB_UAS=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_USB_CDNS3_IMX=y - CONFIG_USB_MUSB_HDRC=y - CONFIG_USB_MUSB_SUNXI=y - CONFIG_USB_DWC3=y -@@ -751,8 +866,11 @@ CONFIG_USB_CHIPIDEA_HOST=y - CONFIG_USB_ISP1760=y - CONFIG_USB_SERIAL=m - CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_TEST=m -+CONFIG_USB_EHSET_TEST_FIXTURE=m - CONFIG_USB_HSIC_USB3503=y - CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y - CONFIG_USB_GADGET=y - CONFIG_USB_RENESAS_USBHS_UDC=m - CONFIG_USB_RENESAS_USB3=m -@@ -767,9 +885,23 @@ CONFIG_USB_CONFIGFS_ECM_SUBSET=y - CONFIG_USB_CONFIGFS_RNDIS=y - CONFIG_USB_CONFIGFS_EEM=y - CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y - CONFIG_USB_CONFIGFS_F_FS=y --CONFIG_TYPEC=m --CONFIG_TYPEC_TCPM=m -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_SWITCH_GPIO=y - CONFIG_TYPEC_FUSB302=m - CONFIG_TYPEC_HD3SS3220=m - CONFIG_MMC=y -@@ -812,6 +944,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y - CONFIG_LEDS_TRIGGER_PANIC=y - CONFIG_EDAC=y - CONFIG_EDAC_GHES=y -+CONFIG_EDAC_SYNOPSYS=y - CONFIG_RTC_CLASS=y - CONFIG_RTC_DRV_DS1307=m - CONFIG_RTC_DRV_MAX77686=y -@@ -830,18 +963,22 @@ CONFIG_RTC_DRV_SUN6I=y - CONFIG_RTC_DRV_ARMADA38X=y - CONFIG_RTC_DRV_PM8XXX=m - CONFIG_RTC_DRV_TEGRA=y --CONFIG_RTC_DRV_SNVS=m --CONFIG_RTC_DRV_IMX_SC=m -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_IMX_SC=y - CONFIG_RTC_DRV_XGENE=y -+CONFIG_RTC_DRV_FSL_FTM_ALARM=y - CONFIG_DMADEVICES=y - CONFIG_DMA_BCM2835=y - CONFIG_DMA_SUN6I=m - CONFIG_FSL_EDMA=y -+CONFIG_FSL_QDMA=m -+CONFIG_FSL_EDMA_V3=y - CONFIG_IMX_SDMA=y - CONFIG_K3_DMA=y - CONFIG_MV_XOR=y - CONFIG_MV_XOR_V2=y - CONFIG_OWL_DMA=y -+CONFIG_MXS_DMA=y - CONFIG_PL330_DMA=y - CONFIG_TEGRA20_APB_DMA=y - CONFIG_TEGRA210_ADMA=m -@@ -850,16 +987,31 @@ CONFIG_QCOM_HIDMA_MGMT=y - CONFIG_QCOM_HIDMA=y - CONFIG_RCAR_DMAC=y - CONFIG_RENESAS_USB_DMAC=m -+CONFIG_FSL_DPAA2_QDMA=m - CONFIG_TI_K3_UDMA=y - CONFIG_TI_K3_UDMA_GLUE_LAYER=y -+CONFIG_DMATEST=y -+CONFIG_UIO=y -+CONFIG_UIO_PCI_GENERIC=y - CONFIG_VFIO=y - CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y - CONFIG_VIRTIO_PCI=y - CONFIG_VIRTIO_BALLOON=y - CONFIG_VIRTIO_MMIO=y - CONFIG_XEN_GNTDEV=y - CONFIG_XEN_GRANT_DEV_ALLOC=y --CONFIG_MFD_CROS_EC_DEV=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_IMX_CAPTURE=y -+CONFIG_ION=y -+CONFIG_ION_SYSTEM_HEAP=y -+CONFIG_ION_CMA_HEAP=y -+CONFIG_FSL_DPAA2=y -+CONFIG_FSL_DPAA2_ETHSW=y -+CONFIG_FSL_DPAA2_MAC=y -+CONFIG_FSL_PPFE=y -+CONFIG_FSL_PPFE_UTIL_DISABLED=y - CONFIG_CHROME_PLATFORMS=y - CONFIG_CROS_EC=y - CONFIG_CROS_EC_I2C=y -@@ -872,7 +1024,6 @@ CONFIG_COMMON_CLK_FSL_SAI=y - CONFIG_COMMON_CLK_S2MPS11=y - CONFIG_COMMON_CLK_PWM=y - CONFIG_COMMON_CLK_VC5=y --CONFIG_COMMON_CLK_BD718XX=m - CONFIG_CLK_RASPBERRYPI=m - CONFIG_CLK_IMX8MM=y - CONFIG_CLK_IMX8MN=y -@@ -885,8 +1036,8 @@ CONFIG_QCOM_A53PLL=y - CONFIG_QCOM_CLK_APCS_MSM8916=y - CONFIG_QCOM_CLK_SMD_RPM=y - CONFIG_QCOM_CLK_RPMH=y --CONFIG_IPQ_GCC_8074=y - CONFIG_IPQ_GCC_6018=y -+CONFIG_IPQ_GCC_8074=y - CONFIG_MSM_GCC_8916=y - CONFIG_MSM_GCC_8994=y - CONFIG_MSM_MMCC_8996=y -@@ -894,12 +1045,9 @@ CONFIG_MSM_GCC_8998=y - CONFIG_QCS_GCC_404=y - CONFIG_SC_GCC_7180=y - CONFIG_SDM_CAMCC_845=m --CONFIG_SDM_GCC_845=y - CONFIG_SDM_GPUCC_845=y - CONFIG_SDM_VIDEOCC_845=y - CONFIG_SDM_DISPCC_845=y --CONFIG_SM_GCC_8150=y --CONFIG_SM_GCC_8250=y - CONFIG_SM_GPUCC_8150=y - CONFIG_SM_GPUCC_8250=y - CONFIG_QCOM_HFPLL=y -@@ -929,6 +1077,7 @@ CONFIG_OWL_PM_DOMAINS=y - CONFIG_RASPBERRYPI_POWER=y - CONFIG_FSL_DPAA=y - CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_QIXIS=y - CONFIG_QCOM_AOSS_QMP=y - CONFIG_QCOM_GENI_SE=y - CONFIG_QCOM_RMTFS_MEM=m -@@ -941,19 +1090,19 @@ CONFIG_QCOM_SMP2P=y - CONFIG_QCOM_SMSM=y - CONFIG_QCOM_SOCINFO=m - CONFIG_QCOM_APR=m --CONFIG_ARCH_R8A774A1=y --CONFIG_ARCH_R8A774B1=y --CONFIG_ARCH_R8A774C0=y --CONFIG_ARCH_R8A774E1=y -+CONFIG_ARCH_R8A77995=y -+CONFIG_ARCH_R8A77990=y - CONFIG_ARCH_R8A77950=y - CONFIG_ARCH_R8A77951=y -+CONFIG_ARCH_R8A77965=y - CONFIG_ARCH_R8A77960=y - CONFIG_ARCH_R8A77961=y --CONFIG_ARCH_R8A77965=y --CONFIG_ARCH_R8A77970=y - CONFIG_ARCH_R8A77980=y --CONFIG_ARCH_R8A77990=y --CONFIG_ARCH_R8A77995=y -+CONFIG_ARCH_R8A77970=y -+CONFIG_ARCH_R8A774C0=y -+CONFIG_ARCH_R8A774E1=y -+CONFIG_ARCH_R8A774A1=y -+CONFIG_ARCH_R8A774B1=y - CONFIG_ROCKCHIP_PM_DOMAINS=y - CONFIG_ARCH_TEGRA_132_SOC=y - CONFIG_ARCH_TEGRA_210_SOC=y -@@ -970,16 +1119,17 @@ CONFIG_IIO=y - CONFIG_EXYNOS_ADC=y - CONFIG_MAX9611=m - CONFIG_QCOM_SPMI_ADC5=m -+CONFIG_IMX8QXP_ADC=y - CONFIG_ROCKCHIP_SARADC=m - CONFIG_IIO_CROS_EC_SENSORS_CORE=m - CONFIG_IIO_CROS_EC_SENSORS=m - CONFIG_IIO_CROS_EC_LIGHT_PROX=m --CONFIG_SENSORS_ISL29018=m - CONFIG_IIO_CROS_EC_BARO=m --CONFIG_MPL3115=m - CONFIG_PWM=y - CONFIG_PWM_BCM2835=m - CONFIG_PWM_CROS_EC=m -+CONFIG_PWM_FSL_FTM=m -+CONFIG_PWM_IMX27=y - CONFIG_PWM_MESON=m - CONFIG_PWM_RCAR=m - CONFIG_PWM_ROCKCHIP=y -@@ -993,9 +1143,14 @@ CONFIG_RESET_IMX7=y - CONFIG_RESET_QCOM_AOSS=y - CONFIG_RESET_QCOM_PDC=m - CONFIG_RESET_TI_SCI=y -+CONFIG_PHY_CADENCE_SALVO=y - CONFIG_PHY_XGENE=y -+CONFIG_PHY_MIXEL_LVDS=y -+CONFIG_PHY_MIXEL_LVDS_COMBO=y - CONFIG_PHY_SUN4I_USB=y --CONFIG_PHY_MIXEL_MIPI_DPHY=m -+CONFIG_PHY_MIXEL_MIPI_DPHY=y -+CONFIG_PHY_FSL_IMX8MP_LVDS=y -+CONFIG_PHY_SAMSUNG_HDMI_PHY=y - CONFIG_PHY_HI6220_USB=y - CONFIG_PHY_HISTB_COMBPHY=y - CONFIG_PHY_HISI_INNO_USB2=y -@@ -1016,10 +1171,10 @@ CONFIG_PHY_UNIPHIER_USB2=y - CONFIG_PHY_UNIPHIER_USB3=y - CONFIG_PHY_TEGRA_XUSB=y - CONFIG_ARM_SMMU_V3_PMU=m --CONFIG_FSL_IMX8_DDR_PMU=m --CONFIG_HISI_PMU=y -+CONFIG_FSL_IMX8_DDR_PMU=y - CONFIG_QCOM_L2_PMU=y - CONFIG_QCOM_L3_PMU=y -+CONFIG_HISI_PMU=y - CONFIG_NVMEM_IMX_OCOTP=y - CONFIG_NVMEM_IMX_OCOTP_SCU=y - CONFIG_QCOM_QFPROM=y -@@ -1035,10 +1190,11 @@ CONFIG_FPGA_REGION=m - CONFIG_OF_FPGA_REGION=m - CONFIG_TEE=y - CONFIG_OPTEE=y --CONFIG_SLIMBUS=m -+CONFIG_MUX_MMIO=y - CONFIG_SLIM_QCOM_CTRL=m - CONFIG_SLIM_QCOM_NGD_CTRL=m --CONFIG_MUX_MMIO=y -+CONFIG_MXC_SIM=y -+CONFIG_MXC_EMVSIM=y - CONFIG_INTERCONNECT=y - CONFIG_INTERCONNECT_QCOM=y - CONFIG_INTERCONNECT_QCOM_MSM8916=m -@@ -1059,8 +1215,9 @@ CONFIG_CUSE=m - CONFIG_OVERLAY_FS=m - CONFIG_VFAT_FS=y - CONFIG_HUGETLBFS=y --CONFIG_CONFIGFS_FS=y - CONFIG_EFIVAR_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y - CONFIG_SQUASHFS=y - CONFIG_NFS_FS=y - CONFIG_NFS_V4=y -@@ -1071,11 +1228,15 @@ CONFIG_9P_FS=y - CONFIG_NLS_CODEPAGE_437=y - CONFIG_NLS_ISO8859_1=y - CONFIG_SECURITY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m - CONFIG_CRYPTO_ECHAINIV=y - CONFIG_CRYPTO_ANSI_CPRNG=y - CONFIG_CRYPTO_USER_API_RNG=m - CONFIG_CRYPTO_DEV_SUN8I_CE=m - CONFIG_CRYPTO_DEV_FSL_CAAM=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m - CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m - CONFIG_CRYPTO_DEV_QCOM_RNG=m - CONFIG_CRYPTO_DEV_CCREE=m -@@ -1092,3 +1253,15 @@ CONFIG_DEBUG_KERNEL=y - # CONFIG_DEBUG_PREEMPT is not set - # CONFIG_FTRACE is not set - CONFIG_MEMTEST=y -+CONFIG_CORESIGHT=y -+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -+CONFIG_CORESIGHT_SOURCE_ETM4X=y -+CONFIG_IMX8_MEDIA_DEVICE=m -+CONFIG_IMX8_ISI_HW=y -+CONFIG_IMX8_ISI_CORE=y -+CONFIG_IMX8_ISI_CAPTURE=y -+CONFIG_IMX8_ISI_M2M=y -+CONFIG_IMX8_MIPI_CSI2=y -+CONFIG_IMX8_MIPI_CSI2_SAM=y -+CONFIG_IMX8_PARALLEL_CSI=y -+CONFIG_GMSL_MAX9286=y -diff --git a/arch/arm64/configs/imx.config b/arch/arm64/configs/imx.config -new file mode 100644 -index 000000000..4c3f869d8 ---- /dev/null -+++ b/arch/arm64/configs/imx.config -@@ -0,0 +1,118 @@ -+# imx specific options -+# -+# required by GPU -+CONFIG_FORCE_MAX_ZONEORDER=14 -+ -+# disable other ARCH -+CONFIG_ARCH_AGILEX=n -+CONFIG_ARCH_SUNXI=n -+CONFIG_ARCH_ALPINE=n -+CONFIG_ARCH_BCM2835=n -+CONFIG_ARCH_BCM_IPROC=n -+CONFIG_ARCH_BERLIN=n -+CONFIG_ARCH_BRCMSTB=n -+CONFIG_ARCH_EXYNOS=n -+CONFIG_ARCH_K3=n -+CONFIG_ARCH_LG1K=n -+CONFIG_ARCH_HISI=n -+CONFIG_ARCH_MEDIATEK=n -+CONFIG_ARCH_MESON=n -+CONFIG_ARCH_MVEBU=n -+CONFIG_ARCH_QCOM=n -+CONFIG_ARCH_RENESAS=n -+CONFIG_ARCH_ROCKCHIP=n -+CONFIG_ARCH_SEATTLE=n -+CONFIG_ARCH_STRATIX10=n -+CONFIG_ARCH_SYNQUACER=n -+CONFIG_ARCH_TEGRA=n -+CONFIG_ARCH_SPRD=n -+CONFIG_ARCH_THUNDER=n -+CONFIG_ARCH_THUNDER2=n -+CONFIG_ARCH_UNIPHIER=n -+CONFIG_ARCH_VEXPRESS=n -+CONFIG_ARCH_XGENE=n -+CONFIG_ARCH_ZX=n -+CONFIG_ARCH_ZYNQMP=n -+CONFIG_ARCH_ACTIONS=n -+CONFIG_ARCH_VISCONTI=n -+ -+# USB related -+CONFIG_USB_OTG_WHITELIST=y -+CONFIG_USB_HCD_TEST_MODE=y -+CONFIG_USB_EHSET_TEST_FIXTURE=y -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_CONSOLE=y -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_SIMPLE=y -+CONFIG_USB_SERIAL_FTDI_SIO=y -+ -+# networking related -+CONFIG_BRCMFMAC=n -+CONFIG_STMMAC_ETH=y -+CONFIG_STMMAC_PLATFORM=y -+CONFIG_DWMAC_IMX8=y -+CONFIG_FEC_UIO=y -+ -+# cpu-freq related -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+ -+#remoteproc -+CONFIG_IMX_REMOTEPROC=y -+ -+#xen -+CONFIG_XEN_NETDEV_BACKEND=m -+CONFIG_XEN_I2C_BACKEND=y -+CONFIG_XEN_WDT=y -+ -+#uio for jailhouse -+CONFIG_UIO_IVSHMEM=y -+CONFIG_VIRTIO_IVSHMEM=y -+ -+# crypto related -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_TLS=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=m -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_SHA3=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_ARC4=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_CFB=m -+CONFIG_CRYPTO_OFB=m -+CONFIG_CRYPTO_PCBC=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_VMAC=m -+CONFIG_CRYPTO_SM3=m -+CONFIG_CRYPTO_STREEBOG=m -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_DES=m -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_SALSA20=m -+CONFIG_CRYPTO_SEED=m -+CONFIG_CRYPTO_SM4=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_DM_CRYPT=m -+ -+# enable DMABUF heaps -+CONFIG_DMABUF_HEAPS=y -+CONFIG_DMABUF_HEAPS_SYSTEM=y -+CONFIG_DMABUF_HEAPS_CMA=y -diff --git a/arch/arm64/configs/imx8qm_cockpit.config b/arch/arm64/configs/imx8qm_cockpit.config -new file mode 100644 -index 000000000..a34f6b9d1 ---- /dev/null -+++ b/arch/arm64/configs/imx8qm_cockpit.config -@@ -0,0 +1,3 @@ -+CONFIG_IMX_SHMEM_NET=y -+CONFIG_GIC_GENTLE_CONFIG=y -+CONFIG_PANIC_TIMEOUT=-1 -diff --git a/arch/arm64/configs/imx_v8_defconfig b/arch/arm64/configs/imx_v8_defconfig -new file mode 100644 -index 000000000..775fd503b ---- /dev/null -+++ b/arch/arm64/configs/imx_v8_defconfig -@@ -0,0 +1,985 @@ -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_AUDIT=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_PREEMPT=y -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_NUMA_BALANCING=y -+CONFIG_MEMCG=y -+CONFIG_BLK_CGROUP=y -+CONFIG_CGROUP_PIDS=y -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_HUGETLB=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_PERF=y -+CONFIG_USER_NS=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_KALLSYMS_ALL=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_ARCH_LAYERSCAPE=y -+CONFIG_ARCH_MXC=y -+CONFIG_ARCH_S32=y -+CONFIG_SOC_S32V234=y -+CONFIG_ARM64_VA_BITS_48=y -+CONFIG_SCHED_MC=y -+CONFIG_SCHED_SMT=y -+CONFIG_NUMA=y -+CONFIG_KEXEC=y -+CONFIG_KEXEC_FILE=y -+CONFIG_CRASH_DUMP=y -+CONFIG_XEN=y -+CONFIG_FORCE_MAX_ZONEORDER=14 -+CONFIG_COMPAT=y -+CONFIG_RANDOMIZE_BASE=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_ENERGY_MODEL=y -+CONFIG_ARM_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+CONFIG_CPUFREQ_DT=y -+CONFIG_ACPI_CPPC_CPUFREQ=m -+CONFIG_ARM_SCPI_CPUFREQ=y -+CONFIG_ARM_IMX_CPUFREQ_DT=y -+CONFIG_QORIQ_CPUFREQ=y -+CONFIG_ARM_SCMI_PROTOCOL=y -+CONFIG_ARM_SCPI_PROTOCOL=y -+CONFIG_EFI_CAPSULE_LOADER=y -+CONFIG_IMX_DSP=y -+CONFIG_IMX_SCU=y -+CONFIG_IMX_SCU_PD=y -+CONFIG_ACPI=y -+CONFIG_ACPI_APEI=y -+CONFIG_ACPI_APEI_GHES=y -+CONFIG_ACPI_APEI_MEMORY_FAILURE=y -+CONFIG_ACPI_APEI_EINJ=y -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y -+CONFIG_ARM64_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+CONFIG_CRYPTO_SHA512_ARM64_CE=m -+CONFIG_CRYPTO_SHA3_ARM64=m -+CONFIG_CRYPTO_SM3_ARM64_CE=m -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -+CONFIG_CRYPTO_CHACHA20_NEON=m -+CONFIG_CRYPTO_AES_ARM64_BS=m -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_KSM=y -+CONFIG_MEMORY_FAILURE=y -+CONFIG_TRANSPARENT_HUGEPAGE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IPV6_SIT=m -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_NET_DSA=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC2=y -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_CBS=m -+CONFIG_NET_SCH_ETF=m -+CONFIG_NET_SCH_TAPRIO=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_FLOWER=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_GACT=m -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_GATE=m -+CONFIG_TSN=y -+CONFIG_QRTR=m -+CONFIG_QRTR_SMD=m -+CONFIG_QRTR_TUN=m -+CONFIG_BPF_JIT=y -+CONFIG_NET_PKTGEN=m -+CONFIG_CAN=m -+CONFIG_CAN_FLEXCAN=m -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+CONFIG_BT_LEDS=y -+# CONFIG_BT_DEBUGFS is not set -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y -+CONFIG_BT_HCIUART_BCM=y -+CONFIG_BT_HCIUART_QCA=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=y -+CONFIG_NL80211_TESTMODE=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y -+CONFIG_MAC80211_LEDS=y -+CONFIG_NET_9P=y -+CONFIG_NET_9P_VIRTIO=y -+CONFIG_NFC=m -+CONFIG_NFC_NCI=m -+CONFIG_NFC_S3FWRN5_I2C=m -+CONFIG_PCI=y -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCI_IOV=y -+CONFIG_PCI_PASID=y -+CONFIG_HOTPLUG_PCI=y -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCI_XGENE=y -+CONFIG_PCIE_ALTERA=y -+CONFIG_PCIE_ALTERA_MSI=y -+CONFIG_PCI_HOST_THUNDER_PEM=y -+CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCI_IMX6_HOST=y -+CONFIG_PCI_IMX6_EP=y -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_PCI_HISI=y -+CONFIG_PCIE_KIRIN=y -+CONFIG_PCI_MESON=m -+CONFIG_PCIE_LAYERSCAPE_GEN4=y -+CONFIG_PCI_ENDPOINT=y -+CONFIG_PCI_ENDPOINT_CONFIGFS=y -+CONFIG_PCI_EPF_TEST=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -+CONFIG_BRCMSTB_GISB_ARB=y -+CONFIG_SIMPLE_PM_BUS=y -+CONFIG_VEXPRESS_CONFIG=y -+CONFIG_FSL_MC_UAPI_SUPPORT=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_RAW_NAND=y -+CONFIG_MTD_NAND_DENALI_DT=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_SPI_NOR=y -+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_NBD=m -+CONFIG_XEN_BLKDEV_BACKEND=m -+CONFIG_VIRTIO_BLK=y -+CONFIG_BLK_DEV_NVME=y -+CONFIG_SENSORS_FXOS8700=y -+CONFIG_SENSORS_FXAS2100X=y -+CONFIG_SRAM=y -+CONFIG_PCI_ENDPOINT_TEST=y -+CONFIG_EEPROM_AT24=m -+CONFIG_EEPROM_AT25=m -+CONFIG_UACCE=m -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_HISI_SAS=y -+CONFIG_SCSI_HISI_SAS_PCI=y -+CONFIG_MEGARAID_SAS=y -+CONFIG_SCSI_MPT3SAS=m -+CONFIG_SCSI_UFSHCD=y -+CONFIG_SCSI_UFSHCD_PLATFORM=y -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_AHCI_CEVA=y -+CONFIG_AHCI_XGENE=y -+CONFIG_AHCI_QORIQ=y -+CONFIG_SATA_SIL24=y -+CONFIG_PATA_PLATFORM=y -+CONFIG_PATA_OF_PLATFORM=y -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_CRYPT=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_ZERO=m -+CONFIG_NETDEVICES=y -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_TUN=y -+CONFIG_VETH=m -+CONFIG_VIRTIO_NET=y -+CONFIG_NET_DSA_MSCC_FELIX=m -+CONFIG_AMD_XGBE=y -+CONFIG_ATL1C=m -+CONFIG_BCMGENET=m -+CONFIG_BNX2X=m -+CONFIG_MACB=y -+CONFIG_THUNDER_NIC_PF=y -+CONFIG_FEC=y -+CONFIG_FEC_UIO=y -+CONFIG_FSL_FMAN=y -+CONFIG_FSL_DPAA_ETH=y -+CONFIG_FSL_DPAA2_ETH=y -+CONFIG_FSL_DPAA2_MAC=y -+CONFIG_FSL_ENETC=y -+CONFIG_FSL_ENETC_VF=y -+CONFIG_FSL_ENETC_QOS=y -+CONFIG_ENETC_TSN=y -+CONFIG_HIX5HD2_GMAC=y -+CONFIG_HNS_DSAF=y -+CONFIG_HNS_ENET=y -+CONFIG_HNS3=y -+CONFIG_HNS3_HCLGE=y -+CONFIG_HNS3_ENET=y -+CONFIG_E1000=y -+CONFIG_E1000E=y -+CONFIG_IGB=y -+CONFIG_IGBVF=y -+CONFIG_MVMDIO=y -+CONFIG_SKY2=y -+CONFIG_MLX4_EN=m -+CONFIG_MLX5_CORE=m -+CONFIG_MLX5_CORE_EN=y -+CONFIG_MSCC_OCELOT_SWITCH=y -+CONFIG_QCOM_EMAC=m -+CONFIG_RMNET=m -+CONFIG_SMC91X=y -+CONFIG_SMSC911X=y -+CONFIG_STMMAC_ETH=y -+CONFIG_DWMAC_GENERIC=m -+CONFIG_AQUANTIA_PHY=y -+CONFIG_BROADCOM_PHY=m -+CONFIG_INPHI_PHY=y -+CONFIG_MARVELL_PHY=m -+CONFIG_MARVELL_10G_PHY=m -+CONFIG_MICREL_PHY=y -+CONFIG_MICROSEMI_PHY=y -+CONFIG_NXP_TJA11XX_PHY=y -+CONFIG_AT803X_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_ROCKCHIP_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_MDIO_BITBANG=y -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_MDIO_BUS_MUX_MMIOREG=y -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=y -+CONFIG_USB_LAN78XX=m -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_HOSTAP=y -+CONFIG_WL18XX=m -+CONFIG_WLCORE_SDIO=m -+CONFIG_XEN_NETDEV_BACKEND=m -+CONFIG_IVSHMEM_NET=y -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_ADC=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y -+CONFIG_KEYBOARD_RPMSG=y -+CONFIG_KEYBOARD_CROS_EC=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_GOODIX=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_MPL3115=y -+CONFIG_INPUT_ISL29023=y -+# CONFIG_SERIO_SERPORT is not set -+CONFIG_SERIO_AMBAKMI=y -+CONFIG_LEGACY_PTY_COUNT=16 -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DW=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_XILINX_PS_UART=y -+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_SERIAL_FSL_LINFLEXUART=y -+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -+CONFIG_SERIAL_DEV_BUS=y -+CONFIG_VIRTIO_CONSOLE=y -+CONFIG_IPMI_HANDLER=m -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_SI=m -+CONFIG_TCG_TPM=y -+CONFIG_TCG_TIS_I2C_INFINEON=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_DESIGNWARE_PLATFORM=y -+CONFIG_I2C_GPIO=m -+CONFIG_I2C_IMX=y -+CONFIG_I2C_IMX_LPI2C=y -+CONFIG_I2C_RK3X=y -+CONFIG_I2C_RPBUS=y -+CONFIG_I2C_CROS_EC_TUNNEL=y -+CONFIG_XEN_I2C_BACKEND=y -+CONFIG_I2C_SLAVE=y -+CONFIG_I3C=y -+CONFIG_SVC_I3C_MASTER=y -+CONFIG_SPI=y -+CONFIG_SPI_CADENCE_QUADSPI=y -+CONFIG_SPI_FSL_LPSPI=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_SPI_NXP_FLEXSPI=y -+CONFIG_SPI_IMX=y -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_SPI_PL022=y -+CONFIG_SPI_ROCKCHIP=y -+CONFIG_SPI_SPIDEV=y -+CONFIG_SPI_SLAVE=y -+CONFIG_SPI_SLAVE_TIME=y -+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y -+CONFIG_SPMI=y -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_PINCTRL_MAX77620=y -+CONFIG_PINCTRL_IMX8MM=y -+CONFIG_PINCTRL_IMX8MN=y -+CONFIG_PINCTRL_IMX8MP=y -+CONFIG_PINCTRL_IMX8MQ=y -+CONFIG_PINCTRL_IMX8QM=y -+CONFIG_PINCTRL_IMX8QXP=y -+CONFIG_PINCTRL_IMX8DXL=y -+CONFIG_PINCTRL_IMX8ULP=y -+CONFIG_PINCTRL_S32V234=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_ALTERA=m -+CONFIG_GPIO_DWAPB=y -+CONFIG_GPIO_IMX_RPMSG=y -+CONFIG_GPIO_MB86S7X=y -+CONFIG_GPIO_MPC8XXX=y -+CONFIG_GPIO_PL061=y -+CONFIG_GPIO_WCD934X=m -+CONFIG_GPIO_XGENE=y -+CONFIG_GPIO_MAX732X=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_BD9571MWV=m -+CONFIG_GPIO_MAX77620=y -+CONFIG_GPIO_SL28CPLD=m -+CONFIG_POWER_RESET_BRCMSTB=y -+CONFIG_POWER_RESET_XGENE=y -+CONFIG_POWER_RESET_SYSCON=y -+CONFIG_SYSCON_REBOOT_MODE=y -+CONFIG_BATTERY_SBS=m -+CONFIG_BATTERY_BQ27XXX=y -+CONFIG_SENSORS_ARM_SCMI=y -+CONFIG_SENSORS_ARM_SCPI=y -+CONFIG_SENSORS_FP9931=y -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_PWM_FAN=m -+CONFIG_SENSORS_SL28CPLD=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_WRITABLE_TRIPS=y -+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -+CONFIG_CPU_THERMAL=y -+CONFIG_THERMAL_EMULATION=y -+CONFIG_IMX_SC_THERMAL=y -+CONFIG_IMX8MM_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_QORIQ_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_SL28CPLD_WATCHDOG=m -+CONFIG_ARM_SP805_WATCHDOG=y -+CONFIG_ARM_SBSA_WATCHDOG=y -+CONFIG_DW_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_IMX_SC_WDT=y -+CONFIG_IMX7ULP_WDT=y -+CONFIG_ARM_SMC_WATCHDOG=y -+CONFIG_XEN_WDT=y -+CONFIG_MFD_BD9571MWV=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_MFD_IMX_MIX=y -+CONFIG_MFD_HI6421_PMIC=y -+CONFIG_MFD_FP9931=y -+CONFIG_MFD_MAX77620=y -+CONFIG_MFD_RK808=y -+CONFIG_MFD_SEC_CORE=y -+CONFIG_MFD_SL28CPLD=y -+CONFIG_MFD_ROHM_BD718XX=y -+CONFIG_MFD_WCD934X=m -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_AXP20X=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_BD9571MWV=y -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_REGULATOR_GPIO=y -+CONFIG_REGULATOR_HI6421V530=y -+CONFIG_REGULATOR_MAX77620=y -+CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_FP9931=y -+CONFIG_REGULATOR_PCA9450=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_QCOM_SPMI=y -+CONFIG_REGULATOR_RK808=y -+CONFIG_REGULATOR_S2MPS11=y -+CONFIG_REGULATOR_VCTRL=m -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_IR_NEC_DECODER=m -+CONFIG_IR_RC5_DECODER=m -+CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m -+CONFIG_IR_SANYO_DECODER=m -+CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m -+CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m -+CONFIG_IR_RCMM_DECODER=m -+CONFIG_RC_DEVICES=y -+CONFIG_IR_GPIO_CIR=m -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_SDR_SUPPORT=y -+CONFIG_MEDIA_PLATFORM_SUPPORT=y -+# CONFIG_DVB_NET is not set -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MXC_CAPTURE=y -+CONFIG_VIDEO_MX8_CAPTURE=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=y -+CONFIG_MXC_MIPI_CSI=y -+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_SDR_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_OV5640=y -+CONFIG_VIDEO_OV5645=m -+CONFIG_IMX_DPU_CORE=y -+CONFIG_IMX_LCDIF_CORE=y -+CONFIG_IMX_LCDIFV3_CORE=y -+CONFIG_DRM=y -+CONFIG_DRM_I2C_NXP_TDA998X=m -+CONFIG_DRM_MALI_DISPLAY=m -+CONFIG_DRM_NOUVEAU=m -+CONFIG_DRM_RCAR_DW_HDMI=m -+CONFIG_DRM_RCAR_LVDS=m -+CONFIG_DRM_PANEL_LVDS=m -+CONFIG_DRM_PANEL_SIMPLE=y -+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y -+CONFIG_DRM_PANEL_RAYDIUM_RM68200=y -+CONFIG_DRM_PANEL_SEIKO_43WVF1G=y -+CONFIG_DRM_PANEL_SITRONIX_ST7703=m -+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -+CONFIG_DRM_PANEL_WKS_101WX001=y -+CONFIG_DRM_DISPLAY_CONNECTOR=m -+CONFIG_DRM_LONTIUM_LT9611=m -+CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y -+CONFIG_DRM_NWL_MIPI_DSI=y -+CONFIG_DRM_NXP_SEIKO_43WVFIG=y -+CONFIG_DRM_SII902X=m -+CONFIG_DRM_SIMPLE_BRIDGE=m -+CONFIG_DRM_THINE_THC63LVD1024=m -+CONFIG_DRM_TI_SN65DSI86=m -+CONFIG_DRM_I2C_ADV7511=y -+CONFIG_DRM_I2C_ADV7511_AUDIO=y -+CONFIG_DRM_CDNS_HDMI_CEC=y -+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m -+CONFIG_DRM_DW_HDMI_GP_AUDIO=y -+CONFIG_DRM_DW_HDMI_CEC=y -+CONFIG_DRM_ITE_IT6263=y -+CONFIG_DRM_ITE_IT6161=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_TVE=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX8QM_LDB=y -+CONFIG_DRM_IMX8QXP_LDB=y -+CONFIG_DRM_IMX8MP_LDB=y -+CONFIG_DRM_IMX_HDMI=y -+CONFIG_DRM_IMX_SEC_DSIM=y -+CONFIG_DRM_IMX_DCNANO=y -+CONFIG_DRM_IMX_DCSS=y -+CONFIG_DRM_IMX_CDNS_MHDP=y -+CONFIG_DRM_ETNAVIV=m -+CONFIG_DRM_HISI_HIBMC=m -+CONFIG_DRM_HISI_KIRIN=m -+CONFIG_DRM_MXSFB=y -+CONFIG_DRM_PL111=m -+CONFIG_DRM_LIMA=m -+CONFIG_DRM_PANFROST=m -+CONFIG_FB_ARMCLCD=y -+CONFIG_FB_EFI=y -+CONFIG_FB_MXC_EINK_V2_PANEL=y -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_DYNAMIC_MINORS=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_SOC_FSL_ASRC=y -+CONFIG_SND_SOC_FSL_MQS=y -+CONFIG_SND_SOC_FSL_EASRC=y -+CONFIG_SND_SOC_FSL_ESAI_CLIENT=y -+CONFIG_SND_SOC_FSL_RPMSG=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_AK4458=y -+CONFIG_SND_SOC_IMX_AK5558=y -+CONFIG_SND_SOC_IMX_AK4497=y -+CONFIG_SND_SOC_IMX_MICFIL=y -+CONFIG_SND_SOC_IMX_RPMSG=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_FSL_ASOC_CARD=y -+CONFIG_SND_SOC_IMX_AUDMIX=y -+CONFIG_SND_SOC_IMX_XCVR=y -+CONFIG_SND_SOC_IMX_PCM512X=y -+CONFIG_SND_SOC_IMX_PDM_MIC=y -+CONFIG_SND_SOC_IMX_DSP=y -+CONFIG_SND_SOC_IMX_CDNHDMI=y -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=m -+CONFIG_SND_SOC_SOF_COMPRESS=y -+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y -+CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=y -+CONFIG_SND_SOC_SOF_IMX8ULP_SUPPORT=y -+CONFIG_SND_SOC_SOF_IMX8ULP=y -+CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_BT_SCO=y -+CONFIG_SND_SOC_CROS_EC_CODEC=m -+CONFIG_SND_SOC_CS42XX8_I2C=y -+CONFIG_SND_SOC_DMIC=m -+CONFIG_SND_SOC_ES7134=m -+CONFIG_SND_SOC_ES7241=m -+CONFIG_SND_SOC_MAX98357A=m -+CONFIG_SND_SOC_MAX98927=m -+CONFIG_SND_SOC_PCM3168A_I2C=m -+CONFIG_SND_SOC_SGTL5000=m -+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -+CONFIG_SND_SOC_SPDIF=m -+CONFIG_SND_SOC_TAS571X=m -+CONFIG_SND_SOC_WCD934X=m -+CONFIG_SND_SOC_WM8524=y -+CONFIG_SND_SOC_WM8904=m -+CONFIG_SND_SOC_WM8960=y -+CONFIG_SND_SOC_RPMSG_WM8960=y -+CONFIG_SND_SOC_RPMSG_WM8960_I2C=y -+CONFIG_SND_SOC_RPMSG_AK4497=y -+CONFIG_SND_SOC_WSA881X=m -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_SND_AUDIO_GRAPH_CARD=y -+CONFIG_SND_ALOOP=m -+CONFIG_I2C_HID=m -+CONFIG_USB_CONN_GPIO=y -+CONFIG_USB=y -+CONFIG_USB_OTG=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_HCD_TEST_MODE=y -+CONFIG_USB_ACM=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_UAS=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_ISP1760=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_CONSOLE=y -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_SIMPLE=y -+CONFIG_USB_SERIAL_FTDI_SIO=y -+CONFIG_USB_TEST=m -+CONFIG_USB_EHSET_TEST_FIXTURE=y -+CONFIG_USB_HSIC_USB3503=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_ULPI=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_SNP_UDC_PLAT=y -+CONFIG_USB_BDC_UDC=y -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_FUSB302=m -+CONFIG_TYPEC_HD3SS3220=m -+CONFIG_TYPEC_SWITCH_GPIO=y -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_ARMMMCI=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ACPI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=y -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+CONFIG_MMC_SDHCI_CADENCE=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MMC_SDHCI_F_SDH30=y -+CONFIG_MMC_SPI=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_EXYNOS=y -+CONFIG_MMC_DW_HI3798CV200=y -+CONFIG_MMC_DW_K3=y -+CONFIG_MMC_SDHCI_XENON=y -+CONFIG_MMC_SDHCI_AM654=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_PWM=y -+CONFIG_LEDS_SYSCON=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_PANIC=y -+CONFIG_EDAC=y -+CONFIG_EDAC_GHES=y -+CONFIG_EDAC_SYNOPSYS=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_MAX77686=y -+CONFIG_RTC_DRV_RK808=m -+CONFIG_RTC_DRV_PCF85363=m -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RV8803=m -+CONFIG_RTC_DRV_S5M=y -+CONFIG_RTC_DRV_DS3232=y -+CONFIG_RTC_DRV_PCF2127=m -+CONFIG_RTC_DRV_EFI=y -+CONFIG_RTC_DRV_CROS_EC=y -+CONFIG_RTC_DRV_FSL_FTM_ALARM=y -+CONFIG_RTC_DRV_PL031=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_IMX_SC=y -+CONFIG_RTC_DRV_IMX_RPMSG=y -+CONFIG_DMADEVICES=y -+CONFIG_BCM_SBA_RAID=m -+CONFIG_FSL_EDMA=y -+CONFIG_FSL_QDMA=m -+CONFIG_FSL_EDMA_V3=y -+CONFIG_IMX_SDMA=y -+CONFIG_MV_XOR_V2=y -+CONFIG_MXS_DMA=y -+CONFIG_PL330_DMA=y -+CONFIG_QCOM_HIDMA_MGMT=y -+CONFIG_QCOM_HIDMA=y -+CONFIG_FSL_DPAA2_QDMA=m -+CONFIG_DMATEST=y -+CONFIG_DMABUF_HEAPS=y -+CONFIG_DMABUF_HEAPS_SYSTEM=y -+CONFIG_DMABUF_HEAPS_CMA=y -+CONFIG_DMABUF_HEAPS_DSP=y -+CONFIG_UIO=y -+CONFIG_UIO_PCI_GENERIC=y -+CONFIG_UIO_IVSHMEM=y -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y -+CONFIG_VIRTIO_PCI=y -+CONFIG_VIRTIO_BALLOON=y -+CONFIG_VIRTIO_MMIO=y -+CONFIG_VIRTIO_IVSHMEM=y -+CONFIG_XEN_GNTDEV=y -+CONFIG_XEN_GRANT_DEV_ALLOC=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_IMX_CAPTURE=y -+CONFIG_IMX8_MEDIA_DEVICE=m -+CONFIG_ION=y -+CONFIG_ION_SYSTEM_HEAP=y -+CONFIG_ION_CMA_HEAP=y -+CONFIG_FSL_DPAA2=y -+CONFIG_FSL_DPAA2_ETHSW=y -+CONFIG_FSL_PPFE=y -+CONFIG_FSL_PPFE_UTIL_DISABLED=y -+CONFIG_CHROME_PLATFORMS=y -+CONFIG_CROS_EC=y -+CONFIG_CROS_EC_I2C=y -+CONFIG_CROS_EC_SPI=y -+CONFIG_CROS_EC_CHARDEV=m -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCPI=y -+CONFIG_COMMON_CLK_CS2000_CP=y -+CONFIG_COMMON_CLK_FSL_SAI=y -+CONFIG_COMMON_CLK_S2MPS11=y -+CONFIG_COMMON_CLK_XGENE=y -+CONFIG_COMMON_CLK_PWM=y -+CONFIG_COMMON_CLK_VC5=y -+CONFIG_CLK_IMX8MM=y -+CONFIG_CLK_IMX8MN=y -+CONFIG_CLK_IMX8MP=y -+CONFIG_CLK_IMX8MQ=y -+CONFIG_CLK_IMX8QXP=y -+CONFIG_CLK_IMX8ULP=y -+CONFIG_HWSPINLOCK=y -+CONFIG_ARM_MHU=y -+CONFIG_IMX_MBOX=y -+CONFIG_PLATFORM_MHU=y -+CONFIG_ARM_SMMU=y -+CONFIG_ARM_SMMU_V3=y -+CONFIG_REMOTEPROC=y -+CONFIG_IMX_REMOTEPROC=y -+CONFIG_IMX_DSP_REMOTEPROC=y -+CONFIG_RPMSG_CHAR=y -+CONFIG_RPMSG_QCOM_GLINK_RPM=y -+CONFIG_SOUNDWIRE=m -+CONFIG_SOUNDWIRE_QCOM=m -+CONFIG_SOC_BRCMSTB=y -+CONFIG_FSL_DPAA=y -+CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_RCPM=y -+CONFIG_FSL_QIXIS=y -+CONFIG_SOC_TI=y -+CONFIG_EXTCON_PTN5150=m -+CONFIG_EXTCON_USB_GPIO=y -+CONFIG_EXTCON_USBC_CROS_EC=y -+CONFIG_IIO=y -+CONFIG_IMX8QXP_ADC=y -+CONFIG_MAX9611=m -+CONFIG_QCOM_SPMI_ADC5=m -+CONFIG_IIO_CROS_EC_SENSORS_CORE=m -+CONFIG_IIO_CROS_EC_SENSORS=m -+CONFIG_IIO_CROS_EC_LIGHT_PROX=m -+CONFIG_IIO_CROS_EC_BARO=m -+CONFIG_IIO_ST_LSM6DSX=y -+CONFIG_PWM=y -+CONFIG_PWM_CROS_EC=m -+CONFIG_PWM_FSL_FTM=m -+CONFIG_PWM_IMX27=y -+CONFIG_PWM_RPCHIP=y -+CONFIG_PWM_SL28CPLD=m -+CONFIG_SL28CPLD_INTC=y -+CONFIG_MST_IRQ=y -+CONFIG_RESET_BRCMSTB_RESCAL=y -+CONFIG_RESET_IMX7=y -+CONFIG_RESET_IMX8ULP_SIM=y -+CONFIG_PHY_XGENE=y -+CONFIG_PHY_MIXEL_LVDS=y -+CONFIG_PHY_MIXEL_LVDS_COMBO=y -+CONFIG_PHY_CADENCE_SALVO=y -+CONFIG_PHY_FSL_IMX8MP_LVDS=y -+CONFIG_PHY_MIXEL_MIPI_DPHY=y -+CONFIG_PHY_SAMSUNG_HDMI_PHY=y -+CONFIG_PHY_QCOM_USB_HS=y -+CONFIG_PHY_SAMSUNG_USB2=y -+CONFIG_ARM_SMMU_V3_PMU=m -+CONFIG_FSL_IMX8_DDR_PMU=y -+CONFIG_HISI_PMU=y -+CONFIG_NVMEM_IMX_OCOTP=y -+CONFIG_NVMEM_IMX_OCOTP_SCU=y -+CONFIG_FPGA=y -+CONFIG_FPGA_BRIDGE=m -+CONFIG_ALTERA_FREEZE_BRIDGE=m -+CONFIG_FPGA_REGION=m -+CONFIG_OF_FPGA_REGION=m -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+CONFIG_MUX_MMIO=y -+CONFIG_SLIM_QCOM_CTRL=m -+CONFIG_INTERCONNECT=y -+CONFIG_MXC_SIM=y -+CONFIG_MXC_EMVSIM=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+CONFIG_QUOTA=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_HUGETLBFS=y -+CONFIG_EFIVAR_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_SQUASHFS=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_ROOT_NFS=y -+CONFIG_9P_FS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_SECURITY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ECHAINIV=y -+CONFIG_CRYPTO_TLS=m -+CONFIG_CRYPTO_CFB=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_OFB=m -+CONFIG_CRYPTO_PCBC=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_VMAC=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_STREEBOG=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_ARC4=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_SALSA20=m -+CONFIG_CRYPTO_SEED=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_USER_API_RNG=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m -+CONFIG_CRYPTO_DEV_FSL_CAAM=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m -+CONFIG_CRYPTO_DEV_CCREE=m -+CONFIG_CRYPTO_DEV_HISI_SEC2=m -+CONFIG_CRYPTO_DEV_HISI_ZIP=m -+CONFIG_CRYPTO_DEV_HISI_HPRE=m -+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m -+CONFIG_INDIRECT_PIO=y -+CONFIG_CRC_CCITT=m -+CONFIG_CMA_SIZE_MBYTES=32 -+CONFIG_PRINTK_TIME=y -+CONFIG_DEBUG_INFO=y -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_DEBUG_FS=y -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_PREEMPT is not set -+# CONFIG_FTRACE is not set -+CONFIG_CORESIGHT=y -+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -+CONFIG_CORESIGHT_SOURCE_ETM4X=y -+CONFIG_MEMTEST=y -+CONFIG_MXC_PXP_V3=y -+CONFIG_CRYPTO_USER_API_HASH=m -+CONFIG_CRYPTO_USER_API_SKCIPHER=m -+CONFIG_CRYPTO_USER_API_AEAD=m -diff --git a/arch/arm64/configs/lsdk.config b/arch/arm64/configs/lsdk.config -new file mode 100644 -index 000000000..c68eb70d2 ---- /dev/null -+++ b/arch/arm64/configs/lsdk.config -@@ -0,0 +1,176 @@ -+#uio -+CONFIG_UIO=y -+CONFIG_UIO_CIF=y -+CONFIG_UIO_PDRV_GENIRQ=y -+CONFIG_UIO_DMEM_GENIRQ=y -+CONFIG_UIO_AEC=y -+CONFIG_UIO_SERCOS3=y -+CONFIG_UIO_PCI_GENERIC=y -+CONFIG_UIO_NETX=y -+CONFIG_UIO_MF624=y -+# general options -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SLAB=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_PID_IN_CONTEXTIDR=y -+CONFIG_EXPERT=y -+CONFIG_CHECKPOINT_RESTORE=y -+CONFIG_PROC_KCORE=y -+# virtualization -+CONFIG_VHOST_NET=y -+CONFIG_KVM_ARM_MAX_VCPUS=8 -+ -+# DPAA1 networking -+# disable the DPAA1 upstream driver -+CONFIG_FSL_DPAA=n -+CONFIG_FSL_FMAN=n -+CONFIG_FSL_DPAA_ETH=n -+# enable the DPAA1 SDK driver -+CONFIG_FSL_SDK_DPA=y -+CONFIG_FSL_SDK_FMAN=y -+CONFIG_FSL_SDK_DPAA_ETH=y -+ -+# network and misc -+CONFIG_NET_DSA=y -+CONFIG_NET_DSA_MSCC_FELIX=y -+CONFIG_INET_ESP=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_DM_CRYPT=m -+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y -+CONFIG_EXT2_FS_XATTR=y -+CONFIG_EXT2_FS_POSIX_ACL=y -+CONFIG_EXT3_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_CFQ_GROUP_IOSCHED=y -+CONFIG_TMPFS_XATTR=y -+CONFIG_NETFILTER_ADVANCED=y -+CONFIG_BRIDGE_NETFILTER=y -+CONFIG_NETFILTER_NETLINK=y -+CONFIG_NETFILTER_XTABLES=y -+CONFIG_NETFILTER_XT_CONNMARK=y -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -+CONFIG_NETFILTER_XT_NAT=y -+CONFIG_NF_CONNTRACK=y -+CONFIG_NF_CONNTRACK_MARK=y -+CONFIG_NF_CONNTRACK_PROCFS=y -+CONFIG_NF_NAT=y -+CONFIG_NF_NAT_NEEDED=y -+CONFIG_NF_TABLES=y -+CONFIG_NFT_CT=y -+CONFIG_NFT_RBTREE=y -+CONFIG_NFT_MASQ=y -+CONFIG_NFT_NAT=y -+CONFIG_NFT_COMPAT=y -+CONFIG_NF_DEFRAG_IPV4=y -+CONFIG_NF_CONNTRACK_IPV4=y -+CONFIG_NF_CONNTRACK_PROC_COMPAT=y -+CONFIG_NF_TABLES_IPV4=y -+CONFIG_NF_NAT_IPV4=y -+CONFIG_NF_NAT_MASQUERADE_IPV4=y -+CONFIG_IP_NF_IPTABLES=y -+CONFIG_IP_NF_FILTER=y -+CONFIG_IP_NF_NAT=y -+CONFIG_IP_NF_TARGET_MASQUERADE=y -+CONFIG_IP_NF_MANGLE=y -+CONFIG_NF_TABLES_BRIDGE=y -+CONFIG_BRIDGE_NF_EBTABLES=y -+CONFIG_BRIDGE_EBT_T_NAT=y -+CONFIG_BRIDGE_EBT_DNAT=y -+CONFIG_BRIDGE_EBT_SNAT=y -+CONFIG_UNIX_DIAG=y -+CONFIG_PACKET_DIAG=y -+CONFIG_NETLINK_DIAG=y -+CONFIG_NETFILTER_XT_MATCH_COMMENT=y -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_TBF=y -+ -+# disable unneeded options and override default options set by defconfig to deduce the size of modules -+# CONFIG_USB_NET_DRIVERS is not set -+# CONFIG_NET_VENDOR_STMICRO is not set -+# CONFIG_BACKLIGHT_GENERIC is not set -+# CONFIG_TEGRA_HOST1X is not set -+# CONFIG_BT is not set -+# CONFIG_DRM_TEGRA is not set -+# CONFIG_DRM_EXYNOS is not set -+# CONFIG_DRM_MSM is not set -+# CONFIG_DRM_VC4 is not set -+# CONFIG_DRM_HISI_HIBMC is not set -+# CONFIG_DRM_HISI_KIRIN is not set -+# CONFIG_DRM_MESON is not set -+# CONFIG_DRM_ROCKCHIP is not set -+# CONFIG_DRM_RCAR_DU is not set -+# CONFIG_USB_RENESAS_USBHS is not set -+# CONFIG_QCOM_EMAC is not set -+# CONFIG_SND_SOC_ROCKCHIP is not set -+ -+CONFIG_IPV6=y -+CONFIG_NF_NAT_IPV6=y -+CONFIG_NF_NAT_MASQUERADE_IPV6=y -+CONFIG_NF_REJECT_IPV6=y -+CONFIG_IPV6_SIT=y -+CONFIG_NF_LOG_IPV6=y -+CONFIG_NF_CONNTRACK_IPV6=y -+CONFIG_VLAN_8021Q=y -+CONFIG_BRIDGE=y -+CONFIG_MACVLAN=y -+CONFIG_MACVTAP=y -+CONFIG_BTRFS_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_SQUASHFS_XZ=y -+ -+# lxc -+CONFIG_UNIX_DIAG=y -+CONFIG_PACKET_DIAG=y -+CONFIG_NETLINK_DIAG=y -+CONFIG_CGROUP_FREEZER=y -+ -+# sound -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=y -+CONFIG_SND_PCM_OSS=y -+CONFIG_SND_PCM_OSS_PLUGINS=y -+ -+# docker -+CONFIG_OVERLAY_FS=y -+ -+# enable iommu passthrough by default for performance -+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y -+ -+# disable the "disable_bypass" temporarily to workaround the MC issue with it -+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=n -+ -+# decrease the default number of CPUs to the maximum available on NXP -+# platforms to increase performance -+CONFIG_NR_CPUS=16 -+ -+#Qos -+CONFIG_NETFILTER_INGRESS=y -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_MULTIQ=y -+CONFIG_NET_SCH_MQPRIO=y -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_BASIC=y -+CONFIG_NET_CLS_TCINDEX=y -+CONFIG_NET_CLS_U32=y -+CONFIG_NET_CLS_FLOWER=y -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_STACK=32 -+CONFIG_NET_EMATCH_U32=y -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_PEDIT=y -+CONFIG_NET_ACT_SKBEDIT=y -+CONFIG_NET_ACT_VLAN=y -+CONFIG_NET_ACT_SKBMOD=y -+CONFIG_USB_NET_DRIVERS=y -+CONFIG_USB_RTL8152=y -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=y -+CONFIG_USB_NET_AX88179_178A=y -+# CONFIG_NET_PKTGEN is not set -diff --git a/arch/arm64/configs/myd_imx8mm_defconfig b/arch/arm64/configs/myd_imx8mm_defconfig -new file mode 100755 -index 000000000..1d712579e ---- /dev/null -+++ b/arch/arm64/configs/myd_imx8mm_defconfig -@@ -0,0 +1,1165 @@ -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_AUDIT=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_PREEMPT=y -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_NUMA_BALANCING=y -+CONFIG_MEMCG=y -+CONFIG_MEMCG_SWAP=y -+CONFIG_BLK_CGROUP=y -+CONFIG_CGROUP_PIDS=y -+CONFIG_CGROUP_HUGETLB=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_PERF=y -+CONFIG_USER_NS=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_KALLSYMS_ALL=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_ARCH_AGILEX=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_ARCH_ALPINE=y -+CONFIG_ARCH_BCM2835=y -+CONFIG_ARCH_BCM_IPROC=y -+CONFIG_ARCH_BERLIN=y -+CONFIG_ARCH_BRCMSTB=y -+CONFIG_ARCH_EXYNOS=y -+CONFIG_ARCH_K3=y -+CONFIG_ARCH_LAYERSCAPE=y -+CONFIG_ARCH_LG1K=y -+CONFIG_ARCH_HISI=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_ARCH_MESON=y -+CONFIG_ARCH_MVEBU=y -+CONFIG_ARCH_MXC=y -+CONFIG_ARCH_QCOM=y -+CONFIG_ARCH_RENESAS=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_ARCH_S32=y -+CONFIG_SOC_S32V234=y -+CONFIG_ARCH_SEATTLE=y -+CONFIG_ARCH_STRATIX10=y -+CONFIG_ARCH_SYNQUACER=y -+CONFIG_ARCH_TEGRA=y -+CONFIG_ARCH_SPRD=y -+CONFIG_ARCH_THUNDER=y -+CONFIG_ARCH_THUNDER2=y -+CONFIG_ARCH_UNIPHIER=y -+CONFIG_ARCH_VEXPRESS=y -+CONFIG_ARCH_XGENE=y -+CONFIG_ARCH_ZX=y -+CONFIG_ARCH_ZYNQMP=y -+CONFIG_ARM64_VA_BITS_48=y -+CONFIG_SCHED_MC=y -+CONFIG_NUMA=y -+CONFIG_SECCOMP=y -+CONFIG_KEXEC=y -+CONFIG_CRASH_DUMP=y -+CONFIG_XEN=y -+CONFIG_COMPAT=y -+CONFIG_RANDOMIZE_BASE=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_ARM_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=m -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+CONFIG_CPUFREQ_DT=y -+CONFIG_ACPI_CPPC_CPUFREQ=m -+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -+CONFIG_ARM_SCPI_CPUFREQ=y -+CONFIG_ARM_IMX_CPUFREQ_DT=y -+CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -+CONFIG_ARM_TEGRA186_CPUFREQ=y -+CONFIG_QORIQ_CPUFREQ=y -+CONFIG_ARM_SCPI_PROTOCOL=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_INTEL_STRATIX10_SERVICE=y -+CONFIG_EFI_CAPSULE_LOADER=y -+CONFIG_IMX_DSP=y -+CONFIG_IMX_SCU=y -+CONFIG_IMX_SCU_PD=y -+CONFIG_ACPI=y -+CONFIG_ACPI_APEI=y -+CONFIG_ACPI_APEI_GHES=y -+CONFIG_ACPI_APEI_PCIEAER=y -+CONFIG_ACPI_APEI_MEMORY_FAILURE=y -+CONFIG_ACPI_APEI_EINJ=y -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y -+CONFIG_ARM64_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+CONFIG_CRYPTO_SHA512_ARM64_CE=m -+CONFIG_CRYPTO_SHA3_ARM64=m -+CONFIG_CRYPTO_SM3_ARM64_CE=m -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -+CONFIG_CRYPTO_CHACHA20_NEON=m -+CONFIG_CRYPTO_AES_ARM64_BS=m -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_KSM=y -+CONFIG_MEMORY_FAILURE=y -+CONFIG_TRANSPARENT_HUGEPAGE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IPV6_SIT=m -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC2=y -+CONFIG_TSN=y -+CONFIG_NET_SWITCHDEV=y -+CONFIG_QRTR=m -+CONFIG_QRTR_SMD=m -+CONFIG_QRTR_TUN=m -+CONFIG_BPF_JIT=y -+CONFIG_CAN=m -+CONFIG_CAN_FLEXCAN=m -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+# CONFIG_BT_HS is not set -+# CONFIG_BT_LE is not set -+CONFIG_BT_LEDS=y -+# CONFIG_BT_DEBUGFS is not set -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y -+CONFIG_BT_HCIUART_BCM=y -+CONFIG_BT_HCIUART_QCA=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=y -+CONFIG_NL80211_TESTMODE=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y -+CONFIG_MAC80211_LEDS=y -+CONFIG_NET_9P=y -+CONFIG_NET_9P_VIRTIO=y -+CONFIG_PCI=y -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCI_IOV=y -+CONFIG_HOTPLUG_PCI=y -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_PCI_AARDVARK=y -+CONFIG_PCI_TEGRA=y -+CONFIG_PCIE_RCAR=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCI_XGENE=y -+CONFIG_PCIE_ALTERA=y -+CONFIG_PCIE_ALTERA_MSI=y -+CONFIG_PCI_HOST_THUNDER_PEM=y -+CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCIE_ROCKCHIP_HOST=m -+CONFIG_PCI_IMX6=y -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_PCI_HISI=y -+CONFIG_PCIE_QCOM=y -+CONFIG_PCIE_ARMADA_8K=y -+CONFIG_PCIE_KIRIN=y -+CONFIG_PCIE_HISI_STB=y -+CONFIG_PCIE_TEGRA194=m -+CONFIG_PCIE_LAYERSCAPE_GEN4=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -+CONFIG_HISILICON_LPC=y -+CONFIG_SIMPLE_PM_BUS=y -+CONFIG_FSL_MC_BUS=y -+CONFIG_FSL_MC_UAPI_SUPPORT=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_RAW_NAND=y -+CONFIG_MTD_NAND_DENALI_DT=y -+CONFIG_MTD_NAND_MARVELL=y -+CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_QCOM=y -+CONFIG_MTD_SPI_NOR=y -+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_NBD=m -+CONFIG_VIRTIO_BLK=y -+CONFIG_BLK_DEV_NVME=y -+CONFIG_SENSORS_FXOS8700=y -+CONFIG_SENSORS_FXAS2100X=y -+CONFIG_SRAM=y -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=m -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_HISI_SAS=y -+CONFIG_SCSI_HISI_SAS_PCI=y -+CONFIG_SCSI_MPT3SAS=m -+CONFIG_SCSI_UFSHCD=y -+CONFIG_SCSI_UFSHCD_PLATFORM=y -+CONFIG_SCSI_UFS_QCOM=m -+CONFIG_SCSI_UFS_HISI=y -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_AHCI_CEVA=y -+CONFIG_AHCI_MVEBU=y -+CONFIG_AHCI_XGENE=y -+CONFIG_AHCI_QORIQ=y -+CONFIG_SATA_SIL24=y -+CONFIG_SATA_RCAR=y -+CONFIG_PATA_PLATFORM=y -+CONFIG_PATA_OF_PLATFORM=y -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_ZERO=m -+CONFIG_NETDEVICES=y -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_TUN=y -+CONFIG_VETH=m -+CONFIG_VIRTIO_NET=y -+CONFIG_AMD_XGBE=y -+CONFIG_NET_XGENE=y -+CONFIG_ATL1C=m -+CONFIG_BNX2X=m -+CONFIG_MACB=y -+CONFIG_THUNDER_NIC_PF=y -+CONFIG_FEC=y -+CONFIG_FSL_SDK_DPAA_ETH=y -+CONFIG_FSL_DPAA2_ETH=y -+CONFIG_FSL_ENETC=y -+CONFIG_FSL_ENETC_VF=y -+CONFIG_FSL_ENETC_MDIO=y -+CONFIG_ENETC_TSN=y -+CONFIG_HIX5HD2_GMAC=y -+CONFIG_HNS_DSAF=y -+CONFIG_HNS_ENET=y -+CONFIG_HNS3=y -+CONFIG_HNS3_HCLGE=y -+CONFIG_HNS3_ENET=y -+CONFIG_E1000=y -+CONFIG_E1000E=y -+CONFIG_IGB=y -+CONFIG_IGBVF=y -+CONFIG_MVNETA=y -+CONFIG_MVPP2=y -+CONFIG_SKY2=y -+CONFIG_MLX4_EN=m -+CONFIG_MLX5_CORE=m -+CONFIG_MLX5_CORE_EN=y -+CONFIG_MSCC_OCELOT_SWITCH=y -+CONFIG_QCOM_EMAC=m -+CONFIG_RAVB=y -+CONFIG_SMC91X=y -+CONFIG_SMSC911X=y -+CONFIG_SNI_AVE=y -+CONFIG_SNI_NETSEC=y -+CONFIG_STMMAC_ETH=m -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_AQUANTIA_PHY=y -+CONFIG_AT803X_PHY=y -+CONFIG_INPHI_PHY=y -+CONFIG_MARVELL_PHY=m -+CONFIG_MARVELL_10G_PHY=m -+CONFIG_MESON_GXL_PHY=m -+CONFIG_MICREL_PHY=y -+CONFIG_MICROSEMI_PHY=y -+CONFIG_NXP_TJA11XX_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_ROCKCHIP_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_PPP=y -+CONFIG_PPP_BSDCOMP=y -+CONFIG_PPP_DEFLATE=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=y -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOE=y -+CONFIG_PPP_ASYNC=y -+CONFIG_PPP_SYNC_TTY=y -+CONFIG_SLHC=y -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_LAN78XX=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_BCMDHD=y -+CONFIG_BCMDHD_FW_PATH="/system/etc/wifi/fw_bcm43438a1_apsta.bin" -+CONFIG_BCMDHD_NVRAM_PATH="/system/etc/wifi/nvram_ap6212a.txt" -+CONFIG_BCMDHD_SDIO=y -+CONFIG_BCMDHD_SDIO_IRQ=y -+CONFIG_HOSTAP=y -+CONFIG_WL18XX=m -+CONFIG_WLCORE_SDIO=m -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_ADC=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y -+CONFIG_KEYBOARD_CROS_EC=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_PM8941_PWRKEY=y -+CONFIG_INPUT_HISI_POWERKEY=y -+CONFIG_INPUT_MPL3115=y -+CONFIG_INPUT_ISL29023=y -+# CONFIG_SERIO_SERPORT is not set -+CONFIG_SERIO_AMBAKMI=y -+CONFIG_LEGACY_PTY_COUNT=16 -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_BCM2835AUX=y -+CONFIG_SERIAL_8250_DW=y -+CONFIG_SERIAL_8250_OMAP=y -+CONFIG_SERIAL_8250_MT6577=y -+CONFIG_SERIAL_8250_UNIPHIER=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_MESON=y -+CONFIG_SERIAL_MESON_CONSOLE=y -+CONFIG_SERIAL_SAMSUNG=y -+CONFIG_SERIAL_SAMSUNG_CONSOLE=y -+CONFIG_SERIAL_TEGRA=y -+CONFIG_SERIAL_TEGRA_TCU=y -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_SH_SCI=y -+CONFIG_SERIAL_MSM=y -+CONFIG_SERIAL_MSM_CONSOLE=y -+CONFIG_SERIAL_QCOM_GENI=y -+CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -+CONFIG_SERIAL_XILINX_PS_UART=y -+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_SERIAL_FSL_LINFLEXUART=y -+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -+CONFIG_SERIAL_MVEBU_UART=y -+CONFIG_SERIAL_DEV_BUS=y -+CONFIG_VIRTIO_CONSOLE=y -+CONFIG_IPMI_HANDLER=m -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_SI=m -+CONFIG_TCG_TPM=y -+CONFIG_TCG_TIS_I2C_INFINEON=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_BCM2835=m -+CONFIG_I2C_DESIGNWARE_PLATFORM=y -+CONFIG_I2C_GPIO=m -+CONFIG_I2C_IMX=y -+CONFIG_I2C_IMX_LPI2C=y -+CONFIG_I2C_MESON=y -+CONFIG_I2C_MV64XXX=y -+CONFIG_I2C_PXA=y -+CONFIG_I2C_QCOM_GENI=m -+CONFIG_I2C_QUP=y -+CONFIG_I2C_RK3X=y -+CONFIG_I2C_RPBUS=y -+CONFIG_I2C_SH_MOBILE=y -+CONFIG_I2C_TEGRA=y -+CONFIG_I2C_UNIPHIER_F=y -+CONFIG_I2C_RCAR=y -+CONFIG_I2C_CROS_EC_TUNNEL=y -+CONFIG_SPI=y -+CONFIG_SPI_ARMADA_3700=y -+CONFIG_SPI_BCM2835=m -+CONFIG_SPI_BCM2835AUX=m -+CONFIG_SPI_FSL_LPSPI=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_SPI_NXP_FLEXSPI=y -+CONFIG_SPI_IMX=y -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_SPI_MESON_SPICC=m -+CONFIG_SPI_MESON_SPIFC=m -+CONFIG_SPI_ORION=y -+CONFIG_SPI_PL022=y -+CONFIG_SPI_ROCKCHIP=y -+CONFIG_SPI_QUP=y -+CONFIG_SPI_S3C64XX=y -+CONFIG_SPI_SUN6I=y -+CONFIG_SPI_SPIDEV=y -+CONFIG_SPI_SLAVE=y -+CONFIG_SPI_SLAVE_TIME=y -+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y -+CONFIG_SPMI=y -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_PINCTRL_MAX77620=y -+CONFIG_PINCTRL_IMX8MM=y -+CONFIG_PINCTRL_IMX8MN=y -+CONFIG_PINCTRL_IMX8MQ=y -+CONFIG_PINCTRL_IMX8QM=y -+CONFIG_PINCTRL_IMX8QXP=y -+CONFIG_PINCTRL_IMX8DXL=y -+CONFIG_PINCTRL_IPQ8074=y -+CONFIG_PINCTRL_MSM8916=y -+CONFIG_PINCTRL_S32V234=y -+CONFIG_PINCTRL_MSM8994=y -+CONFIG_PINCTRL_MSM8996=y -+CONFIG_PINCTRL_MSM8998=y -+CONFIG_PINCTRL_QCS404=y -+CONFIG_PINCTRL_QDF2XXX=y -+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -+CONFIG_PINCTRL_SDM845=y -+CONFIG_PINCTRL_SM8150=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_DWAPB=y -+CONFIG_GPIO_MB86S7X=y -+CONFIG_GPIO_MPC8XXX=y -+CONFIG_GPIO_PL061=y -+CONFIG_GPIO_RCAR=y -+CONFIG_GPIO_UNIPHIER=y -+CONFIG_GPIO_XGENE=y -+CONFIG_GPIO_XGENE_SB=y -+CONFIG_GPIO_MAX732X=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_MAX77620=y -+CONFIG_POWER_AVS=y -+CONFIG_ROCKCHIP_IODOMAIN=y -+CONFIG_POWER_RESET_MSM=y -+CONFIG_POWER_RESET_XGENE=y -+CONFIG_POWER_RESET_SYSCON=y -+CONFIG_SYSCON_REBOOT_MODE=y -+CONFIG_BATTERY_SBS=m -+CONFIG_BATTERY_BQ27XXX=y -+CONFIG_SENSORS_ARM_SCPI=y -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_PWM_FAN=m -+CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_WRITABLE_TRIPS=y -+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -+CONFIG_CPU_THERMAL=y -+CONFIG_THERMAL_EMULATION=y -+CONFIG_IMX_SC_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_IMX8MM_THERMAL=y -+CONFIG_QORIQ_THERMAL=y -+CONFIG_ROCKCHIP_THERMAL=m -+CONFIG_RCAR_THERMAL=y -+CONFIG_RCAR_GEN3_THERMAL=y -+CONFIG_ARMADA_THERMAL=y -+CONFIG_BCM2835_THERMAL=m -+CONFIG_BRCMSTB_THERMAL=m -+CONFIG_EXYNOS_THERMAL=y -+CONFIG_TEGRA_BPMP_THERMAL=m -+CONFIG_QCOM_TSENS=y -+CONFIG_UNIPHIER_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_ARM_SBSA_WATCHDOG=y -+CONFIG_ARM_SP805_WATCHDOG=y -+CONFIG_S3C2410_WATCHDOG=y -+CONFIG_DW_WATCHDOG=y -+CONFIG_SUNXI_WATCHDOG=m -+CONFIG_IMX2_WDT=y -+CONFIG_IMX_SC_WDT=y -+CONFIG_MESON_GXBB_WATCHDOG=m -+CONFIG_MESON_WATCHDOG=m -+CONFIG_RENESAS_WDT=y -+CONFIG_UNIPHIER_WATCHDOG=y -+CONFIG_BCM2835_WDT=y -+CONFIG_MFD_ALTERA_SYSMGR=y -+CONFIG_MFD_BD9571MWV=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_MFD_AXP20X_RSB=y -+CONFIG_MFD_EXYNOS_LPASS=m -+CONFIG_MFD_IMX_AUDIOMIX=y -+CONFIG_MFD_HI6421_PMIC=y -+CONFIG_MFD_HI655X_PMIC=y -+CONFIG_MFD_MAX77620=y -+CONFIG_MFD_SPMI_PMIC=y -+CONFIG_MFD_RK808=y -+CONFIG_MFD_SEC_CORE=y -+CONFIG_MFD_ROHM_BD718XX=y -+CONFIG_MFD_PCA9450=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_AXP20X=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_BD9571MWV=y -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_REGULATOR_GPIO=y -+CONFIG_REGULATOR_HI6421V530=y -+CONFIG_REGULATOR_HI655X=y -+CONFIG_REGULATOR_MAX77620=y -+CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_PCA9450=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_QCOM_RPMH=y -+CONFIG_REGULATOR_QCOM_SMD_RPM=y -+CONFIG_REGULATOR_QCOM_SPMI=y -+CONFIG_REGULATOR_RK808=y -+CONFIG_REGULATOR_S2MPS11=y -+CONFIG_REGULATOR_VCTRL=m -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_RC_DEVICES=y -+CONFIG_IR_MESON=m -+CONFIG_IR_SUNXI=m -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_PLATFORM_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+# CONFIG_DVB_NET is not set -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=y -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MX8_CAPTURE=y -+CONFIG_VIDEO_MXC_CAPTURE=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=y -+CONFIG_MXC_MIPI_CSI=y -+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m -+CONFIG_VIDEO_SUN6I_CSI=m -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -+CONFIG_VIDEO_RENESAS_FCP=m -+CONFIG_VIDEO_RENESAS_VSP1=m -+CONFIG_VIDEO_OV5640=y -+CONFIG_IMX_DPU_CORE=y -+CONFIG_IMX_LCDIF_CORE=y -+CONFIG_DRM=y -+CONFIG_DRM_I2C_NXP_TDA998X=m -+CONFIG_DRM_MALI_DISPLAY=m -+CONFIG_DRM_NOUVEAU=m -+CONFIG_DRM_EXYNOS=m -+CONFIG_DRM_EXYNOS5433_DECON=y -+CONFIG_DRM_EXYNOS7_DECON=y -+CONFIG_DRM_EXYNOS_DSI=y -+# CONFIG_DRM_EXYNOS_DP is not set -+CONFIG_DRM_EXYNOS_HDMI=y -+CONFIG_DRM_EXYNOS_MIC=y -+CONFIG_DRM_ROCKCHIP=m -+CONFIG_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_ROCKCHIP_CDN_DP=y -+CONFIG_ROCKCHIP_DW_HDMI=y -+CONFIG_ROCKCHIP_DW_MIPI_DSI=y -+CONFIG_ROCKCHIP_INNO_HDMI=y -+CONFIG_DRM_RCAR_DU=m -+CONFIG_DRM_SUN4I=m -+CONFIG_DRM_SUN8I_DW_HDMI=m -+CONFIG_DRM_SUN8I_MIXER=m -+CONFIG_DRM_MSM=m -+CONFIG_DRM_TEGRA=m -+CONFIG_DRM_PANEL_TC358775=y -+CONFIG_DRM_BRIDGE=y -+CONFIG_DRM_PANEL_BRIDGE=y -+CONFIG_DRM_SII902X=m -+CONFIG_DRM_NWL_MIPI_DSI=y -+CONFIG_DRM_CDNS_HDMI_CEC=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_TVE=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX_HDMI=y -+CONFIG_DRM_IMX_SEC_DSIM=y -+CONFIG_DRM_IMX_CDNS_MHDP=y -+CONFIG_DRM_IMX_DCSS=y -+CONFIG_DRM_VC4=m -+CONFIG_DRM_ETNAVIV=m -+CONFIG_DRM_HISI_HIBMC=m -+CONFIG_DRM_HISI_KIRIN=m -+CONFIG_DRM_MXSFB=y -+CONFIG_DRM_MESON=m -+CONFIG_DRM_PL111=m -+CONFIG_DRM_LIMA=m -+CONFIG_DRM_PANFROST=m -+CONFIG_FB_ARMCLCD=y -+CONFIG_FB_EFI=y -+CONFIG_BACKLIGHT_GENERIC=m -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_HDA_TEGRA=m -+CONFIG_SND_HDA_CODEC_HDMI=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_BCM2835_SOC_I2S=m -+CONFIG_SND_SOC_FSL_EASRC=y -+CONFIG_SND_SOC_FSL_DAI=m -+# -+# Common SoC Audio options for Freescale CPUs: -+# -+CONFIG_SND_SOC_FSL_ASRC=y -+CONFIG_SND_SOC_FSL_SAI=y -+CONFIG_SND_SOC_FSL_ACM=y -+CONFIG_SND_SOC_FSL_AMIX=y -+CONFIG_SND_SOC_FSL_SSI=y -+CONFIG_SND_SOC_FSL_SPDIF=y -+CONFIG_SND_SOC_FSL_ESAI=y -+CONFIG_SND_SOC_FSL_MICFIL=y -+CONFIG_SND_SOC_FSL_RPMSG_I2S=y -+CONFIG_SND_SOC_FSL_DSP=y -+CONFIG_SND_SOC_FSL_UTILS=y -+CONFIG_SND_SOC_IMX_PCM_DMA=y -+CONFIG_SND_SOC_IMX_PCM_RPMSG=y -+CONFIG_SND_SOC_IMX_AUDMUX=y -+ -+CONFIG_SND_IMX_SOC=y -+# CONFIG_SND_SOC_IMX_AK4458=y -+# CONFIG_SND_SOC_IMX_AK5558=y -+# CONFIG_SND_SOC_IMX_AK4497=y -+# CONFIG_SND_SOC_IMX_WM8960=y -+# CONFIG_SND_SOC_IMX_WM8524=y -+# CONFIG_SND_SOC_IMX_CS42888=y -+CONFIG_SND_SOC_IMX_WM8904=m -+CONFIG_SND_SOC_IMX_MICFIL=y -+CONFIG_SND_SOC_IMX_RPMSG=y -+CONFIG_SND_SOC_IMX_MQS=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_AUDMIX=y -+CONFIG_SND_SOC_IMX_PDM_MIC=y -+CONFIG_SND_SOC_IMX_DSP=y -+CONFIG_SND_SOC_IMX_CDNHDMI=y -+CONFIG_SND_MESON_AXG_SOUND_CARD=m -+CONFIG_SND_SOC_ROCKCHIP=m -+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -+CONFIG_SND_SOC_ROCKCHIP_RT5645=m -+CONFIG_SND_SOC_RK3399_GRU_SOUND=m -+CONFIG_SND_SOC_SAMSUNG=y -+CONFIG_SND_SOC_RCAR=m -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=m -+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y -+CONFIG_SND_SOC_WM8904=y -+CONFIG_SND_SUN4I_SPDIF=m -+CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_ES7134=m -+CONFIG_SND_SOC_ES7241=m -+CONFIG_SND_SOC_PCM3168A_I2C=m -+CONFIG_SND_SOC_SGTL5000=m -+CONFIG_SND_SOC_TAS571X=m -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_SND_AUDIO_GRAPH_CARD=y -+CONFIG_I2C_HID=m -+CONFIG_USB=y -+CONFIG_USB_OTG=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_TEGRA=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_EXYNOS=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_EXYNOS=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_RENESAS_USBHS=m -+CONFIG_USB_ACM=m -+CONFIG_USB_WDM=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_MUSB_SUNXI=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_ISP1760=y -+CONFIG_USB_TEST=m -+CONFIG_USB_EHSET_TEST_FIXTURE=m -+CONFIG_USB_HSIC_USB3503=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_WWAN=y -+CONFIG_USB_SERIAL_OPTION=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_ULPI=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_RENESAS_USBHS_UDC=m -+CONFIG_USB_RENESAS_USB3=m -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_SWITCH_GPIO=y -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_ARMMMCI=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ACPI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=y -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+CONFIG_MMC_SDHCI_CADENCE=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MMC_SDHCI_TEGRA=y -+CONFIG_MMC_SDHCI_F_SDH30=y -+CONFIG_MMC_MESON_GX=y -+CONFIG_MMC_SDHCI_MSM=y -+CONFIG_MMC_SPI=y -+CONFIG_MMC_SDHI=y -+CONFIG_MMC_UNIPHIER=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_EXYNOS=y -+CONFIG_MMC_DW_HI3798CV200=y -+CONFIG_MMC_DW_K3=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SUNXI=y -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_SDHCI_XENON=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_PWM=y -+CONFIG_LEDS_SYSCON=y -+CONFIG_LEDS_TRIGGER_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_PANIC=y -+CONFIG_EDAC=y -+CONFIG_EDAC_GHES=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_RX8025=y -+CONFIG_RTC_DRV_MAX77686=y -+CONFIG_RTC_DRV_RK808=m -+CONFIG_RTC_DRV_PCF85363=y -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_S5M=y -+CONFIG_RTC_DRV_DS3232=y -+CONFIG_RTC_DRV_PCF2127=y -+CONFIG_RTC_DRV_EFI=y -+CONFIG_RTC_DRV_CROS_EC=y -+CONFIG_RTC_DRV_S3C=y -+CONFIG_RTC_DRV_PL031=y -+CONFIG_RTC_DRV_SUN6I=y -+CONFIG_RTC_DRV_ARMADA38X=y -+CONFIG_RTC_DRV_TEGRA=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_IMX_SC=y -+CONFIG_RTC_DRV_XGENE=y -+CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2835=m -+CONFIG_DMA_SUN6I=m -+CONFIG_FSL_EDMA=y -+CONFIG_FSL_EDMA_V3=y -+CONFIG_IMX_SDMA=y -+CONFIG_K3_DMA=y -+CONFIG_MV_XOR=y -+CONFIG_MV_XOR_V2=y -+CONFIG_MXS_DMA=y -+CONFIG_PL330_DMA=y -+CONFIG_TEGRA20_APB_DMA=y -+CONFIG_QCOM_BAM_DMA=y -+CONFIG_QCOM_HIDMA_MGMT=y -+CONFIG_QCOM_HIDMA=y -+CONFIG_RCAR_DMAC=y -+CONFIG_RENESAS_USB_DMAC=m -+CONFIG_DMATEST=y -+CONFIG_UIO=y -+CONFIG_UIO_PCI_GENERIC=y -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y -+CONFIG_VIRTIO_PCI=y -+CONFIG_VIRTIO_BALLOON=y -+CONFIG_VIRTIO_MMIO=y -+CONFIG_XEN_GNTDEV=y -+CONFIG_XEN_GRANT_DEV_ALLOC=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_IMX_CAPTURE=y -+CONFIG_ION=y -+CONFIG_ION_SYSTEM_HEAP=y -+CONFIG_ION_CMA_HEAP=y -+CONFIG_FSL_DPAA2=y -+CONFIG_FSL_DPAA2_ETHSW=y -+CONFIG_FSL_DPAA2_MAC=y -+CONFIG_FSL_SDK_DPA=y -+CONFIG_FSL_PPFE=y -+CONFIG_FSL_PPFE_UTIL_DISABLED=y -+CONFIG_MFD_CROS_EC=y -+CONFIG_CROS_EC_I2C=y -+CONFIG_CROS_EC_SPI=y -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCPI=y -+CONFIG_COMMON_CLK_CS2000_CP=y -+CONFIG_COMMON_CLK_S2MPS11=y -+CONFIG_COMMON_CLK_PWM=y -+CONFIG_CLK_RASPBERRYPI=m -+CONFIG_CLK_IMX8MM=y -+CONFIG_CLK_IMX8MN=y -+CONFIG_CLK_IMX8MQ=y -+CONFIG_CLK_IMX8QXP=y -+CONFIG_TI_SCI_CLK=y -+CONFIG_COMMON_CLK_QCOM=y -+CONFIG_QCOM_A53PLL=y -+CONFIG_QCOM_CLK_APCS_MSM8916=y -+CONFIG_QCOM_CLK_SMD_RPM=y -+CONFIG_QCOM_CLK_RPMH=y -+CONFIG_IPQ_GCC_8074=y -+CONFIG_MSM_GCC_8916=y -+CONFIG_MSM_GCC_8994=y -+CONFIG_MSM_MMCC_8996=y -+CONFIG_MSM_GCC_8998=y -+CONFIG_QCS_GCC_404=y -+CONFIG_SDM_GCC_845=y -+CONFIG_SM_GCC_8150=y -+CONFIG_HWSPINLOCK=y -+CONFIG_HWSPINLOCK_QCOM=y -+CONFIG_ARM_MHU=y -+CONFIG_IMX_MBOX=y -+CONFIG_PLATFORM_MHU=y -+CONFIG_BCM2835_MBOX=y -+CONFIG_QCOM_APCS_IPC=y -+CONFIG_ROCKCHIP_IOMMU=y -+CONFIG_TEGRA_IOMMU_SMMU=y -+CONFIG_ARM_SMMU=y -+CONFIG_ARM_SMMU_V3=y -+CONFIG_QCOM_IOMMU=y -+CONFIG_REMOTEPROC=y -+CONFIG_QCOM_Q6V5_MSS=m -+CONFIG_QCOM_Q6V5_PAS=m -+CONFIG_QCOM_SYSMON=m -+CONFIG_RPMSG_QCOM_GLINK_RPM=y -+CONFIG_RPMSG_QCOM_GLINK_SMEM=m -+CONFIG_RPMSG_QCOM_SMD=y -+CONFIG_RASPBERRYPI_POWER=y -+CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_QIXIS=y -+CONFIG_IMX_SCU_SOC=y -+CONFIG_QCOM_GENI_SE=y -+CONFIG_QCOM_GLINK_SSR=m -+CONFIG_QCOM_RPMH=y -+CONFIG_QCOM_SMEM=y -+CONFIG_QCOM_SMD_RPM=y -+CONFIG_QCOM_SMP2P=y -+CONFIG_QCOM_SMSM=y -+CONFIG_ARCH_R8A774A1=y -+CONFIG_ARCH_R8A774C0=y -+CONFIG_ARCH_R8A7795=y -+CONFIG_ARCH_R8A7796=y -+CONFIG_ARCH_R8A77965=y -+CONFIG_ARCH_R8A77970=y -+CONFIG_ARCH_R8A77980=y -+CONFIG_ARCH_R8A77990=y -+CONFIG_ARCH_R8A77995=y -+CONFIG_ROCKCHIP_PM_DOMAINS=y -+CONFIG_ARCH_TEGRA_132_SOC=y -+CONFIG_ARCH_TEGRA_210_SOC=y -+CONFIG_ARCH_TEGRA_186_SOC=y -+CONFIG_ARCH_TEGRA_194_SOC=y -+CONFIG_ARCH_K3_AM6_SOC=y -+CONFIG_ARCH_K3_J721E_SOC=y -+CONFIG_TI_SCI_PM_DOMAINS=y -+CONFIG_EXTCON_USB_GPIO=y -+CONFIG_EXTCON_USBC_CROS_EC=y -+CONFIG_IIO=y -+CONFIG_EXYNOS_ADC=y -+CONFIG_IMX8QXP_ADC=y -+CONFIG_ROCKCHIP_SARADC=m -+CONFIG_IIO_CROS_EC_SENSORS_CORE=m -+CONFIG_IIO_CROS_EC_SENSORS=m -+CONFIG_IIO_CROS_EC_LIGHT_PROX=m -+CONFIG_IIO_CROS_EC_BARO=m -+CONFIG_PWM=y -+CONFIG_PWM_BCM2835=m -+CONFIG_PWM_CROS_EC=m -+CONFIG_PWM_IMX27=y -+CONFIG_PWM_MESON=m -+CONFIG_PWM_RCAR=m -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_PWM_SAMSUNG=y -+CONFIG_PWM_SUN4I=m -+CONFIG_PWM_TEGRA=m -+CONFIG_RESET_TI_SCI=y -+CONFIG_PHY_XGENE=y -+CONFIG_PHY_SUN4I_USB=y -+CONFIG_PHY_MIXEL_MIPI_DPHY=y -+CONFIG_PHY_HI6220_USB=y -+CONFIG_PHY_HISTB_COMBPHY=y -+CONFIG_PHY_HISI_INNO_USB2=y -+CONFIG_PHY_MVEBU_CP110_COMPHY=y -+CONFIG_PHY_QCOM_QMP=m -+CONFIG_PHY_QCOM_QUSB2=m -+CONFIG_PHY_QCOM_USB_HS=y -+CONFIG_PHY_RCAR_GEN3_PCIE=y -+CONFIG_PHY_RCAR_GEN3_USB2=y -+CONFIG_PHY_RCAR_GEN3_USB3=m -+CONFIG_PHY_ROCKCHIP_EMMC=y -+CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_PCIE=m -+CONFIG_PHY_ROCKCHIP_TYPEC=y -+CONFIG_PHY_UNIPHIER_USB2=y -+CONFIG_PHY_UNIPHIER_USB3=y -+CONFIG_PHY_TEGRA_XUSB=y -+CONFIG_FSL_IMX8_DDR_PMU=y -+CONFIG_HISI_PMU=y -+CONFIG_QCOM_L2_PMU=y -+CONFIG_QCOM_L3_PMU=y -+CONFIG_NVMEM_IMX_OCOTP=y -+CONFIG_NVMEM_IMX_OCOTP_SCU=y -+CONFIG_QCOM_QFPROM=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_NVMEM_SUNXI_SID=y -+CONFIG_UNIPHIER_EFUSE=y -+CONFIG_MESON_EFUSE=m -+CONFIG_FPGA=y -+CONFIG_FPGA_MGR_STRATIX10_SOC=m -+CONFIG_FPGA_BRIDGE=m -+CONFIG_ALTERA_FREEZE_BRIDGE=m -+CONFIG_FPGA_REGION=m -+CONFIG_OF_FPGA_REGION=m -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+CONFIG_MUX_MMIO=y -+CONFIG_MXC_SIM=y -+CONFIG_MXC_EMVSIM=y -+CONFIG_MXC_MLB150=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+CONFIG_QUOTA=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_HUGETLBFS=y -+CONFIG_EFIVAR_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_SQUASHFS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_ROOT_NFS=y -+CONFIG_9P_FS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_SECURITY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_ECHAINIV=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_TLS=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=m -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA3=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y -+CONFIG_CMA_SIZE_MBYTES=320 -+CONFIG_PRINTK_TIME=y -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_FS=y -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_DEBUG_KERNEL=y -+CONFIG_CRC_CCITT=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_PREEMPT is not set -+# CONFIG_FTRACE is not set -+CONFIG_MEMTEST=y -+# CONFIG_TYPEC_STUSB=y -+CONFIG_TOUCHSCREEN_EDT_FT5X06=n -+CONFIG_TOUCHSCREEN_GOODIX=n -+CONFIG_RFKILL=y -+CONFIG_RFKILL_LEDS=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_MOTORCOMM_PHY=y -+CONFIG_MFD_IMX_MIX=y -+CONFIG_ANDROID=y -+CONFIG_ANDROID_BINDER_IPC=y -+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" -+# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set -+# CONFIG_DAX is not set -+CONFIG_NVMEM=y -+# start of hdf Drivers -+CONFIG_DRIVERS_HDF=y -+CONFIG_HDF_SUPPORT_LEVEL=2 -+CONFIG_DRIVERS_HDF_PLATFORM=y -+#CONFIG_DRIVERS_HDF_PLATFORM_MIPI_DSI=y -+CONFIG_DRIVERS_HDF_PLATFORM_GPIO=y -+CONFIG_DRIVERS_HDF_PLATFORM_I2C=y -+#CONFIG_DRIVERS_HDF_PLATFORM_WATCHDOG=y -+CONFIG_PWM_HI35XX=y -+CONFIG_DRIVERS_HDF_PLATFORM_PWM=y -+CONFIG_DRIVERS_HDF_PLATFORM_UART=y -+CONFIG_DRIVERS_HDF_PLATFORM_SDIO=y -+CONFIG_DRIVERS_HDF_PLATFORM_EMMC=y -+CONFIG_DRIVERS_HDF_PLATFORM_MMC=y -+CONFIG_DRIVERS_HDF_PLATFORM_SPI=y -+CONFIG_DRIVERS_HDF_PLATFORM_RTC=y -+CONFIG_DRIVERS_HDF_TEST=n -+CONFIG_DRIVERS_HDF_DISP=n -+# CONFIG_DRIVERS_HDF_LCDKIT is not set -+CONFIG_ARCH_NXP_TOUCH=y -+CONFIG_DRIVERS_HDF_LCD_ICN9700=y -+# CONFIG_DRIVERS_HDF_LCD_ST7789 is not set -+CONFIG_DRIVERS_HDF_INPUT=y -+#CONFIG_DRIVERS_HDF_TP_5P5_GT911=y -+#CONFIG_DRIVERS_HDF_TP_2P35_FT6236=y -+CONFIG_DRIVERS_HDF_WIFI=y -+#CONFIG_DRIVERS_HI3881=y -+# CONFIG_DRIVERS_HDF_BT is not set -+CONFIG_DRIVERS_HDF_SENSOR=y -+# CONFIG_DRIVERS_HDF_SENSOR_ACCEL is not set -+# CONFIG_DRIVERS_HDF_SENSOR_GYRO is not set -+CONFIG_DRIVERS_HDF_STORAGE=y -+CONFIG_DRIVERS_HDF_VIBRATOR=y -+CONFIG_DRIVERS_HDF_VIBRATOR_LINEAR=y -+# CONFIG_HI_DMAC is not set -+# CONFIG_HIEDMAC is not set -+CONFIG_DRIVERS_HDF_IMX8MM_ETHERNET=y -+CONFIG_INPUT_UINPUT=y -+CONFIG_ARCH_ARM64=y -+CONFIG_IMX8MM_AUDIO=y -+CONFIG_IMX8MM_SDIO_TEST=y -+CONFIG_IMX8MM_SPI_TEST=y -+CONFIG_DRIVERS_HDF_PLATFORM_IMX8MM_MIPI_DSI=y -+CONFIG_IMX8MM_WDT=y -+CONFIG_IMX8MM_SDIO=y -+CONFIG_IMX8MM_RTC=y -+CONFIG_IMX8MM_EMMC=y -+CONFIG_DRIVERS_HDF_USB_F_IMX8MM=y -+CONFIG_DRIVERS_AP6212=y -+CONFIG_ACCESS_TOKENID=y -+CONFIG_ASHMEM=y -+CONFIG_NVMEM_SYSFS=y -+# end of hdf Drivers -diff --git a/arch/arm64/configs/myd_jx8mp_defconfig b/arch/arm64/configs/myd_jx8mp_defconfig -new file mode 100755 -index 000000000..7d25cef4b ---- /dev/null -+++ b/arch/arm64/configs/myd_jx8mp_defconfig -@@ -0,0 +1,830 @@ -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_AUDIT=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_PREEMPT=y -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_NUMA_BALANCING=y -+CONFIG_MEMCG=y -+CONFIG_MEMCG_SWAP=y -+CONFIG_BLK_CGROUP=y -+CONFIG_CGROUP_PIDS=y -+CONFIG_CGROUP_HUGETLB=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_PERF=y -+CONFIG_USER_NS=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_KALLSYMS_ALL=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_ARCH_LAYERSCAPE=y -+CONFIG_ARCH_MXC=y -+CONFIG_ARCH_S32=y -+CONFIG_SOC_S32V234=y -+CONFIG_ARM64_VA_BITS_48=y -+CONFIG_SCHED_MC=y -+CONFIG_NUMA=y -+CONFIG_SECCOMP=y -+CONFIG_KEXEC=y -+CONFIG_CRASH_DUMP=y -+CONFIG_XEN=y -+CONFIG_FORCE_MAX_ZONEORDER=14 -+CONFIG_COMPAT=y -+CONFIG_RANDOMIZE_BASE=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_ARM_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+CONFIG_CPUFREQ_DT=y -+CONFIG_ACPI_CPPC_CPUFREQ=m -+CONFIG_ARM_SCPI_CPUFREQ=y -+CONFIG_ARM_IMX_CPUFREQ_DT=y -+CONFIG_QORIQ_CPUFREQ=y -+CONFIG_ARM_SCPI_PROTOCOL=y -+CONFIG_EFI_CAPSULE_LOADER=y -+CONFIG_IMX_DSP=y -+CONFIG_IMX_SCU=y -+CONFIG_IMX_SCU_PD=y -+CONFIG_IMX_SECO_MU=y -+CONFIG_ACPI=y -+CONFIG_ACPI_APEI=y -+CONFIG_ACPI_APEI_GHES=y -+CONFIG_ACPI_APEI_PCIEAER=y -+CONFIG_ACPI_APEI_MEMORY_FAILURE=y -+CONFIG_ACPI_APEI_EINJ=y -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y -+CONFIG_ARM64_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+CONFIG_CRYPTO_SHA512_ARM64_CE=m -+CONFIG_CRYPTO_SHA3_ARM64=m -+CONFIG_CRYPTO_SM3_ARM64_CE=m -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -+CONFIG_CRYPTO_CHACHA20_NEON=m -+CONFIG_CRYPTO_AES_ARM64_BS=m -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_KSM=y -+CONFIG_MEMORY_FAILURE=y -+CONFIG_TRANSPARENT_HUGEPAGE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IPV6_SIT=m -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC2=y -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_MULTIQ=y -+CONFIG_NET_SCH_CBS=y -+CONFIG_NET_SCH_TAPRIO=y -+CONFIG_NET_SCH_MQPRIO=y -+CONFIG_NET_CLS_BASIC=y -+CONFIG_NET_CLS_TCINDEX=y -+CONFIG_TSN=y -+CONFIG_NET_SWITCHDEV=y -+CONFIG_BPF_JIT=y -+CONFIG_NET_PKTGEN=y -+CONFIG_CAN=m -+CONFIG_CAN_FLEXCAN=m -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+# CONFIG_BT_HS is not set -+# CONFIG_BT_LE is not set -+CONFIG_BT_LEDS=y -+# CONFIG_BT_DEBUGFS is not set -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y -+CONFIG_BT_HCIUART_BCM=y -+CONFIG_BT_HCIUART_QCA=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=y -+CONFIG_NL80211_TESTMODE=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y -+CONFIG_MAC80211_LEDS=y -+CONFIG_NET_9P=y -+CONFIG_NET_9P_VIRTIO=y -+CONFIG_PCI=y -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCI_IOV=y -+CONFIG_HOTPLUG_PCI=y -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCI_XGENE=y -+CONFIG_PCIE_ALTERA=y -+CONFIG_PCIE_ALTERA_MSI=y -+CONFIG_PCI_HOST_THUNDER_PEM=y -+CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCI_IMX6=y -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_PCI_HISI=y -+CONFIG_PCIE_KIRIN=y -+CONFIG_PCIE_LAYERSCAPE_GEN4=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -+CONFIG_BRCMSTB_GISB_ARB=y -+CONFIG_SIMPLE_PM_BUS=y -+CONFIG_VEXPRESS_CONFIG=y -+CONFIG_FSL_MC_BUS=y -+CONFIG_FSL_MC_UAPI_SUPPORT=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_RAW_NAND=y -+CONFIG_MTD_NAND_DENALI_DT=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_SPI_NOR=y -+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_NBD=m -+CONFIG_XEN_BLKDEV_BACKEND=m -+CONFIG_VIRTIO_BLK=y -+CONFIG_BLK_DEV_NVME=y -+CONFIG_SENSORS_FXOS8700=y -+CONFIG_SENSORS_FXAS2100X=y -+CONFIG_SRAM=y -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=m -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_HISI_SAS=y -+CONFIG_SCSI_HISI_SAS_PCI=y -+CONFIG_SCSI_MPT3SAS=m -+CONFIG_SCSI_UFSHCD=y -+CONFIG_SCSI_UFSHCD_PLATFORM=y -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_AHCI_CEVA=y -+CONFIG_AHCI_XGENE=y -+CONFIG_AHCI_QORIQ=y -+CONFIG_SATA_SIL24=y -+CONFIG_PATA_PLATFORM=y -+CONFIG_PATA_OF_PLATFORM=y -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_ZERO=m -+CONFIG_NETDEVICES=y -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_TUN=y -+CONFIG_VETH=m -+CONFIG_VIRTIO_NET=y -+CONFIG_AMD_XGBE=y -+CONFIG_ATL1C=m -+CONFIG_BNX2X=m -+CONFIG_MACB=y -+CONFIG_THUNDER_NIC_PF=y -+CONFIG_FEC=y -+CONFIG_FSL_SDK_DPAA_ETH=y -+CONFIG_FSL_DPAA2_ETH=y -+CONFIG_FSL_ENETC=y -+CONFIG_FSL_ENETC_VF=y -+CONFIG_FSL_ENETC_MDIO=y -+CONFIG_HIX5HD2_GMAC=y -+CONFIG_HNS_DSAF=y -+CONFIG_HNS_ENET=y -+CONFIG_HNS3=y -+CONFIG_HNS3_HCLGE=y -+CONFIG_HNS3_ENET=y -+CONFIG_E1000=y -+CONFIG_E1000E=y -+CONFIG_IGB=y -+CONFIG_IGBVF=y -+CONFIG_MVMDIO=y -+CONFIG_SKY2=y -+CONFIG_MLX4_EN=m -+CONFIG_MLX5_CORE=m -+CONFIG_MLX5_CORE_EN=y -+CONFIG_MSCC_OCELOT_SWITCH=y -+CONFIG_QCOM_EMAC=m -+CONFIG_SMC91X=y -+CONFIG_SMSC911X=y -+CONFIG_STMMAC_ETH=y -+CONFIG_MDIO_BITBANG=y -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_AQUANTIA_PHY=y -+CONFIG_AT803X_PHY=y -+CONFIG_INPHI_PHY=y -+CONFIG_MARVELL_PHY=m -+CONFIG_MARVELL_10G_PHY=m -+CONFIG_MICREL_PHY=y -+CONFIG_MICROSEMI_PHY=y -+CONFIG_NXP_TJA11XX_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_ROCKCHIP_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_PPP=y -+CONFIG_PPP_BSDCOMP=y -+CONFIG_PPP_DEFLATE=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=y -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOE=y -+CONFIG_PPP_ASYNC=y -+CONFIG_PPP_SYNC_TTY=y -+CONFIG_SLHC=y -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_LAN78XX=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_PCIE=y -+CONFIG_HOSTAP=y -+CONFIG_WL18XX=m -+CONFIG_WLCORE_SDIO=m -+CONFIG_IVSHMEM_NET=m -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_ADC=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y -+CONFIG_KEYBOARD_CROS_EC=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_EDT_FT5X06=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_MPL3115=y -+CONFIG_INPUT_ISL29023=y -+# CONFIG_SERIO_SERPORT is not set -+CONFIG_SERIO_AMBAKMI=y -+CONFIG_LEGACY_PTY_COUNT=16 -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DW=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_XILINX_PS_UART=y -+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_SERIAL_FSL_LINFLEXUART=y -+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -+CONFIG_SERIAL_DEV_BUS=y -+CONFIG_VIRTIO_CONSOLE=y -+CONFIG_IPMI_HANDLER=m -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_SI=m -+CONFIG_TCG_TPM=y -+CONFIG_TCG_TIS_I2C_INFINEON=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_DESIGNWARE_PLATFORM=y -+CONFIG_I2C_GPIO=m -+CONFIG_I2C_IMX=y -+CONFIG_I2C_IMX_LPI2C=y -+CONFIG_I2C_RK3X=y -+CONFIG_I2C_RPBUS=y -+CONFIG_I2C_CROS_EC_TUNNEL=y -+CONFIG_I2C_SLAVE=y -+CONFIG_SPI=y -+CONFIG_SPI_FSL_LPSPI=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_SPI_NXP_FLEXSPI=y -+CONFIG_SPI_IMX=y -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_SPI_PL022=y -+CONFIG_SPI_ROCKCHIP=y -+CONFIG_SPI_SPIDEV=y -+CONFIG_SPI_SLAVE=y -+CONFIG_SPI_SLAVE_TIME=y -+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y -+CONFIG_SPMI=y -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_PINCTRL_MAX77620=y -+CONFIG_PINCTRL_IMX8MM=y -+CONFIG_PINCTRL_IMX8MN=y -+CONFIG_PINCTRL_IMX8MP=y -+CONFIG_PINCTRL_IMX8MQ=y -+CONFIG_PINCTRL_IMX8QM=y -+CONFIG_PINCTRL_IMX8QXP=y -+CONFIG_PINCTRL_IMX8DXL=y -+CONFIG_PINCTRL_S32V234=y -+CONFIG_GPIOLIB=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_DWAPB=y -+CONFIG_GPIO_MB86S7X=y -+CONFIG_GPIO_MPC8XXX=y -+CONFIG_GPIO_PL061=y -+CONFIG_GPIO_XGENE=y -+CONFIG_GPIO_MAX732X=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_PCF857X=y -+CONFIG_GPIO_MAX77620=y -+CONFIG_POWER_AVS=y -+CONFIG_POWER_RESET_BRCMSTB=y -+CONFIG_POWER_RESET_VEXPRESS=y -+CONFIG_POWER_RESET_XGENE=y -+CONFIG_POWER_RESET_SYSCON=y -+CONFIG_SYSCON_REBOOT_MODE=y -+CONFIG_BATTERY_SBS=m -+CONFIG_BATTERY_BQ27XXX=y -+CONFIG_SENSORS_ARM_SCPI=y -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_PWM_FAN=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_WRITABLE_TRIPS=y -+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -+CONFIG_CPU_THERMAL=y -+CONFIG_THERMAL_EMULATION=y -+CONFIG_IMX_SC_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_IMX8MM_THERMAL=y -+CONFIG_QORIQ_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_ARM_SP805_WATCHDOG=y -+CONFIG_ARM_SBSA_WATCHDOG=y -+CONFIG_DW_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_IMX_SC_WDT=y -+CONFIG_MFD_BD9571MWV=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_MFD_IMX_AUDIOMIX=y -+CONFIG_MFD_HI6421_PMIC=y -+CONFIG_MFD_MAX77620=y -+CONFIG_MFD_RK808=y -+CONFIG_MFD_SEC_CORE=y -+CONFIG_MFD_ROHM_BD718XX=y -+CONFIG_MFD_PCA9450=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_AXP20X=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_BD9571MWV=y -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_REGULATOR_GPIO=y -+CONFIG_REGULATOR_HI6421V530=y -+CONFIG_REGULATOR_MAX77620=y -+CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_PCA9450=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_QCOM_SPMI=y -+CONFIG_REGULATOR_RK808=y -+CONFIG_REGULATOR_S2MPS11=y -+CONFIG_REGULATOR_VCTRL=m -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_RC_DEVICES=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+# CONFIG_DVB_NET is not set -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MX8_CAPTURE=y -+CONFIG_VIDEO_MXC_CAPTURE=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=y -+CONFIG_MXC_MIPI_CSI=y -+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_OV5640=y -+CONFIG_IMX_DPU_CORE=y -+CONFIG_IMX_LCDIF_CORE=y -+CONFIG_IMX_LCDIFV3_CORE=y -+CONFIG_DRM=y -+CONFIG_DRM_I2C_NXP_TDA998X=m -+CONFIG_DRM_MALI_DISPLAY=m -+CONFIG_DRM_NOUVEAU=m -+CONFIG_DRM_RCAR_LVDS=m -+CONFIG_DRM_PANEL_SIMPLE=y -+CONFIG_DRM_PANEL_LVDS=y -+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y -+CONFIG_DRM_LONTIUM_LT8912=y -+CONFIG_DRM_LOAD_EDID_FIRMWARE=y -+CONFIG_DRM_SII902X=m -+CONFIG_DRM_I2C_ADV7511=y -+CONFIG_DRM_NWL_MIPI_DSI=y -+CONFIG_DRM_CDNS_HDMI_CEC=y -+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m -+CONFIG_DRM_DW_HDMI_GP_AUDIO=y -+CONFIG_DRM_ITE_IT6263=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_TVE=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX_HDMI=y -+CONFIG_DRM_IMX_SEC_DSIM=y -+CONFIG_DRM_IMX_CDNS_MHDP=y -+CONFIG_DRM_IMX_DCSS=y -+CONFIG_DRM_ETNAVIV=m -+CONFIG_DRM_HISI_HIBMC=m -+CONFIG_DRM_HISI_KIRIN=m -+CONFIG_DRM_MXSFB=y -+CONFIG_DRM_PL111=m -+CONFIG_DRM_LIMA=m -+CONFIG_DRM_PANFROST=m -+CONFIG_FB_ARMCLCD=y -+CONFIG_FB_EFI=y -+CONFIG_BACKLIGHT_GENERIC=m -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_DYNAMIC_MINORS=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_SOC_FSL_DAI=m -+CONFIG_SND_SOC_FSL_EASRC=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_AK4458=y -+CONFIG_SND_SOC_IMX_AK5558=y -+CONFIG_SND_SOC_IMX_AK4497=y -+CONFIG_SND_SOC_IMX_WM8960=y -+CONFIG_SND_SOC_IMX_WM8524=y -+CONFIG_SND_SOC_IMX_CS42888=y -+CONFIG_SND_SOC_IMX_MICFIL=y -+CONFIG_SND_SOC_IMX_RPMSG=y -+CONFIG_SND_SOC_IMX_MQS=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_AUDMIX=y -+CONFIG_SND_SOC_IMX_PDM_MIC=y -+CONFIG_SND_SOC_IMX_DSP=y -+CONFIG_SND_SOC_IMX_CDNHDMI=y -+CONFIG_SND_SOC_IMX_XCVR=y -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=m -+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_IMX8_SUPPORT=m -+CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=m -+CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_DMIC=m -+CONFIG_SND_SOC_ES7134=m -+CONFIG_SND_SOC_ES7241=m -+CONFIG_SND_SOC_MAX98357A=m -+CONFIG_SND_SOC_PCM3168A_I2C=m -+CONFIG_SND_SOC_SGTL5000=m -+CONFIG_SND_SOC_SPDIF=m -+CONFIG_SND_SOC_TAS571X=m -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_SND_AUDIO_GRAPH_CARD=y -+CONFIG_I2C_HID=m -+CONFIG_USB=y -+CONFIG_USB_OTG=y -+CONFIG_USB_OTG_WHITELIST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_HCD_TEST_MODE=y -+CONFIG_USB_ACM=m -+CONFIG_USB_WDM=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_ISP1760=y -+CONFIG_USB_TEST=m -+CONFIG_USB_EHSET_TEST_FIXTURE=m -+CONFIG_USB_HSIC_USB3503=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_WWAN=y -+CONFIG_USB_SERIAL_OPTION=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_ULPI=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_SNP_UDC_PLAT=y -+CONFIG_USB_BDC_UDC=y -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_STUSB=y -+CONFIG_TYPEC_SWITCH_GPIO=y -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_ARMMMCI=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ACPI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=y -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+CONFIG_MMC_SDHCI_CADENCE=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MMC_SDHCI_F_SDH30=y -+CONFIG_MMC_SPI=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_EXYNOS=y -+CONFIG_MMC_DW_HI3798CV200=y -+CONFIG_MMC_DW_K3=y -+CONFIG_MMC_SDHCI_XENON=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_PWM=y -+CONFIG_LEDS_SYSCON=y -+CONFIG_LEDS_TRIGGER_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_PANIC=y -+CONFIG_EDAC=y -+CONFIG_EDAC_GHES=y -+CONFIG_EDAC_SYNOPSYS=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_RX8025=y -+CONFIG_RTC_DRV_IMX_SC=y -+CONFIG_DMADEVICES=y -+CONFIG_BCM_SBA_RAID=m -+CONFIG_FSL_EDMA=y -+CONFIG_FSL_EDMA_V3=y -+CONFIG_IMX_SDMA=y -+CONFIG_MV_XOR_V2=y -+CONFIG_MXS_DMA=y -+CONFIG_PL330_DMA=y -+CONFIG_QCOM_HIDMA_MGMT=y -+CONFIG_QCOM_HIDMA=y -+CONFIG_DMATEST=y -+CONFIG_UIO=y -+CONFIG_UIO_PCI_GENERIC=y -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y -+CONFIG_VIRTIO_PCI=y -+CONFIG_VIRTIO_BALLOON=y -+CONFIG_VIRTIO_MMIO=y -+CONFIG_XEN_GNTDEV=y -+CONFIG_XEN_GRANT_DEV_ALLOC=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_IMX_CAPTURE=y -+CONFIG_ION=y -+CONFIG_ION_SYSTEM_HEAP=y -+CONFIG_ION_CMA_HEAP=y -+CONFIG_FSL_DPAA2=y -+CONFIG_FSL_DPAA2_ETHSW=y -+CONFIG_FSL_DPAA2_MAC=y -+CONFIG_FSL_SDK_DPA=y -+CONFIG_FSL_PPFE=y -+CONFIG_FSL_PPFE_UTIL_DISABLED=y -+CONFIG_MFD_CROS_EC=y -+CONFIG_CROS_EC_I2C=y -+CONFIG_CROS_EC_SPI=y -+CONFIG_COMMON_CLK_VERSATILE=y -+CONFIG_CLK_SP810=y -+CONFIG_CLK_VEXPRESS_OSC=y -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCPI=y -+CONFIG_COMMON_CLK_CS2000_CP=y -+CONFIG_COMMON_CLK_S2MPS11=y -+CONFIG_COMMON_CLK_XGENE=y -+CONFIG_COMMON_CLK_PWM=y -+CONFIG_CLK_IMX8MM=y -+CONFIG_CLK_IMX8MN=y -+CONFIG_CLK_IMX8MP=y -+CONFIG_CLK_IMX8MQ=y -+CONFIG_CLK_IMX8QXP=y -+CONFIG_HWSPINLOCK=y -+CONFIG_ARM_MHU=y -+CONFIG_IMX_MBOX=y -+CONFIG_PLATFORM_MHU=y -+CONFIG_ARM_SMMU=y -+CONFIG_ARM_SMMU_V3=y -+CONFIG_REMOTEPROC=y -+CONFIG_RPMSG_QCOM_GLINK_RPM=y -+CONFIG_SOC_BRCMSTB=y -+CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_QIXIS=y -+CONFIG_IMX_SCU_SOC=y -+CONFIG_SOC_TI=y -+CONFIG_EXTCON_USB_GPIO=y -+CONFIG_EXTCON_USBC_CROS_EC=y -+CONFIG_IIO=y -+CONFIG_IMX8QXP_ADC=y -+CONFIG_IIO_CROS_EC_SENSORS_CORE=m -+CONFIG_IIO_CROS_EC_SENSORS=m -+CONFIG_IIO_CROS_EC_LIGHT_PROX=m -+CONFIG_IIO_CROS_EC_BARO=m -+CONFIG_PWM=y -+CONFIG_PWM_CROS_EC=m -+CONFIG_PWM_IMX27=y -+CONFIG_PHY_XGENE=y -+CONFIG_PHY_FSL_IMX8MP_LVDS=y -+CONFIG_PHY_MIXEL_MIPI_DPHY=y -+CONFIG_PHY_SAMSUNG_HDMI_PHY=y -+CONFIG_PHY_QCOM_USB_HS=y -+CONFIG_PHY_SAMSUNG_USB2=y -+CONFIG_FSL_IMX8_DDR_PMU=y -+CONFIG_HISI_PMU=y -+CONFIG_NVMEM_IMX_OCOTP=y -+CONFIG_NVMEM_IMX_OCOTP_SCU=y -+CONFIG_FPGA=y -+CONFIG_FPGA_BRIDGE=m -+CONFIG_ALTERA_FREEZE_BRIDGE=m -+CONFIG_FPGA_REGION=m -+CONFIG_OF_FPGA_REGION=m -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+CONFIG_MUX_MMIO=y -+CONFIG_MXC_SIM=y -+CONFIG_MXC_EMVSIM=y -+CONFIG_MXC_MLB150=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+CONFIG_QUOTA=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_HUGETLBFS=y -+CONFIG_EFIVAR_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_SQUASHFS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_ROOT_NFS=y -+CONFIG_9P_FS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_SECURITY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ECHAINIV=y -+CONFIG_CRYPTO_TLS=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_CFB=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_OFB=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=m -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y -+CONFIG_INDIRECT_PIO=y -+CONFIG_CMA_SIZE_MBYTES=320 -+CONFIG_PRINTK_TIME=y -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_FS=y -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_DEBUG_KERNEL=y -+CONFIG_CRC_CCITT=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_PREEMPT is not set -+# CONFIG_FTRACE is not set -+CONFIG_MEMTEST=y -+CONFIG_CORESIGHT=y -+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -+CONFIG_CORESIGHT_SOURCE_ETM4X=y -diff --git a/arch/arm64/configs/myd_jx8mx_defconfig b/arch/arm64/configs/myd_jx8mx_defconfig -new file mode 100755 -index 000000000..5ec600d4c ---- /dev/null -+++ b/arch/arm64/configs/myd_jx8mx_defconfig -@@ -0,0 +1,1100 @@ -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_AUDIT=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_PREEMPT=y -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_NUMA_BALANCING=y -+CONFIG_MEMCG=y -+CONFIG_MEMCG_SWAP=y -+CONFIG_BLK_CGROUP=y -+CONFIG_CGROUP_PIDS=y -+CONFIG_CGROUP_HUGETLB=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_PERF=y -+CONFIG_USER_NS=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_KALLSYMS_ALL=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_ARCH_AGILEX=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_ARCH_ALPINE=y -+CONFIG_ARCH_BCM2835=y -+CONFIG_ARCH_BCM_IPROC=y -+CONFIG_ARCH_BERLIN=y -+CONFIG_ARCH_BRCMSTB=y -+CONFIG_ARCH_EXYNOS=y -+CONFIG_ARCH_K3=y -+CONFIG_ARCH_LAYERSCAPE=y -+CONFIG_ARCH_LG1K=y -+CONFIG_ARCH_HISI=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_ARCH_MESON=y -+CONFIG_ARCH_MVEBU=y -+CONFIG_ARCH_MXC=y -+CONFIG_ARCH_QCOM=y -+CONFIG_ARCH_RENESAS=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_ARCH_S32=y -+CONFIG_SOC_S32V234=y -+CONFIG_ARCH_SEATTLE=y -+CONFIG_ARCH_STRATIX10=y -+CONFIG_ARCH_SYNQUACER=y -+CONFIG_ARCH_TEGRA=y -+CONFIG_ARCH_SPRD=y -+CONFIG_ARCH_THUNDER=y -+CONFIG_ARCH_THUNDER2=y -+CONFIG_ARCH_UNIPHIER=y -+CONFIG_ARCH_VEXPRESS=y -+CONFIG_ARCH_XGENE=y -+CONFIG_ARCH_ZX=y -+CONFIG_ARCH_ZYNQMP=y -+CONFIG_ARM64_VA_BITS_48=y -+CONFIG_SCHED_MC=y -+CONFIG_NUMA=y -+CONFIG_SECCOMP=y -+CONFIG_KEXEC=y -+CONFIG_CRASH_DUMP=y -+CONFIG_XEN=y -+CONFIG_COMPAT=y -+CONFIG_RANDOMIZE_BASE=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_ARM_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=m -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+CONFIG_CPUFREQ_DT=y -+CONFIG_ACPI_CPPC_CPUFREQ=m -+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -+CONFIG_ARM_SCPI_CPUFREQ=y -+CONFIG_ARM_IMX_CPUFREQ_DT=y -+CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -+CONFIG_ARM_TEGRA186_CPUFREQ=y -+CONFIG_QORIQ_CPUFREQ=y -+CONFIG_ARM_SCPI_PROTOCOL=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_INTEL_STRATIX10_SERVICE=y -+CONFIG_EFI_CAPSULE_LOADER=y -+CONFIG_IMX_DSP=y -+CONFIG_IMX_SCU=y -+CONFIG_IMX_SCU_PD=y -+CONFIG_ACPI=y -+CONFIG_ACPI_APEI=y -+CONFIG_ACPI_APEI_GHES=y -+CONFIG_ACPI_APEI_PCIEAER=y -+CONFIG_ACPI_APEI_MEMORY_FAILURE=y -+CONFIG_ACPI_APEI_EINJ=y -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y -+CONFIG_ARM64_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+CONFIG_CRYPTO_SHA512_ARM64_CE=m -+CONFIG_CRYPTO_SHA3_ARM64=m -+CONFIG_CRYPTO_SM3_ARM64_CE=m -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -+CONFIG_CRYPTO_CHACHA20_NEON=m -+CONFIG_CRYPTO_AES_ARM64_BS=m -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_KSM=y -+CONFIG_MEMORY_FAILURE=y -+CONFIG_TRANSPARENT_HUGEPAGE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IPV6_SIT=m -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC2=y -+CONFIG_TSN=y -+CONFIG_NET_SWITCHDEV=y -+CONFIG_QRTR=m -+CONFIG_QRTR_SMD=m -+CONFIG_QRTR_TUN=m -+CONFIG_BPF_JIT=y -+CONFIG_CAN=m -+CONFIG_CAN_FLEXCAN=m -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+# CONFIG_BT_HS is not set -+# CONFIG_BT_LE is not set -+CONFIG_BT_LEDS=y -+# CONFIG_BT_DEBUGFS is not set -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y -+CONFIG_BT_HCIUART_BCM=y -+CONFIG_BT_HCIUART_QCA=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=y -+CONFIG_NL80211_TESTMODE=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y -+CONFIG_MAC80211_LEDS=y -+CONFIG_NET_9P=y -+CONFIG_NET_9P_VIRTIO=y -+CONFIG_PCI=y -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCI_IOV=y -+CONFIG_HOTPLUG_PCI=y -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_PCI_AARDVARK=y -+CONFIG_PCI_TEGRA=y -+CONFIG_PCIE_RCAR=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCI_XGENE=y -+CONFIG_PCIE_ALTERA=y -+CONFIG_PCIE_ALTERA_MSI=y -+CONFIG_PCI_HOST_THUNDER_PEM=y -+CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCIE_ROCKCHIP_HOST=m -+CONFIG_PCI_IMX6=y -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_PCI_HISI=y -+CONFIG_PCIE_QCOM=y -+CONFIG_PCIE_ARMADA_8K=y -+CONFIG_PCIE_KIRIN=y -+CONFIG_PCIE_HISI_STB=y -+CONFIG_PCIE_TEGRA194=m -+CONFIG_PCIE_LAYERSCAPE_GEN4=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -+CONFIG_HISILICON_LPC=y -+CONFIG_SIMPLE_PM_BUS=y -+CONFIG_FSL_MC_BUS=y -+CONFIG_FSL_MC_UAPI_SUPPORT=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_RAW_NAND=y -+CONFIG_MTD_NAND_DENALI_DT=y -+CONFIG_MTD_NAND_MARVELL=y -+CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_QCOM=y -+CONFIG_MTD_SPI_NOR=y -+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_NBD=m -+CONFIG_VIRTIO_BLK=y -+CONFIG_BLK_DEV_NVME=y -+CONFIG_SENSORS_FXOS8700=y -+CONFIG_SENSORS_FXAS2100X=y -+CONFIG_SRAM=y -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=m -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_HISI_SAS=y -+CONFIG_SCSI_HISI_SAS_PCI=y -+CONFIG_SCSI_MPT3SAS=m -+CONFIG_SCSI_UFSHCD=y -+CONFIG_SCSI_UFSHCD_PLATFORM=y -+CONFIG_SCSI_UFS_QCOM=m -+CONFIG_SCSI_UFS_HISI=y -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_AHCI_CEVA=y -+CONFIG_AHCI_MVEBU=y -+CONFIG_AHCI_XGENE=y -+CONFIG_AHCI_QORIQ=y -+CONFIG_SATA_SIL24=y -+CONFIG_SATA_RCAR=y -+CONFIG_PATA_PLATFORM=y -+CONFIG_PATA_OF_PLATFORM=y -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_ZERO=m -+CONFIG_NETDEVICES=y -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_TUN=y -+CONFIG_VETH=m -+CONFIG_VIRTIO_NET=y -+CONFIG_AMD_XGBE=y -+CONFIG_NET_XGENE=y -+CONFIG_ATL1C=m -+CONFIG_BNX2X=m -+CONFIG_MACB=y -+CONFIG_THUNDER_NIC_PF=y -+CONFIG_FEC=y -+CONFIG_FSL_SDK_DPAA_ETH=y -+CONFIG_FSL_DPAA2_ETH=y -+CONFIG_FSL_ENETC=y -+CONFIG_FSL_ENETC_VF=y -+CONFIG_FSL_ENETC_MDIO=y -+CONFIG_ENETC_TSN=y -+CONFIG_HIX5HD2_GMAC=y -+CONFIG_HNS_DSAF=y -+CONFIG_HNS_ENET=y -+CONFIG_HNS3=y -+CONFIG_HNS3_HCLGE=y -+CONFIG_HNS3_ENET=y -+CONFIG_E1000=y -+CONFIG_E1000E=y -+CONFIG_IGB=y -+CONFIG_IGBVF=y -+CONFIG_MVNETA=y -+CONFIG_MVPP2=y -+CONFIG_SKY2=y -+CONFIG_MLX4_EN=m -+CONFIG_MLX5_CORE=m -+CONFIG_MLX5_CORE_EN=y -+CONFIG_MSCC_OCELOT_SWITCH=y -+CONFIG_QCOM_EMAC=m -+CONFIG_RAVB=y -+CONFIG_SMC91X=y -+CONFIG_SMSC911X=y -+CONFIG_SNI_AVE=y -+CONFIG_SNI_NETSEC=y -+CONFIG_STMMAC_ETH=m -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_AQUANTIA_PHY=y -+CONFIG_AT803X_PHY=y -+CONFIG_INPHI_PHY=y -+CONFIG_MARVELL_PHY=m -+CONFIG_MARVELL_10G_PHY=m -+CONFIG_MESON_GXL_PHY=m -+CONFIG_MICREL_PHY=y -+CONFIG_MICROSEMI_PHY=y -+CONFIG_NXP_TJA11XX_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_ROCKCHIP_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_PPP=y -+CONFIG_PPP_BSDCOMP=y -+CONFIG_PPP_DEFLATE=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=y -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOE=y -+CONFIG_PPP_ASYNC=y -+CONFIG_PPP_SYNC_TTY=y -+CONFIG_SLHC=y -+CONFIG_ATH_COMMON=y -+CONFIG_WLAN_VENDOR_ATH=y -+CONFIG_ATH_DEBUG=y -+CONFIG_ATH10K=y -+CONFIG_ATH10K_CE=y -+CONFIG_ATH10K_PCI=y -+CONFIG_ATH10K_AHB=y -+CONFIG_ATH10K_DEBUGFS=y -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_LAN78XX=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_BCMDHD=m -+CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcmd/fw_bcm43456c5_ag_apsta.bin" -+CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcmd/nvram_ap6256.txt" -+CONFIG_BCMDHD_SDIO=y -+CONFIG_BCMDHD_SDIO_IRQ=y -+CONFIG_HOSTAP=y -+CONFIG_WL18XX=m -+CONFIG_WLCORE_SDIO=m -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_ADC=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y -+CONFIG_KEYBOARD_CROS_EC=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_PM8941_PWRKEY=y -+CONFIG_INPUT_HISI_POWERKEY=y -+CONFIG_INPUT_MPL3115=y -+CONFIG_INPUT_ISL29023=y -+# CONFIG_SERIO_SERPORT is not set -+CONFIG_SERIO_AMBAKMI=y -+CONFIG_LEGACY_PTY_COUNT=16 -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_BCM2835AUX=y -+CONFIG_SERIAL_8250_DW=y -+CONFIG_SERIAL_8250_OMAP=y -+CONFIG_SERIAL_8250_MT6577=y -+CONFIG_SERIAL_8250_UNIPHIER=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_MESON=y -+CONFIG_SERIAL_MESON_CONSOLE=y -+CONFIG_SERIAL_SAMSUNG=y -+CONFIG_SERIAL_SAMSUNG_CONSOLE=y -+CONFIG_SERIAL_TEGRA=y -+CONFIG_SERIAL_TEGRA_TCU=y -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_SH_SCI=y -+CONFIG_SERIAL_MSM=y -+CONFIG_SERIAL_MSM_CONSOLE=y -+CONFIG_SERIAL_QCOM_GENI=y -+CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -+CONFIG_SERIAL_XILINX_PS_UART=y -+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_SERIAL_FSL_LINFLEXUART=y -+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -+CONFIG_SERIAL_MVEBU_UART=y -+CONFIG_SERIAL_DEV_BUS=y -+CONFIG_VIRTIO_CONSOLE=y -+CONFIG_IPMI_HANDLER=m -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_SI=m -+CONFIG_TCG_TPM=y -+CONFIG_TCG_TIS_I2C_INFINEON=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_BCM2835=m -+CONFIG_I2C_DESIGNWARE_PLATFORM=y -+CONFIG_I2C_GPIO=m -+CONFIG_I2C_IMX=y -+CONFIG_I2C_IMX_LPI2C=y -+CONFIG_I2C_MESON=y -+CONFIG_I2C_MV64XXX=y -+CONFIG_I2C_PXA=y -+CONFIG_I2C_QCOM_GENI=m -+CONFIG_I2C_QUP=y -+CONFIG_I2C_RK3X=y -+CONFIG_I2C_RPBUS=y -+CONFIG_I2C_SH_MOBILE=y -+CONFIG_I2C_TEGRA=y -+CONFIG_I2C_UNIPHIER_F=y -+CONFIG_I2C_RCAR=y -+CONFIG_I2C_CROS_EC_TUNNEL=y -+CONFIG_SPI=y -+CONFIG_SPI_ARMADA_3700=y -+CONFIG_SPI_BCM2835=m -+CONFIG_SPI_BCM2835AUX=m -+CONFIG_SPI_FSL_LPSPI=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_SPI_NXP_FLEXSPI=y -+CONFIG_SPI_IMX=y -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_SPI_MESON_SPICC=m -+CONFIG_SPI_MESON_SPIFC=m -+CONFIG_SPI_ORION=y -+CONFIG_SPI_PL022=y -+CONFIG_SPI_ROCKCHIP=y -+CONFIG_SPI_QUP=y -+CONFIG_SPI_S3C64XX=y -+CONFIG_SPI_SUN6I=y -+CONFIG_SPI_SPIDEV=y -+CONFIG_SPI_SLAVE=y -+CONFIG_SPI_SLAVE_TIME=y -+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y -+CONFIG_SPMI=y -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_PINCTRL_MAX77620=y -+CONFIG_PINCTRL_IMX8MM=y -+CONFIG_PINCTRL_IMX8MN=y -+CONFIG_PINCTRL_IMX8MQ=y -+CONFIG_PINCTRL_IMX8QM=y -+CONFIG_PINCTRL_IMX8QXP=y -+CONFIG_PINCTRL_IMX8DXL=y -+CONFIG_PINCTRL_IPQ8074=y -+CONFIG_PINCTRL_MSM8916=y -+CONFIG_PINCTRL_S32V234=y -+CONFIG_PINCTRL_MSM8994=y -+CONFIG_PINCTRL_MSM8996=y -+CONFIG_PINCTRL_MSM8998=y -+CONFIG_PINCTRL_QCS404=y -+CONFIG_PINCTRL_QDF2XXX=y -+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -+CONFIG_PINCTRL_SDM845=y -+CONFIG_PINCTRL_SM8150=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_DWAPB=y -+CONFIG_GPIO_MB86S7X=y -+CONFIG_GPIO_MPC8XXX=y -+CONFIG_GPIO_PL061=y -+CONFIG_GPIO_RCAR=y -+CONFIG_GPIO_UNIPHIER=y -+CONFIG_GPIO_XGENE=y -+CONFIG_GPIO_XGENE_SB=y -+CONFIG_GPIO_MAX732X=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_MAX77620=y -+CONFIG_POWER_AVS=y -+CONFIG_ROCKCHIP_IODOMAIN=y -+CONFIG_POWER_RESET_MSM=y -+CONFIG_POWER_RESET_XGENE=y -+CONFIG_POWER_RESET_SYSCON=y -+CONFIG_SYSCON_REBOOT_MODE=y -+CONFIG_BATTERY_SBS=m -+CONFIG_BATTERY_BQ27XXX=y -+CONFIG_SENSORS_ARM_SCPI=y -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_PWM_FAN=m -+CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_WRITABLE_TRIPS=y -+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -+CONFIG_CPU_THERMAL=y -+CONFIG_THERMAL_EMULATION=y -+CONFIG_IMX_SC_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_IMX8MM_THERMAL=y -+CONFIG_QORIQ_THERMAL=y -+CONFIG_ROCKCHIP_THERMAL=m -+CONFIG_RCAR_THERMAL=y -+CONFIG_RCAR_GEN3_THERMAL=y -+CONFIG_ARMADA_THERMAL=y -+CONFIG_BCM2835_THERMAL=m -+CONFIG_BRCMSTB_THERMAL=m -+CONFIG_EXYNOS_THERMAL=y -+CONFIG_TEGRA_BPMP_THERMAL=m -+CONFIG_QCOM_TSENS=y -+CONFIG_UNIPHIER_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_ARM_SBSA_WATCHDOG=y -+CONFIG_ARM_SP805_WATCHDOG=y -+CONFIG_S3C2410_WATCHDOG=y -+CONFIG_DW_WATCHDOG=y -+CONFIG_SUNXI_WATCHDOG=m -+CONFIG_IMX2_WDT=y -+CONFIG_IMX_SC_WDT=y -+CONFIG_MESON_GXBB_WATCHDOG=m -+CONFIG_MESON_WATCHDOG=m -+CONFIG_RENESAS_WDT=y -+CONFIG_UNIPHIER_WATCHDOG=y -+CONFIG_BCM2835_WDT=y -+CONFIG_MFD_ALTERA_SYSMGR=y -+CONFIG_MFD_BD9571MWV=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_MFD_AXP20X_RSB=y -+CONFIG_MFD_EXYNOS_LPASS=m -+CONFIG_MFD_IMX_AUDIOMIX=y -+CONFIG_MFD_HI6421_PMIC=y -+CONFIG_MFD_HI655X_PMIC=y -+CONFIG_MFD_MAX77620=y -+CONFIG_MFD_SPMI_PMIC=y -+CONFIG_MFD_RK808=y -+CONFIG_MFD_SEC_CORE=y -+CONFIG_MFD_ROHM_BD718XX=y -+CONFIG_MFD_PCA9450=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_AXP20X=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_BD9571MWV=y -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_REGULATOR_GPIO=y -+CONFIG_REGULATOR_HI6421V530=y -+CONFIG_REGULATOR_HI655X=y -+CONFIG_REGULATOR_MAX77620=y -+CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_PCA9450=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_QCOM_RPMH=y -+CONFIG_REGULATOR_QCOM_SMD_RPM=y -+CONFIG_REGULATOR_QCOM_SPMI=y -+CONFIG_REGULATOR_RK808=y -+CONFIG_REGULATOR_S2MPS11=y -+CONFIG_REGULATOR_VCTRL=m -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_RC_DEVICES=y -+CONFIG_IR_MESON=m -+CONFIG_IR_SUNXI=m -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+# CONFIG_DVB_NET is not set -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MX8_CAPTURE=y -+CONFIG_VIDEO_MXC_CAPTURE=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=y -+CONFIG_MXC_MIPI_CSI=y -+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m -+CONFIG_VIDEO_SUN6I_CSI=m -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -+CONFIG_VIDEO_RENESAS_FCP=m -+CONFIG_VIDEO_RENESAS_VSP1=m -+CONFIG_VIDEO_OV5640=y -+CONFIG_IMX_DPU_CORE=y -+CONFIG_IMX_LCDIF_CORE=y -+CONFIG_DRM=y -+CONFIG_DRM_I2C_NXP_TDA998X=m -+CONFIG_DRM_MALI_DISPLAY=m -+CONFIG_DRM_NOUVEAU=m -+CONFIG_DRM_EXYNOS=m -+CONFIG_DRM_EXYNOS5433_DECON=y -+CONFIG_DRM_EXYNOS7_DECON=y -+CONFIG_DRM_EXYNOS_DSI=y -+# CONFIG_DRM_EXYNOS_DP is not set -+CONFIG_DRM_EXYNOS_HDMI=y -+CONFIG_DRM_EXYNOS_MIC=y -+CONFIG_DRM_ROCKCHIP=m -+CONFIG_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_ROCKCHIP_CDN_DP=y -+CONFIG_ROCKCHIP_DW_HDMI=y -+CONFIG_ROCKCHIP_DW_MIPI_DSI=y -+CONFIG_ROCKCHIP_INNO_HDMI=y -+CONFIG_DRM_RCAR_DU=m -+CONFIG_DRM_SUN4I=m -+CONFIG_DRM_SUN8I_DW_HDMI=m -+CONFIG_DRM_SUN8I_MIXER=m -+CONFIG_DRM_MSM=m -+CONFIG_DRM_TEGRA=m -+CONFIG_DRM_PANEL_SIMPLE=y -+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y -+CONFIG_DRM_SII902X=m -+CONFIG_DRM_I2C_ADV7511=y -+CONFIG_DRM_NWL_MIPI_DSI=y -+CONFIG_DRM_CDNS_HDMI_CEC=y -+CONFIG_DRM_ITE_IT6263=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_TVE=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX_HDMI=y -+CONFIG_DRM_IMX_SEC_DSIM=y -+CONFIG_DRM_IMX_CDNS_MHDP=y -+CONFIG_DRM_IMX_DCSS=y -+CONFIG_DRM_VC4=m -+CONFIG_DRM_ETNAVIV=m -+CONFIG_DRM_HISI_HIBMC=m -+CONFIG_DRM_HISI_KIRIN=m -+CONFIG_DRM_MXSFB=y -+CONFIG_DRM_MESON=m -+CONFIG_DRM_PL111=m -+CONFIG_DRM_LIMA=m -+CONFIG_DRM_PANFROST=m -+CONFIG_DRM_PANEL_TC358775_JX8MX_ONLY=y -+CONFIG_FB_ARMCLCD=y -+CONFIG_FB_EFI=y -+CONFIG_BACKLIGHT_GENERIC=m -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_LOGO=y -+CONFIG_CUSTOMER_LOGO_LINUX_CLUT224=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_HDA_TEGRA=m -+CONFIG_SND_HDA_CODEC_HDMI=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_BCM2835_SOC_I2S=m -+CONFIG_SND_SOC_FSL_EASRC=y -+CONFIG_SND_SOC_FSL_DAI=m -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_AK4458=y -+CONFIG_SND_SOC_IMX_AK5558=y -+CONFIG_SND_SOC_IMX_AK4497=y -+CONFIG_SND_SOC_IMX_WM8960=y -+CONFIG_SND_SOC_IMX_WM8904=m -+CONFIG_SND_SOC_WM8904=y -+CONFIG_SND_SOC_IMX_WM8524=y -+CONFIG_SND_SOC_IMX_CS42888=y -+CONFIG_SND_SOC_IMX_MICFIL=y -+CONFIG_SND_SOC_IMX_RPMSG=y -+CONFIG_SND_SOC_IMX_MQS=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_AUDMIX=y -+CONFIG_SND_SOC_IMX_PDM_MIC=y -+CONFIG_SND_SOC_IMX_DSP=y -+CONFIG_SND_SOC_IMX_CDNHDMI=y -+CONFIG_SND_MESON_AXG_SOUND_CARD=m -+CONFIG_SND_SOC_ROCKCHIP=m -+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -+CONFIG_SND_SOC_ROCKCHIP_RT5645=m -+CONFIG_SND_SOC_RK3399_GRU_SOUND=m -+CONFIG_SND_SOC_SAMSUNG=y -+CONFIG_SND_SOC_RCAR=m -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=m -+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y -+CONFIG_SND_SUN4I_SPDIF=m -+CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_ES7134=m -+CONFIG_SND_SOC_ES7241=m -+CONFIG_SND_SOC_PCM3168A_I2C=m -+CONFIG_SND_SOC_SGTL5000=m -+CONFIG_SND_SOC_TAS571X=m -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_SND_AUDIO_GRAPH_CARD=y -+CONFIG_I2C_HID=m -+CONFIG_USB=y -+CONFIG_USB_OTG=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_TEGRA=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_EXYNOS=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_EXYNOS=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_RENESAS_USBHS=m -+CONFIG_USB_ACM=m -+CONFIG_USB_WDM=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_MUSB_SUNXI=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_ISP1760=y -+CONFIG_USB_TEST=m -+CONFIG_USB_EHSET_TEST_FIXTURE=m -+CONFIG_USB_HSIC_USB3503=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_WWAN=y -+CONFIG_USB_SERIAL_OPTION=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_ULPI=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_RENESAS_USBHS_UDC=m -+CONFIG_USB_RENESAS_USB3=m -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_SWITCH_GPIO=y -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_ARMMMCI=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ACPI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=y -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+CONFIG_MMC_SDHCI_CADENCE=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MMC_SDHCI_TEGRA=y -+CONFIG_MMC_SDHCI_F_SDH30=y -+CONFIG_MMC_MESON_GX=y -+CONFIG_MMC_SDHCI_MSM=y -+CONFIG_MMC_SPI=y -+CONFIG_MMC_SDHI=y -+CONFIG_MMC_UNIPHIER=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_EXYNOS=y -+CONFIG_MMC_DW_HI3798CV200=y -+CONFIG_MMC_DW_K3=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SUNXI=y -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_SDHCI_XENON=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_PWM=y -+CONFIG_LEDS_SYSCON=y -+CONFIG_LEDS_TRIGGER_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_PANIC=y -+CONFIG_EDAC=y -+CONFIG_EDAC_GHES=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_RX8025=y -+CONFIG_RTC_DRV_MAX77686=y -+CONFIG_RTC_DRV_RK808=m -+CONFIG_RTC_DRV_PCF85363=y -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_S5M=y -+CONFIG_RTC_DRV_DS3232=y -+CONFIG_RTC_DRV_PCF2127=y -+CONFIG_RTC_DRV_EFI=y -+CONFIG_RTC_DRV_CROS_EC=y -+CONFIG_RTC_DRV_S3C=y -+CONFIG_RTC_DRV_PL031=y -+CONFIG_RTC_DRV_SUN6I=y -+CONFIG_RTC_DRV_ARMADA38X=y -+CONFIG_RTC_DRV_TEGRA=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_IMX_SC=y -+CONFIG_RTC_DRV_XGENE=y -+CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2835=m -+CONFIG_DMA_SUN6I=m -+CONFIG_FSL_EDMA=y -+CONFIG_FSL_EDMA_V3=y -+CONFIG_IMX_SDMA=y -+CONFIG_K3_DMA=y -+CONFIG_MV_XOR=y -+CONFIG_MV_XOR_V2=y -+CONFIG_MXS_DMA=y -+CONFIG_PL330_DMA=y -+CONFIG_TEGRA20_APB_DMA=y -+CONFIG_QCOM_BAM_DMA=y -+CONFIG_QCOM_HIDMA_MGMT=y -+CONFIG_QCOM_HIDMA=y -+CONFIG_RCAR_DMAC=y -+CONFIG_RENESAS_USB_DMAC=m -+CONFIG_DMATEST=y -+CONFIG_UIO=y -+CONFIG_UIO_PCI_GENERIC=y -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y -+CONFIG_VIRTIO_PCI=y -+CONFIG_VIRTIO_BALLOON=y -+CONFIG_VIRTIO_MMIO=y -+CONFIG_XEN_GNTDEV=y -+CONFIG_XEN_GRANT_DEV_ALLOC=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_IMX_CAPTURE=y -+CONFIG_ION=y -+CONFIG_ION_SYSTEM_HEAP=y -+CONFIG_ION_CMA_HEAP=y -+CONFIG_FSL_DPAA2=y -+CONFIG_FSL_DPAA2_ETHSW=y -+CONFIG_FSL_DPAA2_MAC=y -+CONFIG_FSL_SDK_DPA=y -+CONFIG_FSL_PPFE=y -+CONFIG_FSL_PPFE_UTIL_DISABLED=y -+CONFIG_MFD_CROS_EC=y -+CONFIG_CROS_EC_I2C=y -+CONFIG_CROS_EC_SPI=y -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCPI=y -+CONFIG_COMMON_CLK_CS2000_CP=y -+CONFIG_COMMON_CLK_S2MPS11=y -+CONFIG_COMMON_CLK_PWM=y -+CONFIG_CLK_RASPBERRYPI=m -+CONFIG_CLK_IMX8MM=y -+CONFIG_CLK_IMX8MN=y -+CONFIG_CLK_IMX8MQ=y -+CONFIG_CLK_IMX8QXP=y -+CONFIG_TI_SCI_CLK=y -+CONFIG_COMMON_CLK_QCOM=y -+CONFIG_QCOM_A53PLL=y -+CONFIG_QCOM_CLK_APCS_MSM8916=y -+CONFIG_QCOM_CLK_SMD_RPM=y -+CONFIG_QCOM_CLK_RPMH=y -+CONFIG_IPQ_GCC_8074=y -+CONFIG_MSM_GCC_8916=y -+CONFIG_MSM_GCC_8994=y -+CONFIG_MSM_MMCC_8996=y -+CONFIG_MSM_GCC_8998=y -+CONFIG_QCS_GCC_404=y -+CONFIG_SDM_GCC_845=y -+CONFIG_SM_GCC_8150=y -+CONFIG_HWSPINLOCK=y -+CONFIG_HWSPINLOCK_QCOM=y -+CONFIG_ARM_MHU=y -+CONFIG_IMX_MBOX=y -+CONFIG_PLATFORM_MHU=y -+CONFIG_BCM2835_MBOX=y -+CONFIG_QCOM_APCS_IPC=y -+CONFIG_ROCKCHIP_IOMMU=y -+CONFIG_TEGRA_IOMMU_SMMU=y -+CONFIG_ARM_SMMU=y -+CONFIG_ARM_SMMU_V3=y -+CONFIG_QCOM_IOMMU=y -+CONFIG_REMOTEPROC=y -+CONFIG_QCOM_Q6V5_MSS=m -+CONFIG_QCOM_Q6V5_PAS=m -+CONFIG_QCOM_SYSMON=m -+CONFIG_RPMSG_QCOM_GLINK_RPM=y -+CONFIG_RPMSG_QCOM_GLINK_SMEM=m -+CONFIG_RPMSG_QCOM_SMD=y -+CONFIG_RASPBERRYPI_POWER=y -+CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_QIXIS=y -+CONFIG_IMX_SCU_SOC=y -+CONFIG_QCOM_GENI_SE=y -+CONFIG_QCOM_GLINK_SSR=m -+CONFIG_QCOM_RPMH=y -+CONFIG_QCOM_SMEM=y -+CONFIG_QCOM_SMD_RPM=y -+CONFIG_QCOM_SMP2P=y -+CONFIG_QCOM_SMSM=y -+CONFIG_ARCH_R8A774A1=y -+CONFIG_ARCH_R8A774C0=y -+CONFIG_ARCH_R8A7795=y -+CONFIG_ARCH_R8A7796=y -+CONFIG_ARCH_R8A77965=y -+CONFIG_ARCH_R8A77970=y -+CONFIG_ARCH_R8A77980=y -+CONFIG_ARCH_R8A77990=y -+CONFIG_ARCH_R8A77995=y -+CONFIG_ROCKCHIP_PM_DOMAINS=y -+CONFIG_ARCH_TEGRA_132_SOC=y -+CONFIG_ARCH_TEGRA_210_SOC=y -+CONFIG_ARCH_TEGRA_186_SOC=y -+CONFIG_ARCH_TEGRA_194_SOC=y -+CONFIG_ARCH_K3_AM6_SOC=y -+CONFIG_ARCH_K3_J721E_SOC=y -+CONFIG_TI_SCI_PM_DOMAINS=y -+CONFIG_EXTCON_USB_GPIO=y -+CONFIG_EXTCON_USBC_CROS_EC=y -+CONFIG_EXTCON_PTN5150=y -+CONFIG_IIO=y -+CONFIG_EXYNOS_ADC=y -+CONFIG_IMX8QXP_ADC=y -+CONFIG_ROCKCHIP_SARADC=m -+CONFIG_IIO_CROS_EC_SENSORS_CORE=m -+CONFIG_IIO_CROS_EC_SENSORS=m -+CONFIG_IIO_CROS_EC_LIGHT_PROX=m -+CONFIG_IIO_CROS_EC_BARO=m -+CONFIG_PWM=y -+CONFIG_PWM_BCM2835=m -+CONFIG_PWM_CROS_EC=m -+CONFIG_PWM_IMX27=y -+CONFIG_PWM_MESON=m -+CONFIG_PWM_RCAR=m -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_PWM_SAMSUNG=y -+CONFIG_PWM_SUN4I=m -+CONFIG_PWM_TEGRA=m -+CONFIG_RESET_TI_SCI=y -+CONFIG_PHY_XGENE=y -+CONFIG_PHY_SUN4I_USB=y -+CONFIG_PHY_MIXEL_MIPI_DPHY=y -+CONFIG_PHY_HI6220_USB=y -+CONFIG_PHY_HISTB_COMBPHY=y -+CONFIG_PHY_HISI_INNO_USB2=y -+CONFIG_PHY_MVEBU_CP110_COMPHY=y -+CONFIG_PHY_QCOM_QMP=m -+CONFIG_PHY_QCOM_QUSB2=m -+CONFIG_PHY_QCOM_USB_HS=y -+CONFIG_PHY_RCAR_GEN3_PCIE=y -+CONFIG_PHY_RCAR_GEN3_USB2=y -+CONFIG_PHY_RCAR_GEN3_USB3=m -+CONFIG_PHY_ROCKCHIP_EMMC=y -+CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_PCIE=m -+CONFIG_PHY_ROCKCHIP_TYPEC=y -+CONFIG_PHY_UNIPHIER_USB2=y -+CONFIG_PHY_UNIPHIER_USB3=y -+CONFIG_PHY_TEGRA_XUSB=y -+CONFIG_FSL_IMX8_DDR_PMU=y -+CONFIG_HISI_PMU=y -+CONFIG_QCOM_L2_PMU=y -+CONFIG_QCOM_L3_PMU=y -+CONFIG_NVMEM_IMX_OCOTP=y -+CONFIG_NVMEM_IMX_OCOTP_SCU=y -+CONFIG_QCOM_QFPROM=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_NVMEM_SUNXI_SID=y -+CONFIG_UNIPHIER_EFUSE=y -+CONFIG_MESON_EFUSE=m -+CONFIG_FPGA=y -+CONFIG_FPGA_MGR_STRATIX10_SOC=m -+CONFIG_FPGA_BRIDGE=m -+CONFIG_ALTERA_FREEZE_BRIDGE=m -+CONFIG_FPGA_REGION=m -+CONFIG_OF_FPGA_REGION=m -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+CONFIG_MUX_MMIO=y -+CONFIG_MXC_SIM=y -+CONFIG_MXC_EMVSIM=y -+CONFIG_MXC_MLB150=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+CONFIG_QUOTA=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_HUGETLBFS=y -+CONFIG_EFIVAR_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_SQUASHFS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_ROOT_NFS=y -+CONFIG_9P_FS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_SECURITY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_ECHAINIV=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_TLS=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=m -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_SHA3=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y -+CONFIG_CMA_SIZE_MBYTES=320 -+CONFIG_PRINTK_TIME=y -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_FS=y -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_DEBUG_KERNEL=y -+CONFIG_CRC_CCITT=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_PREEMPT is not set -+# CONFIG_FTRACE is not set -+CONFIG_MEMTEST=y -+CONFIG_TYPEC_STUSB=y -+CONFIG_DRM_LONTIUM_LT8912=y -+CONFIG_TOUCHSCREEN_EDT_FT5X06=y -+CONFIG_TOUCHSCREEN_GOODIX=y -+CONFIG_RFKILL=y -+CONFIG_RFKILL_LEDS=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_DRM_LOAD_EDID_FIRMWARE=y -diff --git a/arch/arm64/configs/mys_iot_defconfig b/arch/arm64/configs/mys_iot_defconfig -new file mode 100755 -index 000000000..08174cb88 ---- /dev/null -+++ b/arch/arm64/configs/mys_iot_defconfig -@@ -0,0 +1,1089 @@ -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_AUDIT=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_PREEMPT=y -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_NUMA_BALANCING=y -+CONFIG_MEMCG=y -+CONFIG_MEMCG_SWAP=y -+CONFIG_BLK_CGROUP=y -+CONFIG_CGROUP_PIDS=y -+CONFIG_CGROUP_HUGETLB=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_PERF=y -+CONFIG_USER_NS=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_KALLSYMS_ALL=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_ARCH_AGILEX=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_ARCH_ALPINE=y -+CONFIG_ARCH_BCM2835=y -+CONFIG_ARCH_BCM_IPROC=y -+CONFIG_ARCH_BERLIN=y -+CONFIG_ARCH_BRCMSTB=y -+CONFIG_ARCH_EXYNOS=y -+CONFIG_ARCH_K3=y -+CONFIG_ARCH_LAYERSCAPE=y -+CONFIG_ARCH_LG1K=y -+CONFIG_ARCH_HISI=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_ARCH_MESON=y -+CONFIG_ARCH_MVEBU=y -+CONFIG_ARCH_MXC=y -+CONFIG_ARCH_QCOM=y -+CONFIG_ARCH_RENESAS=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_ARCH_S32=y -+CONFIG_SOC_S32V234=y -+CONFIG_ARCH_SEATTLE=y -+CONFIG_ARCH_STRATIX10=y -+CONFIG_ARCH_SYNQUACER=y -+CONFIG_ARCH_TEGRA=y -+CONFIG_ARCH_SPRD=y -+CONFIG_ARCH_THUNDER=y -+CONFIG_ARCH_THUNDER2=y -+CONFIG_ARCH_UNIPHIER=y -+CONFIG_ARCH_VEXPRESS=y -+CONFIG_ARCH_XGENE=y -+CONFIG_ARCH_ZX=y -+CONFIG_ARCH_ZYNQMP=y -+CONFIG_ARM64_VA_BITS_48=y -+CONFIG_SCHED_MC=y -+CONFIG_NUMA=y -+CONFIG_SECCOMP=y -+CONFIG_KEXEC=y -+CONFIG_CRASH_DUMP=y -+CONFIG_XEN=y -+CONFIG_COMPAT=y -+CONFIG_RANDOMIZE_BASE=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_ARM_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=m -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+CONFIG_CPUFREQ_DT=y -+CONFIG_ACPI_CPPC_CPUFREQ=m -+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -+CONFIG_ARM_SCPI_CPUFREQ=y -+CONFIG_ARM_IMX_CPUFREQ_DT=y -+CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -+CONFIG_ARM_TEGRA186_CPUFREQ=y -+CONFIG_QORIQ_CPUFREQ=y -+CONFIG_ARM_SCPI_PROTOCOL=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_INTEL_STRATIX10_SERVICE=y -+CONFIG_EFI_CAPSULE_LOADER=y -+CONFIG_IMX_DSP=y -+CONFIG_IMX_SCU=y -+CONFIG_IMX_SCU_PD=y -+CONFIG_ACPI=y -+CONFIG_ACPI_APEI=y -+CONFIG_ACPI_APEI_GHES=y -+CONFIG_ACPI_APEI_PCIEAER=y -+CONFIG_ACPI_APEI_MEMORY_FAILURE=y -+CONFIG_ACPI_APEI_EINJ=y -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y -+CONFIG_ARM64_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+CONFIG_CRYPTO_SHA512_ARM64_CE=m -+CONFIG_CRYPTO_SHA3_ARM64=m -+CONFIG_CRYPTO_SM3_ARM64_CE=m -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -+CONFIG_CRYPTO_CHACHA20_NEON=m -+CONFIG_CRYPTO_AES_ARM64_BS=m -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_KSM=y -+CONFIG_MEMORY_FAILURE=y -+CONFIG_TRANSPARENT_HUGEPAGE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IPV6_SIT=m -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC2=y -+CONFIG_TSN=y -+CONFIG_NET_SWITCHDEV=y -+CONFIG_QRTR=m -+CONFIG_QRTR_SMD=m -+CONFIG_QRTR_TUN=m -+CONFIG_BPF_JIT=y -+CONFIG_CAN=m -+CONFIG_CAN_FLEXCAN=m -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+# CONFIG_BT_HS is not set -+# CONFIG_BT_LE is not set -+CONFIG_BT_LEDS=y -+# CONFIG_BT_DEBUGFS is not set -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y -+CONFIG_BT_HCIUART_BCM=y -+CONFIG_BT_HCIUART_QCA=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=y -+CONFIG_NL80211_TESTMODE=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y -+CONFIG_MAC80211_LEDS=y -+CONFIG_NET_9P=y -+CONFIG_NET_9P_VIRTIO=y -+CONFIG_PCI=y -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCI_IOV=y -+CONFIG_HOTPLUG_PCI=y -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_PCI_AARDVARK=y -+CONFIG_PCI_TEGRA=y -+CONFIG_PCIE_RCAR=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCI_XGENE=y -+CONFIG_PCIE_ALTERA=y -+CONFIG_PCIE_ALTERA_MSI=y -+CONFIG_PCI_HOST_THUNDER_PEM=y -+CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCIE_ROCKCHIP_HOST=m -+CONFIG_PCI_IMX6=y -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_PCI_HISI=y -+CONFIG_PCIE_QCOM=y -+CONFIG_PCIE_ARMADA_8K=y -+CONFIG_PCIE_KIRIN=y -+CONFIG_PCIE_HISI_STB=y -+CONFIG_PCIE_TEGRA194=m -+CONFIG_PCIE_LAYERSCAPE_GEN4=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -+CONFIG_HISILICON_LPC=y -+CONFIG_SIMPLE_PM_BUS=y -+CONFIG_FSL_MC_BUS=y -+CONFIG_FSL_MC_UAPI_SUPPORT=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_RAW_NAND=y -+CONFIG_MTD_NAND_DENALI_DT=y -+CONFIG_MTD_NAND_MARVELL=y -+CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_QCOM=y -+CONFIG_MTD_SPI_NOR=y -+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_NBD=m -+CONFIG_VIRTIO_BLK=y -+CONFIG_BLK_DEV_NVME=y -+CONFIG_SENSORS_FXOS8700=y -+CONFIG_SENSORS_FXAS2100X=y -+CONFIG_SRAM=y -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=m -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_HISI_SAS=y -+CONFIG_SCSI_HISI_SAS_PCI=y -+CONFIG_SCSI_MPT3SAS=m -+CONFIG_SCSI_UFSHCD=y -+CONFIG_SCSI_UFSHCD_PLATFORM=y -+CONFIG_SCSI_UFS_QCOM=m -+CONFIG_SCSI_UFS_HISI=y -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_AHCI_CEVA=y -+CONFIG_AHCI_MVEBU=y -+CONFIG_AHCI_XGENE=y -+CONFIG_AHCI_QORIQ=y -+CONFIG_SATA_SIL24=y -+CONFIG_SATA_RCAR=y -+CONFIG_PATA_PLATFORM=y -+CONFIG_PATA_OF_PLATFORM=y -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_ZERO=m -+CONFIG_NETDEVICES=y -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_TUN=y -+CONFIG_VETH=m -+CONFIG_VIRTIO_NET=y -+CONFIG_AMD_XGBE=y -+CONFIG_NET_XGENE=y -+CONFIG_ATL1C=m -+CONFIG_BNX2X=m -+CONFIG_MACB=y -+CONFIG_THUNDER_NIC_PF=y -+CONFIG_FEC=y -+CONFIG_FSL_SDK_DPAA_ETH=y -+CONFIG_FSL_DPAA2_ETH=y -+CONFIG_FSL_ENETC=y -+CONFIG_FSL_ENETC_VF=y -+CONFIG_FSL_ENETC_MDIO=y -+CONFIG_ENETC_TSN=y -+CONFIG_HIX5HD2_GMAC=y -+CONFIG_HNS_DSAF=y -+CONFIG_HNS_ENET=y -+CONFIG_HNS3=y -+CONFIG_HNS3_HCLGE=y -+CONFIG_HNS3_ENET=y -+CONFIG_E1000=y -+CONFIG_E1000E=y -+CONFIG_IGB=y -+CONFIG_IGBVF=y -+CONFIG_MVNETA=y -+CONFIG_MVPP2=y -+CONFIG_SKY2=y -+CONFIG_MLX4_EN=m -+CONFIG_MLX5_CORE=m -+CONFIG_MLX5_CORE_EN=y -+CONFIG_MSCC_OCELOT_SWITCH=y -+CONFIG_QCOM_EMAC=m -+CONFIG_RAVB=y -+CONFIG_SMC91X=y -+CONFIG_SMSC911X=y -+CONFIG_SNI_AVE=y -+CONFIG_SNI_NETSEC=y -+CONFIG_STMMAC_ETH=m -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_AQUANTIA_PHY=y -+CONFIG_AT803X_PHY=y -+CONFIG_INPHI_PHY=y -+CONFIG_MARVELL_PHY=m -+CONFIG_MARVELL_10G_PHY=m -+CONFIG_MESON_GXL_PHY=m -+CONFIG_MICREL_PHY=y -+CONFIG_MICROSEMI_PHY=y -+CONFIG_NXP_TJA11XX_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_ROCKCHIP_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_PPP=y -+CONFIG_PPP_BSDCOMP=y -+CONFIG_PPP_DEFLATE=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=y -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOE=y -+CONFIG_PPP_ASYNC=y -+CONFIG_PPP_SYNC_TTY=y -+CONFIG_SLHC=y -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_LAN78XX=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_BCMDHD=m -+CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcmd/fw_bcm43456c5_ag_apsta.bin" -+CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcmd/nvram_ap6256.txt" -+CONFIG_BCMDHD_SDIO=y -+CONFIG_BCMDHD_SDIO_IRQ=y -+CONFIG_HOSTAP=y -+CONFIG_WL18XX=m -+CONFIG_WLCORE_SDIO=m -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_ADC=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y -+CONFIG_KEYBOARD_CROS_EC=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_PM8941_PWRKEY=y -+CONFIG_INPUT_HISI_POWERKEY=y -+CONFIG_INPUT_MPL3115=y -+CONFIG_INPUT_ISL29023=y -+# CONFIG_SERIO_SERPORT is not set -+CONFIG_SERIO_AMBAKMI=y -+CONFIG_LEGACY_PTY_COUNT=16 -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_BCM2835AUX=y -+CONFIG_SERIAL_8250_DW=y -+CONFIG_SERIAL_8250_OMAP=y -+CONFIG_SERIAL_8250_MT6577=y -+CONFIG_SERIAL_8250_UNIPHIER=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_MESON=y -+CONFIG_SERIAL_MESON_CONSOLE=y -+CONFIG_SERIAL_SAMSUNG=y -+CONFIG_SERIAL_SAMSUNG_CONSOLE=y -+CONFIG_SERIAL_TEGRA=y -+CONFIG_SERIAL_TEGRA_TCU=y -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_SH_SCI=y -+CONFIG_SERIAL_MSM=y -+CONFIG_SERIAL_MSM_CONSOLE=y -+CONFIG_SERIAL_QCOM_GENI=y -+CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -+CONFIG_SERIAL_XILINX_PS_UART=y -+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_SERIAL_FSL_LINFLEXUART=y -+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -+CONFIG_SERIAL_MVEBU_UART=y -+CONFIG_SERIAL_DEV_BUS=y -+CONFIG_VIRTIO_CONSOLE=y -+CONFIG_IPMI_HANDLER=m -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_SI=m -+CONFIG_TCG_TPM=y -+CONFIG_TCG_TIS_I2C_INFINEON=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_BCM2835=m -+CONFIG_I2C_DESIGNWARE_PLATFORM=y -+CONFIG_I2C_GPIO=m -+CONFIG_I2C_IMX=y -+CONFIG_I2C_IMX_LPI2C=y -+CONFIG_I2C_MESON=y -+CONFIG_I2C_MV64XXX=y -+CONFIG_I2C_PXA=y -+CONFIG_I2C_QCOM_GENI=m -+CONFIG_I2C_QUP=y -+CONFIG_I2C_RK3X=y -+CONFIG_I2C_RPBUS=y -+CONFIG_I2C_SH_MOBILE=y -+CONFIG_I2C_TEGRA=y -+CONFIG_I2C_UNIPHIER_F=y -+CONFIG_I2C_RCAR=y -+CONFIG_I2C_CROS_EC_TUNNEL=y -+CONFIG_SPI=y -+CONFIG_SPI_ARMADA_3700=y -+CONFIG_SPI_BCM2835=m -+CONFIG_SPI_BCM2835AUX=m -+CONFIG_SPI_FSL_LPSPI=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_SPI_NXP_FLEXSPI=y -+CONFIG_SPI_IMX=y -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_SPI_MESON_SPICC=m -+CONFIG_SPI_MESON_SPIFC=m -+CONFIG_SPI_ORION=y -+CONFIG_SPI_PL022=y -+CONFIG_SPI_ROCKCHIP=y -+CONFIG_SPI_QUP=y -+CONFIG_SPI_S3C64XX=y -+CONFIG_SPI_SUN6I=y -+CONFIG_SPI_SPIDEV=y -+CONFIG_SPI_SLAVE=y -+CONFIG_SPI_SLAVE_TIME=y -+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y -+CONFIG_SPMI=y -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_PINCTRL_MAX77620=y -+CONFIG_PINCTRL_IMX8MM=y -+CONFIG_PINCTRL_IMX8MN=y -+CONFIG_PINCTRL_IMX8MQ=y -+CONFIG_PINCTRL_IMX8QM=y -+CONFIG_PINCTRL_IMX8QXP=y -+CONFIG_PINCTRL_IMX8DXL=y -+CONFIG_PINCTRL_IPQ8074=y -+CONFIG_PINCTRL_MSM8916=y -+CONFIG_PINCTRL_S32V234=y -+CONFIG_PINCTRL_MSM8994=y -+CONFIG_PINCTRL_MSM8996=y -+CONFIG_PINCTRL_MSM8998=y -+CONFIG_PINCTRL_QCS404=y -+CONFIG_PINCTRL_QDF2XXX=y -+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -+CONFIG_PINCTRL_SDM845=y -+CONFIG_PINCTRL_SM8150=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_DWAPB=y -+CONFIG_GPIO_MB86S7X=y -+CONFIG_GPIO_MPC8XXX=y -+CONFIG_GPIO_PL061=y -+CONFIG_GPIO_RCAR=y -+CONFIG_GPIO_UNIPHIER=y -+CONFIG_GPIO_XGENE=y -+CONFIG_GPIO_XGENE_SB=y -+CONFIG_GPIO_MAX732X=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_MAX77620=y -+CONFIG_POWER_AVS=y -+CONFIG_ROCKCHIP_IODOMAIN=y -+CONFIG_POWER_RESET_MSM=y -+CONFIG_POWER_RESET_XGENE=y -+CONFIG_POWER_RESET_SYSCON=y -+CONFIG_SYSCON_REBOOT_MODE=y -+CONFIG_BATTERY_SBS=m -+CONFIG_BATTERY_BQ27XXX=y -+CONFIG_SENSORS_ARM_SCPI=y -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_PWM_FAN=m -+CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_WRITABLE_TRIPS=y -+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -+CONFIG_CPU_THERMAL=y -+CONFIG_THERMAL_EMULATION=y -+CONFIG_IMX_SC_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_IMX8MM_THERMAL=y -+CONFIG_QORIQ_THERMAL=y -+CONFIG_ROCKCHIP_THERMAL=m -+CONFIG_RCAR_THERMAL=y -+CONFIG_RCAR_GEN3_THERMAL=y -+CONFIG_ARMADA_THERMAL=y -+CONFIG_BCM2835_THERMAL=m -+CONFIG_BRCMSTB_THERMAL=m -+CONFIG_EXYNOS_THERMAL=y -+CONFIG_TEGRA_BPMP_THERMAL=m -+CONFIG_QCOM_TSENS=y -+CONFIG_UNIPHIER_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_ARM_SBSA_WATCHDOG=y -+CONFIG_ARM_SP805_WATCHDOG=y -+CONFIG_S3C2410_WATCHDOG=y -+CONFIG_DW_WATCHDOG=y -+CONFIG_SUNXI_WATCHDOG=m -+CONFIG_IMX2_WDT=y -+CONFIG_IMX_SC_WDT=y -+CONFIG_MESON_GXBB_WATCHDOG=m -+CONFIG_MESON_WATCHDOG=m -+CONFIG_RENESAS_WDT=y -+CONFIG_UNIPHIER_WATCHDOG=y -+CONFIG_BCM2835_WDT=y -+CONFIG_MFD_ALTERA_SYSMGR=y -+CONFIG_MFD_BD9571MWV=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_MFD_AXP20X_RSB=y -+CONFIG_MFD_EXYNOS_LPASS=m -+CONFIG_MFD_IMX_AUDIOMIX=y -+CONFIG_MFD_HI6421_PMIC=y -+CONFIG_MFD_HI655X_PMIC=y -+CONFIG_MFD_MAX77620=y -+CONFIG_MFD_SPMI_PMIC=y -+CONFIG_MFD_RK808=y -+CONFIG_MFD_SEC_CORE=y -+CONFIG_MFD_ROHM_BD718XX=y -+CONFIG_MFD_PCA9450=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_AXP20X=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_BD9571MWV=y -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_REGULATOR_GPIO=y -+CONFIG_REGULATOR_HI6421V530=y -+CONFIG_REGULATOR_HI655X=y -+CONFIG_REGULATOR_MAX77620=y -+CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_PCA9450=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_QCOM_RPMH=y -+CONFIG_REGULATOR_QCOM_SMD_RPM=y -+CONFIG_REGULATOR_QCOM_SPMI=y -+CONFIG_REGULATOR_RK808=y -+CONFIG_REGULATOR_S2MPS11=y -+CONFIG_REGULATOR_VCTRL=m -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_RC_DEVICES=y -+CONFIG_IR_MESON=m -+CONFIG_IR_SUNXI=m -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+# CONFIG_DVB_NET is not set -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MX8_CAPTURE=y -+CONFIG_VIDEO_MXC_CAPTURE=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=y -+CONFIG_MXC_MIPI_CSI=y -+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m -+CONFIG_VIDEO_SUN6I_CSI=m -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -+CONFIG_VIDEO_RENESAS_FCP=m -+CONFIG_VIDEO_RENESAS_VSP1=m -+CONFIG_VIDEO_OV5640=y -+CONFIG_IMX_DPU_CORE=y -+CONFIG_IMX_LCDIF_CORE=y -+CONFIG_DRM=y -+CONFIG_DRM_I2C_NXP_TDA998X=m -+CONFIG_DRM_MALI_DISPLAY=m -+CONFIG_DRM_NOUVEAU=m -+CONFIG_DRM_EXYNOS=m -+CONFIG_DRM_EXYNOS5433_DECON=y -+CONFIG_DRM_EXYNOS7_DECON=y -+CONFIG_DRM_EXYNOS_DSI=y -+# CONFIG_DRM_EXYNOS_DP is not set -+CONFIG_DRM_EXYNOS_HDMI=y -+CONFIG_DRM_EXYNOS_MIC=y -+CONFIG_DRM_ROCKCHIP=m -+CONFIG_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_ROCKCHIP_CDN_DP=y -+CONFIG_ROCKCHIP_DW_HDMI=y -+CONFIG_ROCKCHIP_DW_MIPI_DSI=y -+CONFIG_ROCKCHIP_INNO_HDMI=y -+CONFIG_DRM_RCAR_DU=m -+CONFIG_DRM_SUN4I=m -+CONFIG_DRM_SUN8I_DW_HDMI=m -+CONFIG_DRM_SUN8I_MIXER=m -+CONFIG_DRM_MSM=m -+CONFIG_DRM_TEGRA=m -+CONFIG_DRM_PANEL_SIMPLE=y -+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y -+CONFIG_DRM_SII902X=m -+CONFIG_DRM_I2C_ADV7511=y -+CONFIG_DRM_NWL_MIPI_DSI=y -+CONFIG_DRM_CDNS_HDMI_CEC=y -+CONFIG_DRM_ITE_IT6263=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_TVE=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX_HDMI=y -+CONFIG_DRM_IMX_SEC_DSIM=y -+CONFIG_DRM_IMX_CDNS_MHDP=y -+CONFIG_DRM_IMX_DCSS=y -+CONFIG_DRM_VC4=m -+CONFIG_DRM_ETNAVIV=m -+CONFIG_DRM_HISI_HIBMC=m -+CONFIG_DRM_HISI_KIRIN=m -+CONFIG_DRM_MXSFB=y -+CONFIG_DRM_MESON=m -+CONFIG_DRM_PL111=m -+CONFIG_DRM_LIMA=m -+CONFIG_DRM_PANFROST=m -+CONFIG_FB_ARMCLCD=y -+CONFIG_FB_EFI=y -+CONFIG_BACKLIGHT_GENERIC=m -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_LOGO=y -+CONFIG_CUSTOMER_LOGO_LINUX_CLUT224=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_HDA_TEGRA=m -+CONFIG_SND_HDA_CODEC_HDMI=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_BCM2835_SOC_I2S=m -+CONFIG_SND_SOC_FSL_EASRC=y -+CONFIG_SND_SOC_FSL_DAI=m -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_AK4458=y -+CONFIG_SND_SOC_IMX_AK5558=y -+CONFIG_SND_SOC_IMX_AK4497=y -+CONFIG_SND_SOC_IMX_WM8960=y -+CONFIG_SND_SOC_IMX_WM8524=y -+CONFIG_SND_SOC_IMX_CS42888=y -+CONFIG_SND_SOC_IMX_MICFIL=y -+CONFIG_SND_SOC_IMX_RPMSG=y -+CONFIG_SND_SOC_IMX_MQS=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_AUDMIX=y -+CONFIG_SND_SOC_IMX_PDM_MIC=y -+CONFIG_SND_SOC_IMX_DSP=y -+CONFIG_SND_SOC_IMX_CDNHDMI=y -+CONFIG_SND_MESON_AXG_SOUND_CARD=m -+CONFIG_SND_SOC_ROCKCHIP=m -+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -+CONFIG_SND_SOC_ROCKCHIP_RT5645=m -+CONFIG_SND_SOC_RK3399_GRU_SOUND=m -+CONFIG_SND_SOC_SAMSUNG=y -+CONFIG_SND_SOC_RCAR=m -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=m -+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y -+CONFIG_SND_SUN4I_SPDIF=m -+CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_ES7134=m -+CONFIG_SND_SOC_ES7241=m -+CONFIG_SND_SOC_PCM3168A_I2C=m -+CONFIG_SND_SOC_SGTL5000=m -+CONFIG_SND_SOC_TAS571X=m -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_SND_AUDIO_GRAPH_CARD=y -+CONFIG_I2C_HID=m -+CONFIG_USB=y -+CONFIG_USB_OTG=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_TEGRA=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_EXYNOS=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_EXYNOS=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_RENESAS_USBHS=m -+CONFIG_USB_ACM=m -+CONFIG_USB_WDM=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_MUSB_SUNXI=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_ISP1760=y -+CONFIG_USB_TEST=m -+CONFIG_USB_EHSET_TEST_FIXTURE=m -+CONFIG_USB_HSIC_USB3503=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_WWAN=y -+CONFIG_USB_SERIAL_OPTION=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_ULPI=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_RENESAS_USBHS_UDC=m -+CONFIG_USB_RENESAS_USB3=m -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_SWITCH_GPIO=y -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_ARMMMCI=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ACPI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=y -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+CONFIG_MMC_SDHCI_CADENCE=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MMC_SDHCI_TEGRA=y -+CONFIG_MMC_SDHCI_F_SDH30=y -+CONFIG_MMC_MESON_GX=y -+CONFIG_MMC_SDHCI_MSM=y -+CONFIG_MMC_SPI=y -+CONFIG_MMC_SDHI=y -+CONFIG_MMC_UNIPHIER=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_EXYNOS=y -+CONFIG_MMC_DW_HI3798CV200=y -+CONFIG_MMC_DW_K3=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SUNXI=y -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_SDHCI_XENON=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_PWM=y -+CONFIG_LEDS_SYSCON=y -+CONFIG_LEDS_TRIGGER_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_PANIC=y -+CONFIG_EDAC=y -+CONFIG_EDAC_GHES=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_RX8025=y -+CONFIG_RTC_DRV_MAX77686=y -+CONFIG_RTC_DRV_RK808=m -+CONFIG_RTC_DRV_PCF85363=y -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_S5M=y -+CONFIG_RTC_DRV_DS3232=y -+CONFIG_RTC_DRV_PCF2127=y -+CONFIG_RTC_DRV_EFI=y -+CONFIG_RTC_DRV_CROS_EC=y -+CONFIG_RTC_DRV_S3C=y -+CONFIG_RTC_DRV_PL031=y -+CONFIG_RTC_DRV_SUN6I=y -+CONFIG_RTC_DRV_ARMADA38X=y -+CONFIG_RTC_DRV_TEGRA=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_IMX_SC=y -+CONFIG_RTC_DRV_XGENE=y -+CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2835=m -+CONFIG_DMA_SUN6I=m -+CONFIG_FSL_EDMA=y -+CONFIG_FSL_EDMA_V3=y -+CONFIG_IMX_SDMA=y -+CONFIG_K3_DMA=y -+CONFIG_MV_XOR=y -+CONFIG_MV_XOR_V2=y -+CONFIG_MXS_DMA=y -+CONFIG_PL330_DMA=y -+CONFIG_TEGRA20_APB_DMA=y -+CONFIG_QCOM_BAM_DMA=y -+CONFIG_QCOM_HIDMA_MGMT=y -+CONFIG_QCOM_HIDMA=y -+CONFIG_RCAR_DMAC=y -+CONFIG_RENESAS_USB_DMAC=m -+CONFIG_DMATEST=y -+CONFIG_UIO=y -+CONFIG_UIO_PCI_GENERIC=y -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y -+CONFIG_VIRTIO_PCI=y -+CONFIG_VIRTIO_BALLOON=y -+CONFIG_VIRTIO_MMIO=y -+CONFIG_XEN_GNTDEV=y -+CONFIG_XEN_GRANT_DEV_ALLOC=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_IMX_CAPTURE=y -+CONFIG_ION=y -+CONFIG_ION_SYSTEM_HEAP=y -+CONFIG_ION_CMA_HEAP=y -+CONFIG_FSL_DPAA2=y -+CONFIG_FSL_DPAA2_ETHSW=y -+CONFIG_FSL_DPAA2_MAC=y -+CONFIG_FSL_SDK_DPA=y -+CONFIG_FSL_PPFE=y -+CONFIG_FSL_PPFE_UTIL_DISABLED=y -+CONFIG_MFD_CROS_EC=y -+CONFIG_CROS_EC_I2C=y -+CONFIG_CROS_EC_SPI=y -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCPI=y -+CONFIG_COMMON_CLK_CS2000_CP=y -+CONFIG_COMMON_CLK_S2MPS11=y -+CONFIG_COMMON_CLK_PWM=y -+CONFIG_CLK_RASPBERRYPI=m -+CONFIG_CLK_IMX8MM=y -+CONFIG_CLK_IMX8MN=y -+CONFIG_CLK_IMX8MQ=y -+CONFIG_CLK_IMX8QXP=y -+CONFIG_TI_SCI_CLK=y -+CONFIG_COMMON_CLK_QCOM=y -+CONFIG_QCOM_A53PLL=y -+CONFIG_QCOM_CLK_APCS_MSM8916=y -+CONFIG_QCOM_CLK_SMD_RPM=y -+CONFIG_QCOM_CLK_RPMH=y -+CONFIG_IPQ_GCC_8074=y -+CONFIG_MSM_GCC_8916=y -+CONFIG_MSM_GCC_8994=y -+CONFIG_MSM_MMCC_8996=y -+CONFIG_MSM_GCC_8998=y -+CONFIG_QCS_GCC_404=y -+CONFIG_SDM_GCC_845=y -+CONFIG_SM_GCC_8150=y -+CONFIG_HWSPINLOCK=y -+CONFIG_HWSPINLOCK_QCOM=y -+CONFIG_ARM_MHU=y -+CONFIG_IMX_MBOX=y -+CONFIG_PLATFORM_MHU=y -+CONFIG_BCM2835_MBOX=y -+CONFIG_QCOM_APCS_IPC=y -+CONFIG_ROCKCHIP_IOMMU=y -+CONFIG_TEGRA_IOMMU_SMMU=y -+CONFIG_ARM_SMMU=y -+CONFIG_ARM_SMMU_V3=y -+CONFIG_QCOM_IOMMU=y -+CONFIG_REMOTEPROC=y -+CONFIG_QCOM_Q6V5_MSS=m -+CONFIG_QCOM_Q6V5_PAS=m -+CONFIG_QCOM_SYSMON=m -+CONFIG_RPMSG_QCOM_GLINK_RPM=y -+CONFIG_RPMSG_QCOM_GLINK_SMEM=m -+CONFIG_RPMSG_QCOM_SMD=y -+CONFIG_RASPBERRYPI_POWER=y -+CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_QIXIS=y -+CONFIG_IMX_SCU_SOC=y -+CONFIG_QCOM_GENI_SE=y -+CONFIG_QCOM_GLINK_SSR=m -+CONFIG_QCOM_RPMH=y -+CONFIG_QCOM_SMEM=y -+CONFIG_QCOM_SMD_RPM=y -+CONFIG_QCOM_SMP2P=y -+CONFIG_QCOM_SMSM=y -+CONFIG_ARCH_R8A774A1=y -+CONFIG_ARCH_R8A774C0=y -+CONFIG_ARCH_R8A7795=y -+CONFIG_ARCH_R8A7796=y -+CONFIG_ARCH_R8A77965=y -+CONFIG_ARCH_R8A77970=y -+CONFIG_ARCH_R8A77980=y -+CONFIG_ARCH_R8A77990=y -+CONFIG_ARCH_R8A77995=y -+CONFIG_ROCKCHIP_PM_DOMAINS=y -+CONFIG_ARCH_TEGRA_132_SOC=y -+CONFIG_ARCH_TEGRA_210_SOC=y -+CONFIG_ARCH_TEGRA_186_SOC=y -+CONFIG_ARCH_TEGRA_194_SOC=y -+CONFIG_ARCH_K3_AM6_SOC=y -+CONFIG_ARCH_K3_J721E_SOC=y -+CONFIG_TI_SCI_PM_DOMAINS=y -+CONFIG_EXTCON_USB_GPIO=y -+CONFIG_EXTCON_USBC_CROS_EC=y -+CONFIG_IIO=y -+CONFIG_EXYNOS_ADC=y -+CONFIG_IMX8QXP_ADC=y -+CONFIG_ROCKCHIP_SARADC=m -+CONFIG_IIO_CROS_EC_SENSORS_CORE=m -+CONFIG_IIO_CROS_EC_SENSORS=m -+CONFIG_IIO_CROS_EC_LIGHT_PROX=m -+CONFIG_IIO_CROS_EC_BARO=m -+CONFIG_PWM=y -+CONFIG_PWM_BCM2835=m -+CONFIG_PWM_CROS_EC=m -+CONFIG_PWM_IMX27=y -+CONFIG_PWM_MESON=m -+CONFIG_PWM_RCAR=m -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_PWM_SAMSUNG=y -+CONFIG_PWM_SUN4I=m -+CONFIG_PWM_TEGRA=m -+CONFIG_RESET_TI_SCI=y -+CONFIG_PHY_XGENE=y -+CONFIG_PHY_SUN4I_USB=y -+CONFIG_PHY_MIXEL_MIPI_DPHY=y -+CONFIG_PHY_HI6220_USB=y -+CONFIG_PHY_HISTB_COMBPHY=y -+CONFIG_PHY_HISI_INNO_USB2=y -+CONFIG_PHY_MVEBU_CP110_COMPHY=y -+CONFIG_PHY_QCOM_QMP=m -+CONFIG_PHY_QCOM_QUSB2=m -+CONFIG_PHY_QCOM_USB_HS=y -+CONFIG_PHY_RCAR_GEN3_PCIE=y -+CONFIG_PHY_RCAR_GEN3_USB2=y -+CONFIG_PHY_RCAR_GEN3_USB3=m -+CONFIG_PHY_ROCKCHIP_EMMC=y -+CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_PCIE=m -+CONFIG_PHY_ROCKCHIP_TYPEC=y -+CONFIG_PHY_UNIPHIER_USB2=y -+CONFIG_PHY_UNIPHIER_USB3=y -+CONFIG_PHY_TEGRA_XUSB=y -+CONFIG_FSL_IMX8_DDR_PMU=y -+CONFIG_HISI_PMU=y -+CONFIG_QCOM_L2_PMU=y -+CONFIG_QCOM_L3_PMU=y -+CONFIG_NVMEM_IMX_OCOTP=y -+CONFIG_NVMEM_IMX_OCOTP_SCU=y -+CONFIG_QCOM_QFPROM=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_NVMEM_SUNXI_SID=y -+CONFIG_UNIPHIER_EFUSE=y -+CONFIG_MESON_EFUSE=m -+CONFIG_FPGA=y -+CONFIG_FPGA_MGR_STRATIX10_SOC=m -+CONFIG_FPGA_BRIDGE=m -+CONFIG_ALTERA_FREEZE_BRIDGE=m -+CONFIG_FPGA_REGION=m -+CONFIG_OF_FPGA_REGION=m -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+CONFIG_MUX_MMIO=y -+CONFIG_MXC_SIM=y -+CONFIG_MXC_EMVSIM=y -+CONFIG_MXC_MLB150=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+CONFIG_QUOTA=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_HUGETLBFS=y -+CONFIG_EFIVAR_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_SQUASHFS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_ROOT_NFS=y -+CONFIG_9P_FS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_SECURITY=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_ECHAINIV=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_TLS=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=m -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_SHA3=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y -+CONFIG_CMA_SIZE_MBYTES=320 -+CONFIG_PRINTK_TIME=y -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_FS=y -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_DEBUG_KERNEL=y -+CONFIG_CRC_CCITT=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_PREEMPT is not set -+# CONFIG_FTRACE is not set -+CONFIG_MEMTEST=y -+CONFIG_TYPEC_STUSB=y -+CONFIG_DRM_LONTIUM_LT8912=y -+CONFIG_TOUCHSCREEN_EDT_FT5X06=y -+CONFIG_TOUCHSCREEN_GOODIX=y -+CONFIG_RFKILL=y -+CONFIG_RFKILL_LEDS=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_MOTORCOMM_PHY=y -+CONFIG_EXTCON_PTN5150=y -diff --git a/arch/arm64/configs/rk3568_standard_defconfig b/arch/arm64/configs/rk3568_standard_defconfig -new file mode 100644 -index 000000000..cfbac2bb0 ---- /dev/null -+++ b/arch/arm64/configs/rk3568_standard_defconfig -@@ -0,0 +1,6780 @@ -+# -+# Automatically generated file; DO NOT EDIT. -+# Linux/arm64 5.10.79 Kernel Configuration -+# -+CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Linaro GCC 7.5-2019.12) 7.5.0" -+CONFIG_CC_IS_GCC=y -+CONFIG_GCC_VERSION=70500 -+CONFIG_LD_VERSION=228020000 -+CONFIG_CLANG_VERSION=0 -+CONFIG_LLD_VERSION=0 -+CONFIG_CC_CAN_LINK=y -+CONFIG_CC_CAN_LINK_STATIC=y -+CONFIG_CC_HAS_ASM_GOTO=y -+CONFIG_CC_HAS_ASM_INLINE=y -+CONFIG_IRQ_WORK=y -+CONFIG_BUILDTIME_TABLE_SORT=y -+CONFIG_THREAD_INFO_IN_TASK=y -+ -+# -+# General setup -+# -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+# CONFIG_COMPILE_TEST is not set -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_BUILD_SALT="" -+CONFIG_DEFAULT_INIT="" -+CONFIG_DEFAULT_HOSTNAME="localhost" -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_WATCH_QUEUE is not set -+CONFIG_CROSS_MEMORY_ATTACH=y -+# CONFIG_USELIB is not set -+CONFIG_AUDIT=y -+CONFIG_HAVE_ARCH_AUDITSYSCALL=y -+CONFIG_AUDITSYSCALL=y -+ -+# -+# IRQ subsystem -+# -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_GENERIC_IRQ_SHOW=y -+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -+CONFIG_GENERIC_IRQ_MIGRATION=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_CHIP=y -+CONFIG_IRQ_DOMAIN=y -+CONFIG_IRQ_DOMAIN_HIERARCHY=y -+CONFIG_GENERIC_IRQ_IPI=y -+CONFIG_GENERIC_MSI_IRQ=y -+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -+CONFIG_IRQ_MSI_IOMMU=y -+CONFIG_HANDLE_DOMAIN_IRQ=y -+CONFIG_IRQ_FORCED_THREADING=y -+CONFIG_SPARSE_IRQ=y -+# CONFIG_GENERIC_IRQ_DEBUGFS is not set -+# end of IRQ subsystem -+ -+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -+CONFIG_GENERIC_TIME_VSYSCALL=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_ARCH_HAS_TICK_BROADCAST=y -+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -+ -+# -+# Timers subsystem -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ_COMMON=y -+# CONFIG_HZ_PERIODIC is not set -+CONFIG_NO_HZ_IDLE=y -+# CONFIG_NO_HZ_FULL is not set -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+# end of Timers subsystem -+ -+# CONFIG_PREEMPT_NONE is not set -+CONFIG_PREEMPT_VOLUNTARY=y -+# CONFIG_PREEMPT is not set -+ -+# -+# CPU/Task time and stats accounting -+# -+CONFIG_TICK_CPU_ACCOUNTING=y -+CONFIG_SCHED_WALT=y -+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -+# CONFIG_IRQ_TIME_ACCOUNTING is not set -+CONFIG_SCHED_THERMAL_PRESSURE=y -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_TASKSTATS is not set -+CONFIG_PSI=y -+# end of CPU/Task time and stats accounting -+ -+CONFIG_CPU_ISOLATION=y -+CONFIG_SCHED_RUNNING_AVG=y -+CONFIG_CPU_ISOLATION_OPT=y -+CONFIG_SCHED_CORE_CTRL=y -+ -+# -+# RCU Subsystem -+# -+CONFIG_TREE_RCU=y -+# CONFIG_RCU_EXPERT is not set -+CONFIG_SRCU=y -+CONFIG_TREE_SRCU=y -+CONFIG_TASKS_RCU_GENERIC=y -+CONFIG_TASKS_RUDE_RCU=y -+CONFIG_RCU_STALL_COMMON=y -+CONFIG_RCU_NEED_SEGCBLIST=y -+# end of RCU Subsystem -+ -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+# CONFIG_IKHEADERS is not set -+CONFIG_LOG_BUF_SHIFT=18 -+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 -+CONFIG_GENERIC_SCHED_CLOCK=y -+ -+# -+# Scheduler features -+# -+# CONFIG_UCLAMP_TASK is not set -+ -+# -+# Related Thread Group -+# -+CONFIG_SCHED_RTG=y -+CONFIG_SCHED_RTG_DEBUG=y -+CONFIG_SCHED_RTG_CGROUP=y -+CONFIG_SCHED_RTG_FRAME=y -+CONFIG_SCHED_RTG_RT_THREAD_LIMIT=y -+# end of Related Thread Group -+CONFIG_SCHED_EAS=y -+CONFIG_SCHED_RT_CAS=y -+CONFIG_SCHED_RT_ACTIVE_LB=y -+# end of Scheduler features -+ -+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -+CONFIG_CC_HAS_INT128=y -+CONFIG_ARCH_SUPPORTS_INT128=y -+CONFIG_CGROUPS=y -+CONFIG_MEMCG=y -+# CONFIG_BLK_CGROUP is not set -+CONFIG_CGROUP_SCHED=y -+CONFIG_FAIR_GROUP_SCHED=y -+CONFIG_CFS_BANDWIDTH=y -+# CONFIG_RT_GROUP_SCHED is not set -+# CONFIG_CGROUP_PIDS is not set -+# CONFIG_CGROUP_RDMA is not set -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CPUSETS=y -+CONFIG_PROC_PID_CPUSET=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+# CONFIG_CGROUP_PERF is not set -+# CONFIG_CGROUP_DEBUG is not set -+CONFIG_NAMESPACES=y -+CONFIG_UTS_NS=y -+CONFIG_TIME_NS=y -+CONFIG_IPC_NS=y -+CONFIG_USER_NS=y -+CONFIG_PID_NS=y -+CONFIG_NET_NS=y -+# CONFIG_CHECKPOINT_RESTORE is not set -+# CONFIG_SCHED_AUTOGROUP is not set -+# CONFIG_SYSFS_DEPRECATED is not set -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_RD_GZIP=y -+CONFIG_RD_BZIP2=y -+CONFIG_RD_LZMA=y -+CONFIG_RD_XZ=y -+CONFIG_RD_LZO=y -+CONFIG_RD_LZ4=y -+CONFIG_RD_ZSTD=y -+# CONFIG_INITRD_ASYNC is not set -+# CONFIG_BOOT_CONFIG is not set -+# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_LD_ORPHAN_WARN=y -+CONFIG_SYSCTL=y -+CONFIG_HAVE_UID16=y -+CONFIG_SYSCTL_EXCEPTION_TRACE=y -+CONFIG_BPF=y -+CONFIG_EXPERT=y -+CONFIG_UID16=y -+CONFIG_MULTIUSER=y -+# CONFIG_SGETMASK_SYSCALL is not set -+CONFIG_SYSFS_SYSCALL=y -+CONFIG_FHANDLE=y -+CONFIG_POSIX_TIMERS=y -+CONFIG_PRINTK=y -+CONFIG_PRINTK_NMI=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_FUTEX_PI=y -+CONFIG_HAVE_FUTEX_CMPXCHG=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_AIO=y -+CONFIG_IO_URING=y -+CONFIG_ADVISE_SYSCALLS=y -+CONFIG_MEMBARRIER=y -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+CONFIG_KALLSYMS_BASE_RELATIVE=y -+# CONFIG_BPF_SYSCALL is not set -+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -+# CONFIG_USERFAULTFD is not set -+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -+CONFIG_KCMP=y -+CONFIG_RSEQ=y -+# CONFIG_DEBUG_RSEQ is not set -+CONFIG_EMBEDDED=y -+CONFIG_HAVE_PERF_EVENTS=y -+# CONFIG_PC104 is not set -+ -+# -+# Kernel Performance Events And Counters -+# -+CONFIG_PERF_EVENTS=y -+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -+# end of Kernel Performance Events And Counters -+ -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_SLUB_DEBUG=y -+# CONFIG_COMPAT_BRK is not set -+# CONFIG_SLAB is not set -+CONFIG_SLUB=y -+# CONFIG_SLOB is not set -+CONFIG_SLAB_MERGE_DEFAULT=y -+# CONFIG_SLAB_FREELIST_RANDOM is not set -+# CONFIG_SLAB_FREELIST_HARDENED is not set -+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -+CONFIG_SLUB_CPU_PARTIAL=y -+CONFIG_SYSTEM_DATA_VERIFICATION=y -+CONFIG_PROFILING=y -+CONFIG_TRACEPOINTS=y -+# end of General setup -+ -+CONFIG_ARM64=y -+CONFIG_64BIT=y -+CONFIG_MMU=y -+CONFIG_ARM64_PAGE_SHIFT=12 -+CONFIG_ARM64_CONT_PTE_SHIFT=4 -+CONFIG_ARM64_CONT_PMD_SHIFT=4 -+CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -+CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_GENERIC_BUG=y -+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CSUM=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ZONE_DMA=y -+CONFIG_ZONE_DMA32=y -+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -+CONFIG_SMP=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_FIX_EARLYCON_MEM=y -+CONFIG_PGTABLE_LEVELS=3 -+CONFIG_ARCH_SUPPORTS_UPROBES=y -+CONFIG_ARCH_PROC_KCORE_TEXT=y -+ -+# -+# Platform selection -+# -+# CONFIG_ARCH_ACTIONS is not set -+# CONFIG_ARCH_AGILEX is not set -+# CONFIG_ARCH_SUNXI is not set -+# CONFIG_ARCH_ALPINE is not set -+# CONFIG_ARCH_BCM2835 is not set -+# CONFIG_ARCH_BCM_IPROC is not set -+# CONFIG_ARCH_BERLIN is not set -+# CONFIG_ARCH_BITMAIN is not set -+# CONFIG_ARCH_BRCMSTB is not set -+# CONFIG_ARCH_EXYNOS is not set -+# CONFIG_ARCH_SPARX5 is not set -+# CONFIG_ARCH_K3 is not set -+# CONFIG_ARCH_LAYERSCAPE is not set -+# CONFIG_ARCH_LG1K is not set -+# CONFIG_ARCH_HISI is not set -+# CONFIG_ARCH_KEEMBAY is not set -+# CONFIG_ARCH_MEDIATEK is not set -+# CONFIG_ARCH_MESON is not set -+# CONFIG_ARCH_MVEBU is not set -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_QCOM is not set -+# CONFIG_ARCH_REALTEK is not set -+# CONFIG_ARCH_RENESAS is not set -+CONFIG_ARCH_ROCKCHIP=y -+# CONFIG_ARCH_S32 is not set -+# CONFIG_ARCH_SEATTLE is not set -+# CONFIG_ARCH_STRATIX10 is not set -+# CONFIG_ARCH_SYNQUACER is not set -+# CONFIG_ARCH_TEGRA is not set -+# CONFIG_ARCH_SPRD is not set -+# CONFIG_ARCH_THUNDER is not set -+# CONFIG_ARCH_THUNDER2 is not set -+# CONFIG_ARCH_UNIPHIER is not set -+# CONFIG_ARCH_VEXPRESS is not set -+# CONFIG_ARCH_VISCONTI is not set -+# CONFIG_ARCH_XGENE is not set -+# CONFIG_ARCH_ZX is not set -+# CONFIG_ARCH_ZYNQMP is not set -+# end of Platform selection -+ -+# -+# Kernel Features -+# -+ -+# -+# ARM errata workarounds via the alternatives framework -+# -+# CONFIG_ARM64_ERRATUM_826319 is not set -+# CONFIG_ARM64_ERRATUM_827319 is not set -+# CONFIG_ARM64_ERRATUM_824069 is not set -+# CONFIG_ARM64_ERRATUM_819472 is not set -+# CONFIG_ARM64_ERRATUM_832075 is not set -+CONFIG_ARM64_ERRATUM_845719=y -+CONFIG_ARM64_ERRATUM_843419=y -+CONFIG_ARM64_ERRATUM_1024718=y -+CONFIG_ARM64_ERRATUM_1418040=y -+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -+CONFIG_ARM64_ERRATUM_1165522=y -+CONFIG_ARM64_ERRATUM_1319367=y -+CONFIG_ARM64_ERRATUM_1530923=y -+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -+CONFIG_ARM64_ERRATUM_1286807=y -+CONFIG_ARM64_ERRATUM_1463225=y -+CONFIG_ARM64_ERRATUM_1542419=y -+CONFIG_ARM64_ERRATUM_1508412=y -+# CONFIG_CAVIUM_ERRATUM_22375 is not set -+# CONFIG_CAVIUM_ERRATUM_23154 is not set -+CONFIG_CAVIUM_ERRATUM_27456=y -+CONFIG_CAVIUM_ERRATUM_30115=y -+CONFIG_CAVIUM_TX2_ERRATUM_219=y -+CONFIG_FUJITSU_ERRATUM_010001=y -+CONFIG_HISILICON_ERRATUM_161600802=y -+CONFIG_QCOM_FALKOR_ERRATUM_1003=y -+CONFIG_QCOM_FALKOR_ERRATUM_1009=y -+CONFIG_QCOM_QDF2400_ERRATUM_0065=y -+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y -+# end of ARM errata workarounds via the alternatives framework -+ -+CONFIG_ARM64_4K_PAGES=y -+# CONFIG_ARM64_16K_PAGES is not set -+# CONFIG_ARM64_64K_PAGES is not set -+CONFIG_ARM64_VA_BITS_39=y -+# CONFIG_ARM64_VA_BITS_48 is not set -+CONFIG_ARM64_VA_BITS=39 -+CONFIG_ARM64_PA_BITS_48=y -+CONFIG_ARM64_PA_BITS=48 -+# CONFIG_CPU_BIG_ENDIAN is not set -+CONFIG_CPU_LITTLE_ENDIAN=y -+CONFIG_SCHED_MC=y -+# CONFIG_SCHED_SMT is not set -+CONFIG_NR_CPUS=8 -+CONFIG_HOTPLUG_CPU=y -+# CONFIG_NUMA is not set -+# CONFIG_HZ_100 is not set -+# CONFIG_HZ_250 is not set -+CONFIG_HZ_300=y -+# CONFIG_HZ_1000 is not set -+CONFIG_HZ=300 -+CONFIG_SCHED_HRTICK=y -+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -+CONFIG_ARCH_SPARSEMEM_ENABLE=y -+CONFIG_ARCH_SPARSEMEM_DEFAULT=y -+CONFIG_ARCH_SELECT_MEMORY_MODEL=y -+CONFIG_ARCH_FLATMEM_ENABLE=y -+CONFIG_HAVE_ARCH_PFN_VALID=y -+CONFIG_HW_PERF_EVENTS=y -+CONFIG_SYS_SUPPORTS_HUGETLBFS=y -+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -+# CONFIG_PARAVIRT is not set -+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -+# CONFIG_KEXEC is not set -+# CONFIG_KEXEC_FILE is not set -+# CONFIG_CRASH_DUMP is not set -+# CONFIG_XEN is not set -+CONFIG_FORCE_MAX_ZONEORDER=11 -+CONFIG_UNMAP_KERNEL_AT_EL0=y -+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -+# CONFIG_ARM64_SW_TTBR0_PAN is not set -+CONFIG_ARM64_TAGGED_ADDR_ABI=y -+CONFIG_COMPAT=y -+CONFIG_KUSER_HELPERS=y -+CONFIG_ARMV8_DEPRECATED=y -+CONFIG_SWP_EMULATION=y -+CONFIG_CP15_BARRIER_EMULATION=y -+CONFIG_SETEND_EMULATION=y -+ -+# -+# ARMv8.1 architectural features -+# -+CONFIG_ARM64_HW_AFDBM=y -+CONFIG_ARM64_PAN=y -+CONFIG_AS_HAS_LSE_ATOMICS=y -+CONFIG_ARM64_VHE=y -+# end of ARMv8.1 architectural features -+ -+# -+# ARMv8.2 architectural features -+# -+CONFIG_ARM64_UAO=y -+# CONFIG_ARM64_PMEM is not set -+CONFIG_ARM64_RAS_EXTN=y -+CONFIG_ARM64_CNP=y -+# end of ARMv8.2 architectural features -+ -+# -+# ARMv8.3 architectural features -+# -+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y -+CONFIG_AS_HAS_PAC=y -+# end of ARMv8.3 architectural features -+ -+# -+# ARMv8.4 architectural features -+# -+CONFIG_ARM64_AMU_EXTN=y -+# end of ARMv8.4 architectural features -+ -+# -+# ARMv8.5 architectural features -+# -+CONFIG_ARM64_BTI=y -+CONFIG_ARM64_E0PD=y -+CONFIG_ARCH_RANDOM=y -+# end of ARMv8.5 architectural features -+ -+CONFIG_ARM64_SVE=y -+CONFIG_ARM64_MODULE_PLTS=y -+# CONFIG_ARM64_PSEUDO_NMI is not set -+CONFIG_RELOCATABLE=y -+# CONFIG_RANDOMIZE_BASE is not set -+# end of Kernel Features -+ -+# -+# Boot options -+# -+CONFIG_CMDLINE="" -+# CONFIG_EFI is not set -+# end of Boot options -+ -+CONFIG_SYSVIPC_COMPAT=y -+ -+# -+# Power management options -+# -+CONFIG_SUSPEND=y -+CONFIG_SUSPEND_FREEZER=y -+# CONFIG_SUSPEND_SKIP_SYNC is not set -+CONFIG_HIBERNATION=y -+CONFIG_PM_SLEEP=y -+CONFIG_PM_SLEEP_SMP=y -+# CONFIG_PM_AUTOSLEEP is not set -+# CONFIG_PM_WAKELOCKS is not set -+CONFIG_PM=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_ADVANCED_DEBUG=y -+# CONFIG_PM_TEST_SUSPEND is not set -+CONFIG_PM_SLEEP_DEBUG=y -+# CONFIG_DPM_WATCHDOG is not set -+CONFIG_PM_CLK=y -+CONFIG_PM_GENERIC_DOMAINS=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -+CONFIG_PM_GENERIC_DOMAINS_OF=y -+CONFIG_CPU_PM=y -+CONFIG_ENERGY_MODEL=y -+CONFIG_ARCH_HIBERNATION_POSSIBLE=y -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+# end of Power management options -+ -+# -+# CPU Power Management -+# -+ -+# -+# CPU Idle -+# -+CONFIG_CPU_IDLE=y -+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -+# CONFIG_CPU_IDLE_GOV_LADDER is not set -+CONFIG_CPU_IDLE_GOV_MENU=y -+# CONFIG_CPU_IDLE_GOV_TEO is not set -+CONFIG_DT_IDLE_STATES=y -+ -+# -+# ARM CPU Idle Drivers -+# -+CONFIG_ARM_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -+# end of ARM CPU Idle Drivers -+# end of CPU Idle -+ -+# -+# CPU Frequency scaling -+# -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_GOV_ATTR_SET=y -+CONFIG_CPU_FREQ_GOV_COMMON=y -+CONFIG_CPU_FREQ_STAT=y -+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -+ -+# -+# CPU frequency scaling drivers -+# -+CONFIG_CPUFREQ_DT=y -+CONFIG_CPUFREQ_DT_PLATDEV=y -+CONFIG_ARM_ROCKCHIP_CPUFREQ=y -+# CONFIG_ARM_SCMI_CPUFREQ is not set -+# end of CPU Frequency scaling -+# end of CPU Power Management -+ -+# -+# Firmware Drivers -+# -+CONFIG_ARM_SCMI_PROTOCOL=y -+CONFIG_ARM_SCMI_POWER_DOMAIN=y -+# CONFIG_ARM_SCPI_PROTOCOL is not set -+# CONFIG_ARM_SDE_INTERFACE is not set -+# CONFIG_FIRMWARE_MEMMAP is not set -+# CONFIG_FW_CFG_SYSFS is not set -+CONFIG_ROCKCHIP_SIP=y -+# CONFIG_GOOGLE_FIRMWARE is not set -+CONFIG_ARM_PSCI_FW=y -+# CONFIG_ARM_PSCI_CHECKER is not set -+CONFIG_HAVE_ARM_SMCCC=y -+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -+CONFIG_ARM_SMCCC_SOC_ID=y -+ -+# -+# Tegra firmware driver -+# -+# end of Tegra firmware driver -+# end of Firmware Drivers -+ -+# CONFIG_VIRTUALIZATION is not set -+CONFIG_ARM64_CRYPTO=y -+CONFIG_CRYPTO_SHA256_ARM64=y -+# CONFIG_CRYPTO_SHA512_ARM64 is not set -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+# CONFIG_CRYPTO_SHA512_ARM64_CE is not set -+# CONFIG_CRYPTO_SHA3_ARM64 is not set -+# CONFIG_CRYPTO_SM3_ARM64_CE is not set -+# CONFIG_CRYPTO_SM4_ARM64_CE is not set -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set -+CONFIG_CRYPTO_AES_ARM64=y -+CONFIG_CRYPTO_AES_ARM64_CE=y -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -+# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set -+# CONFIG_CRYPTO_CHACHA20_NEON is not set -+# CONFIG_CRYPTO_POLY1305_NEON is not set -+# CONFIG_CRYPTO_NHPOLY1305_NEON is not set -+# CONFIG_CRYPTO_AES_ARM64_BS is not set -+ -+# -+# General architecture-dependent options -+# -+CONFIG_SET_FS=y -+# CONFIG_KPROBES is not set -+# CONFIG_JUMP_LABEL is not set -+CONFIG_UPROBES=y -+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y -+CONFIG_HAVE_NMI=y -+CONFIG_HAVE_ARCH_TRACEHOOK=y -+CONFIG_HAVE_DMA_CONTIGUOUS=y -+CONFIG_GENERIC_SMP_IDLE_THREAD=y -+CONFIG_GENERIC_IDLE_POLL_SETUP=y -+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -+CONFIG_ARCH_HAS_KEEPINITRD=y -+CONFIG_ARCH_HAS_SET_MEMORY=y -+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y -+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -+CONFIG_HAVE_ASM_MODVERSIONS=y -+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -+CONFIG_HAVE_RSEQ=y -+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -+CONFIG_HAVE_HW_BREAKPOINT=y -+CONFIG_HAVE_PERF_REGS=y -+CONFIG_HAVE_PERF_USER_STACK_DUMP=y -+CONFIG_HAVE_ARCH_JUMP_LABEL=y -+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -+CONFIG_MMU_GATHER_TABLE_FREE=y -+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y -+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -+CONFIG_HAVE_CMPXCHG_LOCAL=y -+CONFIG_HAVE_CMPXCHG_DOUBLE=y -+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -+CONFIG_HAVE_ARCH_SECCOMP=y -+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -+CONFIG_SECCOMP=y -+CONFIG_SECCOMP_FILTER=y -+CONFIG_HAVE_ARCH_STACKLEAK=y -+CONFIG_HAVE_STACKPROTECTOR=y -+CONFIG_STACKPROTECTOR=y -+CONFIG_STACKPROTECTOR_STRONG=y -+CONFIG_HAVE_CONTEXT_TRACKING=y -+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -+CONFIG_HAVE_MOVE_PMD=y -+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -+CONFIG_HAVE_ARCH_HUGE_VMAP=y -+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -+CONFIG_MODULES_USE_ELF_RELA=y -+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -+CONFIG_ARCH_MMAP_RND_BITS=18 -+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -+CONFIG_CLONE_BACKWARDS=y -+CONFIG_OLD_SIGSUSPEND3=y -+CONFIG_COMPAT_OLD_SIGACTION=y -+CONFIG_COMPAT_32BIT_TIME=y -+CONFIG_HAVE_ARCH_VMAP_STACK=y -+CONFIG_VMAP_STACK=y -+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -+CONFIG_STRICT_KERNEL_RWX=y -+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -+CONFIG_STRICT_MODULE_RWX=y -+CONFIG_HAVE_ARCH_COMPILER_H=y -+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y -+# CONFIG_LOCK_EVENT_COUNTS is not set -+CONFIG_ARCH_HAS_RELR=y -+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -+ -+# -+# GCOV-based kernel profiling -+# -+# CONFIG_GCOV_KERNEL is not set -+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -+# end of GCOV-based kernel profiling -+ -+CONFIG_HAVE_GCC_PLUGINS=y -+# end of General architecture-dependent options -+ -+CONFIG_RT_MUTEXES=y -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+# CONFIG_MODVERSIONS is not set -+# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_MODULE_SIG is not set -+# CONFIG_MODULE_COMPRESS is not set -+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_TRIM_UNUSED_KSYMS is not set -+CONFIG_MODULES_TREE_LOOKUP=y -+CONFIG_BLOCK=y -+CONFIG_BLK_SCSI_REQUEST=y -+CONFIG_BLK_DEV_BSG=y -+# CONFIG_BLK_DEV_BSGLIB is not set -+# CONFIG_BLK_DEV_INTEGRITY is not set -+# CONFIG_BLK_DEV_ZONED is not set -+# CONFIG_BLK_CMDLINE_PARSER is not set -+# CONFIG_BLK_WBT is not set -+CONFIG_BLK_DEBUG_FS=y -+# CONFIG_BLK_SED_OPAL is not set -+# CONFIG_BLK_INLINE_ENCRYPTION is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_AIX_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+CONFIG_EFI_PARTITION=y -+# CONFIG_SYSV68_PARTITION is not set -+# CONFIG_CMDLINE_PARTITION is not set -+# end of Partition Types -+ -+CONFIG_BLOCK_COMPAT=y -+CONFIG_BLK_MQ_PCI=y -+CONFIG_BLK_PM=y -+ -+# -+# IO Schedulers -+# -+CONFIG_MQ_IOSCHED_DEADLINE=y -+CONFIG_MQ_IOSCHED_KYBER=y -+# CONFIG_IOSCHED_BFQ is not set -+# end of IO Schedulers -+ -+CONFIG_ASN1=y -+CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y -+CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y -+CONFIG_ARCH_INLINE_SPIN_LOCK=y -+CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y -+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y -+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y -+CONFIG_ARCH_INLINE_SPIN_UNLOCK=y -+CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y -+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y -+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y -+CONFIG_ARCH_INLINE_READ_LOCK=y -+CONFIG_ARCH_INLINE_READ_LOCK_BH=y -+CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y -+CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y -+CONFIG_ARCH_INLINE_READ_UNLOCK=y -+CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y -+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y -+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y -+CONFIG_ARCH_INLINE_WRITE_LOCK=y -+CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y -+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y -+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y -+CONFIG_ARCH_INLINE_WRITE_UNLOCK=y -+CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y -+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y -+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y -+CONFIG_UNINLINE_SPIN_UNLOCK=y -+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -+CONFIG_MUTEX_SPIN_ON_OWNER=y -+CONFIG_RWSEM_SPIN_ON_OWNER=y -+CONFIG_LOCK_SPIN_ON_OWNER=y -+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -+CONFIG_QUEUED_SPINLOCKS=y -+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -+CONFIG_QUEUED_RWLOCKS=y -+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y -+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y -+CONFIG_FREEZER=y -+ -+# -+# Executable file formats -+# -+CONFIG_BINFMT_ELF=y -+CONFIG_COMPAT_BINFMT_ELF=y -+CONFIG_ARCH_BINFMT_ELF_STATE=y -+CONFIG_ARCH_HAVE_ELF_PROT=y -+CONFIG_ARCH_USE_GNU_PROPERTY=y -+CONFIG_ELFCORE=y -+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -+CONFIG_BINFMT_SCRIPT=y -+# CONFIG_BINFMT_MISC is not set -+CONFIG_COREDUMP=y -+# end of Executable file formats -+ -+# -+# Memory Management options -+# -+CONFIG_SELECT_MEMORY_MODEL=y -+# CONFIG_FLATMEM_MANUAL is not set -+CONFIG_SPARSEMEM_MANUAL=y -+CONFIG_SPARSEMEM=y -+CONFIG_SPARSEMEM_EXTREME=y -+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -+CONFIG_SPARSEMEM_VMEMMAP=y -+CONFIG_HAVE_FAST_GUP=y -+CONFIG_HOLES_IN_ZONE=y -+CONFIG_ARCH_KEEP_MEMBLOCK=y -+CONFIG_MEMORY_ISOLATION=y -+# CONFIG_MEMORY_HOTPLUG is not set -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+# CONFIG_COMPACTION is not set -+# CONFIG_PAGE_REPORTING is not set -+CONFIG_MIGRATION=y -+CONFIG_CONTIG_ALLOC=y -+CONFIG_PHYS_ADDR_T_64BIT=y -+CONFIG_BOUNCE=y -+# CONFIG_KSM is not set -+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -+# CONFIG_MEMORY_FAILURE is not set -+# CONFIG_TRANSPARENT_HUGEPAGE is not set -+# CONFIG_CLEANCACHE is not set -+# CONFIG_FRONTSWAP is not set -+CONFIG_CMA=y -+CONFIG_CMA_DEBUG=y -+CONFIG_CMA_DEBUGFS=y -+CONFIG_CMA_AREAS=7 -+CONFIG_CMA_REUSE=y -+# CONFIG_ZPOOL is not set -+# CONFIG_ZBUD is not set -+CONFIG_ZSMALLOC=y -+# CONFIG_ZSMALLOC_STAT is not set -+CONFIG_GENERIC_EARLY_IOREMAP=y -+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set -+# CONFIG_IDLE_PAGE_TRACKING is not set -+CONFIG_ARCH_HAS_PTE_DEVMAP=y -+CONFIG_FRAME_VECTOR=y -+# CONFIG_PERCPU_STATS is not set -+# CONFIG_GUP_BENCHMARK is not set -+CONFIG_ARCH_HAS_PTE_SPECIAL=y -+CONFIG_ANON_VMA_NAME=y -+# end of Memory Management options -+ -+CONFIG_NET=y -+CONFIG_COMPAT_NETLINK_MESSAGES=y -+CONFIG_NET_INGRESS=y -+CONFIG_SKB_EXTENSIONS=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+# CONFIG_PACKET_DIAG is not set -+CONFIG_UNIX=y -+CONFIG_UNIX_SCM=y -+# CONFIG_UNIX_DIAG is not set -+CONFIG_TLS=y -+CONFIG_XFRM=y -+CONFIG_XFRM_ALGO=y -+CONFIG_XFRM_USER=y -+# CONFIG_XFRM_INTERFACE is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+# CONFIG_XFRM_STATISTICS is not set -+CONFIG_NET_KEY=y -+# CONFIG_NET_KEY_MIGRATE is not set -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+# CONFIG_IP_FIB_TRIE_STATS is not set -+# CONFIG_IP_MULTIPLE_TABLES is not set -+# CONFIG_IP_ROUTE_MULTIPATH is not set -+# CONFIG_IP_ROUTE_VERBOSE is not set -+# CONFIG_IP_PNP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE_DEMUX is not set -+CONFIG_IP_MROUTE_COMMON=y -+CONFIG_IP_MROUTE=y -+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set -+# CONFIG_IP_PIMSM_V1 is not set -+# CONFIG_IP_PIMSM_V2 is not set -+CONFIG_SYN_COOKIES=y -+# CONFIG_NET_IPVTI is not set -+# CONFIG_NET_FOU is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_DIAG is not set -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+CONFIG_IPV6=y -+# CONFIG_IPV6_ROUTER_PREF is not set -+# CONFIG_IPV6_OPTIMISTIC_DAD is not set -+# CONFIG_INET6_AH is not set -+# CONFIG_INET6_ESP is not set -+# CONFIG_INET6_IPCOMP is not set -+# CONFIG_IPV6_MIP6 is not set -+# CONFIG_IPV6_ILA is not set -+# CONFIG_IPV6_VTI is not set -+# CONFIG_IPV6_SIT is not set -+# CONFIG_IPV6_TUNNEL is not set -+# CONFIG_IPV6_MULTIPLE_TABLES is not set -+# CONFIG_IPV6_MROUTE is not set -+# CONFIG_IPV6_SEG6_LWTUNNEL is not set -+# CONFIG_IPV6_SEG6_HMAC is not set -+# CONFIG_IPV6_RPL_LWTUNNEL is not set -+# CONFIG_NETLABEL is not set -+# CONFIG_MPTCP is not set -+CONFIG_NETWORK_SECMARK=y -+CONFIG_NET_PTP_CLASSIFY=y -+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set -+CONFIG_NETFILTER=y -+CONFIG_NETFILTER_ADVANCED=y -+ -+# -+# Core Netfilter Configuration -+# -+CONFIG_NETFILTER_INGRESS=y -+# CONFIG_NETFILTER_NETLINK_ACCT is not set -+# CONFIG_NETFILTER_NETLINK_QUEUE is not set -+# CONFIG_NETFILTER_NETLINK_LOG is not set -+# CONFIG_NETFILTER_NETLINK_OSF is not set -+# CONFIG_NF_CONNTRACK is not set -+# CONFIG_NF_LOG_NETDEV is not set -+# CONFIG_NF_TABLES is not set -+CONFIG_NETFILTER_XTABLES=y -+ -+# -+# Xtables combined modules -+# -+# CONFIG_NETFILTER_XT_MARK is not set -+ -+# -+# Xtables targets -+# -+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set -+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set -+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -+# CONFIG_NETFILTER_XT_TARGET_HL is not set -+# CONFIG_NETFILTER_XT_TARGET_HMARK is not set -+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set -+# CONFIG_NETFILTER_XT_TARGET_LOG is not set -+# CONFIG_NETFILTER_XT_TARGET_MARK is not set -+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set -+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set -+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set -+# CONFIG_NETFILTER_XT_TARGET_TEE is not set -+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set -+# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set -+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set -+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -+ -+# -+# Xtables matches -+# -+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set -+# CONFIG_NETFILTER_XT_MATCH_BPF is not set -+# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set -+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set -+# CONFIG_NETFILTER_XT_MATCH_CPU is not set -+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set -+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set -+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -+# CONFIG_NETFILTER_XT_MATCH_ECN is not set -+# CONFIG_NETFILTER_XT_MATCH_ESP is not set -+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set -+# CONFIG_NETFILTER_XT_MATCH_HL is not set -+# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set -+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set -+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set -+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set -+# CONFIG_NETFILTER_XT_MATCH_MAC is not set -+# CONFIG_NETFILTER_XT_MATCH_MARK is not set -+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set -+# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set -+# CONFIG_NETFILTER_XT_MATCH_OSF is not set -+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set -+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set -+# CONFIG_NETFILTER_XT_MATCH_REALM is not set -+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set -+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set -+# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set -+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -+# CONFIG_NETFILTER_XT_MATCH_STRING is not set -+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -+# CONFIG_NETFILTER_XT_MATCH_TIME is not set -+# CONFIG_NETFILTER_XT_MATCH_U32 is not set -+# end of Core Netfilter Configuration -+ -+# CONFIG_IP_SET is not set -+# CONFIG_IP_VS is not set -+ -+# -+# IP: Netfilter Configuration -+# -+# CONFIG_NF_SOCKET_IPV4 is not set -+# CONFIG_NF_TPROXY_IPV4 is not set -+# CONFIG_NF_DUP_IPV4 is not set -+# CONFIG_NF_LOG_ARP is not set -+# CONFIG_NF_LOG_IPV4 is not set -+# CONFIG_NF_REJECT_IPV4 is not set -+CONFIG_IP_NF_IPTABLES=y -+# CONFIG_IP_NF_MATCH_AH is not set -+# CONFIG_IP_NF_MATCH_ECN is not set -+# CONFIG_IP_NF_MATCH_RPFILTER is not set -+# CONFIG_IP_NF_MATCH_TTL is not set -+# CONFIG_IP_NF_FILTER is not set -+CONFIG_IP_NF_MANGLE=y -+# CONFIG_IP_NF_TARGET_ECN is not set -+# CONFIG_IP_NF_TARGET_TTL is not set -+# CONFIG_IP_NF_RAW is not set -+# CONFIG_IP_NF_SECURITY is not set -+# CONFIG_IP_NF_ARPTABLES is not set -+# end of IP: Netfilter Configuration -+ -+# -+# IPv6: Netfilter Configuration -+# -+# CONFIG_NF_SOCKET_IPV6 is not set -+# CONFIG_NF_TPROXY_IPV6 is not set -+# CONFIG_NF_DUP_IPV6 is not set -+# CONFIG_NF_REJECT_IPV6 is not set -+# CONFIG_NF_LOG_IPV6 is not set -+# CONFIG_IP6_NF_IPTABLES is not set -+# end of IPv6: Netfilter Configuration -+ -+# CONFIG_BPFILTER is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_RDS is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_L2TP is not set -+# CONFIG_BRIDGE is not set -+CONFIG_HAVE_NET_DSA=y -+# CONFIG_NET_DSA is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_PHONET is not set -+# CONFIG_6LOWPAN is not set -+# CONFIG_IEEE802154 is not set -+# CONFIG_NET_SCHED is not set -+# CONFIG_DCB is not set -+CONFIG_DNS_RESOLVER=y -+# CONFIG_BATMAN_ADV is not set -+# CONFIG_OPENVSWITCH is not set -+# CONFIG_VSOCKETS is not set -+# CONFIG_NETLINK_DIAG is not set -+# CONFIG_MPLS is not set -+# CONFIG_NET_NSH is not set -+# CONFIG_HSR is not set -+# CONFIG_NET_SWITCHDEV is not set -+# CONFIG_NET_L3_MASTER_DEV is not set -+# CONFIG_QRTR is not set -+# CONFIG_NET_NCSI is not set -+CONFIG_RPS=y -+CONFIG_RFS_ACCEL=y -+CONFIG_XPS=y -+# CONFIG_CGROUP_NET_PRIO is not set -+# CONFIG_CGROUP_NET_CLASSID is not set -+CONFIG_NET_RX_BUSY_POLL=y -+CONFIG_BQL=y -+# CONFIG_BPF_JIT is not set -+CONFIG_NET_FLOW_LIMIT=y -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_NET_DROP_MONITOR is not set -+# end of Network testing -+# end of Networking options -+ -+# CONFIG_HAMRADIO is not set -+# CONFIG_CAN is not set -+CONFIG_BT=y -+CONFIG_BT_BREDR=y -+CONFIG_BT_RFCOMM=y -+# CONFIG_BT_RFCOMM_TTY is not set -+# CONFIG_BT_BNEP is not set -+CONFIG_BT_HIDP=y -+# CONFIG_BT_HS is not set -+CONFIG_BT_LE=y -+# CONFIG_BT_LEDS is not set -+# CONFIG_BT_MSFTEXT is not set -+CONFIG_BT_DEBUGFS=y -+# CONFIG_BT_SELFTEST is not set -+ -+# -+# Bluetooth device drivers -+# -+CONFIG_BT_INTEL=y -+CONFIG_BT_BCM=y -+CONFIG_BT_RTL=y -+CONFIG_BT_HCIBTUSB=y -+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set -+CONFIG_BT_HCIBTUSB_BCM=y -+# CONFIG_BT_HCIBTUSB_MTK is not set -+CONFIG_BT_HCIBTUSB_RTL=y -+# CONFIG_BT_HCIBTSDIO is not set -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_H4=y -+# CONFIG_BT_HCIUART_BCSP is not set -+CONFIG_BT_HCIUART_ATH3K=y -+# CONFIG_BT_HCIUART_INTEL is not set -+# CONFIG_BT_HCIUART_AG6XX is not set -+# CONFIG_BT_HCIBCM203X is not set -+# CONFIG_BT_HCIBPA10X is not set -+CONFIG_BT_HCIBFUSB=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_BT_MRVL=y -+CONFIG_BT_MRVL_SDIO=y -+# CONFIG_BT_ATH3K is not set -+# CONFIG_BT_MTKSDIO is not set -+# end of Bluetooth device drivers -+ -+# CONFIG_AF_RXRPC is not set -+# CONFIG_AF_KCM is not set -+CONFIG_WIRELESS=y -+CONFIG_WIRELESS_EXT=y -+CONFIG_WEXT_CORE=y -+CONFIG_WEXT_PROC=y -+CONFIG_WEXT_PRIV=y -+CONFIG_CFG80211=y -+CONFIG_STREAM_PARSER=y -+# CONFIG_NL80211_TESTMODE is not set -+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set -+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y -+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y -+CONFIG_CFG80211_DEFAULT_PS=y -+# CONFIG_CFG80211_DEBUGFS is not set -+CONFIG_CFG80211_CRDA_SUPPORT=y -+# CONFIG_CFG80211_WEXT is not set -+CONFIG_MAC80211=y -+CONFIG_MAC80211_HAS_RC=y -+CONFIG_MAC80211_RC_MINSTREL=y -+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" -+# CONFIG_MAC80211_MESH is not set -+# CONFIG_MAC80211_LEDS is not set -+# CONFIG_MAC80211_DEBUGFS is not set -+# CONFIG_MAC80211_MESSAGE_TRACING is not set -+# CONFIG_MAC80211_DEBUG_MENU is not set -+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -+# CONFIG_WIMAX is not set -+CONFIG_RFKILL=y -+CONFIG_DRIVERS_HDF_LIGHT=y -+# CONFIG_RFKILL_INPUT is not set -+# CONFIG_RFKILL_GPIO is not set -+CONFIG_RFKILL_RK=y -+# CONFIG_NET_9P is not set -+# CONFIG_CAIF is not set -+# CONFIG_CEPH_LIB is not set -+# CONFIG_NFC is not set -+# CONFIG_PSAMPLE is not set -+# CONFIG_NET_IFE is not set -+# CONFIG_LWTUNNEL is not set -+CONFIG_GRO_CELLS=y -+CONFIG_PAGE_POOL=y -+# CONFIG_FAILOVER is not set -+CONFIG_ETHTOOL_NETLINK=y -+CONFIG_HAVE_EBPF_JIT=y -+ -+# -+# Device Drivers -+# -+CONFIG_ARM_AMBA=y -+CONFIG_HAVE_PCI=y -+CONFIG_PCI=y -+CONFIG_PCI_DOMAINS=y -+CONFIG_PCI_DOMAINS_GENERIC=y -+CONFIG_PCI_SYSCALL=y -+CONFIG_PCIEPORTBUS=y -+# CONFIG_PCIEAER is not set -+CONFIG_PCIEASPM=y -+CONFIG_PCIEASPM_DEFAULT=y -+# CONFIG_PCIEASPM_POWERSAVE is not set -+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -+# CONFIG_PCIEASPM_PERFORMANCE is not set -+CONFIG_PCIE_PME=y -+# CONFIG_PCIE_PTM is not set -+CONFIG_PCI_MSI=y -+CONFIG_PCI_MSI_IRQ_DOMAIN=y -+CONFIG_PCI_QUIRKS=y -+# CONFIG_PCI_DEBUG is not set -+# CONFIG_PCI_STUB is not set -+# CONFIG_PCI_IOV is not set -+# CONFIG_PCI_PRI is not set -+# CONFIG_PCI_PASID is not set -+# CONFIG_PCIE_BUS_TUNE_OFF is not set -+CONFIG_PCIE_BUS_DEFAULT=y -+# CONFIG_PCIE_BUS_SAFE is not set -+# CONFIG_PCIE_BUS_PERFORMANCE is not set -+# CONFIG_PCIE_BUS_PEER2PEER is not set -+# CONFIG_HOTPLUG_PCI is not set -+ -+# -+# PCI controller drivers -+# -+# CONFIG_PCI_FTPCI100 is not set -+# CONFIG_PCI_HOST_GENERIC is not set -+# CONFIG_PCIE_XILINX is not set -+# CONFIG_PCI_XGENE is not set -+# CONFIG_PCIE_ALTERA is not set -+# CONFIG_PCI_HOST_THUNDER_PEM is not set -+# CONFIG_PCI_HOST_THUNDER_ECAM is not set -+CONFIG_PCIE_ROCKCHIP=y -+CONFIG_PCIE_ROCKCHIP_HOST=y -+ -+# -+# DesignWare PCI Core Support -+# -+CONFIG_PCIE_DW=y -+CONFIG_PCIE_DW_HOST=y -+# CONFIG_PCIE_DW_PLAT_HOST is not set -+CONFIG_PCIE_DW_ROCKCHIP=y -+# CONFIG_PCI_HISI is not set -+# CONFIG_PCIE_KIRIN is not set -+# CONFIG_PCI_MESON is not set -+# CONFIG_PCIE_AL is not set -+# end of DesignWare PCI Core Support -+ -+# -+# Mobiveil PCIe Core Support -+# -+# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set -+# end of Mobiveil PCIe Core Support -+ -+# -+# Cadence PCIe controllers support -+# -+# CONFIG_PCIE_CADENCE_PLAT_HOST is not set -+# CONFIG_PCI_J721E_HOST is not set -+# end of Cadence PCIe controllers support -+# end of PCI controller drivers -+ -+# -+# PCI Endpoint -+# -+# CONFIG_PCI_ENDPOINT is not set -+# end of PCI Endpoint -+ -+# -+# PCI switch controller drivers -+# -+# CONFIG_PCI_SW_SWITCHTEC is not set -+# end of PCI switch controller drivers -+ -+# CONFIG_PCCARD is not set -+# CONFIG_RAPIDIO is not set -+ -+# -+# Generic Driver Options -+# -+# CONFIG_UEVENT_HELPER is not set -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+ -+# -+# Hyperhold -+# -+CONFIG_HYPERHOLD=y -+CONFIG_HYPERHOLD_DEBUG=y -+CONFIG_HYPERHOLD_ZSWAPD=y -+CONFIG_HYPERHOLD_FILE_LRU=y -+CONFIG_HYPERHOLD_MEMCG=y -+CONFIG_ZRAM_GROUP=y -+CONFIG_ZRAM_GROUP_DEBUG=y -+CONFIG_ZLIST_DEBUG=y -+CONFIG_ZRAM_GROUP_WRITEBACK=y -+ -+# -+# Firmware loader -+# -+CONFIG_FW_LOADER=y -+CONFIG_EXTRA_FIRMWARE="" -+# CONFIG_FW_LOADER_USER_HELPER is not set -+# CONFIG_FW_LOADER_COMPRESS is not set -+CONFIG_FW_CACHE=y -+# end of Firmware loader -+ -+CONFIG_WANT_DEV_COREDUMP=y -+CONFIG_ALLOW_DEV_COREDUMP=y -+CONFIG_DEV_COREDUMP=y -+# CONFIG_DEBUG_DRIVER is not set -+CONFIG_DEBUG_DEVRES=y -+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -+CONFIG_GENERIC_CPU_AUTOPROBE=y -+CONFIG_GENERIC_CPU_VULNERABILITIES=y -+CONFIG_SOC_BUS=y -+CONFIG_REGMAP=y -+CONFIG_REGMAP_I2C=y -+CONFIG_REGMAP_SPI=y -+CONFIG_REGMAP_MMIO=y -+CONFIG_REGMAP_IRQ=y -+CONFIG_DMA_SHARED_BUFFER=y -+# CONFIG_DMA_FENCE_TRACE is not set -+CONFIG_GENERIC_ARCH_TOPOLOGY=y -+# end of Generic Driver Options -+ -+# -+# Bus devices -+# -+# CONFIG_BRCMSTB_GISB_ARB is not set -+# CONFIG_MOXTET is not set -+# CONFIG_SIMPLE_PM_BUS is not set -+# CONFIG_VEXPRESS_CONFIG is not set -+# CONFIG_MHI_BUS is not set -+# end of Bus devices -+ -+CONFIG_CONNECTOR=y -+CONFIG_PROC_EVENTS=y -+# CONFIG_GNSS is not set -+CONFIG_MTD=y -+# CONFIG_MTD_TESTS is not set -+ -+# -+# Partition parsers -+# -+# CONFIG_MTD_AR7_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_OF_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_REDBOOT_PARTS is not set -+# end of Partition parsers -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_SM_FTL is not set -+# CONFIG_MTD_OOPS is not set -+# CONFIG_MTD_SWAP is not set -+# CONFIG_MTD_PARTITIONED_MASTER is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+# CONFIG_MTD_CFI is not set -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+# end of RAM/ROM/Flash chip drivers -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+# CONFIG_MTD_INTEL_VR_NOR is not set -+# CONFIG_MTD_PLATRAM is not set -+# end of Mapping drivers for chip access -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_PMC551 is not set -+# CONFIG_MTD_DATAFLASH is not set -+# CONFIG_MTD_MCHP23K256 is not set -+# CONFIG_MTD_SST25L is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOCG3 is not set -+# end of Self-contained MTD device drivers -+ -+# -+# NAND -+# -+# CONFIG_MTD_ONENAND is not set -+# CONFIG_MTD_RAW_NAND is not set -+# CONFIG_MTD_SPI_NAND is not set -+ -+# -+# ECC engine support -+# -+# end of ECC engine support -+# end of NAND -+ -+# -+# LPDDR & LPDDR2 PCM memory drivers -+# -+# CONFIG_MTD_LPDDR is not set -+# end of LPDDR & LPDDR2 PCM memory drivers -+ -+# CONFIG_MTD_SPI_NOR is not set -+CONFIG_MTD_UBI=y -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_LIMIT=20 -+# CONFIG_MTD_UBI_FASTMAP is not set -+# CONFIG_MTD_UBI_GLUEBI is not set -+# CONFIG_MTD_UBI_BLOCK is not set -+# CONFIG_MTD_HYPERBUS is not set -+CONFIG_DTC=y -+CONFIG_OF=y -+# CONFIG_DTC_SYMBOLS is not set -+# CONFIG_OF_UNITTEST is not set -+CONFIG_OF_FLATTREE=y -+CONFIG_OF_EARLY_FLATTREE=y -+CONFIG_OF_KOBJ=y -+CONFIG_OF_ADDRESS=y -+CONFIG_OF_IRQ=y -+CONFIG_OF_NET=y -+CONFIG_OF_RESERVED_MEM=y -+# CONFIG_OF_OVERLAY is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_DEV_NULL_BLK is not set -+CONFIG_CDROM=y -+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -+CONFIG_ZRAM=y -+# CONFIG_ZRAM_WRITEBACK is not set -+# CONFIG_ZRAM_MEMORY_TRACKING is not set -+# CONFIG_BLK_DEV_UMEM is not set -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+# CONFIG_BLK_DEV_DRBD is not set -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_SKD is not set -+# CONFIG_BLK_DEV_SX8 is not set -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=1 -+CONFIG_BLK_DEV_RAM_SIZE=4096 -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+# CONFIG_BLK_DEV_RBD is not set -+# CONFIG_BLK_DEV_RSXX is not set -+ -+# -+# NVME Support -+# -+CONFIG_NVME_CORE=y -+CONFIG_BLK_DEV_NVME=y -+# CONFIG_NVME_MULTIPATH is not set -+# CONFIG_NVME_HWMON is not set -+# CONFIG_NVME_FC is not set -+# CONFIG_NVME_TCP is not set -+# CONFIG_NVME_TARGET is not set -+# end of NVME Support -+ -+# -+# Misc devices -+# -+# CONFIG_AD525X_DPOT is not set -+# CONFIG_DUMMY_IRQ is not set -+# CONFIG_PHANTOM is not set -+# CONFIG_TIFM_CORE is not set -+# CONFIG_ICS932S401 is not set -+# CONFIG_ENCLOSURE_SERVICES is not set -+# CONFIG_HP_ILO is not set -+# CONFIG_APDS9802ALS is not set -+# CONFIG_ISL29003 is not set -+# CONFIG_ISL29020 is not set -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_SENSORS_BH1770 is not set -+# CONFIG_SENSORS_APDS990X is not set -+# CONFIG_HMC6352 is not set -+# CONFIG_DS1682 is not set -+# CONFIG_LATTICE_ECP3_CONFIG is not set -+CONFIG_SRAM=y -+# CONFIG_PCI_ENDPOINT_TEST is not set -+# CONFIG_XILINX_SDFEC is not set -+# CONFIG_PVPANIC is not set -+# CONFIG_HISI_HIKEY_USB is not set -+# CONFIG_C2PORT is not set -+ -+# -+# EEPROM support -+# -+# CONFIG_EEPROM_AT24 is not set -+# CONFIG_EEPROM_AT25 is not set -+# CONFIG_EEPROM_LEGACY is not set -+# CONFIG_EEPROM_MAX6875 is not set -+# CONFIG_EEPROM_93CX6 is not set -+# CONFIG_EEPROM_93XX46 is not set -+# CONFIG_EEPROM_IDT_89HPESX is not set -+# CONFIG_EEPROM_EE1004 is not set -+# end of EEPROM support -+ -+# CONFIG_CB710_CORE is not set -+ -+# -+# Texas Instruments shared transport line discipline -+# -+# CONFIG_TI_ST is not set -+# end of Texas Instruments shared transport line discipline -+ -+# CONFIG_SENSORS_LIS3_SPI is not set -+# CONFIG_SENSORS_LIS3_I2C is not set -+# CONFIG_ALTERA_STAPL is not set -+# CONFIG_GENWQE is not set -+# CONFIG_ECHO is not set -+# CONFIG_MISC_ALCOR_PCI is not set -+# CONFIG_MISC_RTSX_PCI is not set -+# CONFIG_MISC_RTSX_USB is not set -+# CONFIG_HABANA_AI is not set -+# CONFIG_UACCE is not set -+# end of Misc devices -+ -+# -+# SCSI device support -+# -+CONFIG_SCSI_MOD=y -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+CONFIG_SCSI_PROC_FS=y -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+CONFIG_BLK_DEV_SR=y -+# CONFIG_CHR_DEV_SG is not set -+# CONFIG_CHR_DEV_SCH is not set -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+CONFIG_SCSI_SCAN_ASYNC=y -+ -+# -+# SCSI Transports -+# -+CONFIG_SCSI_SPI_ATTRS=y -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+# end of SCSI Transports -+ -+CONFIG_SCSI_LOWLEVEL=y -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_ISCSI_BOOT_SYSFS is not set -+# CONFIG_SCSI_CXGB3_ISCSI is not set -+# CONFIG_SCSI_CXGB4_ISCSI is not set -+# CONFIG_SCSI_BNX2_ISCSI is not set -+# CONFIG_BE2ISCSI is not set -+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -+# CONFIG_SCSI_HPSA is not set -+# CONFIG_SCSI_3W_9XXX is not set -+# CONFIG_SCSI_3W_SAS is not set -+# CONFIG_SCSI_ACARD is not set -+# CONFIG_SCSI_AACRAID is not set -+# CONFIG_SCSI_AIC7XXX is not set -+# CONFIG_SCSI_AIC79XX is not set -+# CONFIG_SCSI_AIC94XX is not set -+# CONFIG_SCSI_HISI_SAS is not set -+# CONFIG_SCSI_MVSAS is not set -+# CONFIG_SCSI_MVUMI is not set -+# CONFIG_SCSI_ADVANSYS is not set -+# CONFIG_SCSI_ARCMSR is not set -+# CONFIG_SCSI_ESAS2R is not set -+# CONFIG_MEGARAID_NEWGEN is not set -+# CONFIG_MEGARAID_LEGACY is not set -+# CONFIG_MEGARAID_SAS is not set -+# CONFIG_SCSI_MPT3SAS is not set -+# CONFIG_SCSI_MPT2SAS is not set -+# CONFIG_SCSI_SMARTPQI is not set -+# CONFIG_SCSI_UFSHCD is not set -+# CONFIG_SCSI_HPTIOP is not set -+# CONFIG_SCSI_MYRB is not set -+# CONFIG_SCSI_MYRS is not set -+# CONFIG_SCSI_SNIC is not set -+# CONFIG_SCSI_DMX3191D is not set -+# CONFIG_SCSI_FDOMAIN_PCI is not set -+# CONFIG_SCSI_GDTH is not set -+# CONFIG_SCSI_IPS is not set -+# CONFIG_SCSI_INITIO is not set -+# CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_STEX is not set -+# CONFIG_SCSI_SYM53C8XX_2 is not set -+# CONFIG_SCSI_IPR is not set -+# CONFIG_SCSI_QLOGIC_1280 is not set -+# CONFIG_SCSI_QLA_ISCSI is not set -+# CONFIG_SCSI_DC395x is not set -+# CONFIG_SCSI_AM53C974 is not set -+# CONFIG_SCSI_WD719X is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_PMCRAID is not set -+# CONFIG_SCSI_PM8001 is not set -+# CONFIG_SCSI_DH is not set -+# end of SCSI device support -+ -+CONFIG_HAVE_PATA_PLATFORM=y -+CONFIG_ATA=y -+CONFIG_SATA_HOST=y -+CONFIG_ATA_VERBOSE_ERROR=y -+CONFIG_ATA_FORCE=y -+CONFIG_SATA_PMP=y -+ -+# -+# Controllers with non-SFF native interface -+# -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_MOBILE_LPM_POLICY=0 -+CONFIG_SATA_AHCI_PLATFORM=y -+# CONFIG_AHCI_CEVA is not set -+# CONFIG_AHCI_QORIQ is not set -+# CONFIG_SATA_INIC162X is not set -+# CONFIG_SATA_ACARD_AHCI is not set -+# CONFIG_SATA_SIL24 is not set -+# CONFIG_ATA_SFF is not set -+CONFIG_MD=y -+# CONFIG_BLK_DEV_MD is not set -+# CONFIG_BCACHE is not set -+# CONFIG_BLK_DEV_DM is not set -+# CONFIG_TARGET_CORE is not set -+# CONFIG_FUSION is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+# CONFIG_FIREWIRE is not set -+# CONFIG_FIREWIRE_NOSY is not set -+# end of IEEE 1394 (FireWire) support -+ -+CONFIG_NETDEVICES=y -+CONFIG_MII=y -+CONFIG_NET_CORE=y -+# CONFIG_BONDING is not set -+# CONFIG_DUMMY is not set -+# CONFIG_WIREGUARD is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_NET_FC is not set -+# CONFIG_NET_TEAM is not set -+# CONFIG_MACVLAN is not set -+# CONFIG_IPVLAN is not set -+# CONFIG_VXLAN is not set -+# CONFIG_GENEVE is not set -+# CONFIG_BAREUDP is not set -+# CONFIG_GTP is not set -+# CONFIG_MACSEC is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_TUN is not set -+# CONFIG_TUN_VNET_CROSS_LE is not set -+# CONFIG_VETH is not set -+# CONFIG_NLMON is not set -+# CONFIG_ARCNET is not set -+ -+# -+# Distributed Switch Architecture drivers -+# -+# end of Distributed Switch Architecture drivers -+ -+CONFIG_ETHERNET=y -+# CONFIG_NET_VENDOR_3COM is not set -+# CONFIG_NET_VENDOR_ADAPTEC is not set -+# CONFIG_NET_VENDOR_AGERE is not set -+CONFIG_NET_VENDOR_ALACRITECH=y -+# CONFIG_SLICOSS is not set -+# CONFIG_NET_VENDOR_ALTEON is not set -+# CONFIG_ALTERA_TSE is not set -+CONFIG_NET_VENDOR_AMAZON=y -+# CONFIG_ENA_ETHERNET is not set -+# CONFIG_NET_VENDOR_AMD is not set -+CONFIG_NET_VENDOR_AQUANTIA=y -+# CONFIG_AQTION is not set -+# CONFIG_NET_VENDOR_ARC is not set -+# CONFIG_NET_VENDOR_ATHEROS is not set -+CONFIG_NET_VENDOR_AURORA=y -+# CONFIG_AURORA_NB8800 is not set -+# CONFIG_NET_VENDOR_BROADCOM is not set -+# CONFIG_NET_VENDOR_BROCADE is not set -+CONFIG_NET_VENDOR_CADENCE=y -+# CONFIG_MACB is not set -+# CONFIG_NET_VENDOR_CAVIUM is not set -+# CONFIG_NET_VENDOR_CHELSIO is not set -+# CONFIG_NET_VENDOR_CISCO is not set -+CONFIG_NET_VENDOR_CORTINA=y -+# CONFIG_GEMINI_ETHERNET is not set -+# CONFIG_DNET is not set -+# CONFIG_NET_VENDOR_DEC is not set -+# CONFIG_NET_VENDOR_DLINK is not set -+# CONFIG_NET_VENDOR_EMULEX is not set -+# CONFIG_NET_VENDOR_EZCHIP is not set -+CONFIG_NET_VENDOR_GOOGLE=y -+# CONFIG_GVE is not set -+# CONFIG_NET_VENDOR_HISILICON is not set -+CONFIG_NET_VENDOR_HUAWEI=y -+# CONFIG_HINIC is not set -+# CONFIG_NET_VENDOR_INTEL is not set -+# CONFIG_JME is not set -+# CONFIG_NET_VENDOR_MARVELL is not set -+# CONFIG_NET_VENDOR_MELLANOX is not set -+# CONFIG_NET_VENDOR_MICREL is not set -+# CONFIG_NET_VENDOR_MICROCHIP is not set -+CONFIG_NET_VENDOR_MICROSEMI=y -+# CONFIG_NET_VENDOR_MYRI is not set -+# CONFIG_FEALNX is not set -+# CONFIG_NET_VENDOR_NATSEMI is not set -+CONFIG_NET_VENDOR_NETERION=y -+# CONFIG_S2IO is not set -+# CONFIG_VXGE is not set -+CONFIG_NET_VENDOR_NETRONOME=y -+# CONFIG_NFP is not set -+CONFIG_NET_VENDOR_NI=y -+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -+# CONFIG_NET_VENDOR_NVIDIA is not set -+# CONFIG_NET_VENDOR_OKI is not set -+# CONFIG_ETHOC is not set -+CONFIG_NET_VENDOR_PACKET_ENGINES=y -+# CONFIG_HAMACHI is not set -+# CONFIG_YELLOWFIN is not set -+CONFIG_NET_VENDOR_PENSANDO=y -+# CONFIG_IONIC is not set -+# CONFIG_NET_VENDOR_QLOGIC is not set -+# CONFIG_NET_VENDOR_QUALCOMM is not set -+# CONFIG_NET_VENDOR_RDC is not set -+# CONFIG_NET_VENDOR_REALTEK is not set -+# CONFIG_NET_VENDOR_RENESAS is not set -+# CONFIG_NET_VENDOR_ROCKER is not set -+# CONFIG_NET_VENDOR_SAMSUNG is not set -+# CONFIG_NET_VENDOR_SEEQ is not set -+CONFIG_NET_VENDOR_SOLARFLARE=y -+# CONFIG_SFC is not set -+# CONFIG_SFC_FALCON is not set -+# CONFIG_NET_VENDOR_SILAN is not set -+# CONFIG_NET_VENDOR_SIS is not set -+# CONFIG_NET_VENDOR_SMSC is not set -+CONFIG_NET_VENDOR_SOCIONEXT=y -+CONFIG_NET_VENDOR_STMICRO=y -+CONFIG_STMMAC_ETH=y -+# CONFIG_STMMAC_SELFTESTS is not set -+CONFIG_STMMAC_PLATFORM=y -+# CONFIG_DWMAC_DWC_QOS_ETH is not set -+CONFIG_DWMAC_GENERIC=y -+CONFIG_DWMAC_ROCKCHIP=y -+# CONFIG_DWMAC_INTEL_PLAT is not set -+# CONFIG_STMMAC_PCI is not set -+# CONFIG_NET_VENDOR_SUN is not set -+# CONFIG_NET_VENDOR_SYNOPSYS is not set -+# CONFIG_NET_VENDOR_TEHUTI is not set -+# CONFIG_NET_VENDOR_TI is not set -+# CONFIG_NET_VENDOR_VIA is not set -+# CONFIG_NET_VENDOR_WIZNET is not set -+CONFIG_NET_VENDOR_XILINX=y -+# CONFIG_XILINX_AXI_EMAC is not set -+# CONFIG_XILINX_LL_TEMAC is not set -+# CONFIG_FDDI is not set -+# CONFIG_HIPPI is not set -+CONFIG_PHYLINK=y -+CONFIG_PHYLIB=y -+CONFIG_SWPHY=y -+CONFIG_FIXED_PHY=y -+# CONFIG_SFP is not set -+ -+# -+# MII PHY device drivers -+# -+# CONFIG_AMD_PHY is not set -+# CONFIG_ADIN_PHY is not set -+# CONFIG_AQUANTIA_PHY is not set -+# CONFIG_AX88796B_PHY is not set -+# CONFIG_BROADCOM_PHY is not set -+# CONFIG_BCM54140_PHY is not set -+# CONFIG_BCM7XXX_PHY is not set -+# CONFIG_BCM84881_PHY is not set -+# CONFIG_BCM87XX_PHY is not set -+# CONFIG_CICADA_PHY is not set -+# CONFIG_CORTINA_PHY is not set -+# CONFIG_DAVICOM_PHY is not set -+# CONFIG_ICPLUS_PHY is not set -+# CONFIG_LXT_PHY is not set -+# CONFIG_INTEL_XWAY_PHY is not set -+# CONFIG_LSI_ET1011C_PHY is not set -+# CONFIG_MARVELL_PHY is not set -+# CONFIG_MARVELL_10G_PHY is not set -+# CONFIG_MICREL_PHY is not set -+# CONFIG_MICROCHIP_PHY is not set -+# CONFIG_MICROCHIP_T1_PHY is not set -+# CONFIG_MICROSEMI_PHY is not set -+# CONFIG_NATIONAL_PHY is not set -+# CONFIG_NXP_TJA11XX_PHY is not set -+# CONFIG_AT803X_PHY is not set -+# CONFIG_QSEMI_PHY is not set -+# CONFIG_REALTEK_PHY is not set -+# CONFIG_RENESAS_PHY is not set -+CONFIG_ROCKCHIP_PHY=y -+# CONFIG_SMSC_PHY is not set -+# CONFIG_STE10XP is not set -+# CONFIG_TERANETICS_PHY is not set -+# CONFIG_DP83822_PHY is not set -+# CONFIG_DP83TC811_PHY is not set -+# CONFIG_DP83848_PHY is not set -+# CONFIG_DP83867_PHY is not set -+# CONFIG_DP83869_PHY is not set -+# CONFIG_VITESSE_PHY is not set -+# CONFIG_XILINX_GMII2RGMII is not set -+# CONFIG_MICREL_KS8995MA is not set -+CONFIG_MDIO_DEVICE=y -+CONFIG_MDIO_BUS=y -+CONFIG_OF_MDIO=y -+CONFIG_MDIO_DEVRES=y -+# CONFIG_MDIO_BITBANG is not set -+# CONFIG_MDIO_BCM_UNIMAC is not set -+# CONFIG_MDIO_HISI_FEMAC is not set -+# CONFIG_MDIO_MVUSB is not set -+# CONFIG_MDIO_MSCC_MIIM is not set -+# CONFIG_MDIO_OCTEON is not set -+# CONFIG_MDIO_IPQ4019 is not set -+# CONFIG_MDIO_IPQ8064 is not set -+# CONFIG_MDIO_THUNDER is not set -+ -+# -+# MDIO Multiplexers -+# -+# CONFIG_MDIO_BUS_MUX_GPIO is not set -+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set -+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -+ -+# -+# PCS device drivers -+# -+CONFIG_PCS_XPCS=y -+# end of PCS device drivers -+ -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+CONFIG_USB_NET_DRIVERS=y -+# CONFIG_USB_CATC is not set -+# CONFIG_USB_KAWETH is not set -+# CONFIG_USB_PEGASUS is not set -+CONFIG_USB_RTL8150=y -+CONFIG_USB_RTL8152=y -+# CONFIG_USB_LAN78XX is not set -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=y -+CONFIG_USB_NET_AX88179_178A=y -+CONFIG_USB_NET_CDCETHER=y -+# CONFIG_USB_NET_CDC_EEM is not set -+# CONFIG_USB_NET_CDC_NCM is not set -+# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -+# CONFIG_USB_NET_CDC_MBIM is not set -+# CONFIG_USB_NET_DM9601 is not set -+# CONFIG_USB_NET_SR9700 is not set -+# CONFIG_USB_NET_SR9800 is not set -+# CONFIG_USB_NET_SMSC75XX is not set -+# CONFIG_USB_NET_SMSC95XX is not set -+# CONFIG_USB_NET_GL620A is not set -+CONFIG_USB_NET_NET1080=y -+# CONFIG_USB_NET_PLUSB is not set -+# CONFIG_USB_NET_MCS7830 is not set -+CONFIG_USB_NET_RNDIS_HOST=y -+CONFIG_USB_NET_CDC_SUBSET_ENABLE=y -+CONFIG_USB_NET_CDC_SUBSET=y -+# CONFIG_USB_ALI_M5632 is not set -+# CONFIG_USB_AN2720 is not set -+CONFIG_USB_BELKIN=y -+CONFIG_USB_ARMLINUX=y -+# CONFIG_USB_EPSON2888 is not set -+# CONFIG_USB_KC2190 is not set -+CONFIG_USB_NET_ZAURUS=y -+# CONFIG_USB_NET_CX82310_ETH is not set -+# CONFIG_USB_NET_KALMIA is not set -+# CONFIG_USB_NET_QMI_WWAN is not set -+# CONFIG_USB_HSO is not set -+# CONFIG_USB_NET_INT51X1 is not set -+# CONFIG_USB_IPHETH is not set -+# CONFIG_USB_SIERRA_NET is not set -+# CONFIG_USB_VL600 is not set -+# CONFIG_USB_NET_CH9200 is not set -+# CONFIG_USB_NET_AQC111 is not set -+CONFIG_WLAN=y -+# CONFIG_WIRELESS_WDS is not set -+CONFIG_WLAN_VENDOR_ADMTEK=y -+# CONFIG_ADM8211 is not set -+CONFIG_WLAN_VENDOR_ATH=y -+# CONFIG_ATH_DEBUG is not set -+# CONFIG_ATH5K is not set -+# CONFIG_ATH5K_PCI is not set -+# CONFIG_ATH9K is not set -+# CONFIG_ATH9K_HTC is not set -+# CONFIG_CARL9170 is not set -+# CONFIG_ATH6KL is not set -+# CONFIG_AR5523 is not set -+# CONFIG_WIL6210 is not set -+# CONFIG_ATH10K is not set -+# CONFIG_WCN36XX is not set -+CONFIG_WLAN_VENDOR_ATMEL=y -+# CONFIG_ATMEL is not set -+# CONFIG_AT76C50X_USB is not set -+CONFIG_WLAN_VENDOR_BROADCOM=y -+# CONFIG_B43 is not set -+# CONFIG_B43LEGACY is not set -+# CONFIG_BRCMSMAC is not set -+# CONFIG_BRCMFMAC is not set -+CONFIG_WLAN_VENDOR_CISCO=y -+CONFIG_WLAN_VENDOR_INTEL=y -+# CONFIG_IPW2100 is not set -+# CONFIG_IPW2200 is not set -+# CONFIG_IWL4965 is not set -+# CONFIG_IWL3945 is not set -+# CONFIG_IWLWIFI is not set -+CONFIG_WLAN_VENDOR_INTERSIL=y -+# CONFIG_HOSTAP is not set -+# CONFIG_HERMES is not set -+# CONFIG_P54_COMMON is not set -+# CONFIG_PRISM54 is not set -+CONFIG_WLAN_VENDOR_MARVELL=y -+# CONFIG_LIBERTAS is not set -+# CONFIG_LIBERTAS_THINFIRM is not set -+# CONFIG_MWIFIEX is not set -+# CONFIG_MWL8K is not set -+CONFIG_WLAN_VENDOR_MEDIATEK=y -+# CONFIG_MT7601U is not set -+# CONFIG_MT76x0U is not set -+# CONFIG_MT76x0E is not set -+# CONFIG_MT76x2E is not set -+# CONFIG_MT76x2U is not set -+# CONFIG_MT7603E is not set -+# CONFIG_MT7615E is not set -+# CONFIG_MT7663U is not set -+# CONFIG_MT7663S is not set -+# CONFIG_MT7915E is not set -+CONFIG_WLAN_VENDOR_MICROCHIP=y -+# CONFIG_WILC1000_SDIO is not set -+# CONFIG_WILC1000_SPI is not set -+CONFIG_WLAN_VENDOR_RALINK=y -+# CONFIG_RT2X00 is not set -+CONFIG_WLAN_VENDOR_REALTEK=y -+# CONFIG_RTL8180 is not set -+# CONFIG_RTL8187 is not set -+CONFIG_RTL_CARDS=y -+# CONFIG_RTL8192CE is not set -+# CONFIG_RTL8192SE is not set -+# CONFIG_RTL8192DE is not set -+# CONFIG_RTL8723AE is not set -+# CONFIG_RTL8723BE is not set -+# CONFIG_RTL8188EE is not set -+# CONFIG_RTL8192EE is not set -+# CONFIG_RTL8821AE is not set -+# CONFIG_RTL8192CU is not set -+# CONFIG_RTL8XXXU is not set -+# CONFIG_RTW88 is not set -+CONFIG_WLAN_VENDOR_RSI=y -+# CONFIG_RSI_91X is not set -+CONFIG_WLAN_VENDOR_ST=y -+# CONFIG_CW1200 is not set -+CONFIG_WLAN_VENDOR_TI=y -+# CONFIG_WL1251 is not set -+# CONFIG_WL12XX is not set -+# CONFIG_WL18XX is not set -+# CONFIG_WLCORE is not set -+CONFIG_WLAN_VENDOR_ZYDAS=y -+# CONFIG_USB_ZD1201 is not set -+# CONFIG_ZD1211RW is not set -+CONFIG_WLAN_VENDOR_QUANTENNA=y -+# CONFIG_QTNFMAC_PCIE is not set -+CONFIG_WL_ROCKCHIP=y -+# CONFIG_WIFI_BUILD_MODULE is not set -+CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP=y -+# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set -+CONFIG_BCMDHD=y -+CONFIG_AP6XXX_WIFI6=y -+CONFIG_BCMDHD_FW_PATH="/vendor/etc/firmware/fw_bcmdhd.bin" -+CONFIG_BCMDHD_NVRAM_PATH="/vendor/etc/firmware/nvram.txt" -+# CONFIG_BCMDHD_STATIC_IF is not set -+# CONFIG_MAC80211_HWSIM is not set -+CONFIG_USB_NET_RNDIS_WLAN=y -+# CONFIG_VIRT_WIFI is not set -+ -+# -+# Enable WiMAX (Networking options) to see the WiMAX drivers -+# -+# CONFIG_WAN is not set -+# CONFIG_VMXNET3 is not set -+# CONFIG_NETDEVSIM is not set -+# CONFIG_NET_FAILOVER is not set -+# CONFIG_ISDN is not set -+# CONFIG_NVM is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+CONFIG_INPUT_LEDS=y -+CONFIG_INPUT_FF_MEMLESS=y -+# CONFIG_INPUT_POLLDEV is not set -+# CONFIG_INPUT_SPARSEKMAP is not set -+# CONFIG_INPUT_MATRIXKMAP is not set -+ -+# -+# Userland interfaces -+# -+# CONFIG_INPUT_MOUSEDEV is not set -+# CONFIG_INPUT_JOYDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+CONFIG_KEYBOARD_ADC=y -+# CONFIG_KEYBOARD_ADP5588 is not set -+# CONFIG_KEYBOARD_ADP5589 is not set -+# CONFIG_KEYBOARD_ATKBD is not set -+# CONFIG_KEYBOARD_QT1050 is not set -+# CONFIG_KEYBOARD_QT1070 is not set -+# CONFIG_KEYBOARD_QT2160 is not set -+# CONFIG_KEYBOARD_DLINK_DIR685 is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_GPIO_POLLED=y -+# CONFIG_KEYBOARD_TCA6416 is not set -+# CONFIG_KEYBOARD_TCA8418 is not set -+# CONFIG_KEYBOARD_MATRIX is not set -+# CONFIG_KEYBOARD_LM8323 is not set -+# CONFIG_KEYBOARD_LM8333 is not set -+# CONFIG_KEYBOARD_MAX7359 is not set -+# CONFIG_KEYBOARD_MCS is not set -+# CONFIG_KEYBOARD_MPR121 is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_OPENCORES is not set -+# CONFIG_KEYBOARD_SAMSUNG is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_OMAP4 is not set -+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+# CONFIG_KEYBOARD_CAP11XX is not set -+# CONFIG_KEYBOARD_BCM is not set -+CONFIG_INPUT_MOUSE=y -+# CONFIG_MOUSE_PS2 is not set -+# CONFIG_MOUSE_SERIAL is not set -+# CONFIG_MOUSE_APPLETOUCH is not set -+# CONFIG_MOUSE_BCM5974 is not set -+CONFIG_MOUSE_CYAPA=y -+CONFIG_MOUSE_ELAN_I2C=y -+CONFIG_MOUSE_ELAN_I2C_I2C=y -+# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set -+# CONFIG_MOUSE_VSXXXAA is not set -+# CONFIG_MOUSE_GPIO is not set -+# CONFIG_MOUSE_SYNAPTICS_I2C is not set -+# CONFIG_MOUSE_SYNAPTICS_USB is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_PROPERTIES=y -+# CONFIG_TOUCHSCREEN_ADS7846 is not set -+# CONFIG_TOUCHSCREEN_AD7877 is not set -+# CONFIG_TOUCHSCREEN_AD7879 is not set -+# CONFIG_TOUCHSCREEN_ADC is not set -+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set -+CONFIG_TOUCHSCREEN_ATMEL_MXT=y -+# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set -+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set -+# CONFIG_TOUCHSCREEN_BU21013 is not set -+# CONFIG_TOUCHSCREEN_BU21029 is not set -+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set -+# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set -+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set -+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set -+# CONFIG_TOUCHSCREEN_DYNAPRO is not set -+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set -+# CONFIG_TOUCHSCREEN_EETI is not set -+# CONFIG_TOUCHSCREEN_EGALAX is not set -+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set -+# CONFIG_TOUCHSCREEN_EXC3000 is not set -+# CONFIG_TOUCHSCREEN_FUJITSU is not set -+# CONFIG_TOUCHSCREEN_GOODIX is not set -+# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set -+# CONFIG_TOUCHSCREEN_GT1X is not set -+# CONFIG_TOUCHSCREEN_GT9XX is not set -+# CONFIG_TOUCHSCREEN_HIDEEP is not set -+# CONFIG_TOUCHSCREEN_ILI210X is not set -+# CONFIG_TOUCHSCREEN_S6SY761 is not set -+# CONFIG_TOUCHSCREEN_GUNZE is not set -+# CONFIG_TOUCHSCREEN_EKTF2127 is not set -+CONFIG_TOUCHSCREEN_ELAN=y -+# CONFIG_TOUCHSCREEN_ELO is not set -+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set -+# CONFIG_TOUCHSCREEN_MAX11801 is not set -+# CONFIG_TOUCHSCREEN_MCS5000 is not set -+# CONFIG_TOUCHSCREEN_MMS114 is not set -+# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set -+# CONFIG_TOUCHSCREEN_MTOUCH is not set -+# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set -+# CONFIG_TOUCHSCREEN_INEXIO is not set -+# CONFIG_TOUCHSCREEN_MK712 is not set -+# CONFIG_TOUCHSCREEN_PENMOUNT is not set -+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set -+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -+# CONFIG_TOUCHSCREEN_PIXCIR is not set -+# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set -+CONFIG_TOUCHSCREEN_USB_COMPOSITE=y -+CONFIG_TOUCHSCREEN_USB_EGALAX=y -+CONFIG_TOUCHSCREEN_USB_PANJIT=y -+CONFIG_TOUCHSCREEN_USB_3M=y -+CONFIG_TOUCHSCREEN_USB_ITM=y -+CONFIG_TOUCHSCREEN_USB_ETURBO=y -+CONFIG_TOUCHSCREEN_USB_GUNZE=y -+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y -+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y -+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y -+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y -+CONFIG_TOUCHSCREEN_USB_GOTOP=y -+CONFIG_TOUCHSCREEN_USB_JASTEC=y -+CONFIG_TOUCHSCREEN_USB_ELO=y -+CONFIG_TOUCHSCREEN_USB_E2I=y -+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y -+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y -+CONFIG_TOUCHSCREEN_USB_NEXIO=y -+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y -+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set -+# CONFIG_TOUCHSCREEN_TSC2004 is not set -+# CONFIG_TOUCHSCREEN_TSC2005 is not set -+# CONFIG_TOUCHSCREEN_TSC2007 is not set -+# CONFIG_TOUCHSCREEN_RM_TS is not set -+# CONFIG_TOUCHSCREEN_SILEAD is not set -+# CONFIG_TOUCHSCREEN_SIS_I2C is not set -+# CONFIG_TOUCHSCREEN_ST1232 is not set -+# CONFIG_TOUCHSCREEN_STMFTS is not set -+# CONFIG_TOUCHSCREEN_SUR40 is not set -+# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set -+# CONFIG_TOUCHSCREEN_SX8654 is not set -+# CONFIG_TOUCHSCREEN_TPS6507X is not set -+# CONFIG_TOUCHSCREEN_ZET6223 is not set -+# CONFIG_TOUCHSCREEN_ZFORCE is not set -+# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set -+# CONFIG_TOUCHSCREEN_IQS5XX is not set -+# CONFIG_TOUCHSCREEN_ZINITIX is not set -+CONFIG_ROCKCHIP_REMOTECTL=y -+CONFIG_ROCKCHIP_REMOTECTL_PWM=y -+ -+# -+# handle all sensors -+# -+# CONFIG_SENSOR_DEVICE is not set -+CONFIG_INPUT_MISC=y -+# CONFIG_INPUT_AD714X is not set -+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set -+# CONFIG_INPUT_BMA150 is not set -+# CONFIG_INPUT_E3X0_BUTTON is not set -+# CONFIG_INPUT_MMA8450 is not set -+# CONFIG_INPUT_GPIO_BEEPER is not set -+# CONFIG_INPUT_GPIO_DECODER is not set -+# CONFIG_INPUT_GPIO_VIBRA is not set -+# CONFIG_INPUT_ATI_REMOTE2 is not set -+# CONFIG_INPUT_KEYSPAN_REMOTE is not set -+# CONFIG_INPUT_KXTJ9 is not set -+# CONFIG_INPUT_POWERMATE is not set -+# CONFIG_INPUT_YEALINK is not set -+# CONFIG_INPUT_CM109 is not set -+# CONFIG_INPUT_REGULATOR_HAPTIC is not set -+CONFIG_INPUT_UINPUT=y -+# CONFIG_INPUT_PCF8574 is not set -+# CONFIG_INPUT_PWM_BEEPER is not set -+# CONFIG_INPUT_PWM_VIBRA is not set -+CONFIG_INPUT_RK805_PWRKEY=y -+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -+# CONFIG_INPUT_ADXL34X is not set -+# CONFIG_INPUT_IMS_PCU is not set -+# CONFIG_INPUT_IQS269A is not set -+# CONFIG_INPUT_CMA3000 is not set -+# CONFIG_INPUT_DRV260X_HAPTICS is not set -+# CONFIG_INPUT_DRV2665_HAPTICS is not set -+# CONFIG_INPUT_DRV2667_HAPTICS is not set -+# CONFIG_RMI4_CORE is not set -+ -+# -+# Hardware I/O ports -+# -+# CONFIG_SERIO is not set -+# CONFIG_GAMEPORT is not set -+# end of Hardware I/O ports -+# end of Input device support -+ -+# -+# Character devices -+# -+CONFIG_TTY=y -+CONFIG_VT=y -+CONFIG_CONSOLE_TRANSLATIONS=y -+CONFIG_VT_CONSOLE=y -+CONFIG_VT_CONSOLE_SLEEP=y -+CONFIG_HW_CONSOLE=y -+CONFIG_VT_HW_CONSOLE_BINDING=y -+CONFIG_UNIX98_PTYS=y -+# CONFIG_LEGACY_PTYS is not set -+CONFIG_LDISC_AUTOLOAD=y -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_EARLYCON=y -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -+CONFIG_SERIAL_8250_16550A_VARIANTS=y -+# CONFIG_SERIAL_8250_FINTEK is not set -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_DMA=y -+# CONFIG_SERIAL_8250_PCI is not set -+CONFIG_SERIAL_8250_NR_UARTS=10 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=10 -+# CONFIG_SERIAL_8250_EXTENDED is not set -+# CONFIG_SERIAL_8250_ASPEED_VUART is not set -+CONFIG_SERIAL_8250_DWLIB=y -+CONFIG_SERIAL_8250_FSL=y -+CONFIG_SERIAL_8250_DW=y -+# CONFIG_SERIAL_8250_RT288X is not set -+CONFIG_SERIAL_OF_PLATFORM=y -+ -+# -+# Non-8250 serial port support -+# -+# CONFIG_SERIAL_AMBA_PL010 is not set -+# CONFIG_SERIAL_AMBA_PL011 is not set -+# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set -+# CONFIG_SERIAL_MAX3100 is not set -+# CONFIG_SERIAL_MAX310X is not set -+# CONFIG_SERIAL_UARTLITE is not set -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_JSM is not set -+# CONFIG_SERIAL_SIFIVE is not set -+# CONFIG_SERIAL_SCCNXP is not set -+# CONFIG_SERIAL_SC16IS7XX is not set -+# CONFIG_SERIAL_ALTERA_JTAGUART is not set -+# CONFIG_SERIAL_ALTERA_UART is not set -+# CONFIG_SERIAL_IFX6X60 is not set -+# CONFIG_SERIAL_XILINX_PS_UART is not set -+# CONFIG_SERIAL_ARC is not set -+# CONFIG_SERIAL_RP2 is not set -+# CONFIG_SERIAL_FSL_LPUART is not set -+# CONFIG_SERIAL_FSL_LINFLEXUART is not set -+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set -+# CONFIG_SERIAL_SPRD is not set -+# end of Serial drivers -+ -+CONFIG_SERIAL_MCTRL_GPIO=y -+# CONFIG_SERIAL_NONSTANDARD is not set -+# CONFIG_N_GSM is not set -+# CONFIG_NOZOMI is not set -+# CONFIG_NULL_TTY is not set -+# CONFIG_TRACE_SINK is not set -+# CONFIG_HVC_DCC is not set -+# CONFIG_SERIAL_DEV_BUS is not set -+# CONFIG_TTY_PRINTK is not set -+# CONFIG_VIRTIO_CONSOLE is not set -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_HW_RANDOM=y -+# CONFIG_HW_RANDOM_TIMERIOMEM is not set -+# CONFIG_HW_RANDOM_BA431 is not set -+CONFIG_HW_RANDOM_CAVIUM=y -+CONFIG_HW_RANDOM_OPTEE=y -+# CONFIG_HW_RANDOM_CCTRNG is not set -+# CONFIG_HW_RANDOM_XIPHERA is not set -+# CONFIG_APPLICOM is not set -+CONFIG_DEVMEM=y -+# CONFIG_RAW_DRIVER is not set -+CONFIG_DEVPORT=y -+CONFIG_TCG_TPM=y -+CONFIG_HW_RANDOM_TPM=y -+# CONFIG_TCG_TIS is not set -+# CONFIG_TCG_TIS_SPI is not set -+# CONFIG_TCG_TIS_I2C_ATMEL is not set -+CONFIG_TCG_TIS_I2C_INFINEON=y -+# CONFIG_TCG_TIS_I2C_NUVOTON is not set -+# CONFIG_TCG_ATMEL is not set -+# CONFIG_TCG_VTPM_PROXY is not set -+# CONFIG_TCG_FTPM_TEE is not set -+# CONFIG_TCG_TIS_ST33ZP24_I2C is not set -+# CONFIG_TCG_TIS_ST33ZP24_SPI is not set -+# CONFIG_XILLYBUS is not set -+# end of Character devices -+ -+# CONFIG_RANDOM_TRUST_CPU is not set -+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set -+ -+# -+# I2C support -+# -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_COMPAT=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+ -+# -+# Multiplexer I2C Chip support -+# -+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set -+# CONFIG_I2C_MUX_GPIO is not set -+# CONFIG_I2C_MUX_GPMUX is not set -+# CONFIG_I2C_MUX_LTC4306 is not set -+# CONFIG_I2C_MUX_PCA9541 is not set -+# CONFIG_I2C_MUX_PCA954x is not set -+# CONFIG_I2C_MUX_PINCTRL is not set -+# CONFIG_I2C_MUX_REG is not set -+# CONFIG_I2C_DEMUX_PINCTRL is not set -+# CONFIG_I2C_MUX_MLXCPLD is not set -+# end of Multiplexer I2C Chip support -+ -+CONFIG_I2C_HELPER_AUTO=y -+CONFIG_I2C_ALGOBIT=y -+ -+# -+# I2C Hardware Bus support -+# -+ -+# -+# PC SMBus host controller drivers -+# -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_ISCH is not set -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_I2C_NFORCE2 is not set -+# CONFIG_I2C_NVIDIA_GPU is not set -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+ -+# -+# I2C system bus drivers (mostly embedded / system-on-chip) -+# -+# CONFIG_I2C_CADENCE is not set -+# CONFIG_I2C_CBUS_GPIO is not set -+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -+# CONFIG_I2C_DESIGNWARE_PCI is not set -+# CONFIG_I2C_EMEV2 is not set -+# CONFIG_I2C_GPIO is not set -+# CONFIG_I2C_NOMADIK is not set -+# CONFIG_I2C_OCORES is not set -+# CONFIG_I2C_PCA_PLATFORM is not set -+CONFIG_I2C_RK3X=y -+# CONFIG_I2C_SIMTEC is not set -+# CONFIG_I2C_THUNDERX is not set -+# CONFIG_I2C_XILINX is not set -+ -+# -+# External I2C/SMBus adapter drivers -+# -+# CONFIG_I2C_DIOLAN_U2C is not set -+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_TINY_USB is not set -+ -+# -+# Other I2C/SMBus bus drivers -+# -+# end of I2C Hardware Bus support -+ -+# CONFIG_I2C_STUB is not set -+# CONFIG_I2C_SLAVE is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# end of I2C support -+ -+# CONFIG_I3C is not set -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+# CONFIG_SPI_MEM is not set -+ -+# -+# SPI Master Controller Drivers -+# -+# CONFIG_SPI_ALTERA is not set -+# CONFIG_SPI_AXI_SPI_ENGINE is not set -+CONFIG_SPI_BITBANG=y -+# CONFIG_SPI_CADENCE is not set -+# CONFIG_SPI_CADENCE_QUADSPI is not set -+# CONFIG_SPI_DESIGNWARE is not set -+# CONFIG_SPI_NXP_FLEXSPI is not set -+# CONFIG_SPI_GPIO is not set -+# CONFIG_SPI_FSL_SPI is not set -+# CONFIG_SPI_OC_TINY is not set -+# CONFIG_SPI_PL022 is not set -+# CONFIG_SPI_PXA2XX is not set -+CONFIG_SPI_ROCKCHIP=y -+# CONFIG_SPI_SC18IS602 is not set -+# CONFIG_SPI_SIFIVE is not set -+# CONFIG_SPI_MXIC is not set -+# CONFIG_SPI_THUNDERX is not set -+# CONFIG_SPI_XCOMM is not set -+# CONFIG_SPI_XILINX is not set -+# CONFIG_SPI_ZYNQMP_GQSPI is not set -+# CONFIG_SPI_AMD is not set -+ -+# -+# SPI Multiplexer support -+# -+# CONFIG_SPI_MUX is not set -+ -+# -+# SPI Protocol Masters -+# -+CONFIG_SPI_SPIDEV=y -+# CONFIG_SPI_LOOPBACK_TEST is not set -+# CONFIG_SPI_TLE62X0 is not set -+# CONFIG_SPI_SLAVE is not set -+# CONFIG_SPMI is not set -+# CONFIG_HSI is not set -+CONFIG_PPS=y -+# CONFIG_PPS_DEBUG is not set -+ -+# -+# PPS clients support -+# -+# CONFIG_PPS_CLIENT_KTIMER is not set -+# CONFIG_PPS_CLIENT_LDISC is not set -+# CONFIG_PPS_CLIENT_GPIO is not set -+ -+# -+# PPS generators support -+# -+ -+# -+# PTP clock support -+# -+CONFIG_PTP_1588_CLOCK=y -+ -+# -+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -+# -+# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set -+# CONFIG_PTP_1588_CLOCK_IDTCM is not set -+# end of PTP clock support -+ -+CONFIG_PINCTRL=y -+CONFIG_PINMUX=y -+CONFIG_PINCONF=y -+CONFIG_GENERIC_PINCONF=y -+# CONFIG_DEBUG_PINCTRL is not set -+# CONFIG_PINCTRL_MCP23S08 is not set -+CONFIG_PINCTRL_ROCKCHIP=y -+# CONFIG_PINCTRL_SINGLE is not set -+# CONFIG_PINCTRL_SX150X is not set -+# CONFIG_PINCTRL_STMFX is not set -+CONFIG_PINCTRL_RK805=y -+# CONFIG_PINCTRL_OCELOT is not set -+ -+# -+# Renesas pinctrl drivers -+# -+# end of Renesas pinctrl drivers -+ -+CONFIG_GPIOLIB=y -+CONFIG_GPIOLIB_FASTPATH_LIMIT=512 -+CONFIG_OF_GPIO=y -+CONFIG_GPIOLIB_IRQCHIP=y -+# CONFIG_DEBUG_GPIO is not set -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_CDEV=y -+CONFIG_GPIO_CDEV_V1=y -+CONFIG_GPIO_GENERIC=y -+ -+# -+# Memory mapped GPIO drivers -+# -+# CONFIG_GPIO_74XX_MMIO is not set -+# CONFIG_GPIO_ALTERA is not set -+# CONFIG_GPIO_CADENCE is not set -+# CONFIG_GPIO_DWAPB is not set -+# CONFIG_GPIO_FTGPIO010 is not set -+CONFIG_GPIO_GENERIC_PLATFORM=y -+# CONFIG_GPIO_GRGPIO is not set -+# CONFIG_GPIO_HLWD is not set -+# CONFIG_GPIO_LOGICVC is not set -+# CONFIG_GPIO_MB86S7X is not set -+# CONFIG_GPIO_PL061 is not set -+CONFIG_GPIO_ROCKCHIP=y -+# CONFIG_GPIO_SAMA5D2_PIOBU is not set -+# CONFIG_GPIO_SIFIVE is not set -+# CONFIG_GPIO_SYSCON is not set -+# CONFIG_GPIO_XGENE is not set -+# CONFIG_GPIO_XILINX is not set -+# CONFIG_GPIO_AMD_FCH is not set -+# end of Memory mapped GPIO drivers -+ -+# -+# I2C GPIO expanders -+# -+# CONFIG_GPIO_ADP5588 is not set -+# CONFIG_GPIO_ADNP is not set -+# CONFIG_GPIO_GW_PLD is not set -+# CONFIG_GPIO_MAX7300 is not set -+# CONFIG_GPIO_MAX732X is not set -+# CONFIG_GPIO_PCA953X is not set -+# CONFIG_GPIO_PCA9570 is not set -+# CONFIG_GPIO_PCF857X is not set -+# CONFIG_GPIO_TPIC2810 is not set -+# end of I2C GPIO expanders -+ -+# -+# MFD GPIO expanders -+# -+# CONFIG_GPIO_TPS6586X is not set -+# end of MFD GPIO expanders -+ -+# -+# PCI GPIO expanders -+# -+# CONFIG_GPIO_BT8XX is not set -+# CONFIG_GPIO_PCI_IDIO_16 is not set -+# CONFIG_GPIO_PCIE_IDIO_24 is not set -+# CONFIG_GPIO_RDC321X is not set -+# end of PCI GPIO expanders -+ -+# -+# SPI GPIO expanders -+# -+# CONFIG_GPIO_74X164 is not set -+# CONFIG_GPIO_MAX3191X is not set -+# CONFIG_GPIO_MAX7301 is not set -+# CONFIG_GPIO_MC33880 is not set -+# CONFIG_GPIO_PISOSR is not set -+# CONFIG_GPIO_XRA1403 is not set -+# end of SPI GPIO expanders -+ -+# -+# USB GPIO expanders -+# -+# end of USB GPIO expanders -+ -+# CONFIG_GPIO_AGGREGATOR is not set -+# CONFIG_GPIO_MOCKUP is not set -+# CONFIG_W1 is not set -+CONFIG_POWER_RESET=y -+# CONFIG_POWER_RESET_BRCMSTB is not set -+CONFIG_POWER_RESET_GPIO=y -+CONFIG_POWER_RESET_GPIO_RESTART=y -+# CONFIG_POWER_RESET_LTC2952 is not set -+# CONFIG_POWER_RESET_RESTART is not set -+# CONFIG_POWER_RESET_XGENE is not set -+# CONFIG_POWER_RESET_SYSCON is not set -+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set -+CONFIG_REBOOT_MODE=y -+CONFIG_SYSCON_REBOOT_MODE=y -+# CONFIG_NVMEM_REBOOT_MODE is not set -+CONFIG_POWER_SUPPLY=y -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+CONFIG_POWER_SUPPLY_HWMON=y -+# CONFIG_PDA_POWER is not set -+# CONFIG_GENERIC_ADC_BATTERY is not set -+# CONFIG_TEST_POWER is not set -+# CONFIG_CHARGER_ADP5061 is not set -+# CONFIG_BATTERY_CW2015 is not set -+# CONFIG_BATTERY_DS2780 is not set -+# CONFIG_BATTERY_DS2781 is not set -+# CONFIG_BATTERY_DS2782 is not set -+CONFIG_BATTERY_SBS=y -+# CONFIG_CHARGER_SBS is not set -+# CONFIG_MANAGER_SBS is not set -+# CONFIG_BATTERY_BQ27XXX is not set -+# CONFIG_BATTERY_MAX17040 is not set -+# CONFIG_BATTERY_MAX17042 is not set -+# CONFIG_CHARGER_ISP1704 is not set -+# CONFIG_CHARGER_MAX8903 is not set -+# CONFIG_CHARGER_LP8727 is not set -+CONFIG_CHARGER_GPIO=y -+# CONFIG_CHARGER_MANAGER is not set -+# CONFIG_CHARGER_LT3651 is not set -+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set -+# CONFIG_CHARGER_BQ2415X is not set -+# CONFIG_CHARGER_BQ24190 is not set -+# CONFIG_CHARGER_BQ24257 is not set -+CONFIG_CHARGER_BQ24735=y -+# CONFIG_CHARGER_BQ2515X is not set -+# CONFIG_CHARGER_BQ25700 is not set -+# CONFIG_CHARGER_BQ25890 is not set -+# CONFIG_CHARGER_BQ25980 is not set -+# CONFIG_CHARGER_SMB347 is not set -+# CONFIG_BATTERY_GAUGE_LTC2941 is not set -+# CONFIG_CHARGER_RT9455 is not set -+# CONFIG_CHARGER_UCS1002 is not set -+# CONFIG_CHARGER_BD99954 is not set -+# CONFIG_BATTERY_RK816 is not set -+CONFIG_BATTERY_RK817=y -+CONFIG_CHARGER_RK817=y -+# CONFIG_BATTERY_RK818 is not set -+# CONFIG_CHARGER_RK818 is not set -+CONFIG_HWMON=y -+# CONFIG_HWMON_DEBUG_CHIP is not set -+ -+# -+# Native drivers -+# -+# CONFIG_SENSORS_AD7314 is not set -+# CONFIG_SENSORS_AD7414 is not set -+# CONFIG_SENSORS_AD7418 is not set -+# CONFIG_SENSORS_ADM1021 is not set -+# CONFIG_SENSORS_ADM1025 is not set -+# CONFIG_SENSORS_ADM1026 is not set -+# CONFIG_SENSORS_ADM1029 is not set -+# CONFIG_SENSORS_ADM1031 is not set -+# CONFIG_SENSORS_ADM1177 is not set -+# CONFIG_SENSORS_ADM9240 is not set -+# CONFIG_SENSORS_ADT7310 is not set -+# CONFIG_SENSORS_ADT7410 is not set -+# CONFIG_SENSORS_ADT7411 is not set -+# CONFIG_SENSORS_ADT7462 is not set -+# CONFIG_SENSORS_ADT7470 is not set -+# CONFIG_SENSORS_ADT7475 is not set -+# CONFIG_SENSORS_AS370 is not set -+# CONFIG_SENSORS_ASC7621 is not set -+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -+# CONFIG_SENSORS_ARM_SCMI is not set -+# CONFIG_SENSORS_ASPEED is not set -+# CONFIG_SENSORS_ATXP1 is not set -+# CONFIG_SENSORS_CORSAIR_CPRO is not set -+# CONFIG_SENSORS_DRIVETEMP is not set -+# CONFIG_SENSORS_DS620 is not set -+# CONFIG_SENSORS_DS1621 is not set -+# CONFIG_SENSORS_I5K_AMB is not set -+# CONFIG_SENSORS_F71805F is not set -+# CONFIG_SENSORS_F71882FG is not set -+# CONFIG_SENSORS_F75375S is not set -+# CONFIG_SENSORS_FTSTEUTATES is not set -+# CONFIG_SENSORS_GL518SM is not set -+# CONFIG_SENSORS_GL520SM is not set -+# CONFIG_SENSORS_G760A is not set -+# CONFIG_SENSORS_G762 is not set -+# CONFIG_SENSORS_GPIO_FAN is not set -+# CONFIG_SENSORS_HIH6130 is not set -+# CONFIG_SENSORS_IIO_HWMON is not set -+# CONFIG_SENSORS_IT87 is not set -+# CONFIG_SENSORS_JC42 is not set -+# CONFIG_SENSORS_POWR1220 is not set -+# CONFIG_SENSORS_LINEAGE is not set -+# CONFIG_SENSORS_LTC2945 is not set -+# CONFIG_SENSORS_LTC2947_I2C is not set -+# CONFIG_SENSORS_LTC2947_SPI is not set -+# CONFIG_SENSORS_LTC2990 is not set -+# CONFIG_SENSORS_LTC4151 is not set -+# CONFIG_SENSORS_LTC4215 is not set -+# CONFIG_SENSORS_LTC4222 is not set -+# CONFIG_SENSORS_LTC4245 is not set -+# CONFIG_SENSORS_LTC4260 is not set -+# CONFIG_SENSORS_LTC4261 is not set -+# CONFIG_SENSORS_MAX1111 is not set -+# CONFIG_SENSORS_MAX16065 is not set -+# CONFIG_SENSORS_MAX1619 is not set -+# CONFIG_SENSORS_MAX1668 is not set -+# CONFIG_SENSORS_MAX197 is not set -+# CONFIG_SENSORS_MAX31722 is not set -+# CONFIG_SENSORS_MAX31730 is not set -+# CONFIG_SENSORS_MAX6621 is not set -+# CONFIG_SENSORS_MAX6639 is not set -+# CONFIG_SENSORS_MAX6642 is not set -+# CONFIG_SENSORS_MAX6650 is not set -+# CONFIG_SENSORS_MAX6697 is not set -+# CONFIG_SENSORS_MAX31790 is not set -+# CONFIG_SENSORS_MCP3021 is not set -+# CONFIG_SENSORS_TC654 is not set -+# CONFIG_SENSORS_MR75203 is not set -+# CONFIG_SENSORS_ADCXX is not set -+# CONFIG_SENSORS_LM63 is not set -+# CONFIG_SENSORS_LM70 is not set -+# CONFIG_SENSORS_LM73 is not set -+# CONFIG_SENSORS_LM75 is not set -+# CONFIG_SENSORS_LM77 is not set -+# CONFIG_SENSORS_LM78 is not set -+# CONFIG_SENSORS_LM80 is not set -+# CONFIG_SENSORS_LM83 is not set -+# CONFIG_SENSORS_LM85 is not set -+# CONFIG_SENSORS_LM87 is not set -+# CONFIG_SENSORS_LM90 is not set -+# CONFIG_SENSORS_LM92 is not set -+# CONFIG_SENSORS_LM93 is not set -+# CONFIG_SENSORS_LM95234 is not set -+# CONFIG_SENSORS_LM95241 is not set -+# CONFIG_SENSORS_LM95245 is not set -+# CONFIG_SENSORS_PC87360 is not set -+# CONFIG_SENSORS_PC87427 is not set -+# CONFIG_SENSORS_NTC_THERMISTOR is not set -+# CONFIG_SENSORS_NCT6683 is not set -+# CONFIG_SENSORS_NCT6775 is not set -+# CONFIG_SENSORS_NCT7802 is not set -+# CONFIG_SENSORS_NCT7904 is not set -+# CONFIG_SENSORS_NPCM7XX is not set -+# CONFIG_SENSORS_OCC_P8_I2C is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_PMBUS is not set -+# CONFIG_SENSORS_PWM_FAN is not set -+# CONFIG_SENSORS_SHT15 is not set -+# CONFIG_SENSORS_SHT21 is not set -+# CONFIG_SENSORS_SHT3x is not set -+# CONFIG_SENSORS_SHTC1 is not set -+# CONFIG_SENSORS_SIS5595 is not set -+# CONFIG_SENSORS_DME1737 is not set -+# CONFIG_SENSORS_EMC1403 is not set -+# CONFIG_SENSORS_EMC2103 is not set -+# CONFIG_SENSORS_EMC6W201 is not set -+# CONFIG_SENSORS_SMSC47M1 is not set -+# CONFIG_SENSORS_SMSC47M192 is not set -+# CONFIG_SENSORS_SMSC47B397 is not set -+# CONFIG_SENSORS_SCH5627 is not set -+# CONFIG_SENSORS_SCH5636 is not set -+# CONFIG_SENSORS_STTS751 is not set -+# CONFIG_SENSORS_SMM665 is not set -+# CONFIG_SENSORS_ADC128D818 is not set -+# CONFIG_SENSORS_ADS7828 is not set -+# CONFIG_SENSORS_ADS7871 is not set -+# CONFIG_SENSORS_AMC6821 is not set -+# CONFIG_SENSORS_INA209 is not set -+# CONFIG_SENSORS_INA2XX is not set -+# CONFIG_SENSORS_INA3221 is not set -+# CONFIG_SENSORS_TC74 is not set -+# CONFIG_SENSORS_THMC50 is not set -+# CONFIG_SENSORS_TMP102 is not set -+# CONFIG_SENSORS_TMP103 is not set -+# CONFIG_SENSORS_TMP108 is not set -+# CONFIG_SENSORS_TMP401 is not set -+# CONFIG_SENSORS_TMP421 is not set -+# CONFIG_SENSORS_TMP513 is not set -+# CONFIG_SENSORS_VIA686A is not set -+# CONFIG_SENSORS_VT1211 is not set -+# CONFIG_SENSORS_VT8231 is not set -+# CONFIG_SENSORS_W83773G is not set -+# CONFIG_SENSORS_W83781D is not set -+# CONFIG_SENSORS_W83791D is not set -+# CONFIG_SENSORS_W83792D is not set -+# CONFIG_SENSORS_W83793 is not set -+# CONFIG_SENSORS_W83795 is not set -+# CONFIG_SENSORS_W83L785TS is not set -+# CONFIG_SENSORS_W83L786NG is not set -+# CONFIG_SENSORS_W83627HF is not set -+# CONFIG_SENSORS_W83627EHF is not set -+CONFIG_THERMAL=y -+# CONFIG_THERMAL_NETLINK is not set -+# CONFIG_THERMAL_STATISTICS is not set -+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -+CONFIG_THERMAL_HWMON=y -+CONFIG_THERMAL_OF=y -+CONFIG_THERMAL_WRITABLE_TRIPS=y -+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -+CONFIG_THERMAL_GOV_FAIR_SHARE=y -+CONFIG_THERMAL_GOV_STEP_WISE=y -+# CONFIG_THERMAL_GOV_BANG_BANG is not set -+# CONFIG_THERMAL_GOV_USER_SPACE is not set -+# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set -+CONFIG_CPU_THERMAL=y -+CONFIG_CPU_FREQ_THERMAL=y -+CONFIG_DEVFREQ_THERMAL=y -+# CONFIG_THERMAL_EMULATION is not set -+# CONFIG_THERMAL_MMIO is not set -+CONFIG_ROCKCHIP_THERMAL=y -+# CONFIG_GENERIC_ADC_THERMAL is not set -+CONFIG_WATCHDOG=y -+CONFIG_WATCHDOG_CORE=y -+# CONFIG_WATCHDOG_NOWAYOUT is not set -+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -+CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -+# CONFIG_WATCHDOG_SYSFS is not set -+ -+# -+# Watchdog Pretimeout Governors -+# -+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set -+ -+# -+# Watchdog Device Drivers -+# -+# CONFIG_SOFT_WATCHDOG is not set -+# CONFIG_GPIO_WATCHDOG is not set -+# CONFIG_XILINX_WATCHDOG is not set -+# CONFIG_ZIIRAVE_WATCHDOG is not set -+# CONFIG_ARM_SP805_WATCHDOG is not set -+# CONFIG_ARM_SBSA_WATCHDOG is not set -+# CONFIG_CADENCE_WATCHDOG is not set -+CONFIG_DW_WATCHDOG=y -+# CONFIG_MAX63XX_WATCHDOG is not set -+# CONFIG_ARM_SMC_WATCHDOG is not set -+# CONFIG_ALIM7101_WDT is not set -+# CONFIG_I6300ESB_WDT is not set -+# CONFIG_MEN_A21_WDT is not set -+ -+# -+# PCI-based Watchdog Cards -+# -+# CONFIG_PCIPCWATCHDOG is not set -+# CONFIG_WDTPCI is not set -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_SSB_POSSIBLE=y -+# CONFIG_SSB is not set -+CONFIG_BCMA_POSSIBLE=y -+# CONFIG_BCMA is not set -+ -+# -+# Multifunction device drivers -+# -+CONFIG_MFD_CORE=y -+# CONFIG_MFD_ACT8945A is not set -+# CONFIG_MFD_AS3711 is not set -+# CONFIG_MFD_AS3722 is not set -+# CONFIG_PMIC_ADP5520 is not set -+# CONFIG_MFD_AAT2870_CORE is not set -+# CONFIG_MFD_ATMEL_FLEXCOM is not set -+# CONFIG_MFD_ATMEL_HLCDC is not set -+# CONFIG_MFD_BCM590XX is not set -+# CONFIG_MFD_BD9571MWV is not set -+# CONFIG_MFD_AXP20X_I2C is not set -+# CONFIG_MFD_MADERA is not set -+# CONFIG_PMIC_DA903X is not set -+# CONFIG_MFD_DA9052_SPI is not set -+# CONFIG_MFD_DA9052_I2C is not set -+# CONFIG_MFD_DA9055 is not set -+# CONFIG_MFD_DA9062 is not set -+# CONFIG_MFD_DA9063 is not set -+# CONFIG_MFD_DA9150 is not set -+# CONFIG_MFD_DLN2 is not set -+# CONFIG_MFD_GATEWORKS_GSC is not set -+# CONFIG_MFD_MC13XXX_SPI is not set -+# CONFIG_MFD_MC13XXX_I2C is not set -+# CONFIG_MFD_MP2629 is not set -+# CONFIG_MFD_HI6421_PMIC is not set -+# CONFIG_HTC_PASIC3 is not set -+# CONFIG_HTC_I2CPLD is not set -+# CONFIG_LPC_ICH is not set -+# CONFIG_LPC_SCH is not set -+# CONFIG_MFD_IQS62X is not set -+# CONFIG_MFD_JANZ_CMODIO is not set -+# CONFIG_MFD_KEMPLD is not set -+# CONFIG_MFD_88PM800 is not set -+# CONFIG_MFD_88PM805 is not set -+# CONFIG_MFD_88PM860X is not set -+# CONFIG_MFD_MAX14577 is not set -+# CONFIG_MFD_MAX77620 is not set -+# CONFIG_MFD_MAX77650 is not set -+# CONFIG_MFD_MAX77686 is not set -+# CONFIG_MFD_MAX77693 is not set -+# CONFIG_MFD_MAX77843 is not set -+# CONFIG_MFD_MAX8907 is not set -+# CONFIG_MFD_MAX8925 is not set -+# CONFIG_MFD_MAX8997 is not set -+# CONFIG_MFD_MAX8998 is not set -+# CONFIG_MFD_MT6360 is not set -+# CONFIG_MFD_MT6397 is not set -+# CONFIG_MFD_MENF21BMC is not set -+# CONFIG_EZX_PCAP is not set -+# CONFIG_MFD_CPCAP is not set -+# CONFIG_MFD_VIPERBOARD is not set -+# CONFIG_MFD_RETU is not set -+# CONFIG_MFD_PCF50633 is not set -+# CONFIG_MFD_RDC321X is not set -+# CONFIG_MFD_RT5033 is not set -+# CONFIG_MFD_RC5T583 is not set -+CONFIG_MFD_RK808=y -+# CONFIG_MFD_RN5T618 is not set -+# CONFIG_MFD_SEC_CORE is not set -+# CONFIG_MFD_SI476X_CORE is not set -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_SKY81452 is not set -+# CONFIG_ABX500_CORE is not set -+# CONFIG_MFD_STMPE is not set -+CONFIG_MFD_SYSCON=y -+# CONFIG_MFD_TI_AM335X_TSCADC is not set -+# CONFIG_MFD_LP3943 is not set -+# CONFIG_MFD_LP8788 is not set -+# CONFIG_MFD_TI_LMU is not set -+# CONFIG_MFD_PALMAS is not set -+# CONFIG_TPS6105X is not set -+# CONFIG_TPS65010 is not set -+# CONFIG_TPS6507X is not set -+# CONFIG_MFD_TPS65086 is not set -+# CONFIG_MFD_TPS65090 is not set -+# CONFIG_MFD_TPS65217 is not set -+# CONFIG_MFD_TI_LP873X is not set -+# CONFIG_MFD_TI_LP87565 is not set -+# CONFIG_MFD_TPS65218 is not set -+CONFIG_MFD_TPS6586X=y -+# CONFIG_MFD_TPS65910 is not set -+# CONFIG_MFD_TPS65912_I2C is not set -+# CONFIG_MFD_TPS65912_SPI is not set -+# CONFIG_MFD_TPS80031 is not set -+# CONFIG_TWL4030_CORE is not set -+# CONFIG_TWL6040_CORE is not set -+# CONFIG_MFD_WL1273_CORE is not set -+# CONFIG_MFD_LM3533 is not set -+# CONFIG_MFD_TC3589X is not set -+# CONFIG_MFD_TQMX86 is not set -+# CONFIG_MFD_VX855 is not set -+# CONFIG_MFD_LOCHNAGAR is not set -+# CONFIG_MFD_ARIZONA_I2C is not set -+# CONFIG_MFD_ARIZONA_SPI is not set -+# CONFIG_MFD_WM8400 is not set -+# CONFIG_MFD_WM831X_I2C is not set -+# CONFIG_MFD_WM831X_SPI is not set -+# CONFIG_MFD_WM8350_I2C is not set -+# CONFIG_MFD_WM8994 is not set -+# CONFIG_MFD_ROHM_BD718XX is not set -+# CONFIG_MFD_ROHM_BD70528 is not set -+# CONFIG_MFD_ROHM_BD71828 is not set -+# CONFIG_MFD_STPMIC1 is not set -+# CONFIG_MFD_STMFX is not set -+# CONFIG_MFD_KHADAS_MCU is not set -+# CONFIG_MFD_INTEL_M10_BMC is not set -+# end of Multifunction device drivers -+ -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_DEBUG=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -+# CONFIG_REGULATOR_88PG86X is not set -+CONFIG_REGULATOR_ACT8865=y -+# CONFIG_REGULATOR_AD5398 is not set -+# CONFIG_REGULATOR_DA9210 is not set -+# CONFIG_REGULATOR_DA9211 is not set -+CONFIG_REGULATOR_FAN53555=y -+# CONFIG_REGULATOR_FAN53880 is not set -+CONFIG_REGULATOR_GPIO=y -+# CONFIG_REGULATOR_ISL9305 is not set -+# CONFIG_REGULATOR_ISL6271A is not set -+# CONFIG_REGULATOR_LP3971 is not set -+# CONFIG_REGULATOR_LP3972 is not set -+# CONFIG_REGULATOR_LP872X is not set -+# CONFIG_REGULATOR_LP8755 is not set -+# CONFIG_REGULATOR_LTC3589 is not set -+# CONFIG_REGULATOR_LTC3676 is not set -+# CONFIG_REGULATOR_MAX1586 is not set -+# CONFIG_REGULATOR_MAX8649 is not set -+# CONFIG_REGULATOR_MAX8660 is not set -+# CONFIG_REGULATOR_MAX8952 is not set -+# CONFIG_REGULATOR_MAX8973 is not set -+# CONFIG_REGULATOR_MAX77826 is not set -+# CONFIG_REGULATOR_MCP16502 is not set -+# CONFIG_REGULATOR_MP5416 is not set -+# CONFIG_REGULATOR_MP8859 is not set -+# CONFIG_REGULATOR_MP886X is not set -+# CONFIG_REGULATOR_MPQ7920 is not set -+# CONFIG_REGULATOR_MT6311 is not set -+# CONFIG_REGULATOR_PCA9450 is not set -+# CONFIG_REGULATOR_PFUZE100 is not set -+# CONFIG_REGULATOR_PV88060 is not set -+# CONFIG_REGULATOR_PV88080 is not set -+# CONFIG_REGULATOR_PV88090 is not set -+CONFIG_REGULATOR_PWM=y -+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set -+CONFIG_REGULATOR_RK808=y -+# CONFIG_REGULATOR_RT4801 is not set -+# CONFIG_REGULATOR_RTMV20 is not set -+# CONFIG_REGULATOR_SLG51000 is not set -+# CONFIG_REGULATOR_SY8106A is not set -+# CONFIG_REGULATOR_SY8824X is not set -+# CONFIG_REGULATOR_SY8827N is not set -+# CONFIG_REGULATOR_TPS51632 is not set -+# CONFIG_REGULATOR_TPS62360 is not set -+# CONFIG_REGULATOR_TPS65023 is not set -+# CONFIG_REGULATOR_TPS6507X is not set -+CONFIG_REGULATOR_TPS65132=y -+# CONFIG_REGULATOR_TPS6524X is not set -+CONFIG_REGULATOR_TPS6586X=y -+# CONFIG_REGULATOR_VCTRL is not set -+CONFIG_REGULATOR_XZ3216=y -+# CONFIG_RC_CORE is not set -+CONFIG_CEC_CORE=y -+CONFIG_CEC_NOTIFIER=y -+CONFIG_MEDIA_CEC_SUPPORT=y -+# CONFIG_CEC_CH7322 is not set -+# CONFIG_USB_PULSE8_CEC is not set -+# CONFIG_USB_RAINSHADOW_CEC is not set -+CONFIG_MEDIA_SUPPORT=y -+# CONFIG_MEDIA_SUPPORT_FILTER is not set -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+ -+# -+# Media device types -+# -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_SDR_SUPPORT=y -+CONFIG_MEDIA_PLATFORM_SUPPORT=y -+CONFIG_MEDIA_TEST_SUPPORT=y -+# end of Media device types -+ -+# -+# Media core support -+# -+CONFIG_VIDEO_DEV=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_DVB_CORE=y -+# end of Media core support -+ -+# -+# Video4Linux options -+# -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_V4L2_I2C=y -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+# CONFIG_VIDEO_ADV_DEBUG is not set -+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -+CONFIG_V4L2_MEM2MEM_DEV=y -+CONFIG_V4L2_FWNODE=y -+# end of Video4Linux options -+ -+# -+# Media controller options -+# -+# CONFIG_MEDIA_CONTROLLER_DVB is not set -+# end of Media controller options -+ -+# -+# Digital TV options -+# -+# CONFIG_DVB_MMAP is not set -+CONFIG_DVB_NET=y -+CONFIG_DVB_MAX_ADAPTERS=16 -+CONFIG_DVB_DYNAMIC_MINORS=y -+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set -+# CONFIG_DVB_ULE_DEBUG is not set -+# end of Digital TV options -+ -+# -+# Media drivers -+# -+CONFIG_MEDIA_USB_SUPPORT=y -+ -+# -+# Webcam devices -+# -+CONFIG_USB_VIDEO_CLASS=y -+# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set -+# CONFIG_USB_GSPCA is not set -+# CONFIG_USB_PWC is not set -+# CONFIG_VIDEO_CPIA2 is not set -+# CONFIG_USB_ZR364XX is not set -+# CONFIG_USB_STKWEBCAM is not set -+# CONFIG_USB_S2255 is not set -+# CONFIG_VIDEO_USBTV is not set -+ -+# -+# Analog TV USB devices -+# -+# CONFIG_VIDEO_PVRUSB2 is not set -+# CONFIG_VIDEO_HDPVR is not set -+# CONFIG_VIDEO_STK1160_COMMON is not set -+# CONFIG_VIDEO_GO7007 is not set -+ -+# -+# Analog/digital TV USB devices -+# -+# CONFIG_VIDEO_AU0828 is not set -+# CONFIG_VIDEO_CX231XX is not set -+ -+# -+# Digital TV USB devices -+# -+# CONFIG_DVB_USB_V2 is not set -+# CONFIG_DVB_TTUSB_BUDGET is not set -+# CONFIG_DVB_TTUSB_DEC is not set -+# CONFIG_SMS_USB_DRV is not set -+# CONFIG_DVB_B2C2_FLEXCOP_USB is not set -+# CONFIG_DVB_AS102 is not set -+ -+# -+# Webcam, TV (analog/digital) USB devices -+# -+# CONFIG_VIDEO_EM28XX is not set -+ -+# -+# Software defined radio USB devices -+# -+# CONFIG_USB_AIRSPY is not set -+# CONFIG_USB_HACKRF is not set -+# CONFIG_USB_MSI2500 is not set -+# CONFIG_MEDIA_PCI_SUPPORT is not set -+CONFIG_RADIO_ADAPTERS=y -+# CONFIG_RADIO_SI470X is not set -+# CONFIG_RADIO_SI4713 is not set -+# CONFIG_USB_MR800 is not set -+# CONFIG_USB_DSBR is not set -+# CONFIG_RADIO_MAXIRADIO is not set -+# CONFIG_RADIO_SHARK is not set -+# CONFIG_RADIO_SHARK2 is not set -+# CONFIG_USB_KEENE is not set -+# CONFIG_USB_RAREMONO is not set -+# CONFIG_USB_MA901 is not set -+# CONFIG_RADIO_TEA5764 is not set -+# CONFIG_RADIO_SAA7706H is not set -+# CONFIG_RADIO_TEF6862 is not set -+# CONFIG_RADIO_WL1273 is not set -+CONFIG_VIDEOBUF2_CORE=y -+CONFIG_VIDEOBUF2_V4L2=y -+CONFIG_VIDEOBUF2_MEMOPS=y -+CONFIG_VIDEOBUF2_DMA_CONTIG=y -+CONFIG_VIDEOBUF2_VMALLOC=y -+CONFIG_VIDEOBUF2_DMA_SG=y -+CONFIG_V4L_PLATFORM_DRIVERS=y -+# CONFIG_VIDEO_CAFE_CCIC is not set -+# CONFIG_VIDEO_CADENCE is not set -+# CONFIG_VIDEO_ASPEED is not set -+# CONFIG_VIDEO_MUX is not set -+# CONFIG_VIDEO_XILINX is not set -+CONFIG_VIDEO_ROCKCHIP_CIF=y -+CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y -+# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set -+CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y -+# CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set -+CONFIG_VIDEO_ROCKCHIP_ISP=y -+CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X=y -+# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20 is not set -+CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21=y -+CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30=y -+CONFIG_VIDEO_ROCKCHIP_ISPP=y -+# CONFIG_VIDEO_ROCKCHIP_ISPP_FEC is not set -+# CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V10 is not set -+CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20=y -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set -+CONFIG_VIDEO_ROCKCHIP_RGA=y -+# CONFIG_DVB_PLATFORM_DRIVERS is not set -+# CONFIG_SDR_PLATFORM_DRIVERS is not set -+ -+# -+# MMC/SDIO DVB adapters -+# -+# CONFIG_SMS_SDIO_DRV is not set -+# CONFIG_V4L_TEST_DRIVERS is not set -+# CONFIG_DVB_TEST_DRIVERS is not set -+# end of Media drivers -+ -+# -+# Media ancillary drivers -+# -+CONFIG_MEDIA_ATTACH=y -+ -+# -+# Audio decoders, processors and mixers -+# -+# CONFIG_VIDEO_TVAUDIO is not set -+# CONFIG_VIDEO_TDA7432 is not set -+# CONFIG_VIDEO_TDA9840 is not set -+# CONFIG_VIDEO_TDA1997X is not set -+# CONFIG_VIDEO_TEA6415C is not set -+# CONFIG_VIDEO_TEA6420 is not set -+# CONFIG_VIDEO_MSP3400 is not set -+# CONFIG_VIDEO_CS3308 is not set -+# CONFIG_VIDEO_CS5345 is not set -+# CONFIG_VIDEO_CS53L32A is not set -+# CONFIG_VIDEO_TLV320AIC23B is not set -+# CONFIG_VIDEO_UDA1342 is not set -+# CONFIG_VIDEO_WM8775 is not set -+# CONFIG_VIDEO_WM8739 is not set -+# CONFIG_VIDEO_VP27SMPX is not set -+# CONFIG_VIDEO_SONY_BTF_MPX is not set -+# end of Audio decoders, processors and mixers -+ -+# -+# RDS decoders -+# -+# CONFIG_VIDEO_SAA6588 is not set -+# end of RDS decoders -+ -+# -+# Video decoders -+# -+# CONFIG_VIDEO_ADV7180 is not set -+# CONFIG_VIDEO_ADV7183 is not set -+# CONFIG_VIDEO_ADV748X is not set -+# CONFIG_VIDEO_ADV7604 is not set -+# CONFIG_VIDEO_ADV7842 is not set -+# CONFIG_VIDEO_BT819 is not set -+# CONFIG_VIDEO_BT856 is not set -+# CONFIG_VIDEO_BT866 is not set -+# CONFIG_VIDEO_KS0127 is not set -+# CONFIG_VIDEO_ML86V7667 is not set -+# CONFIG_VIDEO_SAA7110 is not set -+# CONFIG_VIDEO_SAA711X is not set -+# CONFIG_VIDEO_TC358743 is not set -+# CONFIG_VIDEO_TVP514X is not set -+# CONFIG_VIDEO_TVP5150 is not set -+# CONFIG_VIDEO_TVP7002 is not set -+# CONFIG_VIDEO_TW2804 is not set -+# CONFIG_VIDEO_TW9903 is not set -+# CONFIG_VIDEO_TW9906 is not set -+# CONFIG_VIDEO_TW9910 is not set -+# CONFIG_VIDEO_VPX3220 is not set -+# CONFIG_VIDEO_MAX9286 is not set -+ -+# -+# Video and audio decoders -+# -+# CONFIG_VIDEO_SAA717X is not set -+# CONFIG_VIDEO_CX25840 is not set -+# end of Video decoders -+ -+# -+# Video encoders -+# -+# CONFIG_VIDEO_SAA7127 is not set -+# CONFIG_VIDEO_SAA7185 is not set -+# CONFIG_VIDEO_ADV7170 is not set -+# CONFIG_VIDEO_ADV7175 is not set -+# CONFIG_VIDEO_ADV7343 is not set -+# CONFIG_VIDEO_ADV7393 is not set -+# CONFIG_VIDEO_ADV7511 is not set -+# CONFIG_VIDEO_AD9389B is not set -+# CONFIG_VIDEO_AK881X is not set -+# CONFIG_VIDEO_THS8200 is not set -+# end of Video encoders -+ -+# -+# Video improvement chips -+# -+# CONFIG_VIDEO_UPD64031A is not set -+# CONFIG_VIDEO_UPD64083 is not set -+# end of Video improvement chips -+ -+# -+# Audio/Video compression chips -+# -+# CONFIG_VIDEO_SAA6752HS is not set -+# end of Audio/Video compression chips -+ -+# -+# SDR tuner chips -+# -+# CONFIG_SDR_MAX2175 is not set -+# end of SDR tuner chips -+ -+# -+# Miscellaneous helper chips -+# -+# CONFIG_VIDEO_THS7303 is not set -+# CONFIG_VIDEO_M52790 is not set -+# CONFIG_VIDEO_I2C is not set -+# CONFIG_VIDEO_ST_MIPID02 is not set -+# end of Miscellaneous helper chips -+ -+# -+# Camera sensor devices -+# -+CONFIG_VIDEO_GC8034=y -+# CONFIG_VIDEO_HI556 is not set -+# CONFIG_VIDEO_IMX214 is not set -+# CONFIG_VIDEO_IMX219 is not set -+# CONFIG_VIDEO_IMX258 is not set -+# CONFIG_VIDEO_IMX274 is not set -+# CONFIG_VIDEO_IMX290 is not set -+# CONFIG_VIDEO_IMX319 is not set -+# CONFIG_VIDEO_IMX355 is not set -+# CONFIG_VIDEO_OV2640 is not set -+# CONFIG_VIDEO_OV2659 is not set -+# CONFIG_VIDEO_OV2680 is not set -+# CONFIG_VIDEO_OV2685 is not set -+# CONFIG_VIDEO_OV5640 is not set -+# CONFIG_VIDEO_OV5645 is not set -+# CONFIG_VIDEO_OV5647 is not set -+# CONFIG_VIDEO_OV6650 is not set -+# CONFIG_VIDEO_OV5670 is not set -+# CONFIG_VIDEO_OV5675 is not set -+CONFIG_VIDEO_OV5695=y -+CONFIG_VIDEO_OV7251=y -+# CONFIG_VIDEO_OV772X is not set -+# CONFIG_VIDEO_OV7640 is not set -+# CONFIG_VIDEO_OV7670 is not set -+# CONFIG_VIDEO_OV7740 is not set -+# CONFIG_VIDEO_OV8856 is not set -+# CONFIG_VIDEO_OV9640 is not set -+# CONFIG_VIDEO_OV9650 is not set -+# CONFIG_VIDEO_OV13858 is not set -+# CONFIG_VIDEO_VS6624 is not set -+# CONFIG_VIDEO_MT9M001 is not set -+# CONFIG_VIDEO_MT9M032 is not set -+# CONFIG_VIDEO_MT9M111 is not set -+# CONFIG_VIDEO_MT9P031 is not set -+# CONFIG_VIDEO_MT9T001 is not set -+# CONFIG_VIDEO_MT9T112 is not set -+# CONFIG_VIDEO_MT9V011 is not set -+# CONFIG_VIDEO_MT9V032 is not set -+# CONFIG_VIDEO_MT9V111 is not set -+# CONFIG_VIDEO_SR030PC30 is not set -+# CONFIG_VIDEO_NOON010PC30 is not set -+# CONFIG_VIDEO_M5MOLS is not set -+# CONFIG_VIDEO_RDACM20 is not set -+# CONFIG_VIDEO_RJ54N1 is not set -+# CONFIG_VIDEO_S5K6AA is not set -+# CONFIG_VIDEO_S5K6A3 is not set -+# CONFIG_VIDEO_S5K4ECGX is not set -+# CONFIG_VIDEO_S5K5BAF is not set -+# CONFIG_VIDEO_SMIAPP is not set -+# CONFIG_VIDEO_ET8EK8 is not set -+# CONFIG_VIDEO_S5C73M3 is not set -+# end of Camera sensor devices -+ -+# -+# Lens drivers -+# -+# CONFIG_VIDEO_AD5820 is not set -+# CONFIG_VIDEO_AK7375 is not set -+# CONFIG_VIDEO_DW9714 is not set -+# CONFIG_VIDEO_DW9768 is not set -+# CONFIG_VIDEO_DW9807_VCM is not set -+# end of Lens drivers -+ -+# -+# Flash devices -+# -+# CONFIG_VIDEO_ADP1653 is not set -+# CONFIG_VIDEO_LM3560 is not set -+# CONFIG_VIDEO_LM3646 is not set -+# end of Flash devices -+ -+# -+# SPI helper chips -+# -+# CONFIG_VIDEO_GS1662 is not set -+# end of SPI helper chips -+ -+# -+# Media SPI Adapters -+# -+CONFIG_CXD2880_SPI_DRV=m -+# end of Media SPI Adapters -+ -+CONFIG_MEDIA_TUNER=y -+ -+# -+# Customize TV tuners -+# -+CONFIG_MEDIA_TUNER_SIMPLE=m -+CONFIG_MEDIA_TUNER_TDA18250=m -+CONFIG_MEDIA_TUNER_TDA8290=m -+CONFIG_MEDIA_TUNER_TDA827X=m -+CONFIG_MEDIA_TUNER_TDA18271=m -+CONFIG_MEDIA_TUNER_TDA9887=m -+CONFIG_MEDIA_TUNER_TEA5761=m -+CONFIG_MEDIA_TUNER_TEA5767=m -+CONFIG_MEDIA_TUNER_MSI001=m -+CONFIG_MEDIA_TUNER_MT20XX=m -+CONFIG_MEDIA_TUNER_MT2060=m -+CONFIG_MEDIA_TUNER_MT2063=m -+CONFIG_MEDIA_TUNER_MT2266=m -+CONFIG_MEDIA_TUNER_MT2131=m -+CONFIG_MEDIA_TUNER_QT1010=m -+CONFIG_MEDIA_TUNER_XC2028=m -+CONFIG_MEDIA_TUNER_XC5000=m -+CONFIG_MEDIA_TUNER_XC4000=m -+CONFIG_MEDIA_TUNER_MXL5005S=m -+CONFIG_MEDIA_TUNER_MXL5007T=m -+CONFIG_MEDIA_TUNER_MC44S803=m -+CONFIG_MEDIA_TUNER_MAX2165=m -+CONFIG_MEDIA_TUNER_TDA18218=m -+CONFIG_MEDIA_TUNER_FC0011=m -+CONFIG_MEDIA_TUNER_FC0012=m -+CONFIG_MEDIA_TUNER_FC0013=m -+CONFIG_MEDIA_TUNER_TDA18212=m -+CONFIG_MEDIA_TUNER_E4000=m -+CONFIG_MEDIA_TUNER_FC2580=m -+CONFIG_MEDIA_TUNER_M88RS6000T=m -+CONFIG_MEDIA_TUNER_TUA9001=m -+CONFIG_MEDIA_TUNER_SI2157=m -+CONFIG_MEDIA_TUNER_IT913X=m -+CONFIG_MEDIA_TUNER_R820T=m -+CONFIG_MEDIA_TUNER_MXL301RF=m -+CONFIG_MEDIA_TUNER_QM1D1C0042=m -+CONFIG_MEDIA_TUNER_QM1D1B0004=m -+# end of Customize TV tuners -+ -+# -+# Customise DVB Frontends -+# -+ -+# -+# Multistandard (satellite) frontends -+# -+CONFIG_DVB_STB0899=m -+CONFIG_DVB_STB6100=m -+CONFIG_DVB_STV090x=m -+CONFIG_DVB_STV0910=m -+CONFIG_DVB_STV6110x=m -+CONFIG_DVB_STV6111=m -+CONFIG_DVB_MXL5XX=m -+CONFIG_DVB_M88DS3103=m -+ -+# -+# Multistandard (cable + terrestrial) frontends -+# -+CONFIG_DVB_DRXK=m -+CONFIG_DVB_TDA18271C2DD=m -+CONFIG_DVB_SI2165=m -+CONFIG_DVB_MN88472=m -+CONFIG_DVB_MN88473=m -+ -+# -+# DVB-S (satellite) frontends -+# -+CONFIG_DVB_CX24110=m -+CONFIG_DVB_CX24123=m -+CONFIG_DVB_MT312=m -+CONFIG_DVB_ZL10036=m -+CONFIG_DVB_ZL10039=m -+CONFIG_DVB_S5H1420=m -+CONFIG_DVB_STV0288=m -+CONFIG_DVB_STB6000=m -+CONFIG_DVB_STV0299=m -+CONFIG_DVB_STV6110=m -+CONFIG_DVB_STV0900=m -+CONFIG_DVB_TDA8083=m -+CONFIG_DVB_TDA10086=m -+CONFIG_DVB_TDA8261=m -+CONFIG_DVB_VES1X93=m -+CONFIG_DVB_TUNER_ITD1000=m -+CONFIG_DVB_TUNER_CX24113=m -+CONFIG_DVB_TDA826X=m -+CONFIG_DVB_TUA6100=m -+CONFIG_DVB_CX24116=m -+CONFIG_DVB_CX24117=m -+CONFIG_DVB_CX24120=m -+CONFIG_DVB_SI21XX=m -+CONFIG_DVB_TS2020=m -+CONFIG_DVB_DS3000=m -+CONFIG_DVB_MB86A16=m -+CONFIG_DVB_TDA10071=m -+ -+# -+# DVB-T (terrestrial) frontends -+# -+CONFIG_DVB_SP8870=m -+CONFIG_DVB_SP887X=m -+CONFIG_DVB_CX22700=m -+CONFIG_DVB_CX22702=m -+CONFIG_DVB_S5H1432=m -+CONFIG_DVB_DRXD=m -+CONFIG_DVB_L64781=m -+CONFIG_DVB_TDA1004X=m -+CONFIG_DVB_NXT6000=m -+CONFIG_DVB_MT352=m -+CONFIG_DVB_ZL10353=m -+CONFIG_DVB_DIB3000MB=m -+CONFIG_DVB_DIB3000MC=m -+CONFIG_DVB_DIB7000M=m -+CONFIG_DVB_DIB7000P=m -+CONFIG_DVB_DIB9000=m -+CONFIG_DVB_TDA10048=m -+CONFIG_DVB_AF9013=m -+CONFIG_DVB_EC100=m -+CONFIG_DVB_STV0367=m -+CONFIG_DVB_CXD2820R=m -+CONFIG_DVB_CXD2841ER=m -+CONFIG_DVB_RTL2830=m -+CONFIG_DVB_RTL2832=m -+CONFIG_DVB_RTL2832_SDR=m -+CONFIG_DVB_SI2168=m -+CONFIG_DVB_ZD1301_DEMOD=m -+CONFIG_DVB_CXD2880=m -+ -+# -+# DVB-C (cable) frontends -+# -+CONFIG_DVB_VES1820=m -+CONFIG_DVB_TDA10021=m -+CONFIG_DVB_TDA10023=m -+CONFIG_DVB_STV0297=m -+ -+# -+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -+# -+CONFIG_DVB_NXT200X=m -+CONFIG_DVB_OR51211=m -+CONFIG_DVB_OR51132=m -+CONFIG_DVB_BCM3510=m -+CONFIG_DVB_LGDT330X=m -+CONFIG_DVB_LGDT3305=m -+CONFIG_DVB_LGDT3306A=m -+CONFIG_DVB_LG2160=m -+CONFIG_DVB_S5H1409=m -+CONFIG_DVB_AU8522=m -+CONFIG_DVB_AU8522_DTV=m -+CONFIG_DVB_AU8522_V4L=m -+CONFIG_DVB_S5H1411=m -+ -+# -+# ISDB-T (terrestrial) frontends -+# -+CONFIG_DVB_S921=m -+CONFIG_DVB_DIB8000=m -+CONFIG_DVB_MB86A20S=m -+ -+# -+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends -+# -+CONFIG_DVB_TC90522=m -+CONFIG_DVB_MN88443X=m -+ -+# -+# Digital terrestrial only tuners/PLL -+# -+CONFIG_DVB_PLL=m -+CONFIG_DVB_TUNER_DIB0070=m -+CONFIG_DVB_TUNER_DIB0090=m -+ -+# -+# SEC control devices for DVB-S -+# -+CONFIG_DVB_DRX39XYJ=m -+CONFIG_DVB_LNBH25=m -+CONFIG_DVB_LNBH29=m -+CONFIG_DVB_LNBP21=m -+CONFIG_DVB_LNBP22=m -+CONFIG_DVB_ISL6405=m -+CONFIG_DVB_ISL6421=m -+CONFIG_DVB_ISL6423=m -+CONFIG_DVB_A8293=m -+CONFIG_DVB_LGS8GL5=m -+CONFIG_DVB_LGS8GXX=m -+CONFIG_DVB_ATBM8830=m -+CONFIG_DVB_TDA665x=m -+CONFIG_DVB_IX2505V=m -+CONFIG_DVB_M88RS2000=m -+CONFIG_DVB_AF9033=m -+CONFIG_DVB_HORUS3A=m -+CONFIG_DVB_ASCOT2E=m -+CONFIG_DVB_HELENE=m -+ -+# -+# Common Interface (EN50221) controller drivers -+# -+CONFIG_DVB_CXD2099=m -+CONFIG_DVB_SP2=m -+# end of Customise DVB Frontends -+ -+# -+# Tools to develop new frontends -+# -+# CONFIG_DVB_DUMMY_FE is not set -+# end of Media ancillary drivers -+ -+# -+# Graphics support -+# -+# CONFIG_VGA_ARB is not set -+CONFIG_DRM=y -+CONFIG_DRM_IGNORE_IOTCL_PERMIT=y -+CONFIG_DRM_MIPI_DSI=y -+# CONFIG_DRM_DP_AUX_CHARDEV is not set -+# CONFIG_DRM_DEBUG_MM is not set -+# CONFIG_DRM_DEBUG_SELFTEST is not set -+CONFIG_DRM_KMS_HELPER=y -+CONFIG_DRM_KMS_FB_HELPER=y -+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -+CONFIG_DRM_FBDEV_EMULATION=y -+CONFIG_DRM_FBDEV_OVERALLOC=100 -+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -+CONFIG_DRM_LOAD_EDID_FIRMWARE=y -+# CONFIG_DRM_DP_CEC is not set -+CONFIG_DRM_GEM_CMA_HELPER=y -+ -+# -+# I2C encoder or helper chips -+# -+# CONFIG_DRM_I2C_CH7006 is not set -+# CONFIG_DRM_I2C_SIL164 is not set -+# CONFIG_DRM_I2C_NXP_TDA998X is not set -+# CONFIG_DRM_I2C_NXP_TDA9950 is not set -+# end of I2C encoder or helper chips -+ -+# -+# ARM devices -+# -+# CONFIG_DRM_HDLCD is not set -+# CONFIG_DRM_MALI_DISPLAY is not set -+# CONFIG_DRM_KOMEDA is not set -+# end of ARM devices -+ -+# CONFIG_DRM_RADEON is not set -+# CONFIG_DRM_AMDGPU is not set -+# CONFIG_DRM_NOUVEAU is not set -+# CONFIG_DRM_VGEM is not set -+# CONFIG_DRM_VKMS is not set -+CONFIG_DRM_ROCKCHIP=y -+# CONFIG_ROCKCHIP_DRM_CUBIC_LUT is not set -+CONFIG_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_ROCKCHIP_CDN_DP=y -+CONFIG_ROCKCHIP_DW_HDMI=y -+CONFIG_ROCKCHIP_DW_MIPI_DSI=y -+CONFIG_ROCKCHIP_INNO_HDMI=y -+CONFIG_ROCKCHIP_LVDS=y -+CONFIG_ROCKCHIP_RGB=y -+# CONFIG_ROCKCHIP_RK3066_HDMI is not set -+# CONFIG_DRM_UDL is not set -+# CONFIG_DRM_AST is not set -+# CONFIG_DRM_MGAG200 is not set -+# CONFIG_DRM_RCAR_DW_HDMI is not set -+# CONFIG_DRM_RCAR_LVDS is not set -+# CONFIG_DRM_QXL is not set -+# CONFIG_DRM_BOCHS is not set -+CONFIG_DRM_PANEL=y -+ -+# -+# Display Panels -+# -+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set -+# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -+# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set -+# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -+# CONFIG_DRM_PANEL_LVDS is not set -+CONFIG_DRM_PANEL_SIMPLE=y -+# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set -+# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set -+# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set -+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set -+# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set -+# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set -+# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set -+# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set -+# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set -+# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set -+# CONFIG_DRM_PANEL_LG_LG4573 is not set -+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -+# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set -+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -+# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set -+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set -+# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set -+# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set -+# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set -+# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set -+# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set -+# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set -+# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set -+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -+# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set -+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set -+# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set -+# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set -+# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set -+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -+# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set -+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set -+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set -+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set -+# CONFIG_DRM_PANEL_TPO_TPG110 is not set -+# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set -+# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set -+# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set -+# end of Display Panels -+ -+CONFIG_DRM_BRIDGE=y -+CONFIG_DRM_PANEL_BRIDGE=y -+ -+# -+# Display Interface Bridges -+# -+# CONFIG_DRM_CDNS_DSI is not set -+# CONFIG_DRM_CHRONTEL_CH7033 is not set -+# CONFIG_DRM_DISPLAY_CONNECTOR is not set -+# CONFIG_DRM_LONTIUM_LT9611 is not set -+# CONFIG_DRM_LVDS_CODEC is not set -+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set -+# CONFIG_DRM_NWL_MIPI_DSI is not set -+# CONFIG_DRM_NXP_PTN3460 is not set -+# CONFIG_DRM_PARADE_PS8622 is not set -+# CONFIG_DRM_PARADE_PS8640 is not set -+# CONFIG_DRM_SIL_SII8620 is not set -+CONFIG_DRM_SII902X=y -+# CONFIG_DRM_SII9234 is not set -+# CONFIG_DRM_SIMPLE_BRIDGE is not set -+# CONFIG_DRM_THINE_THC63LVD1024 is not set -+# CONFIG_DRM_TOSHIBA_TC358762 is not set -+# CONFIG_DRM_TOSHIBA_TC358764 is not set -+# CONFIG_DRM_TOSHIBA_TC358767 is not set -+# CONFIG_DRM_TOSHIBA_TC358768 is not set -+# CONFIG_DRM_TOSHIBA_TC358775 is not set -+# CONFIG_DRM_TI_TFP410 is not set -+# CONFIG_DRM_TI_SN65DSI86 is not set -+# CONFIG_DRM_TI_TPD12S015 is not set -+# CONFIG_DRM_ANALOGIX_ANX6345 is not set -+# CONFIG_DRM_ANALOGIX_ANX78XX is not set -+CONFIG_DRM_ANALOGIX_DP=y -+# CONFIG_DRM_I2C_ADV7511 is not set -+# CONFIG_DRM_CDNS_MHDP8546 is not set -+CONFIG_DRM_DW_HDMI=y -+# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set -+CONFIG_DRM_DW_HDMI_I2S_AUDIO=y -+CONFIG_DRM_DW_HDMI_CEC=y -+CONFIG_DRM_DW_MIPI_DSI=y -+# end of Display Interface Bridges -+ -+# CONFIG_DRM_ETNAVIV is not set -+# CONFIG_DRM_ARCPGU is not set -+# CONFIG_DRM_HISI_HIBMC is not set -+# CONFIG_DRM_HISI_KIRIN is not set -+# CONFIG_DRM_MXSFB is not set -+# CONFIG_DRM_CIRRUS_QEMU is not set -+# CONFIG_DRM_GM12U320 is not set -+# CONFIG_TINYDRM_HX8357D is not set -+# CONFIG_TINYDRM_ILI9225 is not set -+# CONFIG_TINYDRM_ILI9341 is not set -+# CONFIG_TINYDRM_ILI9486 is not set -+# CONFIG_TINYDRM_MI0283QT is not set -+# CONFIG_TINYDRM_REPAPER is not set -+# CONFIG_TINYDRM_ST7586 is not set -+# CONFIG_TINYDRM_ST7735R is not set -+# CONFIG_DRM_PL111 is not set -+# CONFIG_DRM_LIMA is not set -+# CONFIG_DRM_PANFROST is not set -+# CONFIG_DRM_TIDSS is not set -+# CONFIG_DRM_LEGACY is not set -+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -+CONFIG_MALI400=y -+CONFIG_MALI450=y -+# CONFIG_MALI470 is not set -+# CONFIG_MALI400_DEBUG is not set -+# CONFIG_MALI400_PROFILING is not set -+# CONFIG_MALI400_UMP is not set -+CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y -+CONFIG_MALI_SHARED_INTERRUPTS=y -+# CONFIG_MALI_PMU_PARALLEL_POWER_UP is not set -+CONFIG_MALI_DT=y -+CONFIG_MALI_DEVFREQ=y -+# CONFIG_MALI_QUIET is not set -+CONFIG_MALI_MIDGARD_FOR_ANDROID=y -+# CONFIG_MALI_MIDGARD_FOR_LINUX is not set -+CONFIG_MALI_MIDGARD=y -+# CONFIG_MALI_GATOR_SUPPORT is not set -+# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set -+# CONFIG_MALI_DMA_FENCE is not set -+CONFIG_MALI_EXPERT=y -+# CONFIG_MALI_CORESTACK is not set -+# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set -+# CONFIG_MALI_PLATFORM_FAKE is not set -+# CONFIG_MALI_PLATFORM_DEVICETREE is not set -+CONFIG_MALI_PLATFORM_THIRDPARTY=y -+CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk" -+CONFIG_MALI_DEBUG=y -+CONFIG_MALI_FENCE_DEBUG=y -+# CONFIG_MALI_NO_MALI is not set -+# CONFIG_MALI_TRACE_TIMELINE is not set -+# CONFIG_MALI_SYSTEM_TRACE is not set -+# CONFIG_MALI_GPU_MMU_AARCH64 is not set -+CONFIG_MALI_PWRSOFT_765=y -+# CONFIG_MALI_KUTF is not set -+CONFIG_MALI_BIFROST_FOR_ANDROID=y -+# CONFIG_MALI_BIFROST_FOR_LINUX is not set -+CONFIG_MALI_BIFROST=y -+# CONFIG_MALI_BIFROST_GATOR_SUPPORT is not set -+CONFIG_MALI_BIFROST_ENABLE_TRACE=y -+CONFIG_MALI_BIFROST_DEVFREQ=y -+# CONFIG_MALI_BIFROST_DMA_FENCE is not set -+CONFIG_MALI_PLATFORM_NAME="rk" -+# CONFIG_MALI_ARBITER_SUPPORT is not set -+CONFIG_MALI_BIFROST_EXPERT=y -+CONFIG_MALI_BIFROST_DEBUG=y -+CONFIG_MALI_BIFROST_FENCE_DEBUG=y -+# CONFIG_MALI_BIFROST_NO_MALI is not set -+CONFIG_MALI_REAL_HW=y -+CONFIG_MALI_BIFROST_SYSTEM_TRACE=y -+# CONFIG_MALI_2MB_ALLOC is not set -+# CONFIG_MALI_MEMORY_FULLY_BACKED is not set -+# CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND is not set -+# CONFIG_MALI_DMA_BUF_LEGACY_COMPAT is not set -+# CONFIG_MALI_HW_ERRATA_1485982_NOT_AFFECTED is not set -+# CONFIG_MALI_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is not set -+# CONFIG_MALI_GEM5_BUILD is not set -+# CONFIG_MALI_JOB_DUMP is not set -+# CONFIG_MALI_BIFROST_PRFCNT_SET_SECONDARY is not set -+# CONFIG_MALI_PRFCNT_SET_SECONDARY_VIA_DEBUG_FS is not set -+ -+# -+# Frame buffer Devices -+# -+CONFIG_FB_CMDLINE=y -+CONFIG_FB_NOTIFY=y -+CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+CONFIG_FB_SYS_FILLRECT=y -+CONFIG_FB_SYS_COPYAREA=y -+CONFIG_FB_SYS_IMAGEBLIT=y -+# CONFIG_FB_FOREIGN_ENDIAN is not set -+CONFIG_FB_SYS_FOPS=y -+CONFIG_FB_DEFERRED_IO=y -+# CONFIG_FB_MODE_HELPERS is not set -+# CONFIG_FB_TILEBLITTING is not set -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_CIRRUS is not set -+# CONFIG_FB_PM2 is not set -+# CONFIG_FB_ARMCLCD is not set -+# CONFIG_FB_CYBER2000 is not set -+# CONFIG_FB_ASILIANT is not set -+# CONFIG_FB_IMSTT is not set -+# CONFIG_FB_UVESA is not set -+# CONFIG_FB_OPENCORES is not set -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_NVIDIA is not set -+# CONFIG_FB_RIVA is not set -+# CONFIG_FB_I740 is not set -+# CONFIG_FB_MATROX is not set -+# CONFIG_FB_RADEON is not set -+# CONFIG_FB_ATY128 is not set -+# CONFIG_FB_ATY is not set -+# CONFIG_FB_S3 is not set -+# CONFIG_FB_SAVAGE is not set -+# CONFIG_FB_SIS is not set -+# CONFIG_FB_NEOMAGIC is not set -+# CONFIG_FB_KYRO is not set -+# CONFIG_FB_3DFX is not set -+# CONFIG_FB_VOODOO1 is not set -+# CONFIG_FB_VT8623 is not set -+# CONFIG_FB_TRIDENT is not set -+# CONFIG_FB_ARK is not set -+# CONFIG_FB_PM3 is not set -+# CONFIG_FB_CARMINE is not set -+# CONFIG_FB_SMSCUFX is not set -+# CONFIG_FB_UDL is not set -+# CONFIG_FB_IBM_GXT4500 is not set -+# CONFIG_FB_VIRTUAL is not set -+# CONFIG_FB_METRONOME is not set -+# CONFIG_FB_MB862XX is not set -+# CONFIG_FB_SIMPLE is not set -+# CONFIG_FB_SSD1307 is not set -+# CONFIG_FB_SM712 is not set -+# end of Frame buffer Devices -+ -+# -+# Backlight & LCD device support -+# -+# CONFIG_LCD_CLASS_DEVICE is not set -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+# CONFIG_BACKLIGHT_KTD253 is not set -+CONFIG_BACKLIGHT_PWM=y -+# CONFIG_BACKLIGHT_QCOM_WLED is not set -+# CONFIG_BACKLIGHT_ADP8860 is not set -+# CONFIG_BACKLIGHT_ADP8870 is not set -+# CONFIG_BACKLIGHT_LM3630A is not set -+# CONFIG_BACKLIGHT_LM3639 is not set -+# CONFIG_BACKLIGHT_LP855X is not set -+# CONFIG_BACKLIGHT_GPIO is not set -+# CONFIG_BACKLIGHT_LV5207LP is not set -+# CONFIG_BACKLIGHT_BD6107 is not set -+# CONFIG_BACKLIGHT_ARCXCNN is not set -+# CONFIG_BACKLIGHT_LED is not set -+# end of Backlight & LCD device support -+ -+# -+# Rockchip Misc Video driver -+# -+ -+# -+# RGA -+# -+# CONFIG_ROCKCHIP_RGA is not set -+# end of RGA -+ -+CONFIG_ROCKCHIP_RGA2=y -+# CONFIG_ROCKCHIP_RGA2_PROC_FS is not set -+CONFIG_ROCKCHIP_RGA2_DEBUG_FS=y -+CONFIG_ROCKCHIP_RGA2_DEBUGGER=y -+ -+# -+# IEP -+# -+# CONFIG_IEP is not set -+# end of IEP -+ -+CONFIG_ROCKCHIP_MPP_SERVICE=y -+CONFIG_ROCKCHIP_MPP_PROC_FS=y -+CONFIG_ROCKCHIP_MPP_RKVDEC=y -+CONFIG_ROCKCHIP_MPP_RKVDEC2=y -+CONFIG_ROCKCHIP_MPP_RKVENC=y -+CONFIG_ROCKCHIP_MPP_RKVENC2=y -+CONFIG_ROCKCHIP_MPP_VDPU1=y -+CONFIG_ROCKCHIP_MPP_VEPU1=y -+CONFIG_ROCKCHIP_MPP_VDPU2=y -+CONFIG_ROCKCHIP_MPP_VEPU2=y -+CONFIG_ROCKCHIP_MPP_IEP2=y -+CONFIG_ROCKCHIP_MPP_JPGDEC=y -+# end of Rockchip Misc Video driver -+ -+CONFIG_VIDEOMODE_HELPERS=y -+CONFIG_HDMI=y -+ -+# -+# Console display driver support -+# -+CONFIG_DUMMY_CONSOLE=y -+CONFIG_DUMMY_CONSOLE_COLUMNS=80 -+CONFIG_DUMMY_CONSOLE_ROWS=25 -+# CONFIG_FRAMEBUFFER_CONSOLE is not set -+# end of Console display driver support -+ -+# CONFIG_LOGO is not set -+# end of Graphics support -+ -+# CONFIG_SOUND is not set -+# CONFIG_SND is not set -+CONFIG_SND_TIMER=y -+CONFIG_SND_PCM=y -+CONFIG_SND_PCM_ELD=y -+CONFIG_SND_PCM_IEC958=y -+CONFIG_SND_DMAENGINE_PCM=y -+CONFIG_SND_HWDEP=y -+CONFIG_SND_SEQ_DEVICE=y -+CONFIG_SND_RAWMIDI=y -+CONFIG_SND_JACK=y -+CONFIG_SND_JACK_INPUT_DEV=y -+# CONFIG_SND_OSSEMUL is not set -+CONFIG_SND_PCM_TIMER=y -+CONFIG_SND_HRTIMER=y -+CONFIG_SND_DYNAMIC_MINORS=y -+CONFIG_SND_MAX_CARDS=32 -+# CONFIG_SND_SUPPORT_OLD_API is not set -+CONFIG_SND_PROC_FS=y -+CONFIG_SND_VERBOSE_PROCFS=y -+# CONFIG_SND_VERBOSE_PRINTK is not set -+# CONFIG_SND_DEBUG is not set -+CONFIG_SND_SEQUENCER=y -+CONFIG_SND_SEQ_DUMMY=y -+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -+CONFIG_SND_SEQ_MIDI_EVENT=y -+CONFIG_SND_SEQ_MIDI=y -+CONFIG_SND_DRIVERS=y -+# CONFIG_SND_DUMMY is not set -+# CONFIG_SND_ALOOP is not set -+# CONFIG_SND_VIRMIDI is not set -+# CONFIG_SND_MTPAV is not set -+# CONFIG_SND_SERIAL_U16550 is not set -+# CONFIG_SND_MPU401 is not set -+# CONFIG_SND_PCI is not set -+ -+# -+# HD-Audio -+# -+# end of HD-Audio -+ -+CONFIG_SND_HDA_PREALLOC_SIZE=64 -+# CONFIG_SND_SPI is not set -+CONFIG_SND_USB=y -+CONFIG_SND_USB_AUDIO=y -+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y -+# CONFIG_SND_USB_UA101 is not set -+# CONFIG_SND_USB_CAIAQ is not set -+# CONFIG_SND_USB_6FIRE is not set -+# CONFIG_SND_USB_HIFACE is not set -+# CONFIG_SND_BCD2000 is not set -+# CONFIG_SND_USB_POD is not set -+# CONFIG_SND_USB_PODHD is not set -+# CONFIG_SND_USB_TONEPORT is not set -+# CONFIG_SND_USB_VARIAX is not set -+CONFIG_SND_SOC=y -+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -+# CONFIG_SND_SOC_AMD_ACP is not set -+# CONFIG_SND_ATMEL_SOC is not set -+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set -+# CONFIG_SND_DESIGNWARE_I2S is not set -+ -+# -+# SoC Audio for Freescale CPUs -+# -+ -+# -+# Common SoC Audio options for Freescale CPUs: -+# -+# CONFIG_SND_SOC_FSL_ASRC is not set -+# CONFIG_SND_SOC_FSL_SAI is not set -+# CONFIG_SND_SOC_FSL_AUDMIX is not set -+# CONFIG_SND_SOC_FSL_SSI is not set -+# CONFIG_SND_SOC_FSL_SPDIF is not set -+# CONFIG_SND_SOC_FSL_ESAI is not set -+# CONFIG_SND_SOC_FSL_MICFIL is not set -+# CONFIG_SND_SOC_IMX_AUDMUX is not set -+# end of SoC Audio for Freescale CPUs -+ -+# CONFIG_SND_I2S_HI6210_I2S is not set -+# CONFIG_SND_SOC_IMG is not set -+# CONFIG_SND_SOC_MTK_BTCVSD is not set -+CONFIG_SND_SOC_ROCKCHIP=y -+CONFIG_SND_SOC_ROCKCHIP_I2S=y -+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y -+CONFIG_SND_SOC_ROCKCHIP_PDM=y -+CONFIG_SND_SOC_ROCKCHIP_SPDIF=y -+CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y -+# CONFIG_SND_SOC_ROCKCHIP_VAD is not set -+CONFIG_SND_SOC_ROCKCHIP_MAX98090=y -+CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y -+CONFIG_SND_SOC_ROCKCHIP_RT5645=y -+CONFIG_SND_SOC_ROCKCHIP_HDMI=y -+# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set -+# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set -+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set -+ -+# -+# STMicroelectronics STM32 SOC audio support -+# -+# end of STMicroelectronics STM32 SOC audio support -+ -+# CONFIG_SND_SOC_XILINX_I2S is not set -+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set -+# CONFIG_SND_SOC_XILINX_SPDIF is not set -+# CONFIG_SND_SOC_XTFPGA_I2S is not set -+# CONFIG_ZX_TDM is not set -+CONFIG_SND_SOC_I2C_AND_SPI=y -+ -+# -+# CODEC drivers -+# -+# CONFIG_SND_SOC_AC97_CODEC is not set -+# CONFIG_SND_SOC_ADAU1701 is not set -+# CONFIG_SND_SOC_ADAU1761_I2C is not set -+# CONFIG_SND_SOC_ADAU1761_SPI is not set -+# CONFIG_SND_SOC_ADAU7002 is not set -+# CONFIG_SND_SOC_ADAU7118_HW is not set -+# CONFIG_SND_SOC_ADAU7118_I2C is not set -+# CONFIG_SND_SOC_AK4104 is not set -+# CONFIG_SND_SOC_AK4118 is not set -+# CONFIG_SND_SOC_AK4458 is not set -+# CONFIG_SND_SOC_AK4554 is not set -+# CONFIG_SND_SOC_AK4613 is not set -+# CONFIG_SND_SOC_AK4642 is not set -+# CONFIG_SND_SOC_AK5386 is not set -+# CONFIG_SND_SOC_AK5558 is not set -+# CONFIG_SND_SOC_ALC5623 is not set -+# CONFIG_SND_SOC_BD28623 is not set -+# CONFIG_SND_SOC_BT_SCO is not set -+# CONFIG_SND_SOC_CS35L32 is not set -+# CONFIG_SND_SOC_CS35L33 is not set -+# CONFIG_SND_SOC_CS35L34 is not set -+# CONFIG_SND_SOC_CS35L35 is not set -+# CONFIG_SND_SOC_CS35L36 is not set -+# CONFIG_SND_SOC_CS42L42 is not set -+# CONFIG_SND_SOC_CS42L51_I2C is not set -+# CONFIG_SND_SOC_CS42L52 is not set -+# CONFIG_SND_SOC_CS42L56 is not set -+# CONFIG_SND_SOC_CS42L73 is not set -+# CONFIG_SND_SOC_CS4234 is not set -+# CONFIG_SND_SOC_CS4265 is not set -+# CONFIG_SND_SOC_CS4270 is not set -+# CONFIG_SND_SOC_CS4271_I2C is not set -+# CONFIG_SND_SOC_CS4271_SPI is not set -+# CONFIG_SND_SOC_CS42XX8_I2C is not set -+# CONFIG_SND_SOC_CS43130 is not set -+# CONFIG_SND_SOC_CS4341 is not set -+# CONFIG_SND_SOC_CS4349 is not set -+# CONFIG_SND_SOC_CS53L30 is not set -+# CONFIG_SND_SOC_CX2072X is not set -+# CONFIG_SND_SOC_DA7213 is not set -+# CONFIG_SND_SOC_DMIC is not set -+CONFIG_SND_SOC_DUMMY_CODEC=y -+CONFIG_SND_SOC_HDMI_CODEC=y -+# CONFIG_SND_SOC_ES7134 is not set -+CONFIG_SND_SOC_ES7202=y -+# CONFIG_SND_SOC_ES7210 is not set -+# CONFIG_SND_SOC_ES7241 is not set -+CONFIG_SND_SOC_ES7243E=y -+CONFIG_SND_SOC_ES8311=y -+CONFIG_SND_SOC_ES8316=y -+# CONFIG_SND_SOC_ES8323 is not set -+# CONFIG_SND_SOC_ES8328_I2C is not set -+# CONFIG_SND_SOC_ES8328_SPI is not set -+# CONFIG_SND_SOC_ES8396 is not set -+# CONFIG_SND_SOC_GTM601 is not set -+# CONFIG_SND_SOC_INNO_RK3036 is not set -+# CONFIG_SND_SOC_MAX98088 is not set -+CONFIG_SND_SOC_MAX98090=y -+# CONFIG_SND_SOC_MAX98357A is not set -+# CONFIG_SND_SOC_MAX98504 is not set -+# CONFIG_SND_SOC_MAX9867 is not set -+# CONFIG_SND_SOC_MAX98927 is not set -+# CONFIG_SND_SOC_MAX98373_I2C is not set -+# CONFIG_SND_SOC_MAX98390 is not set -+# CONFIG_SND_SOC_MAX9860 is not set -+# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set -+# CONFIG_SND_SOC_PCM1681 is not set -+# CONFIG_SND_SOC_PCM1789_I2C is not set -+# CONFIG_SND_SOC_PCM179X_I2C is not set -+# CONFIG_SND_SOC_PCM179X_SPI is not set -+# CONFIG_SND_SOC_PCM186X_I2C is not set -+# CONFIG_SND_SOC_PCM186X_SPI is not set -+# CONFIG_SND_SOC_PCM3060_I2C is not set -+# CONFIG_SND_SOC_PCM3060_SPI is not set -+# CONFIG_SND_SOC_PCM3168A_I2C is not set -+# CONFIG_SND_SOC_PCM3168A_SPI is not set -+# CONFIG_SND_SOC_PCM512x_I2C is not set -+# CONFIG_SND_SOC_PCM512x_SPI is not set -+# CONFIG_SND_SOC_RK312X is not set -+# CONFIG_SND_SOC_RK3228 is not set -+CONFIG_SND_SOC_RK3308=y -+CONFIG_SND_SOC_RK3328=y -+CONFIG_SND_SOC_RK817=y -+CONFIG_SND_SOC_RK_CODEC_DIGITAL=y -+CONFIG_SND_SOC_RL6231=y -+CONFIG_SND_SOC_RT5616=y -+# CONFIG_SND_SOC_RT5631 is not set -+CONFIG_SND_SOC_RT5640=y -+CONFIG_SND_SOC_RT5645=y -+CONFIG_SND_SOC_RT5651=y -+# CONFIG_SND_SOC_SGTL5000 is not set -+# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -+# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -+CONFIG_SND_SOC_SPDIF=y -+# CONFIG_SND_SOC_SSM2305 is not set -+# CONFIG_SND_SOC_SSM2602_SPI is not set -+# CONFIG_SND_SOC_SSM2602_I2C is not set -+# CONFIG_SND_SOC_SSM4567 is not set -+# CONFIG_SND_SOC_STA32X is not set -+# CONFIG_SND_SOC_STA350 is not set -+# CONFIG_SND_SOC_STI_SAS is not set -+# CONFIG_SND_SOC_TAS2552 is not set -+# CONFIG_SND_SOC_TAS2562 is not set -+# CONFIG_SND_SOC_TAS2764 is not set -+# CONFIG_SND_SOC_TAS2770 is not set -+# CONFIG_SND_SOC_TAS5086 is not set -+# CONFIG_SND_SOC_TAS571X is not set -+# CONFIG_SND_SOC_TAS5720 is not set -+# CONFIG_SND_SOC_TAS6424 is not set -+# CONFIG_SND_SOC_TDA7419 is not set -+# CONFIG_SND_SOC_TFA9879 is not set -+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set -+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set -+# CONFIG_SND_SOC_TLV320AIC31XX is not set -+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set -+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -+# CONFIG_SND_SOC_TLV320AIC3X is not set -+# CONFIG_SND_SOC_TLV320ADCX140 is not set -+CONFIG_SND_SOC_TS3A227E=y -+# CONFIG_SND_SOC_TSCS42XX is not set -+# CONFIG_SND_SOC_TSCS454 is not set -+# CONFIG_SND_SOC_UDA1334 is not set -+# CONFIG_SND_SOC_WM8510 is not set -+# CONFIG_SND_SOC_WM8523 is not set -+# CONFIG_SND_SOC_WM8524 is not set -+# CONFIG_SND_SOC_WM8580 is not set -+# CONFIG_SND_SOC_WM8711 is not set -+# CONFIG_SND_SOC_WM8728 is not set -+# CONFIG_SND_SOC_WM8731 is not set -+# CONFIG_SND_SOC_WM8737 is not set -+# CONFIG_SND_SOC_WM8741 is not set -+# CONFIG_SND_SOC_WM8750 is not set -+# CONFIG_SND_SOC_WM8753 is not set -+# CONFIG_SND_SOC_WM8770 is not set -+# CONFIG_SND_SOC_WM8776 is not set -+# CONFIG_SND_SOC_WM8782 is not set -+# CONFIG_SND_SOC_WM8804_I2C is not set -+# CONFIG_SND_SOC_WM8804_SPI is not set -+# CONFIG_SND_SOC_WM8903 is not set -+# CONFIG_SND_SOC_WM8904 is not set -+# CONFIG_SND_SOC_WM8960 is not set -+# CONFIG_SND_SOC_WM8962 is not set -+# CONFIG_SND_SOC_WM8974 is not set -+# CONFIG_SND_SOC_WM8978 is not set -+# CONFIG_SND_SOC_WM8985 is not set -+# CONFIG_SND_SOC_ZL38060 is not set -+# CONFIG_SND_SOC_ZX_AUD96P22 is not set -+# CONFIG_SND_SOC_MAX9759 is not set -+# CONFIG_SND_SOC_MT6351 is not set -+# CONFIG_SND_SOC_MT6358 is not set -+# CONFIG_SND_SOC_MT6660 is not set -+# CONFIG_SND_SOC_NAU8540 is not set -+# CONFIG_SND_SOC_NAU8810 is not set -+# CONFIG_SND_SOC_NAU8822 is not set -+# CONFIG_SND_SOC_NAU8824 is not set -+# CONFIG_SND_SOC_TPA6130A2 is not set -+# end of CODEC drivers -+ -+CONFIG_SND_SIMPLE_CARD_UTILS=y -+CONFIG_SND_SIMPLE_CARD=y -+# CONFIG_SND_AUDIO_GRAPH_CARD is not set -+ -+# -+# HID support -+# -+CONFIG_HID=y -+CONFIG_HID_BATTERY_STRENGTH=y -+CONFIG_HIDRAW=y -+CONFIG_UHID=y -+CONFIG_HID_GENERIC=y -+ -+# -+# Special HID drivers -+# -+# CONFIG_HID_A4TECH is not set -+# CONFIG_HID_ACCUTOUCH is not set -+# CONFIG_HID_ACRUX is not set -+# CONFIG_HID_APPLE is not set -+# CONFIG_HID_APPLEIR is not set -+# CONFIG_HID_ASUS is not set -+# CONFIG_HID_AUREAL is not set -+# CONFIG_HID_BELKIN is not set -+# CONFIG_HID_BETOP_FF is not set -+# CONFIG_HID_BIGBEN_FF is not set -+# CONFIG_HID_CHERRY is not set -+# CONFIG_HID_CHICONY is not set -+# CONFIG_HID_CORSAIR is not set -+# CONFIG_HID_COUGAR is not set -+# CONFIG_HID_MACALLY is not set -+# CONFIG_HID_PRODIKEYS is not set -+# CONFIG_HID_CMEDIA is not set -+# CONFIG_HID_CP2112 is not set -+# CONFIG_HID_CREATIVE_SB0540 is not set -+# CONFIG_HID_CYPRESS is not set -+# CONFIG_HID_DRAGONRISE is not set -+# CONFIG_HID_EMS_FF is not set -+# CONFIG_HID_ELAN is not set -+# CONFIG_HID_ELECOM is not set -+# CONFIG_HID_ELO is not set -+# CONFIG_HID_EZKEY is not set -+# CONFIG_HID_GEMBIRD is not set -+# CONFIG_HID_GFRM is not set -+# CONFIG_HID_GLORIOUS is not set -+# CONFIG_HID_HOLTEK is not set -+# CONFIG_HID_VIVALDI is not set -+# CONFIG_HID_GT683R is not set -+# CONFIG_HID_KEYTOUCH is not set -+# CONFIG_HID_KYE is not set -+# CONFIG_HID_UCLOGIC is not set -+# CONFIG_HID_WALTOP is not set -+# CONFIG_HID_VIEWSONIC is not set -+# CONFIG_HID_GYRATION is not set -+# CONFIG_HID_ICADE is not set -+# CONFIG_HID_ITE is not set -+# CONFIG_HID_JABRA is not set -+# CONFIG_HID_TWINHAN is not set -+CONFIG_HID_KENSINGTON=y -+# CONFIG_HID_LCPOWER is not set -+# CONFIG_HID_LED is not set -+# CONFIG_HID_LENOVO is not set -+# CONFIG_HID_LOGITECH is not set -+# CONFIG_HID_MAGICMOUSE is not set -+# CONFIG_HID_MALTRON is not set -+# CONFIG_HID_MAYFLASH is not set -+# CONFIG_HID_REDRAGON is not set -+# CONFIG_HID_MICROSOFT is not set -+# CONFIG_HID_MONTEREY is not set -+CONFIG_HID_MULTITOUCH=y -+# CONFIG_HID_NTI is not set -+# CONFIG_HID_NTRIG is not set -+# CONFIG_HID_ORTEK is not set -+# CONFIG_HID_PANTHERLORD is not set -+# CONFIG_HID_PENMOUNT is not set -+# CONFIG_HID_PETALYNX is not set -+# CONFIG_HID_PICOLCD is not set -+# CONFIG_HID_PLANTRONICS is not set -+# CONFIG_HID_PRIMAX is not set -+# CONFIG_HID_RETRODE is not set -+# CONFIG_HID_ROCCAT is not set -+# CONFIG_HID_SAITEK is not set -+# CONFIG_HID_SAMSUNG is not set -+# CONFIG_HID_SONY is not set -+# CONFIG_HID_SPEEDLINK is not set -+# CONFIG_HID_STEAM is not set -+# CONFIG_HID_STEELSERIES is not set -+# CONFIG_HID_SUNPLUS is not set -+# CONFIG_HID_RMI is not set -+# CONFIG_HID_GREENASIA is not set -+# CONFIG_HID_SMARTJOYPLUS is not set -+# CONFIG_HID_TIVO is not set -+# CONFIG_HID_TOPSEED is not set -+# CONFIG_HID_THINGM is not set -+# CONFIG_HID_THRUSTMASTER is not set -+# CONFIG_HID_UDRAW_PS3 is not set -+# CONFIG_HID_U2FZERO is not set -+CONFIG_HID_WACOM=y -+# CONFIG_HID_WIIMOTE is not set -+# CONFIG_HID_XINMO is not set -+# CONFIG_HID_ZEROPLUS is not set -+# CONFIG_HID_ZYDACRON is not set -+# CONFIG_HID_SENSOR_HUB is not set -+# CONFIG_HID_ALPS is not set -+# CONFIG_HID_MCP2221 is not set -+# end of Special HID drivers -+ -+# -+# USB HID support -+# -+CONFIG_USB_HID=y -+# CONFIG_HID_PID is not set -+CONFIG_USB_HIDDEV=y -+# end of USB HID support -+ -+# -+# I2C HID support -+# -+CONFIG_I2C_HID=y -+# end of I2C HID support -+# end of HID support -+ -+CONFIG_USB_OHCI_LITTLE_ENDIAN=y -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_COMMON=y -+# CONFIG_USB_ULPI_BUS is not set -+# CONFIG_USB_CONN_GPIO is not set -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB=y -+CONFIG_USB_PCI=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+ -+# -+# Miscellaneous USB options -+# -+# CONFIG_USB_DEFAULT_PERSIST is not set -+# CONFIG_USB_FEW_INIT_RETRIES is not set -+# CONFIG_USB_DYNAMIC_MINORS is not set -+CONFIG_USB_OTG=y -+# CONFIG_USB_OTG_PRODUCTLIST is not set -+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -+# CONFIG_USB_OTG_FSM is not set -+CONFIG_USB_AUTOSUSPEND_DELAY=2 -+CONFIG_USB_MON=y -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+CONFIG_USB_XHCI_HCD=y -+# CONFIG_USB_XHCI_DBGCAP is not set -+CONFIG_USB_XHCI_PCI=y -+# CONFIG_USB_XHCI_PCI_RENESAS is not set -+CONFIG_USB_XHCI_PLATFORM=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+CONFIG_USB_EHCI_PCI=y -+# CONFIG_USB_EHCI_FSL is not set -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+# CONFIG_USB_OXU210HP_HCD is not set -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_FOTG210_HCD is not set -+# CONFIG_USB_MAX3421_HCD is not set -+CONFIG_USB_OHCI_HCD=y -+# CONFIG_USB_OHCI_HCD_PCI is not set -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_HCD_TEST_MODE is not set -+ -+# -+# USB Device Class drivers -+# -+# CONFIG_USB_ACM is not set -+# CONFIG_USB_PRINTER is not set -+# CONFIG_USB_WDM is not set -+# CONFIG_USB_TMC is not set -+ -+# -+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -+# -+ -+# -+# also be needed; see USB_STORAGE Help for more info -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+# CONFIG_USB_STORAGE_REALTEK is not set -+# CONFIG_USB_STORAGE_DATAFAB is not set -+# CONFIG_USB_STORAGE_FREECOM is not set -+# CONFIG_USB_STORAGE_ISD200 is not set -+# CONFIG_USB_STORAGE_USBAT is not set -+# CONFIG_USB_STORAGE_SDDR09 is not set -+# CONFIG_USB_STORAGE_SDDR55 is not set -+# CONFIG_USB_STORAGE_JUMPSHOT is not set -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -+# CONFIG_USB_STORAGE_ENE_UB6250 is not set -+CONFIG_USB_UAS=y -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+# CONFIG_USBIP_CORE is not set -+# CONFIG_USB_CDNS3 is not set -+# CONFIG_USB_MUSB_HDRC is not set -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_HOST is not set -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_DWC3_DUAL_ROLE=y -+ -+# -+# Platform Glue Driver Support -+# -+CONFIG_USB_DWC3_HAPS=y -+CONFIG_USB_DWC3_OF_SIMPLE=y -+CONFIG_USB_DWC2=y -+# CONFIG_USB_DWC2_HOST is not set -+ -+# -+# Gadget/Dual-role mode requires USB Gadget support to be enabled -+# -+# CONFIG_USB_DWC2_PERIPHERAL is not set -+CONFIG_USB_DWC2_DUAL_ROLE=y -+# CONFIG_USB_DWC2_PCI is not set -+# CONFIG_USB_DWC2_DEBUG is not set -+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -+# CONFIG_USB_CHIPIDEA is not set -+# CONFIG_USB_ISP1760 is not set -+ -+# -+# USB port drivers -+# -+CONFIG_USB_SERIAL=y -+# CONFIG_USB_SERIAL_CONSOLE is not set -+CONFIG_USB_SERIAL_GENERIC=y -+# CONFIG_USB_SERIAL_SIMPLE is not set -+# CONFIG_USB_SERIAL_AIRCABLE is not set -+# CONFIG_USB_SERIAL_ARK3116 is not set -+# CONFIG_USB_SERIAL_BELKIN is not set -+# CONFIG_USB_SERIAL_CH341 is not set -+# CONFIG_USB_SERIAL_WHITEHEAT is not set -+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -+CONFIG_USB_SERIAL_CP210X=y -+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -+# CONFIG_USB_SERIAL_EMPEG is not set -+CONFIG_USB_SERIAL_FTDI_SIO=y -+# CONFIG_USB_SERIAL_VISOR is not set -+# CONFIG_USB_SERIAL_IPAQ is not set -+# CONFIG_USB_SERIAL_IR is not set -+# CONFIG_USB_SERIAL_EDGEPORT is not set -+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -+# CONFIG_USB_SERIAL_F81232 is not set -+# CONFIG_USB_SERIAL_F8153X is not set -+# CONFIG_USB_SERIAL_GARMIN is not set -+# CONFIG_USB_SERIAL_IPW is not set -+# CONFIG_USB_SERIAL_IUU is not set -+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -+CONFIG_USB_SERIAL_KEYSPAN=y -+# CONFIG_USB_SERIAL_KLSI is not set -+# CONFIG_USB_SERIAL_KOBIL_SCT is not set -+# CONFIG_USB_SERIAL_MCT_U232 is not set -+# CONFIG_USB_SERIAL_METRO is not set -+# CONFIG_USB_SERIAL_MOS7720 is not set -+# CONFIG_USB_SERIAL_MOS7840 is not set -+# CONFIG_USB_SERIAL_MXUPORT is not set -+# CONFIG_USB_SERIAL_NAVMAN is not set -+CONFIG_USB_SERIAL_PL2303=y -+CONFIG_USB_SERIAL_OTI6858=y -+# CONFIG_USB_SERIAL_QCAUX is not set -+CONFIG_USB_SERIAL_QUALCOMM=y -+# CONFIG_USB_SERIAL_SPCP8X5 is not set -+# CONFIG_USB_SERIAL_SAFE is not set -+CONFIG_USB_SERIAL_SIERRAWIRELESS=y -+# CONFIG_USB_SERIAL_SYMBOL is not set -+# CONFIG_USB_SERIAL_TI is not set -+# CONFIG_USB_SERIAL_CYBERJACK is not set -+# CONFIG_USB_SERIAL_XIRCOM is not set -+CONFIG_USB_SERIAL_WWAN=y -+CONFIG_USB_SERIAL_OPTION=y -+# CONFIG_USB_SERIAL_OMNINET is not set -+# CONFIG_USB_SERIAL_OPTICON is not set -+# CONFIG_USB_SERIAL_XSENS_MT is not set -+# CONFIG_USB_SERIAL_WISHBONE is not set -+# CONFIG_USB_SERIAL_SSU100 is not set -+# CONFIG_USB_SERIAL_QT2 is not set -+# CONFIG_USB_SERIAL_UPD78F0730 is not set -+# CONFIG_USB_SERIAL_DEBUG is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_SEVSEG is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_APPLE_MFI_FASTCHARGE is not set -+# CONFIG_USB_SISUSBVGA is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+# CONFIG_USB_EHSET_TEST_FIXTURE is not set -+# CONFIG_USB_ISIGHTFW is not set -+# CONFIG_USB_YUREX is not set -+CONFIG_USB_EZUSB_FX2=y -+# CONFIG_USB_HUB_USB251XB is not set -+# CONFIG_USB_HSIC_USB3503 is not set -+# CONFIG_USB_HSIC_USB4604 is not set -+# CONFIG_USB_LINK_LAYER_TEST is not set -+# CONFIG_USB_CHAOSKEY is not set -+ -+# -+# USB Physical Layer drivers -+# -+CONFIG_USB_PHY=y -+# CONFIG_NOP_USB_XCEIV is not set -+# CONFIG_USB_GPIO_VBUS is not set -+# CONFIG_USB_ISP1301 is not set -+# CONFIG_USB_ULPI is not set -+# end of USB Physical Layer drivers -+ -+CONFIG_USB_GADGET=y -+# CONFIG_USB_GADGET_DEBUG is not set -+CONFIG_USB_GADGET_DEBUG_FILES=y -+# CONFIG_USB_GADGET_DEBUG_FS is not set -+CONFIG_USB_GADGET_VBUS_DRAW=500 -+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 -+# CONFIG_U_SERIAL_CONSOLE is not set -+ -+# -+# USB Peripheral Controller -+# -+# CONFIG_USB_FOTG210_UDC is not set -+# CONFIG_USB_GR_UDC is not set -+# CONFIG_USB_R8A66597 is not set -+# CONFIG_USB_PXA27X is not set -+# CONFIG_USB_MV_UDC is not set -+# CONFIG_USB_MV_U3D is not set -+# CONFIG_USB_SNP_UDC_PLAT is not set -+# CONFIG_USB_M66592 is not set -+# CONFIG_USB_BDC_UDC is not set -+# CONFIG_USB_AMD5536UDC is not set -+# CONFIG_USB_NET2272 is not set -+# CONFIG_USB_NET2280 is not set -+# CONFIG_USB_GOKU is not set -+# CONFIG_USB_EG20T is not set -+# CONFIG_USB_GADGET_XILINX is not set -+# CONFIG_USB_MAX3420_UDC is not set -+# CONFIG_USB_DUMMY_HCD is not set -+# end of USB Peripheral Controller -+ -+CONFIG_USB_LIBCOMPOSITE=y -+CONFIG_USB_F_ACM=y -+CONFIG_USB_U_SERIAL=y -+CONFIG_USB_F_MASS_STORAGE=y -+CONFIG_USB_F_FS=y -+CONFIG_USB_F_UVC=y -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_UEVENT=y -+# CONFIG_USB_CONFIGFS_SERIAL is not set -+CONFIG_USB_CONFIGFS_ACM=y -+# CONFIG_USB_CONFIGFS_OBEX is not set -+# CONFIG_USB_CONFIGFS_NCM is not set -+# CONFIG_USB_CONFIGFS_ECM is not set -+# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set -+# CONFIG_USB_CONFIGFS_RNDIS is not set -+# CONFIG_USB_CONFIGFS_EEM is not set -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+# CONFIG_USB_CONFIGFS_F_LB_SS is not set -+CONFIG_USB_CONFIGFS_F_FS=y -+# CONFIG_USB_CONFIGFS_F_ACC is not set -+# CONFIG_USB_CONFIGFS_F_AUDIO_SRC is not set -+# CONFIG_USB_CONFIGFS_F_UAC1 is not set -+# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set -+# CONFIG_USB_CONFIGFS_F_UAC2 is not set -+# CONFIG_USB_CONFIGFS_F_MIDI is not set -+# CONFIG_USB_CONFIGFS_F_HID is not set -+CONFIG_USB_CONFIGFS_F_UVC=y -+# CONFIG_USB_CONFIGFS_F_PRINTER is not set -+ -+# -+# USB Gadget precomposed configurations -+# -+# CONFIG_USB_ZERO is not set -+# CONFIG_USB_AUDIO is not set -+# CONFIG_USB_ETH is not set -+# CONFIG_USB_G_NCM is not set -+# CONFIG_USB_GADGETFS is not set -+# CONFIG_USB_FUNCTIONFS is not set -+# CONFIG_USB_MASS_STORAGE is not set -+# CONFIG_USB_G_SERIAL is not set -+# CONFIG_USB_MIDI_GADGET is not set -+# CONFIG_USB_G_PRINTER is not set -+# CONFIG_USB_CDC_COMPOSITE is not set -+# CONFIG_USB_G_ACM_MS is not set -+# CONFIG_USB_G_MULTI is not set -+# CONFIG_USB_G_HID is not set -+# CONFIG_USB_G_DBGP is not set -+# CONFIG_USB_G_WEBCAM is not set -+# CONFIG_USB_RAW_GADGET is not set -+# end of USB Gadget precomposed configurations -+ -+# CONFIG_TYPEC is not set -+CONFIG_USB_ROLE_SWITCH=y -+CONFIG_MMC=y -+CONFIG_PWRSEQ_EMMC=y -+# CONFIG_PWRSEQ_SD8787 is not set -+CONFIG_PWRSEQ_SIMPLE=y -+CONFIG_MMC_BLOCK=y -+CONFIG_MMC_BLOCK_MINORS=32 -+# CONFIG_SDIO_UART is not set -+CONFIG_MMC_TEST=y -+ -+# -+# MMC/SD/SDIO Host Controller Drivers -+# -+# CONFIG_MMC_DEBUG is not set -+# CONFIG_MMC_ARMMMCI is not set -+CONFIG_MMC_SDHCI=y -+# CONFIG_MMC_SDHCI_PCI is not set -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=y -+# CONFIG_MMC_SDHCI_OF_ASPEED is not set -+# CONFIG_MMC_SDHCI_OF_AT91 is not set -+CONFIG_MMC_SDHCI_OF_DWCMSHC=y -+# CONFIG_MMC_SDHCI_CADENCE is not set -+# CONFIG_MMC_SDHCI_F_SDH30 is not set -+# CONFIG_MMC_SDHCI_MILBEAUT is not set -+# CONFIG_MMC_TIFM_SD is not set -+# CONFIG_MMC_SPI is not set -+# CONFIG_MMC_CB710 is not set -+# CONFIG_MMC_VIA_SDMMC is not set -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_PLTFM=y -+# CONFIG_MMC_DW_BLUEFIELD is not set -+# CONFIG_MMC_DW_EXYNOS is not set -+# CONFIG_MMC_DW_HI3798CV200 is not set -+# CONFIG_MMC_DW_K3 is not set -+# CONFIG_MMC_DW_PCI is not set -+CONFIG_MMC_DW_ROCKCHIP=y -+# CONFIG_MMC_VUB300 is not set -+# CONFIG_MMC_USHC is not set -+# CONFIG_MMC_USDHI6ROL0 is not set -+CONFIG_MMC_CQHCI=y -+# CONFIG_MMC_HSQ is not set -+# CONFIG_MMC_TOSHIBA_PCI is not set -+# CONFIG_MMC_MTK is not set -+# CONFIG_MMC_SDHCI_XENON is not set -+# CONFIG_MMC_SDHCI_OMAP is not set -+# CONFIG_MMC_SDHCI_AM654 is not set -+# CONFIG_MEMSTICK is not set -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+# CONFIG_LEDS_CLASS_FLASH is not set -+# CONFIG_LEDS_CLASS_MULTICOLOR is not set -+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -+ -+# -+# LED drivers -+# -+# CONFIG_LEDS_AN30259A is not set -+# CONFIG_LEDS_AW2013 is not set -+# CONFIG_LEDS_BCM6328 is not set -+# CONFIG_LEDS_BCM6358 is not set -+# CONFIG_LEDS_CR0014114 is not set -+# CONFIG_LEDS_EL15203000 is not set -+# CONFIG_LEDS_LM3530 is not set -+# CONFIG_LEDS_LM3532 is not set -+# CONFIG_LEDS_LM3642 is not set -+# CONFIG_LEDS_LM3692X is not set -+# CONFIG_LEDS_PCA9532 is not set -+CONFIG_LEDS_GPIO=y -+# CONFIG_LEDS_LP3944 is not set -+# CONFIG_LEDS_LP3952 is not set -+# CONFIG_LEDS_LP50XX is not set -+# CONFIG_LEDS_LP55XX_COMMON is not set -+# CONFIG_LEDS_LP8860 is not set -+# CONFIG_LEDS_PCA955X is not set -+# CONFIG_LEDS_PCA963X is not set -+# CONFIG_LEDS_DAC124S085 is not set -+# CONFIG_LEDS_PWM is not set -+# CONFIG_LEDS_REGULATOR is not set -+# CONFIG_LEDS_BD2802 is not set -+# CONFIG_LEDS_LT3593 is not set -+# CONFIG_LEDS_TCA6507 is not set -+# CONFIG_LEDS_TLC591XX is not set -+# CONFIG_LEDS_LM355x is not set -+# CONFIG_LEDS_IS31FL319X is not set -+CONFIG_LEDS_IS31FL32XX=y -+ -+# -+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -+# -+# CONFIG_LEDS_BLINKM is not set -+# CONFIG_LEDS_SYSCON is not set -+# CONFIG_LEDS_MLXREG is not set -+# CONFIG_LEDS_USER is not set -+# CONFIG_LEDS_SPI_BYTE is not set -+# CONFIG_LEDS_TI_LMU_COMMON is not set -+ -+# -+# LED Triggers -+# -+# CONFIG_LEDS_TRIGGERS is not set -+# CONFIG_ACCESSIBILITY is not set -+# CONFIG_INFINIBAND is not set -+CONFIG_EDAC_SUPPORT=y -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_HCTOSYS=y -+CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -+CONFIG_RTC_SYSTOHC=y -+CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -+# CONFIG_RTC_DEBUG is not set -+CONFIG_RTC_NVMEM=y -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_ABB5ZES3 is not set -+# CONFIG_RTC_DRV_ABEOZ9 is not set -+# CONFIG_RTC_DRV_ABX80X is not set -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1374 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+CONFIG_RTC_DRV_HYM8563=y -+# CONFIG_RTC_DRV_MAX6900 is not set -+CONFIG_RTC_DRV_RK808=y -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_ISL12022 is not set -+# CONFIG_RTC_DRV_ISL12026 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8523 is not set -+# CONFIG_RTC_DRV_PCF85063 is not set -+# CONFIG_RTC_DRV_PCF85363 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+# CONFIG_RTC_DRV_M41T80 is not set -+# CONFIG_RTC_DRV_BQ32K is not set -+# CONFIG_RTC_DRV_TPS6586X is not set -+# CONFIG_RTC_DRV_S35390A is not set -+# CONFIG_RTC_DRV_FM3130 is not set -+# CONFIG_RTC_DRV_RX8010 is not set -+# CONFIG_RTC_DRV_RX8581 is not set -+# CONFIG_RTC_DRV_RX8025 is not set -+# CONFIG_RTC_DRV_EM3027 is not set -+# CONFIG_RTC_DRV_RV3028 is not set -+# CONFIG_RTC_DRV_RV3032 is not set -+# CONFIG_RTC_DRV_RV8803 is not set -+# CONFIG_RTC_DRV_SD3078 is not set -+ -+# -+# SPI RTC drivers -+# -+# CONFIG_RTC_DRV_M41T93 is not set -+# CONFIG_RTC_DRV_M41T94 is not set -+# CONFIG_RTC_DRV_DS1302 is not set -+# CONFIG_RTC_DRV_DS1305 is not set -+# CONFIG_RTC_DRV_DS1343 is not set -+# CONFIG_RTC_DRV_DS1347 is not set -+# CONFIG_RTC_DRV_DS1390 is not set -+# CONFIG_RTC_DRV_MAX6916 is not set -+# CONFIG_RTC_DRV_R9701 is not set -+# CONFIG_RTC_DRV_RX4581 is not set -+# CONFIG_RTC_DRV_RX6110 is not set -+# CONFIG_RTC_DRV_RS5C348 is not set -+# CONFIG_RTC_DRV_MAX6902 is not set -+# CONFIG_RTC_DRV_PCF2123 is not set -+# CONFIG_RTC_DRV_MCP795 is not set -+CONFIG_RTC_I2C_AND_SPI=y -+ -+# -+# SPI and I2C RTC drivers -+# -+# CONFIG_RTC_DRV_DS3232 is not set -+# CONFIG_RTC_DRV_PCF2127 is not set -+# CONFIG_RTC_DRV_RV3029C2 is not set -+ -+# -+# Platform RTC drivers -+# -+# CONFIG_RTC_DRV_DS1286 is not set -+# CONFIG_RTC_DRV_DS1511 is not set -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1685_FAMILY is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_DS2404 is not set -+# CONFIG_RTC_DRV_STK17TA8 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T35 is not set -+# CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_MSM6242 is not set -+# CONFIG_RTC_DRV_BQ4802 is not set -+# CONFIG_RTC_DRV_RP5C01 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+# CONFIG_RTC_DRV_ZYNQMP is not set -+ -+# -+# on-CPU RTC drivers -+# -+# CONFIG_RTC_DRV_PL030 is not set -+# CONFIG_RTC_DRV_PL031 is not set -+# CONFIG_RTC_DRV_CADENCE is not set -+# CONFIG_RTC_DRV_FTRTC010 is not set -+# CONFIG_RTC_DRV_R7301 is not set -+ -+# -+# HID Sensor RTC drivers -+# -+CONFIG_DMADEVICES=y -+# CONFIG_DMADEVICES_DEBUG is not set -+ -+# -+# DMA Devices -+# -+CONFIG_DMA_ENGINE=y -+CONFIG_DMA_OF=y -+# CONFIG_ALTERA_MSGDMA is not set -+# CONFIG_AMBA_PL08X is not set -+# CONFIG_DW_AXI_DMAC is not set -+# CONFIG_FSL_EDMA is not set -+# CONFIG_FSL_QDMA is not set -+# CONFIG_HISI_DMA is not set -+# CONFIG_INTEL_IDMA64 is not set -+# CONFIG_MV_XOR_V2 is not set -+CONFIG_PL330_DMA=y -+# CONFIG_PLX_DMA is not set -+# CONFIG_XILINX_DMA is not set -+# CONFIG_XILINX_ZYNQMP_DMA is not set -+# CONFIG_XILINX_ZYNQMP_DPDMA is not set -+# CONFIG_QCOM_HIDMA_MGMT is not set -+# CONFIG_QCOM_HIDMA is not set -+# CONFIG_DW_DMAC is not set -+# CONFIG_DW_DMAC_PCI is not set -+# CONFIG_DW_EDMA is not set -+# CONFIG_DW_EDMA_PCIE is not set -+# CONFIG_SF_PDMA is not set -+ -+# -+# DMA Clients -+# -+# CONFIG_ASYNC_TX_DMA is not set -+# CONFIG_DMATEST is not set -+ -+# -+# DMABUF options -+# -+CONFIG_SYNC_FILE=y -+CONFIG_SW_SYNC=y -+# CONFIG_UDMABUF is not set -+# CONFIG_DMABUF_MOVE_NOTIFY is not set -+# CONFIG_DMABUF_SELFTESTS is not set -+CONFIG_DMABUF_HEAPS=y -+CONFIG_DMABUF_SYSFS_STATS=y -+CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y -+CONFIG_DMABUF_HEAPS_PAGE_POOL=y -+CONFIG_DMABUF_HEAPS_SYSTEM=y -+CONFIG_DMABUF_HEAPS_CMA=y -+# end of DMABUF options -+ -+# CONFIG_AUXDISPLAY is not set -+# CONFIG_UIO is not set -+# CONFIG_VFIO is not set -+# CONFIG_VIRT_DRIVERS is not set -+CONFIG_VIRTIO_MENU=y -+# CONFIG_VIRTIO_PCI is not set -+# CONFIG_VIRTIO_MMIO is not set -+# CONFIG_VDPA is not set -+CONFIG_VHOST_MENU=y -+# CONFIG_VHOST_NET is not set -+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set -+ -+# -+# Microsoft Hyper-V guest support -+# -+# end of Microsoft Hyper-V guest support -+ -+# CONFIG_GREYBUS is not set -+CONFIG_STAGING=y -+# CONFIG_PRISM2_USB is not set -+# CONFIG_COMEDI is not set -+# CONFIG_RTL8192U is not set -+# CONFIG_RTLLIB is not set -+# CONFIG_RTL8723BS is not set -+# CONFIG_R8712U is not set -+# CONFIG_R8188EU is not set -+# CONFIG_RTS5208 is not set -+# CONFIG_VT6655 is not set -+# CONFIG_VT6656 is not set -+ -+# -+# IIO staging drivers -+# -+ -+# -+# Accelerometers -+# -+# CONFIG_ADIS16203 is not set -+# CONFIG_ADIS16240 is not set -+# end of Accelerometers -+ -+# -+# Analog to digital converters -+# -+# CONFIG_AD7816 is not set -+# CONFIG_AD7280 is not set -+# end of Analog to digital converters -+ -+# -+# Analog digital bi-direction converters -+# -+# CONFIG_ADT7316 is not set -+# end of Analog digital bi-direction converters -+ -+# -+# Capacitance to digital converters -+# -+# CONFIG_AD7150 is not set -+# CONFIG_AD7746 is not set -+# end of Capacitance to digital converters -+ -+# -+# Direct Digital Synthesis -+# -+# CONFIG_AD9832 is not set -+# CONFIG_AD9834 is not set -+# end of Direct Digital Synthesis -+ -+# -+# Network Analyzer, Impedance Converters -+# -+# CONFIG_AD5933 is not set -+# end of Network Analyzer, Impedance Converters -+ -+# -+# Active energy metering IC -+# -+# CONFIG_ADE7854 is not set -+# end of Active energy metering IC -+ -+# -+# Resolver to digital converters -+# -+# CONFIG_AD2S1210 is not set -+# end of Resolver to digital converters -+# end of IIO staging drivers -+ -+# CONFIG_FB_SM750 is not set -+# CONFIG_STAGING_MEDIA is not set -+ -+# -+# Android -+# -+CONFIG_ASHMEM=y -+# CONFIG_ION is not set -+CONFIG_FIQ_DEBUGGER=y -+CONFIG_FIQ_DEBUGGER_NO_SLEEP=y -+# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set -+CONFIG_FIQ_DEBUGGER_CONSOLE=y -+CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y -+CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y -+# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set -+CONFIG_RK_CONSOLE_THREAD=y -+# end of Android -+ -+# CONFIG_STAGING_BOARD is not set -+# CONFIG_LTE_GDM724X is not set -+# CONFIG_GS_FPGABOOT is not set -+# CONFIG_UNISYSSPAR is not set -+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set -+# CONFIG_FB_TFT is not set -+# CONFIG_KS7010 is not set -+# CONFIG_PI433 is not set -+ -+# -+# Gasket devices -+# -+# CONFIG_STAGING_GASKET_FRAMEWORK is not set -+# end of Gasket devices -+ -+# CONFIG_XIL_AXIS_FIFO is not set -+# CONFIG_FIELDBUS_DEV is not set -+# CONFIG_QLGE is not set -+# CONFIG_WFX is not set -+# CONFIG_HILOG is not set -+CONFIG_HIEVENT=y -+CONFIG_DFX_ZEROHUNG=y -+CONFIG_DFX_HUNGTASK=y -+CONFIG_DFX_HUNGTASK_USER=y -+# CONFIG_GOLDFISH is not set -+# CONFIG_CHROME_PLATFORMS is not set -+# CONFIG_MELLANOX_PLATFORM is not set -+CONFIG_HAVE_CLK=y -+CONFIG_CLKDEV_LOOKUP=y -+CONFIG_HAVE_CLK_PREPARE=y -+CONFIG_COMMON_CLK=y -+# CONFIG_COMMON_CLK_PROCFS is not set -+# CONFIG_COMMON_CLK_MAX9485 is not set -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCMI=y -+# CONFIG_COMMON_CLK_SI5341 is not set -+# CONFIG_COMMON_CLK_SI5351 is not set -+# CONFIG_COMMON_CLK_SI514 is not set -+# CONFIG_COMMON_CLK_SI544 is not set -+# CONFIG_COMMON_CLK_SI570 is not set -+# CONFIG_COMMON_CLK_CDCE706 is not set -+# CONFIG_COMMON_CLK_CDCE925 is not set -+# CONFIG_COMMON_CLK_CS2000_CP is not set -+# CONFIG_CLK_QORIQ is not set -+# CONFIG_COMMON_CLK_XGENE is not set -+CONFIG_COMMON_CLK_PWM=y -+# CONFIG_COMMON_CLK_VC5 is not set -+# CONFIG_COMMON_CLK_FIXED_MMIO is not set -+CONFIG_COMMON_CLK_ROCKCHIP=y -+CONFIG_CLK_PX30=y -+CONFIG_CLK_RK1808=y -+CONFIG_CLK_RK3308=y -+CONFIG_CLK_RK3328=y -+CONFIG_CLK_RK3368=y -+CONFIG_CLK_RK3399=y -+CONFIG_CLK_RK3568=y -+# CONFIG_ROCKCHIP_CLK_COMPENSATION is not set -+# CONFIG_HWSPINLOCK is not set -+ -+# -+# Clock Source drivers -+# -+CONFIG_TIMER_OF=y -+CONFIG_TIMER_PROBE=y -+CONFIG_CLKSRC_MMIO=y -+CONFIG_ROCKCHIP_TIMER=y -+CONFIG_ARM_ARCH_TIMER=y -+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -+CONFIG_FSL_ERRATUM_A008585=y -+CONFIG_HISILICON_ERRATUM_161010101=y -+CONFIG_ARM64_ERRATUM_858921=y -+# CONFIG_MICROCHIP_PIT64B is not set -+# end of Clock Source drivers -+ -+CONFIG_MAILBOX=y -+# CONFIG_ARM_MHU is not set -+# CONFIG_PLATFORM_MHU is not set -+# CONFIG_PL320_MBOX is not set -+# CONFIG_ROCKCHIP_MBOX is not set -+# CONFIG_ALTERA_MBOX is not set -+# CONFIG_MAILBOX_TEST is not set -+CONFIG_IOMMU_IOVA=y -+CONFIG_IOMMU_API=y -+CONFIG_IOMMU_SUPPORT=y -+ -+# -+# Generic IOMMU Pagetable Support -+# -+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -+# end of Generic IOMMU Pagetable Support -+ -+# CONFIG_IOMMU_DEBUGFS is not set -+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -+CONFIG_OF_IOMMU=y -+CONFIG_IOMMU_DMA=y -+CONFIG_ROCKCHIP_IOMMU=y -+# CONFIG_ARM_SMMU is not set -+# CONFIG_ARM_SMMU_V3 is not set -+ -+# -+# Remoteproc drivers -+# -+# CONFIG_REMOTEPROC is not set -+# end of Remoteproc drivers -+ -+# -+# Rpmsg drivers -+# -+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set -+# CONFIG_RPMSG_VIRTIO is not set -+# end of Rpmsg drivers -+ -+# CONFIG_SOUNDWIRE is not set -+ -+# -+# SOC (System On Chip) specific Drivers -+# -+ -+# -+# Amlogic SoC drivers -+# -+# end of Amlogic SoC drivers -+ -+# -+# Aspeed SoC drivers -+# -+# end of Aspeed SoC drivers -+ -+# -+# Broadcom SoC drivers -+# -+# CONFIG_SOC_BRCMSTB is not set -+# end of Broadcom SoC drivers -+ -+# -+# NXP/Freescale QorIQ SoC drivers -+# -+# CONFIG_QUICC_ENGINE is not set -+# CONFIG_FSL_RCPM is not set -+# end of NXP/Freescale QorIQ SoC drivers -+ -+# -+# i.MX SoC drivers -+# -+# end of i.MX SoC drivers -+ -+# -+# Qualcomm SoC drivers -+# -+# end of Qualcomm SoC drivers -+ -+# -+# Rockchip CPU selection -+# -+CONFIG_CPU_PX30=y -+CONFIG_CPU_RK1808=y -+# CONFIG_CPU_RK3308 is not set -+CONFIG_CPU_RK3328=y -+# CONFIG_CPU_RK3368 is not set -+CONFIG_CPU_RK3399=y -+CONFIG_CPU_RK3568=y -+# CONFIG_CPU_RK3588 is not set -+# end of Rockchip CPU selection -+ -+CONFIG_NO_GKI=y -+CONFIG_ROCKCHIP_CPUINFO=y -+CONFIG_ROCKCHIP_GRF=y -+# CONFIG_ROCKCHIP_HW_DECOMPRESS is not set -+CONFIG_ROCKCHIP_IODOMAIN=y -+CONFIG_ROCKCHIP_IPA=y -+CONFIG_ROCKCHIP_OPP=y -+CONFIG_ROCKCHIP_PM_DOMAINS=y -+CONFIG_ROCKCHIP_PVTM=y -+# CONFIG_ROCKCHIP_SUSPEND_MODE is not set -+CONFIG_ROCKCHIP_SYSTEM_MONITOR=y -+CONFIG_ROCKCHIP_VENDOR_STORAGE=y -+CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y -+CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y -+CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y -+CONFIG_ROCKCHIP_FIQ_DEBUGGER=y -+CONFIG_ROCKCHIP_DEBUG=y -+# CONFIG_ROCKCHIP_THUNDER_BOOT is not set -+# CONFIG_SOC_TI is not set -+ -+# -+# Xilinx SoC drivers -+# -+# CONFIG_XILINX_VCU is not set -+# end of Xilinx SoC drivers -+# end of SOC (System On Chip) specific Drivers -+ -+CONFIG_PM_DEVFREQ=y -+ -+# -+# DEVFREQ Governors -+# -+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -+CONFIG_DEVFREQ_GOV_PERFORMANCE=y -+CONFIG_DEVFREQ_GOV_POWERSAVE=y -+CONFIG_DEVFREQ_GOV_USERSPACE=y -+# CONFIG_DEVFREQ_GOV_PASSIVE is not set -+ -+# -+# DEVFREQ Drivers -+# -+CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y -+CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y -+CONFIG_PM_DEVFREQ_EVENT=y -+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y -+CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y -+CONFIG_EXTCON=y -+ -+# -+# Extcon Device Drivers -+# -+# CONFIG_EXTCON_ADC_JACK is not set -+# CONFIG_EXTCON_FSA9480 is not set -+# CONFIG_EXTCON_GPIO is not set -+# CONFIG_EXTCON_MAX3355 is not set -+# CONFIG_EXTCON_PTN5150 is not set -+# CONFIG_EXTCON_RT8973A is not set -+# CONFIG_EXTCON_SM5502 is not set -+# CONFIG_EXTCON_USB_GPIO is not set -+# CONFIG_MEMORY is not set -+CONFIG_IIO=y -+CONFIG_IIO_BUFFER=y -+# CONFIG_IIO_BUFFER_CB is not set -+# CONFIG_IIO_BUFFER_DMA is not set -+# CONFIG_IIO_BUFFER_DMAENGINE is not set -+# CONFIG_IIO_BUFFER_HW_CONSUMER is not set -+CONFIG_IIO_KFIFO_BUF=y -+CONFIG_IIO_TRIGGERED_BUFFER=y -+# CONFIG_IIO_CONFIGFS is not set -+CONFIG_IIO_TRIGGER=y -+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -+# CONFIG_IIO_SW_DEVICE is not set -+# CONFIG_IIO_SW_TRIGGER is not set -+# CONFIG_IIO_TRIGGERED_EVENT is not set -+ -+# -+# Accelerometers -+# -+# CONFIG_ADIS16201 is not set -+# CONFIG_ADIS16209 is not set -+# CONFIG_ADXL345_I2C is not set -+# CONFIG_ADXL345_SPI is not set -+# CONFIG_ADXL372_SPI is not set -+# CONFIG_ADXL372_I2C is not set -+# CONFIG_BMA180 is not set -+# CONFIG_BMA220 is not set -+# CONFIG_BMA400 is not set -+# CONFIG_BMC150_ACCEL is not set -+# CONFIG_DA280 is not set -+# CONFIG_DA311 is not set -+# CONFIG_DMARD06 is not set -+# CONFIG_DMARD09 is not set -+# CONFIG_DMARD10 is not set -+# CONFIG_IIO_ST_ACCEL_3AXIS is not set -+# CONFIG_KXSD9 is not set -+# CONFIG_KXCJK1013 is not set -+# CONFIG_MC3230 is not set -+# CONFIG_MMA7455_I2C is not set -+# CONFIG_MMA7455_SPI is not set -+# CONFIG_MMA7660 is not set -+# CONFIG_MMA8452 is not set -+# CONFIG_MMA9551 is not set -+# CONFIG_MMA9553 is not set -+# CONFIG_MXC4005 is not set -+# CONFIG_MXC6255 is not set -+# CONFIG_SCA3000 is not set -+# CONFIG_STK8312 is not set -+# CONFIG_STK8BA50 is not set -+# end of Accelerometers -+ -+# -+# Analog to digital converters -+# -+# CONFIG_AD7091R5 is not set -+# CONFIG_AD7124 is not set -+# CONFIG_AD7192 is not set -+# CONFIG_AD7266 is not set -+# CONFIG_AD7291 is not set -+# CONFIG_AD7292 is not set -+# CONFIG_AD7298 is not set -+# CONFIG_AD7476 is not set -+# CONFIG_AD7606_IFACE_PARALLEL is not set -+# CONFIG_AD7606_IFACE_SPI is not set -+# CONFIG_AD7766 is not set -+# CONFIG_AD7768_1 is not set -+# CONFIG_AD7780 is not set -+# CONFIG_AD7791 is not set -+# CONFIG_AD7793 is not set -+# CONFIG_AD7887 is not set -+# CONFIG_AD7923 is not set -+# CONFIG_AD7949 is not set -+# CONFIG_AD799X is not set -+# CONFIG_ADI_AXI_ADC is not set -+# CONFIG_CC10001_ADC is not set -+# CONFIG_ENVELOPE_DETECTOR is not set -+# CONFIG_HI8435 is not set -+# CONFIG_HX711 is not set -+# CONFIG_INA2XX_ADC is not set -+# CONFIG_LTC2471 is not set -+# CONFIG_LTC2485 is not set -+# CONFIG_LTC2496 is not set -+# CONFIG_LTC2497 is not set -+# CONFIG_MAX1027 is not set -+# CONFIG_MAX11100 is not set -+# CONFIG_MAX1118 is not set -+# CONFIG_MAX1241 is not set -+# CONFIG_MAX1363 is not set -+# CONFIG_MAX9611 is not set -+# CONFIG_MCP320X is not set -+# CONFIG_MCP3422 is not set -+# CONFIG_MCP3911 is not set -+# CONFIG_NAU7802 is not set -+CONFIG_ROCKCHIP_SARADC=y -+# CONFIG_ROCKCHIP_SARADC_TEST_CHN is not set -+# CONFIG_SD_ADC_MODULATOR is not set -+# CONFIG_TI_ADC081C is not set -+# CONFIG_TI_ADC0832 is not set -+# CONFIG_TI_ADC084S021 is not set -+# CONFIG_TI_ADC12138 is not set -+# CONFIG_TI_ADC108S102 is not set -+# CONFIG_TI_ADC128S052 is not set -+# CONFIG_TI_ADC161S626 is not set -+# CONFIG_TI_ADS1015 is not set -+# CONFIG_TI_ADS7950 is not set -+# CONFIG_TI_ADS8344 is not set -+# CONFIG_TI_ADS8688 is not set -+# CONFIG_TI_ADS124S08 is not set -+# CONFIG_TI_TLC4541 is not set -+# CONFIG_VF610_ADC is not set -+# CONFIG_XILINX_XADC is not set -+# end of Analog to digital converters -+ -+# -+# Analog Front Ends -+# -+# CONFIG_IIO_RESCALE is not set -+# end of Analog Front Ends -+ -+# -+# Amplifiers -+# -+# CONFIG_AD8366 is not set -+# CONFIG_HMC425 is not set -+# end of Amplifiers -+ -+# -+# Chemical Sensors -+# -+# CONFIG_ATLAS_PH_SENSOR is not set -+# CONFIG_ATLAS_EZO_SENSOR is not set -+# CONFIG_BME680 is not set -+# CONFIG_CCS811 is not set -+# CONFIG_IAQCORE is not set -+# CONFIG_SCD30_CORE is not set -+# CONFIG_SENSIRION_SGP30 is not set -+# CONFIG_SPS30 is not set -+# CONFIG_VZ89X is not set -+# end of Chemical Sensors -+ -+# -+# Hid Sensor IIO Common -+# -+# end of Hid Sensor IIO Common -+ -+# -+# SSP Sensor Common -+# -+# CONFIG_IIO_SSP_SENSORHUB is not set -+# end of SSP Sensor Common -+ -+# -+# Digital to analog converters -+# -+# CONFIG_AD5064 is not set -+# CONFIG_AD5360 is not set -+# CONFIG_AD5380 is not set -+# CONFIG_AD5421 is not set -+# CONFIG_AD5446 is not set -+# CONFIG_AD5449 is not set -+# CONFIG_AD5592R is not set -+# CONFIG_AD5593R is not set -+# CONFIG_AD5504 is not set -+# CONFIG_AD5624R_SPI is not set -+# CONFIG_AD5686_SPI is not set -+# CONFIG_AD5696_I2C is not set -+# CONFIG_AD5755 is not set -+# CONFIG_AD5758 is not set -+# CONFIG_AD5761 is not set -+# CONFIG_AD5764 is not set -+# CONFIG_AD5770R is not set -+# CONFIG_AD5791 is not set -+# CONFIG_AD7303 is not set -+# CONFIG_AD8801 is not set -+# CONFIG_DPOT_DAC is not set -+# CONFIG_DS4424 is not set -+# CONFIG_LTC1660 is not set -+# CONFIG_LTC2632 is not set -+# CONFIG_M62332 is not set -+# CONFIG_MAX517 is not set -+# CONFIG_MAX5821 is not set -+# CONFIG_MCP4725 is not set -+# CONFIG_MCP4922 is not set -+# CONFIG_TI_DAC082S085 is not set -+# CONFIG_TI_DAC5571 is not set -+# CONFIG_TI_DAC7311 is not set -+# CONFIG_TI_DAC7612 is not set -+# CONFIG_VF610_DAC is not set -+# end of Digital to analog converters -+ -+# -+# IIO dummy driver -+# -+# end of IIO dummy driver -+ -+# -+# Frequency Synthesizers DDS/PLL -+# -+ -+# -+# Clock Generator/Distribution -+# -+# CONFIG_AD9523 is not set -+# end of Clock Generator/Distribution -+ -+# -+# Phase-Locked Loop (PLL) frequency synthesizers -+# -+# CONFIG_ADF4350 is not set -+# CONFIG_ADF4371 is not set -+# end of Phase-Locked Loop (PLL) frequency synthesizers -+# end of Frequency Synthesizers DDS/PLL -+ -+# -+# Digital gyroscope sensors -+# -+# CONFIG_ADIS16080 is not set -+# CONFIG_ADIS16130 is not set -+# CONFIG_ADIS16136 is not set -+# CONFIG_ADIS16260 is not set -+# CONFIG_ADXRS290 is not set -+# CONFIG_ADXRS450 is not set -+# CONFIG_BMG160 is not set -+# CONFIG_FXAS21002C is not set -+# CONFIG_MPU3050_I2C is not set -+# CONFIG_IIO_ST_GYRO_3AXIS is not set -+# CONFIG_ITG3200 is not set -+# end of Digital gyroscope sensors -+ -+# -+# Health Sensors -+# -+ -+# -+# Heart Rate Monitors -+# -+# CONFIG_AFE4403 is not set -+# CONFIG_AFE4404 is not set -+# CONFIG_MAX30100 is not set -+# CONFIG_MAX30102 is not set -+# end of Heart Rate Monitors -+# end of Health Sensors -+ -+# -+# Humidity sensors -+# -+# CONFIG_AM2315 is not set -+# CONFIG_DHT11 is not set -+# CONFIG_HDC100X is not set -+# CONFIG_HDC2010 is not set -+# CONFIG_HTS221 is not set -+# CONFIG_HTU21 is not set -+# CONFIG_SI7005 is not set -+# CONFIG_SI7020 is not set -+# end of Humidity sensors -+ -+# -+# Inertial measurement units -+# -+# CONFIG_ADIS16400 is not set -+# CONFIG_ADIS16460 is not set -+# CONFIG_ADIS16475 is not set -+# CONFIG_ADIS16480 is not set -+# CONFIG_BMI160_I2C is not set -+# CONFIG_BMI160_SPI is not set -+# CONFIG_FXOS8700_I2C is not set -+# CONFIG_FXOS8700_SPI is not set -+# CONFIG_KMX61 is not set -+# CONFIG_INV_ICM42600_I2C is not set -+# CONFIG_INV_ICM42600_SPI is not set -+# CONFIG_INV_MPU6050_I2C is not set -+# CONFIG_INV_MPU6050_SPI is not set -+# CONFIG_IIO_ST_LSM6DSX is not set -+# end of Inertial measurement units -+ -+# -+# Light sensors -+# -+# CONFIG_ADJD_S311 is not set -+# CONFIG_ADUX1020 is not set -+# CONFIG_AL3010 is not set -+# CONFIG_AL3320A is not set -+# CONFIG_APDS9300 is not set -+# CONFIG_APDS9960 is not set -+# CONFIG_AS73211 is not set -+# CONFIG_BH1750 is not set -+# CONFIG_BH1780 is not set -+# CONFIG_CM32181 is not set -+# CONFIG_CM3232 is not set -+# CONFIG_CM3323 is not set -+# CONFIG_CM3605 is not set -+# CONFIG_CM36651 is not set -+# CONFIG_GP2AP002 is not set -+# CONFIG_GP2AP020A00F is not set -+CONFIG_SENSORS_ISL29018=y -+# CONFIG_SENSORS_ISL29028 is not set -+# CONFIG_ISL29125 is not set -+# CONFIG_JSA1212 is not set -+# CONFIG_RPR0521 is not set -+# CONFIG_LTR501 is not set -+# CONFIG_LV0104CS is not set -+# CONFIG_MAX44000 is not set -+# CONFIG_MAX44009 is not set -+# CONFIG_NOA1305 is not set -+# CONFIG_OPT3001 is not set -+# CONFIG_PA12203001 is not set -+# CONFIG_SI1133 is not set -+# CONFIG_SI1145 is not set -+# CONFIG_STK3310 is not set -+# CONFIG_ST_UVIS25 is not set -+# CONFIG_TCS3414 is not set -+# CONFIG_TCS3472 is not set -+CONFIG_SENSORS_TSL2563=y -+CONFIG_TSL2583=y -+# CONFIG_TSL2772 is not set -+# CONFIG_TSL4531 is not set -+# CONFIG_US5182D is not set -+# CONFIG_VCNL4000 is not set -+# CONFIG_VCNL4035 is not set -+# CONFIG_VEML6030 is not set -+# CONFIG_VEML6070 is not set -+# CONFIG_VL6180 is not set -+# CONFIG_ZOPT2201 is not set -+# end of Light sensors -+ -+# -+# Magnetometer sensors -+# -+# CONFIG_AK8974 is not set -+# CONFIG_AK8975 is not set -+# CONFIG_AK09911 is not set -+# CONFIG_BMC150_MAGN_I2C is not set -+# CONFIG_BMC150_MAGN_SPI is not set -+# CONFIG_MAG3110 is not set -+# CONFIG_MMC35240 is not set -+# CONFIG_IIO_ST_MAGN_3AXIS is not set -+# CONFIG_SENSORS_HMC5843_I2C is not set -+# CONFIG_SENSORS_HMC5843_SPI is not set -+# CONFIG_SENSORS_RM3100_I2C is not set -+# CONFIG_SENSORS_RM3100_SPI is not set -+# end of Magnetometer sensors -+ -+# -+# Multiplexers -+# -+# CONFIG_IIO_MUX is not set -+# end of Multiplexers -+ -+# -+# Inclinometer sensors -+# -+# end of Inclinometer sensors -+ -+# -+# Triggers - standalone -+# -+# CONFIG_IIO_INTERRUPT_TRIGGER is not set -+CONFIG_IIO_SYSFS_TRIGGER=y -+# end of Triggers - standalone -+ -+# -+# Linear and angular position sensors -+# -+# end of Linear and angular position sensors -+ -+# -+# Digital potentiometers -+# -+# CONFIG_AD5272 is not set -+# CONFIG_DS1803 is not set -+# CONFIG_MAX5432 is not set -+# CONFIG_MAX5481 is not set -+# CONFIG_MAX5487 is not set -+# CONFIG_MCP4018 is not set -+# CONFIG_MCP4131 is not set -+# CONFIG_MCP4531 is not set -+# CONFIG_MCP41010 is not set -+# CONFIG_TPL0102 is not set -+# end of Digital potentiometers -+ -+# -+# Digital potentiostats -+# -+# CONFIG_LMP91000 is not set -+# end of Digital potentiostats -+ -+# -+# Pressure sensors -+# -+# CONFIG_ABP060MG is not set -+# CONFIG_BMP280 is not set -+# CONFIG_DLHL60D is not set -+# CONFIG_DPS310 is not set -+# CONFIG_HP03 is not set -+# CONFIG_ICP10100 is not set -+# CONFIG_MPL115_I2C is not set -+# CONFIG_MPL115_SPI is not set -+# CONFIG_MPL3115 is not set -+# CONFIG_MS5611 is not set -+# CONFIG_MS5637 is not set -+# CONFIG_IIO_ST_PRESS is not set -+# CONFIG_T5403 is not set -+# CONFIG_HP206C is not set -+# CONFIG_ZPA2326 is not set -+# end of Pressure sensors -+ -+# -+# Lightning sensors -+# -+# CONFIG_AS3935 is not set -+# end of Lightning sensors -+ -+# -+# Proximity and distance sensors -+# -+# CONFIG_ISL29501 is not set -+# CONFIG_LIDAR_LITE_V2 is not set -+# CONFIG_MB1232 is not set -+# CONFIG_PING is not set -+# CONFIG_RFD77402 is not set -+# CONFIG_SRF04 is not set -+# CONFIG_SX9310 is not set -+# CONFIG_SX9500 is not set -+# CONFIG_SRF08 is not set -+# CONFIG_VCNL3020 is not set -+# CONFIG_VL53L0X_I2C is not set -+# end of Proximity and distance sensors -+ -+# -+# Resolver to digital converters -+# -+# CONFIG_AD2S90 is not set -+# CONFIG_AD2S1200 is not set -+# end of Resolver to digital converters -+ -+# -+# Temperature sensors -+# -+# CONFIG_LTC2983 is not set -+# CONFIG_MAXIM_THERMOCOUPLE is not set -+# CONFIG_MLX90614 is not set -+# CONFIG_MLX90632 is not set -+# CONFIG_TMP006 is not set -+# CONFIG_TMP007 is not set -+# CONFIG_TSYS01 is not set -+# CONFIG_TSYS02D is not set -+# CONFIG_MAX31856 is not set -+# end of Temperature sensors -+ -+# CONFIG_NTB is not set -+# CONFIG_VME_BUS is not set -+CONFIG_PWM=y -+CONFIG_PWM_SYSFS=y -+# CONFIG_PWM_DEBUG is not set -+# CONFIG_PWM_FSL_FTM is not set -+# CONFIG_PWM_PCA9685 is not set -+CONFIG_PWM_ROCKCHIP=y -+# CONFIG_PWM_ROCKCHIP_ONESHOT is not set -+ -+# -+# IRQ chip support -+# -+CONFIG_IRQCHIP=y -+CONFIG_ARM_GIC=y -+CONFIG_ARM_GIC_MAX_NR=1 -+CONFIG_ARM_GIC_V2M=y -+CONFIG_ARM_GIC_V3=y -+CONFIG_ARM_GIC_V3_ITS=y -+CONFIG_ARM_GIC_V3_ITS_PCI=y -+# CONFIG_AL_FIC is not set -+CONFIG_PARTITION_PERCPU=y -+# end of IRQ chip support -+ -+# CONFIG_IPACK_BUS is not set -+CONFIG_ARCH_HAS_RESET_CONTROLLER=y -+CONFIG_RESET_CONTROLLER=y -+CONFIG_RESET_SCMI=y -+# CONFIG_RESET_TI_SYSCON is not set -+ -+# -+# PHY Subsystem -+# -+CONFIG_GENERIC_PHY=y -+CONFIG_GENERIC_PHY_MIPI_DPHY=y -+# CONFIG_PHY_XGENE is not set -+# CONFIG_BCM_KONA_USB2_PHY is not set -+# CONFIG_PHY_CADENCE_TORRENT is not set -+# CONFIG_PHY_CADENCE_DPHY is not set -+# CONFIG_PHY_CADENCE_SIERRA is not set -+# CONFIG_PHY_CADENCE_SALVO is not set -+# CONFIG_PHY_FSL_IMX8MQ_USB is not set -+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set -+# CONFIG_PHY_PXA_28NM_HSIC is not set -+# CONFIG_PHY_PXA_28NM_USB2 is not set -+# CONFIG_PHY_CPCAP_USB is not set -+# CONFIG_PHY_MAPPHONE_MDM6600 is not set -+# CONFIG_PHY_OCELOT_SERDES is not set -+CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y -+CONFIG_PHY_ROCKCHIP_DP=y -+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set -+CONFIG_PHY_ROCKCHIP_EMMC=y -+# CONFIG_PHY_ROCKCHIP_INNO_COMBPHY is not set -+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_INNO_USB3=y -+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y -+CONFIG_PHY_ROCKCHIP_MIPI_RX=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y -+CONFIG_PHY_ROCKCHIP_NANENG_EDP=y -+# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set -+CONFIG_PHY_ROCKCHIP_PCIE=y -+# CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY is not set -+# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set -+# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI is not set -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -+CONFIG_PHY_ROCKCHIP_TYPEC=y -+CONFIG_PHY_ROCKCHIP_USB=y -+# CONFIG_PHY_ROCKCHIP_USBDP is not set -+# CONFIG_PHY_SAMSUNG_USB2 is not set -+# end of PHY Subsystem -+ -+# CONFIG_POWERCAP is not set -+# CONFIG_MCB is not set -+ -+# -+# Performance monitor support -+# -+# CONFIG_ARM_CCI_PMU is not set -+# CONFIG_ARM_CCN is not set -+# CONFIG_ARM_CMN is not set -+CONFIG_ARM_PMU=y -+# CONFIG_ARM_DSU_PMU is not set -+# CONFIG_ARM_SPE_PMU is not set -+# end of Performance monitor support -+ -+# CONFIG_RAS is not set -+# CONFIG_USB4 is not set -+ -+# -+# Android -+# -+CONFIG_ANDROID=y -+CONFIG_ANDROID_BINDER_IPC=y -+# CONFIG_ANDROID_BINDERFS is not set -+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" -+# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set -+# end of Android -+ -+# CONFIG_LIBNVDIMM is not set -+# CONFIG_DAX is not set -+CONFIG_NVMEM=y -+CONFIG_NVMEM_SYSFS=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_ROCKCHIP_OTP=y -+ -+# -+# HW tracing support -+# -+# CONFIG_STM is not set -+# CONFIG_INTEL_TH is not set -+# end of HW tracing support -+ -+# CONFIG_FPGA is not set -+# CONFIG_FSI is not set -+CONFIG_TEE=y -+ -+# -+# TEE drivers -+# -+CONFIG_OPTEE=y -+CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 -+# end of TEE drivers -+ -+CONFIG_PM_OPP=y -+# CONFIG_SIOX is not set -+# CONFIG_SLIMBUS is not set -+# CONFIG_INTERCONNECT is not set -+# CONFIG_COUNTER is not set -+CONFIG_DRIVERS_HDF=y -+CONFIG_HDF_SUPPORT_LEVEL=2 -+CONFIG_DRIVERS_HDF_PLATFORM=y -+# CONFIG_DRIVERS_HDF_PLATFORM_MIPI_DSI is not set -+# CONFIG_DRIVERS_HDF_PLATFORM_MIPI_CSI is not set -+CONFIG_DRIVERS_HDF_PLATFORM_GPIO=y -+CONFIG_DRIVERS_HDF_PLATFORM_I2C=y -+# CONFIG_DRIVERS_HDF_PLATFORM_WATCHDOG is not set -+CONFIG_DRIVERS_HDF_PLATFORM_PWM=y -+CONFIG_DRIVERS_HDF_PLATFORM_UART=y -+# CONFIG_DRIVERS_HDF_PLATFORM_SDIO is not set -+# CONFIG_DRIVERS_HDF_PLATFORM_EMMC is not set -+# CONFIG_DRIVERS_HDF_PLATFORM_MMC is not set -+CONFIG_DRIVERS_HDF_PLATFORM_SPI=y -+# CONFIG_DRIVERS_HDF_PLATFORM_RTC is not set -+# CONFIG_PWM_HI35XX is not set -+# CONFIG_DRIVERS_HDF_PLATFORM_REGULATOR is not set -+CONFIG_DRIVERS_HDF_TEST=y -+# CONFIG_DRIVERS_HDF_DISP is not set -+CONFIG_DRIVERS_HDF_INPUT=y -+CONFIG_DRIVERS_HDF_TP_5P5_GT911=y -+# CONFIG_DRIVERS_HDF_TP_2P35_FT6236 is not set -+# CONFIG_DRIVERS_HDF_WIFI is not set -+# CONFIG_DRIVERS_HDF_BT is not set -+CONFIG_DRIVERS_HDF_SENSOR=y -+CONFIG_DRIVERS_HDF_SENSOR_ACCEL=y -+CONFIG_DRIVERS_HDF_SENSOR_ACCEL_MXC6655XA=y -+# CONFIG_DRIVERS_HDF_STORAGE is not set -+CONFIG_DRIVERS_HDF_USB_PNP_NOTIFY=y -+CONFIG_DRIVERS_HDF_USB_F_GENERIC=y -+CONFIG_DRIVERS_HDF_AUDIO=y -+CONFIG_DRIVERS_HDF_AUDIO_RK3568=y -+CONFIG_DRIVERS_HDF_AUDIO_ANA_HEADSET=y -+CONFIG_DRIVERS_HDF_VIBRATOR=y -+CONFIG_DRIVERS_HDF_VIBRATOR_LINEAR=y -+# CONFIG_DRIVERS_HDF_DSOFTBUS is not set -+# CONFIG_MOST is not set -+# CONFIG_RK_FLASH is not set -+# CONFIG_RK_NAND is not set -+CONFIG_ACCESS_TOKENID=y -+# end of Device Drivers -+ -+# -+# File systems -+# -+CONFIG_DCACHE_WORD_ACCESS=y -+# CONFIG_VALIDATE_FS_PARSER is not set -+CONFIG_FS_IOMAP=y -+# CONFIG_EXT2_FS is not set -+# CONFIG_EXT3_FS is not set -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_USE_FOR_EXT2=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+# CONFIG_EXT4_DEBUG is not set -+CONFIG_HMDFS_FS=y -+CONFIG_HMDFS_FS_PERMISSION=y -+CONFIG_JBD2=y -+# CONFIG_JBD2_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+CONFIG_XFS_FS=y -+CONFIG_XFS_SUPPORT_V4=y -+# CONFIG_XFS_QUOTA is not set -+# CONFIG_XFS_POSIX_ACL is not set -+# CONFIG_XFS_RT is not set -+# CONFIG_XFS_ONLINE_SCRUB is not set -+# CONFIG_XFS_WARN is not set -+# CONFIG_XFS_DEBUG is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+# CONFIG_BTRFS_FS is not set -+# CONFIG_NILFS2_FS is not set -+CONFIG_F2FS_FS=y -+CONFIG_F2FS_STAT_FS=y -+CONFIG_F2FS_FS_XATTR=y -+CONFIG_F2FS_FS_POSIX_ACL=y -+CONFIG_F2FS_FS_SECURITY=y -+CONFIG_F2FS_GRADING_SSR=y -+# CONFIG_F2FS_CHECK_FS is not set -+# CONFIG_F2FS_IO_TRACE is not set -+# CONFIG_F2FS_FAULT_INJECTION is not set -+# CONFIG_F2FS_FS_COMPRESSION is not set -+# CONFIG_FS_DAX is not set -+CONFIG_FS_POSIX_ACL=y -+CONFIG_EXPORTFS=y -+# CONFIG_EXPORTFS_BLOCK_OPS is not set -+CONFIG_FILE_LOCKING=y -+CONFIG_MANDATORY_FILE_LOCKING=y -+CONFIG_FS_ENCRYPTION=y -+CONFIG_FS_ENCRYPTION_ALGS=y -+# CONFIG_FS_VERITY is not set -+CONFIG_FSNOTIFY=y -+# CONFIG_DNOTIFY is not set -+CONFIG_INOTIFY_USER=y -+# CONFIG_FANOTIFY is not set -+# CONFIG_QUOTA is not set -+# CONFIG_AUTOFS4_FS is not set -+# CONFIG_AUTOFS_FS is not set -+CONFIG_FUSE_FS=y -+# CONFIG_CUSE is not set -+# CONFIG_VIRTIO_FS is not set -+# CONFIG_OVERLAY_FS is not set -+ -+# -+# Caches -+# -+# CONFIG_FSCACHE is not set -+# end of Caches -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=y -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+# CONFIG_UDF_FS is not set -+# end of CD-ROM/DVD Filesystems -+ -+# -+# DOS/FAT/EXFAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=936 -+CONFIG_FAT_DEFAULT_IOCHARSET="utf8" -+# CONFIG_FAT_DEFAULT_UTF8 is not set -+CONFIG_EXFAT_FS=y -+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -+CONFIG_NTFS_FS=y -+# CONFIG_NTFS_DEBUG is not set -+# CONFIG_NTFS_RW is not set -+# end of DOS/FAT/EXFAT/NT Filesystems -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+# CONFIG_PROC_KCORE is not set -+CONFIG_PROC_SYSCTL=y -+CONFIG_PROC_PAGE_MONITOR=y -+# CONFIG_PROC_CHILDREN is not set -+CONFIG_KERNFS=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_TMPFS_XATTR=y -+# CONFIG_TMPFS_INODE64 is not set -+# CONFIG_HUGETLBFS is not set -+CONFIG_MEMFD_CREATE=y -+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y -+CONFIG_CONFIGFS_FS=y -+# end of Pseudo filesystems -+ -+CONFIG_MISC_FILESYSTEMS=y -+# CONFIG_ORANGEFS_FS is not set -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_ECRYPT_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_RTIME=y -+CONFIG_UBIFS_FS=y -+CONFIG_UBIFS_FS_ADVANCED_COMPR=y -+CONFIG_UBIFS_FS_LZO=y -+CONFIG_UBIFS_FS_ZLIB=y -+CONFIG_UBIFS_FS_ZSTD=y -+# CONFIG_UBIFS_ATIME_SUPPORT is not set -+CONFIG_UBIFS_FS_XATTR=y -+CONFIG_UBIFS_FS_SECURITY=y -+# CONFIG_UBIFS_FS_AUTHENTICATION is not set -+# CONFIG_CRAMFS is not set -+CONFIG_SQUASHFS=y -+CONFIG_SQUASHFS_FILE_CACHE=y -+# CONFIG_SQUASHFS_FILE_DIRECT is not set -+CONFIG_SQUASHFS_DECOMP_SINGLE=y -+# CONFIG_SQUASHFS_DECOMP_MULTI is not set -+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -+# CONFIG_SQUASHFS_XATTR is not set -+CONFIG_SQUASHFS_ZLIB=y -+# CONFIG_SQUASHFS_LZ4 is not set -+# CONFIG_SQUASHFS_LZO is not set -+# CONFIG_SQUASHFS_XZ is not set -+# CONFIG_SQUASHFS_ZSTD is not set -+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set -+# CONFIG_SQUASHFS_EMBEDDED is not set -+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -+# CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_OMFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_QNX6FS_FS is not set -+# CONFIG_ROMFS_FS is not set -+CONFIG_PSTORE=y -+CONFIG_PSTORE_DEFLATE_COMPRESS=y -+# CONFIG_PSTORE_LZO_COMPRESS is not set -+# CONFIG_PSTORE_LZ4_COMPRESS is not set -+# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -+# CONFIG_PSTORE_842_COMPRESS is not set -+# CONFIG_PSTORE_ZSTD_COMPRESS is not set -+CONFIG_PSTORE_COMPRESS=y -+CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -+CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -+CONFIG_PSTORE_CONSOLE=y -+# CONFIG_PSTORE_PMSG is not set -+# CONFIG_PSTORE_FTRACE is not set -+CONFIG_PSTORE_BLACKBOX=y -+CONFIG_PSTORE_RAM=y -+CONFIG_BLACKBOX_STORAGE_BY_PSTORE_RAM=y -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+# CONFIG_EROFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V2=y -+CONFIG_NFS_V3=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_SWAP=y -+# CONFIG_NFS_V4_1 is not set -+# CONFIG_NFS_USE_LEGACY_DNS is not set -+CONFIG_NFS_USE_KERNEL_DNS=y -+CONFIG_NFS_DISABLE_UDP_SUPPORT=y -+# CONFIG_NFSD is not set -+CONFIG_GRACE_PERIOD=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_ACL_SUPPORT=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+CONFIG_SUNRPC_GSS=y -+CONFIG_SUNRPC_SWAP=y -+# CONFIG_SUNRPC_DEBUG is not set -+# CONFIG_CEPH_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+# CONFIG_NLS_CODEPAGE_850 is not set -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+CONFIG_NLS_CODEPAGE_936=y -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+# CONFIG_NLS_ISO8859_2 is not set -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+# CONFIG_NLS_MAC_ROMAN is not set -+# CONFIG_NLS_MAC_CELTIC is not set -+# CONFIG_NLS_MAC_CENTEURO is not set -+# CONFIG_NLS_MAC_CROATIAN is not set -+# CONFIG_NLS_MAC_CYRILLIC is not set -+# CONFIG_NLS_MAC_GAELIC is not set -+# CONFIG_NLS_MAC_GREEK is not set -+# CONFIG_NLS_MAC_ICELAND is not set -+# CONFIG_NLS_MAC_INUIT is not set -+# CONFIG_NLS_MAC_ROMANIAN is not set -+# CONFIG_NLS_MAC_TURKISH is not set -+CONFIG_NLS_UTF8=y -+# CONFIG_DLM is not set -+CONFIG_UNICODE=y -+# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set -+CONFIG_IO_WQ=y -+# end of File systems -+ -+# -+# Security options -+# -+CONFIG_KEYS=y -+# CONFIG_KEYS_REQUEST_CACHE is not set -+# CONFIG_PERSISTENT_KEYRINGS is not set -+# CONFIG_TRUSTED_KEYS is not set -+# CONFIG_ENCRYPTED_KEYS is not set -+# CONFIG_KEY_DH_OPERATIONS is not set -+# CONFIG_SECURITY_DMESG_RESTRICT is not set -+CONFIG_SECURITY=y -+CONFIG_SECURITYFS=y -+CONFIG_SECURITY_NETWORK=y -+# CONFIG_SECURITY_NETWORK_XFRM is not set -+CONFIG_SECURITY_PATH=y -+CONFIG_LSM_MMAP_MIN_ADDR=32768 -+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -+# CONFIG_HARDENED_USERCOPY is not set -+# CONFIG_FORTIFY_SOURCE is not set -+# CONFIG_STATIC_USERMODEHELPER is not set -+CONFIG_SECURITY_SELINUX=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM=y -+# CONFIG_SECURITY_SELINUX_DISABLE is not set -+CONFIG_SECURITY_SELINUX_DEVELOP=y -+CONFIG_SECURITY_SELINUX_AVC_STATS=y -+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 -+CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 -+CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 -+# CONFIG_SECURITY_SMACK is not set -+# CONFIG_SECURITY_TOMOYO is not set -+CONFIG_SECURITY_APPARMOR=y -+CONFIG_SECURITY_APPARMOR_HASH=y -+CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y -+# CONFIG_SECURITY_APPARMOR_DEBUG is not set -+# CONFIG_SECURITY_LOADPIN is not set -+# CONFIG_SECURITY_YAMA is not set -+# CONFIG_SECURITY_SAFESETID is not set -+# CONFIG_SECURITY_LOCKDOWN_LSM is not set -+CONFIG_INTEGRITY=y -+# CONFIG_INTEGRITY_SIGNATURE is not set -+CONFIG_INTEGRITY_AUDIT=y -+# CONFIG_IMA is not set -+# CONFIG_EVM is not set -+# CONFIG_DEFAULT_SECURITY_SELINUX is not set -+# CONFIG_DEFAULT_SECURITY_APPARMOR is not set -+CONFIG_DEFAULT_SECURITY_DAC=y -+CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf,selinux" -+ -+# -+# Kernel hardening options -+# -+ -+# -+# Memory initialization -+# -+CONFIG_INIT_STACK_NONE=y -+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -+# end of Memory initialization -+# end of Kernel hardening options -+# end of Security options -+ -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_ALGAPI2=y -+CONFIG_CRYPTO_AEAD=y -+CONFIG_CRYPTO_AEAD2=y -+CONFIG_CRYPTO_SKCIPHER=y -+CONFIG_CRYPTO_SKCIPHER2=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_HASH2=y -+CONFIG_CRYPTO_RNG=y -+CONFIG_CRYPTO_RNG2=y -+CONFIG_CRYPTO_RNG_DEFAULT=y -+CONFIG_CRYPTO_AKCIPHER2=y -+CONFIG_CRYPTO_AKCIPHER=y -+CONFIG_CRYPTO_KPP2=y -+CONFIG_CRYPTO_KPP=y -+CONFIG_CRYPTO_ACOMP2=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_MANAGER2=y -+# CONFIG_CRYPTO_USER is not set -+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -+CONFIG_CRYPTO_GF128MUL=y -+CONFIG_CRYPTO_NULL=y -+CONFIG_CRYPTO_NULL2=y -+# CONFIG_CRYPTO_PCRYPT is not set -+CONFIG_CRYPTO_CRYPTD=y -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_TEST is not set -+CONFIG_CRYPTO_SIMD=y -+ -+# -+# Public-key cryptography -+# -+CONFIG_CRYPTO_RSA=y -+# CONFIG_CRYPTO_DH is not set -+CONFIG_CRYPTO_ECC=y -+CONFIG_CRYPTO_ECDH=y -+# CONFIG_CRYPTO_ECRDSA is not set -+# CONFIG_CRYPTO_SM2 is not set -+# CONFIG_CRYPTO_CURVE25519 is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+CONFIG_CRYPTO_CCM=y -+CONFIG_CRYPTO_GCM=y -+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set -+# CONFIG_CRYPTO_AEGIS128 is not set -+# CONFIG_CRYPTO_SEQIV is not set -+# CONFIG_CRYPTO_ECHAINIV is not set -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=y -+# CONFIG_CRYPTO_CFB is not set -+CONFIG_CRYPTO_CTR=y -+CONFIG_CRYPTO_CTS=y -+CONFIG_CRYPTO_ECB=y -+# CONFIG_CRYPTO_LRW is not set -+# CONFIG_CRYPTO_OFB is not set -+# CONFIG_CRYPTO_PCBC is not set -+CONFIG_CRYPTO_XTS=y -+# CONFIG_CRYPTO_KEYWRAP is not set -+# CONFIG_CRYPTO_ADIANTUM is not set -+# CONFIG_CRYPTO_ESSIV is not set -+ -+# -+# Hash modes -+# -+CONFIG_CRYPTO_CMAC=y -+CONFIG_CRYPTO_HMAC=y -+# CONFIG_CRYPTO_XCBC is not set -+# CONFIG_CRYPTO_VMAC is not set -+ -+# -+# Digest -+# -+CONFIG_CRYPTO_CRC32C=y -+CONFIG_CRYPTO_CRC32=y -+# CONFIG_CRYPTO_XXHASH is not set -+# CONFIG_CRYPTO_BLAKE2B is not set -+# CONFIG_CRYPTO_BLAKE2S is not set -+CONFIG_CRYPTO_CRCT10DIF=y -+CONFIG_CRYPTO_GHASH=y -+# CONFIG_CRYPTO_POLY1305 is not set -+# CONFIG_CRYPTO_MD4 is not set -+CONFIG_CRYPTO_MD5=y -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_RMD128 is not set -+# CONFIG_CRYPTO_RMD160 is not set -+# CONFIG_CRYPTO_RMD256 is not set -+# CONFIG_CRYPTO_RMD320 is not set -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=y -+CONFIG_CRYPTO_SHA512=y -+# CONFIG_CRYPTO_SHA3 is not set -+# CONFIG_CRYPTO_SM3 is not set -+# CONFIG_CRYPTO_STREEBOG is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_WP512 is not set -+ -+# -+# Ciphers -+# -+CONFIG_CRYPTO_AES=y -+# CONFIG_CRYPTO_AES_TI is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+# CONFIG_CRYPTO_DES is not set -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_SALSA20 is not set -+# CONFIG_CRYPTO_CHACHA20 is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_SM4 is not set -+# CONFIG_CRYPTO_TEA is not set -+CONFIG_CRYPTO_TWOFISH=y -+CONFIG_CRYPTO_TWOFISH_COMMON=y -+ -+# -+# Compression -+# -+CONFIG_CRYPTO_DEFLATE=y -+CONFIG_CRYPTO_LZO=y -+# CONFIG_CRYPTO_842 is not set -+# CONFIG_CRYPTO_LZ4 is not set -+# CONFIG_CRYPTO_LZ4HC is not set -+CONFIG_CRYPTO_ZSTD=y -+ -+# -+# Random Number Generation -+# -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_DRBG_MENU=y -+CONFIG_CRYPTO_DRBG_HMAC=y -+# CONFIG_CRYPTO_DRBG_HASH is not set -+# CONFIG_CRYPTO_DRBG_CTR is not set -+CONFIG_CRYPTO_DRBG=y -+CONFIG_CRYPTO_JITTERENTROPY=y -+CONFIG_CRYPTO_USER_API=y -+CONFIG_CRYPTO_USER_API_HASH=y -+CONFIG_CRYPTO_USER_API_SKCIPHER=y -+# CONFIG_CRYPTO_USER_API_RNG is not set -+# CONFIG_CRYPTO_USER_API_AEAD is not set -+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y -+CONFIG_CRYPTO_HASH_INFO=y -+ -+# -+# Crypto library routines -+# -+CONFIG_CRYPTO_LIB_AES=y -+CONFIG_CRYPTO_LIB_ARC4=y -+# CONFIG_CRYPTO_LIB_BLAKE2S is not set -+# CONFIG_CRYPTO_LIB_CHACHA is not set -+# CONFIG_CRYPTO_LIB_CURVE25519 is not set -+CONFIG_CRYPTO_LIB_DES=y -+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -+# CONFIG_CRYPTO_LIB_POLY1305 is not set -+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set -+CONFIG_CRYPTO_LIB_SHA256=y -+CONFIG_CRYPTO_HW=y -+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set -+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -+# CONFIG_CRYPTO_DEV_CCP is not set -+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set -+CONFIG_CRYPTO_DEV_ROCKCHIP=y -+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set -+# CONFIG_CRYPTO_DEV_CCREE is not set -+# CONFIG_CRYPTO_DEV_HISI_SEC is not set -+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -+CONFIG_ASYMMETRIC_KEY_TYPE=y -+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -+CONFIG_X509_CERTIFICATE_PARSER=y -+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set -+CONFIG_PKCS7_MESSAGE_PARSER=y -+# CONFIG_PKCS7_TEST_KEY is not set -+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set -+ -+# -+# Certificates for signature checking -+# -+CONFIG_SYSTEM_TRUSTED_KEYRING=y -+CONFIG_SYSTEM_TRUSTED_KEYS="" -+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set -+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set -+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -+# end of Certificates for signature checking -+ -+CONFIG_BINARY_PRINTF=y -+ -+# -+# Library routines -+# -+CONFIG_LINEAR_RANGES=y -+# CONFIG_PACKING is not set -+CONFIG_BITREVERSE=y -+CONFIG_HAVE_ARCH_BITREVERSE=y -+CONFIG_GENERIC_STRNCPY_FROM_USER=y -+CONFIG_GENERIC_STRNLEN_USER=y -+CONFIG_GENERIC_NET_UTILS=y -+# CONFIG_CORDIC is not set -+# CONFIG_PRIME_NUMBERS is not set -+CONFIG_RATIONAL=y -+CONFIG_GENERIC_PCI_IOMAP=y -+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y -+# CONFIG_INDIRECT_PIO is not set -+CONFIG_CRC_CCITT=y -+CONFIG_CRC16=y -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC_ITU_T=y -+CONFIG_CRC32=y -+# CONFIG_CRC32_SELFTEST is not set -+CONFIG_CRC32_SLICEBY8=y -+# CONFIG_CRC32_SLICEBY4 is not set -+# CONFIG_CRC32_SARWATE is not set -+# CONFIG_CRC32_BIT is not set -+# CONFIG_CRC64 is not set -+# CONFIG_CRC4 is not set -+CONFIG_CRC7=y -+CONFIG_LIBCRC32C=y -+# CONFIG_CRC8 is not set -+CONFIG_XXHASH=y -+CONFIG_AUDIT_GENERIC=y -+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -+CONFIG_AUDIT_COMPAT_GENERIC=y -+# CONFIG_RANDOM32_SELFTEST is not set -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_LZO_COMPRESS=y -+CONFIG_LZO_DECOMPRESS=y -+CONFIG_LZ4_DECOMPRESS=y -+CONFIG_ZSTD_COMPRESS=y -+CONFIG_ZSTD_DECOMPRESS=y -+CONFIG_XZ_DEC=y -+# CONFIG_XZ_DEC_X86 is not set -+# CONFIG_XZ_DEC_POWERPC is not set -+# CONFIG_XZ_DEC_IA64 is not set -+CONFIG_XZ_DEC_ARM=y -+CONFIG_XZ_DEC_ARMTHUMB=y -+# CONFIG_XZ_DEC_SPARC is not set -+CONFIG_XZ_DEC_BCJ=y -+# CONFIG_XZ_DEC_TEST is not set -+CONFIG_DECOMPRESS_GZIP=y -+CONFIG_DECOMPRESS_BZIP2=y -+CONFIG_DECOMPRESS_LZMA=y -+CONFIG_DECOMPRESS_XZ=y -+CONFIG_DECOMPRESS_LZO=y -+CONFIG_DECOMPRESS_LZ4=y -+CONFIG_DECOMPRESS_ZSTD=y -+CONFIG_GENERIC_ALLOCATOR=y -+CONFIG_REED_SOLOMON=y -+CONFIG_REED_SOLOMON_ENC8=y -+CONFIG_REED_SOLOMON_DEC8=y -+CONFIG_ASSOCIATIVE_ARRAY=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT_MAP=y -+CONFIG_HAS_DMA=y -+CONFIG_DMA_OPS=y -+CONFIG_NEED_SG_DMA_LENGTH=y -+CONFIG_NEED_DMA_MAP_STATE=y -+CONFIG_ARCH_DMA_ADDR_T_64BIT=y -+CONFIG_DMA_DECLARE_COHERENT=y -+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y -+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y -+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -+CONFIG_SWIOTLB=y -+CONFIG_DMA_NONCOHERENT_MMAP=y -+CONFIG_DMA_COHERENT_POOL=y -+CONFIG_DMA_REMAP=y -+CONFIG_DMA_DIRECT_REMAP=y -+CONFIG_DMA_CMA=y -+# CONFIG_DMA_PERNUMA_CMA is not set -+ -+# -+# Default contiguous memory area size: -+# -+CONFIG_CMA_SIZE_MBYTES=16 -+CONFIG_CMA_SIZE_SEL_MBYTES=y -+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -+# CONFIG_CMA_SIZE_SEL_MIN is not set -+# CONFIG_CMA_SIZE_SEL_MAX is not set -+CONFIG_CMA_ALIGNMENT=8 -+# CONFIG_DMA_API_DEBUG is not set -+CONFIG_SGL_ALLOC=y -+CONFIG_CPU_RMAP=y -+CONFIG_DQL=y -+CONFIG_GLOB=y -+# CONFIG_GLOB_SELFTEST is not set -+CONFIG_NLATTR=y -+CONFIG_CLZ_TAB=y -+# CONFIG_IRQ_POLL is not set -+CONFIG_MPILIB=y -+CONFIG_LIBFDT=y -+CONFIG_OID_REGISTRY=y -+CONFIG_HAVE_GENERIC_VDSO=y -+CONFIG_GENERIC_GETTIMEOFDAY=y -+CONFIG_GENERIC_VDSO_TIME_NS=y -+CONFIG_SG_POOL=y -+CONFIG_ARCH_STACKWALK=y -+CONFIG_SBITMAP=y -+# CONFIG_STRING_SELFTEST is not set -+# end of Library routines -+ -+# -+# Kernel hacking -+# -+ -+# -+# printk and dmesg options -+# -+CONFIG_PRINTK_TIME=y -+# CONFIG_PRINTK_CALLER is not set -+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -+CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -+# CONFIG_BOOT_PRINTK_DELAY is not set -+CONFIG_DYNAMIC_DEBUG=y -+CONFIG_DYNAMIC_DEBUG_CORE=y -+CONFIG_SYMBOLIC_ERRNAME=y -+CONFIG_DEBUG_BUGVERBOSE=y -+# end of printk and dmesg options -+ -+# -+# Compile-time checks and compiler options -+# -+CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_INFO_REDUCED is not set -+# CONFIG_DEBUG_INFO_COMPRESSED is not set -+# CONFIG_DEBUG_INFO_SPLIT is not set -+# CONFIG_DEBUG_INFO_DWARF4 is not set -+# CONFIG_DEBUG_INFO_BTF is not set -+# CONFIG_GDB_SCRIPTS is not set -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_FRAME_WARN=2048 -+# CONFIG_STRIP_ASM_SYMS is not set -+# CONFIG_READABLE_ASM is not set -+# CONFIG_HEADERS_INSTALL is not set -+# CONFIG_DEBUG_SECTION_MISMATCH is not set -+CONFIG_SECTION_MISMATCH_WARN_ONLY=y -+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set -+CONFIG_ARCH_WANT_FRAME_POINTERS=y -+CONFIG_FRAME_POINTER=y -+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -+# end of Compile-time checks and compiler options -+ -+# -+# Generic Kernel Debugging Instruments -+# -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 -+CONFIG_MAGIC_SYSRQ_SERIAL=y -+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -+CONFIG_DEBUG_FS=y -+CONFIG_DEBUG_FS_ALLOW_ALL=y -+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -+# CONFIG_DEBUG_FS_ALLOW_NONE is not set -+CONFIG_HAVE_ARCH_KGDB=y -+# CONFIG_KGDB is not set -+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -+# CONFIG_UBSAN is not set -+# end of Generic Kernel Debugging Instruments -+ -+CONFIG_DEBUG_KERNEL=y -+CONFIG_DEBUG_MISC=y -+ -+# -+# Memory Debugging -+# -+# CONFIG_PAGE_EXTENSION is not set -+# CONFIG_DEBUG_PAGEALLOC is not set -+# CONFIG_PAGE_OWNER is not set -+# CONFIG_PAGE_POISONING is not set -+# CONFIG_DEBUG_PAGE_REF is not set -+# CONFIG_DEBUG_RODATA_TEST is not set -+CONFIG_ARCH_HAS_DEBUG_WX=y -+# CONFIG_DEBUG_WX is not set -+CONFIG_GENERIC_PTDUMP=y -+# CONFIG_PTDUMP_DEBUGFS is not set -+# CONFIG_DEBUG_OBJECTS is not set -+# CONFIG_SLUB_DEBUG_ON is not set -+# CONFIG_SLUB_STATS is not set -+CONFIG_HAVE_DEBUG_KMEMLEAK=y -+# CONFIG_DEBUG_KMEMLEAK is not set -+# CONFIG_DEBUG_STACK_USAGE is not set -+# CONFIG_SCHED_STACK_END_CHECK is not set -+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_VM_PGTABLE is not set -+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -+# CONFIG_DEBUG_VIRTUAL is not set -+# CONFIG_DEBUG_MEMORY_INIT is not set -+# CONFIG_DEBUG_PER_CPU_MAPS is not set -+CONFIG_HAVE_ARCH_KASAN=y -+CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y -+CONFIG_CC_HAS_KASAN_GENERIC=y -+# end of Memory Debugging -+ -+# CONFIG_DEBUG_SHIRQ is not set -+ -+# -+# Debug Oops, Lockups and Hangs -+# -+# CONFIG_PANIC_ON_OOPS is not set -+CONFIG_PANIC_ON_OOPS_VALUE=0 -+CONFIG_PANIC_TIMEOUT=0 -+# CONFIG_SOFTLOCKUP_DETECTOR is not set -+CONFIG_DETECT_HUNG_TASK=y -+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=90 -+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y -+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 -+# CONFIG_WQ_WATCHDOG is not set -+# CONFIG_TEST_LOCKUP is not set -+# end of Debug Oops, Lockups and Hangs -+ -+# -+# Scheduler Debugging -+# -+CONFIG_SCHED_DEBUG=y -+CONFIG_SCHED_INFO=y -+CONFIG_SCHEDSTATS=y -+# end of Scheduler Debugging -+ -+# CONFIG_DEBUG_TIMEKEEPING is not set -+ -+# -+# Lock Debugging (spinlocks, mutexes, etc...) -+# -+CONFIG_LOCK_DEBUGGING_SUPPORT=y -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_RT_MUTEXES is not set -+CONFIG_DEBUG_SPINLOCK=y -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -+# CONFIG_DEBUG_RWSEMS is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_DEBUG_ATOMIC_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_LOCK_TORTURE_TEST is not set -+# CONFIG_WW_MUTEX_SELFTEST is not set -+# CONFIG_SCF_TORTURE_TEST is not set -+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set -+# end of Lock Debugging (spinlocks, mutexes, etc...) -+ -+CONFIG_STACKTRACE=y -+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -+# CONFIG_DEBUG_KOBJECT is not set -+CONFIG_HAVE_DEBUG_BUGVERBOSE=y -+ -+# -+# Debug kernel data structures -+# -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_PLIST is not set -+# CONFIG_DEBUG_SG is not set -+# CONFIG_DEBUG_NOTIFIERS is not set -+# CONFIG_BUG_ON_DATA_CORRUPTION is not set -+# end of Debug kernel data structures -+ -+CONFIG_DEBUG_CREDENTIALS=y -+ -+# -+# RCU Debugging -+# -+# CONFIG_RCU_SCALE_TEST is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_RCU_REF_SCALE_TEST is not set -+CONFIG_RCU_CPU_STALL_TIMEOUT=60 -+CONFIG_RCU_TRACE=y -+# CONFIG_RCU_EQS_DEBUG is not set -+# end of RCU Debugging -+ -+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -+# CONFIG_LATENCYTOP is not set -+CONFIG_NOP_TRACER=y -+CONFIG_HAVE_FUNCTION_TRACER=y -+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -+CONFIG_HAVE_DYNAMIC_FTRACE=y -+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -+CONFIG_HAVE_C_RECORDMCOUNT=y -+CONFIG_TRACE_CLOCK=y -+CONFIG_RING_BUFFER=y -+CONFIG_EVENT_TRACING=y -+CONFIG_CONTEXT_SWITCH_TRACER=y -+CONFIG_TRACING=y -+CONFIG_GENERIC_TRACER=y -+CONFIG_TRACING_SUPPORT=y -+CONFIG_FTRACE=y -+# CONFIG_BOOTTIME_TRACING is not set -+CONFIG_FUNCTION_TRACER=y -+CONFIG_FUNCTION_GRAPH_TRACER=y -+CONFIG_DYNAMIC_FTRACE=y -+# CONFIG_FUNCTION_PROFILER is not set -+# CONFIG_STACK_TRACER is not set -+# CONFIG_IRQSOFF_TRACER is not set -+# CONFIG_SCHED_TRACER is not set -+# CONFIG_HWLAT_TRACER is not set -+# CONFIG_FTRACE_SYSCALLS is not set -+# CONFIG_TRACER_SNAPSHOT is not set -+CONFIG_BRANCH_PROFILE_NONE=y -+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -+# CONFIG_PROFILE_ALL_BRANCHES is not set -+CONFIG_BLK_DEV_IO_TRACE=y -+CONFIG_UPROBE_EVENTS=y -+CONFIG_DYNAMIC_EVENTS=y -+CONFIG_PROBE_EVENTS=y -+CONFIG_FTRACE_MCOUNT_RECORD=y -+# CONFIG_SYNTH_EVENTS is not set -+# CONFIG_HIST_TRIGGERS is not set -+# CONFIG_TRACE_EVENT_INJECT is not set -+# CONFIG_TRACEPOINT_BENCHMARK is not set -+# CONFIG_RING_BUFFER_BENCHMARK is not set -+# CONFIG_TRACE_EVAL_MAP_FILE is not set -+# CONFIG_FTRACE_STARTUP_TEST is not set -+# CONFIG_RING_BUFFER_STARTUP_TEST is not set -+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -+# CONFIG_SAMPLES is not set -+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -+CONFIG_STRICT_DEVMEM=y -+# CONFIG_IO_STRICT_DEVMEM is not set -+ -+# -+# arm64 Debugging -+# -+# CONFIG_PID_IN_CONTEXTIDR is not set -+# CONFIG_ARM64_RELOC_TEST is not set -+# CONFIG_CORESIGHT is not set -+# end of arm64 Debugging -+ -+# -+# Kernel Testing and Coverage -+# -+# CONFIG_KUNIT is not set -+# CONFIG_NOTIFIER_ERROR_INJECTION is not set -+# CONFIG_FAULT_INJECTION is not set -+CONFIG_ARCH_HAS_KCOV=y -+CONFIG_CC_HAS_SANCOV_TRACE_PC=y -+# CONFIG_KCOV is not set -+CONFIG_RUNTIME_TESTING_MENU=y -+CONFIG_LKDTM=y -+# CONFIG_TEST_LIST_SORT is not set -+# CONFIG_TEST_MIN_HEAP is not set -+# CONFIG_TEST_SORT is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_RBTREE_TEST is not set -+# CONFIG_REED_SOLOMON_TEST is not set -+# CONFIG_INTERVAL_TREE_TEST is not set -+# CONFIG_PERCPU_TEST is not set -+# CONFIG_ATOMIC64_SELFTEST is not set -+# CONFIG_TEST_HEXDUMP is not set -+# CONFIG_TEST_STRING_HELPERS is not set -+# CONFIG_TEST_STRSCPY is not set -+# CONFIG_TEST_KSTRTOX is not set -+# CONFIG_TEST_PRINTF is not set -+# CONFIG_TEST_BITMAP is not set -+# CONFIG_TEST_UUID is not set -+# CONFIG_TEST_XARRAY is not set -+# CONFIG_TEST_OVERFLOW is not set -+# CONFIG_TEST_RHASHTABLE is not set -+# CONFIG_TEST_HASH is not set -+# CONFIG_TEST_IDA is not set -+# CONFIG_TEST_LKM is not set -+# CONFIG_TEST_BITOPS is not set -+# CONFIG_TEST_VMALLOC is not set -+# CONFIG_TEST_USER_COPY is not set -+# CONFIG_TEST_BPF is not set -+# CONFIG_TEST_BLACKHOLE_DEV is not set -+# CONFIG_FIND_BIT_BENCHMARK is not set -+# CONFIG_TEST_FIRMWARE is not set -+# CONFIG_TEST_SYSCTL is not set -+# CONFIG_TEST_UDELAY is not set -+# CONFIG_TEST_STATIC_KEYS is not set -+# CONFIG_TEST_KMOD is not set -+# CONFIG_TEST_MEMCAT_P is not set -+# CONFIG_TEST_STACKINIT is not set -+# CONFIG_TEST_MEMINIT is not set -+# CONFIG_TEST_FREE_PAGES is not set -+# CONFIG_MEMTEST is not set -+# end of Kernel Testing and Coverage -+# end of Kernel hacking -+CONFIG_BLACKBOX=y -+CONFIG_BLACKBOX_LOG_ROOT_PATH="/data/log/bbox" -+CONFIG_BLACKBOX_LOG_PART_REPRESENTATIVE="/data/lost+found" -+CONFIG_BLACKBOX_ROCKCHIP=y -diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h -index ef5e60d6d..c7b9b859a 100644 ---- a/arch/arm64/include/asm/assembler.h -+++ b/arch/arm64/include/asm/assembler.h -@@ -106,13 +106,6 @@ - hint #20 - .endm - --/* -- * Clear Branch History instruction -- */ -- .macro clearbhb -- hint #22 -- .endm -- - /* - * Speculation barrier - */ -@@ -770,30 +763,4 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU - - #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */ - -- .macro __mitigate_spectre_bhb_loop tmp --#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY --alternative_cb spectre_bhb_patch_loop_iter -- mov \tmp, #32 // Patched to correct the immediate --alternative_cb_end --.Lspectre_bhb_loop\@: -- b . + 4 -- subs \tmp, \tmp, #1 -- b.ne .Lspectre_bhb_loop\@ -- sb --#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ -- .endm -- -- /* Save/restores x0-x3 to the stack */ -- .macro __mitigate_spectre_bhb_fw --#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY -- stp x0, x1, [sp, #-16]! -- stp x2, x3, [sp, #-16]! -- mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 --alternative_cb smccc_patch_fw_mitigation_conduit -- nop // Patched to SMC/HVC #0 --alternative_cb_end -- ldp x2, x3, [sp], #16 -- ldp x0, x1, [sp], #16 --#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ -- .endm - #endif /* __ASM_ASSEMBLER_H */ -diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h -index 37d891af8..a75f048c4 100644 ---- a/arch/arm64/include/asm/barrier.h -+++ b/arch/arm64/include/asm/barrier.h -@@ -45,9 +45,9 @@ - #define rmb() dsb(ld) - #define wmb() dsb(st) - --#define dma_mb() dmb(osh) --#define dma_rmb() dmb(oshld) --#define dma_wmb() dmb(oshst) -+#define dma_mb() dmb(sy) -+#define dma_rmb() dmb(ld) -+#define dma_wmb() dmb(st) - - /* - * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz -diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h -index 24ed6643d..7faae6ff3 100644 ---- a/arch/arm64/include/asm/cpu.h -+++ b/arch/arm64/include/asm/cpu.h -@@ -25,7 +25,6 @@ struct cpuinfo_arm64 { - u64 reg_id_aa64dfr1; - u64 reg_id_aa64isar0; - u64 reg_id_aa64isar1; -- u64 reg_id_aa64isar2; - u64 reg_id_aa64mmfr0; - u64 reg_id_aa64mmfr1; - u64 reg_id_aa64mmfr2; -diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h -index f42fd0a2e..e7d98997c 100644 ---- a/arch/arm64/include/asm/cpucaps.h -+++ b/arch/arm64/include/asm/cpucaps.h -@@ -66,8 +66,7 @@ - #define ARM64_HAS_TLB_RANGE 56 - #define ARM64_MTE 57 - #define ARM64_WORKAROUND_1508412 58 --#define ARM64_SPECTRE_BHB 59 - --#define ARM64_NCAPS 60 -+#define ARM64_NCAPS 59 - - #endif /* __ASM_CPUCAPS_H */ -diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h -index 423f9b40e..da250e474 100644 ---- a/arch/arm64/include/asm/cpufeature.h -+++ b/arch/arm64/include/asm/cpufeature.h -@@ -606,34 +606,6 @@ static inline bool cpu_supports_mixed_endian_el0(void) - return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); - } - --static inline bool supports_csv2p3(int scope) --{ -- u64 pfr0; -- u8 csv2_val; -- -- if (scope == SCOPE_LOCAL_CPU) -- pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1); -- else -- pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); -- -- csv2_val = cpuid_feature_extract_unsigned_field(pfr0, -- ID_AA64PFR0_CSV2_SHIFT); -- return csv2_val == 3; --} -- --static inline bool supports_clearbhb(int scope) --{ -- u64 isar2; -- -- if (scope == SCOPE_LOCAL_CPU) -- isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1); -- else -- isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); -- -- return cpuid_feature_extract_unsigned_field(isar2, -- ID_AA64ISAR2_CLEARBHB_SHIFT); --} -- - static inline bool system_supports_32bit_el0(void) - { - return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); -diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h -index 7a58d54ee..ef5b040de 100644 ---- a/arch/arm64/include/asm/cputype.h -+++ b/arch/arm64/include/asm/cputype.h -@@ -72,10 +72,6 @@ - #define ARM_CPU_PART_CORTEX_A76 0xD0B - #define ARM_CPU_PART_NEOVERSE_N1 0xD0C - #define ARM_CPU_PART_CORTEX_A77 0xD0D --#define ARM_CPU_PART_NEOVERSE_V1 0xD40 --#define ARM_CPU_PART_CORTEX_A78 0xD41 --#define ARM_CPU_PART_CORTEX_X1 0xD44 --#define ARM_CPU_PART_CORTEX_A78C 0xD4B - - #define APM_CPU_PART_POTENZA 0x000 - -@@ -113,10 +109,6 @@ - #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) - #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) - #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) --#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1) --#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) --#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) --#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) - #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) - #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) - #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) -diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h -index daff88288..433580020 100644 ---- a/arch/arm64/include/asm/fixmap.h -+++ b/arch/arm64/include/asm/fixmap.h -@@ -62,11 +62,9 @@ enum fixed_addresses { - #endif /* CONFIG_ACPI_APEI_GHES */ - - #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -- FIX_ENTRY_TRAMP_TEXT3, -- FIX_ENTRY_TRAMP_TEXT2, -- FIX_ENTRY_TRAMP_TEXT1, - FIX_ENTRY_TRAMP_DATA, --#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT1)) -+ FIX_ENTRY_TRAMP_TEXT, -+#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT)) - #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ - __end_of_permanent_fixed_addresses, - -diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h -index d45b42295..4b39293d0 100644 ---- a/arch/arm64/include/asm/insn.h -+++ b/arch/arm64/include/asm/insn.h -@@ -65,7 +65,6 @@ enum aarch64_insn_hint_cr_op { - AARCH64_INSN_HINT_PSB = 0x11 << 5, - AARCH64_INSN_HINT_TSB = 0x12 << 5, - AARCH64_INSN_HINT_CSDB = 0x14 << 5, -- AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5, - - AARCH64_INSN_HINT_BTI = 0x20 << 5, - AARCH64_INSN_HINT_BTIC = 0x22 << 5, -diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h -index fd172c41d..85f728b1d 100644 ---- a/arch/arm64/include/asm/io.h -+++ b/arch/arm64/include/asm/io.h -@@ -169,6 +169,7 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); - - #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) - #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) -+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS)) - - /* - * PCI configuration space mapping function. -diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h -index ada24a20a..044bb9e2c 100644 ---- a/arch/arm64/include/asm/kvm_asm.h -+++ b/arch/arm64/include/asm/kvm_asm.h -@@ -35,9 +35,6 @@ - #define KVM_VECTOR_PREAMBLE (2 * AARCH64_INSN_SIZE) - - #define __SMCCC_WORKAROUND_1_SMC_SZ 36 --#define __SMCCC_WORKAROUND_3_SMC_SZ 36 --#define __SPECTRE_BHB_LOOP_SZ 44 --#define __SPECTRE_BHB_CLEARBHB_SZ 12 - - #define KVM_HOST_SMCCC_ID(id) \ - ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ -@@ -202,11 +199,6 @@ extern void __vgic_v3_init_lrs(void); - extern u32 __kvm_get_mdcr_el2(void); - - extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ]; --extern char __smccc_workaround_3_smc[__SMCCC_WORKAROUND_3_SMC_SZ]; --extern char __spectre_bhb_loop_k8[__SPECTRE_BHB_LOOP_SZ]; --extern char __spectre_bhb_loop_k24[__SPECTRE_BHB_LOOP_SZ]; --extern char __spectre_bhb_loop_k32[__SPECTRE_BHB_LOOP_SZ]; --extern char __spectre_bhb_clearbhb[__SPECTRE_BHB_LOOP_SZ]; - - /* - * Obtain the PC-relative address of a kernel symbol -diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h -index 47dafd6ab..79c671d72 100644 ---- a/arch/arm64/include/asm/kvm_mmu.h -+++ b/arch/arm64/include/asm/kvm_mmu.h -@@ -123,7 +123,8 @@ void stage2_unmap_vm(struct kvm *kvm); - int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu); - void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu); - int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, -- phys_addr_t pa, unsigned long size, bool writable); -+ phys_addr_t pa, unsigned long size, bool writable, -+ enum kvm_pgtable_prot prot_device); - - int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); - -@@ -237,8 +238,7 @@ static inline void *kvm_get_hyp_vector(void) - void *vect = kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector)); - int slot = -1; - -- if ((cpus_have_const_cap(ARM64_SPECTRE_V2) || -- cpus_have_const_cap(ARM64_SPECTRE_BHB)) && data->template_start) { -+ if (cpus_have_const_cap(ARM64_SPECTRE_V2) && data->fn) { - vect = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs)); - slot = data->hyp_vectors_slot; - } -diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h -index 52ab38db0..46cad48db 100644 ---- a/arch/arm64/include/asm/kvm_pgtable.h -+++ b/arch/arm64/include/asm/kvm_pgtable.h -@@ -42,6 +42,7 @@ enum kvm_pgtable_prot { - KVM_PGTABLE_PROT_R = BIT(2), - - KVM_PGTABLE_PROT_DEVICE = BIT(3), -+ KVM_PGTABLE_PROT_DEVICE_NS = BIT(4), - }; - - #define PAGE_HYP (KVM_PGTABLE_PROT_R | KVM_PGTABLE_PROT_W) -diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h -index bc151b7dc..c7315862e 100644 ---- a/arch/arm64/include/asm/mmu.h -+++ b/arch/arm64/include/asm/mmu.h -@@ -67,12 +67,6 @@ typedef void (*bp_hardening_cb_t)(void); - struct bp_hardening_data { - int hyp_vectors_slot; - bp_hardening_cb_t fn; -- -- /* -- * template_start is only used by the BHB mitigation to identify the -- * hyp_vectors_slot sequence. -- */ -- const char *template_start; - }; - - DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); -diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h -index 9a65fb528..9c5a1047c 100644 ---- a/arch/arm64/include/asm/pgtable-prot.h -+++ b/arch/arm64/include/asm/pgtable-prot.h -@@ -57,6 +57,7 @@ extern bool arm64_use_ng_mappings; - #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) - #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) - #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) -+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) - #define PROT_NORMAL_TAGGED (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED)) - - #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) -diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h -index 10ffbc96a..de457cb9c 100644 ---- a/arch/arm64/include/asm/pgtable.h -+++ b/arch/arm64/include/asm/pgtable.h -@@ -482,6 +482,11 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) - #define pgprot_writecombine(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) -+#define pgprot_cached(prot) \ -+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \ -+ PTE_PXN | PTE_UXN) -+#define pgprot_cached_ns(prot) \ -+ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED) - #define pgprot_device(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) - #define pgprot_tagged(prot) \ -diff --git a/arch/arm64/include/asm/sections.h b/arch/arm64/include/asm/sections.h -index 6a45c26da..399416998 100644 ---- a/arch/arm64/include/asm/sections.h -+++ b/arch/arm64/include/asm/sections.h -@@ -19,9 +19,4 @@ extern char __irqentry_text_start[], __irqentry_text_end[]; - extern char __mmuoff_data_start[], __mmuoff_data_end[]; - extern char __entry_tramp_text_start[], __entry_tramp_text_end[]; - --static inline size_t entry_tramp_text_size(void) --{ -- return __entry_tramp_text_end - __entry_tramp_text_start; --} -- - #endif /* __ASM_SECTIONS_H */ -diff --git a/arch/arm64/include/asm/spectre.h b/arch/arm64/include/asm/spectre.h -index 4b3a5f050..fcdfbce30 100644 ---- a/arch/arm64/include/asm/spectre.h -+++ b/arch/arm64/include/asm/spectre.h -@@ -29,8 +29,4 @@ bool has_spectre_v4(const struct arm64_cpu_capabilities *cap, int scope); - void spectre_v4_enable_mitigation(const struct arm64_cpu_capabilities *__unused); - void spectre_v4_enable_task_mitigation(struct task_struct *tsk); - --enum mitigation_state arm64_get_spectre_bhb_state(void); --bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, int scope); --u8 spectre_bhb_loop_affected(int scope); --void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *__unused); - #endif /* __ASM_SPECTRE_H */ -diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h -index ecae3523d..801861d05 100644 ---- a/arch/arm64/include/asm/sysreg.h -+++ b/arch/arm64/include/asm/sysreg.h -@@ -175,7 +175,6 @@ - - #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) - #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) --#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) - - #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) - #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) -@@ -688,21 +687,6 @@ - #define ID_AA64ISAR1_GPI_NI 0x0 - #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 - --/* id_aa64isar2 */ --#define ID_AA64ISAR2_CLEARBHB_SHIFT 28 --#define ID_AA64ISAR2_RPRES_SHIFT 4 --#define ID_AA64ISAR2_WFXT_SHIFT 0 -- --#define ID_AA64ISAR2_RPRES_8BIT 0x0 --#define ID_AA64ISAR2_RPRES_12BIT 0x1 --/* -- * Value 0x1 has been removed from the architecture, and is -- * reserved, but has not yet been removed from the ARM ARM -- * as of ARM DDI 0487G.b. -- */ --#define ID_AA64ISAR2_WFXT_NI 0x0 --#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 -- - /* id_aa64pfr0 */ - #define ID_AA64PFR0_CSV3_SHIFT 60 - #define ID_AA64PFR0_CSV2_SHIFT 56 -@@ -802,7 +786,6 @@ - #endif - - /* id_aa64mmfr1 */ --#define ID_AA64MMFR1_ECBHB_SHIFT 60 - #define ID_AA64MMFR1_ETS_SHIFT 36 - #define ID_AA64MMFR1_TWED_SHIFT 32 - #define ID_AA64MMFR1_XNX_SHIFT 28 -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index 36f02892e..397b055ba 100644 ---- a/arch/arm64/include/asm/tlbflush.h -+++ b/arch/arm64/include/asm/tlbflush.h -@@ -16,6 +16,8 @@ - #include - #include - -+extern bool TKT340553_SW_WORKAROUND; -+ - /* - * Raw TLBI operations. - * -@@ -248,10 +250,17 @@ static inline void flush_tlb_mm(struct mm_struct *mm) - unsigned long asid; - - dsb(ishst); -- asid = __TLBI_VADDR(0, ASID(mm)); -- __tlbi(aside1is, asid); -- __tlbi_user(aside1is, asid); -- dsb(ish); -+ if (TKT340553_SW_WORKAROUND) { -+ /* Flush the entire TLB */ -+ __tlbi(vmalle1is); -+ dsb(ish); -+ isb(); -+ } else { -+ asid = __TLBI_VADDR(0, ASID(mm)); -+ __tlbi(aside1is, asid); -+ __tlbi_user(aside1is, asid); -+ dsb(ish); -+ } - } - - static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, -@@ -260,9 +269,16 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, - unsigned long addr; - - dsb(ishst); -- addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); -- __tlbi(vale1is, addr); -- __tlbi_user(vale1is, addr); -+ if (TKT340553_SW_WORKAROUND) { -+ /* Flush the entire TLB */ -+ __tlbi(vmalle1is); -+ dsb(ish); -+ isb(); -+ } else { -+ addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); -+ __tlbi(vale1is, addr); -+ __tlbi_user(vale1is, addr); -+ } - } - - static inline void flush_tlb_page(struct vm_area_struct *vma, -@@ -307,6 +323,14 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, - dsb(ishst); - asid = ASID(vma->vm_mm); - -+ if (TKT340553_SW_WORKAROUND) { -+ /* Flush the entire TLB and exit */ -+ __tlbi(vmalle1is); -+ dsb(ish); -+ isb(); -+ return; -+ } -+ - /* - * When the CPU does not support TLB range operations, flush the TLB - * entries one by one at the granularity of 'stride'. If the the TLB -@@ -357,6 +381,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, - } - scale++; - } -+ - dsb(ish); - } - -@@ -375,7 +400,8 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end - { - unsigned long addr; - -- if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) { -+ if (((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) -+ || (TKT340553_SW_WORKAROUND)) { - flush_tlb_all(); - return; - } -@@ -399,7 +425,11 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) - unsigned long addr = __TLBI_VADDR(kaddr, 0); - - dsb(ishst); -- __tlbi(vaae1is, addr); -+ if (TKT340553_SW_WORKAROUND) -+ /* Flush the entire TLB */ -+ __tlbi(vmalle1is); -+ else -+ __tlbi(vaae1is, addr); - dsb(ish); - isb(); - } -diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h -index 385a189f7..af003a185 100644 ---- a/arch/arm64/include/asm/uaccess.h -+++ b/arch/arm64/include/asm/uaccess.h -@@ -10,6 +10,9 @@ - #include - #include - #include -+#include -+#include -+#include - - /* - * User space memory access functions -@@ -17,6 +20,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -24,6 +28,7 @@ - #include - #include - -+#define get_ds() (KERNEL_DS) - #define get_fs() (current_thread_info()->addr_limit) - - static inline void set_fs(mm_segment_t fs) -diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h -index 6069be50b..765638f64 100644 ---- a/arch/arm64/include/asm/virt.h -+++ b/arch/arm64/include/asm/virt.h -@@ -62,6 +62,7 @@ - */ - extern u32 __boot_cpu_mode[2]; - -+extern char __hyp_stub_vectors[]; - void __hyp_set_vectors(phys_addr_t phys_vector_base); - void __hyp_reset_vectors(void); - -diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h -index 531ff62e8..1c17c3a24 100644 ---- a/arch/arm64/include/uapi/asm/kvm.h -+++ b/arch/arm64/include/uapi/asm/kvm.h -@@ -273,11 +273,6 @@ struct kvm_vcpu_events { - #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 - #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) - --#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) --#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 --#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 --#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 -- - /* SVE registers */ - #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) - -diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c -index 533559c7d..cafaf0da0 100644 ---- a/arch/arm64/kernel/cpu_errata.c -+++ b/arch/arm64/kernel/cpu_errata.c -@@ -473,13 +473,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { - .matches = has_spectre_v4, - .cpu_enable = spectre_v4_enable_mitigation, - }, -- { -- .desc = "Spectre-BHB", -- .capability = ARM64_SPECTRE_BHB, -- .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, -- .matches = is_spectre_bhb_affected, -- .cpu_enable = spectre_bhb_enable_mitigation, -- }, - #ifdef CONFIG_ARM64_ERRATUM_1418040 - { - .desc = "ARM erratum 1418040", -diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c -index ec8ed4fc3..ccce3c946 100644 ---- a/arch/arm64/kernel/cpufeature.c -+++ b/arch/arm64/kernel/cpufeature.c -@@ -65,13 +65,11 @@ - #include - #include - #include --#include - #include - #include - #include - #include - #include -- - #include - #include - #include -@@ -81,7 +79,6 @@ - #include - #include - #include --#include - #include - - /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ -@@ -107,8 +104,6 @@ DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); - bool arm64_use_ng_mappings = false; - EXPORT_SYMBOL(arm64_use_ng_mappings); - --DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; -- - /* - * Flag to indicate if we have computed the system wide - * capabilities based on the boot time active CPUs. This -@@ -210,11 +205,6 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { - ARM64_FTR_END, - }; - --static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { -- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), -- ARM64_FTR_END, --}; -- - static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), -@@ -606,7 +596,6 @@ static const struct __ftr_reg_entry { - /* Op1 = 0, CRn = 0, CRm = 6 */ - ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), - ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), -- ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), - - /* Op1 = 0, CRn = 0, CRm = 7 */ - ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), -@@ -821,9 +810,22 @@ init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *ca - } - } - -+bool TKT340553_SW_WORKAROUND; - static void __init init_cpu_hwcaps_indirect_list(void) - { - init_cpu_hwcaps_indirect_list_from_array(arm64_features); -+#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE -+#if defined(CONFIG_ARM64_ERRATUM_826319) || \ -+ defined(CONFIG_ARM64_ERRATUM_827319) || \ -+ defined(CONFIG_ARM64_ERRATUM_824069) -+ if (TKT340553_SW_WORKAROUND) { -+ struct midr_range *midr_range_list = -+ (struct midr_range *)(arm64_errata[0].midr_range_list); -+ -+ midr_range_list[0].rv_max = MIDR_CPU_VAR_REV(0, 4); -+ } -+#endif -+#endif - init_cpu_hwcaps_indirect_list_from_array(arm64_errata); - } - -@@ -841,7 +843,6 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) - init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); - init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); - init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); -- init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); - init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); - init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); - init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); -@@ -1070,8 +1071,6 @@ void update_cpu_features(int cpu, - info->reg_id_aa64isar0, boot->reg_id_aa64isar0); - taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, - info->reg_id_aa64isar1, boot->reg_id_aa64isar1); -- taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, -- info->reg_id_aa64isar2, boot->reg_id_aa64isar2); - - /* - * Differing PARange support is fine as long as all peripherals and -@@ -1171,7 +1170,6 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) - read_sysreg_case(SYS_ID_AA64MMFR2_EL1); - read_sysreg_case(SYS_ID_AA64ISAR0_EL1); - read_sysreg_case(SYS_ID_AA64ISAR1_EL1); -- read_sysreg_case(SYS_ID_AA64ISAR2_EL1); - - read_sysreg_case(SYS_CNTFRQ_EL0); - read_sysreg_case(SYS_CTR_EL0); -@@ -1417,12 +1415,6 @@ kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) - - int cpu = smp_processor_id(); - -- if (__this_cpu_read(this_cpu_vector) == vectors) { -- const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); -- -- __this_cpu_write(this_cpu_vector, v); -- } -- - /* - * We don't need to rewrite the page-tables if either we've done - * it already or we have KASLR enabled and therefore have not -diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c -index 61204ba07..77605aec2 100644 ---- a/arch/arm64/kernel/cpuinfo.c -+++ b/arch/arm64/kernel/cpuinfo.c -@@ -364,7 +364,6 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) - info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); - info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); - info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); -- info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); - info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); - info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); - info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); -diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S -index d5bc1dbdd..fe83d6d67 100644 ---- a/arch/arm64/kernel/entry.S -+++ b/arch/arm64/kernel/entry.S -@@ -62,21 +62,18 @@ - - .macro kernel_ventry, el, label, regsize = 64 - .align 7 --.Lventry_start\@: -+#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - .if \el == 0 -- /* -- * This must be the first instruction of the EL0 vector entries. It is -- * skipped by the trampoline vectors, to trigger the cleanup. -- */ -- b .Lskip_tramp_vectors_cleanup\@ -+alternative_if ARM64_UNMAP_KERNEL_AT_EL0 - .if \regsize == 64 - mrs x30, tpidrro_el0 - msr tpidrro_el0, xzr - .else - mov x30, xzr - .endif --.Lskip_tramp_vectors_cleanup\@: -+alternative_else_nop_endif - .endif -+#endif - - sub sp, sp, #S_FRAME_SIZE - #ifdef CONFIG_VMAP_STACK -@@ -123,15 +120,11 @@ - mrs x0, tpidrro_el0 - #endif - b el\()\el\()_\label --.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? - .endm - -- .macro tramp_alias, dst, sym, tmp -+ .macro tramp_alias, dst, sym - mov_q \dst, TRAMP_VALIAS -- adr_l \tmp, \sym -- add \dst, \dst, \tmp -- adr_l \tmp, .entry.tramp.text -- sub \dst, \dst, \tmp -+ add \dst, \dst, #(\sym - .entry.tramp.text) - .endm - - /* -@@ -148,7 +141,7 @@ alternative_cb_end - tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ - mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 - mov w1, #\state --alternative_cb smccc_patch_fw_mitigation_conduit -+alternative_cb spectre_v4_patch_fw_mitigation_conduit - nop // Patched to SMC/HVC #0 - alternative_cb_end - .L__asm_ssbd_skip\@: -@@ -358,26 +351,21 @@ alternative_else_nop_endif - ldp x24, x25, [sp, #16 * 12] - ldp x26, x27, [sp, #16 * 13] - ldp x28, x29, [sp, #16 * 14] -- -- .if \el == 0 --alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 - ldr lr, [sp, #S_LR] - add sp, sp, #S_FRAME_SIZE // restore sp -- eret --alternative_else_nop_endif -+ -+ .if \el == 0 -+alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 - #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - bne 4f -- msr far_el1, x29 -- tramp_alias x30, tramp_exit_native, x29 -+ msr far_el1, x30 -+ tramp_alias x30, tramp_exit_native - br x30 - 4: -- tramp_alias x30, tramp_exit_compat, x29 -+ tramp_alias x30, tramp_exit_compat - br x30 - #endif - .else -- ldr lr, [sp, #S_LR] -- add sp, sp, #S_FRAME_SIZE // restore sp -- - /* Ensure any device/NC reads complete */ - alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 - -@@ -776,6 +764,12 @@ SYM_CODE_END(ret_to_user) - - .popsection // .entry.text - -+#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -+/* -+ * Exception vectors trampoline. -+ */ -+ .pushsection ".entry.tramp.text", "ax" -+ - // Move from tramp_pg_dir to swapper_pg_dir - .macro tramp_map_kernel, tmp - mrs \tmp, ttbr1_el1 -@@ -809,47 +803,12 @@ alternative_else_nop_endif - */ - .endm - -- .macro tramp_data_page dst -- adr_l \dst, .entry.tramp.text -- sub \dst, \dst, PAGE_SIZE -- .endm -- -- .macro tramp_data_read_var dst, var --#ifdef CONFIG_RANDOMIZE_BASE -- tramp_data_page \dst -- add \dst, \dst, #:lo12:__entry_tramp_data_\var -- ldr \dst, [\dst] --#else -- ldr \dst, =\var --#endif -- .endm -- --#define BHB_MITIGATION_NONE 0 --#define BHB_MITIGATION_LOOP 1 --#define BHB_MITIGATION_FW 2 --#define BHB_MITIGATION_INSN 3 -- -- .macro tramp_ventry, vector_start, regsize, kpti, bhb -+ .macro tramp_ventry, regsize = 64 - .align 7 - 1: - .if \regsize == 64 - msr tpidrro_el0, x30 // Restored in kernel_ventry - .endif -- -- .if \bhb == BHB_MITIGATION_LOOP -- /* -- * This sequence must appear before the first indirect branch. i.e. the -- * ret out of tramp_ventry. It appears here because x30 is free. -- */ -- __mitigate_spectre_bhb_loop x30 -- .endif // \bhb == BHB_MITIGATION_LOOP -- -- .if \bhb == BHB_MITIGATION_INSN -- clearbhb -- isb -- .endif // \bhb == BHB_MITIGATION_INSN -- -- .if \kpti == 1 - /* - * Defend against branch aliasing attacks by pushing a dummy - * entry onto the return stack and using a RET instruction to -@@ -859,75 +818,46 @@ alternative_else_nop_endif - b . - 2: - tramp_map_kernel x30 -+#ifdef CONFIG_RANDOMIZE_BASE -+ adr x30, tramp_vectors + PAGE_SIZE - alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 -- tramp_data_read_var x30, vectors -+ ldr x30, [x30] -+#else -+ ldr x30, =vectors -+#endif - alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM -- prfm plil1strm, [x30, #(1b - \vector_start)] -+ prfm plil1strm, [x30, #(1b - tramp_vectors)] - alternative_else_nop_endif -- - msr vbar_el1, x30 -+ add x30, x30, #(1b - tramp_vectors) - isb -- .else -- ldr x30, =vectors -- .endif // \kpti == 1 -- -- .if \bhb == BHB_MITIGATION_FW -- /* -- * The firmware sequence must appear before the first indirect branch. -- * i.e. the ret out of tramp_ventry. But it also needs the stack to be -- * mapped to save/restore the registers the SMC clobbers. -- */ -- __mitigate_spectre_bhb_fw -- .endif // \bhb == BHB_MITIGATION_FW -- -- add x30, x30, #(1b - \vector_start + 4) - ret --.org 1b + 128 // Did we overflow the ventry slot? - .endm - - .macro tramp_exit, regsize = 64 -- tramp_data_read_var x30, this_cpu_vector -- this_cpu_offset x29 -- ldr x30, [x30, x29] -- -+ adr x30, tramp_vectors - msr vbar_el1, x30 -- ldr lr, [sp, #S_LR] -- tramp_unmap_kernel x29 -+ tramp_unmap_kernel x30 - .if \regsize == 64 -- mrs x29, far_el1 -+ mrs x30, far_el1 - .endif -- add sp, sp, #S_FRAME_SIZE // restore sp - eret - sb - .endm - -- .macro generate_tramp_vector, kpti, bhb --.Lvector_start\@: -+ .align 11 -+SYM_CODE_START_NOALIGN(tramp_vectors) - .space 0x400 - -- .rept 4 -- tramp_ventry .Lvector_start\@, 64, \kpti, \bhb -- .endr -- .rept 4 -- tramp_ventry .Lvector_start\@, 32, \kpti, \bhb -- .endr -- .endm -+ tramp_ventry -+ tramp_ventry -+ tramp_ventry -+ tramp_ventry - --#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 --/* -- * Exception vectors trampoline. -- * The order must match __bp_harden_el1_vectors and the -- * arm64_bp_harden_el1_vectors enum. -- */ -- .pushsection ".entry.tramp.text", "ax" -- .align 11 --SYM_CODE_START_NOALIGN(tramp_vectors) --#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY -- generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP -- generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW -- generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN --#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ -- generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE -+ tramp_ventry 32 -+ tramp_ventry 32 -+ tramp_ventry 32 -+ tramp_ventry 32 - SYM_CODE_END(tramp_vectors) - - SYM_CODE_START(tramp_exit_native) -@@ -944,56 +874,12 @@ SYM_CODE_END(tramp_exit_compat) - .pushsection ".rodata", "a" - .align PAGE_SHIFT - SYM_DATA_START(__entry_tramp_data_start) --__entry_tramp_data_vectors: - .quad vectors --#ifdef CONFIG_ARM_SDE_INTERFACE --__entry_tramp_data___sdei_asm_handler: -- .quad __sdei_asm_handler --#endif /* CONFIG_ARM_SDE_INTERFACE */ --__entry_tramp_data_this_cpu_vector: -- .quad this_cpu_vector - SYM_DATA_END(__entry_tramp_data_start) - .popsection // .rodata - #endif /* CONFIG_RANDOMIZE_BASE */ - #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ - --/* -- * Exception vectors for spectre mitigations on entry from EL1 when -- * kpti is not in use. -- */ -- .macro generate_el1_vector, bhb --.Lvector_start\@: -- kernel_ventry 1, sync_invalid // Synchronous EL1t -- kernel_ventry 1, irq_invalid // IRQ EL1t -- kernel_ventry 1, fiq_invalid // FIQ EL1t -- kernel_ventry 1, error_invalid // Error EL1t -- -- kernel_ventry 1, sync // Synchronous EL1h -- kernel_ventry 1, irq // IRQ EL1h -- kernel_ventry 1, fiq_invalid // FIQ EL1h -- kernel_ventry 1, error // Error EL1h -- -- .rept 4 -- tramp_ventry .Lvector_start\@, 64, 0, \bhb -- .endr -- .rept 4 -- tramp_ventry .Lvector_start\@, 32, 0, \bhb -- .endr -- .endm -- --/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ -- .pushsection ".entry.text", "ax" -- .align 11 --SYM_CODE_START(__bp_harden_el1_vectors) --#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY -- generate_el1_vector bhb=BHB_MITIGATION_LOOP -- generate_el1_vector bhb=BHB_MITIGATION_FW -- generate_el1_vector bhb=BHB_MITIGATION_INSN --#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ --SYM_CODE_END(__bp_harden_el1_vectors) -- .popsection -- -- - /* - * Register switch for AArch64. The callee-saved registers need to be saved - * and restored. On entry: -@@ -1083,7 +969,13 @@ SYM_CODE_START(__sdei_asm_entry_trampoline) - */ - 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] - -- tramp_data_read_var x4, __sdei_asm_handler -+#ifdef CONFIG_RANDOMIZE_BASE -+ adr x4, tramp_vectors + PAGE_SIZE -+ add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler -+ ldr x4, [x4] -+#else -+ ldr x4, =__sdei_asm_handler -+#endif - br x4 - SYM_CODE_END(__sdei_asm_entry_trampoline) - NOKPROBE(__sdei_asm_entry_trampoline) -@@ -1106,6 +998,13 @@ SYM_CODE_END(__sdei_asm_exit_trampoline) - NOKPROBE(__sdei_asm_exit_trampoline) - .ltorg - .popsection // .entry.tramp.text -+#ifdef CONFIG_RANDOMIZE_BASE -+.pushsection ".rodata", "a" -+SYM_DATA_START(__sdei_asm_trampoline_next_handler) -+ .quad __sdei_asm_handler -+SYM_DATA_END(__sdei_asm_trampoline_next_handler) -+.popsection // .rodata -+#endif /* CONFIG_RANDOMIZE_BASE */ - #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ - - /* -@@ -1213,7 +1112,7 @@ alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 - alternative_else_nop_endif - - #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -- tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3 -+ tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline - br x5 - #endif - SYM_CODE_END(__sdei_asm_handler) -diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S -index 160f5881a..a055e28be 100644 ---- a/arch/arm64/kernel/hyp-stub.S -+++ b/arch/arm64/kernel/hyp-stub.S -@@ -10,6 +10,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -42,6 +43,7 @@ SYM_CODE_START(__hyp_stub_vectors) - ventry el1_fiq_invalid // FIQ 32-bit EL1 - ventry el1_error_invalid // Error 32-bit EL1 - SYM_CODE_END(__hyp_stub_vectors) -+EXPORT_SYMBOL_GPL(__hyp_stub_vectors) - - .align 11 - -diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c -index 1006ed2d7..6fabfa0a4 100644 ---- a/arch/arm64/kernel/pci.c -+++ b/arch/arm64/kernel/pci.c -@@ -13,11 +13,14 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - -+#include "../../../drivers/pci/pcie/portdrv.h" -+ - #ifdef CONFIG_ACPI - /* - * Try to assign the IRQ number when probing a new device -@@ -31,6 +34,47 @@ int pcibios_alloc_irq(struct pci_dev *dev) - } - #endif - -+/* -+ * Check device tree if the service interrupts are there -+ */ -+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask) -+{ -+ int ret, count = 0; -+ struct device_node *np = NULL; -+ -+ if (dev->bus->dev.of_node) -+ np = dev->bus->dev.of_node; -+ -+ if (np == NULL) -+ return 0; -+ -+ if (!IS_ENABLED(CONFIG_OF_IRQ)) -+ return 0; -+ -+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode, -+ * request irq for aer -+ */ -+ if (mask & PCIE_PORT_SERVICE_AER) { -+ ret = of_irq_get_byname(np, "aer"); -+ if (ret > 0) { -+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; -+ count++; -+ } -+ } -+ -+ if (mask & PCIE_PORT_SERVICE_PME) { -+ ret = of_irq_get_byname(np, "pme"); -+ if (ret > 0) { -+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; -+ count++; -+ } -+ } -+ -+ /* TODO: add more service interrupts if there it is in the device tree*/ -+ -+ return count; -+} -+ - /* - * raw_pci_read/write - Platform-specific PCI config space access. - */ -diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c -index 5d5f2fa19..f6e4e3737 100644 ---- a/arch/arm64/kernel/proton-pack.c -+++ b/arch/arm64/kernel/proton-pack.c -@@ -18,18 +18,14 @@ - */ - - #include --#include - #include - #include - #include - #include - #include - --#include - #include - #include --#include --#include - - /* - * We try to ensure that the mitigation state can never change as the result of -@@ -98,51 +94,14 @@ static bool spectre_v2_mitigations_off(void) - return ret; - } - --static const char *get_bhb_affected_string(enum mitigation_state bhb_state) --{ -- switch (bhb_state) { -- case SPECTRE_UNAFFECTED: -- return ""; -- default: -- case SPECTRE_VULNERABLE: -- return ", but not BHB"; -- case SPECTRE_MITIGATED: -- return ", BHB"; -- } --} -- --static bool _unprivileged_ebpf_enabled(void) --{ --#ifdef CONFIG_BPF_SYSCALL -- return !sysctl_unprivileged_bpf_disabled; --#else -- return false; --#endif --} -- - ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, - char *buf) - { -- enum mitigation_state bhb_state = arm64_get_spectre_bhb_state(); -- const char *bhb_str = get_bhb_affected_string(bhb_state); -- const char *v2_str = "Branch predictor hardening"; -- - switch (spectre_v2_state) { - case SPECTRE_UNAFFECTED: -- if (bhb_state == SPECTRE_UNAFFECTED) -- return sprintf(buf, "Not affected\n"); -- -- /* -- * Platforms affected by Spectre-BHB can't report -- * "Not affected" for Spectre-v2. -- */ -- v2_str = "CSV2"; -- fallthrough; -+ return sprintf(buf, "Not affected\n"); - case SPECTRE_MITIGATED: -- if (bhb_state == SPECTRE_MITIGATED && _unprivileged_ebpf_enabled()) -- return sprintf(buf, "Vulnerable: Unprivileged eBPF enabled\n"); -- -- return sprintf(buf, "Mitigation: %s%s\n", v2_str, bhb_str); -+ return sprintf(buf, "Mitigation: Branch predictor hardening\n"); - case SPECTRE_VULNERABLE: - fallthrough; - default: -@@ -236,9 +195,9 @@ static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, - __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); - } - --static DEFINE_RAW_SPINLOCK(bp_lock); - static void install_bp_hardening_cb(bp_hardening_cb_t fn) - { -+ static DEFINE_RAW_SPINLOCK(bp_lock); - int cpu, slot = -1; - const char *hyp_vecs_start = __smccc_workaround_1_smc; - const char *hyp_vecs_end = __smccc_workaround_1_smc + -@@ -269,7 +228,6 @@ static void install_bp_hardening_cb(bp_hardening_cb_t fn) - - __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); - __this_cpu_write(bp_hardening_data.fn, fn); -- __this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start); - raw_spin_unlock(&bp_lock); - } - #else -@@ -613,9 +571,9 @@ void __init spectre_v4_patch_fw_mitigation_enable(struct alt_instr *alt, - * Patch a NOP in the Spectre-v4 mitigation code with an SMC/HVC instruction - * to call into firmware to adjust the mitigation state. - */ --void __init smccc_patch_fw_mitigation_conduit(struct alt_instr *alt, -- __le32 *origptr, -- __le32 *updptr, int nr_inst) -+void __init spectre_v4_patch_fw_mitigation_conduit(struct alt_instr *alt, -+ __le32 *origptr, -+ __le32 *updptr, int nr_inst) - { - u32 insn; - -@@ -829,305 +787,3 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) - return -ENODEV; - } - } -- --/* -- * Spectre BHB. -- * -- * A CPU is either: -- * - Mitigated by a branchy loop a CPU specific number of times, and listed -- * in our "loop mitigated list". -- * - Mitigated in software by the firmware Spectre v2 call. -- * - Has the ClearBHB instruction to perform the mitigation. -- * - Has the 'Exception Clears Branch History Buffer' (ECBHB) feature, so no -- * software mitigation in the vectors is needed. -- * - Has CSV2.3, so is unaffected. -- */ --static enum mitigation_state spectre_bhb_state; -- --enum mitigation_state arm64_get_spectre_bhb_state(void) --{ -- return spectre_bhb_state; --} -- --/* -- * This must be called with SCOPE_LOCAL_CPU for each type of CPU, before any -- * SCOPE_SYSTEM call will give the right answer. -- */ --u8 spectre_bhb_loop_affected(int scope) --{ -- u8 k = 0; -- static u8 max_bhb_k; -- -- if (scope == SCOPE_LOCAL_CPU) { -- static const struct midr_range spectre_bhb_k32_list[] = { -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), -- MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), -- MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), -- {}, -- }; -- static const struct midr_range spectre_bhb_k24_list[] = { -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), -- MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), -- {}, -- }; -- static const struct midr_range spectre_bhb_k8_list[] = { -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), -- {}, -- }; -- -- if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) -- k = 32; -- else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) -- k = 24; -- else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list)) -- k = 8; -- -- max_bhb_k = max(max_bhb_k, k); -- } else { -- k = max_bhb_k; -- } -- -- return k; --} -- --static enum mitigation_state spectre_bhb_get_cpu_fw_mitigation_state(void) --{ -- int ret; -- struct arm_smccc_res res; -- -- arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, -- ARM_SMCCC_ARCH_WORKAROUND_3, &res); -- -- ret = res.a0; -- switch (ret) { -- case SMCCC_RET_SUCCESS: -- return SPECTRE_MITIGATED; -- case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED: -- return SPECTRE_UNAFFECTED; -- default: -- fallthrough; -- case SMCCC_RET_NOT_SUPPORTED: -- return SPECTRE_VULNERABLE; -- } --} -- --static bool is_spectre_bhb_fw_affected(int scope) --{ -- static bool system_affected; -- enum mitigation_state fw_state; -- bool has_smccc = arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE; -- static const struct midr_range spectre_bhb_firmware_mitigated_list[] = { -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), -- MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), -- {}, -- }; -- bool cpu_in_list = is_midr_in_range_list(read_cpuid_id(), -- spectre_bhb_firmware_mitigated_list); -- -- if (scope != SCOPE_LOCAL_CPU) -- return system_affected; -- -- fw_state = spectre_bhb_get_cpu_fw_mitigation_state(); -- if (cpu_in_list || (has_smccc && fw_state == SPECTRE_MITIGATED)) { -- system_affected = true; -- return true; -- } -- -- return false; --} -- --static bool supports_ecbhb(int scope) --{ -- u64 mmfr1; -- -- if (scope == SCOPE_LOCAL_CPU) -- mmfr1 = read_sysreg_s(SYS_ID_AA64MMFR1_EL1); -- else -- mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); -- -- return cpuid_feature_extract_unsigned_field(mmfr1, -- ID_AA64MMFR1_ECBHB_SHIFT); --} -- --bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, -- int scope) --{ -- WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); -- -- if (supports_csv2p3(scope)) -- return false; -- -- if (supports_clearbhb(scope)) -- return true; -- -- if (spectre_bhb_loop_affected(scope)) -- return true; -- -- if (is_spectre_bhb_fw_affected(scope)) -- return true; -- -- return false; --} -- --static void this_cpu_set_vectors(enum arm64_bp_harden_el1_vectors slot) --{ -- const char *v = arm64_get_bp_hardening_vector(slot); -- -- if (slot < 0) -- return; -- -- __this_cpu_write(this_cpu_vector, v); -- -- /* -- * When KPTI is in use, the vectors are switched when exiting to -- * user-space. -- */ -- if (arm64_kernel_unmapped_at_el0()) -- return; -- -- write_sysreg(v, vbar_el1); -- isb(); --} -- --#ifdef CONFIG_KVM --static int kvm_bhb_get_vecs_size(const char *start) --{ -- if (start == __smccc_workaround_3_smc) -- return __SMCCC_WORKAROUND_3_SMC_SZ; -- else if (start == __spectre_bhb_loop_k8 || -- start == __spectre_bhb_loop_k24 || -- start == __spectre_bhb_loop_k32) -- return __SPECTRE_BHB_LOOP_SZ; -- else if (start == __spectre_bhb_clearbhb) -- return __SPECTRE_BHB_CLEARBHB_SZ; -- -- return 0; --} -- --static void kvm_setup_bhb_slot(const char *hyp_vecs_start) --{ -- int cpu, slot = -1, size; -- const char *hyp_vecs_end; -- -- if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) -- return; -- -- size = kvm_bhb_get_vecs_size(hyp_vecs_start); -- if (WARN_ON_ONCE(!hyp_vecs_start || !size)) -- return; -- hyp_vecs_end = hyp_vecs_start + size; -- -- raw_spin_lock(&bp_lock); -- for_each_possible_cpu(cpu) { -- if (per_cpu(bp_hardening_data.template_start, cpu) == hyp_vecs_start) { -- slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); -- break; -- } -- } -- -- if (slot == -1) { -- slot = atomic_inc_return(&arm64_el2_vector_last_slot); -- BUG_ON(slot >= BP_HARDEN_EL2_SLOTS); -- __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); -- } -- -- __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); -- __this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start); -- raw_spin_unlock(&bp_lock); --} --#else --#define __smccc_workaround_3_smc NULL --#define __spectre_bhb_loop_k8 NULL --#define __spectre_bhb_loop_k24 NULL --#define __spectre_bhb_loop_k32 NULL --#define __spectre_bhb_clearbhb NULL -- --static void kvm_setup_bhb_slot(const char *hyp_vecs_start) { } --#endif /* CONFIG_KVM */ -- --void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *entry) --{ -- enum mitigation_state fw_state, state = SPECTRE_VULNERABLE; -- -- if (!is_spectre_bhb_affected(entry, SCOPE_LOCAL_CPU)) -- return; -- -- if (arm64_get_spectre_v2_state() == SPECTRE_VULNERABLE) { -- /* No point mitigating Spectre-BHB alone. */ -- } else if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY)) { -- pr_info_once("spectre-bhb mitigation disabled by compile time option\n"); -- } else if (cpu_mitigations_off()) { -- pr_info_once("spectre-bhb mitigation disabled by command line option\n"); -- } else if (supports_ecbhb(SCOPE_LOCAL_CPU)) { -- state = SPECTRE_MITIGATED; -- } else if (supports_clearbhb(SCOPE_LOCAL_CPU)) { -- kvm_setup_bhb_slot(__spectre_bhb_clearbhb); -- this_cpu_set_vectors(EL1_VECTOR_BHB_CLEAR_INSN); -- -- state = SPECTRE_MITIGATED; -- } else if (spectre_bhb_loop_affected(SCOPE_LOCAL_CPU)) { -- switch (spectre_bhb_loop_affected(SCOPE_SYSTEM)) { -- case 8: -- kvm_setup_bhb_slot(__spectre_bhb_loop_k8); -- break; -- case 24: -- kvm_setup_bhb_slot(__spectre_bhb_loop_k24); -- break; -- case 32: -- kvm_setup_bhb_slot(__spectre_bhb_loop_k32); -- break; -- default: -- WARN_ON_ONCE(1); -- } -- this_cpu_set_vectors(EL1_VECTOR_BHB_LOOP); -- -- state = SPECTRE_MITIGATED; -- } else if (is_spectre_bhb_fw_affected(SCOPE_LOCAL_CPU)) { -- fw_state = spectre_bhb_get_cpu_fw_mitigation_state(); -- if (fw_state == SPECTRE_MITIGATED) { -- kvm_setup_bhb_slot(__smccc_workaround_3_smc); -- this_cpu_set_vectors(EL1_VECTOR_BHB_FW); -- -- state = SPECTRE_MITIGATED; -- } -- } -- -- update_mitigation_state(&spectre_bhb_state, state); --} -- --/* Patched to correct the immediate */ --void noinstr spectre_bhb_patch_loop_iter(struct alt_instr *alt, -- __le32 *origptr, __le32 *updptr, int nr_inst) --{ -- u8 rd; -- u32 insn; -- u16 loop_count = spectre_bhb_loop_affected(SCOPE_SYSTEM); -- -- BUG_ON(nr_inst != 1); /* MOV -> MOV */ -- -- if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY)) -- return; -- -- insn = le32_to_cpu(*origptr); -- rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn); -- insn = aarch64_insn_gen_movewide(rd, loop_count, 0, -- AARCH64_INSN_VARIANT_64BIT, -- AARCH64_INSN_MOVEWIDE_ZERO); -- *updptr++ = cpu_to_le32(insn); --} -- --#ifdef CONFIG_BPF_SYSCALL --#define EBPF_WARN "Unprivileged eBPF is enabled, data leaks possible via Spectre v2 BHB attacks!\n" --void unpriv_ebpf_notify(int new_state) --{ -- if (spectre_v2_state == SPECTRE_VULNERABLE || -- spectre_bhb_state != SPECTRE_MITIGATED) -- return; -- -- if (!new_state) -- pr_err("WARNING: %s", EBPF_WARN); --} --#endif -diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c -index feee5a3cd..547eaf158 100644 ---- a/arch/arm64/kernel/smp.c -+++ b/arch/arm64/kernel/smp.c -@@ -948,10 +948,19 @@ static irqreturn_t ipi_handler(int irq, void *data) - return IRQ_HANDLED; - } - -+#ifdef CONFIG_IMX_GPCV2 -+extern void imx_gpcv2_raise_softirq(const struct cpumask *mask, -+ unsigned int irq); -+#endif -+ - static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) - { - trace_ipi_raise(target, ipi_types[ipinr]); - __ipi_send_mask(ipi_desc[ipinr], target); -+ -+#ifdef CONFIG_IMX_GPCV2 -+ imx_gpcv2_raise_softirq(target, ipinr); -+#endif - } - - static void ipi_setup(int cpu) -diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c -index 2059d8f43..3c2a03e19 100644 ---- a/arch/arm64/kernel/traps.c -+++ b/arch/arm64/kernel/traps.c -@@ -447,6 +447,29 @@ NOKPROBE_SYMBOL(do_ptrauth_fault); - uaccess_ttbr0_disable(); \ - } - -+#define __user_cache_maint_ivau(insn, address, res) \ -+ do { \ -+ if (address >= user_addr_max()) { \ -+ res = -EFAULT; \ -+ } else { \ -+ uaccess_ttbr0_enable(); \ -+ asm volatile ( \ -+ "1: " insn "\n" \ -+ " mov %w0, #0\n" \ -+ "2:\n" \ -+ " .pushsection .fixup,\"ax\"\n" \ -+ " .align 2\n" \ -+ "3: mov %w0, %w2\n" \ -+ " b 2b\n" \ -+ " .popsection\n" \ -+ _ASM_EXTABLE(1b, 3b) \ -+ : "=r" (res) \ -+ : "r" (address), "i" (-EFAULT)); \ -+ uaccess_ttbr0_disable(); \ -+ } \ -+ } while (0) -+ -+extern bool TKT340553_SW_WORKAROUND; - static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) - { - unsigned long address; -@@ -473,7 +496,10 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) - __user_cache_maint("dc civac", address, ret); - break; - case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ -- __user_cache_maint("ic ivau", address, ret); -+ if (TKT340553_SW_WORKAROUND) -+ __user_cache_maint_ivau("ic ialluis", address, ret); -+ else -+ __user_cache_maint("ic ivau", address, ret); - break; - default: - force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); -diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S -index 71f4b5f24..30c102978 100644 ---- a/arch/arm64/kernel/vmlinux.lds.S -+++ b/arch/arm64/kernel/vmlinux.lds.S -@@ -299,7 +299,7 @@ ASSERT(__hibernate_exit_text_end - (__hibernate_exit_text_start & ~(SZ_4K - 1)) - <= SZ_4K, "Hibernate exit text too big or misaligned") - #endif - #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 --ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) <= 3*PAGE_SIZE, -+ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) == PAGE_SIZE, - "Entry trampoline text too big") - #endif - /* -diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c -index 4d63fcd75..5bc978be8 100644 ---- a/arch/arm64/kvm/arm.c -+++ b/arch/arm64/kvm/arm.c -@@ -1337,8 +1337,7 @@ static int kvm_map_vectors(void) - * !SV2 + HEL2 -> allocate one vector slot and use exec mapping - * SV2 + HEL2 -> use hardened vectors and use exec mapping - */ -- if (cpus_have_const_cap(ARM64_SPECTRE_V2) || -- cpus_have_const_cap(ARM64_SPECTRE_BHB)) { -+ if (cpus_have_const_cap(ARM64_SPECTRE_V2)) { - __kvm_bp_vect_base = kvm_ksym_ref(__bp_harden_hyp_vecs); - __kvm_bp_vect_base = kern_hyp_va(__kvm_bp_vect_base); - } -diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S -index 99204c41f..0a5b36eb5 100644 ---- a/arch/arm64/kvm/hyp/hyp-entry.S -+++ b/arch/arm64/kvm/hyp/hyp-entry.S -@@ -61,10 +61,6 @@ el1_sync: // Guest trapped into EL2 - /* ARM_SMCCC_ARCH_WORKAROUND_2 handling */ - eor w1, w1, #(ARM_SMCCC_ARCH_WORKAROUND_1 ^ \ - ARM_SMCCC_ARCH_WORKAROUND_2) -- cbz w1, wa_epilogue -- -- eor w1, w1, #(ARM_SMCCC_ARCH_WORKAROUND_2 ^ \ -- ARM_SMCCC_ARCH_WORKAROUND_3) - cbnz w1, el1_trap - - wa_epilogue: -diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c -index 4d99d07c6..c2acd41e6 100644 ---- a/arch/arm64/kvm/hyp/pgtable.c -+++ b/arch/arm64/kvm/hyp/pgtable.c -@@ -443,7 +443,10 @@ static int stage2_map_set_prot_attr(enum kvm_pgtable_prot prot, - bool device = prot & KVM_PGTABLE_PROT_DEVICE; - kvm_pte_t attr = device ? PAGE_S2_MEMATTR(DEVICE_nGnRE) : - PAGE_S2_MEMATTR(NORMAL); -- u32 sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS; -+ u32 sh = 0; -+ -+ if (!(prot & KVM_PGTABLE_PROT_DEVICE_NS)) -+ sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS; - - if (!(prot & KVM_PGTABLE_PROT_X)) - attr |= KVM_PTE_LEAF_ATTR_HI_S2_XN; -@@ -836,7 +839,15 @@ static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, - if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pte)) - return 0; - -- stage2_flush_dcache(kvm_pte_follow(pte), kvm_granule_size(level)); -+ if (pfn_valid(__phys_to_pfn(kvm_pte_to_phys(pte)))) { -+ stage2_flush_dcache(kvm_pte_follow(pte), kvm_granule_size(level)); -+ } else { -+ void __iomem *va = ioremap_cache_ns(kvm_pte_to_phys(pte), PAGE_SIZE); -+ -+ stage2_flush_dcache(va, kvm_granule_size(level)); -+ iounmap(va); -+ } -+ - return 0; - } - -diff --git a/arch/arm64/kvm/hyp/smccc_wa.S b/arch/arm64/kvm/hyp/smccc_wa.S -index 533b0aa73..b0441dbdf 100644 ---- a/arch/arm64/kvm/hyp/smccc_wa.S -+++ b/arch/arm64/kvm/hyp/smccc_wa.S -@@ -30,78 +30,3 @@ SYM_DATA_START(__smccc_workaround_1_smc) - 1: .org __smccc_workaround_1_smc + __SMCCC_WORKAROUND_1_SMC_SZ - .org 1b - SYM_DATA_END(__smccc_workaround_1_smc) -- -- .global __smccc_workaround_3_smc --SYM_DATA_START(__smccc_workaround_3_smc) -- esb -- sub sp, sp, #(8 * 4) -- stp x2, x3, [sp, #(8 * 0)] -- stp x0, x1, [sp, #(8 * 2)] -- mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 -- smc #0 -- ldp x2, x3, [sp, #(8 * 0)] -- ldp x0, x1, [sp, #(8 * 2)] -- add sp, sp, #(8 * 4) --1: .org __smccc_workaround_3_smc + __SMCCC_WORKAROUND_3_SMC_SZ -- .org 1b --SYM_DATA_END(__smccc_workaround_3_smc) -- -- .global __spectre_bhb_loop_k8 --SYM_DATA_START(__spectre_bhb_loop_k8) -- esb -- sub sp, sp, #(8 * 2) -- stp x0, x1, [sp, #(8 * 0)] -- mov x0, #8 --2: b . + 4 -- subs x0, x0, #1 -- b.ne 2b -- dsb nsh -- isb -- ldp x0, x1, [sp, #(8 * 0)] -- add sp, sp, #(8 * 2) --1: .org __spectre_bhb_loop_k8 + __SPECTRE_BHB_LOOP_SZ -- .org 1b --SYM_DATA_END(__spectre_bhb_loop_k8) -- -- .global __spectre_bhb_loop_k24 --SYM_DATA_START(__spectre_bhb_loop_k24) -- esb -- sub sp, sp, #(8 * 2) -- stp x0, x1, [sp, #(8 * 0)] -- mov x0, #24 --2: b . + 4 -- subs x0, x0, #1 -- b.ne 2b -- dsb nsh -- isb -- ldp x0, x1, [sp, #(8 * 0)] -- add sp, sp, #(8 * 2) --1: .org __spectre_bhb_loop_k24 + __SPECTRE_BHB_LOOP_SZ -- .org 1b --SYM_DATA_END(__spectre_bhb_loop_k24) -- -- .global __spectre_bhb_loop_k32 --SYM_DATA_START(__spectre_bhb_loop_k32) -- esb -- sub sp, sp, #(8 * 2) -- stp x0, x1, [sp, #(8 * 0)] -- mov x0, #32 --2: b . + 4 -- subs x0, x0, #1 -- b.ne 2b -- dsb nsh -- isb -- ldp x0, x1, [sp, #(8 * 0)] -- add sp, sp, #(8 * 2) --1: .org __spectre_bhb_loop_k32 + __SPECTRE_BHB_LOOP_SZ -- .org 1b --SYM_DATA_END(__spectre_bhb_loop_k32) -- -- .global __spectre_bhb_clearbhb --SYM_DATA_START(__spectre_bhb_clearbhb) -- esb -- clearbhb -- isb --1: .org __spectre_bhb_clearbhb + __SPECTRE_BHB_CLEARBHB_SZ -- .org 1b --SYM_DATA_END(__spectre_bhb_clearbhb) -diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c -index 532e687f6..62546e20b 100644 ---- a/arch/arm64/kvm/hyp/vhe/switch.c -+++ b/arch/arm64/kvm/hyp/vhe/switch.c -@@ -10,7 +10,6 @@ - #include - #include - #include --#include - #include - - #include -@@ -26,7 +25,6 @@ - #include - #include - #include --#include - - const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n"; - -@@ -72,7 +70,7 @@ NOKPROBE_SYMBOL(__activate_traps); - - static void __deactivate_traps(struct kvm_vcpu *vcpu) - { -- const char *host_vectors = vectors; -+ extern char vectors[]; /* kernel exception vectors */ - - ___deactivate_traps(vcpu); - -@@ -86,10 +84,7 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) - asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); - - write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); -- -- if (!arm64_kernel_unmapped_at_el0()) -- host_vectors = __this_cpu_read(this_cpu_vector); -- write_sysreg(host_vectors, vbar_el1); -+ write_sysreg(vectors, vbar_el1); - } - NOKPROBE_SYMBOL(__deactivate_traps); - -diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c -index bc111a1af..25ea4ecb6 100644 ---- a/arch/arm64/kvm/hypercalls.c -+++ b/arch/arm64/kvm/hypercalls.c -@@ -58,18 +58,6 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) - break; - } - break; -- case ARM_SMCCC_ARCH_WORKAROUND_3: -- switch (arm64_get_spectre_bhb_state()) { -- case SPECTRE_VULNERABLE: -- break; -- case SPECTRE_MITIGATED: -- val = SMCCC_RET_SUCCESS; -- break; -- case SPECTRE_UNAFFECTED: -- val = SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED; -- break; -- } -- break; - case ARM_SMCCC_HV_PV_TIME_FEATURES: - val = SMCCC_RET_SUCCESS; - break; -diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c -index 26068456e..2758177fd 100644 ---- a/arch/arm64/kvm/mmu.c -+++ b/arch/arm64/kvm/mmu.c -@@ -497,13 +497,14 @@ void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu) - * @writable: Whether or not to create a writable mapping - */ - int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, -- phys_addr_t pa, unsigned long size, bool writable) -+ phys_addr_t pa, unsigned long size, bool writable, -+ enum kvm_pgtable_prot prot_device) - { - phys_addr_t addr; - int ret = 0; - struct kvm_mmu_memory_cache cache = { 0, __GFP_ZERO, NULL, }; - struct kvm_pgtable *pgt = kvm->arch.mmu.pgt; -- enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_DEVICE | -+ enum kvm_pgtable_prot prot = prot_device | - KVM_PGTABLE_PROT_R | - (writable ? KVM_PGTABLE_PROT_W : 0); - -@@ -738,6 +739,23 @@ transparent_hugepage_adjust(struct kvm_memory_slot *memslot, - return PAGE_SIZE; - } - -+static enum kvm_pgtable_prot stage1_to_stage2_pgprot(pgprot_t prot) -+{ -+ switch (pgprot_val(prot) & PTE_ATTRINDX_MASK) { -+ case PTE_ATTRINDX(MT_DEVICE_nGnRE): -+ case PTE_ATTRINDX(MT_DEVICE_nGnRnE): -+ case PTE_ATTRINDX(MT_DEVICE_GRE): -+ return KVM_PGTABLE_PROT_DEVICE; -+ case PTE_ATTRINDX(MT_NORMAL_NC): -+ case PTE_ATTRINDX(MT_NORMAL): -+ return (pgprot_val(prot) & PTE_SHARED) -+ ? 0 -+ : KVM_PGTABLE_PROT_DEVICE_NS; -+ } -+ -+ return KVM_PGTABLE_PROT_DEVICE; -+} -+ - static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, - struct kvm_memory_slot *memslot, unsigned long hva, - unsigned long fault_status) -@@ -893,10 +911,18 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, - invalidate_icache_guest_page(pfn, vma_pagesize); - } - -- if (device) -- prot |= KVM_PGTABLE_PROT_DEVICE; -- else if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) -+ if (device) { -+ pte_t *pte; -+ spinlock_t *ptl; -+ enum kvm_pgtable_prot prot_us; -+ -+ pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl); -+ prot_us = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte))); -+ pte_unmap_unlock(pte, ptl); -+ prot |= prot_us; -+ } else if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { - prot |= KVM_PGTABLE_PROT_X; -+ } - - /* - * Under the premise of getting a FSC_PERM fault, we just need to relax -@@ -1342,6 +1368,9 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, - gpa_t gpa = mem->guest_phys_addr + - (vm_start - mem->userspace_addr); - phys_addr_t pa; -+ enum kvm_pgtable_prot prot; -+ pte_t *pte; -+ spinlock_t *ptl; - - pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT; - pa += vm_start - vma->vm_start; -@@ -1352,9 +1381,13 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, - goto out; - } - -+ pte = get_locked_pte(current->mm, mem->userspace_addr, &ptl); -+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte))); -+ pte_unmap_unlock(pte, ptl); -+ - ret = kvm_phys_addr_ioremap(kvm, gpa, pa, - vm_end - vm_start, -- writable); -+ writable, prot); - if (ret) - break; - } -diff --git a/arch/arm64/kvm/psci.c b/arch/arm64/kvm/psci.c -index 20ba5136a..db4056ecc 100644 ---- a/arch/arm64/kvm/psci.c -+++ b/arch/arm64/kvm/psci.c -@@ -397,7 +397,7 @@ int kvm_psci_call(struct kvm_vcpu *vcpu) - - int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) - { -- return 4; /* PSCI version and three workaround registers */ -+ return 3; /* PSCI version and two workaround registers */ - } - - int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) -@@ -411,9 +411,6 @@ int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) - if (put_user(KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, uindices++)) - return -EFAULT; - -- if (put_user(KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3, uindices++)) -- return -EFAULT; -- - return 0; - } - -@@ -453,17 +450,6 @@ static int get_kernel_wa_level(u64 regid) - case SPECTRE_VULNERABLE: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - } -- break; -- case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3: -- switch (arm64_get_spectre_bhb_state()) { -- case SPECTRE_VULNERABLE: -- return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL; -- case SPECTRE_MITIGATED: -- return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL; -- case SPECTRE_UNAFFECTED: -- return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED; -- } -- return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL; - } - - return -EINVAL; -@@ -480,7 +466,6 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) - break; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: -- case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3: - val = get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; - break; - default: -@@ -526,7 +511,6 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) - } - - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: -- case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3: - if (val & ~KVM_REG_FEATURE_LEVEL_MASK) - return -EINVAL; - -diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c -index 835fa036b..568f11e23 100644 ---- a/arch/arm64/kvm/sys_regs.c -+++ b/arch/arm64/kvm/sys_regs.c -@@ -1517,7 +1517,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { - /* CRm=6 */ - ID_SANITISED(ID_AA64ISAR0_EL1), - ID_SANITISED(ID_AA64ISAR1_EL1), -- ID_SANITISED(ID_AA64ISAR2_EL1), -+ ID_UNALLOCATED(6,2), - ID_UNALLOCATED(6,3), - ID_UNALLOCATED(6,4), - ID_UNALLOCATED(6,5), -diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c -index b9518f94b..7e6ae628d 100644 ---- a/arch/arm64/kvm/vgic/vgic-its.c -+++ b/arch/arm64/kvm/vgic/vgic-its.c -@@ -248,7 +248,7 @@ static struct its_ite *find_ite(struct vgic_its *its, u32 device_id, - #define GIC_LPI_OFFSET 8192 - - #define VITS_TYPER_IDBITS 16 --#define VITS_TYPER_DEVBITS 16 -+#define VITS_TYPER_DEVBITS 17 - #define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1) - #define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1) - -diff --git a/arch/arm64/kvm/vgic/vgic-v2.c b/arch/arm64/kvm/vgic/vgic-v2.c -index ebf53a4e1..014864551 100644 ---- a/arch/arm64/kvm/vgic/vgic-v2.c -+++ b/arch/arm64/kvm/vgic/vgic-v2.c -@@ -341,7 +341,8 @@ int vgic_v2_map_resources(struct kvm *kvm) - if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) { - ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base, - kvm_vgic_global_state.vcpu_base, -- KVM_VGIC_V2_CPU_SIZE, true); -+ KVM_VGIC_V2_CPU_SIZE, true, -+ KVM_PGTABLE_PROT_DEVICE); - if (ret) { - kvm_err("Unable to remap VGIC CPU to VCPU\n"); - goto out; -diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c -index 93e87b287..abd29ac4c 100644 ---- a/arch/arm64/mm/dma-mapping.c -+++ b/arch/arm64/mm/dma-mapping.c -@@ -57,3 +57,4 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - dev->dma_ops = &xen_swiotlb_dma_ops; - #endif - } -+EXPORT_SYMBOL(arch_setup_dma_ops); -diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c -index c0a7f0d90..5909a1ae4 100644 ---- a/arch/arm64/mm/init.c -+++ b/arch/arm64/mm/init.c -@@ -403,10 +403,10 @@ void __init arm64_memblock_init(void) - initrd_end = initrd_start + phys_initrd_size; - } - -- early_init_fdt_scan_reserved_mem(); -- - reserve_elfcorehdr(); - -+ early_init_fdt_scan_reserved_mem(); -+ - high_memory = __va(memblock_end_of_DRAM() - 1) + 1; - } - -diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c -index 104408d4c..58dc93e56 100644 ---- a/arch/arm64/mm/mmu.c -+++ b/arch/arm64/mm/mmu.c -@@ -592,8 +592,6 @@ early_param("rodata", parse_rodata); - #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - static int __init map_entry_trampoline(void) - { -- int i; -- - pgprot_t prot = rodata_enabled ? PAGE_KERNEL_ROX : PAGE_KERNEL_EXEC; - phys_addr_t pa_start = __pa_symbol(__entry_tramp_text_start); - -@@ -602,15 +600,11 @@ static int __init map_entry_trampoline(void) - - /* Map only the text into the trampoline page table */ - memset(tramp_pg_dir, 0, PGD_SIZE); -- __create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, -- entry_tramp_text_size(), prot, -- __pgd_pgtable_alloc, NO_BLOCK_MAPPINGS); -+ __create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, PAGE_SIZE, -+ prot, __pgd_pgtable_alloc, 0); - - /* Map both the text and data into the kernel page table */ -- for (i = 0; i < DIV_ROUND_UP(entry_tramp_text_size(), PAGE_SIZE); i++) -- __set_fixmap(FIX_ENTRY_TRAMP_TEXT1 - i, -- pa_start + i * PAGE_SIZE, prot); -- -+ __set_fixmap(FIX_ENTRY_TRAMP_TEXT, pa_start, prot); - if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { - extern char __entry_tramp_data_start[]; - diff --git a/imx8mm/kernel/patches/002_imx_8m_mini_certs_crypto_modify_content.patch b/imx8mm/kernel/patches/002_imx_8m_mini_certs_crypto_modify_content.patch deleted file mode 100644 index de00814..0000000 --- a/imx8mm/kernel/patches/002_imx_8m_mini_certs_crypto_modify_content.patch +++ /dev/null @@ -1,1365 +0,0 @@ -commit af1fde456682ff60db8aab79d0c3c37ede6f87e9 -Author: zhaoxc0502 -Date: Wed Jun 1 11:53:51 2022 +0800 - - modify kernel certs & crypto for imx8m mini - - Change-Id: I20682d0566bb84a83126b04991b9ca1bf7ddb6f5 - -diff --git a/block/blk-map.c b/block/blk-map.c -index ede73f4f7..61e94a5a6 100644 ---- a/block/blk-map.c -+++ b/block/blk-map.c -@@ -488,7 +488,7 @@ static struct bio *bio_copy_kern(struct request_queue *q, void *data, - if (bytes > len) - bytes = len; - -- page = alloc_page(q->bounce_gfp | __GFP_ZERO | gfp_mask); -+ page = alloc_page(q->bounce_gfp | gfp_mask); - if (!page) - goto cleanup; - -@@ -668,6 +668,12 @@ int blk_rq_unmap_user(struct bio *bio) - } - EXPORT_SYMBOL(blk_rq_unmap_user); - -+#ifdef CONFIG_AHCI_IMX -+extern void *sg_io_buffer_hack; -+#else -+#define sg_io_buffer_hack NULL -+#endif -+ - /** - * blk_rq_map_kern - map kernel data to a request, for passthrough requests - * @q: request queue where request should be inserted -@@ -694,7 +700,12 @@ int blk_rq_map_kern(struct request_queue *q, struct request *rq, void *kbuf, - if (!len || !kbuf) - return -EINVAL; - -+#ifdef CONFIG_AHCI_IMX -+ if ((kbuf != sg_io_buffer_hack) && (!blk_rq_aligned(q, addr, len) -+ || object_is_on_stack(kbuf))) -+#else - if (!blk_rq_aligned(q, addr, len) || object_is_on_stack(kbuf)) -+#endif - bio = bio_copy_kern(q, kbuf, len, gfp_mask, reading); - else - bio = bio_map_kern(q, kbuf, len, gfp_mask); -diff --git a/block/scsi_ioctl.c b/block/scsi_ioctl.c -index c9f009cc0..bc596b8f9 100644 ---- a/block/scsi_ioctl.c -+++ b/block/scsi_ioctl.c -@@ -243,6 +243,12 @@ static int blk_fill_sghdr_rq(struct request_queue *q, struct request *rq, - return 0; - } - -+#ifdef CONFIG_AHCI_IMX -+extern void *sg_io_buffer_hack; -+#else -+#define sg_io_buffer_hack NULL -+#endif -+ - static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, - struct bio *bio) - { -@@ -272,7 +278,12 @@ static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, - ret = -EFAULT; - } - -- r = blk_rq_unmap_user(bio); -+ if (sg_io_buffer_hack && !hdr->iovec_count) -+ r = copy_to_user(hdr->dxferp, sg_io_buffer_hack, -+ hdr->dxfer_len); -+ else -+ r = blk_rq_unmap_user(bio); -+ - if (!ret) - ret = r; - -@@ -296,6 +307,9 @@ static int sg_io(struct request_queue *q, struct gendisk *bd_disk, - if (hdr->dxfer_len > (queue_max_hw_sectors(q) << 9)) - return -EIO; - -+ if (sg_io_buffer_hack && hdr->dxfer_len > 0x10000) -+ return -EIO; -+ - if (hdr->dxfer_len) - switch (hdr->dxfer_direction) { - default: -@@ -341,9 +355,14 @@ static int sg_io(struct request_queue *q, struct gendisk *bd_disk, - - ret = blk_rq_map_user_iov(q, rq, NULL, &i, GFP_KERNEL); - kfree(iov); -- } else if (hdr->dxfer_len) -- ret = blk_rq_map_user(q, rq, NULL, hdr->dxferp, hdr->dxfer_len, -- GFP_KERNEL); -+ } else if (hdr->dxfer_len) { -+ if (sg_io_buffer_hack) -+ ret = blk_rq_map_kern(q, rq, sg_io_buffer_hack, -+ hdr->dxfer_len, GFP_KERNEL); -+ else -+ ret = blk_rq_map_user(q, rq, NULL, hdr->dxferp, -+ hdr->dxfer_len, GFP_KERNEL); -+ } - - if (ret) - goto out_free_cdb; -diff --git a/crypto/Kconfig b/crypto/Kconfig -index 774adc984..5b623f6f0 100644 ---- a/crypto/Kconfig -+++ b/crypto/Kconfig -@@ -365,6 +365,26 @@ config CRYPTO_ECHAINIV - a sequence number xored with a salt. This is the default - algorithm for CBC. - -+config CRYPTO_TLS -+ tristate "TLS support" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_HASH -+ select CRYPTO_NULL -+ select CRYPTO_AUTHENC -+ help -+ Support for TLS 1.0 record encryption and decryption -+ -+ This module adds support for encryption/decryption of TLS 1.0 frames -+ using blockcipher algorithms. The name of the resulting algorithm is -+ "tls10(hmac(),cbc())". By default, the generic base -+ algorithms are used (e.g. aes-generic, sha1-generic), but hardware -+ accelerated versions will be used automatically if available. -+ -+ User-space applications (OpenSSL, GnuTLS) can offload TLS 1.0 -+ operations through AF_ALG or cryptodev interfaces -+ - comment "Block modes" - - config CRYPTO_CBC -diff --git a/crypto/Makefile b/crypto/Makefile -index b279483fb..802d9a5e0 100644 ---- a/crypto/Makefile -+++ b/crypto/Makefile -@@ -151,6 +151,7 @@ obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o - obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o - obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o - obj-$(CONFIG_CRYPTO_LZO) += lzo.o lzo-rle.o -+obj-$(CONFIG_CRYPTO_TLS) += tls.o - obj-$(CONFIG_CRYPTO_LZ4) += lz4.o - obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o - obj-$(CONFIG_CRYPTO_XXHASH) += xxhash_generic.o -diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c -index 8609174e0..c0f5c91b1 100644 ---- a/crypto/tcrypt.c -+++ b/crypto/tcrypt.c -@@ -72,9 +72,8 @@ static const char *check[] = { - "cast6", "arc4", "michael_mic", "deflate", "crc32c", "tea", "xtea", - "khazad", "wp512", "wp384", "wp256", "tnepres", "xeta", "fcrypt", - "camellia", "seed", "salsa20", "rmd128", "rmd160", "rmd256", "rmd320", -- "lzo", "lzo-rle", "cts", "sha3-224", "sha3-256", "sha3-384", -- "sha3-512", "streebog256", "streebog512", -- NULL -+ "lzo", "lzo-rle", "cts", "zlib", "sha3-224", "sha3-256", "sha3-384", -+ "sha3-512", "streebog256", "streebog512", "rsa", NULL - }; - - static u32 block_sizes[] = { 16, 64, 256, 1024, 1472, 8192, 0 }; -@@ -258,7 +257,7 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, - unsigned int i, j, iv_len; - const char *key; - const char *e; -- void *assoc; -+ void *assoc, *assoc_out; - u32 *b_size; - char *iv; - int ret; -@@ -378,6 +377,8 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, - - assoc = cur->axbuf[0]; - memset(assoc, 0xff, aad_size); -+ assoc_out = cur->axbuf[1]; -+ memset(assoc_out, 0xff, aad_size); - - sg_init_aead(cur->sg, cur->xbuf, - *b_size + (enc ? 0 : authsize), -@@ -385,7 +386,7 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, - - sg_init_aead(cur->sgout, cur->xoutbuf, - *b_size + (enc ? authsize : 0), -- assoc, aad_size); -+ assoc_out, aad_size); - - aead_request_set_ad(cur->req, aad_size); - -@@ -403,6 +404,9 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs, - ret); - break; - } -+ -+ memset(assoc, 0xff, aad_size); -+ memset(assoc_out, 0xff, aad_size); - } - - aead_request_set_crypt(cur->req, cur->sg, -@@ -529,7 +533,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, - struct scatterlist *sg; - struct scatterlist *sgout; - const char *e; -- void *assoc; -+ void *assoc, *assoc_out; - char *iv; - char *xbuf[XBUFSIZE]; - char *xoutbuf[XBUFSIZE]; -@@ -592,6 +596,8 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, - do { - assoc = axbuf[0]; - memset(assoc, 0xff, aad_size); -+ assoc_out = axbuf[1]; -+ memset(assoc_out, 0xff, aad_size); - - if ((*keysize + *b_size) > TVMEMSIZE * PAGE_SIZE) { - pr_err("template (%u) too big for tvmem (%lu)\n", -@@ -631,7 +637,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, - assoc, aad_size); - - sg_init_aead(sgout, xoutbuf, -- *b_size + (enc ? authsize : 0), assoc, -+ *b_size + (enc ? authsize : 0), assoc_out, - aad_size); - - aead_request_set_ad(req, aad_size); -@@ -653,6 +659,9 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, - ret); - break; - } -+ -+ memset(assoc, 0xff, aad_size); -+ memset(assoc_out, 0xff, aad_size); - } - - aead_request_set_crypt(req, sg, sgout, -@@ -1984,6 +1993,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) - ret += tcrypt_test("hmac(streebog512)"); - break; - -+ case 117: -+ ret += tcrypt_test("rsa"); -+ break; -+ - case 150: - ret += tcrypt_test("ansi_cprng"); - break; -@@ -2050,6 +2063,9 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) - ret += tcrypt_test("cbc(sm4)"); - ret += tcrypt_test("ctr(sm4)"); - break; -+ case 192: -+ ret += tcrypt_test("tls10(hmac(sha1),cbc(aes))"); -+ break; - case 200: - test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0, - speed_template_16_24_32); -diff --git a/crypto/testmgr.c b/crypto/testmgr.c -index a64a639ed..d2bc27682 100644 ---- a/crypto/testmgr.c -+++ b/crypto/testmgr.c -@@ -126,6 +126,13 @@ struct drbg_test_suite { - unsigned int count; - }; - -+struct tls_test_suite { -+ struct { -+ struct tls_testvec *vecs; -+ unsigned int count; -+ } enc, dec; -+}; -+ - struct akcipher_test_suite { - const struct akcipher_testvec *vecs; - unsigned int count; -@@ -150,6 +157,7 @@ struct alg_test_desc { - struct hash_test_suite hash; - struct cprng_test_suite cprng; - struct drbg_test_suite drbg; -+ struct tls_test_suite tls; - struct akcipher_test_suite akcipher; - struct kpp_test_suite kpp; - } suite; -@@ -2555,6 +2563,227 @@ static int test_aead(const char *driver, int enc, - return 0; - } - -+static int __test_tls(struct crypto_aead *tfm, int enc, -+ struct tls_testvec *template, unsigned int tcount, -+ const bool diff_dst) -+{ -+ const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm)); -+ unsigned int i, k, authsize; -+ char *q; -+ struct aead_request *req; -+ struct scatterlist *sg; -+ struct scatterlist *sgout; -+ const char *e, *d; -+ struct crypto_wait wait; -+ void *input; -+ void *output; -+ void *assoc; -+ char *iv; -+ char *key; -+ char *xbuf[XBUFSIZE]; -+ char *xoutbuf[XBUFSIZE]; -+ char *axbuf[XBUFSIZE]; -+ int ret = -ENOMEM; -+ -+ if (testmgr_alloc_buf(xbuf)) -+ goto out_noxbuf; -+ -+ if (diff_dst && testmgr_alloc_buf(xoutbuf)) -+ goto out_nooutbuf; -+ -+ if (testmgr_alloc_buf(axbuf)) -+ goto out_noaxbuf; -+ -+ iv = kzalloc(MAX_IVLEN, GFP_KERNEL); -+ if (!iv) -+ goto out_noiv; -+ -+ key = kzalloc(MAX_KEYLEN, GFP_KERNEL); -+ if (!key) -+ goto out_nokey; -+ -+ sg = kmalloc(sizeof(*sg) * 8 * (diff_dst ? 2 : 1), GFP_KERNEL); -+ if (!sg) -+ goto out_nosg; -+ -+ sgout = sg + 8; -+ -+ d = diff_dst ? "-ddst" : ""; -+ e = enc ? "encryption" : "decryption"; -+ -+ crypto_init_wait(&wait); -+ -+ req = aead_request_alloc(tfm, GFP_KERNEL); -+ if (!req) { -+ pr_err("alg: tls%s: Failed to allocate request for %s\n", -+ d, algo); -+ goto out; -+ } -+ -+ aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, -+ crypto_req_done, &wait); -+ -+ for (i = 0; i < tcount; i++) { -+ input = xbuf[0]; -+ assoc = axbuf[0]; -+ -+ ret = -EINVAL; -+ if (WARN_ON(template[i].ilen > PAGE_SIZE || -+ template[i].alen > PAGE_SIZE)) -+ goto out; -+ -+ memcpy(assoc, template[i].assoc, template[i].alen); -+ memcpy(input, template[i].input, template[i].ilen); -+ -+ if (template[i].iv) -+ memcpy(iv, template[i].iv, MAX_IVLEN); -+ else -+ memset(iv, 0, MAX_IVLEN); -+ -+ crypto_aead_clear_flags(tfm, ~0); -+ -+ if (template[i].klen > MAX_KEYLEN) { -+ pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n", -+ d, i, algo, template[i].klen, MAX_KEYLEN); -+ ret = -EINVAL; -+ goto out; -+ } -+ memcpy(key, template[i].key, template[i].klen); -+ -+ ret = crypto_aead_setkey(tfm, key, template[i].klen); -+ if ((!ret) == template[i].fail) { -+ pr_err("alg: tls%s: setkey failed on test %d for %s: flags=%x\n", -+ d, i, algo, crypto_aead_get_flags(tfm)); -+ goto out; -+ } else if (ret) -+ continue; -+ -+ authsize = 20; -+ ret = crypto_aead_setauthsize(tfm, authsize); -+ if (ret) { -+ pr_err("alg: aead%s: Failed to set authsize to %u on test %d for %s\n", -+ d, authsize, i, algo); -+ goto out; -+ } -+ -+ k = !!template[i].alen; -+ sg_init_table(sg, k + 1); -+ sg_set_buf(&sg[0], assoc, template[i].alen); -+ sg_set_buf(&sg[k], input, (enc ? template[i].rlen : -+ template[i].ilen)); -+ output = input; -+ -+ if (diff_dst) { -+ sg_init_table(sgout, k + 1); -+ sg_set_buf(&sgout[0], assoc, template[i].alen); -+ -+ output = xoutbuf[0]; -+ sg_set_buf(&sgout[k], output, -+ (enc ? template[i].rlen : template[i].ilen)); -+ } -+ -+ aead_request_set_crypt(req, sg, (diff_dst) ? sgout : sg, -+ template[i].ilen, iv); -+ -+ aead_request_set_ad(req, template[i].alen); -+ -+ ret = crypto_wait_req(enc ? crypto_aead_encrypt(req) -+ : crypto_aead_decrypt(req), &wait); -+ -+ switch (ret) { -+ case 0: -+ if (template[i].novrfy) { -+ /* verification was supposed to fail */ -+ pr_err("alg: tls%s: %s failed on test %d for %s: ret was 0, expected -EBADMSG\n", -+ d, e, i, algo); -+ /* so really, we got a bad message */ -+ ret = -EBADMSG; -+ goto out; -+ } -+ break; -+ case -EBADMSG: -+ /* verification failure was expected */ -+ if (template[i].novrfy) -+ continue; -+ /* fall through */ -+ default: -+ pr_err("alg: tls%s: %s failed on test %d for %s: ret=%d\n", -+ d, e, i, algo, -ret); -+ goto out; -+ } -+ -+ q = output; -+ if (memcmp(q, template[i].result, template[i].rlen)) { -+ pr_err("alg: tls%s: Test %d failed on %s for %s\n", -+ d, i, e, algo); -+ hexdump(q, template[i].rlen); -+ pr_err("should be:\n"); -+ hexdump(template[i].result, template[i].rlen); -+ ret = -EINVAL; -+ goto out; -+ } -+ } -+ -+out: -+ aead_request_free(req); -+ -+ kfree(sg); -+out_nosg: -+ kfree(key); -+out_nokey: -+ kfree(iv); -+out_noiv: -+ testmgr_free_buf(axbuf); -+out_noaxbuf: -+ if (diff_dst) -+ testmgr_free_buf(xoutbuf); -+out_nooutbuf: -+ testmgr_free_buf(xbuf); -+out_noxbuf: -+ return ret; -+} -+ -+static int test_tls(struct crypto_aead *tfm, int enc, -+ struct tls_testvec *template, unsigned int tcount) -+{ -+ int ret; -+ /* test 'dst == src' case */ -+ ret = __test_tls(tfm, enc, template, tcount, false); -+ if (ret) -+ return ret; -+ /* test 'dst != src' case */ -+ return __test_tls(tfm, enc, template, tcount, true); -+} -+ -+static int alg_test_tls(const struct alg_test_desc *desc, const char *driver, -+ u32 type, u32 mask) -+{ -+ struct crypto_aead *tfm; -+ int err = 0; -+ -+ tfm = crypto_alloc_aead(driver, type, mask); -+ if (IS_ERR(tfm)) { -+ pr_err("alg: aead: Failed to load transform for %s: %ld\n", -+ driver, PTR_ERR(tfm)); -+ return PTR_ERR(tfm); -+ } -+ -+ if (desc->suite.tls.enc.vecs) { -+ err = test_tls(tfm, ENCRYPT, desc->suite.tls.enc.vecs, -+ desc->suite.tls.enc.count); -+ if (err) -+ goto out; -+ } -+ -+ if (!err && desc->suite.tls.dec.vecs) -+ err = test_tls(tfm, DECRYPT, desc->suite.tls.dec.vecs, -+ desc->suite.tls.dec.count); -+ -+out: -+ crypto_free_aead(tfm); -+ return err; -+} -+ - static int alg_test_aead(const struct alg_test_desc *desc, const char *driver, - u32 type, u32 mask) - { -@@ -5427,6 +5656,15 @@ static const struct alg_test_desc alg_test_descs[] = { - .suite = { - .hash = __VECS(tgr192_tv_template) - } -+ }, { -+ .alg = "tls10(hmac(sha1),cbc(aes))", -+ .test = alg_test_tls, -+ .suite = { -+ .tls = { -+ .enc = __VECS(tls_enc_tv_template), -+ .dec = __VECS(tls_dec_tv_template) -+ } -+ } - }, { - .alg = "vmac64(aes)", - .test = alg_test_hash, -diff --git a/crypto/testmgr.h b/crypto/testmgr.h -index 8c83811c0..16ae80824 100644 ---- a/crypto/testmgr.h -+++ b/crypto/testmgr.h -@@ -21,7 +21,12 @@ - #define _CRYPTO_TESTMGR_H - - #include -+#include - -+#define MAX_DIGEST_SIZE 64 -+#define MAX_TAP 8 -+ -+#define MAX_KEYLEN 160 - #define MAX_IVLEN 32 - - /* -@@ -146,6 +151,20 @@ struct drbg_testvec { - size_t expectedlen; - }; - -+struct tls_testvec { -+ char *key; /* wrapped keys for encryption and authentication */ -+ char *iv; /* initialization vector */ -+ char *input; /* input data */ -+ char *assoc; /* associated data: seq num, type, version, input len */ -+ char *result; /* result data */ -+ unsigned char fail; /* the test failure is expected */ -+ unsigned char novrfy; /* dec verification failure expected */ -+ unsigned char klen; /* key length */ -+ unsigned short ilen; /* input data length */ -+ unsigned short alen; /* associated data length */ -+ unsigned short rlen; /* result length */ -+}; -+ - struct akcipher_testvec { - const unsigned char *key; - const unsigned char *params; -@@ -176,6 +195,211 @@ struct kpp_testvec { - - static const char zeroed_string[48]; - -+/* -+ * TLS1.0 synthetic test vectors -+ */ -+static struct tls_testvec tls_enc_tv_template[] = { -+ { -+#ifdef __LITTLE_ENDIAN -+ .key = "\x08\x00" /* rta length */ -+ "\x01\x00" /* rta type */ -+#else -+ .key = "\x00\x08" /* rta length */ -+ "\x00\x01" /* rta type */ -+#endif -+ "\x00\x00\x00\x10" /* enc key length */ -+ "authenticationkey20benckeyis16_bytes", -+ .klen = 8 + 20 + 16, -+ .iv = "iv0123456789abcd", -+ .input = "Single block msg", -+ .ilen = 16, -+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" -+ "\x00\x03\x01\x00\x10", -+ .alen = 13, -+ .result = "\xd5\xac\xb\xd2\xac\xad\x3f\xb1" -+ "\x59\x79\x1e\x91\x5f\x52\x14\x9c" -+ "\xc0\x75\xd8\x4c\x97\x0f\x07\x73" -+ "\xdc\x89\x47\x49\x49\xcb\x30\x6b" -+ "\x1b\x45\x23\xa1\xd0\x51\xcf\x02" -+ "\x2e\xa8\x5d\xa0\xfe\xca\x82\x61", -+ .rlen = 16 + 20 + 12, -+ }, { -+#ifdef __LITTLE_ENDIAN -+ .key = "\x08\x00" /* rta length */ -+ "\x01\x00" /* rta type */ -+#else -+ .key = "\x00\x08" /* rta length */ -+ "\x00\x01" /* rta type */ -+#endif -+ "\x00\x00\x00\x10" /* enc key length */ -+ "authenticationkey20benckeyis16_bytes", -+ .klen = 8 + 20 + 16, -+ .iv = "iv0123456789abcd", -+ .input = "", -+ .ilen = 0, -+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" -+ "\x00\x03\x01\x00\x00", -+ .alen = 13, -+ .result = "\x58\x2a\x11\xc\x86\x8e\x4b\x67" -+ "\x2d\x16\x26\x1a\xac\x4b\xe2\x1a" -+ "\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45" -+ "\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a", -+ .rlen = 20 + 12, -+ }, { -+#ifdef __LITTLE_ENDIAN -+ .key = "\x08\x00" /* rta length */ -+ "\x01\x00" /* rta type */ -+#else -+ .key = "\x00\x08" /* rta length */ -+ "\x00\x01" /* rta type */ -+#endif -+ "\x00\x00\x00\x10" /* enc key length */ -+ "authenticationkey20benckeyis16_bytes", -+ .klen = 8 + 20 + 16, -+ .iv = "iv0123456789abcd", -+ .input = "285 bytes plaintext285 bytes plaintext285 bytes" -+ " plaintext285 bytes plaintext285 bytes plaintext285" -+ " bytes plaintext285 bytes plaintext285 bytes" -+ " plaintext285 bytes plaintext285 bytes plaintext285" -+ " bytes plaintext285 bytes plaintext285 bytes" -+ " plaintext285 bytes plaintext285 bytes plaintext285" -+ " bytes plaintext285 bytes plaintext", -+ .ilen = 285, -+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" -+ "\x00\x03\x01\x01\x1d", -+ .alen = 13, -+ .result = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd" -+ "\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90" -+ "\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a" -+ "\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94" -+ "\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51" -+ "\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31" -+ "\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8" -+ "\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50" -+ "\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac" -+ "\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14" -+ "\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d" -+ "\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8" -+ "\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c" -+ "\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74" -+ "\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e" -+ "\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b" -+ "\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d" -+ "\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13" -+ "\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d" -+ "\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5" -+ "\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2" -+ "\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20" -+ "\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1" -+ "\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e" -+ "\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7" -+ "\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e" -+ "\x2a\x9e\x26\xf1\x3d\x21\xac\x65", -+ .rlen = 285 + 20 + 15, -+ } -+}; -+ -+static struct tls_testvec tls_dec_tv_template[] = { -+ { -+#ifdef __LITTLE_ENDIAN -+ .key = "\x08\x00" /* rta length */ -+ "\x01\x00" /* rta type */ -+#else -+ .key = "\x00\x08" /* rta length */ -+ "\x00\x01" /* rta type */ -+#endif -+ "\x00\x00\x00\x10" /* enc key length */ -+ "authenticationkey20benckeyis16_bytes", -+ .klen = 8 + 20 + 16, -+ .iv = "iv0123456789abcd", -+ .input = "\xd5\xac\xb\xd2\xac\xad\x3f\xb1" -+ "\x59\x79\x1e\x91\x5f\x52\x14\x9c" -+ "\xc0\x75\xd8\x4c\x97\x0f\x07\x73" -+ "\xdc\x89\x47\x49\x49\xcb\x30\x6b" -+ "\x1b\x45\x23\xa1\xd0\x51\xcf\x02" -+ "\x2e\xa8\x5d\xa0\xfe\xca\x82\x61", -+ .ilen = 16 + 20 + 12, -+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" -+ "\x00\x03\x01\x00\x30", -+ .alen = 13, -+ .result = "Single block msg", -+ .rlen = 16, -+ }, { -+#ifdef __LITTLE_ENDIAN -+ .key = "\x08\x00" /* rta length */ -+ "\x01\x00" /* rta type */ -+#else -+ .key = "\x00\x08" /* rta length */ -+ "\x00\x01" /* rta type */ -+#endif -+ "\x00\x00\x00\x10" /* enc key length */ -+ "authenticationkey20benckeyis16_bytes", -+ .klen = 8 + 20 + 16, -+ .iv = "iv0123456789abcd", -+ .input = "\x58\x2a\x11\xc\x86\x8e\x4b\x67" -+ "\x2d\x16\x26\x1a\xac\x4b\xe2\x1a" -+ "\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45" -+ "\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a", -+ .ilen = 20 + 12, -+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" -+ "\x00\x03\x01\x00\x20", -+ .alen = 13, -+ .result = "", -+ .rlen = 0, -+ }, { -+#ifdef __LITTLE_ENDIAN -+ .key = "\x08\x00" /* rta length */ -+ "\x01\x00" /* rta type */ -+#else -+ .key = "\x00\x08" /* rta length */ -+ "\x00\x01" /* rta type */ -+#endif -+ "\x00\x00\x00\x10" /* enc key length */ -+ "authenticationkey20benckeyis16_bytes", -+ .klen = 8 + 20 + 16, -+ .iv = "iv0123456789abcd", -+ .input = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd" -+ "\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90" -+ "\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a" -+ "\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94" -+ "\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51" -+ "\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31" -+ "\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8" -+ "\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50" -+ "\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac" -+ "\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14" -+ "\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d" -+ "\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8" -+ "\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c" -+ "\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74" -+ "\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e" -+ "\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b" -+ "\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d" -+ "\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13" -+ "\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d" -+ "\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5" -+ "\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2" -+ "\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20" -+ "\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1" -+ "\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e" -+ "\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7" -+ "\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e" -+ "\x2a\x9e\x26\xf1\x3d\x21\xac\x65", -+ -+ .ilen = 285 + 20 + 15, -+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" -+ "\x00\x03\x01\x01\x40", -+ .alen = 13, -+ .result = "285 bytes plaintext285 bytes plaintext285 bytes" -+ " plaintext285 bytes plaintext285 bytes plaintext285" -+ " bytes plaintext285 bytes plaintext285 bytes" -+ " plaintext285 bytes plaintext285 bytes plaintext285" -+ " bytes plaintext285 bytes plaintext285 bytes" -+ " plaintext285 bytes plaintext285 bytes plaintext", -+ .rlen = 285, -+ } -+}; -+ - /* - * RSA test vectors. Borrowed from openSSL. - */ -diff --git a/crypto/tls.c b/crypto/tls.c -new file mode 100644 -index 000000000..e04f3b450 ---- /dev/null -+++ b/crypto/tls.c -@@ -0,0 +1,579 @@ -+/* -+ * Copyright 2013 Freescale -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the Free -+ * Software Foundation; either version 2 of the License, or (at your option) -+ * any later version. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct tls_instance_ctx { -+ struct crypto_ahash_spawn auth; -+ struct crypto_skcipher_spawn enc; -+}; -+ -+struct crypto_tls_ctx { -+ unsigned int reqoff; -+ struct crypto_ahash *auth; -+ struct crypto_skcipher *enc; -+ struct crypto_sync_skcipher *null; -+}; -+ -+struct tls_request_ctx { -+ /* -+ * cryptlen holds the payload length in the case of encryption or -+ * payload_len + icv_len + padding_len in case of decryption -+ */ -+ unsigned int cryptlen; -+ /* working space for partial results */ -+ struct scatterlist tmp[2]; -+ struct scatterlist cipher[2]; -+ struct scatterlist dst[2]; -+ char tail[]; -+}; -+ -+struct async_op { -+ struct completion completion; -+ int err; -+}; -+ -+static void tls_async_op_done(struct crypto_async_request *req, int err) -+{ -+ struct async_op *areq = req->data; -+ -+ if (err == -EINPROGRESS) -+ return; -+ -+ areq->err = err; -+ complete(&areq->completion); -+} -+ -+static int crypto_tls_setkey(struct crypto_aead *tls, const u8 *key, -+ unsigned int keylen) -+{ -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); -+ struct crypto_ahash *auth = ctx->auth; -+ struct crypto_skcipher *enc = ctx->enc; -+ struct crypto_authenc_keys keys; -+ int err = -EINVAL; -+ -+ if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) -+ goto out; -+ -+ crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK); -+ crypto_ahash_set_flags(auth, crypto_aead_get_flags(tls) & -+ CRYPTO_TFM_REQ_MASK); -+ err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen); -+ if (err) -+ goto out; -+ -+ crypto_skcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK); -+ crypto_skcipher_set_flags(enc, crypto_aead_get_flags(tls) & -+ CRYPTO_TFM_REQ_MASK); -+ err = crypto_skcipher_setkey(enc, keys.enckey, keys.enckeylen); -+ -+out: -+ memzero_explicit(&keys, sizeof(keys)); -+ return err; -+} -+ -+/** -+ * crypto_tls_genicv - Calculate hmac digest for a TLS record -+ * @hash: (output) buffer to save the digest into -+ * @src: (input) scatterlist with the assoc and payload data -+ * @srclen: (input) size of the source buffer (assoclen + cryptlen) -+ * @req: (input) aead request -+ **/ -+static int crypto_tls_genicv(u8 *hash, struct scatterlist *src, -+ unsigned int srclen, struct aead_request *req) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); -+ struct tls_request_ctx *treq_ctx = aead_request_ctx(req); -+ struct async_op ahash_op; -+ struct ahash_request *ahreq = (void *)(treq_ctx->tail + ctx->reqoff); -+ unsigned int flags = CRYPTO_TFM_REQ_MAY_SLEEP; -+ int err = -EBADMSG; -+ -+ /* Bail out if the request assoc len is 0 */ -+ if (!req->assoclen) -+ return err; -+ -+ init_completion(&ahash_op.completion); -+ -+ /* the hash transform to be executed comes from the original request */ -+ ahash_request_set_tfm(ahreq, ctx->auth); -+ /* prepare the hash request with input data and result pointer */ -+ ahash_request_set_crypt(ahreq, src, hash, srclen); -+ /* set the notifier for when the async hash function returns */ -+ ahash_request_set_callback(ahreq, aead_request_flags(req) & flags, -+ tls_async_op_done, &ahash_op); -+ -+ /* Calculate the digest on the given data. The result is put in hash */ -+ err = crypto_ahash_digest(ahreq); -+ if (err == -EINPROGRESS) { -+ err = wait_for_completion_interruptible(&ahash_op.completion); -+ if (!err) -+ err = ahash_op.err; -+ } -+ -+ return err; -+} -+ -+/** -+ * crypto_tls_gen_padicv - Calculate and pad hmac digest for a TLS record -+ * @hash: (output) buffer to save the digest and padding into -+ * @phashlen: (output) the size of digest + padding -+ * @req: (input) aead request -+ **/ -+static int crypto_tls_gen_padicv(u8 *hash, unsigned int *phashlen, -+ struct aead_request *req) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ unsigned int hash_size = crypto_aead_authsize(tls); -+ unsigned int block_size = crypto_aead_blocksize(tls); -+ unsigned int srclen = req->cryptlen + hash_size; -+ unsigned int icvlen = req->cryptlen + req->assoclen; -+ unsigned int padlen; -+ int err; -+ -+ err = crypto_tls_genicv(hash, req->src, icvlen, req); -+ if (err) -+ goto out; -+ -+ /* add padding after digest */ -+ padlen = block_size - (srclen % block_size); -+ memset(hash + hash_size, padlen - 1, padlen); -+ -+ *phashlen = hash_size + padlen; -+out: -+ return err; -+} -+ -+static int crypto_tls_copy_data(struct aead_request *req, -+ struct scatterlist *src, -+ struct scatterlist *dst, -+ unsigned int len) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); -+ SYNC_SKCIPHER_REQUEST_ON_STACK(skreq, ctx->null); -+ -+ skcipher_request_set_sync_tfm(skreq, ctx->null); -+ skcipher_request_set_callback(skreq, aead_request_flags(req), -+ NULL, NULL); -+ skcipher_request_set_crypt(skreq, src, dst, len, NULL); -+ -+ return crypto_skcipher_encrypt(skreq); -+} -+ -+static int crypto_tls_encrypt(struct aead_request *req) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); -+ struct tls_request_ctx *treq_ctx = aead_request_ctx(req); -+ struct skcipher_request *skreq; -+ struct scatterlist *cipher = treq_ctx->cipher; -+ struct scatterlist *tmp = treq_ctx->tmp; -+ struct scatterlist *sg, *src, *dst; -+ unsigned int cryptlen, phashlen; -+ u8 *hash = treq_ctx->tail; -+ int err; -+ -+ /* -+ * The hash result is saved at the beginning of the tls request ctx -+ * and is aligned as required by the hash transform. Enough space was -+ * allocated in crypto_tls_init_tfm to accommodate the difference. The -+ * requests themselves start later at treq_ctx->tail + ctx->reqoff so -+ * the result is not overwritten by the second (cipher) request. -+ */ -+ hash = (u8 *)ALIGN((unsigned long)hash + -+ crypto_ahash_alignmask(ctx->auth), -+ crypto_ahash_alignmask(ctx->auth) + 1); -+ -+ /* -+ * STEP 1: create ICV together with necessary padding -+ */ -+ err = crypto_tls_gen_padicv(hash, &phashlen, req); -+ if (err) -+ return err; -+ -+ /* -+ * STEP 2: Hash and padding are combined with the payload -+ * depending on the form it arrives. Scatter tables must have at least -+ * one page of data before chaining with another table and can't have -+ * an empty data page. The following code addresses these requirements. -+ * -+ * If the payload is empty, only the hash is encrypted, otherwise the -+ * payload scatterlist is merged with the hash. A special merging case -+ * is when the payload has only one page of data. In that case the -+ * payload page is moved to another scatterlist and prepared there for -+ * encryption. -+ */ -+ if (req->cryptlen) { -+ src = scatterwalk_ffwd(tmp, req->src, req->assoclen); -+ -+ sg_init_table(cipher, 2); -+ sg_set_buf(cipher + 1, hash, phashlen); -+ -+ if (sg_is_last(src)) { -+ sg_set_page(cipher, sg_page(src), req->cryptlen, -+ src->offset); -+ src = cipher; -+ } else { -+ unsigned int rem_len = req->cryptlen; -+ -+ for (sg = src; rem_len > sg->length; sg = sg_next(sg)) -+ rem_len -= min(rem_len, sg->length); -+ -+ sg_set_page(cipher, sg_page(sg), rem_len, sg->offset); -+ sg_chain(sg, 1, cipher); -+ } -+ } else { -+ sg_init_one(cipher, hash, phashlen); -+ src = cipher; -+ } -+ -+ /** -+ * If src != dst copy the associated data from source to destination. -+ * In both cases fast-forward passed the associated data in the dest. -+ */ -+ if (req->src != req->dst) { -+ err = crypto_tls_copy_data(req, req->src, req->dst, -+ req->assoclen); -+ if (err) -+ return err; -+ } -+ dst = scatterwalk_ffwd(treq_ctx->dst, req->dst, req->assoclen); -+ -+ /* -+ * STEP 3: encrypt the frame and return the result -+ */ -+ cryptlen = req->cryptlen + phashlen; -+ -+ /* -+ * The hash and the cipher are applied at different times and their -+ * requests can use the same memory space without interference -+ */ -+ skreq = (void *)(treq_ctx->tail + ctx->reqoff); -+ skcipher_request_set_tfm(skreq, ctx->enc); -+ skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv); -+ skcipher_request_set_callback(skreq, aead_request_flags(req), -+ req->base.complete, req->base.data); -+ /* -+ * Apply the cipher transform. The result will be in req->dst when the -+ * asynchronuous call terminates -+ */ -+ err = crypto_skcipher_encrypt(skreq); -+ -+ return err; -+} -+ -+static int crypto_tls_decrypt(struct aead_request *req) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); -+ struct tls_request_ctx *treq_ctx = aead_request_ctx(req); -+ unsigned int cryptlen = req->cryptlen; -+ unsigned int hash_size = crypto_aead_authsize(tls); -+ unsigned int block_size = crypto_aead_blocksize(tls); -+ struct skcipher_request *skreq = (void *)(treq_ctx->tail + ctx->reqoff); -+ struct scatterlist *tmp = treq_ctx->tmp; -+ struct scatterlist *src, *dst; -+ -+ u8 padding[255]; /* padding can be 0-255 bytes */ -+ u8 pad_size; -+ u16 *len_field; -+ u8 *ihash, *hash = treq_ctx->tail; -+ -+ int paderr = 0; -+ int err = -EINVAL; -+ int i; -+ struct async_op ciph_op; -+ -+ /* -+ * Rule out bad packets. The input packet length must be at least one -+ * byte more than the hash_size -+ */ -+ if (cryptlen <= hash_size || cryptlen % block_size) -+ goto out; -+ -+ /* -+ * Step 1 - Decrypt the source. Fast-forward past the associated data -+ * to the encrypted data. The result will be overwritten in place so -+ * that the decrypted data will be adjacent to the associated data. The -+ * last step (computing the hash) will have it's input data already -+ * prepared and ready to be accessed at req->src. -+ */ -+ src = scatterwalk_ffwd(tmp, req->src, req->assoclen); -+ dst = src; -+ -+ init_completion(&ciph_op.completion); -+ skcipher_request_set_tfm(skreq, ctx->enc); -+ skcipher_request_set_callback(skreq, aead_request_flags(req), -+ tls_async_op_done, &ciph_op); -+ skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv); -+ err = crypto_skcipher_decrypt(skreq); -+ if (err == -EINPROGRESS) { -+ err = wait_for_completion_interruptible(&ciph_op.completion); -+ if (!err) -+ err = ciph_op.err; -+ } -+ if (err) -+ goto out; -+ -+ /* -+ * Step 2 - Verify padding -+ * Retrieve the last byte of the payload; this is the padding size. -+ */ -+ cryptlen -= 1; -+ scatterwalk_map_and_copy(&pad_size, dst, cryptlen, 1, 0); -+ -+ /* RFC recommendation for invalid padding size. */ -+ if (cryptlen < pad_size + hash_size) { -+ pad_size = 0; -+ paderr = -EBADMSG; -+ } -+ cryptlen -= pad_size; -+ scatterwalk_map_and_copy(padding, dst, cryptlen, pad_size, 0); -+ -+ /* Padding content must be equal with pad_size. We verify it all */ -+ for (i = 0; i < pad_size; i++) -+ if (padding[i] != pad_size) -+ paderr = -EBADMSG; -+ -+ /* -+ * Step 3 - Verify hash -+ * Align the digest result as required by the hash transform. Enough -+ * space was allocated in crypto_tls_init_tfm -+ */ -+ hash = (u8 *)ALIGN((unsigned long)hash + -+ crypto_ahash_alignmask(ctx->auth), -+ crypto_ahash_alignmask(ctx->auth) + 1); -+ /* -+ * Two bytes at the end of the associated data make the length field. -+ * It must be updated with the length of the cleartext message before -+ * the hash is calculated. -+ */ -+ len_field = sg_virt(req->src) + req->assoclen - 2; -+ cryptlen -= hash_size; -+ *len_field = htons(cryptlen); -+ -+ /* This is the hash from the decrypted packet. Save it for later */ -+ ihash = hash + hash_size; -+ scatterwalk_map_and_copy(ihash, dst, cryptlen, hash_size, 0); -+ -+ /* Now compute and compare our ICV with the one from the packet */ -+ err = crypto_tls_genicv(hash, req->src, cryptlen + req->assoclen, req); -+ if (!err) -+ err = memcmp(hash, ihash, hash_size) ? -EBADMSG : 0; -+ -+ if (req->src != req->dst) { -+ err = crypto_tls_copy_data(req, req->src, req->dst, cryptlen + -+ req->assoclen); -+ if (err) -+ goto out; -+ } -+ -+ /* return the first found error */ -+ if (paderr) -+ err = paderr; -+ -+out: -+ aead_request_complete(req, err); -+ return err; -+} -+ -+static int crypto_tls_init_tfm(struct crypto_aead *tfm) -+{ -+ struct aead_instance *inst = aead_alg_instance(tfm); -+ struct tls_instance_ctx *ictx = aead_instance_ctx(inst); -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm); -+ struct crypto_ahash *auth; -+ struct crypto_skcipher *enc; -+ struct crypto_sync_skcipher *null; -+ int err; -+ -+ auth = crypto_spawn_ahash(&ictx->auth); -+ if (IS_ERR(auth)) -+ return PTR_ERR(auth); -+ -+ enc = crypto_spawn_skcipher(&ictx->enc); -+ err = PTR_ERR(enc); -+ if (IS_ERR(enc)) -+ goto err_free_ahash; -+ -+ null = crypto_get_default_null_skcipher(); -+ err = PTR_ERR(null); -+ if (IS_ERR(null)) -+ goto err_free_skcipher; -+ -+ ctx->auth = auth; -+ ctx->enc = enc; -+ ctx->null = null; -+ -+ /* -+ * Allow enough space for two digests. The two digests will be compared -+ * during the decryption phase. One will come from the decrypted packet -+ * and the other will be calculated. For encryption, one digest is -+ * padded (up to a cipher blocksize) and chained with the payload -+ */ -+ ctx->reqoff = ALIGN(crypto_ahash_digestsize(auth) + -+ crypto_ahash_alignmask(auth), -+ crypto_ahash_alignmask(auth) + 1) + -+ max(crypto_ahash_digestsize(auth), -+ crypto_skcipher_blocksize(enc)); -+ -+ crypto_aead_set_reqsize(tfm, -+ sizeof(struct tls_request_ctx) + -+ ctx->reqoff + -+ max_t(unsigned int, -+ crypto_ahash_reqsize(auth) + -+ sizeof(struct ahash_request), -+ crypto_skcipher_reqsize(enc) + -+ sizeof(struct skcipher_request))); -+ -+ return 0; -+ -+err_free_skcipher: -+ crypto_free_skcipher(enc); -+err_free_ahash: -+ crypto_free_ahash(auth); -+ return err; -+} -+ -+static void crypto_tls_exit_tfm(struct crypto_aead *tfm) -+{ -+ struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm); -+ -+ crypto_free_ahash(ctx->auth); -+ crypto_free_skcipher(ctx->enc); -+ crypto_put_default_null_skcipher(); -+} -+ -+static void crypto_tls_free(struct aead_instance *inst) -+{ -+ struct tls_instance_ctx *ctx = aead_instance_ctx(inst); -+ -+ crypto_drop_skcipher(&ctx->enc); -+ crypto_drop_ahash(&ctx->auth); -+ kfree(inst); -+} -+ -+static int crypto_tls_create(struct crypto_template *tmpl, struct rtattr **tb) -+{ -+ struct crypto_attr_type *algt; -+ struct aead_instance *inst; -+ struct hash_alg_common *auth; -+ struct crypto_alg *auth_base; -+ struct skcipher_alg *enc; -+ struct tls_instance_ctx *ctx; -+ u32 mask; -+ int err; -+ -+ algt = crypto_get_attr_type(tb); -+ if (IS_ERR(algt)) -+ return PTR_ERR(algt); -+ -+ if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) -+ return -EINVAL; -+ -+ err = crypto_check_attr_type(tb, CRYPTO_ALG_TYPE_AEAD, &mask); -+ if (err) -+ return err; -+ -+ inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); -+ if (!inst) -+ return -ENOMEM; -+ ctx = aead_instance_ctx(inst); -+ -+ err = crypto_grab_ahash(&ctx->auth, aead_crypto_instance(inst), -+ crypto_attr_alg_name(tb[1]), 0, mask); -+ if (err) -+ goto err_free_inst; -+ auth = crypto_spawn_ahash_alg(&ctx->auth); -+ auth_base = &auth->base; -+ -+ err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst), -+ crypto_attr_alg_name(tb[2]), 0, mask); -+ if (err) -+ goto err_free_inst; -+ enc = crypto_spawn_skcipher_alg(&ctx->enc); -+ -+ err = -ENAMETOOLONG; -+ if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, -+ "tls10(%s,%s)", auth_base->cra_name, -+ enc->base.cra_name) >= CRYPTO_MAX_ALG_NAME) -+ goto err_free_inst; -+ -+ if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, -+ "tls10(%s,%s)", auth_base->cra_driver_name, -+ enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) -+ goto err_free_inst; -+ -+ inst->alg.base.cra_flags = (auth_base->cra_flags | -+ enc->base.cra_flags) & CRYPTO_ALG_ASYNC; -+ inst->alg.base.cra_priority = enc->base.cra_priority * 10 + -+ auth_base->cra_priority; -+ inst->alg.base.cra_blocksize = enc->base.cra_blocksize; -+ inst->alg.base.cra_alignmask = auth_base->cra_alignmask | -+ enc->base.cra_alignmask; -+ inst->alg.base.cra_ctxsize = sizeof(struct crypto_tls_ctx); -+ -+ inst->alg.ivsize = crypto_skcipher_alg_ivsize(enc); -+ inst->alg.chunksize = crypto_skcipher_alg_chunksize(enc); -+ inst->alg.maxauthsize = auth->digestsize; -+ -+ inst->alg.init = crypto_tls_init_tfm; -+ inst->alg.exit = crypto_tls_exit_tfm; -+ -+ inst->alg.setkey = crypto_tls_setkey; -+ inst->alg.encrypt = crypto_tls_encrypt; -+ inst->alg.decrypt = crypto_tls_decrypt; -+ -+ inst->free = crypto_tls_free; -+ -+ err = aead_register_instance(tmpl, inst); -+ if (err) { -+err_free_inst: -+ crypto_tls_free(inst); -+ } -+ -+ return err; -+} -+ -+static struct crypto_template crypto_tls_tmpl = { -+ .name = "tls10", -+ .create = crypto_tls_create, -+ .module = THIS_MODULE, -+}; -+ -+static int __init crypto_tls_module_init(void) -+{ -+ return crypto_register_template(&crypto_tls_tmpl); -+} -+ -+static void __exit crypto_tls_module_exit(void) -+{ -+ crypto_unregister_template(&crypto_tls_tmpl); -+} -+ -+module_init(crypto_tls_module_init); -+module_exit(crypto_tls_module_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("TLS 1.0 record encryption"); -+MODULE_ALIAS_CRYPTO("tls10"); diff --git a/imx8mm/kernel/patches/003_imx_8m_mini_drivers_modify_content.patch b/imx8mm/kernel/patches/003_imx_8m_mini_drivers_modify_content.patch deleted file mode 100644 index 8e695f1..0000000 --- a/imx8mm/kernel/patches/003_imx_8m_mini_drivers_modify_content.patch +++ /dev/null @@ -1,774154 +0,0 @@ -commit 685bbd5864d15dedd80d6fb129d957ef1d10578d -Author: zhaoxc0502 -Date: Mon Jun 6 23:31:05 2022 +0800 - - get patch - - Change-Id: Iccbf929641f5249785179f72d9d5dbccd19ebc42 - -diff --git a/drivers/Kconfig b/drivers/Kconfig -index 826b2b19d..fac66ea92 100644 ---- a/drivers/Kconfig -+++ b/drivers/Kconfig -@@ -238,5 +238,7 @@ source "drivers/counter/Kconfig" - - source "drivers/most/Kconfig" - -+source "drivers/mxc/Kconfig" -+ - source "drivers/accesstokenid/Kconfig" - endmenu -diff --git a/drivers/Makefile b/drivers/Makefile -index ecc494918..9b0f77d66 100644 ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -192,4 +192,5 @@ obj-$(CONFIG_GNSS) += gnss/ - obj-$(CONFIG_INTERCONNECT) += interconnect/ - obj-$(CONFIG_COUNTER) += counter/ - obj-$(CONFIG_MOST) += most/ --obj-$(CONFIG_ACCESS_TOKENID) += accesstokenid/ -+obj-y += mxc/ -+obj-y += accesstokenid/ -diff --git a/drivers/base/core.c b/drivers/base/core.c -index 2bc4db5ff..8952f231f 100644 ---- a/drivers/base/core.c -+++ b/drivers/base/core.c -@@ -2055,6 +2055,34 @@ static ssize_t online_store(struct device *dev, struct device_attribute *attr, - } - static DEVICE_ATTR_RW(online); - -+static ssize_t suppliers_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ struct device_link *link; -+ size_t count = 0; -+ -+ list_for_each_entry(link, &dev->links.suppliers, c_node) -+ count += scnprintf(buf + count, PAGE_SIZE - count, "%s\n", -+ dev_name(link->supplier)); -+ -+ return count; -+} -+static DEVICE_ATTR_RO(suppliers); -+ -+static ssize_t consumers_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ struct device_link *link; -+ size_t count = 0; -+ -+ list_for_each_entry(link, &dev->links.consumers, s_node) -+ count += scnprintf(buf + count, PAGE_SIZE - count, "%s\n", -+ dev_name(link->consumer)); -+ -+ return count; -+} -+static DEVICE_ATTR_RO(consumers); -+ - int device_add_groups(struct device *dev, const struct attribute_group **groups) - { - return sysfs_create_groups(&dev->kobj, groups); -@@ -2226,14 +2254,26 @@ static int device_add_attrs(struct device *dev) - goto err_remove_dev_groups; - } - -+ error = device_create_file(dev, &dev_attr_suppliers); -+ if (error) -+ goto err_remove_dev_online; -+ -+ error = device_create_file(dev, &dev_attr_consumers); -+ if (error) -+ goto err_remove_dev_suppliers; -+ - if (fw_devlink_flags && !fw_devlink_is_permissive()) { - error = device_create_file(dev, &dev_attr_waiting_for_supplier); - if (error) -- goto err_remove_dev_online; -+ goto err_remove_dev_consumers; - } - - return 0; - -+ err_remove_dev_consumers: -+ device_remove_file(dev, &dev_attr_consumers); -+ err_remove_dev_suppliers: -+ device_remove_file(dev, &dev_attr_suppliers); - err_remove_dev_online: - device_remove_file(dev, &dev_attr_online); - err_remove_dev_groups: -@@ -2254,6 +2294,8 @@ static void device_remove_attrs(struct device *dev) - const struct device_type *type = dev->type; - - device_remove_file(dev, &dev_attr_waiting_for_supplier); -+ device_remove_file(dev, &dev_attr_consumers); -+ device_remove_file(dev, &dev_attr_suppliers); - device_remove_file(dev, &dev_attr_online); - device_remove_groups(dev, dev->groups); - -@@ -4354,6 +4396,13 @@ void device_set_of_node_from_dev(struct device *dev, const struct device *dev2) - } - EXPORT_SYMBOL_GPL(device_set_of_node_from_dev); - -+void device_set_node(struct device *dev, struct fwnode_handle *fwnode) -+{ -+ dev->fwnode = fwnode; -+ dev->of_node = to_of_node(fwnode); -+} -+EXPORT_SYMBOL_GPL(device_set_node); -+ - int device_match_name(struct device *dev, const void *name) - { - return sysfs_streq(dev_name(dev), name); -diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c -index f41e4e499..402a58b44 100644 ---- a/drivers/base/firmware_loader/main.c -+++ b/drivers/base/firmware_loader/main.c -@@ -468,7 +468,9 @@ static const char * const fw_path[] = { - "/lib/firmware/updates/" UTS_RELEASE, - "/lib/firmware/updates", - "/lib/firmware/" UTS_RELEASE, -- "/lib/firmware" -+ "/lib/firmware", -+ "/system/etc/imx_sdma/" UTS_RELEASE, -+ "/system/etc/imx_sdma" - }; - - /* -diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c -index 743268996..e91bbd75f 100644 ---- a/drivers/base/power/domain.c -+++ b/drivers/base/power/domain.c -@@ -475,6 +475,9 @@ static int _genpd_power_off(struct generic_pm_domain *genpd, bool timed) - if (!genpd->power_off) - goto out; - -+ if (atomic_read(&genpd->sd_count) > 0) -+ return -EBUSY; -+ - if (!timed) { - ret = genpd->power_off(genpd); - if (ret) -@@ -583,9 +586,9 @@ static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on, - if (!genpd->gov) - genpd->state_idx = 0; - -- /* Don't power off, if a child domain is waiting to power on. */ -- if (atomic_read(&genpd->sd_count) > 0) -- return -EBUSY; -+ /* Choose the deepest state if no devices using this domain */ -+ if (!genpd->device_count) -+ genpd->state_idx = genpd->state_count - 1; - - ret = _genpd_power_off(genpd, true); - if (ret) { -@@ -980,11 +983,20 @@ static void genpd_sync_power_off(struct generic_pm_domain *genpd, bool use_lock, - { - struct gpd_link *link; - -- if (!genpd_status_on(genpd) || genpd_is_always_on(genpd)) -+ /* -+ * Give the power domain a chance to switch to the deepest state in -+ * case it's already off but in an intermediate low power state. -+ */ -+ genpd->state_idx_saved = genpd->state_idx; -+ -+ if (genpd_is_always_on(genpd)) -+ return; -+ -+ if (!genpd_status_on(genpd) && -+ genpd->state_idx == (genpd->state_count - 1)) - return; - -- if (genpd->suspended_count != genpd->device_count -- || atomic_read(&genpd->sd_count) > 0) -+ if (genpd->suspended_count != genpd->device_count) - return; - - /* Choose the deepest state when suspending */ -@@ -992,6 +1004,9 @@ static void genpd_sync_power_off(struct generic_pm_domain *genpd, bool use_lock, - if (_genpd_power_off(genpd, false)) - return; - -+ if (genpd->status == GENPD_STATE_OFF) -+ return; -+ - genpd->status = GENPD_STATE_OFF; - - list_for_each_entry(link, &genpd->child_links, child_node) { -@@ -1038,6 +1053,9 @@ static void genpd_sync_power_on(struct generic_pm_domain *genpd, bool use_lock, - } - - _genpd_power_on(genpd, false); -+ /* restore save power domain state after resume */ -+ genpd->state_idx = genpd->state_idx_saved; -+ - genpd->status = GENPD_STATE_ON; - } - -diff --git a/drivers/bus/fsl-mc/Kconfig b/drivers/bus/fsl-mc/Kconfig -index c23c77c9b..cde6f408b 100644 ---- a/drivers/bus/fsl-mc/Kconfig -+++ b/drivers/bus/fsl-mc/Kconfig -@@ -14,3 +14,10 @@ config FSL_MC_BUS - architecture. The fsl-mc bus driver handles discovery of - DPAA2 objects (which are represented as Linux devices) and - binding objects to drivers. -+ -+config FSL_MC_UAPI_SUPPORT -+ bool "Management Complex (MC) userspace support" -+ depends on FSL_MC_BUS -+ help -+ Provides userspace support for creating/destroying/configuring -+ DPAA2 objects in the Management Complex. -diff --git a/drivers/bus/fsl-mc/Makefile b/drivers/bus/fsl-mc/Makefile -index 3c518c7e8..892946245 100644 ---- a/drivers/bus/fsl-mc/Makefile -+++ b/drivers/bus/fsl-mc/Makefile -@@ -15,4 +15,8 @@ mc-bus-driver-objs := fsl-mc-bus.o \ - dprc-driver.o \ - fsl-mc-allocator.o \ - fsl-mc-msi.o \ -- dpmcp.o -+ dpmcp.o \ -+ obj-api.o -+ -+# MC userspace support -+obj-$(CONFIG_FSL_MC_UAPI_SUPPORT) += fsl-mc-uapi.o -diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c -index 91dc01596..e3f6e41fe 100644 ---- a/drivers/bus/fsl-mc/dprc-driver.c -+++ b/drivers/bus/fsl-mc/dprc-driver.c -@@ -237,8 +237,8 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, - * populated before they can get allocation requests from probe callbacks - * of the device drivers for the non-allocatable devices. - */ --static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -- bool alloc_interrupts) -+int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -+ bool alloc_interrupts) - { - int num_child_objects; - int dprc_get_obj_failures; -@@ -373,6 +373,34 @@ int dprc_scan_container(struct fsl_mc_device *mc_bus_dev, - return error; - } - EXPORT_SYMBOL_GPL(dprc_scan_container); -+ -+static ssize_t rescan_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct fsl_mc_device *root_mc_dev; -+ struct fsl_mc_bus *root_mc_bus; -+ unsigned long val; -+ -+ if (!fsl_mc_is_root_dprc(dev)) -+ return -EINVAL; -+ -+ root_mc_dev = to_fsl_mc_device(dev); -+ root_mc_bus = to_fsl_mc_bus(root_mc_dev); -+ -+ if (kstrtoul(buf, 0, &val) < 0) -+ return -EINVAL; -+ -+ if (val) { -+ mutex_lock(&root_mc_bus->scan_mutex); -+ dprc_scan_objects(root_mc_dev, NULL); -+ mutex_unlock(&root_mc_bus->scan_mutex); -+ } -+ -+ return count; -+} -+static DEVICE_ATTR_WO(rescan); -+ - /** - * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 - * -@@ -458,8 +486,9 @@ static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) - /* - * Disable and clear interrupt for a given DPRC object - */ --static int disable_dprc_irq(struct fsl_mc_device *mc_dev) -+int disable_dprc_irq(struct fsl_mc_device *mc_dev) - { -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - int error; - struct fsl_mc_io *mc_io = mc_dev->mc_io; - -@@ -496,9 +525,18 @@ static int disable_dprc_irq(struct fsl_mc_device *mc_dev) - return error; - } - -+ mc_bus->irq_enabled = 0; -+ - return 0; - } - -+int get_dprc_irq_state(struct fsl_mc_device *mc_dev) -+{ -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); -+ -+ return mc_bus->irq_enabled; -+} -+ - static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) - { - int error; -@@ -525,8 +563,9 @@ static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) - return 0; - } - --static int enable_dprc_irq(struct fsl_mc_device *mc_dev) -+int enable_dprc_irq(struct fsl_mc_device *mc_dev) - { -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - int error; - - /* -@@ -554,6 +593,8 @@ static int enable_dprc_irq(struct fsl_mc_device *mc_dev) - return error; - } - -+ mc_bus->irq_enabled = 1; -+ - return 0; - } - -@@ -603,6 +644,7 @@ int dprc_setup(struct fsl_mc_device *mc_dev) - struct irq_domain *mc_msi_domain; - bool mc_io_created = false; - bool msi_domain_set = false; -+ bool uapi_created = false; - u16 major_ver, minor_ver; - size_t region_size; - int error; -@@ -635,6 +677,12 @@ int dprc_setup(struct fsl_mc_device *mc_dev) - return error; - - mc_io_created = true; -+ } else { -+ error = fsl_mc_uapi_create_device_file(mc_bus); -+ if (error < 0) { -+ return -EPROBE_DEFER; -+ } -+ uapi_created = true; - } - - mc_msi_domain = fsl_mc_find_msi_domain(&mc_dev->dev); -@@ -670,9 +718,7 @@ int dprc_setup(struct fsl_mc_device *mc_dev) - goto error_cleanup_open; - } - -- if (major_ver < DPRC_MIN_VER_MAJOR || -- (major_ver == DPRC_MIN_VER_MAJOR && -- minor_ver < DPRC_MIN_VER_MINOR)) { -+ if (major_ver < DPRC_MIN_VER_MAJOR) { - dev_err(&mc_dev->dev, - "ERROR: DPRC version %d.%d not supported\n", - major_ver, minor_ver); -@@ -680,6 +726,13 @@ int dprc_setup(struct fsl_mc_device *mc_dev) - goto error_cleanup_open; - } - -+ error = device_create_file(&mc_dev->dev, &dev_attr_rescan); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, "device_create_file() failed: %d\n", -+ error); -+ goto error_cleanup_open; -+ } -+ - return 0; - - error_cleanup_open: -@@ -694,6 +747,9 @@ int dprc_setup(struct fsl_mc_device *mc_dev) - mc_dev->mc_io = NULL; - } - -+ if (uapi_created) -+ fsl_mc_uapi_remove_device_file(mc_bus); -+ - return error; - } - EXPORT_SYMBOL_GPL(dprc_setup); -@@ -765,6 +821,7 @@ static void dprc_teardown_irq(struct fsl_mc_device *mc_dev) - - int dprc_cleanup(struct fsl_mc_device *mc_dev) - { -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - int error; - - /* this function should be called only for DPRCs, it -@@ -795,8 +852,12 @@ int dprc_cleanup(struct fsl_mc_device *mc_dev) - if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { - fsl_destroy_mc_io(mc_dev->mc_io); - mc_dev->mc_io = NULL; -+ } else { -+ fsl_mc_uapi_remove_device_file(mc_bus); - } - -+ device_remove_file(&mc_dev->dev, &dev_attr_rescan); -+ - return 0; - } - EXPORT_SYMBOL_GPL(dprc_cleanup); -diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c -index 57b097caf..27b0a01ba 100644 ---- a/drivers/bus/fsl-mc/dprc.c -+++ b/drivers/bus/fsl-mc/dprc.c -@@ -576,6 +576,8 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io, - rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params; - region_desc->base_offset = le64_to_cpu(rsp_params->base_offset); - region_desc->size = le32_to_cpu(rsp_params->size); -+ region_desc->type = rsp_params->type; -+ region_desc->flags = le32_to_cpu(rsp_params->flags); - if (dprc_major_ver > 6 || (dprc_major_ver == 6 && dprc_minor_ver >= 3)) - region_desc->base_address = le64_to_cpu(rsp_params->base_addr); - else -diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c -index e329cdd71..b6070799a 100644 ---- a/drivers/bus/fsl-mc/fsl-mc-bus.c -+++ b/drivers/bus/fsl-mc/fsl-mc-bus.c -@@ -207,12 +207,108 @@ static struct attribute *fsl_mc_dev_attrs[] = { - - ATTRIBUTE_GROUPS(fsl_mc_dev); - -+static int scan_fsl_mc_bus(struct device *dev, void *data) -+{ -+ struct fsl_mc_device *root_mc_dev; -+ struct fsl_mc_bus *root_mc_bus; -+ -+ if (!fsl_mc_is_root_dprc(dev)) -+ goto exit; -+ -+ root_mc_dev = to_fsl_mc_device(dev); -+ root_mc_bus = to_fsl_mc_bus(root_mc_dev); -+ mutex_lock(&root_mc_bus->scan_mutex); -+ dprc_scan_objects(root_mc_dev, NULL); -+ mutex_unlock(&root_mc_bus->scan_mutex); -+ -+exit: -+ return 0; -+} -+ -+static ssize_t rescan_store(struct bus_type *bus, -+ const char *buf, size_t count) -+{ -+ unsigned long val; -+ -+ if (kstrtoul(buf, 0, &val) < 0) -+ return -EINVAL; -+ -+ if (val) -+ bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus); -+ -+ return count; -+} -+static BUS_ATTR_WO(rescan); -+ -+static int fsl_mc_bus_set_autorescan(struct device *dev, void *data) -+{ -+ struct fsl_mc_device *root_mc_dev; -+ unsigned long val; -+ char *buf = data; -+ -+ if (!fsl_mc_is_root_dprc(dev)) -+ goto exit; -+ -+ root_mc_dev = to_fsl_mc_device(dev); -+ -+ if (kstrtoul(buf, 0, &val) < 0) -+ return -EINVAL; -+ -+ if (val) -+ enable_dprc_irq(root_mc_dev); -+ else -+ disable_dprc_irq(root_mc_dev); -+ -+exit: -+ return 0; -+} -+ -+static int fsl_mc_bus_get_autorescan(struct device *dev, void *data) -+{ -+ struct fsl_mc_device *root_mc_dev; -+ char *buf = data; -+ -+ if (!fsl_mc_is_root_dprc(dev)) -+ goto exit; -+ -+ root_mc_dev = to_fsl_mc_device(dev); -+ -+ sprintf(buf, "%d\n", get_dprc_irq_state(root_mc_dev)); -+exit: -+ return 0; -+} -+ -+static ssize_t autorescan_store(struct bus_type *bus, -+ const char *buf, size_t count) -+{ -+ bus_for_each_dev(bus, NULL, (void *)buf, fsl_mc_bus_set_autorescan); -+ -+ return count; -+} -+ -+static ssize_t autorescan_show(struct bus_type *bus, char *buf) -+{ -+ bus_for_each_dev(bus, NULL, (void *)buf, fsl_mc_bus_get_autorescan); -+ return strlen(buf); -+} -+ -+static BUS_ATTR_RW(autorescan); -+ -+static struct attribute *fsl_mc_bus_attrs[] = { -+ &bus_attr_rescan.attr, -+ &bus_attr_autorescan.attr, -+ NULL, -+}; -+ -+ATTRIBUTE_GROUPS(fsl_mc_bus); -+ - struct bus_type fsl_mc_bus_type = { - .name = "fsl-mc", - .match = fsl_mc_bus_match, - .uevent = fsl_mc_bus_uevent, - .dma_configure = fsl_mc_dma_configure, - .dev_groups = fsl_mc_dev_groups, -+ .bus_groups = fsl_mc_bus_groups, - }; - EXPORT_SYMBOL_GPL(fsl_mc_bus_type); - -@@ -291,6 +387,11 @@ struct device_type fsl_mc_bus_dpdmai_type = { - }; - EXPORT_SYMBOL_GPL(fsl_mc_bus_dpdmai_type); - -+struct device_type fsl_mc_bus_dpdbg_type = { -+ .name = "fsl_mc_bus_dpdbg" -+}; -+EXPORT_SYMBOL_GPL(fsl_mc_bus_dpdbg_type); -+ - static struct device_type *fsl_mc_get_device_type(const char *type) - { - static const struct { -@@ -312,6 +413,7 @@ static struct device_type *fsl_mc_get_device_type(const char *type) - { &fsl_mc_bus_dpaiop_type, "dpaiop" }, - { &fsl_mc_bus_dpci_type, "dpci" }, - { &fsl_mc_bus_dpdmai_type, "dpdmai" }, -+ { &fsl_mc_bus_dpdbg_type, "dpdbg" }, - { NULL, NULL } - }; - int i; -@@ -855,6 +957,32 @@ struct fsl_mc_device *fsl_mc_get_endpoint(struct fsl_mc_device *mc_dev) - endpoint_desc.id = endpoint2.id; - endpoint = fsl_mc_device_lookup(&endpoint_desc, mc_bus_dev); - -+ /* -+ * We know that the device has an endpoint because we verified by -+ * interrogating the firmware. This is the case when the device was not -+ * yet discovered by the fsl-mc bus, thus the lookup returned NULL. -+ * Force a rescan of the devices in this container and retry the lookup. -+ */ -+ if (!endpoint) { -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); -+ -+ mutex_lock(&mc_bus->scan_mutex); -+ err = dprc_scan_objects(mc_bus_dev, true); -+ mutex_unlock(&mc_bus->scan_mutex); -+ -+ if (err < 0) -+ return ERR_PTR(err); -+ } -+ -+ endpoint = fsl_mc_device_lookup(&endpoint_desc, mc_bus_dev); -+ /* -+ * This means that the endpoint might reside in a different isolation -+ * context (DPRC/container). Not much to do, so return a permssion -+ * error. -+ */ -+ if (!endpoint) -+ return ERR_PTR(-EPERM); -+ - return endpoint; - } - EXPORT_SYMBOL_GPL(fsl_mc_get_endpoint); -diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h -index 85ca5fdee..fb4049f97 100644 ---- a/drivers/bus/fsl-mc/fsl-mc-private.h -+++ b/drivers/bus/fsl-mc/fsl-mc-private.h -@@ -10,6 +10,8 @@ - - #include - #include -+#include -+#include - - /* - * Data Path Management Complex (DPMNG) General API -@@ -211,12 +213,13 @@ struct dprc_cmd_get_obj_region { - - struct dprc_rsp_get_obj_region { - /* response word 0 */ -- __le64 pad; -+ __le64 pad0; - /* response word 1 */ - __le64 base_offset; - /* response word 2 */ - __le32 size; -- __le32 pad2; -+ u8 type; -+ u8 pad2[3]; - /* response word 3 */ - __le32 flags; - __le32 pad3; -@@ -521,6 +524,34 @@ struct dpcon_cmd_set_notification { - __le64 user_ctx; - }; - -+/* generic command versioning */ -+#define OBJ_CMD_BASE_VERSION 1 -+#define OBJ_CMD_ID_OFFSET 4 -+#define OBJ_CMD_MODULE_OFFSET 8 -+ -+#define OBJ_CMD(id) (((id) << OBJ_CMD_ID_OFFSET) | OBJ_CMD_BASE_VERSION) -+ -+/* open command codes */ -+#define DPRTC_CMDID_OPEN OBJ_CMD(0x810) -+#define DPNI_CMDID_OPEN OBJ_CMD(0x801) -+#define DPSW_CMDID_OPEN OBJ_CMD(0x802) -+#define DPIO_CMDID_OPEN OBJ_CMD(0x803) -+#define DPDMUX_CMDID_OPEN OBJ_CMD(0x806) -+#define DPCI_CMDID_OPEN OBJ_CMD(0x807) -+#define DPSECI_CMDID_OPEN OBJ_CMD(0x809) -+#define DPAIOP_CMDID_OPEN OBJ_CMD(0x80a) -+#define DPMAC_CMDID_OPEN OBJ_CMD(0x80c) -+#define DPDCEI_CMDID_OPEN OBJ_CMD(0x80d) -+#define DPDMAI_CMDID_OPEN OBJ_CMD(0x80e) -+#define DPDBG_CMDID_OPEN OBJ_CMD(0x80f) -+ -+/* Generic object command IDs */ -+#define OBJ_CMDID_CLOSE OBJ_CMD(0x800) -+#define OBJ_CMDID_RESET OBJ_CMD(0x005) -+ -+struct obj_cmd_open { -+ __le32 obj_id; -+}; - - /** - * struct fsl_mc_resource_pool - Pool of MC resources of a given -@@ -541,6 +572,22 @@ struct fsl_mc_resource_pool { - struct fsl_mc_bus *mc_bus; - }; - -+/** -+ * struct fsl_mc_uapi - information associated with a device file -+ * @misc: struct miscdevice linked to the root dprc -+ * @device: newly created device in /dev -+ * @mutex: mutex lock to serialize the open/release operations -+ * @local_instance_in_use: local MC I/O instance in use or not -+ * @static_mc_io: pointer to the static MC I/O object -+ */ -+struct fsl_mc_uapi { -+ struct miscdevice misc; -+ struct device *device; -+ struct mutex mutex; /* serialize open/release operations */ -+ u32 local_instance_in_use; -+ struct fsl_mc_io *static_mc_io; -+}; -+ - /** - * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC - * @mc_dev: fsl-mc device for the bus device itself. -@@ -550,6 +597,7 @@ struct fsl_mc_resource_pool { - * @irq_resources: Pointer to array of IRQ objects for the IRQ pool - * @scan_mutex: Serializes bus scanning - * @dprc_attr: DPRC attributes -+ * @uapi_misc: struct that abstracts the interaction with userspace - */ - struct fsl_mc_bus { - struct fsl_mc_device mc_dev; -@@ -557,6 +605,8 @@ struct fsl_mc_bus { - struct fsl_mc_device_irq *irq_resources; - struct mutex scan_mutex; /* serializes bus scanning */ - struct dprc_attributes dprc_attr; -+ struct fsl_mc_uapi uapi_misc; -+ int irq_enabled; - }; - - #define to_fsl_mc_bus(_mc_dev) \ -@@ -573,6 +623,9 @@ int __init dprc_driver_init(void); - - void dprc_driver_exit(void); - -+int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -+ bool alloc_interrupts); -+ - int __init fsl_mc_allocator_driver_init(void); - - void fsl_mc_allocator_driver_exit(void); -@@ -611,4 +664,27 @@ void fsl_mc_get_root_dprc(struct device *dev, - struct fsl_mc_device *fsl_mc_device_lookup(struct fsl_mc_obj_desc *obj_desc, - struct fsl_mc_device *mc_bus_dev); - -+#ifdef CONFIG_FSL_MC_UAPI_SUPPORT -+ -+int fsl_mc_uapi_create_device_file(struct fsl_mc_bus *mc_bus); -+ -+void fsl_mc_uapi_remove_device_file(struct fsl_mc_bus *mc_bus); -+ -+#else -+ -+static inline int fsl_mc_uapi_create_device_file(struct fsl_mc_bus *mc_bus) -+{ -+ return 0; -+} -+ -+static inline void fsl_mc_uapi_remove_device_file(struct fsl_mc_bus *mc_bus) -+{ -+} -+ -+#endif -+ -+int disable_dprc_irq(struct fsl_mc_device *mc_dev); -+int enable_dprc_irq(struct fsl_mc_device *mc_dev); -+int get_dprc_irq_state(struct fsl_mc_device *mc_dev); -+ - #endif /* _FSL_MC_PRIVATE_H_ */ -diff --git a/drivers/bus/fsl-mc/fsl-mc-uapi.c b/drivers/bus/fsl-mc/fsl-mc-uapi.c -new file mode 100644 -index 000000000..b5bd5a249 ---- /dev/null -+++ b/drivers/bus/fsl-mc/fsl-mc-uapi.c -@@ -0,0 +1,169 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Management Complex (MC) userspace support -+ * -+ * Copyright 2018 NXP -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "fsl-mc-private.h" -+ -+struct uapi_priv_data { -+ struct fsl_mc_uapi *uapi; -+ struct fsl_mc_io *mc_io; -+}; -+ -+static int fsl_mc_uapi_send_command(unsigned long arg, -+ struct fsl_mc_io *mc_io) -+{ -+ struct fsl_mc_command mc_cmd; -+ int error; -+ -+ error = copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd)); -+ if (error) -+ return -EFAULT; -+ -+ error = mc_send_command(mc_io, &mc_cmd); -+ if (error) -+ return error; -+ -+ error = copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd)); -+ if (error) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+static int fsl_mc_uapi_dev_open(struct inode *inode, struct file *filep) -+{ -+ struct fsl_mc_device *root_mc_device; -+ struct uapi_priv_data *priv_data; -+ struct fsl_mc_io *dynamic_mc_io; -+ struct fsl_mc_uapi *mc_uapi; -+ struct fsl_mc_bus *mc_bus; -+ int error; -+ -+ priv_data = kzalloc(sizeof(*priv_data), GFP_KERNEL); -+ if (!priv_data) -+ return -ENOMEM; -+ -+ mc_uapi = container_of(filep->private_data, struct fsl_mc_uapi, misc); -+ mc_bus = container_of(mc_uapi, struct fsl_mc_bus, uapi_misc); -+ root_mc_device = &mc_bus->mc_dev; -+ -+ mutex_lock(&mc_uapi->mutex); -+ -+ if (!mc_uapi->local_instance_in_use) { -+ priv_data->mc_io = mc_uapi->static_mc_io; -+ mc_uapi->local_instance_in_use = 1; -+ } else { -+ error = fsl_mc_portal_allocate(root_mc_device, 0, -+ &dynamic_mc_io); -+ if (error) { -+ dev_dbg(&root_mc_device->dev, -+ "Could not allocate MC portal\n"); -+ goto error_portal_allocate; -+ } -+ -+ priv_data->mc_io = dynamic_mc_io; -+ } -+ priv_data->uapi = mc_uapi; -+ filep->private_data = priv_data; -+ -+ mutex_unlock(&mc_uapi->mutex); -+ -+ return 0; -+ -+error_portal_allocate: -+ mutex_unlock(&mc_uapi->mutex); -+ kfree(priv_data); -+ -+ return error; -+} -+ -+static int fsl_mc_uapi_dev_release(struct inode *inode, struct file *filep) -+{ -+ struct uapi_priv_data *priv_data; -+ struct fsl_mc_uapi *mc_uapi; -+ struct fsl_mc_io *mc_io; -+ -+ priv_data = filep->private_data; -+ mc_uapi = priv_data->uapi; -+ mc_io = priv_data->mc_io; -+ -+ mutex_lock(&mc_uapi->mutex); -+ -+ if (mc_io == mc_uapi->static_mc_io) -+ mc_uapi->local_instance_in_use = 0; -+ else -+ fsl_mc_portal_free(mc_io); -+ -+ kfree(filep->private_data); -+ filep->private_data = NULL; -+ -+ mutex_unlock(&mc_uapi->mutex); -+ -+ return 0; -+} -+ -+static long fsl_mc_uapi_dev_ioctl(struct file *file, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct uapi_priv_data *priv_data = file->private_data; -+ struct fsl_mc_device *root_mc_device; -+ struct fsl_mc_bus *mc_bus; -+ int error; -+ -+ mc_bus = container_of(priv_data->uapi, struct fsl_mc_bus, uapi_misc); -+ root_mc_device = &mc_bus->mc_dev; -+ -+ switch (cmd) { -+ case FSL_MC_SEND_MC_COMMAND: -+ error = fsl_mc_uapi_send_command(arg, priv_data->mc_io); -+ break; -+ default: -+ dev_dbg(&root_mc_device->dev, "unexpected ioctl call number\n"); -+ error = -EINVAL; -+ } -+ -+ return error; -+} -+ -+static const struct file_operations fsl_mc_uapi_dev_fops = { -+ .owner = THIS_MODULE, -+ .open = fsl_mc_uapi_dev_open, -+ .release = fsl_mc_uapi_dev_release, -+ .unlocked_ioctl = fsl_mc_uapi_dev_ioctl, -+}; -+ -+int fsl_mc_uapi_create_device_file(struct fsl_mc_bus *mc_bus) -+{ -+ struct fsl_mc_device *mc_dev = &mc_bus->mc_dev; -+ struct fsl_mc_uapi *mc_uapi = &mc_bus->uapi_misc; -+ int error; -+ -+ mc_uapi->misc.minor = MISC_DYNAMIC_MINOR; -+ mc_uapi->misc.name = dev_name(&mc_dev->dev); -+ mc_uapi->misc.fops = &fsl_mc_uapi_dev_fops; -+ -+ error = misc_register(&mc_uapi->misc); -+ if (error) -+ return error; -+ -+ mc_uapi->static_mc_io = mc_bus->mc_dev.mc_io; -+ -+ mutex_init(&mc_uapi->mutex); -+ -+ return 0; -+} -+ -+void fsl_mc_uapi_remove_device_file(struct fsl_mc_bus *mc_bus) -+{ -+ misc_deregister(&mc_bus->uapi_misc.misc); -+} -diff --git a/drivers/bus/fsl-mc/mc-sys.c b/drivers/bus/fsl-mc/mc-sys.c -index 85a0225db..14d77dc61 100644 ---- a/drivers/bus/fsl-mc/mc-sys.c -+++ b/drivers/bus/fsl-mc/mc-sys.c -@@ -19,7 +19,7 @@ - /** - * Timeout in milliseconds to wait for the completion of an MC command - */ --#define MC_CMD_COMPLETION_TIMEOUT_MS 500 -+#define MC_CMD_COMPLETION_TIMEOUT_MS 15000 - - /* - * usleep_range() min and max values used to throttle down polling -diff --git a/drivers/bus/fsl-mc/obj-api.c b/drivers/bus/fsl-mc/obj-api.c -new file mode 100644 -index 000000000..2197368de ---- /dev/null -+++ b/drivers/bus/fsl-mc/obj-api.c -@@ -0,0 +1,105 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright 2021 NXP -+ * -+ */ -+#include -+#include -+ -+#include "fsl-mc-private.h" -+ -+static int fsl_mc_get_open_cmd_id(const char *type) -+{ -+ static const struct { -+ int cmd_id; -+ const char *type; -+ } dev_ids[] = { -+ { DPRTC_CMDID_OPEN, "dprtc" }, -+ { DPRC_CMDID_OPEN, "dprc" }, -+ { DPNI_CMDID_OPEN, "dpni" }, -+ { DPIO_CMDID_OPEN, "dpio" }, -+ { DPSW_CMDID_OPEN, "dpsw" }, -+ { DPBP_CMDID_OPEN, "dpbp" }, -+ { DPCON_CMDID_OPEN, "dpcon" }, -+ { DPMCP_CMDID_OPEN, "dpmcp" }, -+ { DPMAC_CMDID_OPEN, "dpmac" }, -+ { DPSECI_CMDID_OPEN, "dpseci" }, -+ { DPDMUX_CMDID_OPEN, "dpdmux" }, -+ { DPDCEI_CMDID_OPEN, "dpdcei" }, -+ { DPAIOP_CMDID_OPEN, "dpaiop" }, -+ { DPCI_CMDID_OPEN, "dpci" }, -+ { DPDMAI_CMDID_OPEN, "dpdmai" }, -+ { DPDBG_CMDID_OPEN, "dpdbg" }, -+ { 0, NULL } -+ }; -+ int i; -+ -+ for (i = 0; dev_ids[i].type; i++) -+ if (!strcmp(dev_ids[i].type, type)) -+ return dev_ids[i].cmd_id; -+ -+ return -1; -+} -+ -+int fsl_mc_obj_open(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ int obj_id, -+ char *obj_type, -+ u16 *token) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct obj_cmd_open *cmd_params; -+ int err = 0; -+ int cmd_id = fsl_mc_get_open_cmd_id(obj_type); -+ -+ if (cmd_id == -1) -+ return -ENODEV; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(fsl_mc_get_open_cmd_id(obj_type), -+ cmd_flags, 0); -+ cmd_params = (struct obj_cmd_open *)cmd.params; -+ cmd_params->obj_id = cpu_to_le32(obj_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = mc_cmd_hdr_read_token(&cmd); -+ -+ return err; -+} -+EXPORT_SYMBOL_GPL(fsl_mc_obj_open); -+ -+int fsl_mc_obj_close(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ u16 token) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(OBJ_CMDID_CLOSE, cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+EXPORT_SYMBOL_GPL(fsl_mc_obj_close); -+ -+int fsl_mc_obj_reset(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ u16 token) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(OBJ_CMDID_RESET, cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+EXPORT_SYMBOL_GPL(fsl_mc_obj_reset); -+ -diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index c715d4681..3853ce51b 100644 ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -374,6 +374,7 @@ source "drivers/clk/mvebu/Kconfig" - source "drivers/clk/qcom/Kconfig" - source "drivers/clk/renesas/Kconfig" - source "drivers/clk/rockchip/Kconfig" -+source "drivers/clk/s32/Kconfig" - source "drivers/clk/samsung/Kconfig" - source "drivers/clk/sifive/Kconfig" - source "drivers/clk/sprd/Kconfig" -diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile -index da8fcf147..8a52da49c 100644 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -102,6 +102,7 @@ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ - obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ - obj-y += renesas/ - obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ -+obj-$(CONFIG_ARCH_S32) += s32/ - obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ - obj-$(CONFIG_CLK_SIFIVE) += sifive/ - obj-$(CONFIG_ARCH_SIRF) += sirf/ -diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c -index 61c78714c..18cfdbaab 100644 ---- a/drivers/clk/clk.c -+++ b/drivers/clk/clk.c -@@ -807,8 +807,7 @@ static void clk_core_unprepare(struct clk_core *core) - if (!core) - return; - -- if (WARN(core->prepare_count == 0, -- "%s already unprepared\n", core->name)) -+ if (core->prepare_count == 0) - return; - - if (WARN(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL, -@@ -949,7 +948,7 @@ static void clk_core_disable(struct clk_core *core) - if (!core) - return; - -- if (WARN(core->enable_count == 0, "%s already disabled\n", core->name)) -+ if (core->enable_count == 0) - return; - - if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL, -@@ -1008,8 +1007,7 @@ static int clk_core_enable(struct clk_core *core) - if (!core) - return 0; - -- if (WARN(core->prepare_count == 0, -- "Enabling unprepared %s\n", core->name)) -+ if (core->prepare_count == 0) - return -ESHUTDOWN; - - if (core->enable_count == 0) { -@@ -2495,7 +2493,8 @@ static int clk_core_set_parent_nolock(struct clk_core *core, - if (!core) - return 0; - -- if (core->parent == parent) -+ if ((core->parent == parent) && -+ !(core->flags & CLK_SET_PARENT_NOCACHE)) - return 0; - - /* verify ops for multi-parent clks */ -diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c -index 7c4f31b31..6cc1b8bb8 100644 ---- a/drivers/clk/imx/clk-composite-7ulp.c -+++ b/drivers/clk/imx/clk-composite-7ulp.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - - #include "clk.h" -@@ -22,17 +23,61 @@ - #define PCG_PCD_WIDTH 3 - #define PCG_PCD_MASK 0x7 - --struct clk_hw *imx7ulp_clk_hw_composite(const char *name, -+#define SW_RST BIT(28) -+ -+static int pcc_gate_enable(struct clk_hw *hw) -+{ -+ struct clk_gate *gate = to_clk_gate(hw); -+ unsigned long flags; -+ u32 val; -+ int ret; -+ -+ ret = clk_gate_ops.enable(hw); -+ if (ret) -+ return ret; -+ -+ spin_lock_irqsave(gate->lock, flags); -+ /* -+ * release the sw reset for peripherals associated with -+ * with this pcc clock. -+ */ -+ val = readl(gate->reg); -+ val |= SW_RST; -+ writel(val, gate->reg); -+ -+ spin_unlock_irqrestore(gate->lock, flags); -+ -+ return 0; -+} -+ -+static void pcc_gate_disable(struct clk_hw *hw) -+{ -+ clk_gate_ops.disable(hw); -+} -+ -+static int pcc_gate_is_enabled(struct clk_hw *hw) -+{ -+ return clk_gate_ops.is_enabled(hw); -+} -+ -+static const struct clk_ops pcc_gate_ops = { -+ .enable = pcc_gate_enable, -+ .disable = pcc_gate_disable, -+ .is_enabled = pcc_gate_is_enabled, -+}; -+ -+static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, - const char * const *parent_names, - int num_parents, bool mux_present, - bool rate_present, bool gate_present, -- void __iomem *reg) -+ void __iomem *reg, bool has_swrst) - { - struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL; - struct clk_fractional_divider *fd = NULL; - struct clk_gate *gate = NULL; - struct clk_mux *mux = NULL; - struct clk_hw *hw; -+ u32 val; - - if (mux_present) { - mux = kzalloc(sizeof(*mux), GFP_KERNEL); -@@ -42,6 +87,8 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, - mux->reg = reg; - mux->shift = PCG_PCS_SHIFT; - mux->mask = PCG_PCS_MASK; -+ if (has_swrst) -+ mux->lock = &imx_ccm_lock; - } - - if (rate_present) { -@@ -59,6 +106,8 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, - fd->nwidth = PCG_PCD_WIDTH; - fd->nmask = PCG_PCD_MASK; - fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED; -+ if (has_swrst) -+ fd->lock = &imx_ccm_lock; - } - - if (gate_present) { -@@ -71,13 +120,27 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, - gate_hw = &gate->hw; - gate->reg = reg; - gate->bit_idx = PCG_CGC_SHIFT; -+ if (has_swrst) -+ gate->lock = &imx_ccm_lock; -+ /* -+ * make sure clock is gated during clock tree initialization, -+ * the HW ONLY allow clock parent/rate changed with clock gated, -+ * during clock tree initialization, clocks could be enabled -+ * by bootloader, so the HW status will mismatch with clock tree -+ * prepare count, then clock core driver will allow parent/rate -+ * change since the prepare count is zero, but HW actually -+ * prevent the parent/rate change due to the clock is enabled. -+ */ -+ val = readl_relaxed(reg); -+ val &= ~(1 << PCG_CGC_SHIFT); -+ writel_relaxed(val, reg); - } - - hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, - mux_hw, &clk_mux_ops, fd_hw, - &clk_fractional_divider_ops, gate_hw, -- &clk_gate_ops, CLK_SET_RATE_GATE | -- CLK_SET_PARENT_GATE); -+ has_swrst ? &pcc_gate_ops : &clk_gate_ops, CLK_SET_RATE_GATE | -+ CLK_SET_PARENT_GATE | CLK_SET_RATE_NO_REPARENT); - if (IS_ERR(hw)) { - kfree(mux); - kfree(fd); -@@ -86,3 +149,19 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, - - return hw; - } -+ -+struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names, -+ int num_parents, bool mux_present, bool rate_present, -+ bool gate_present, void __iomem *reg) -+{ -+ return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present, -+ gate_present, reg, false); -+} -+ -+struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names, -+ int num_parents, bool mux_present, bool rate_present, -+ bool gate_present, void __iomem *reg, bool has_swrst) -+{ -+ return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present, -+ gate_present, reg, has_swrst); -+} -diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c -index 04e728538..fec34169a 100644 ---- a/drivers/clk/imx/clk-composite-8m.c -+++ b/drivers/clk/imx/clk-composite-8m.c -@@ -223,14 +223,19 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, - div->lock = &imx_ccm_lock; - div->flags = CLK_DIVIDER_ROUND_CLOSEST; - -- gate = kzalloc(sizeof(*gate), GFP_KERNEL); -- if (!gate) -- goto fail; -- -- gate_hw = &gate->hw; -- gate->reg = reg; -- gate->bit_idx = PCG_CGC_SHIFT; -- gate->lock = &imx_ccm_lock; -+ /* skip registering the gate ops if M4 is enabled */ -+ if (imx_src_is_m4_enabled()) { -+ gate_hw = NULL; -+ } else { -+ gate = kzalloc(sizeof(*gate), GFP_KERNEL); -+ if (!gate) -+ goto fail; -+ -+ gate_hw = &gate->hw; -+ gate->reg = reg; -+ gate->bit_idx = PCG_CGC_SHIFT; -+ gate->lock = &imx_ccm_lock; -+ } - - hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, - mux_hw, mux_ops, div_hw, -diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c -index 7eed7083f..0f8fb0341 100644 ---- a/drivers/clk/imx/clk-gate2.c -+++ b/drivers/clk/imx/clk-gate2.c -@@ -8,11 +8,13 @@ - - #include - #include -+#include - #include - #include - #include - #include - #include -+#include - #include "clk.h" - - /** -@@ -37,10 +39,54 @@ struct clk_gate2 { - - #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) - -+static void clk_gate2_do_hardware(struct clk_gate2 *gate, bool enable) -+{ -+ u32 reg; -+ -+ reg = readl(gate->reg); -+ if (enable) -+ reg |= gate->cgr_val << gate->bit_idx; -+ else -+ reg &= ~(gate->cgr_val << gate->bit_idx); -+ writel(reg, gate->reg); -+} -+ -+static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) -+{ -+ struct clk_gate2 *gate = to_clk_gate2(hw); -+ -+ if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { -+#ifdef CONFIG_SOC_IMX6SX -+ if (!amp_power_mutex || !shared_mem) { -+ if (enable) -+ clk_gate2_do_hardware(gate, enable); -+ return; -+ } -+ -+ imx_sema4_mutex_lock(amp_power_mutex); -+ if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || -+ shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { -+ imx_sema4_mutex_unlock(amp_power_mutex); -+ return; -+ } -+ -+ if (!imx_update_shared_mem(hw, enable)) { -+ imx_sema4_mutex_unlock(amp_power_mutex); -+ return; -+ } -+ -+ clk_gate2_do_hardware(gate, enable); -+ -+ imx_sema4_mutex_unlock(amp_power_mutex); -+#endif -+ } else { -+ clk_gate2_do_hardware(gate, enable); -+ } -+} -+ - static int clk_gate2_enable(struct clk_hw *hw) - { - struct clk_gate2 *gate = to_clk_gate2(hw); -- u32 reg; - unsigned long flags; - int ret = 0; - -@@ -49,15 +95,7 @@ static int clk_gate2_enable(struct clk_hw *hw) - if (gate->share_count && (*gate->share_count)++ > 0) - goto out; - -- if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) { -- ret = clk_gate_ops.enable(hw); -- } else { -- reg = readl(gate->reg); -- reg &= ~(3 << gate->bit_idx); -- reg |= gate->cgr_val << gate->bit_idx; -- writel(reg, gate->reg); -- } -- -+ clk_gate2_do_shared_clks(hw, true); - out: - spin_unlock_irqrestore(gate->lock, flags); - -@@ -67,7 +105,6 @@ static int clk_gate2_enable(struct clk_hw *hw) - static void clk_gate2_disable(struct clk_hw *hw) - { - struct clk_gate2 *gate = to_clk_gate2(hw); -- u32 reg; - unsigned long flags; - - spin_lock_irqsave(gate->lock, flags); -@@ -79,23 +116,16 @@ static void clk_gate2_disable(struct clk_hw *hw) - goto out; - } - -- if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) { -- clk_gate_ops.disable(hw); -- } else { -- reg = readl(gate->reg); -- reg &= ~(3 << gate->bit_idx); -- writel(reg, gate->reg); -- } -- -+ clk_gate2_do_shared_clks(hw, false); - out: - spin_unlock_irqrestore(gate->lock, flags); - } - --static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) -+static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, u8 cgr_val) - { - u32 val = readl(reg); - -- if (((val >> bit_idx) & 1) == 1) -+ if (((val >> bit_idx) & cgr_val) == 1) - return 1; - - return 0; -@@ -104,29 +134,27 @@ static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) - static int clk_gate2_is_enabled(struct clk_hw *hw) - { - struct clk_gate2 *gate = to_clk_gate2(hw); -+ unsigned long flags; -+ int ret; - -- if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) -- return clk_gate_ops.is_enabled(hw); -+ spin_lock_irqsave(gate->lock, flags); -+ -+ ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, gate->cgr_val); -+ -+ spin_unlock_irqrestore(gate->lock, flags); - -- return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); -+ return ret; - } - - static void clk_gate2_disable_unused(struct clk_hw *hw) - { - struct clk_gate2 *gate = to_clk_gate2(hw); - unsigned long flags; -- u32 reg; -- -- if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) -- return; - - spin_lock_irqsave(gate->lock, flags); - -- if (!gate->share_count || *gate->share_count == 0) { -- reg = readl(gate->reg); -- reg &= ~(3 << gate->bit_idx); -- writel(reg, gate->reg); -- } -+ if (!gate->share_count || *gate->share_count == 0) -+ clk_gate2_do_shared_clks(hw, false); - - spin_unlock_irqrestore(gate->lock, flags); - } -diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c -index 711bd2294..61db2de25 100644 ---- a/drivers/clk/imx/clk-imx8mm.c -+++ b/drivers/clk/imx/clk-imx8mm.c -@@ -4,7 +4,9 @@ - */ - - #include -+#include - #include -+#include - #include - #include - #include -@@ -12,6 +14,7 @@ - #include - #include - #include -+#include - - #include "clk.h" - -@@ -291,6 +294,34 @@ static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_ - static struct clk_hw_onecell_data *clk_hw_data; - static struct clk_hw **hws; - -+static int imx_clk_init_on(struct device_node *np, -+ struct clk_hw * const clks[]) -+{ -+ u32 *array; -+ int i, ret, elems; -+ -+ elems = of_property_count_u32_elems(np, "init-on-array"); -+ if (elems < 0) -+ return elems; -+ array = kcalloc(elems, sizeof(elems), GFP_KERNEL); -+ if (!array) -+ return -ENOMEM; -+ -+ ret = of_property_read_u32_array(np, "init-on-array", array, elems); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < elems; i++) { -+ ret = clk_prepare_enable(clks[array[i]]->clk); -+ if (ret) -+ pr_err("clk_prepare_enable failed %d\n", array[i]); -+ } -+ -+ kfree(array); -+ -+ return 0; -+} -+ - static int imx8mm_clocks_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -298,6 +329,8 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) - void __iomem *base; - int ret; - -+ check_m4_enabled(); -+ - clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, - IMX8MM_CLK_END), GFP_KERNEL); - if (WARN_ON(!clk_hw_data)) -@@ -361,45 +394,29 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) - hws[IMX8MM_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); - - /* SYS PLL1 fixed output */ -- hws[IMX8MM_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27); -- hws[IMX8MM_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25); -- hws[IMX8MM_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23); -- hws[IMX8MM_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21); -- hws[IMX8MM_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19); -- hws[IMX8MM_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17); -- hws[IMX8MM_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15); -- hws[IMX8MM_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13); - hws[IMX8MM_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - -- hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20); -- hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10); -- hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8); -- hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6); -- hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5); -- hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4); -- hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3); -- hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2); -+ hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); -+ hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); -+ hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); -+ hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); -+ hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); -+ hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); -+ hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); -+ hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); - hws[IMX8MM_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); - - /* SYS PLL2 fixed output */ -- hws[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27); -- hws[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25); -- hws[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23); -- hws[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21); -- hws[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19); -- hws[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17); -- hws[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15); -- hws[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13); - hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - -- hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20); -- hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10); -- hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8); -- hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6); -- hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5); -- hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4); -- hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3); -- hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2); -+ hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); -+ hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); -+ hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); -+ hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); -+ hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); -+ hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); -+ hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); -+ hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); - hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); - - np = dev->of_node; -@@ -437,7 +454,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) - /* BUS */ - hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); - hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); -- hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); -+ hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); - hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980); - hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00); - hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80); -@@ -565,7 +582,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) - hws[IMX8MM_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); - hws[IMX8MM_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); - hws[IMX8MM_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); -- hws[IMX8MM_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); -+ hws[IMX8MM_CLK_SNVS_ROOT] = imx_clk_hw_gate2_flags("snvs_root_clk", "ipg_root", base + 0x4470, 0, CLK_IS_CRITICAL); - hws[IMX8MM_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); - hws[IMX8MM_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); - hws[IMX8MM_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); -@@ -615,6 +632,12 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) - goto unregister_hws; - } - -+ imx_clk_init_on(np, hws); -+ -+ clk_set_parent(hws[IMX8MM_CLK_CSI1_CORE]->clk, hws[IMX8MM_SYS_PLL2_1000M]->clk); -+ clk_set_parent(hws[IMX8MM_CLK_CSI1_PHY_REF]->clk, hws[IMX8MM_SYS_PLL2_1000M]->clk); -+ clk_set_parent(hws[IMX8MM_CLK_CSI1_ESC]->clk, hws[IMX8MM_SYS_PLL1_800M]->clk); -+ - imx_register_uart_clocks(4); - - return 0; -@@ -645,6 +668,81 @@ static struct platform_driver imx8mm_clk_driver = { - }; - module_platform_driver(imx8mm_clk_driver); - -+/* -+ * Debugfs interface for audio PLL K divider change dynamically. -+ * Monitor control for the Audio PLL K-Divider -+ */ -+#ifdef CONFIG_DEBUG_FS -+ -+#define KDIV_MASK GENMASK(15, 0) -+#define MDIV_SHIFT 12 -+#define MDIV_MASK GENMASK(21, 12) -+#define PDIV_SHIFT 4 -+#define PDIV_MASK GENMASK(9, 4) -+#define SDIV_SHIFT 0 -+#define SDIV_MASK GENMASK(2, 0) -+ -+static int pll_delta_k_set(void *data, u64 val) -+{ -+ struct clk_hw *hw; -+ short int delta_k; -+ -+ hw = data; -+ delta_k = (short int) (val & KDIV_MASK); -+ -+ clk_set_delta_k(hw, val); -+ -+ pr_debug("the delta k is %d\n", delta_k); -+ return 0; -+} -+DEFINE_DEBUGFS_ATTRIBUTE(delta_k_fops, NULL, pll_delta_k_set, "%lld\n"); -+ -+static int pll_setting_show(struct seq_file *s, void *data) -+{ -+ struct clk_hw *hw; -+ u32 pll_div_ctrl0, pll_div_ctrl1; -+ u32 mdiv, pdiv, sdiv, kdiv; -+ -+ hw = s->private;; -+ -+ clk_get_pll_setting(hw, &pll_div_ctrl0, &pll_div_ctrl1); -+ mdiv = (pll_div_ctrl0 & MDIV_MASK) >> MDIV_SHIFT; -+ pdiv = (pll_div_ctrl0 & PDIV_MASK) >> PDIV_SHIFT; -+ sdiv = (pll_div_ctrl0 & SDIV_MASK) >> SDIV_SHIFT; -+ kdiv = (pll_div_ctrl1 & KDIV_MASK); -+ -+ seq_printf(s, "Mdiv: 0x%x; Pdiv: 0x%x; Sdiv: 0x%x; Kdiv: 0x%x\n", -+ mdiv, pdiv, sdiv, kdiv); -+ -+ return 0; -+} -+DEFINE_SHOW_ATTRIBUTE(pll_setting); -+ -+static int __init pll_debug_init(void) -+{ -+ struct dentry *root, *audio_pll1, *audio_pll2; -+ -+ if (of_machine_is_compatible("fsl,imx8mm") && hws) { -+ /* create a root dir for audio pll monitor */ -+ root = debugfs_create_dir("audio_pll_monitor", NULL); -+ audio_pll1 = debugfs_create_dir("audio_pll1", root); -+ audio_pll2 = debugfs_create_dir("audio_pll2", root); -+ -+ debugfs_create_file_unsafe("delta_k", 0444, audio_pll1, -+ hws[IMX8MM_AUDIO_PLL1], &delta_k_fops); -+ debugfs_create_file("pll_parameter", 0x444, audio_pll1, -+ hws[IMX8MM_AUDIO_PLL1], &pll_setting_fops); -+ debugfs_create_file_unsafe("delta_k", 0444, audio_pll2, -+ hws[IMX8MM_AUDIO_PLL2], &delta_k_fops); -+ debugfs_create_file("pll_parameter", 0x444, audio_pll2, -+ hws[IMX8MM_AUDIO_PLL2], &pll_setting_fops); -+ } -+ -+ return 0; -+} -+late_initcall(pll_debug_init); -+#endif /* CONFIG_DEBUG_FS */ -+ - MODULE_AUTHOR("Bai Ping "); - MODULE_DESCRIPTION("NXP i.MX8MM clock driver"); - MODULE_LICENSE("GPL v2"); -diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c -index 33a7ddc23..d54d3c52c 100644 ---- a/drivers/clk/imx/clk-imx8mn.c -+++ b/drivers/clk/imx/clk-imx8mn.c -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -12,6 +13,7 @@ - #include - #include - #include -+#include - - #include "clk.h" - -@@ -284,6 +286,34 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy - static struct clk_hw_onecell_data *clk_hw_data; - static struct clk_hw **hws; - -+static int imx_clk_init_on(struct device_node *np, -+ struct clk_hw * const clks[]) -+{ -+ u32 *array; -+ int i, ret, elems; -+ -+ elems = of_property_count_u32_elems(np, "init-on-array"); -+ if (elems < 0) -+ return elems; -+ array = kcalloc(elems, sizeof(elems), GFP_KERNEL); -+ if (!array) -+ return -ENOMEM; -+ -+ ret = of_property_read_u32_array(np, "init-on-array", array, elems); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < elems; i++) { -+ ret = clk_prepare_enable(clks[array[i]]->clk); -+ if (ret) -+ pr_err("clk_prepare_enable failed %d\n", array[i]); -+ } -+ -+ kfree(array); -+ -+ return 0; -+} -+ - static int imx8mn_clocks_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -291,6 +321,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) - void __iomem *base; - int ret; - -+ check_m4_enabled(); -+ - clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, - IMX8MN_CLK_END), GFP_KERNEL); - if (WARN_ON(!clk_hw_data)) -@@ -356,45 +388,29 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) - hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); - - /* SYS PLL1 fixed output */ -- hws[IMX8MN_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27); -- hws[IMX8MN_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25); -- hws[IMX8MN_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23); -- hws[IMX8MN_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21); -- hws[IMX8MN_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19); -- hws[IMX8MN_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17); -- hws[IMX8MN_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15); -- hws[IMX8MN_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13); - hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - -- hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20); -- hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10); -- hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8); -- hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6); -- hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5); -- hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4); -- hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3); -- hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2); -+ hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); -+ hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); -+ hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); -+ hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); -+ hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); -+ hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); -+ hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); -+ hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); - hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); - - /* SYS PLL2 fixed output */ -- hws[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27); -- hws[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25); -- hws[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23); -- hws[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21); -- hws[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19); -- hws[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17); -- hws[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15); -- hws[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13); - hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - -- hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20); -- hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10); -- hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8); -- hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6); -- hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5); -- hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4); -- hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3); -- hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2); -+ hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); -+ hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); -+ hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); -+ hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); -+ hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); -+ hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); -+ hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); -+ hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); - hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); - - np = dev->of_node; -@@ -523,7 +539,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) - hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); - hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); - hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); -- hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); -+ hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate2_flags("snvs_root_clk", "ipg_root", base + 0x4470, 0, CLK_IS_CRITICAL); - hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); - hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); - hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); -@@ -549,6 +565,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) - hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); - hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); - hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7); -+ hws[IMX8MN_CLK_SAI7_IPG] = imx_clk_hw_gate2_shared2("sai7_ipg_clk", "ipg_audio_root", base + 0x4650, 0, &share_count_sai7); - - hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4); - -@@ -566,6 +583,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) - goto unregister_hws; - } - -+ imx_clk_init_on(np, hws); -+ -+ clk_set_parent(hws[IMX8MN_CLK_AUDIO_AHB]->clk, hws[IMX8MN_SYS_PLL1_800M]->clk); -+ clk_set_rate(hws[IMX8MN_CLK_AUDIO_AHB]->clk, 400000000); -+ clk_set_rate(hws[IMX8MN_CLK_IPG_AUDIO_ROOT]->clk, 400000000); -+ - imx_register_uart_clocks(4); - - return 0; -diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c -index f679e5cc3..bf2fc15a7 100644 ---- a/drivers/clk/imx/clk-imx8mq.c -+++ b/drivers/clk/imx/clk-imx8mq.c -@@ -5,6 +5,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -13,6 +14,8 @@ - #include - #include - #include -+#include -+#include - - #include "clk.h" - -@@ -25,7 +28,7 @@ static u32 share_count_sai6; - static u32 share_count_dcss; - static u32 share_count_nand; - --static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; -+static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "phy_27m", "dummy", }; - static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; - static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; - static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; -@@ -113,12 +116,12 @@ static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", " - static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", }; - - static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", -- "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", }; -+ "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", }; - - static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", }; - --static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out", -+static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out", - "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; - - static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", }; -@@ -273,6 +276,34 @@ static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sy - static struct clk_hw_onecell_data *clk_hw_data; - static struct clk_hw **hws; - -+static int imx_clk_init_on(struct device_node *np, -+ struct clk_hw * const clks[]) -+{ -+ u32 *array; -+ int i, ret, elems; -+ -+ elems = of_property_count_u32_elems(np, "init-on-array"); -+ if (elems < 0) -+ return elems; -+ array = kzalloc(elems * sizeof(elems), GFP_KERNEL); -+ if (!array) -+ return -ENOMEM; -+ -+ ret = of_property_read_u32_array(np, "init-on-array", array, elems); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < elems; i++) { -+ ret = clk_prepare_enable(clks[array[i]]->clk); -+ if (ret) -+ pr_err("clk_prepare_enable failed %d\n", array[i]); -+ } -+ -+ kfree(array); -+ -+ return 0; -+} -+ - static int imx8mq_clocks_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -280,6 +311,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) - void __iomem *base; - int err; - -+ check_m4_enabled(); -+ - clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, - IMX8MQ_CLK_END), GFP_KERNEL); - if (WARN_ON(!clk_hw_data)) -@@ -296,6 +329,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) - hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); -+ hws[IMX8MQ_CLK_PHY_27MHZ] = imx_clk_hw_fixed("phy_27m", 27000000); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); - base = of_iomap(np, 0); -@@ -335,6 +369,13 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) - hws[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); - hws[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); - -+ /* unbypass all the plls */ -+ clk_set_parent(hws[IMX8MQ_GPU_PLL_BYPASS]->clk, hws[IMX8MQ_GPU_PLL]->clk); -+ clk_set_parent(hws[IMX8MQ_VPU_PLL_BYPASS]->clk, hws[IMX8MQ_VPU_PLL]->clk); -+ clk_set_parent(hws[IMX8MQ_AUDIO_PLL1_BYPASS]->clk, hws[IMX8MQ_AUDIO_PLL1]->clk); -+ clk_set_parent(hws[IMX8MQ_AUDIO_PLL2_BYPASS]->clk, hws[IMX8MQ_AUDIO_PLL2]->clk); -+ clk_set_parent(hws[IMX8MQ_VIDEO_PLL1_BYPASS]->clk, hws[IMX8MQ_VIDEO_PLL1]->clk); -+ - /* PLL OUT GATE */ - hws[IMX8MQ_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21); - hws[IMX8MQ_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21); -@@ -535,7 +576,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) - hws[IMX8MQ_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); - hws[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); - hws[IMX8MQ_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); -- hws[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); -+ hws[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_hw_gate2_flags("snvs_root_clk", "ipg_root", base + 0x4470, 0, CLK_IS_CRITICAL); - hws[IMX8MQ_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); - hws[IMX8MQ_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); - hws[IMX8MQ_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); -@@ -580,6 +621,16 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) - goto unregister_hws; - } - -+ /* enable all the clocks just for bringup */ -+ imx_clk_init_on(np, hws); -+ -+ clk_set_parent(hws[IMX8MQ_CLK_CSI1_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_CSI1_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_CSI1_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_CSI2_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_CSI2_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_CSI2_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); -+ - imx_register_uart_clocks(4); - - return 0; -diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c -index 5d2a9a3be..6c39b8c5a 100644 ---- a/drivers/clk/imx/clk-pfd.c -+++ b/drivers/clk/imx/clk-pfd.c -@@ -5,9 +5,11 @@ - */ - - #include -+#include - #include - #include - #include -+#include - #include "clk.h" - - /** -@@ -32,20 +34,57 @@ struct clk_pfd { - #define CLR 0x8 - #define OTG 0xc - --static int clk_pfd_enable(struct clk_hw *hw) -+static void clk_pfd_do_hardware(struct clk_pfd *pfd, bool enable) -+{ -+ if (enable) -+ writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); -+ else -+ writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); -+} -+ -+static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable) - { - struct clk_pfd *pfd = to_clk_pfd(hw); - -- writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); -+ if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { -+#ifdef CONFIG_SOC_IMX6SX -+ if (!amp_power_mutex || !shared_mem) { -+ if (enable) -+ clk_pfd_do_hardware(pfd, enable); -+ return; -+ } -+ -+ imx_sema4_mutex_lock(amp_power_mutex); -+ if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || -+ shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { -+ imx_sema4_mutex_unlock(amp_power_mutex); -+ return; -+ } -+ -+ if (!imx_update_shared_mem(hw, enable)) { -+ imx_sema4_mutex_unlock(amp_power_mutex); -+ return; -+ } -+ -+ clk_pfd_do_hardware(pfd, enable); -+ -+ imx_sema4_mutex_unlock(amp_power_mutex); -+#endif -+ } else { -+ clk_pfd_do_hardware(pfd, enable); -+ } -+} -+ -+static int clk_pfd_enable(struct clk_hw *hw) -+{ -+ clk_pfd_do_shared_clks(hw, true); - - return 0; - } - - static void clk_pfd_disable(struct clk_hw *hw) - { -- struct clk_pfd *pfd = to_clk_pfd(hw); -- -- writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); -+ clk_pfd_do_shared_clks(hw, false); - } - - static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, -diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c -index 6b744c842..42505669c 100644 ---- a/drivers/clk/imx/clk-pfdv2.c -+++ b/drivers/clk/imx/clk-pfdv2.c -@@ -161,8 +161,17 @@ static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate, - if (!rate) - return -EINVAL; - -- /* PFD can NOT change rate without gating */ -- WARN_ON(clk_pfdv2_is_enabled(hw)); -+ /* -+ * PFD can NOT change rate without gating. -+ * as the PFDs may enabled in HW by default but no -+ * consumer used it, the enable count is '0', so the -+ * 'SET_RATE_GATE' can NOT help on blocking the set_rate -+ * ops especially for 'assigned-clock-xxx'. In order -+ * to simplify the case, just disable the PFD if it is -+ * enabled in HW but not in SW. -+ */ -+ if (clk_pfdv2_is_enabled(hw)) -+ clk_pfdv2_disable(hw); - - tmp = tmp * 18 + rate / 2; - do_div(tmp, rate); -@@ -191,8 +200,8 @@ static const struct clk_ops clk_pfdv2_ops = { - .is_enabled = clk_pfdv2_is_enabled, - }; - --struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name, -- void __iomem *reg, u8 idx) -+struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name, -+ const char *parent_name, void __iomem *reg, u8 idx) - { - struct clk_init_data init; - struct clk_pfdv2 *pfd; -@@ -214,7 +223,10 @@ struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name, - init.ops = &clk_pfdv2_ops; - init.parent_names = &parent_name; - init.num_parents = 1; -- init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; -+ if (type == IMX_PFDV2_IMX7ULP) -+ init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; -+ else -+ init.flags = CLK_SET_RATE_GATE; - - pfd->hw.init = &init; - -diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c -index aba36e421..f7cfc5fea 100644 ---- a/drivers/clk/imx/clk-pll14xx.c -+++ b/drivers/clk/imx/clk-pll14xx.c -@@ -137,9 +137,12 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { - struct clk_pll14xx *pll = to_clk_pll14xx(hw); -+ const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; - u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; - short int kdiv; - u64 fvco = parent_rate; -+ long rate = 0; -+ int i; - - pll_div_ctl0 = readl_relaxed(pll->base + 4); - pll_div_ctl1 = readl_relaxed(pll->base + 8); -@@ -148,13 +151,25 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, - sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; - kdiv = pll_div_ctl1 & KDIV_MASK; - -+ /* -+ * Sometimes, the recalculated rate has deviation due to -+ * the frac part. So find the accurate pll rate from the table -+ * first, if no match rate in the table, use the rate calculated -+ * from the equation below. -+ */ -+ for (i = 0; i < pll->rate_count; i++) { -+ if (rate_table[i].pdiv == pdiv && rate_table[i].mdiv == mdiv && -+ rate_table[i].sdiv == sdiv && rate_table[i].kdiv == kdiv) -+ rate = rate_table[i].rate; -+ } -+ - /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ - fvco *= (mdiv * 65536 + kdiv); - pdiv *= 65536; - - do_div(fvco, pdiv << sdiv); - -- return fvco; -+ return rate ? (unsigned long) rate : (unsigned long)fvco; - } - - static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate, -@@ -360,6 +375,26 @@ static void clk_pll14xx_unprepare(struct clk_hw *hw) - writel_relaxed(val, pll->base + GNRL_CTL); - } - -+void clk_set_delta_k(struct clk_hw *hw, short int delta_k) -+{ -+ struct clk_pll14xx *pll = to_clk_pll14xx(hw); -+ short int k; -+ u32 val; -+ -+ val = readl_relaxed(pll->base + 8); -+ k = (val & KDIV_MASK) + delta_k; -+ writel_relaxed(k << KDIV_SHIFT, pll->base + 8); -+} -+ -+void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0, -+ u32 *pll_div_ctrl1) -+{ -+ struct clk_pll14xx *pll = to_clk_pll14xx(hw); -+ -+ *pll_div_ctrl0 = readl_relaxed(pll->base + 4); -+ *pll_div_ctrl1 = readl_relaxed(pll->base + 8); -+} -+ - static const struct clk_ops clk_pll1416x_ops = { - .prepare = clk_pll14xx_prepare, - .unprepare = clk_pll14xx_unprepare, -diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c -index 20ee9611b..5fd4765e6 100644 ---- a/drivers/clk/imx/clk-pllv3.c -+++ b/drivers/clk/imx/clk-pllv3.c -@@ -8,9 +8,11 @@ - #include - #include - #include -+#include - #include - #include - #include -+#include - #include "clk.h" - - #define PLL_NUM_OFFSET 0x10 -@@ -65,36 +67,82 @@ static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) - if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) - return 0; - -- return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, -- 500, PLL_LOCK_TIMEOUT); -+ if (!(imx_src_is_m4_enabled() && clk_on_imx6sx())) -+ return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, -+ 500, PLL_LOCK_TIMEOUT); -+ else -+ return readl_relaxed_poll_timeout_atomic(pll->base, val, val & BM_PLL_LOCK, -+ 10, PLL_LOCK_TIMEOUT); - } - --static int clk_pllv3_prepare(struct clk_hw *hw) -+static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) - { - struct clk_pllv3 *pll = to_clk_pllv3(hw); -+ int ret; - u32 val; - - val = readl_relaxed(pll->base); -- if (pll->powerup_set) -- val |= pll->power_bit; -- else -- val &= ~pll->power_bit; -- writel_relaxed(val, pll->base); -+ if (enable) { -+ if (pll->powerup_set) -+ val |= pll->power_bit; -+ else -+ val &= ~pll->power_bit; -+ writel_relaxed(val, pll->base); -+ -+ ret = clk_pllv3_wait_lock(pll); -+ if (ret) -+ return ret; -+ } else { -+ if (pll->powerup_set) -+ val &= ~pll->power_bit; -+ else -+ val |= pll->power_bit; -+ writel_relaxed(val, pll->base); -+ } - -- return clk_pllv3_wait_lock(pll); -+ return 0; - } - --static void clk_pllv3_unprepare(struct clk_hw *hw) -+static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable) - { -- struct clk_pllv3 *pll = to_clk_pllv3(hw); -- u32 val; -+ if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { -+#ifdef CONFIG_SOC_IMX6SX -+ if (!amp_power_mutex || !shared_mem) { -+ if (enable) -+ clk_pllv3_do_hardware(hw, enable); -+ return; -+ } -+ -+ imx_sema4_mutex_lock(amp_power_mutex); -+ if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || -+ shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { -+ imx_sema4_mutex_unlock(amp_power_mutex); -+ return; -+ } -+ -+ if (!imx_update_shared_mem(hw, enable)) { -+ imx_sema4_mutex_unlock(amp_power_mutex); -+ return; -+ } -+ clk_pllv3_do_hardware(hw, enable); -+ -+ imx_sema4_mutex_unlock(amp_power_mutex); -+#endif -+ } else { -+ clk_pllv3_do_hardware(hw, enable); -+ } -+} - -- val = readl_relaxed(pll->base); -- if (pll->powerup_set) -- val &= ~pll->power_bit; -- else -- val |= pll->power_bit; -- writel_relaxed(val, pll->base); -+static int clk_pllv3_prepare(struct clk_hw *hw) -+{ -+ clk_pllv3_do_shared_clks(hw, true); -+ -+ return 0; -+} -+ -+static void clk_pllv3_unprepare(struct clk_hw *hw) -+{ -+ clk_pllv3_do_shared_clks(hw, false); - } - - static int clk_pllv3_is_prepared(struct clk_hw *hw) -diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c -index 8ec703f27..3c750ccbe 100644 ---- a/drivers/clk/imx/clk-pllv4.c -+++ b/drivers/clk/imx/clk-pllv4.c -@@ -23,14 +23,17 @@ - - /* PLL Configuration Register (xPLLCFG) */ - #define PLL_CFG_OFFSET 0x08 -+#define IMX8ULP_PLL_CFG_OFFSET 0x10 - #define BP_PLL_MULT 16 - #define BM_PLL_MULT (0x7f << 16) - - /* PLL Numerator Register (xPLLNUM) */ - #define PLL_NUM_OFFSET 0x10 -+#define IMX8ULP_PLL_NUM_OFFSET 0x1c - - /* PLL Denominator Register (xPLLDENOM) */ - #define PLL_DENOM_OFFSET 0x14 -+#define IMX8ULP_PLL_DENOM_OFFSET 0x18 - - #define MAX_MFD 0x3fffffff - #define DEFAULT_MFD 1000000 -@@ -38,6 +41,9 @@ - struct clk_pllv4 { - struct clk_hw hw; - void __iomem *base; -+ u32 cfg_offset; -+ u32 num_offset; -+ u32 denom_offset; - }; - - /* Valid PLL MULT Table */ -@@ -72,12 +78,12 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, - u32 mult, mfn, mfd; - u64 temp64; - -- mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); -+ mult = readl_relaxed(pll->base + pll->cfg_offset); - mult &= BM_PLL_MULT; - mult >>= BP_PLL_MULT; - -- mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); -- mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); -+ mfn = readl_relaxed(pll->base + pll->num_offset); -+ mfd = readl_relaxed(pll->base + pll->denom_offset); - temp64 = parent_rate; - temp64 *= mfn; - do_div(temp64, mfd); -@@ -165,13 +171,13 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, - do_div(temp64, parent_rate); - mfn = temp64; - -- val = readl_relaxed(pll->base + PLL_CFG_OFFSET); -+ val = readl_relaxed(pll->base + pll->cfg_offset); - val &= ~BM_PLL_MULT; - val |= mult << BP_PLL_MULT; -- writel_relaxed(val, pll->base + PLL_CFG_OFFSET); -+ writel_relaxed(val, pll->base + pll->cfg_offset); - -- writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); -- writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); -+ writel_relaxed(mfn, pll->base + pll->num_offset); -+ writel_relaxed(mfd, pll->base + pll->denom_offset); - - return 0; - } -@@ -207,8 +213,8 @@ static const struct clk_ops clk_pllv4_ops = { - .is_prepared = clk_pllv4_is_prepared, - }; - --struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, -- void __iomem *base) -+struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, -+ const char *parent_name, void __iomem *base) - { - struct clk_pllv4 *pll; - struct clk_hw *hw; -@@ -221,6 +227,16 @@ struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, - - pll->base = base; - -+ if (type == IMX_PLLV4_IMX8ULP) { -+ pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET; -+ pll->num_offset = IMX8ULP_PLL_NUM_OFFSET; -+ pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET; -+ } else { -+ pll->cfg_offset = PLL_CFG_OFFSET; -+ pll->num_offset = PLL_NUM_OFFSET; -+ pll->denom_offset = PLL_DENOM_OFFSET; -+ } -+ - init.name = name; - init.ops = &clk_pllv4_ops; - init.parent_names = &parent_name; -diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c -index 7cc669934..c323ddbbb 100644 ---- a/drivers/clk/imx/clk.c -+++ b/drivers/clk/imx/clk.c -@@ -17,6 +17,8 @@ - DEFINE_SPINLOCK(imx_ccm_lock); - EXPORT_SYMBOL_GPL(imx_ccm_lock); - -+bool uart_from_osc; -+ - void imx_unregister_clocks(struct clk *clks[], unsigned int count) - { - unsigned int i; -@@ -207,6 +209,14 @@ static int __init imx_clk_disable_uart(void) - return 0; - } - late_initcall_sync(imx_clk_disable_uart); -+ -+static int __init setup_uart_clk(char *uart_rate) -+{ -+ uart_from_osc = true; -+ return 1; -+} -+__setup("uart_from_osc", setup_uart_clk); -+ - #endif - - MODULE_LICENSE("GPL v2"); -diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h -index c66e00e87..7f82eea83 100644 ---- a/drivers/clk/imx/clk.h -+++ b/drivers/clk/imx/clk.h -@@ -5,8 +5,7 @@ - #include - #include - #include -- --#define IMX_CLK_GATE2_SINGLE_BIT 1 -+#include - - extern spinlock_t imx_ccm_lock; - -@@ -24,6 +23,9 @@ void imx_unregister_clocks(struct clk *clks[], unsigned int count); - void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); - - extern void imx_cscmr1_fixup(u32 *val); -+extern struct imx_sema4_mutex *amp_power_mutex; -+extern struct imx_shared_mem *shared_mem; -+extern bool uart_from_osc; - - enum imx_pllv1_type { - IMX_PLLV1_IMX1, -@@ -44,6 +46,16 @@ enum imx_pll14xx_type { - PLL_1443X, - }; - -+enum imx_pllv4_type { -+ IMX_PLLV4_IMX7ULP, -+ IMX_PLLV4_IMX8ULP, -+}; -+ -+enum imx_pfdv2_type { -+ IMX_PFDV2_IMX7ULP, -+ IMX_PFDV2_IMX8ULP, -+}; -+ - /* NOTE: Rate table should be kept sorted in descending order. */ - struct imx_pll14xx_rate_table { - unsigned int rate; -@@ -173,6 +185,25 @@ enum imx_pllv3_type { - IMX_PLLV3_AV_IMX7, - }; - -+#define MAX_SHARED_CLK_NUMBER 100 -+#define SHARED_MEM_MAGIC_NUMBER 0x12345678 -+#define MCC_POWER_SHMEM_NUMBER (6) -+ -+struct imx_shared_clk { -+ struct clk *self; -+ struct clk *parent; -+ void *m4_clk; -+ void *m4_clk_parent; -+ u8 ca9_enabled; -+ u8 cm4_enabled; -+}; -+ -+struct imx_shared_mem { -+ u32 ca9_valid; -+ u32 cm4_valid; -+ struct imx_shared_clk imx_clk[MAX_SHARED_CLK_NUMBER]; -+}; -+ - struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, u32 div_mask); - -@@ -193,8 +224,8 @@ struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, - .kdiv = (_k), \ - } - --struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, -- void __iomem *base); -+struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, -+ const char *parent_name, void __iomem *base); - - struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, -@@ -217,8 +248,8 @@ struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, - struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name, - void __iomem *reg, u8 idx); - --struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name, -- void __iomem *reg, u8 idx); -+struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name, -+ const char *parent_name, void __iomem *reg, u8 idx); - - struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name, - void __iomem *reg, u8 shift, u8 width, -@@ -228,12 +259,25 @@ struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift - u8 width, void __iomem *busy_reg, u8 busy_shift, - const char * const *parent_names, int num_parents); - -+int imx_update_shared_mem(struct clk_hw *hw, bool enable); -+ -+static inline int clk_on_imx6sx(void) -+{ -+ return of_machine_is_compatible("fsl,imx6sx"); -+} -+ - struct clk_hw *imx7ulp_clk_hw_composite(const char *name, - const char * const *parent_names, - int num_parents, bool mux_present, - bool rate_present, bool gate_present, - void __iomem *reg); - -+struct clk_hw *imx8ulp_clk_hw_composite(const char *name, -+ const char * const *parent_names, -+ int num_parents, bool mux_present, -+ bool rate_present, bool gate_present, -+ void __iomem *reg, bool has_swrst); -+ - struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width, - void (*fixup)(u32 *val)); -@@ -286,6 +330,15 @@ static inline struct clk_hw *imx_clk_hw_divider(const char *name, - reg, shift, width, 0, &imx_ccm_lock); - } - -+static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name, -+ const char *parent, -+ void __iomem *reg, u8 shift, -+ u8 width) -+{ -+ return clk_hw_register_divider(NULL, name, parent, 0, -+ reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock); -+} -+ - static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, - const char *parent, - void __iomem *reg, u8 shift, -@@ -383,10 +436,8 @@ static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev, - void __iomem *reg, u8 shift, - unsigned int *share_count) - { -- return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | -- CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, -- IMX_CLK_GATE2_SINGLE_BIT, -- &imx_ccm_lock, share_count); -+ return clk_hw_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg, -+ shift, 0x1, 0, &imx_ccm_lock, share_count); - } - - static inline struct clk *imx_clk_gate2_cgr(const char *name, -@@ -399,7 +450,17 @@ static inline struct clk *imx_clk_gate2_cgr(const char *name, - static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent, - void __iomem *reg, u8 shift) - { -- return clk_hw_register_gate(NULL, name, parent, -+ /* -+ * per design team's suggestion, clk root is NOT consuming -+ * much power, and clk root enable/disable does NOT have domain -+ * control, so they suggest to leave clk root always on when -+ * M4 is enabled. -+ */ -+ if (imx_src_is_m4_enabled()) -+ return clk_hw_register_fixed_factor(NULL, name, parent, -+ CLK_SET_RATE_PARENT, 1, 1); -+ else -+ return clk_hw_register_gate(NULL, name, parent, - CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, - reg, shift, 0, &imx_ccm_lock); - } -@@ -454,6 +515,15 @@ static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev, - reg, shift, width, 0, &imx_ccm_lock); - } - -+static inline struct clk *imx_dev_clk_mux(struct device *dev, const char *name, -+ void __iomem *reg, u8 shift, u8 width, -+ const char * const *parents, int num_parents) -+{ -+ return clk_register_mux(dev, name, parents, num_parents, -+ CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, -+ reg, shift, width, 0, &imx_ccm_lock); -+} -+ - static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, - u8 shift, u8 width, const char * const *parents, - int num_parents) -@@ -601,4 +671,7 @@ struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name - unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags, const struct clk_div_table *table, - spinlock_t *lock); -+ -+void clk_set_delta_k(struct clk_hw *hw, short int delta_k); -+void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0, u32 *pll_div_ctrl1); - #endif -diff --git a/drivers/clk/s32/Kconfig b/drivers/clk/s32/Kconfig -new file mode 100644 -index 000000000..c28bdbbfa ---- /dev/null -+++ b/drivers/clk/s32/Kconfig -@@ -0,0 +1,4 @@ -+config ARCH_S32_CLK -+ bool "Enable S32 CLK Framework" -+ help -+ Support for the Clock Framework on S32 SoCs. -diff --git a/drivers/clk/s32/Makefile b/drivers/clk/s32/Makefile -new file mode 100644 -index 000000000..169b8b590 ---- /dev/null -+++ b/drivers/clk/s32/Makefile -@@ -0,0 +1,2 @@ -+obj-$(CONFIG_ARCH_S32_CLK) += clk-core.o -+obj-$(CONFIG_ARCH_S32_CLK) += s32v234/ -diff --git a/drivers/clk/s32/clk-core.c b/drivers/clk/s32/clk-core.c -new file mode 100644 -index 000000000..a8cca66f7 ---- /dev/null -+++ b/drivers/clk/s32/clk-core.c -@@ -0,0 +1,53 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright 2015 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk.h" -+ -+void __init s32_check_clocks(struct clk *clks[], unsigned int count) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < count; i++) -+ if (IS_ERR(clks[i])) -+ pr_err("S32 clk %u: register failed with %ld\n", -+ i, PTR_ERR(clks[i])); -+} -+ -+static struct clk * __init s32_obtain_fixed_clock_from_dt(const char *name) -+{ -+ struct of_phandle_args phandle; -+ struct clk *clk = ERR_PTR(-ENODEV); -+ char *path; -+ -+ path = kasprintf(GFP_KERNEL, "/clocks/%s", name); -+ if (!path) -+ return ERR_PTR(-ENOMEM); -+ -+ phandle.np = of_find_node_by_path(path); -+ kfree(path); -+ -+ if (phandle.np) { -+ clk = of_clk_get_from_provider(&phandle); -+ of_node_put(phandle.np); -+ } -+ return clk; -+} -+ -+struct clk * __init s32_obtain_fixed_clock( -+ const char *name, unsigned long rate) -+{ -+ struct clk *clk; -+ -+ clk = s32_obtain_fixed_clock_from_dt(name); -+ if (IS_ERR(clk)) -+ clk = s32_clk_fixed(name, rate); -+ return clk; -+} -diff --git a/drivers/clk/s32/clk.h b/drivers/clk/s32/clk.h -new file mode 100644 -index 000000000..831006411 ---- /dev/null -+++ b/drivers/clk/s32/clk.h -@@ -0,0 +1,55 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2018 NXP -+ */ -+ -+#ifndef __MACH_S32_CLK_H -+#define __MACH_S32_CLK_H -+ -+#include -+#include -+ -+#define PNAME(x) \ -+ static const char *x[] __initconst -+ -+void s32_check_clocks(struct clk *clks[], unsigned int count); -+ -+struct clk *s32_obtain_fixed_clock( -+ const char *name, unsigned long rate); -+ -+static inline struct clk *s32_clk_fixed(const char *name, unsigned long rate) -+{ -+ return clk_register_fixed_rate(NULL, name, NULL, 0, rate); -+} -+ -+static inline struct clk *s32_clk_divider(const char *name, const char *parent, -+ void __iomem *reg, u8 shift, u8 width, -+ spinlock_t *lock) -+{ -+ struct clk *tmp_clk = clk_register_divider(NULL, name, parent, -+ CLK_SET_RATE_PARENT, -+ reg, shift, width, 0, lock); -+ -+ return tmp_clk; -+} -+ -+static inline struct clk *s32_clk_mux(const char *name, void __iomem *reg, -+ u8 shift, u8 width, const char **parents, -+ u8 num_parents, spinlock_t *lock) -+{ -+ return clk_register_mux(NULL, name, parents, num_parents, -+ CLK_SET_RATE_NO_REPARENT, reg, shift, -+ width, 0, lock); -+} -+ -+static inline struct clk *s32_clk_fixed_factor(const char *name, -+ const char *parent, -+ unsigned int mult, -+ unsigned int div) -+{ -+ return clk_register_fixed_factor(NULL, name, parent, -+ CLK_SET_RATE_PARENT, mult, div); -+} -+ -+#endif -diff --git a/drivers/clk/s32/s32v234/Makefile b/drivers/clk/s32/s32v234/Makefile -new file mode 100644 -index 000000000..7ddf9f4b5 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_ARCH_S32_CLK) += clk.o clk-plldig.o clk-dfs.o -diff --git a/drivers/clk/s32/s32v234/clk-dfs.c b/drivers/clk/s32/s32v234/clk-dfs.c -new file mode 100644 -index 000000000..2bd569e13 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/clk-dfs.c -@@ -0,0 +1,236 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2018 NXP -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk.h" -+ -+/** -+ * struct clk_dfs - S32 DFS clock -+ * @clk_hw: clock source -+ * @reg: DFS register address -+ * @idx: the index of DFS encoded in the register -+ * -+ * DFS clock found on S32 series. Each register for DFS has 4 clk_dfs -+ * data encoded, and member idx is used to specify the one. -+ * Only ARMPLL(3 DFS), ENETPLL(4 DFS) and DDRPLL(3 DFS) has DFS outputs. -+ */ -+struct clk_dfs { -+ struct clk_hw hw; -+ void __iomem *reg; -+ enum s32v234_plldig_type plltype; -+ u8 idx; -+ u32 mfn; -+}; -+ -+#define to_clk_dfs(_hw) container_of(_hw, struct clk_dfs, hw) -+ -+static int get_pllx_dfs_nr(enum s32v234_plldig_type plltype) -+{ -+ switch (plltype) { -+ case S32_PLLDIG_ARM: -+ return ARMPLL_DFS_NR; -+ case S32_PLLDIG_ENET: -+ return ENETPLL_DFS_NR; -+ case S32_PLLDIG_DDR: -+ return DDRPLL_DFS_NR; -+ case S32_PLLDIG_PERIPH: -+ case S32_PLLDIG_VIDEO: -+ pr_warn("Current selected PLL has no DFS\n"); -+ break; -+ } -+ -+ return -EINVAL; -+} -+static unsigned long get_pllx_dfsy_max_rate(enum s32v234_plldig_type plltype, -+ int dfsno) -+{ -+ switch (plltype) { -+ case S32_PLLDIG_ARM: -+ switch (dfsno) { -+ case 0: -+ return ARMPLL_DFS0_MAX_RATE; -+ case 1: -+ return ARMPLL_DFS1_MAX_RATE; -+ case 2: -+ return ARMPLL_DFS2_MAX_RATE; -+ } -+ break; -+ case S32_PLLDIG_ENET: -+ switch (dfsno) { -+ case 0: -+ return ENETPLL_DFS0_MAX_RATE; -+ case 1: -+ return ENETPLL_DFS1_MAX_RATE; -+ case 2: -+ return ENETPLL_DFS2_MAX_RATE; -+ case 3: -+ return ENETPLL_DFS3_MAX_RATE; -+ } -+ break; -+ case S32_PLLDIG_DDR: -+ switch (dfsno) { -+ case 0: -+ return DDRPLL_DFS0_MAX_RATE; -+ case 1: -+ return DDRPLL_DFS1_MAX_RATE; -+ case 2: -+ return DDRPLL_DFS2_MAX_RATE; -+ } -+ break; -+ case S32_PLLDIG_PERIPH: -+ case S32_PLLDIG_VIDEO: -+ pr_warn("Current selected PLL has no DFS."); -+ break; -+ default: -+ pr_warn("Unsupported PLL. Use %d or %d\n", -+ S32_PLLDIG_ARM, S32_PLLDIG_VIDEO); -+ break; -+ } -+ -+ return -EINVAL; -+} -+static int clk_dfs_enable(struct clk_hw *hw) -+{ -+ /* -+ * TODO: When SOC is available, this function -+ * should be tested and implemented for DFS -+ * if it is possible -+ */ -+ return 0; -+} -+ -+static void clk_dfs_disable(struct clk_hw *hw) -+{ -+ /* -+ * TODO: When SOC is available, this function -+ * should be tested and implemented for DFS -+ * if it is possible -+ */ -+} -+ -+static unsigned long clk_dfs_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_dfs *dfs = to_clk_dfs(hw); -+ u32 mfn, mfi, rate; -+ u32 dvport = readl_relaxed(DFS_DVPORTn(dfs->reg, dfs->idx)); -+ -+ mfn = (dvport & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_OFFSET; -+ mfi = (dvport & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_OFFSET; -+ mfi <<= 8; -+ rate = parent_rate / (mfi + mfn); -+ rate <<= 8; -+ -+ return rate; -+} -+ -+static long clk_dfs_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) -+{ -+ struct clk_dfs *dfs = to_clk_dfs(hw); -+ unsigned long max_allowed_rate; -+ -+ max_allowed_rate = get_pllx_dfsy_max_rate(dfs->plltype, dfs->idx); -+ -+ if (rate > max_allowed_rate) -+ rate = max_allowed_rate; -+ -+ return rate; -+} -+ -+static int clk_dfs_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_dfs *dfs = to_clk_dfs(hw); -+ u32 mfi; -+ u32 portreset = readl_relaxed(DFS_PORTRESET(dfs->reg)); -+ -+ writel_relaxed(DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg)); -+ writel_relaxed(portreset | ~DFS_PORTRESET_PORTRESET_SET(dfs->idx), -+ DFS_PORTRESET(dfs->reg)); -+ -+ mfi = parent_rate/rate; -+ writel_relaxed(DFS_DVPORTn_MFI_SET(mfi) | -+ DFS_DVPORTn_MFN_SET(dfs->mfn), -+ DFS_DVPORTn(dfs->reg, dfs->idx)); -+ -+ writel_relaxed(~DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg)); -+ -+ while (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx))) -+ ; -+ -+ return 0; -+} -+ -+static int clk_dfs_is_enabled(struct clk_hw *hw) -+{ -+ struct clk_dfs *dfs = to_clk_dfs(hw); -+ -+ /* Check if current DFS output port is locked */ -+ if (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx))) -+ return 0; -+ -+ return 1; -+} -+ -+static const struct clk_ops clk_dfs_ops = { -+ .enable = clk_dfs_enable, -+ .disable = clk_dfs_disable, -+ .recalc_rate = clk_dfs_recalc_rate, -+ .round_rate = clk_dfs_round_rate, -+ .set_rate = clk_dfs_set_rate, -+ .is_enabled = clk_dfs_is_enabled, -+}; -+ -+struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name, -+ const char *parent_name, void __iomem *reg, -+ u8 idx, u32 mfn) -+{ -+ struct clk_dfs *dfs; -+ struct clk *clk; -+ struct clk_init_data init; -+ -+ /* PERIPH and VIDEO PLL do not have DFS */ -+ if (type == S32_PLLDIG_PERIPH || type == S32_PLLDIG_VIDEO) -+ return ERR_PTR(-EINVAL); -+ -+ /* check if DFS index is valid for current pll */ -+ if (idx >= get_pllx_dfs_nr(type)) -+ return ERR_PTR(-EINVAL); -+ -+ dfs = kzalloc(sizeof(*dfs), GFP_KERNEL); -+ if (!dfs) -+ return ERR_PTR(-ENOMEM); -+ -+ dfs->reg = reg; -+ dfs->idx = idx; -+ dfs->mfn = mfn; -+ dfs->plltype = type; -+ -+ init.name = name; -+ init.ops = &clk_dfs_ops; -+ init.flags = 0; -+ init.parent_names = &parent_name; -+ init.num_parents = 1; -+ -+ dfs->hw.init = &init; -+ -+ clk = clk_register(NULL, &dfs->hw); -+ if (IS_ERR(clk)) -+ kfree(dfs); -+ -+ return clk; -+} -diff --git a/drivers/clk/s32/s32v234/clk-plldig.c b/drivers/clk/s32/s32v234/clk-plldig.c -new file mode 100644 -index 000000000..6ed23974e ---- /dev/null -+++ b/drivers/clk/s32/s32v234/clk-plldig.c -@@ -0,0 +1,240 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2018 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "clk.h" -+ -+/* -+ * struct clk_plldig - S32 PLLDIG clock -+ * @clk_hw: clock source -+ * @base: base address of PLL registers -+ * @plldv_mfd: multiplication loop factor divider -+ * @plldv_rfdphi: PHI reduced frequency divider -+ * @plldv_rfdphi1: PHI reduced frequency divider -+ * -+ * PLLDIG clock version 1, found on S32 series. -+ */ -+struct clk_plldig { -+ struct clk_hw hw; -+ void __iomem *base; -+ enum s32v234_plldig_type type; -+ u32 plldv_mfd; -+ u32 pllfd_mfn; -+ u32 plldv_rfdphi; -+ u32 plldv_rfdphi1; -+}; -+ -+#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) -+ -+static unsigned long get_pllx_max_vco_rate(enum s32v234_plldig_type plltype) -+{ -+ switch (plltype) { -+ case S32_PLLDIG_PERIPH: -+ return PERIPHPLL_MAX_VCO_RATE; -+ default: -+ pr_warn("Unsupported PLL.\n"); -+ return -EINVAL; -+ } -+} -+ -+static unsigned long get_pllx_phiy_max_rate(enum s32v234_plldig_type plltype, -+ unsigned int phino) -+{ -+ switch (plltype) { -+ case S32_PLLDIG_PERIPH: -+ switch (phino) { -+ case 0: -+ return PERIPHPLL_MAX_PHI0_MAX_RATE; -+ case 1: -+ return PERIPHPLL_MAX_PHI1_MAX_RATE; -+ default: -+ break; -+ } -+ break; -+ default: -+ pr_warn("Unsupported PLL.\n"); -+ break; -+ } -+ return -EINVAL; -+} -+ -+static int clk_plldig_prepare(struct clk_hw *hw) -+{ -+ return 0; -+} -+ -+static void clk_plldig_unprepare(struct clk_hw *hw) -+{ -+} -+ -+static unsigned long clk_plldig_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_plldig *pll = to_clk_plldig(hw); -+ u32 plldv = readl_relaxed(PLLDIG_PLLDV(pll->base)); -+ u32 pllfd = readl_relaxed(PLLDIG_PLLFD(pll->base)); -+ u32 prediv, mfd, mfn, vco; -+ -+ prediv = (plldv & PLLDIG_PLLDV_PREDIV_MASK) -+ >> PLLDIG_PLLDV_PREDIV_OFFSET; -+ mfd = (plldv & PLLDIG_PLLDV_MFD_MASK); -+ -+ mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK); -+ -+ if (prediv == 0) -+ prediv = 1; -+ -+ /* -+ * This formula is from platform reference manual -+ * (Rev. 1, 6/2015), PLLDIG chapter. -+ */ -+ vco = (parent_rate / prediv) * (mfd + mfn / 20480); -+ -+ return vco; -+} -+ -+static long clk_plldig_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) -+{ -+ struct clk_plldig *pll = to_clk_plldig(hw); -+ unsigned long max_allowed_rate = get_pllx_max_vco_rate(pll->type); -+ -+ if (rate > max_allowed_rate) -+ rate = max_allowed_rate; -+ else if (rate < MIN_VCO_RATE) -+ rate = MIN_VCO_RATE; -+ -+ return rate; -+} -+ -+static int clk_plldig_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_plldig *pll = to_clk_plldig(hw); -+ u32 pllfd, prediv; -+ -+ unsigned long max_allowed_rate = get_pllx_max_vco_rate(pll->type); -+ unsigned long phi0_max_rate = get_pllx_phiy_max_rate(pll->type, 0); -+ unsigned long phi1_max_rate = get_pllx_phiy_max_rate(pll->type, 1); -+ -+ if (rate < MIN_VCO_RATE || rate > max_allowed_rate) -+ return -EINVAL; -+ -+ if (((rate / pll->plldv_rfdphi) > phi0_max_rate) || -+ ((rate / pll->plldv_rfdphi) > phi1_max_rate)) -+ return -EINVAL; -+ -+ pllfd = readl_relaxed(PLLDIG_PLLFD(pll->base)); -+ prediv = (parent_rate / rate) * -+ (pll->plldv_mfd + pll->pllfd_mfn / 20480); -+ -+ writel_relaxed(PLLDIG_PLLDV_RFDPHI1_SET(pll->plldv_rfdphi1) | -+ PLLDIG_PLLDV_RFDPHI_SET(pll->plldv_rfdphi) | -+ PLLDIG_PLLDV_PREDIV_SET(prediv) | -+ PLLDIG_PLLDV_MFD_SET(pll->plldv_mfd), -+ PLLDIG_PLLDV(pll->base)); -+ -+ writel_relaxed(pllfd | PLLDIG_PLLFD_MFN_SET(pll->pllfd_mfn), -+ PLLDIG_PLLFD(pll->base)); -+ -+ /* -+ * To be implemented the wait_lock or an equivalent state -+ * return clk_plldig_wait_lock(pll); -+ */ -+ return 0; -+} -+ -+static const struct clk_ops clk_plldig_ops = { -+ .prepare = clk_plldig_prepare, -+ .unprepare = clk_plldig_unprepare, -+ .recalc_rate = clk_plldig_recalc_rate, -+ .round_rate = clk_plldig_round_rate, -+ .set_rate = clk_plldig_set_rate, -+}; -+ -+struct clk *s32v234_clk_plldig_phi(enum s32v234_plldig_type type, -+ const char *name, const char *parent, -+ void __iomem *base, u32 phi) -+{ -+ u32 plldv, rfd_phi; -+ -+ if (!base) -+ return ERR_PTR(-ENOMEM); -+ -+ plldv = readl_relaxed(PLLDIG_PLLDV(base)); -+ -+ switch (phi) { -+ /* PHI0 */ -+ case 0: -+ rfd_phi = (plldv & PLLDIG_PLLDV_RFDPHI_MASK) -+ >> PLLDIG_PLLDV_RFDPHI_OFFSET; -+ break; -+ /* PHI1 */ -+ case 1: -+ rfd_phi = (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) -+ >> PLLDIG_PLLDV_RFDPHI1_OFFSET; -+ -+ if (rfd_phi == 0) -+ rfd_phi = 1; -+ -+ break; -+ default: -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return clk_register_fixed_factor(NULL, name, parent, -+ CLK_SET_RATE_PARENT, 1, rfd_phi); -+} -+ -+struct clk *s32v234_clk_plldig(enum s32v234_plldig_type type, const char *name, -+ const char *parent_name, void __iomem *base, -+ u32 plldv_mfd, u32 pllfd_mfn, -+ u32 plldv_rfdphi, u32 plldv_rfdphi1) -+{ -+ struct clk_plldig *pll; -+ const struct clk_ops *ops; -+ struct clk *clk; -+ struct clk_init_data init; -+ -+ if (plldv_rfdphi > PLLDIG_PLLDV_RFDPHI_MAXVALUE) -+ return ERR_PTR(-EINVAL); -+ -+ if (plldv_rfdphi1 > PLLDIG_PLLDV_RFDPHI1_MAXVALUE) -+ return ERR_PTR(-EINVAL); -+ -+ pll = kzalloc(sizeof(*pll), GFP_KERNEL); -+ if (!pll) -+ return ERR_PTR(-ENOMEM); -+ -+ ops = &clk_plldig_ops; -+ -+ pll->base = base; -+ pll->type = type; -+ pll->plldv_mfd = plldv_mfd; -+ pll->pllfd_mfn = pllfd_mfn; -+ pll->plldv_rfdphi = plldv_rfdphi; -+ pll->plldv_rfdphi1 = plldv_rfdphi1; -+ -+ init.name = name; -+ init.ops = ops; -+ init.flags = 0; -+ init.parent_names = &parent_name; -+ init.num_parents = 1; -+ -+ pll->hw.init = &init; -+ -+ clk = clk_register(NULL, &pll->hw); -+ if (IS_ERR(clk)) -+ kfree(pll); -+ -+ return clk; -+} -diff --git a/drivers/clk/s32/s32v234/clk.c b/drivers/clk/s32/s32v234/clk.c -new file mode 100644 -index 000000000..ad88c6b45 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/clk.c -@@ -0,0 +1,299 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2018 NXP -+ */ -+ -+#include -+#include -+#include -+ -+#include "clk.h" -+ -+static void __iomem *mc_cgm0_base; -+static void __iomem *mc_cgm1_base; -+static void __iomem *mc_cgm2_base; -+static void __iomem *mc_cgm3_base; -+static void __iomem *mc_me_base; -+static void __iomem *src_base; -+ -+DEFINE_SPINLOCK(s32v234_lock); -+ -+/* sources for multiplexer clocks, this is used multiple times */ -+PNAME(osc_sels) = {"firc", "fxosc", }; -+ -+PNAME(sys_sels) = {"firc", "fxosc", "armpll_dfs0", }; -+ -+PNAME(can_sels) = {"firc", "fxosc", "dummy", -+ "periphpll_phi0_div5", }; -+ -+PNAME(lin_sels) = {"firc", "fxosc", "dummy", -+ "periphpll_phi0_div3", "dummy", "dummy", -+ "dummy", "dummy", "sys6",}; -+ -+PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", "dummy", -+ "enetpll_dfs3",}; -+ -+PNAME(enet_sels) = {"firc", "fxosc", "dummy", -+ "dummy", "enetpll_phi0",}; -+ -+PNAME(enet_time_sels) = {"firc", "fxosc", "dummy", -+ "dummy", "enetpll_phi0",}; -+ -+static struct clk *clk[S32V234_CLK_END]; -+static struct clk_onecell_data clk_data; -+ -+static void __init s32v234_clocks_init(struct device_node *mc_cgm0_node) -+{ -+ struct device_node *np; -+ -+ clk[S32V234_CLK_DUMMY] = s32_clk_fixed("dummy", 0); -+ clk[S32V234_CLK_FXOSC] = s32_obtain_fixed_clock("fxosc", 0); -+ clk[S32V234_CLK_FIRC] = s32_obtain_fixed_clock("firc", 0); -+ -+ np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_me"); -+ mc_me_base = of_iomap(np, 0); -+ if (WARN_ON(!mc_me_base)) -+ return; -+ -+ np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-src"); -+ src_base = of_iomap(np, 0); -+ if (WARN_ON(!src_base)) -+ return; -+ -+ np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm1"); -+ mc_cgm1_base = of_iomap(np, 0); -+ if (WARN_ON(!mc_cgm1_base)) -+ return; -+ -+ np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm2"); -+ mc_cgm2_base = of_iomap(np, 0); -+ if (WARN_ON(!mc_cgm2_base)) -+ return; -+ -+ np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm3"); -+ mc_cgm3_base = of_iomap(np, 0); -+ if (WARN_ON(!mc_cgm3_base)) -+ return; -+ -+ np = mc_cgm0_node; -+ mc_cgm0_base = of_iomap(np, 0); -+ if (WARN_ON(!mc_cgm0_base)) -+ return; -+ -+ enable_cpumodes_onperipheralconfig(mc_me_base, MC_ME_RUN_PCn_DRUN | -+ MC_ME_RUN_PCn_RUN0 | -+ MC_ME_RUN_PCn_RUN1 | -+ MC_ME_RUN_PCn_RUN2 | -+ MC_ME_RUN_PCn_RUN3, -+ 0); -+ -+ /* turn on XOSC and FIRC */ -+ enable_clocks_sources(MC_ME_MODE_MC_MVRON, MC_ME_MODE_MC_XOSCON | -+ MC_ME_MODE_MC_FIRCON, -+ MC_ME_RUNn_MC(mc_me_base, 0)); -+ -+ /* transition the core to RUN0 mode */ -+ entry_to_target_mode(mc_me_base, MC_ME_MCTL_RUN0); -+ -+ clk[S32V234_CLK_ARMPLL_SRC_SEL] = s32_clk_mux("armpll_sel", -+ SRC_GPR1, SRC_GPR1_ARMPLL_SRC_SEL_OFFSET, -+ SRC_GPR1_XPLL_SRC_SEL_SIZE, -+ osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_PERIPHPLL_SRC_SEL] = s32_clk_mux("periphpll_sel", -+ SRC_GPR1, SRC_GPR1_PERIPHPLL_SRC_SEL_OFFSET, -+ SRC_GPR1_XPLL_SRC_SEL_SIZE, -+ osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_ENETPLL_SRC_SEL] = s32_clk_mux("enetpll_sel", -+ SRC_GPR1, SRC_GPR1_ENETPLL_SRC_SEL_OFFSET, -+ SRC_GPR1_XPLL_SRC_SEL_SIZE, -+ osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); -+ -+ /* ARM_PLL */ -+ clk[S32V234_CLK_ARMPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_ARM, -+ "armpll_vco", "armpll_sel", ARMPLL_PLLDIG(mc_cgm0_base), -+ ARMPLL_PLLDIG_PLLDV_MFD, ARMPLL_PLLDIG_PLLDV_MFN, -+ ARMPLL_PLLDIG_PLLDV_RFDPHI0, ARMPLL_PLLDIG_PLLDV_RFDPHI1); -+ -+ clk[S32V234_CLK_ARMPLL_PHI0] = s32v234_clk_plldig_phi(S32_PLLDIG_ARM, -+ "armpll_phi0", "armpll_vco", -+ ARMPLL_PLLDIG(mc_cgm0_base), 0); -+ -+ clk[S32V234_CLK_ARMPLL_PHI1] = s32v234_clk_plldig_phi(S32_PLLDIG_ARM, -+ "armpll_phi1", "armpll_vco", -+ ARMPLL_PLLDIG(mc_cgm0_base), 1); -+ -+ clk[S32V234_CLK_ARMPLL_DFS0] = s32v234_clk_dfs(S32_PLLDIG_ARM, -+ "armpll_dfs0", "armpll_phi1", -+ ARMPLL_PLLDIG_DFS(mc_cgm0_base), 0, -+ ARMPLL_PLLDIG_DFS0_MFN); -+ -+ clk[S32V234_CLK_ARMPLL_DFS1] = s32v234_clk_dfs(S32_PLLDIG_ARM, -+ "armpll_dfs1", "armpll_phi1", -+ ARMPLL_PLLDIG_DFS(mc_cgm0_base), 1, -+ ARMPLL_PLLDIG_DFS1_MFN); -+ -+ clk[S32V234_CLK_ARMPLL_DFS2] = s32v234_clk_dfs(S32_PLLDIG_ARM, -+ "armpll_dfs2", "armpll_phi1", -+ ARMPLL_PLLDIG_DFS(mc_cgm0_base), 2, -+ ARMPLL_PLLDIG_DFS2_MFN); -+ -+ clk[S32V234_CLK_SYS_SEL] = s32_clk_mux("sys_sel", -+ MC_ME_RUNn_MC(mc_me_base, 0), -+ MC_ME_MODE_MC_SYSCLK_OFFSET, -+ MC_ME_MODE_MC_SYSCLK_SIZE, -+ sys_sels, ARRAY_SIZE(sys_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_SYS3] = s32_clk_divider("sys3", "sys_sel", -+ CGM_SC_DCn(mc_cgm0_base, 0), MC_CGM_SC_DCn_PREDIV_OFFSET, -+ MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); -+ -+ clk[S32V234_CLK_SYS6] = s32_clk_divider("sys6", "sys_sel", -+ CGM_SC_DCn(mc_cgm0_base, 1), MC_CGM_SC_DCn_PREDIV_OFFSET, -+ MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); -+ -+ clk[S32V234_CLK_SYS6_DIV2] = s32_clk_divider("sys6_div2", "sys_sel", -+ CGM_SC_DCn(mc_cgm0_base, 2), MC_CGM_SC_DCn_PREDIV_OFFSET, -+ MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); -+ -+ /* PERIPH_PLL */ -+ clk[S32V234_CLK_PERIPHPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_PERIPH, -+ "periphpll_vco", "periphpll_sel", -+ PERIPHPLL_PLLDIG(mc_cgm0_base), -+ PERIPHPLL_PLLDIG_PLLDV_MFD, PERIPHPLL_PLLDIG_PLLDV_MFN, -+ PERIPHPLL_PLLDIG_PLLDV_RFDPHI0, -+ PERIPHPLL_PLLDIG_PLLDV_RFDPHI1); -+ -+ clk[S32V234_CLK_PERIPHPLL_PHI0] = -+ s32v234_clk_plldig_phi(S32_PLLDIG_PERIPH, -+ "periphpll_phi0", "periphpll_vco", -+ PERIPHPLL_PLLDIG(mc_cgm0_base), 0); -+ -+ clk[S32V234_CLK_PERIPHPLL_PHI1] = -+ s32v234_clk_plldig_phi(S32_PLLDIG_PERIPH, -+ "periphpll_phi1", "periphpll_vco", -+ PERIPHPLL_PLLDIG(mc_cgm0_base), 1); -+ -+ clk[S32V234_CLK_PERIPHPLL_PHI0_DIV3] = s32_clk_fixed_factor( -+ "periphpll_phi0_div3", "periphpll_phi0", 1, 3); -+ -+ clk[S32V234_CLK_PERIPHPLL_PHI0_DIV5] = s32_clk_fixed_factor( -+ "periphpll_phi0_div5", "periphpll_phi0", 1, 5); -+ -+ clk[S32V234_CLK_CAN_SEL] = s32_clk_mux("can_sel", -+ CGM_ACn_SC(mc_cgm0_base, 6), -+ MC_CGM_ACn_SEL_OFFSET, -+ MC_CGM_ACn_SEL_SIZE, -+ can_sels, ARRAY_SIZE(can_sels), &s32v234_lock); -+ -+ /* CAN Clock */ -+ clk[S32V234_CLK_CAN] = s32_clk_divider("can", "can_sel", -+ CGM_ACn_DCm(mc_cgm0_base, 6, 0), -+ MC_CGM_ACn_DCm_PREDIV_OFFSET, -+ MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); -+ -+ /* Lin Clock */ -+ clk[S32V234_CLK_LIN_SEL] = s32_clk_mux("lin_sel", -+ CGM_ACn_SC(mc_cgm0_base, 3), -+ MC_CGM_ACn_SEL_OFFSET, -+ MC_CGM_ACn_SEL_SIZE, -+ lin_sels, ARRAY_SIZE(lin_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_LIN] = s32_clk_divider("lin", "lin_sel", -+ CGM_ACn_DCm(mc_cgm0_base, 3, 0), -+ MC_CGM_ACn_DCm_PREDIV_OFFSET, -+ MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); -+ -+ clk[S32V234_CLK_LIN_IPG] = s32_clk_fixed_factor("lin_ipg", -+ "lin", 1, 2); -+ -+ /* enable PERIPHPLL */ -+ enable_clocks_sources(0, MC_ME_MODE_MC_PERIPHPLL, -+ MC_ME_RUNn_MC(mc_me_base, 0)); -+ -+ /* ENET_PLL */ -+ clk[S32V234_CLK_ENETPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_ENET, -+ "enetpll_vco", "enetpll_sel", ENETPLL_PLLDIG(mc_cgm0_base), -+ ENETPLL_PLLDIG_PLLDV_MFD, ENETPLL_PLLDIG_PLLDV_MFN, -+ ENETPLL_PLLDIG_PLLDV_RFDPHI0, ENETPLL_PLLDIG_PLLDV_RFDPHI1); -+ -+ clk[S32V234_CLK_ENETPLL_PHI0] = s32v234_clk_plldig_phi(S32_PLLDIG_ENET, -+ "enetpll_phi0", "enetpll_vco", -+ ENETPLL_PLLDIG(mc_cgm0_base), 0); -+ -+ clk[S32V234_CLK_ENETPLL_PHI1] = s32v234_clk_plldig_phi(S32_PLLDIG_ENET, -+ "enetpll_phi1", "enetpll_vco", -+ ENETPLL_PLLDIG(mc_cgm0_base), 1); -+ -+ clk[S32V234_CLK_ENETPLL_DFS0] = s32v234_clk_dfs(S32_PLLDIG_ENET, -+ "enetpll_dfs0", "enetpll_phi1", -+ ENETPLL_PLLDIG_DFS(mc_cgm0_base), 0, -+ ENETPLL_PLLDIG_DFS0_MFN); -+ -+ clk[S32V234_CLK_ENETPLL_DFS1] = s32v234_clk_dfs(S32_PLLDIG_ENET, -+ "enetpll_dfs1", "enetpll_phi1", -+ ENETPLL_PLLDIG_DFS(mc_cgm0_base), 1, -+ ENETPLL_PLLDIG_DFS1_MFN); -+ -+ clk[S32V234_CLK_ENETPLL_DFS2] = s32v234_clk_dfs(S32_PLLDIG_ENET, -+ "enetpll_dfs2", "enetpll_phi1", -+ ENETPLL_PLLDIG_DFS(mc_cgm0_base), 2, -+ ENETPLL_PLLDIG_DFS2_MFN); -+ -+ clk[S32V234_CLK_ENETPLL_DFS3] = s32v234_clk_dfs(S32_PLLDIG_ENET, -+ "enetpll_dfs3", "enetpll_phi1", -+ ENETPLL_PLLDIG_DFS(mc_cgm0_base), 3, -+ ENETPLL_PLLDIG_DFS3_MFN); -+ -+ /* ENET Clock */ -+ clk[S32V234_CLK_ENET_SEL] = s32_clk_mux("enet_sel", -+ CGM_ACn_SC(mc_cgm2_base, 2), -+ MC_CGM_ACn_SEL_OFFSET, -+ MC_CGM_ACn_SEL_SIZE, -+ enet_sels, ARRAY_SIZE(enet_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_ENET_TIME_SEL] = s32_clk_mux("enet_time_sel", -+ CGM_ACn_SC(mc_cgm0_base, 7), -+ MC_CGM_ACn_SEL_OFFSET, -+ MC_CGM_ACn_SEL_SIZE, -+ enet_time_sels, ARRAY_SIZE(enet_time_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_ENET] = s32_clk_divider("enet", "enet_sel", -+ CGM_ACn_DCm(mc_cgm2_base, 2, 0), -+ MC_CGM_ACn_DCm_PREDIV_OFFSET, -+ MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); -+ -+ clk[S32V234_CLK_ENET_TIME] = s32_clk_divider("enet_time", -+ "enet_time_sel", -+ CGM_ACn_DCm(mc_cgm0_base, 7, 1), -+ MC_CGM_ACn_DCm_PREDIV_OFFSET, -+ MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); -+ -+ /* SDHC Clock */ -+ clk[S32V234_CLK_SDHC_SEL] = s32_clk_mux("sdhc_sel", -+ CGM_ACn_SC(mc_cgm0_base, 15), -+ MC_CGM_ACn_SEL_OFFSET, -+ MC_CGM_ACn_SEL_SIZE, -+ sdhc_sels, ARRAY_SIZE(sdhc_sels), &s32v234_lock); -+ -+ clk[S32V234_CLK_SDHC] = s32_clk_divider("sdhc", "sdhc_sel", -+ CGM_ACn_DCm(mc_cgm0_base, 15, 0), -+ MC_CGM_ACn_DCm_PREDIV_OFFSET, -+ MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); -+ -+ /* set the system clock */ -+ enable_sysclock(MC_ME_MODE_MC_SYSCLK(0x2), -+ MC_ME_RUNn_MC(mc_me_base, 0)); -+ -+ /* transition the core to RUN0 mode */ -+ entry_to_target_mode(mc_me_base, MC_ME_MCTL_RUN0); -+ -+ /* Add the clocks to provider list */ -+ clk_data.clks = clk; -+ clk_data.clk_num = ARRAY_SIZE(clk); -+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -+} -+ -+CLK_OF_DECLARE(S32V234, "fsl,s32v234-mc_cgm0", s32v234_clocks_init); -diff --git a/drivers/clk/s32/s32v234/clk.h b/drivers/clk/s32/s32v234/clk.h -new file mode 100644 -index 000000000..82a222483 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/clk.h -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2018 NXP -+ */ -+ -+#ifndef __MACH_S32V234_CLK_H -+#define __MACH_S32V234_CLK_H -+ -+#include -+#include -+#include "mc_cgm.h" -+#include "mc_me.h" -+#include "pll.h" -+#include "src.h" -+#include "dfs.h" -+#include "../clk.h" -+ -+struct clk *s32v234_clk_plldig(enum s32v234_plldig_type type, const char *name, -+ const char *parent_name, void __iomem *base, -+ u32 plldv_mfd, u32 plldv_mfn, -+ u32 plldv_rfdphi, u32 plldv_rfdphi1); -+ -+struct clk *s32v234_clk_plldig_phi(enum s32v234_plldig_type type, -+ const char *name, const char *parent, -+ void __iomem *base, u32 phi); -+ -+struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name, -+ const char *parent_name, -+ void __iomem *reg, u8 idx, u32 mfn); -+#endif -diff --git a/drivers/clk/s32/s32v234/dfs.h b/drivers/clk/s32/s32v234/dfs.h -new file mode 100644 -index 000000000..be3104f7a ---- /dev/null -+++ b/drivers/clk/s32/s32v234/dfs.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright 2018 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+#ifndef _DFS_S32V234_H -+#define _DFS_S32V234_H -+ -+/* DFS Control Register (DFS_CTRL) */ -+#define DFS_CTRL(base) ((base) + 0x00000018) -+#define DFS_CTRL_DLL_LOLIE (1 << 0) -+#define DFS_CTRL_DLL_RESET (1 << 1) -+ -+/* DFS Port Status (DFS_PORTSR) */ -+#define DFS_PORTSR(base) ((base) + 0x0000000C) -+#define DFS_PORTSR_MASK (0x0000000F) -+#define DFS_PORTSR_OFFSET (28) -+ -+/* DFS Port Reset Register (DFS_PORTRESET) */ -+#define DFS_PORTRESET(base) ((base) + 0x00000014) -+#define DFS_PORTRESET_PORTRESET_SET(val) \ -+ (DFS_PORTRESET_PORTRESET_MASK | \ -+ (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) \ -+ << DFS_PORTRESET_PORTRESET_OFFSET)) -+#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) -+#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) -+#define DFS_PORTRESET_PORTRESET_OFFSET (28) -+ -+/* DFS Divide Register Portn (DFS_DVPORTn) */ -+#define DFS_DVPORTn(base, n) ((base) + (0x0000001C + \ -+ ((n) * sizeof(u32)))) -+#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & \ -+ (((val) & DFS_DVPORTn_MFI_MAXVAL) \ -+ << DFS_DVPORTn_MFI_OFFSET)) -+#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & \ -+ (((val) & DFS_DVPORTn_MFN_MAXVAL) \ -+ << DFS_DVPORTn_MFN_OFFSET)) -+#define DFS_DVPORTn_MFI_MASK (0x0000FF00) -+#define DFS_DVPORTn_MFN_MASK (0x000000FF) -+#define DFS_DVPORTn_MFI_MAXVAL (0xFF) -+#define DFS_DVPORTn_MFN_MAXVAL (0xFF) -+#define DFS_DVPORTn_MFI_OFFSET (8) -+#define DFS_DVPORTn_MFN_OFFSET (0) -+#define DFS_MAXNUMBER (4) -+ -+/* -+ * Naming convention for PLL: -+ * ARMPLL - PLL0 -+ * PERIPHPLL - PLL1 -+ * ENETPLL - PLL2 -+ * DDRPLL - PLL3 -+ * VIDEOPLL - PLL4 -+ */ -+ -+/* The max values for PLL DFS is in Hz */ -+/* ARMPLL */ -+#define ARMPLL_DFS0_MAX_RATE (266000000) -+#define ARMPLL_DFS1_MAX_RATE (600000000) -+#define ARMPLL_DFS2_MAX_RATE (600000000) -+/* ENETPLL */ -+#define ENETPLL_DFS0_MAX_RATE (350000000) -+#define ENETPLL_DFS1_MAX_RATE (350000000) -+#define ENETPLL_DFS2_MAX_RATE (416000000) -+#define ENETPLL_DFS3_MAX_RATE (104000000) -+/* DDRPLL */ -+#define DDRPLL_DFS0_MAX_RATE (500000000) -+#define DDRPLL_DFS1_MAX_RATE (500000000) -+#define DDRPLL_DFS2_MAX_RATE (350000000) -+ -+#define ARMPLL_DFS_NR (3) -+#define ENETPLL_DFS_NR (4) -+#define DDRPLL_DFS_NR (3) -+ -+#endif -diff --git a/drivers/clk/s32/s32v234/mc_cgm.h b/drivers/clk/s32/s32v234/mc_cgm.h -new file mode 100644 -index 000000000..aeac68771 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/mc_cgm.h -@@ -0,0 +1,70 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright (C) 2017 NXP -+ */ -+#ifndef _MC_CGM_H -+#define _MC_CGM_H -+ -+#define ARMPLL_PLLDIG(mc_cgm) (mc_cgm) -+#define ARMPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x40) -+#define ARMPLL_PLLDIG_PLLDV_MFD (50) -+#define ARMPLL_PLLDIG_PLLDV_MFN (0) -+#define ARMPLL_PLLDIG_PLLDV_RFDPHI0 (1) -+#define ARMPLL_PLLDIG_PLLDV_RFDPHI1 (1) -+#define ARMPLL_PLLDIG_DFS0_MFN (195) -+#define ARMPLL_PLLDIG_DFS1_MFN (171) -+#define ARMPLL_PLLDIG_DFS2_MFN (171) -+ -+#define PERIPHPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x80) -+#define PERIPHPLL_PLLDIG_PLLDV_MFD (30) -+#define PERIPHPLL_PLLDIG_PLLDV_MFN (0) -+#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI0 (0x1) -+#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI1 (0x1) -+ -+#define ENETPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x100) -+#define ENETPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x100 + 0x40) -+#define ENETPLL_PLLDIG_PLLDV_MFD (50) -+#define ENETPLL_PLLDIG_PLLDV_MFN (0) -+#define ENETPLL_PLLDIG_PLLDV_RFDPHI0 (0x1) -+#define ENETPLL_PLLDIG_PLLDV_RFDPHI1 (0x1) -+#define ENETPLL_PLLDIG_DFS0_MFN (220) -+#define ENETPLL_PLLDIG_DFS1_MFN (220) -+#define ENETPLL_PLLDIG_DFS2_MFN (33) -+#define ENETPLL_PLLDIG_DFS3_MFN (1) -+ -+/* MC_CGM_SC_SS */ -+#define CGM_SC_SS(mc_cgm) (((mc_cgm) + 0x7E4)) -+ -+/* MC_CGM_SC_DCn */ -+#define CGM_SC_DCn(mc_cgm, dc) (((mc_cgm) + 0x7E8) + ((dc) * 0x4)) -+ -+#define MC_CGM_SC_DCn_PREDIV_OFFSET (16) -+#define MC_CGM_SC_DCn_PREDIV_SIZE (3) -+#define MC_CGM_SC_DCn_DE (1 << 31) -+#define MC_CGM_SC_SEL_OFFSET (24) -+#define MC_CGM_SC_SEL_SIZE (4) -+ -+/* MC_CGM_ACn_DCm */ -+#define CGM_ACn_DCm(mc_cgm, ac, dc) (((mc_cgm) + 0x808) + ((ac) * 0x20)\ -+ + ((dc) * 0x4)) -+ -+#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & \ -+ ((val) \ -+ << MC_CGM_ACn_DCm_PREDIV_OFFSET)) -+#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) -+#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) -+#define MC_CGM_ACn_DCm_PREDIV_SIZE (5) -+#define MC_CGM_ACn_DCm_DE (1 << 31) -+ -+/* MC_CGM_ACn_SC/MC_CGM_ACn_SS */ -+#define CGM_ACn_SC(mc_cgm, ac) (((mc_cgm) + 0x800) + ((ac) * 0x20)) -+#define CGM_ACn_SS(mc_cgm, ac) (((mc_cgm) + 0x804) + ((ac) * 0x24)) -+#define MC_CGM_ACn_SEL_MASK (0x07000000) -+#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & \ -+ (((source) & 0x7) \ -+ << MC_CGM_ACn_SEL_OFFSET)) -+#define MC_CGM_ACn_SEL_OFFSET (24) -+#define MC_CGM_ACn_SEL_SIZE (4) -+ -+#endif -diff --git a/drivers/clk/s32/s32v234/mc_me.h b/drivers/clk/s32/s32v234/mc_me.h -new file mode 100644 -index 000000000..718f1d1a0 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/mc_me.h -@@ -0,0 +1,110 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright (C) 2017 NXP -+ */ -+ -+#ifndef _MC_ME_H -+#define _MC_ME_H -+ -+/* MC_ME registers definitions */ -+/* MC_ME_GS */ -+ #define MC_ME_GS(mc_me) ((mc_me) + 0x00000000) -+ -+/* MC_ME_MCTL */ -+#define MC_ME_MCTL(mc_me) ((mc_me) + 0x00000004) -+#define MC_ME_MCTL_RESET (0x0 << 28) -+#define MC_ME_MCTL_TEST (0x1 << 28) -+#define MC_ME_MCTL_DRUN (0x3 << 28) -+#define MC_ME_MCTL_RUN0 (0x4 << 28) -+#define MC_ME_MCTL_RUN1 (0x5 << 28) -+#define MC_ME_MCTL_RUN2 (0x6 << 28) -+#define MC_ME_MCTL_RUN3 (0x7 << 28) -+ -+#define MC_ME_GS_S_MTRANS (1 << 27) -+ -+#define MC_ME_MCTL_KEY (0x00005AF0) -+#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) -+ -+/* -+ * MC_ME_RESET_MC/MC_ME_TEST_MC -+ * MC_ME_DRUN_MC -+ * MC_ME_RUNn_MC -+ */ -+#define MC_ME_RESET_MC(mc_me) ((mc_me) + 0x00000020) -+#define MC_ME_TEST_MC(mc_me) ((mc_me) + 0x00000024) -+#define MC_ME_DRUN_MC(mc_me) ((mc_me) + 0x0000002C) -+#define MC_ME_RUNn_MC(mc_me, n) ((mc_me) + 0x00000030 + 0x4 * (n)) -+#define MC_ME_MODE_MC_SYSCLK_OFFSET (0) -+#define MC_ME_MODE_MC_SYSCLK_SIZE (0x3) -+#define MC_ME_MODE_MC_SYSCLK(val) (MC_ME_MODE_MC_SYSCLK_MASK & (val)) -+#define MC_ME_MODE_MC_SYSCLK_MASK (0x0000000F) -+#define MC_ME_MODE_MC_FIRCON (1 << 4) -+#define MC_ME_MODE_MC_XOSCON (1 << 5) -+#define MC_ME_MODE_MC_ARMPLL (1 << 6) -+#define MC_ME_MODE_MC_PERIPHPLL (1 << 7) -+#define MC_ME_MODE_MC_ENETPLL (1 << 8) -+#define MC_ME_MODE_MC_DDRPLL (1 << 9) -+#define MC_ME_MODE_MC_VIDEOPLL (1 << 10) -+#define MC_ME_MODE_MC_MVRON (1 << 20) -+ -+/* MC_ME_DRUN_SEC_CC_I */ -+#define MC_ME_DRUN_SEC_CC_I(mc_me) ((mc_me) + 0x260) -+/* MC_ME_RUNn_SEC_CC_I */ -+#define MC_ME_RUNn_SEC_CC_I(mc_me, n) ((mc_me) + 0x270 + (n) * 0x10) -+#define MC_ME_MODE_SEC_CC_I_SYSCLK1_OFFSET (4) -+#define MC_ME_MODE_SEC_CC_I_SYSCLK2_OFFSET (8) -+#define MC_ME_MODE_SEC_CC_I_SYSCLK3_OFFSET (12) -+/* Consider only the defined clocks */ -+#define MC_ME_MODE_SEC_CC_I_SYSCLK1_SIZE (0x3) -+#define MC_ME_MODE_SEC_CC_I_SYSCLK2_SIZE (0x3) -+#define MC_ME_MODE_SEC_CC_I_SYSCLK3_SIZE (0x3) -+ -+/* MC_ME_RUN_PCn */ -+#define MC_ME_RUN_PCn(mc_me, n) (mc_me + 0x00000080 + 0x4 * (n)) -+ -+#define MC_ME_RUN_PCn_MAX_IDX (7) -+#define MC_ME_RUN_PCn_RESET (1 << 0) -+#define MC_ME_RUN_PCn_TEST (1 << 1) -+#define MC_ME_RUN_PCn_DRUN (1 << 3) -+#define MC_ME_RUN_PCn_RUN0 (1 << 4) -+#define MC_ME_RUN_PCn_RUN1 (1 << 5) -+#define MC_ME_RUN_PCn_RUN2 (1 << 6) -+#define MC_ME_RUN_PCn_RUN3 (1 << 7) -+ -+#define MC_ME_PCTLn(mc_me, n) (mc_me + 0xC0 + 4 * (n >> 2) + \ -+ (3 - (n) % 4)) -+ -+static inline void entry_to_target_mode(void __iomem *mc_me, u32 mode) -+{ -+ writel_relaxed(mode | MC_ME_MCTL_KEY, MC_ME_MCTL(mc_me)); -+ writel_relaxed(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL(mc_me)); -+ while ((readl_relaxed(MC_ME_GS(mc_me)) & -+ MC_ME_GS_S_MTRANS) != 0x00000000) -+ ; -+} -+ -+static inline void enable_cpumodes_onperipheralconfig(void __iomem *mc_me, -+ u32 modes, u32 run_pc_idx) -+{ -+ WARN_ON(run_pc_idx > MC_ME_RUN_PCn_MAX_IDX); -+ if (run_pc_idx > MC_ME_RUN_PCn_MAX_IDX) -+ return; -+ -+ writel_relaxed(modes, MC_ME_RUN_PCn(mc_me, run_pc_idx)); -+} -+ -+static inline void enable_clocks_sources(u32 flags, u32 clks, -+ void __iomem *xrun_mc_addr) -+{ -+ writel_relaxed(readl_relaxed(xrun_mc_addr) | flags | clks, -+ xrun_mc_addr); -+} -+ -+static inline void enable_sysclock(u32 clk, void __iomem *xrun_mc_addr) -+{ -+ writel_relaxed(readl_relaxed(xrun_mc_addr) & clk, -+ xrun_mc_addr); -+} -+ -+#endif -diff --git a/drivers/clk/s32/s32v234/pll.h b/drivers/clk/s32/s32v234/pll.h -new file mode 100644 -index 000000000..b7bcc50f0 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/pll.h -@@ -0,0 +1,78 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ * Copyright (C) 2017-2018 NXP -+ */ -+#ifndef _PLL_S32V234_H -+#define _PLL_S32V234_H -+ -+/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ -+#define PLLDIG_PLLDV(base) ((base) + 0x00000028) -+#define PLLDIG_PLLDV_MFD_SET(val) (PLLDIG_PLLDV_MFD_MASK & (val)) -+#define PLLDIG_PLLDV_MFD_MASK (0x000000FF) -+ -+#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & \ -+ (((val) & \ -+ PLLDIG_PLLDV_RFDPHI_MAXVALUE) \ -+ << PLLDIG_PLLDV_RFDPHI_OFFSET)) -+#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) -+#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) -+ -+#define PLLDIG_PLLDV_RFDPHI_OFFSET (16) -+ -+#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & \ -+ (((val) & \ -+ PLLDIG_PLLDV_RFDPHI1_MAXVALUE) \ -+ << PLLDIG_PLLDV_RFDPHI1_OFFSET)) -+#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) -+#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) -+#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) -+ -+#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & \ -+ (((val) & \ -+ PLLDIG_PLLDV_PREDIV_MAXVALUE) \ -+ << PLLDIG_PLLDV_PREDIV_OFFSET)) -+#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) -+#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) -+#define PLLDIG_PLLDV_PREDIV_OFFSET (12) -+ -+/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ -+#define PLLDIG_PLLFD(base) ((base) + 0x00000030) -+#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) -+#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) -+ -+/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ -+#define PLLDIG_PLLCAL1(base) ((base) + 0x00000038) -+#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & \ -+ ((val) \ -+ << PLLDIG_PLLCAL1_NDAC1_OFFSET)) -+#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) -+#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) -+ -+/* Naming convention for PLL: -+ * ARMPLL - PLL0 -+ * PERIPHPLL - PLL1 -+ * ENETPLL - PLL2 -+ * DDRPLL - PLL3 -+ * VIDEOPLL - PLL4 -+ */ -+/* The min,max values for PLL VCO (Hz) */ -+#define PERIPHPLL_MAX_VCO_RATE (1200000000) -+ -+/* The min,max values for PLL PHI0 and PHI1 outputs (Hz) */ -+#define PERIPHPLL_MAX_PHI0_MAX_RATE (400000000) -+#define PERIPHPLL_MAX_PHI1_MAX_RATE (100000000) -+ -+/* The maximum value for PLL VCO according to data sheet */ -+#define MAX_VCO_RATE (1300000000) -+#define MIN_VCO_RATE (650000000) -+ -+enum s32v234_plldig_type { -+ S32_PLLDIG_ARM, -+ S32_PLLDIG_PERIPH, -+ S32_PLLDIG_ENET, -+ S32_PLLDIG_DDR, -+ S32_PLLDIG_VIDEO, -+}; -+ -+#endif -diff --git a/drivers/clk/s32/s32v234/src.h b/drivers/clk/s32/s32v234/src.h -new file mode 100644 -index 000000000..39fa973b7 ---- /dev/null -+++ b/drivers/clk/s32/s32v234/src.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2016 Freescale Semiconductor, Inc. -+ */ -+#ifndef _SRC_H -+#define _SRC_H -+ -+/* Source Reset Control: General Purpose Register 1 */ -+#define SRC_GPR1 (src_base + 0x100) -+#define SRC_GPR1_ARMPLL_SRC_SEL_OFFSET (27) -+#define SRC_GPR1_ENETPLL_SRC_SEL_OFFSET (28) -+#define SRC_GPR1_DDRPLL_SRC_SEL_OFFSET (29) -+#define SRC_GPR1_PERIPHPLL_SRC_SEL_OFFSET (30) -+#define SRC_GPR1_VIDEOPLL_SRC_SEL_OFFSET (31) -+#define SRC_GPR1_XPLL_SRC_SEL_SIZE (1) -+ -+#endif -diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c -index 5bf5fc759..88b476826 100644 ---- a/drivers/cpufreq/imx6q-cpufreq.c -+++ b/drivers/cpufreq/imx6q-cpufreq.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2013 Freescale Semiconductor, Inc. - */ - -+#include - #include - #include - #include -@@ -14,14 +15,27 @@ - #include - #include - #include -+#include - - #define PU_SOC_VOLTAGE_NORMAL 1250000 - #define PU_SOC_VOLTAGE_HIGH 1275000 - #define FREQ_1P2_GHZ 1200000000 -+#define FREQ_396_MHZ 396000 - --static struct regulator *arm_reg; --static struct regulator *pu_reg; --static struct regulator *soc_reg; -+#define PU_SOC_VOLTAGE_NORMAL 1250000 -+#define PU_SOC_VOLTAGE_HIGH 1275000 -+#define DC_VOLTAGE_MIN 1300000 -+#define DC_VOLTAGE_MAX 1400000 -+#define FREQ_1P2_GHZ 1200000000 -+#define FREQ_396_MHZ 396000 -+#define FREQ_528_MHZ 528000 -+#define FREQ_198_MHZ 198000 -+#define FREQ_24_MHZ 24000 -+ -+struct regulator *arm_reg; -+struct regulator *pu_reg; -+struct regulator *soc_reg; -+struct regulator *dc_reg; - - enum IMX6_CPUFREQ_CLKS { - ARM, -@@ -29,12 +43,15 @@ enum IMX6_CPUFREQ_CLKS { - STEP, - PLL1_SW, - PLL2_PFD2_396M, -+ PLL1, -+ PLL1_BYPASS, -+ PLL1_BYPASS_SRC, - /* MX6UL requires two more clks */ - PLL2_BUS, - SECONDARY_SEL, - }; --#define IMX6Q_CPUFREQ_CLK_NUM 5 --#define IMX6UL_CPUFREQ_CLK_NUM 7 -+#define IMX6Q_CPUFREQ_CLK_NUM 8 -+#define IMX6UL_CPUFREQ_CLK_NUM 10 - - static int num_clks; - static struct clk_bulk_data clks[] = { -@@ -43,6 +60,9 @@ static struct clk_bulk_data clks[] = { - { .id = "step" }, - { .id = "pll1_sw" }, - { .id = "pll2_pfd2_396m" }, -+ { .id = "pll1" }, -+ { .id = "pll1_bypass" }, -+ { .id = "pll1_bypass_src" }, - { .id = "pll2_bus" }, - { .id = "secondary_sel" }, - }; -@@ -55,6 +75,9 @@ static unsigned int transition_latency; - static u32 *imx6_soc_volt; - static u32 soc_opp_count; - -+static bool ignore_dc_reg; -+static bool low_power_run_support; -+ - static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) - { - struct dev_pm_opp *opp; -@@ -65,7 +88,16 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) - - new_freq = freq_table[index].frequency; - freq_hz = new_freq * 1000; -- old_freq = clk_get_rate(clks[ARM].clk) / 1000; -+ old_freq = policy->cur; -+ -+ /* -+ * ON i.MX6ULL, the 24MHz setpoint is not seen by cpufreq -+ * so we neet to prevent the cpufreq change frequency -+ * from 24MHz to 198Mhz directly. busfreq will handle this -+ * when exit from low bus mode. -+ */ -+ if (old_freq == FREQ_24_MHZ && new_freq == FREQ_198_MHZ) -+ return 0; - - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); - if (IS_ERR(opp)) { -@@ -82,6 +114,13 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) - old_freq / 1000, volt_old / 1000, - new_freq / 1000, volt / 1000); - -+ if (low_power_run_support) { -+ if (old_freq == freq_table[0].frequency) -+ request_bus_freq(BUS_FREQ_HIGH); -+ } else if (old_freq <= FREQ_396_MHZ && new_freq > FREQ_396_MHZ) { -+ request_bus_freq(BUS_FREQ_HIGH); -+ } -+ - /* scaling up? scale voltage before frequency */ - if (new_freq > old_freq) { - if (!IS_ERR(pu_reg)) { -@@ -142,11 +181,18 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) - clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); - clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); - if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { -+ /* Ensure that pll1_bypass is set back to -+ * pll1. We have to do this first so that the -+ * change rate done to pll1_sys_clk done below -+ * can propagate up to pll1. -+ */ -+ clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1].clk); - clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); - clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); - } else { - /* pll1_sys needs to be enabled for divider rate change to work. */ - pll1_sys_temp_enabled = true; -+ clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1_BYPASS_SRC].clk); - clk_prepare_enable(clks[PLL1_SYS].clk); - } - } -@@ -184,16 +230,34 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) - } - } - -+ /* -+ * If CPU is dropped to the lowest level, release the need -+ * for a high bus frequency. -+ */ -+ if (low_power_run_support) { -+ if (new_freq == freq_table[0].frequency) -+ release_bus_freq(BUS_FREQ_HIGH); -+ } else if (old_freq > FREQ_396_MHZ && new_freq <= FREQ_396_MHZ) { -+ release_bus_freq(BUS_FREQ_HIGH); -+ } -+ - return 0; - } - - static int imx6q_cpufreq_init(struct cpufreq_policy *policy) - { - policy->clk = clks[ARM].clk; -+ policy->cur = clk_get_rate(policy->clk) / 1000; - cpufreq_generic_init(policy, freq_table, transition_latency); - policy->suspend_freq = max_freq; - dev_pm_opp_of_register_em(cpu_dev, policy->cpus); - -+ if (low_power_run_support && policy->cur > freq_table[0].frequency) { -+ request_bus_freq(BUS_FREQ_HIGH); -+ } else if (policy->cur > FREQ_396_MHZ) { -+ request_bus_freq(BUS_FREQ_HIGH); -+ } -+ - return 0; - } - -@@ -335,6 +399,43 @@ static int imx6ul_opp_check_speed_grading(struct device *dev) - return ret; - } - -+static int imx6_cpufreq_pm_notify(struct notifier_block *nb, -+ unsigned long event, void *dummy) -+{ -+ int ret; -+ -+ switch (event) { -+ case PM_SUSPEND_PREPARE: -+ if (!IS_ERR(dc_reg) && !ignore_dc_reg) { -+ ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MAX, 0); -+ if (ret) { -+ dev_err(cpu_dev, -+ "failed to scale dc_reg to max: %d\n", ret); -+ return ret; -+ } -+ } -+ break; -+ case PM_POST_SUSPEND: -+ if (!IS_ERR(dc_reg) && !ignore_dc_reg) { -+ ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); -+ if (ret) { -+ dev_err(cpu_dev, -+ "failed to scale dc_reg to min: %d\n", ret); -+ return ret; -+ } -+ } -+ break; -+ default: -+ break; -+ } -+ -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block imx6_cpufreq_pm_notifier = { -+ .notifier_call = imx6_cpufreq_pm_notify, -+}; -+ - static int imx6q_cpufreq_probe(struct platform_device *pdev) - { - struct device_node *np; -@@ -383,6 +484,11 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) - goto put_reg; - } - -+ dc_reg = devm_regulator_get_optional(cpu_dev, "dc"); -+ -+ /* On i.MX6ULL, check the 24MHz low power run mode support */ -+ low_power_run_support = of_property_read_bool(np, "fsl,low-power-run"); -+ - ret = dev_pm_opp_of_add_table(cpu_dev); - if (ret < 0) { - dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); -@@ -415,6 +521,21 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) - goto out_free_opp; - } - -+ /* -+ * On i.MX6UL/ULL EVK board, if the SOC is run in overide frequency, -+ * the dc_regulator voltage should not be touched. -+ */ -+ if (freq_table[num - 1].frequency > FREQ_528_MHZ) -+ ignore_dc_reg = true; -+ if (!IS_ERR(dc_reg) && !ignore_dc_reg) { -+ ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); -+ if (ret) { -+ dev_err(cpu_dev, -+ "failed to scale dc_reg to min: %d\n", ret); -+ return ret; -+ } -+ } -+ - /* Make imx6_soc_volt array's size same as arm opp number */ - imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), - GFP_KERNEL); -@@ -497,6 +618,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) - goto free_freq_table; - } - -+ register_pm_notifier(&imx6_cpufreq_pm_notifier); -+ - of_node_put(np); - return 0; - -diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig -index 84ea7cba5..2bd830668 100644 ---- a/drivers/crypto/caam/Kconfig -+++ b/drivers/crypto/caam/Kconfig -@@ -8,6 +8,17 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC - config CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC - tristate - -+config CRYPTO_DEV_FSL_CAAM_KEYBLOB_API_DESC -+ tristate -+ -+config CRYPTO_DEV_FSL_CAAM_SECVIO -+ tristate "CAAM/SNVS Security Violation Handler" -+ depends on ARCH_MXC -+ help -+ Enables installation of an interrupt handler with registrable -+ handler functions which can be specified to act on the consequences -+ of a security violation. -+ - config CRYPTO_DEV_FSL_CAAM - tristate "Freescale CAAM-Multicore platform driver backend" - depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE -@@ -109,7 +120,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API - - config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI - bool "Queue Interface as Crypto API backend" -- depends on FSL_DPAA && NET -+ depends on FSL_SDK_DPA && NET - default y - select CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC - select CRYPTO_AUTHENC -@@ -151,6 +162,79 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API - Selecting this will register the SEC4 hardware rng to - the hw_random API for supplying the kernel entropy pool. - -+config CRYPTO_DEV_FSL_CAAM_TK_API -+ bool "Register tagged key cryptography implementations with Crypto API" -+ default y -+ select CRYPTO_DEV_FSL_CAAM_CRYPTO_API -+ select CRYPTO_DEV_FSL_CAAM_KEYBLOB_API_DESC -+ help -+ Selecting this will register algorithms supporting tagged key and -+ generate black keys and encapsulate them into black blobs. -+ -+ Tagged keys are black keys that contain metadata indicating what -+ they are and how to handle them. -+ CAAM protects data in a data structure called a Blob, which provides -+ both confidentiality and integrity protection. -+ -+config CRYPTO_DEV_FSL_CAAM_TK_API_TEST -+ tristate "CAAM keys and blobs test" -+ depends on CRYPTO_DEV_FSL_CAAM_TK_API -+ depends on m -+ help -+ Test to exercise black key generation and blob encapsulation and -+ decapsulation. -+ -+config CRYPTO_DEV_FSL_CAAM_RNG_TEST -+ bool "Test caam rng" -+ depends on CRYPTO_DEV_FSL_CAAM_RNG_API -+ help -+ Selecting this will enable a self-test to run for the -+ caam RNG. This test is several minutes long and executes -+ just before the RNG is registered with the hw_random API. -+ -+config CRYPTO_DEV_FSL_CAAM_SM -+ bool "CAAM Secure Memory / Keystore API" -+ default y -+ help -+ Enables use of a prototype kernel-level Keystore API with CAAM -+ Secure Memory for insertion/extraction of bus-protected secrets. -+ -+config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE -+ int "Size of each keystore slot in Secure Memory" -+ depends on CRYPTO_DEV_FSL_CAAM_SM -+ range 5 9 -+ default 7 -+ help -+ Select size of allocation units to divide Secure Memory pages into -+ (the size of a "slot" as referenced inside the API code). -+ Established as powers of two. -+ Examples: -+ 5 => 32 bytes -+ 6 => 64 bytes -+ 7 => 128 bytes -+ 8 => 256 bytes -+ 9 => 512 bytes -+ -+config CRYPTO_DEV_FSL_CAAM_SM_TEST -+ tristate "CAAM Secure Memory - Keystore Test/Example" -+ depends on CRYPTO_DEV_FSL_CAAM_SM -+ depends on m -+ help -+ Example thread to exercise the Keystore API and to verify that -+ stored and recovered secrets can be used for general purpose -+ encryption/decryption. -+ -+config CRYPTO_DEV_FSL_CAAM_JR_UIO -+ tristate "Freescale Job Ring UIO support" -+ depends on UIO -+ default m -+ help -+ Selecting this will allow job ring UIO support for -+ Userspace drivers -+ -+ To compile this as a module, choose M here: the module -+ will be called fsl_jr_uio. -+ - endif # CRYPTO_DEV_FSL_CAAM_JR - - endif # CRYPTO_DEV_FSL_CAAM -diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile -index 3570286eb..3534f1a0e 100644 ---- a/drivers/crypto/caam/Makefile -+++ b/drivers/crypto/caam/Makefile -@@ -13,14 +13,21 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC) += caamhash_desc.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_KEYBLOB_API_DESC) += caamkeyblob_desc.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR_UIO) += fsl_jr_uio.o - - caam-y := ctrl.o - caam_jr-y := jr.o key_gen.o -+caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) += tag_object.o caamkeyblob.o caamkeygen.o - caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o - caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o - caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o - caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o - caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caampkc.o pkc_desc.o -+caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API_TEST) += caamkeyblob_test.o - - caam-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += qi.o - ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),) -diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c -index 8697ae53b..46dcf0728 100644 ---- a/drivers/crypto/caam/caamalg.c -+++ b/drivers/crypto/caam/caamalg.c -@@ -3,7 +3,7 @@ - * caam - Freescale FSL CAAM support for crypto API - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. -- * Copyright 2016-2019 NXP -+ * Copyright 2016-2020 NXP - * - * Based on talitos crypto API driver. - * -@@ -60,6 +60,10 @@ - #include - #include - -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API -+#include "tag_object.h" -+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ -+ - /* - * crypto alg - */ -@@ -86,6 +90,7 @@ struct caam_alg_entry { - bool rfc3686; - bool geniv; - bool nodkp; -+ bool support_tagged_key; - }; - - struct caam_aead_alg { -@@ -738,12 +743,19 @@ static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, - u32 *desc; - const bool is_rfc3686 = alg->caam.rfc3686; - -- print_hex_dump_debug("key in @"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); -+ /* -+ * If the algorithm has support for tagged key, -+ * this is already set in tk_skcipher_setkey(). -+ * Otherwise, set here the algorithm details. -+ */ -+ if (!alg->caam.support_tagged_key) { -+ ctx->cdata.keylen = keylen; -+ ctx->cdata.key_virt = key; -+ ctx->cdata.key_inline = true; -+ } - -- ctx->cdata.keylen = keylen; -- ctx->cdata.key_virt = key; -- ctx->cdata.key_inline = true; -+ print_hex_dump_debug("key in @" __stringify(__LINE__) ": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); - - /* skcipher_encrypt shared descriptor */ - desc = ctx->sh_desc_enc; -@@ -815,6 +827,63 @@ static int ctr_skcipher_setkey(struct crypto_skcipher *skcipher, - return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off); - } - -+ -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API -+static int tk_skcipher_setkey(struct crypto_skcipher *skcipher, -+ const u8 *key, unsigned int keylen) -+{ -+ struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); -+ struct device *jrdev = ctx->jrdev; -+ struct header_conf *header; -+ struct tagged_object *tag_obj; -+ int ret; -+ -+ ctx->cdata.key_inline = true; -+ -+ /* Check if one can retrieve the tag object header configuration */ -+ if (keylen <= TAG_OVERHEAD_SIZE) -+ return -EINVAL; -+ -+ /* Retrieve the tag object */ -+ tag_obj = (struct tagged_object *)key; -+ -+ /* -+ * Check tag object header configuration -+ * and retrieve the tag object header configuration -+ */ -+ if (is_valid_header_conf(&tag_obj->header)) { -+ header = &tag_obj->header; -+ } else { -+ dev_err(jrdev, -+ "unable to get tag object header configuration\n"); -+ return -EINVAL; -+ } -+ -+ /* Check if the tag object header is a black key */ -+ if (!is_black_key(header)) { -+ dev_err(jrdev, -+ "tagged key provided is not a black key\n"); -+ return -EINVAL; -+ } -+ -+ /* Retrieve the black key configuration */ -+ get_key_conf(header, -+ &ctx->cdata.key_real_len, -+ &ctx->cdata.keylen, -+ &ctx->cdata.key_cmd_opt); -+ -+ /* Retrieve the address of the data of the tagged object */ -+ ctx->cdata.key_virt = &tag_obj->object; -+ -+ /* Validate key length for AES algorithms */ -+ ret = aes_check_keylen(ctx->cdata.key_real_len); -+ if (ret) -+ return ret; -+ -+ return skcipher_setkey(skcipher, NULL, 0, 0); -+} -+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ -+ - static int des_skcipher_setkey(struct crypto_skcipher *skcipher, - const u8 *key, unsigned int keylen) - { -@@ -1874,6 +1943,25 @@ static struct caam_skcipher_alg driver_algs[] = { - }, - .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, - }, -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API -+ { -+ .skcipher = { -+ .base = { -+ .cra_name = "tk(cbc(aes))", -+ .cra_driver_name = "tk-cbc-aes-caam", -+ .cra_blocksize = AES_BLOCK_SIZE, -+ }, -+ .setkey = tk_skcipher_setkey, -+ .encrypt = skcipher_encrypt, -+ .decrypt = skcipher_decrypt, -+ .min_keysize = TAG_MIN_SIZE, -+ .max_keysize = CAAM_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ }, -+ .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, -+ .caam.support_tagged_key = true, -+ }, -+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ - { - .skcipher = { - .base = { -@@ -1994,6 +2082,24 @@ static struct caam_skcipher_alg driver_algs[] = { - }, - .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, - }, -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API -+ { -+ .skcipher = { -+ .base = { -+ .cra_name = "tk(ecb(aes))", -+ .cra_driver_name = "tk-ecb-aes-caam", -+ .cra_blocksize = AES_BLOCK_SIZE, -+ }, -+ .setkey = tk_skcipher_setkey, -+ .encrypt = skcipher_encrypt, -+ .decrypt = skcipher_decrypt, -+ .min_keysize = TAG_MIN_SIZE, -+ .max_keysize = CAAM_MAX_KEY_SIZE, -+ }, -+ .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, -+ .caam.support_tagged_key = true, -+ }, -+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ - { - .skcipher = { - .base = { -@@ -3520,13 +3626,14 @@ int caam_algapi_init(struct device *ctrldev) - * First, detect presence and attributes of DES, AES, and MD blocks. - */ - if (priv->era < 10) { -+ struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; - u32 cha_vid, cha_inst, aes_rn; - -- cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls); -+ cha_vid = rd_reg32(&perfmon->cha_id_ls); - aes_vid = cha_vid & CHA_ID_LS_AES_MASK; - md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; - -- cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls); -+ cha_inst = rd_reg32(&perfmon->cha_num_ls); - des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> - CHA_ID_LS_DES_SHIFT; - aes_inst = cha_inst & CHA_ID_LS_AES_MASK; -@@ -3534,23 +3641,23 @@ int caam_algapi_init(struct device *ctrldev) - ccha_inst = 0; - ptha_inst = 0; - -- aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) & -- CHA_ID_LS_AES_MASK; -+ aes_rn = rd_reg32(&perfmon->cha_rev_ls) & CHA_ID_LS_AES_MASK; - gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8); - } else { -+ struct version_regs __iomem *vreg = &priv->jr[0]->vreg; - u32 aesa, mdha; - -- aesa = rd_reg32(&priv->ctrl->vreg.aesa); -- mdha = rd_reg32(&priv->ctrl->vreg.mdha); -+ aesa = rd_reg32(&vreg->aesa); -+ mdha = rd_reg32(&vreg->mdha); - - aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; - md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; - -- des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK; -+ des_inst = rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK; - aes_inst = aesa & CHA_VER_NUM_MASK; - md_inst = mdha & CHA_VER_NUM_MASK; -- ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK; -- ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK; -+ ccha_inst = rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK; -+ ptha_inst = rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK; - - gcm_support = aesa & CHA_VER_MISC_AES_GCM; - } -diff --git a/drivers/crypto/caam/caamalg_desc.c b/drivers/crypto/caam/caamalg_desc.c -index 7571e1ac9..fa1309e90 100644 ---- a/drivers/crypto/caam/caamalg_desc.c -+++ b/drivers/crypto/caam/caamalg_desc.c -@@ -622,6 +622,420 @@ void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata, - } - EXPORT_SYMBOL(cnstr_shdsc_aead_givencap); - -+/** -+ * cnstr_shdsc_tls_encap - tls encapsulation shared descriptor -+ * @desc: pointer to buffer used for descriptor construction -+ * @cdata: pointer to block cipher transform definitions -+ * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed -+ * with OP_ALG_AAI_CBC -+ * @adata: pointer to authentication transform definitions. -+ * A split key is required for SEC Era < 6; the size of the split key -+ * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 -+ * ANDed with OP_ALG_AAI_HMAC_PRECOMP. -+ * @assoclen: associated data length -+ * @ivsize: initialization vector size -+ * @authsize: authentication data size -+ * @blocksize: block cipher size -+ * @era: SEC Era -+ */ -+void cnstr_shdsc_tls_encap(u32 * const desc, struct alginfo *cdata, -+ struct alginfo *adata, unsigned int assoclen, -+ unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize, int era) -+{ -+ u32 *key_jump_cmd, *zero_payload_jump_cmd; -+ u32 genpad, idx_ld_datasz, idx_ld_pad, stidx; -+ -+ /* -+ * Compute the index (in bytes) for the LOAD with destination of -+ * Class 1 Data Size Register and for the LOAD that generates padding -+ */ -+ if (adata->key_inline) { -+ idx_ld_datasz = DESC_TLS10_ENC_LEN + adata->keylen_pad + -+ cdata->keylen - 4 * CAAM_CMD_SZ; -+ idx_ld_pad = DESC_TLS10_ENC_LEN + adata->keylen_pad + -+ cdata->keylen - 2 * CAAM_CMD_SZ; -+ } else { -+ idx_ld_datasz = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ - -+ 4 * CAAM_CMD_SZ; -+ idx_ld_pad = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ - -+ 2 * CAAM_CMD_SZ; -+ } -+ -+ stidx = 1 << HDR_START_IDX_SHIFT; -+ init_sh_desc(desc, HDR_SHARE_SERIAL | stidx); -+ -+ /* skip key loading if they are loaded due to sharing */ -+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -+ JUMP_COND_SHRD); -+ -+ if (era < 6) { -+ if (adata->key_inline) -+ append_key_as_imm(desc, adata->key_virt, -+ adata->keylen_pad, adata->keylen, -+ CLASS_2 | KEY_DEST_MDHA_SPLIT | -+ KEY_ENC); -+ else -+ append_key(desc, adata->key_dma, adata->keylen, -+ CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); -+ } else { -+ append_proto_dkp(desc, adata); -+ } -+ -+ if (cdata->key_inline) -+ append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -+ cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); -+ else -+ append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | -+ KEY_DEST_CLASS_REG); -+ -+ set_jump_tgt_here(desc, key_jump_cmd); -+ -+ /* class 2 operation */ -+ append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | -+ OP_ALG_ENCRYPT); -+ /* class 1 operation */ -+ append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL | -+ OP_ALG_ENCRYPT); -+ -+ /* payloadlen = input data length - (assoclen + ivlen) */ -+ append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, assoclen + ivsize); -+ -+ /* math1 = payloadlen + icvlen */ -+ append_math_add_imm_u32(desc, REG1, REG0, IMM, authsize); -+ -+ /* padlen = block_size - math1 % block_size */ -+ append_math_and_imm_u32(desc, REG3, REG1, IMM, blocksize - 1); -+ append_math_sub_imm_u32(desc, REG2, IMM, REG3, blocksize); -+ -+ /* cryptlen = payloadlen + icvlen + padlen */ -+ append_math_add(desc, VARSEQOUTLEN, REG1, REG2, 4); -+ -+ /* -+ * update immediate data with the padding length value -+ * for the LOAD in the class 1 data size register. -+ */ -+ append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 | -+ (idx_ld_datasz << MOVE_OFFSET_SHIFT) | 7); -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF | -+ (idx_ld_datasz << MOVE_OFFSET_SHIFT) | 8); -+ -+ /* overwrite PL field for the padding iNFO FIFO entry */ -+ append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 | -+ (idx_ld_pad << MOVE_OFFSET_SHIFT) | 7); -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF | -+ (idx_ld_pad << MOVE_OFFSET_SHIFT) | 8); -+ -+ /* store encrypted payload, icv and padding */ -+ append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF); -+ -+ /* if payload length is zero, jump to zero-payload commands */ -+ append_math_add(desc, VARSEQINLEN, ZERO, REG0, 4); -+ zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | -+ JUMP_COND_MATH_Z); -+ -+ /* load iv in context1 */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | -+ LDST_CLASS_1_CCB | ivsize); -+ -+ /* read assoc for authentication */ -+ append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 | -+ FIFOLD_TYPE_MSG); -+ /* insnoop payload */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLD_TYPE_MSG | -+ FIFOLD_TYPE_LAST2 | FIFOLDST_VLF); -+ -+ /* jump the zero-payload commands */ -+ append_jump(desc, JUMP_TEST_ALL | 3); -+ -+ /* zero-payload commands */ -+ set_jump_tgt_here(desc, zero_payload_jump_cmd); -+ -+ /* load iv in context1 */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | -+ LDST_CLASS_1_CCB | ivsize); -+ -+ /* assoc data is the only data for authentication */ -+ append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 | -+ FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2); -+ -+ /* send icv to encryption */ -+ append_move(desc, MOVE_SRC_CLASS2CTX | MOVE_DEST_CLASS1INFIFO | -+ authsize); -+ -+ /* update class 1 data size register with padding length */ -+ append_load_imm_u32(desc, 0, LDST_CLASS_1_CCB | -+ LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM); -+ -+ /* generate padding and send it to encryption */ -+ genpad = NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_LC1 | NFIFOENTRY_FC1 | -+ NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_PTYPE_N; -+ append_load_imm_u32(desc, genpad, LDST_CLASS_IND_CCB | -+ LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); -+ -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "tls enc shdesc@" __stringify(__LINE__) ": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, -+ desc_bytes(desc), 1); -+#endif -+} -+EXPORT_SYMBOL(cnstr_shdsc_tls_encap); -+ -+/** -+ * cnstr_shdsc_tls_decap - tls decapsulation shared descriptor -+ * @desc: pointer to buffer used for descriptor construction -+ * @cdata: pointer to block cipher transform definitions -+ * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed -+ * with OP_ALG_AAI_CBC -+ * @adata: pointer to authentication transform definitions. -+ * A split key is required for SEC Era < 6; the size of the split key -+ * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 -+ * ANDed with OP_ALG_AAI_HMAC_PRECOMP. -+ * @assoclen: associated data length -+ * @ivsize: initialization vector size -+ * @authsize: authentication data size -+ * @blocksize: block cipher size -+ * @era: SEC Era -+ */ -+void cnstr_shdsc_tls_decap(u32 * const desc, struct alginfo *cdata, -+ struct alginfo *adata, unsigned int assoclen, -+ unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize, int era) -+{ -+ u32 stidx, jumpback; -+ u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd; -+ /* -+ * Pointer Size bool determines the size of address pointers. -+ * false - Pointers fit in one 32-bit word. -+ * true - Pointers fit in two 32-bit words. -+ */ -+ bool ps = (CAAM_PTR_SZ != CAAM_CMD_SZ); -+ -+ stidx = 1 << HDR_START_IDX_SHIFT; -+ init_sh_desc(desc, HDR_SHARE_SERIAL | stidx); -+ -+ /* skip key loading if they are loaded due to sharing */ -+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -+ JUMP_COND_SHRD); -+ -+ if (era < 6) -+ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); -+ else -+ append_proto_dkp(desc, adata); -+ -+ append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | -+ KEY_DEST_CLASS_REG); -+ -+ set_jump_tgt_here(desc, key_jump_cmd); -+ -+ /* class 2 operation */ -+ append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | -+ OP_ALG_DECRYPT | OP_ALG_ICV_ON); -+ /* class 1 operation */ -+ append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL | -+ OP_ALG_DECRYPT); -+ -+ /* VSIL = input data length - 2 * block_size */ -+ append_math_sub_imm_u32(desc, VARSEQINLEN, SEQINLEN, IMM, 2 * -+ blocksize); -+ -+ /* -+ * payloadlen + icvlen + padlen = input data length - (assoclen + -+ * ivsize) -+ */ -+ append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, assoclen + ivsize); -+ -+ /* skip data to the last but one cipher block */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | LDST_VLF); -+ -+ /* load iv for the last cipher block */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | -+ LDST_CLASS_1_CCB | ivsize); -+ -+ /* read last cipher block */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG | -+ FIFOLD_TYPE_LAST1 | blocksize); -+ -+ /* move decrypted block into math0 and math1 */ -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO | MOVE_DEST_MATH0 | -+ blocksize); -+ -+ /* reset AES CHA */ -+ append_load_imm_u32(desc, CCTRL_RESET_CHA_AESA, LDST_CLASS_IND_CCB | -+ LDST_SRCDST_WORD_CHACTRL | LDST_IMM); -+ -+ /* rewind input sequence */ -+ append_seq_in_ptr_intlen(desc, 0, 65535, SQIN_RTO); -+ -+ /* key1 is in decryption form */ -+ append_operation(desc, cdata->algtype | OP_ALG_AAI_DK | -+ OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT); -+ -+ /* load iv in context1 */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_1_CCB | -+ LDST_SRCDST_WORD_CLASS_CTX | ivsize); -+ -+ /* read sequence number */ -+ append_seq_fifo_load(desc, 8, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG); -+ /* load Type, Version and Len fields in math0 */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_DECO | -+ LDST_SRCDST_WORD_DECO_MATH0 | (3 << LDST_OFFSET_SHIFT) | 5); -+ -+ /* compute (padlen - 1) */ -+ append_math_and_imm_u64(desc, REG1, REG1, IMM, 255); -+ -+ /* math2 = icvlen + (padlen - 1) + 1 */ -+ append_math_add_imm_u32(desc, REG2, REG1, IMM, authsize + 1); -+ -+ append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); -+ -+ /* VSOL = payloadlen + icvlen + padlen */ -+ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, 4); -+ -+ if (caam_little_end) -+ append_moveb(desc, MOVE_WAITCOMP | -+ MOVE_SRC_MATH0 | MOVE_DEST_MATH0 | 8); -+ -+ /* update Len field */ -+ append_math_sub(desc, REG0, REG0, REG2, 8); -+ -+ /* store decrypted payload, icv and padding */ -+ append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF); -+ -+ /* VSIL = (payloadlen + icvlen + padlen) - (icvlen + padlen)*/ -+ append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4); -+ -+ zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | -+ JUMP_COND_MATH_Z); -+ -+ /* send Type, Version and Len(pre ICV) fields to authentication */ -+ append_move(desc, MOVE_WAITCOMP | -+ MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO | -+ (3 << MOVE_OFFSET_SHIFT) | 5); -+ -+ /* outsnooping payload */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | -+ FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LAST2 | -+ FIFOLDST_VLF); -+ skip_zero_jump_cmd = append_jump(desc, JUMP_TEST_ALL | 2); -+ -+ set_jump_tgt_here(desc, zero_payload_jump_cmd); -+ /* send Type, Version and Len(pre ICV) fields to authentication */ -+ append_move(desc, MOVE_WAITCOMP | MOVE_AUX_LS | -+ MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO | -+ (3 << MOVE_OFFSET_SHIFT) | 5); -+ -+ set_jump_tgt_here(desc, skip_zero_jump_cmd); -+ append_math_add(desc, VARSEQINLEN, ZERO, REG2, 4); -+ -+ /* load icvlen and padlen */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG | -+ FIFOLD_TYPE_LAST1 | FIFOLDST_VLF); -+ -+ /* VSIL = (payloadlen + icvlen + padlen) - icvlen + padlen */ -+ append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4); -+ -+ /* -+ * Start a new input sequence using the SEQ OUT PTR command options, -+ * pointer and length used when the current output sequence was defined. -+ */ -+ if (ps) { -+ /* -+ * Move the lower 32 bits of Shared Descriptor address, the -+ * SEQ OUT PTR command, Output Pointer (2 words) and -+ * Output Length into math registers. -+ */ -+ if (caam_little_end) -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | -+ MOVE_DEST_MATH0 | -+ (55 * 4 << MOVE_OFFSET_SHIFT) | 20); -+ else -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | -+ MOVE_DEST_MATH0 | -+ (54 * 4 << MOVE_OFFSET_SHIFT) | 20); -+ -+ /* Transform SEQ OUT PTR command in SEQ IN PTR command */ -+ append_math_and_imm_u32(desc, REG0, REG0, IMM, -+ ~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR)); -+ /* Append a JUMP command after the copied fields */ -+ jumpback = CMD_JUMP | (char)-9; -+ append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM | -+ LDST_SRCDST_WORD_DECO_MATH2 | -+ (4 << LDST_OFFSET_SHIFT)); -+ append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); -+ /* Move the updated fields back to the Job Descriptor */ -+ if (caam_little_end) -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | -+ MOVE_DEST_DESCBUF | -+ (55 * 4 << MOVE_OFFSET_SHIFT) | 24); -+ else -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | -+ MOVE_DEST_DESCBUF | -+ (54 * 4 << MOVE_OFFSET_SHIFT) | 24); -+ -+ /* -+ * Read the new SEQ IN PTR command, Input Pointer, Input Length -+ * and then jump back to the next command from the -+ * Shared Descriptor. -+ */ -+ append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 6); -+ } else { -+ /* -+ * Move the SEQ OUT PTR command, Output Pointer (1 word) and -+ * Output Length into math registers. -+ */ -+ if (caam_little_end) -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | -+ MOVE_DEST_MATH0 | -+ (54 * 4 << MOVE_OFFSET_SHIFT) | 12); -+ else -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | -+ MOVE_DEST_MATH0 | -+ (53 * 4 << MOVE_OFFSET_SHIFT) | 12); -+ -+ /* Transform SEQ OUT PTR command in SEQ IN PTR command */ -+ append_math_and_imm_u64(desc, REG0, REG0, IMM, -+ ~(((u64)(CMD_SEQ_IN_PTR ^ -+ CMD_SEQ_OUT_PTR)) << 32)); -+ /* Append a JUMP command after the copied fields */ -+ jumpback = CMD_JUMP | (char)-7; -+ append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM | -+ LDST_SRCDST_WORD_DECO_MATH1 | -+ (4 << LDST_OFFSET_SHIFT)); -+ append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); -+ /* Move the updated fields back to the Job Descriptor */ -+ if (caam_little_end) -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | -+ MOVE_DEST_DESCBUF | -+ (54 * 4 << MOVE_OFFSET_SHIFT) | 16); -+ else -+ append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | -+ MOVE_DEST_DESCBUF | -+ (53 * 4 << MOVE_OFFSET_SHIFT) | 16); -+ -+ /* -+ * Read the new SEQ IN PTR command, Input Pointer, Input Length -+ * and then jump back to the next command from the -+ * Shared Descriptor. -+ */ -+ append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 5); -+ } -+ -+ /* skip payload */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | FIFOLDST_VLF); -+ /* check icv */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_ICV | -+ FIFOLD_TYPE_LAST2 | authsize); -+ -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "tls dec shdesc@" __stringify(__LINE__) ": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, -+ desc_bytes(desc), 1); -+#endif -+} -+EXPORT_SYMBOL(cnstr_shdsc_tls_decap); -+ - /** - * cnstr_shdsc_gcm_encap - gcm encapsulation shared descriptor - * @desc: pointer to buffer used for descriptor construction -@@ -1390,8 +1804,18 @@ void cnstr_shdsc_skcipher_encap(u32 * const desc, struct alginfo *cdata, - JUMP_COND_SHRD); - - /* Load class1 key only */ -- append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -- cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); -+ if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) && -+ cdata->key_cmd_opt) -+ /* -+ * Black keys can be loaded using only a KEY command -+ * with ENC=1 and the proper setting of the EKT bit. -+ */ -+ append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -+ cdata->key_real_len, CLASS_1 | -+ KEY_DEST_CLASS_REG | cdata->key_cmd_opt); -+ else -+ append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -+ cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); - - /* Load nonce into CONTEXT1 reg */ - if (is_rfc3686) { -@@ -1465,8 +1889,18 @@ void cnstr_shdsc_skcipher_decap(u32 * const desc, struct alginfo *cdata, - JUMP_COND_SHRD); - - /* Load class1 key only */ -- append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -- cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); -+ if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) && -+ cdata->key_cmd_opt) -+ /* -+ * Black keys can be loaded using only a KEY command -+ * with ENC=1 and the proper setting of the EKT bit. -+ */ -+ append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -+ cdata->key_real_len, CLASS_1 | -+ KEY_DEST_CLASS_REG | cdata->key_cmd_opt); -+ else -+ append_key_as_imm(desc, cdata->key_virt, cdata->keylen, -+ cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); - - /* Load nonce into CONTEXT1 reg */ - if (is_rfc3686) { -diff --git a/drivers/crypto/caam/caamalg_desc.h b/drivers/crypto/caam/caamalg_desc.h -index f2893393b..99f0d1471 100644 ---- a/drivers/crypto/caam/caamalg_desc.h -+++ b/drivers/crypto/caam/caamalg_desc.h -@@ -17,6 +17,9 @@ - #define DESC_QI_AEAD_DEC_LEN (DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ) - #define DESC_QI_AEAD_GIVENC_LEN (DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ) - -+#define DESC_TLS_BASE (4 * CAAM_CMD_SZ) -+#define DESC_TLS10_ENC_LEN (DESC_TLS_BASE + 29 * CAAM_CMD_SZ) -+ - /* Note: Nonce is counted in cdata.keylen */ - #define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ) - -@@ -72,6 +75,16 @@ void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata, - u32 *nonce, const u32 ctx1_iv_off, - const bool is_qi, int era); - -+void cnstr_shdsc_tls_encap(u32 *const desc, struct alginfo *cdata, -+ struct alginfo *adata, unsigned int assoclen, -+ unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize, int era); -+ -+void cnstr_shdsc_tls_decap(u32 *const desc, struct alginfo *cdata, -+ struct alginfo *adata, unsigned int assoclen, -+ unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize, int era); -+ - void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata, - unsigned int ivsize, unsigned int icvsize, - const bool is_qi); -diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c -index a24ae966d..81a8ee300 100644 ---- a/drivers/crypto/caam/caamalg_qi.c -+++ b/drivers/crypto/caam/caamalg_qi.c -@@ -297,6 +297,166 @@ static int des3_aead_setkey(struct crypto_aead *aead, const u8 *key, - return err; - } - -+static int tls_set_sh_desc(struct crypto_aead *tls) -+{ -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ unsigned int ivsize = crypto_aead_ivsize(tls); -+ unsigned int blocksize = crypto_aead_blocksize(tls); -+ unsigned int assoclen = 13; /* always 13 bytes for TLS */ -+ unsigned int data_len[2]; -+ u32 inl_mask; -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); -+ -+ if (!ctx->cdata.keylen || !ctx->authsize) -+ return 0; -+ -+ /* -+ * TLS 1.0 encrypt shared descriptor -+ * Job Descriptor and Shared Descriptor -+ * must fit into the 64-word Descriptor h/w Buffer -+ */ -+ data_len[0] = ctx->adata.keylen_pad; -+ data_len[1] = ctx->cdata.keylen; -+ -+ if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len, -+ &inl_mask, ARRAY_SIZE(data_len)) < 0) -+ return -EINVAL; -+ -+ if (inl_mask & 1) -+ ctx->adata.key_virt = ctx->key; -+ else -+ ctx->adata.key_dma = ctx->key_dma; -+ -+ if (inl_mask & 2) -+ ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; -+ else -+ ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; -+ -+ ctx->adata.key_inline = !!(inl_mask & 1); -+ ctx->cdata.key_inline = !!(inl_mask & 2); -+ -+ cnstr_shdsc_tls_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata, -+ assoclen, ivsize, ctx->authsize, blocksize, -+ ctrlpriv->era); -+ -+ /* -+ * TLS 1.0 decrypt shared descriptor -+ * Keys do not fit inline, regardless of algorithms used -+ */ -+ ctx->adata.key_inline = false; -+ ctx->adata.key_dma = ctx->key_dma; -+ ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; -+ -+ cnstr_shdsc_tls_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata, -+ assoclen, ivsize, ctx->authsize, blocksize, -+ ctrlpriv->era); -+ -+ return 0; -+} -+ -+static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize) -+{ -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ -+ ctx->authsize = authsize; -+ tls_set_sh_desc(tls); -+ -+ return 0; -+} -+ -+static int tls_setkey(struct crypto_aead *tls, const u8 *key, -+ unsigned int keylen) -+{ -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ struct device *jrdev = ctx->jrdev; -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); -+ struct crypto_authenc_keys keys; -+ int ret = 0; -+ -+ if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) -+ goto badkey; -+ -+#ifdef DEBUG -+ dev_err(jrdev, "keylen %d enckeylen %d authkeylen %d\n", -+ keys.authkeylen + keys.enckeylen, keys.enckeylen, -+ keys.authkeylen); -+ print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); -+#endif -+ -+ /* -+ * If DKP is supported, use it in the shared descriptor to generate -+ * the split key. -+ */ -+ if (ctrlpriv->era >= 6) { -+ ctx->adata.keylen = keys.authkeylen; -+ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & -+ OP_ALG_ALGSEL_MASK); -+ -+ if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) -+ goto badkey; -+ -+ memcpy(ctx->key, keys.authkey, keys.authkeylen); -+ memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, -+ keys.enckeylen); -+ dma_sync_single_for_device(jrdev, ctx->key_dma, -+ ctx->adata.keylen_pad + -+ keys.enckeylen, ctx->dir); -+ goto skip_split_key; -+ } -+ -+ ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey, -+ keys.authkeylen, CAAM_MAX_KEY_SIZE - -+ keys.enckeylen); -+ if (ret) -+ goto badkey; -+ -+ /* postpend encryption key to auth split key */ -+ memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); -+ dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad + -+ keys.enckeylen, ctx->dir); -+ -+#ifdef DEBUG -+ dev_err(jrdev, "split keylen %d split keylen padded %d\n", -+ ctx->adata.keylen, ctx->adata.keylen_pad); -+ print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, -+ ctx->adata.keylen_pad + keys.enckeylen, 1); -+#endif -+ -+skip_split_key: -+ ctx->cdata.keylen = keys.enckeylen; -+ -+ ret = tls_set_sh_desc(tls); -+ if (ret) -+ goto badkey; -+ -+ /* Now update the driver contexts with the new shared descriptor */ -+ if (ctx->drv_ctx[ENCRYPT]) { -+ ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT], -+ ctx->sh_desc_enc); -+ if (ret) { -+ dev_err(jrdev, "driver enc context update failed\n"); -+ goto badkey; -+ } -+ } -+ -+ if (ctx->drv_ctx[DECRYPT]) { -+ ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT], -+ ctx->sh_desc_dec); -+ if (ret) { -+ dev_err(jrdev, "driver dec context update failed\n"); -+ goto badkey; -+ } -+ } -+ -+ memzero_explicit(&keys, sizeof(keys)); -+ return ret; -+badkey: -+ memzero_explicit(&keys, sizeof(keys)); -+ return -EINVAL; -+} -+ - static int gcm_set_sh_desc(struct crypto_aead *aead) - { - struct caam_ctx *ctx = crypto_aead_ctx(aead); -@@ -806,6 +966,29 @@ struct aead_edesc { - struct qm_sg_entry sgt[]; - }; - -+/* -+ * tls_edesc - s/w-extended tls descriptor -+ * @src_nents: number of segments in input scatterlist -+ * @dst_nents: number of segments in output scatterlist -+ * @iv_dma: dma address of iv for checking continuity and link table -+ * @qm_sg_bytes: length of dma mapped h/w link table -+ * @tmp: array of scatterlists used by 'scatterwalk_ffwd' -+ * @qm_sg_dma: bus physical mapped address of h/w link table -+ * @drv_req: driver-specific request structure -+ * @sgt: the h/w link table, followed by IV -+ */ -+struct tls_edesc { -+ int src_nents; -+ int dst_nents; -+ dma_addr_t iv_dma; -+ int qm_sg_bytes; -+ dma_addr_t qm_sg_dma; -+ struct scatterlist tmp[2]; -+ struct scatterlist *dst; -+ struct caam_drv_req drv_req; -+ struct qm_sg_entry sgt[0]; -+}; -+ - /* - * skcipher_edesc - s/w-extended skcipher descriptor - * @src_nents: number of segments in input scatterlist -@@ -898,6 +1081,18 @@ static void aead_unmap(struct device *dev, - dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE); - } - -+static void tls_unmap(struct device *dev, -+ struct tls_edesc *edesc, -+ struct aead_request *req) -+{ -+ struct crypto_aead *aead = crypto_aead_reqtfm(req); -+ int ivsize = crypto_aead_ivsize(aead); -+ -+ caam_unmap(dev, req->src, edesc->dst, edesc->src_nents, -+ edesc->dst_nents, edesc->iv_dma, ivsize, DMA_TO_DEVICE, -+ edesc->qm_sg_dma, edesc->qm_sg_bytes); -+} -+ - static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, - struct skcipher_request *req) - { -@@ -1190,6 +1385,238 @@ static int aead_decrypt(struct aead_request *req) - return aead_crypt(req, false); - } - -+static void tls_done(struct caam_drv_req *drv_req, u32 status) -+{ -+ struct device *qidev; -+ struct tls_edesc *edesc; -+ struct aead_request *aead_req = drv_req->app_ctx; -+ struct crypto_aead *aead = crypto_aead_reqtfm(aead_req); -+ struct caam_ctx *caam_ctx = crypto_aead_ctx(aead); -+ int ecode = 0; -+ -+ qidev = caam_ctx->qidev; -+ -+ if (unlikely(status)) -+ ecode = caam_jr_strstatus(qidev, status); -+ -+ edesc = container_of(drv_req, typeof(*edesc), drv_req); -+ tls_unmap(qidev, edesc, aead_req); -+ -+ aead_request_complete(aead_req, ecode); -+ qi_cache_free(edesc); -+} -+ -+/* -+ * allocate and map the tls extended descriptor -+ */ -+static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, bool encrypt) -+{ -+ struct crypto_aead *aead = crypto_aead_reqtfm(req); -+ struct caam_ctx *ctx = crypto_aead_ctx(aead); -+ unsigned int blocksize = crypto_aead_blocksize(aead); -+ unsigned int padsize, authsize; -+ struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead), -+ typeof(*alg), aead); -+ struct device *qidev = ctx->qidev; -+ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? -+ GFP_KERNEL : GFP_ATOMIC; -+ int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; -+ struct tls_edesc *edesc; -+ dma_addr_t qm_sg_dma, iv_dma = 0; -+ int ivsize = crypto_aead_ivsize(aead); -+ u8 *iv; -+ int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes; -+ int src_len, dst_len, data_len; -+ struct qm_sg_entry *sg_table, *fd_sgt; -+ struct caam_drv_ctx *drv_ctx; -+ struct scatterlist *dst; -+ -+ if (encrypt) { -+ padsize = blocksize - ((req->cryptlen + ctx->authsize) % -+ blocksize); -+ authsize = ctx->authsize + padsize; -+ } else { -+ authsize = ctx->authsize; -+ } -+ -+ drv_ctx = get_drv_ctx(ctx, encrypt ? ENCRYPT : DECRYPT); -+ if (unlikely(IS_ERR_OR_NULL(drv_ctx))) -+ return (struct tls_edesc *)drv_ctx; -+ -+ /* allocate space for base edesc, link tables and IV */ -+ edesc = qi_cache_alloc(GFP_DMA | flags); -+ if (unlikely(!edesc)) { -+ dev_err(qidev, "could not allocate extended descriptor\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ data_len = req->assoclen + req->cryptlen; -+ dst_len = req->cryptlen + (encrypt ? authsize : 0); -+ -+ if (likely(req->src == req->dst)) { -+ src_len = req->assoclen + dst_len; -+ -+ src_nents = sg_nents_for_len(req->src, src_len); -+ if (unlikely(src_nents < 0)) { -+ dev_err(qidev, "Insufficient bytes (%d) in src S/G\n", -+ src_len); -+ qi_cache_free(edesc); -+ return ERR_PTR(src_nents); -+ } -+ -+ mapped_src_nents = dma_map_sg(qidev, req->src, src_nents, -+ DMA_BIDIRECTIONAL); -+ if (unlikely(!mapped_src_nents)) { -+ dev_err(qidev, "unable to map source\n"); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ dst = req->dst; -+ } else { -+ src_len = data_len; -+ -+ src_nents = sg_nents_for_len(req->src, src_len); -+ if (unlikely(src_nents < 0)) { -+ dev_err(qidev, "Insufficient bytes (%d) in src S/G\n", -+ src_len); -+ qi_cache_free(edesc); -+ return ERR_PTR(src_nents); -+ } -+ -+ dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen); -+ -+ dst_nents = sg_nents_for_len(dst, dst_len); -+ if (unlikely(dst_nents < 0)) { -+ dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n", -+ dst_len); -+ qi_cache_free(edesc); -+ return ERR_PTR(dst_nents); -+ } -+ -+ if (src_nents) { -+ mapped_src_nents = dma_map_sg(qidev, req->src, -+ src_nents, DMA_TO_DEVICE); -+ if (unlikely(!mapped_src_nents)) { -+ dev_err(qidev, "unable to map source\n"); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ } else { -+ mapped_src_nents = 0; -+ } -+ -+ mapped_dst_nents = dma_map_sg(qidev, dst, dst_nents, -+ DMA_FROM_DEVICE); -+ if (unlikely(!mapped_dst_nents)) { -+ dev_err(qidev, "unable to map destination\n"); -+ dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ } -+ -+ /* -+ * Create S/G table: IV, src, dst. -+ * Input is not contiguous. -+ */ -+ qm_sg_ents = 1 + mapped_src_nents + -+ (mapped_dst_nents > 1 ? mapped_dst_nents : 0); -+ sg_table = &edesc->sgt[0]; -+ qm_sg_bytes = qm_sg_ents * sizeof(*sg_table); -+ -+ iv = (u8 *)(sg_table + qm_sg_ents); -+ /* Make sure IV is located in a DMAable area */ -+ memcpy(iv, req->iv, ivsize); -+ iv_dma = dma_map_single(qidev, iv, ivsize, DMA_TO_DEVICE); -+ if (dma_mapping_error(qidev, iv_dma)) { -+ dev_err(qidev, "unable to map IV\n"); -+ caam_unmap(qidev, req->src, dst, src_nents, dst_nents, 0, 0, -+ DMA_NONE, 0, 0); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ edesc->src_nents = src_nents; -+ edesc->dst_nents = dst_nents; -+ edesc->dst = dst; -+ edesc->iv_dma = iv_dma; -+ edesc->drv_req.app_ctx = req; -+ edesc->drv_req.cbk = tls_done; -+ edesc->drv_req.drv_ctx = drv_ctx; -+ -+ dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0); -+ qm_sg_index = 1; -+ -+ sg_to_qm_sg_last(req->src, src_len, sg_table + qm_sg_index, 0); -+ qm_sg_index += mapped_src_nents; -+ -+ if (mapped_dst_nents > 1) -+ sg_to_qm_sg_last(dst, dst_len, sg_table + qm_sg_index, 0); -+ -+ qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE); -+ if (dma_mapping_error(qidev, qm_sg_dma)) { -+ dev_err(qidev, "unable to map S/G table\n"); -+ caam_unmap(qidev, req->src, dst, src_nents, dst_nents, iv_dma, -+ ivsize, DMA_TO_DEVICE, 0, 0); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ edesc->qm_sg_dma = qm_sg_dma; -+ edesc->qm_sg_bytes = qm_sg_bytes; -+ -+ fd_sgt = &edesc->drv_req.fd_sgt[0]; -+ -+ dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, ivsize + data_len, 0); -+ -+ if (req->dst == req->src) -+ dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + -+ (sg_nents_for_len(req->src, req->assoclen) + -+ 1) * sizeof(*sg_table), dst_len, 0); -+ else if (mapped_dst_nents == 1) -+ dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(dst), dst_len, 0); -+ else -+ dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) * -+ qm_sg_index, dst_len, 0); -+ -+ return edesc; -+} -+ -+static int tls_crypt(struct aead_request *req, bool encrypt) -+{ -+ struct tls_edesc *edesc; -+ struct crypto_aead *aead = crypto_aead_reqtfm(req); -+ struct caam_ctx *ctx = crypto_aead_ctx(aead); -+ int ret; -+ -+ if (unlikely(caam_congested)) -+ return -EAGAIN; -+ -+ edesc = tls_edesc_alloc(req, encrypt); -+ if (IS_ERR_OR_NULL(edesc)) -+ return PTR_ERR(edesc); -+ -+ ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req); -+ if (!ret) { -+ ret = -EINPROGRESS; -+ } else { -+ tls_unmap(ctx->qidev, edesc, req); -+ qi_cache_free(edesc); -+ } -+ -+ return ret; -+} -+ -+static int tls_encrypt(struct aead_request *req) -+{ -+ return tls_crypt(req, true); -+} -+ -+static int tls_decrypt(struct aead_request *req) -+{ -+ return tls_crypt(req, false); -+} -+ - static int ipsec_gcm_encrypt(struct aead_request *req) - { - return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_crypt(req, -@@ -2440,6 +2867,26 @@ static struct caam_aead_alg driver_aeads[] = { - .geniv = true, - } - }, -+ { -+ .aead = { -+ .base = { -+ .cra_name = "tls10(hmac(sha1),cbc(aes))", -+ .cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi", -+ .cra_blocksize = AES_BLOCK_SIZE, -+ }, -+ .setkey = tls_setkey, -+ .setauthsize = tls_setauthsize, -+ .encrypt = tls_encrypt, -+ .decrypt = tls_decrypt, -+ .ivsize = AES_BLOCK_SIZE, -+ .maxauthsize = SHA1_DIGEST_SIZE, -+ }, -+ .caam = { -+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, -+ .class2_alg_type = OP_ALG_ALGSEL_SHA1 | -+ OP_ALG_AAI_HMAC_PRECOMP, -+ } -+ } - }; - - static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, -@@ -2447,6 +2894,16 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, - { - struct caam_drv_private *priv; - struct device *dev; -+ /* Digest sizes for MD5, SHA1, SHA-224, SHA-256, SHA-384, SHA-512 */ -+ static const u8 digest_size[] = { -+ MD5_DIGEST_SIZE, -+ SHA1_DIGEST_SIZE, -+ SHA224_DIGEST_SIZE, -+ SHA256_DIGEST_SIZE, -+ SHA384_DIGEST_SIZE, -+ SHA512_DIGEST_SIZE -+ }; -+ u8 op_id; - - /* - * distribute tfms across job rings to ensure in-order -@@ -2478,6 +2935,21 @@ static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, - ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type; - - ctx->qidev = dev; -+ if (ctx->adata.algtype) { -+ op_id = (ctx->adata.algtype & OP_ALG_ALGSEL_SUBMASK) -+ >> OP_ALG_ALGSEL_SHIFT; -+ if (op_id < ARRAY_SIZE(digest_size)) { -+ ctx->authsize = digest_size[op_id]; -+ } else { -+ dev_err(ctx->jrdev, -+ "incorrect op_id %d; must be less than %zu\n", -+ op_id, ARRAY_SIZE(digest_size)); -+ caam_jr_free(ctx->jrdev); -+ return -EINVAL; -+ } -+ } else { -+ ctx->authsize = 0; -+ } - - spin_lock_init(&ctx->lock); - ctx->drv_ctx[ENCRYPT] = NULL; -diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c -index a780e6278..4592b634a 100644 ---- a/drivers/crypto/caam/caamalg_qi2.c -+++ b/drivers/crypto/caam/caamalg_qi2.c -@@ -582,6 +582,254 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, - return edesc; - } - -+static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, -+ bool encrypt) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ unsigned int blocksize = crypto_aead_blocksize(tls); -+ unsigned int padsize, authsize; -+ struct caam_request *req_ctx = aead_request_ctx(req); -+ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; -+ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ struct caam_aead_alg *alg = container_of(crypto_aead_alg(tls), -+ typeof(*alg), aead); -+ struct device *dev = ctx->dev; -+ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? -+ GFP_KERNEL : GFP_ATOMIC; -+ int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; -+ struct tls_edesc *edesc; -+ dma_addr_t qm_sg_dma, iv_dma = 0; -+ int ivsize = crypto_aead_ivsize(tls); -+ u8 *iv; -+ int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes; -+ int src_len, dst_len, data_len; -+ struct dpaa2_sg_entry *sg_table; -+ struct scatterlist *dst; -+ -+ if (encrypt) { -+ padsize = blocksize - ((req->cryptlen + ctx->authsize) % -+ blocksize); -+ authsize = ctx->authsize + padsize; -+ } else { -+ authsize = ctx->authsize; -+ } -+ -+ /* allocate space for base edesc, link tables and IV */ -+ edesc = qi_cache_zalloc(GFP_DMA | flags); -+ if (unlikely(!edesc)) { -+ dev_err(dev, "could not allocate extended descriptor\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ data_len = req->assoclen + req->cryptlen; -+ dst_len = req->cryptlen + (encrypt ? authsize : 0); -+ -+ if (likely(req->src == req->dst)) { -+ src_len = req->assoclen + dst_len; -+ -+ src_nents = sg_nents_for_len(req->src, src_len); -+ if (unlikely(src_nents < 0)) { -+ dev_err(dev, "Insufficient bytes (%d) in src S/G\n", -+ src_len); -+ qi_cache_free(edesc); -+ return ERR_PTR(src_nents); -+ } -+ -+ mapped_src_nents = dma_map_sg(dev, req->src, src_nents, -+ DMA_BIDIRECTIONAL); -+ if (unlikely(!mapped_src_nents)) { -+ dev_err(dev, "unable to map source\n"); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ dst = req->dst; -+ } else { -+ src_len = data_len; -+ -+ src_nents = sg_nents_for_len(req->src, src_len); -+ if (unlikely(src_nents < 0)) { -+ dev_err(dev, "Insufficient bytes (%d) in src S/G\n", -+ src_len); -+ qi_cache_free(edesc); -+ return ERR_PTR(src_nents); -+ } -+ -+ dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen); -+ -+ dst_nents = sg_nents_for_len(dst, dst_len); -+ if (unlikely(dst_nents < 0)) { -+ dev_err(dev, "Insufficient bytes (%d) in dst S/G\n", -+ dst_len); -+ qi_cache_free(edesc); -+ return ERR_PTR(dst_nents); -+ } -+ -+ if (src_nents) { -+ mapped_src_nents = dma_map_sg(dev, req->src, -+ src_nents, DMA_TO_DEVICE); -+ if (unlikely(!mapped_src_nents)) { -+ dev_err(dev, "unable to map source\n"); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ } else { -+ mapped_src_nents = 0; -+ } -+ -+ mapped_dst_nents = dma_map_sg(dev, dst, dst_nents, -+ DMA_FROM_DEVICE); -+ if (unlikely(!mapped_dst_nents)) { -+ dev_err(dev, "unable to map destination\n"); -+ dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ } -+ -+ /* -+ * Create S/G table: IV, src, dst. -+ * Input is not contiguous. -+ */ -+ qm_sg_ents = 1 + mapped_src_nents + -+ (mapped_dst_nents > 1 ? mapped_dst_nents : 0); -+ sg_table = &edesc->sgt[0]; -+ qm_sg_bytes = qm_sg_ents * sizeof(*sg_table); -+ -+ iv = (u8 *)(sg_table + qm_sg_ents); -+ /* Make sure IV is located in a DMAable area */ -+ memcpy(iv, req->iv, ivsize); -+ iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, iv_dma)) { -+ dev_err(dev, "unable to map IV\n"); -+ caam_unmap(dev, req->src, dst, src_nents, dst_nents, 0, 0, -+ DMA_NONE, 0, 0); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ edesc->src_nents = src_nents; -+ edesc->dst_nents = dst_nents; -+ edesc->dst = dst; -+ edesc->iv_dma = iv_dma; -+ -+ dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0); -+ qm_sg_index = 1; -+ -+ sg_to_qm_sg_last(req->src, src_len, sg_table + qm_sg_index, 0); -+ qm_sg_index += mapped_src_nents; -+ -+ if (mapped_dst_nents > 1) -+ sg_to_qm_sg_last(dst, dst_len, sg_table + qm_sg_index, 0); -+ -+ qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, qm_sg_dma)) { -+ dev_err(dev, "unable to map S/G table\n"); -+ caam_unmap(dev, req->src, dst, src_nents, dst_nents, iv_dma, -+ ivsize, DMA_TO_DEVICE, 0, 0); -+ qi_cache_free(edesc); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ edesc->qm_sg_dma = qm_sg_dma; -+ edesc->qm_sg_bytes = qm_sg_bytes; -+ -+ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); -+ dpaa2_fl_set_final(in_fle, true); -+ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); -+ dpaa2_fl_set_addr(in_fle, qm_sg_dma); -+ dpaa2_fl_set_len(in_fle, ivsize + data_len); -+ -+ if (req->dst == req->src) { -+ dpaa2_fl_set_format(out_fle, dpaa2_fl_sg); -+ dpaa2_fl_set_addr(out_fle, qm_sg_dma + -+ (sg_nents_for_len(req->src, req->assoclen) + -+ 1) * sizeof(*sg_table)); -+ } else if (mapped_dst_nents == 1) { -+ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); -+ dpaa2_fl_set_addr(out_fle, sg_dma_address(dst)); -+ } else { -+ dpaa2_fl_set_format(out_fle, dpaa2_fl_sg); -+ dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index * -+ sizeof(*sg_table)); -+ } -+ -+ dpaa2_fl_set_len(out_fle, dst_len); -+ -+ return edesc; -+} -+ -+static int tls_set_sh_desc(struct crypto_aead *tls) -+{ -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ unsigned int ivsize = crypto_aead_ivsize(tls); -+ unsigned int blocksize = crypto_aead_blocksize(tls); -+ struct device *dev = ctx->dev; -+ struct dpaa2_caam_priv *priv = dev_get_drvdata(dev); -+ struct caam_flc *flc; -+ u32 *desc; -+ unsigned int assoclen = 13; /* always 13 bytes for TLS */ -+ unsigned int data_len[2]; -+ u32 inl_mask; -+ -+ if (!ctx->cdata.keylen || !ctx->authsize) -+ return 0; -+ -+ /* -+ * TLS 1.0 encrypt shared descriptor -+ * Job Descriptor and Shared Descriptor -+ * must fit into the 64-word Descriptor h/w Buffer -+ */ -+ data_len[0] = ctx->adata.keylen_pad; -+ data_len[1] = ctx->cdata.keylen; -+ -+ if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len, -+ &inl_mask, ARRAY_SIZE(data_len)) < 0) -+ return -EINVAL; -+ -+ if (inl_mask & 1) -+ ctx->adata.key_virt = ctx->key; -+ else -+ ctx->adata.key_dma = ctx->key_dma; -+ -+ if (inl_mask & 2) -+ ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; -+ else -+ ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; -+ -+ ctx->adata.key_inline = !!(inl_mask & 1); -+ ctx->cdata.key_inline = !!(inl_mask & 2); -+ -+ flc = &ctx->flc[ENCRYPT]; -+ desc = flc->sh_desc; -+ cnstr_shdsc_tls_encap(desc, &ctx->cdata, &ctx->adata, -+ assoclen, ivsize, ctx->authsize, blocksize, -+ priv->sec_attr.era); -+ flc->flc[1] = cpu_to_caam32(desc_len(desc)); -+ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], -+ sizeof(flc->flc) + desc_bytes(desc), -+ ctx->dir); -+ -+ /* -+ * TLS 1.0 decrypt shared descriptor -+ * Keys do not fit inline, regardless of algorithms used -+ */ -+ ctx->adata.key_inline = false; -+ ctx->adata.key_dma = ctx->key_dma; -+ ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; -+ -+ flc = &ctx->flc[DECRYPT]; -+ desc = flc->sh_desc; -+ cnstr_shdsc_tls_decap(desc, &ctx->cdata, &ctx->adata, assoclen, ivsize, -+ ctx->authsize, blocksize, priv->sec_attr.era); -+ flc->flc[1] = cpu_to_caam32(desc_len(desc)); -+ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], -+ sizeof(flc->flc) + desc_bytes(desc), -+ ctx->dir); -+ -+ return 0; -+} -+ - static int chachapoly_set_sh_desc(struct crypto_aead *aead) - { - struct caam_ctx *ctx = crypto_aead_ctx(aead); -@@ -626,6 +874,60 @@ static int chachapoly_setauthsize(struct crypto_aead *aead, - return chachapoly_set_sh_desc(aead); - } - -+static int tls_setkey(struct crypto_aead *tls, const u8 *key, -+ unsigned int keylen) -+{ -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ struct device *dev = ctx->dev; -+ struct crypto_authenc_keys keys; -+ -+ if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) -+ goto badkey; -+ -+#ifdef DEBUG -+ dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n", -+ keys.authkeylen + keys.enckeylen, keys.enckeylen, -+ keys.authkeylen); -+ print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); -+#endif -+ -+ ctx->adata.keylen = keys.authkeylen; -+ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & -+ OP_ALG_ALGSEL_MASK); -+ -+ if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) -+ goto badkey; -+ -+ memcpy(ctx->key, keys.authkey, keys.authkeylen); -+ memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); -+ dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad + -+ keys.enckeylen, ctx->dir); -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, -+ ctx->adata.keylen_pad + keys.enckeylen, 1); -+#endif -+ -+ ctx->cdata.keylen = keys.enckeylen; -+ -+ memzero_explicit(&keys, sizeof(keys)); -+ return tls_set_sh_desc(tls); -+badkey: -+ memzero_explicit(&keys, sizeof(keys)); -+ return -EINVAL; -+} -+ -+static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize) -+{ -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ -+ ctx->authsize = authsize; -+ tls_set_sh_desc(tls); -+ -+ return 0; -+} -+ - static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key, - unsigned int keylen) - { -@@ -1264,6 +1566,17 @@ static void aead_unmap(struct device *dev, struct aead_edesc *edesc, - dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE); - } - -+static void tls_unmap(struct device *dev, struct tls_edesc *edesc, -+ struct aead_request *req) -+{ -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ int ivsize = crypto_aead_ivsize(tls); -+ -+ caam_unmap(dev, req->src, edesc->dst, edesc->src_nents, -+ edesc->dst_nents, edesc->iv_dma, ivsize, DMA_TO_DEVICE, -+ edesc->qm_sg_dma, edesc->qm_sg_bytes); -+} -+ - static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, - struct skcipher_request *req) - { -@@ -1275,7 +1588,7 @@ static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, - edesc->qm_sg_bytes); - } - --static void aead_encrypt_done(void *cbk_ctx, u32 status) -+static void aead_crypt_done(void *cbk_ctx, u32 status) - { - struct crypto_async_request *areq = cbk_ctx; - struct aead_request *req = container_of(areq, struct aead_request, -@@ -1296,28 +1609,7 @@ static void aead_encrypt_done(void *cbk_ctx, u32 status) - aead_request_complete(req, ecode); - } - --static void aead_decrypt_done(void *cbk_ctx, u32 status) --{ -- struct crypto_async_request *areq = cbk_ctx; -- struct aead_request *req = container_of(areq, struct aead_request, -- base); -- struct caam_request *req_ctx = to_caam_req(areq); -- struct aead_edesc *edesc = req_ctx->edesc; -- struct crypto_aead *aead = crypto_aead_reqtfm(req); -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- int ecode = 0; -- -- dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); -- -- if (unlikely(status)) -- ecode = caam_qi2_strstatus(ctx->dev, status); -- -- aead_unmap(ctx->dev, edesc, req); -- qi_cache_free(edesc); -- aead_request_complete(req, ecode); --} -- --static int aead_encrypt(struct aead_request *req) -+static int aead_crypt(struct aead_request *req, enum optype op) - { - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); -@@ -1326,13 +1618,13 @@ static int aead_encrypt(struct aead_request *req) - int ret; - - /* allocate extended descriptor */ -- edesc = aead_edesc_alloc(req, true); -+ edesc = aead_edesc_alloc(req, op == ENCRYPT); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - -- caam_req->flc = &ctx->flc[ENCRYPT]; -- caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; -- caam_req->cbk = aead_encrypt_done; -+ caam_req->flc = &ctx->flc[op]; -+ caam_req->flc_dma = ctx->flc_dma[op]; -+ caam_req->cbk = aead_crypt_done; - caam_req->ctx = &req->base; - caam_req->edesc = edesc; - ret = dpaa2_caam_enqueue(ctx->dev, caam_req); -@@ -1345,83 +1637,88 @@ static int aead_encrypt(struct aead_request *req) - return ret; - } - -+static int aead_encrypt(struct aead_request *req) -+{ -+ return aead_crypt(req, ENCRYPT); -+} -+ - static int aead_decrypt(struct aead_request *req) - { -- struct aead_edesc *edesc; -- struct crypto_aead *aead = crypto_aead_reqtfm(req); -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -+ return aead_crypt(req, DECRYPT); -+} -+ -+static void tls_crypt_done(void *cbk_ctx, u32 status) -+{ -+ struct crypto_async_request *areq = cbk_ctx; -+ struct aead_request *req = container_of(areq, struct aead_request, -+ base); -+ struct caam_request *req_ctx = to_caam_req(areq); -+ struct tls_edesc *edesc = req_ctx->edesc; -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); -+ int ecode = 0; -+ -+#ifdef DEBUG -+ dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); -+#endif -+ -+ if (unlikely(status)) -+ ecode = caam_qi2_strstatus(ctx->dev, status); -+ -+ tls_unmap(ctx->dev, edesc, req); -+ qi_cache_free(edesc); -+ aead_request_complete(req, ecode); -+} -+ -+static int tls_crypt(struct aead_request *req, enum optype op) -+{ -+ struct tls_edesc *edesc; -+ struct crypto_aead *tls = crypto_aead_reqtfm(req); -+ struct caam_ctx *ctx = crypto_aead_ctx(tls); - struct caam_request *caam_req = aead_request_ctx(req); - int ret; - - /* allocate extended descriptor */ -- edesc = aead_edesc_alloc(req, false); -+ edesc = tls_edesc_alloc(req, op == ENCRYPT); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - -- caam_req->flc = &ctx->flc[DECRYPT]; -- caam_req->flc_dma = ctx->flc_dma[DECRYPT]; -- caam_req->cbk = aead_decrypt_done; -+ caam_req->flc = &ctx->flc[op]; -+ caam_req->flc_dma = ctx->flc_dma[op]; -+ caam_req->cbk = tls_crypt_done; - caam_req->ctx = &req->base; - caam_req->edesc = edesc; - ret = dpaa2_caam_enqueue(ctx->dev, caam_req); - if (ret != -EINPROGRESS && - !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { -- aead_unmap(ctx->dev, edesc, req); -+ tls_unmap(ctx->dev, edesc, req); - qi_cache_free(edesc); - } - - return ret; - } - --static int ipsec_gcm_encrypt(struct aead_request *req) -+static int tls_encrypt(struct aead_request *req) - { -- return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_encrypt(req); -+ return tls_crypt(req, ENCRYPT); - } - --static int ipsec_gcm_decrypt(struct aead_request *req) -+static int tls_decrypt(struct aead_request *req) - { -- return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_decrypt(req); -+ return tls_crypt(req, DECRYPT); - } - --static void skcipher_encrypt_done(void *cbk_ctx, u32 status) -+static int ipsec_gcm_encrypt(struct aead_request *req) - { -- struct crypto_async_request *areq = cbk_ctx; -- struct skcipher_request *req = skcipher_request_cast(areq); -- struct caam_request *req_ctx = to_caam_req(areq); -- struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); -- struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); -- struct skcipher_edesc *edesc = req_ctx->edesc; -- int ecode = 0; -- int ivsize = crypto_skcipher_ivsize(skcipher); -- -- dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); -- -- if (unlikely(status)) -- ecode = caam_qi2_strstatus(ctx->dev, status); -- -- print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, req->iv, -- edesc->src_nents > 1 ? 100 : ivsize, 1); -- caam_dump_sg("dst @" __stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, req->dst, -- edesc->dst_nents > 1 ? 100 : req->cryptlen, 1); -- -- skcipher_unmap(ctx->dev, edesc, req); -- -- /* -- * The crypto API expects us to set the IV (req->iv) to the last -- * ciphertext block (CBC mode) or last counter (CTR mode). -- * This is used e.g. by the CTS mode. -- */ -- if (!ecode) -- memcpy(req->iv, (u8 *)&edesc->sgt[0] + edesc->qm_sg_bytes, -- ivsize); -+ return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_encrypt(req); -+} - -- qi_cache_free(edesc); -- skcipher_request_complete(req, ecode); -+static int ipsec_gcm_decrypt(struct aead_request *req) -+{ -+ return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_decrypt(req); - } - --static void skcipher_decrypt_done(void *cbk_ctx, u32 status) -+static void skcipher_crypt_done(void *cbk_ctx, u32 status) - { - struct crypto_async_request *areq = cbk_ctx; - struct skcipher_request *req = skcipher_request_cast(areq); -@@ -1467,7 +1764,7 @@ static inline bool xts_skcipher_ivsize(struct skcipher_request *req) - return !!get_unaligned((u64 *)(req->iv + (ivsize / 2))); - } - --static int skcipher_encrypt(struct skcipher_request *req) -+static int skcipher_crypt(struct skcipher_request *req, enum optype op) - { - struct skcipher_edesc *edesc; - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); -@@ -1494,7 +1791,9 @@ static int skcipher_encrypt(struct skcipher_request *req) - skcipher_request_set_crypt(&caam_req->fallback_req, req->src, - req->dst, req->cryptlen, req->iv); - -- return crypto_skcipher_encrypt(&caam_req->fallback_req); -+ return (op == ENCRYPT) ? -+ crypto_skcipher_encrypt(&caam_req->fallback_req) : -+ crypto_skcipher_decrypt(&caam_req->fallback_req); - } - - /* allocate extended descriptor */ -@@ -1502,9 +1801,9 @@ static int skcipher_encrypt(struct skcipher_request *req) - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - -- caam_req->flc = &ctx->flc[ENCRYPT]; -- caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; -- caam_req->cbk = skcipher_encrypt_done; -+ caam_req->flc = &ctx->flc[op]; -+ caam_req->flc_dma = ctx->flc_dma[op]; -+ caam_req->cbk = skcipher_crypt_done; - caam_req->ctx = &req->base; - caam_req->edesc = edesc; - ret = dpaa2_caam_enqueue(ctx->dev, caam_req); -@@ -1517,54 +1816,14 @@ static int skcipher_encrypt(struct skcipher_request *req) - return ret; - } - --static int skcipher_decrypt(struct skcipher_request *req) -+static int skcipher_encrypt(struct skcipher_request *req) - { -- struct skcipher_edesc *edesc; -- struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); -- struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); -- struct caam_request *caam_req = skcipher_request_ctx(req); -- struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev); -- int ret; -- -- /* -- * XTS is expected to return an error even for input length = 0 -- * Note that the case input length < block size will be caught during -- * HW offloading and return an error. -- */ -- if (!req->cryptlen && !ctx->fallback) -- return 0; -- -- if (ctx->fallback && ((priv->sec_attr.era <= 8 && xts_skcipher_ivsize(req)) || -- ctx->xts_key_fallback)) { -- skcipher_request_set_tfm(&caam_req->fallback_req, ctx->fallback); -- skcipher_request_set_callback(&caam_req->fallback_req, -- req->base.flags, -- req->base.complete, -- req->base.data); -- skcipher_request_set_crypt(&caam_req->fallback_req, req->src, -- req->dst, req->cryptlen, req->iv); -- -- return crypto_skcipher_decrypt(&caam_req->fallback_req); -- } -- -- /* allocate extended descriptor */ -- edesc = skcipher_edesc_alloc(req); -- if (IS_ERR(edesc)) -- return PTR_ERR(edesc); -- -- caam_req->flc = &ctx->flc[DECRYPT]; -- caam_req->flc_dma = ctx->flc_dma[DECRYPT]; -- caam_req->cbk = skcipher_decrypt_done; -- caam_req->ctx = &req->base; -- caam_req->edesc = edesc; -- ret = dpaa2_caam_enqueue(ctx->dev, caam_req); -- if (ret != -EINPROGRESS && -- !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { -- skcipher_unmap(ctx->dev, edesc, req); -- qi_cache_free(edesc); -- } -+ return skcipher_crypt(req, ENCRYPT); -+} - -- return ret; -+static int skcipher_decrypt(struct skcipher_request *req) -+{ -+ return skcipher_crypt(req, DECRYPT); - } - - static int caam_cra_init(struct caam_ctx *ctx, struct caam_alg_entry *caam, -@@ -2997,6 +3256,26 @@ static struct caam_aead_alg driver_aeads[] = { - .geniv = true, - }, - }, -+ { -+ .aead = { -+ .base = { -+ .cra_name = "tls10(hmac(sha1),cbc(aes))", -+ .cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi2", -+ .cra_blocksize = AES_BLOCK_SIZE, -+ }, -+ .setkey = tls_setkey, -+ .setauthsize = tls_setauthsize, -+ .encrypt = tls_encrypt, -+ .decrypt = tls_decrypt, -+ .ivsize = AES_BLOCK_SIZE, -+ .maxauthsize = SHA1_DIGEST_SIZE, -+ }, -+ .caam = { -+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, -+ .class2_alg_type = OP_ALG_ALGSEL_SHA1 | -+ OP_ALG_AAI_HMAC_PRECOMP, -+ }, -+ }, - }; - - static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg) -diff --git a/drivers/crypto/caam/caamalg_qi2.h b/drivers/crypto/caam/caamalg_qi2.h -index d35253407..0b610c106 100644 ---- a/drivers/crypto/caam/caamalg_qi2.h -+++ b/drivers/crypto/caam/caamalg_qi2.h -@@ -118,6 +118,28 @@ struct aead_edesc { - struct dpaa2_sg_entry sgt[]; - }; - -+/* -+ * tls_edesc - s/w-extended tls descriptor -+ * @src_nents: number of segments in input scatterlist -+ * @dst_nents: number of segments in output scatterlist -+ * @iv_dma: dma address of iv for checking continuity and link table -+ * @qm_sg_bytes: length of dma mapped h/w link table -+ * @qm_sg_dma: bus physical mapped address of h/w link table -+ * @tmp: array of scatterlists used by 'scatterwalk_ffwd' -+ * @dst: pointer to output scatterlist, usefull for unmapping -+ * @sgt: the h/w link table, followed by IV -+ */ -+struct tls_edesc { -+ int src_nents; -+ int dst_nents; -+ dma_addr_t iv_dma; -+ int qm_sg_bytes; -+ dma_addr_t qm_sg_dma; -+ struct scatterlist tmp[2]; -+ struct scatterlist *dst; -+ struct dpaa2_sg_entry sgt[0]; -+}; -+ - /* - * skcipher_edesc - s/w-extended skcipher descriptor - * @src_nents: number of segments in input scatterlist -diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c -index e8a6d8bc4..ae2ae28e3 100644 ---- a/drivers/crypto/caam/caamhash.c -+++ b/drivers/crypto/caam/caamhash.c -@@ -1946,12 +1946,14 @@ int caam_algapi_hash_init(struct device *ctrldev) - * presence and attributes of MD block. - */ - if (priv->era < 10) { -- md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) & -+ struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; -+ -+ md_vid = (rd_reg32(&perfmon->cha_id_ls) & - CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; -- md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & -+ md_inst = (rd_reg32(&perfmon->cha_num_ls) & - CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; - } else { -- u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha); -+ u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha); - - md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; - md_inst = mdha & CHA_VER_NUM_MASK; -diff --git a/drivers/crypto/caam/caamkeyblob.c b/drivers/crypto/caam/caamkeyblob.c -new file mode 100644 -index 000000000..03821d437 ---- /dev/null -+++ b/drivers/crypto/caam/caamkeyblob.c -@@ -0,0 +1,670 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Black key generation and blob encapsulation/decapsulation for CAAM -+ * -+ * Copyright 2018-2020 NXP -+ */ -+#include "caamkeyblob.h" -+#include "error.h" -+ -+/* Black key generation and blob encap/decap job completion handler */ -+static void caam_key_blob_done(struct device *dev, u32 *desc, u32 err, -+ void *context) -+{ -+ struct jr_job_result *res = context; -+ int ecode = 0; -+ -+ dev_dbg(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err); -+ -+ if (err) -+ ecode = caam_jr_strstatus(dev, err); -+ -+ /* Save the error for post-processing */ -+ res->error = ecode; -+ /* Mark job as complete */ -+ complete(&res->completion); -+} -+ -+/** -+ * map_write_data - Prepare data to be written to CAAM -+ * -+ * @dev : struct device of the job ring to be used -+ * @data : The data to be prepared -+ * @size : The size of data to be prepared -+ * @dma_addr : The retrieve DMA address of the input data -+ * @allocated_data : Pointer to a DMA-able address where the input -+ * data is copied and synchronized -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int map_write_data(struct device *dev, const u8 *data, size_t size, -+ dma_addr_t *dma_addr, u8 **allocated_data) -+{ -+ int ret = 0; -+ -+ /* Allocate memory for data and copy it to DMA zone */ -+ *allocated_data = kmemdup(data, size, GFP_KERNEL | GFP_DMA); -+ if (!*allocated_data) { -+ ret = -ENOMEM; -+ goto exit; -+ } -+ -+ *dma_addr = dma_map_single(dev, *allocated_data, size, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, *dma_addr)) { -+ dev_err(dev, "Unable to map write data\n"); -+ ret = -ENOMEM; -+ goto free_alloc; -+ } -+ -+ goto exit; -+ -+free_alloc: -+ kfree(*allocated_data); -+ -+exit: -+ return ret; -+} -+ -+/** -+ * map_read_data - Prepare data to be read from CAAM -+ * -+ * @dev : struct device of the job ring to be used -+ * @size : The size of data to be prepared -+ * @dma_addr : The retrieve DMA address of the data to be read -+ * @allocated_data : Pointer to a DMA-able address where the data -+ * to be read will be copied and synchronized -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int map_read_data(struct device *dev, size_t size, dma_addr_t *dma_addr, -+ u8 **allocated_data) -+{ -+ int ret = 0; -+ -+ /* Allocate memory for data compatible with DMA */ -+ *allocated_data = kmalloc(size, GFP_KERNEL | GFP_DMA); -+ if (!*allocated_data) { -+ ret = -ENOMEM; -+ goto exit; -+ } -+ -+ *dma_addr = dma_map_single(dev, *allocated_data, size, DMA_FROM_DEVICE); -+ if (dma_mapping_error(dev, *dma_addr)) { -+ dev_err(dev, "Unable to map read data\n"); -+ ret = -ENOMEM; -+ goto free_alloc; -+ } -+ -+ goto exit; -+ -+free_alloc: -+ kfree(*allocated_data); -+ -+exit: -+ return ret; -+} -+ -+/** -+ * read_map_data - Read the data from CAAM -+ * -+ * @dev : struct device of the job ring to be used -+ * @data : The read data from CAAM will be copied here -+ * @dma_addr : The DMA address of the data to be read -+ * @allocated_data : Pointer to a DMA-able address where the data -+ * to be read is -+ * @size : The size of data to be read -+ */ -+static void read_map_data(struct device *dev, u8 *data, dma_addr_t dma_addr, -+ u8 *allocated_data, size_t size) -+{ -+ /* Synchronize the DMA and copy the data */ -+ dma_sync_single_for_cpu(dev, dma_addr, size, DMA_FROM_DEVICE); -+ memcpy(data, allocated_data, size); -+} -+ -+/** -+ * unmap_read_write_data - Unmap the data needed for or from CAAM -+ * -+ * @dev : struct device of the job ring to be used -+ * @dma_addr : The DMA address of the data used for DMA transfer -+ * @allocated_data : The data used for DMA transfer -+ * @size : The size of data -+ * @dir : The DMA_API direction -+ */ -+static void unmap_read_write_data(struct device *dev, dma_addr_t dma_addr, -+ u8 *allocated_data, size_t size, -+ enum dma_data_direction dir) -+{ -+ /* Free the resources and clear the data*/ -+ dma_unmap_single(dev, dma_addr, size, dir); -+ kfree_sensitive(allocated_data); -+} -+ -+/** -+ * get_caam_dma_addr - Get the CAAM DMA address of a physical address. -+ * -+ * @phy_address : The physical address -+ * -+ * Return : The CAAM DMA address -+ */ -+static dma_addr_t get_caam_dma_addr(const void *phy_address) -+{ -+ uintptr_t ptr_conv; -+ dma_addr_t caam_dma_address = 0; -+ -+ /* Check if conversion is possible */ -+ if (sizeof(caam_dma_address) < sizeof(phy_address)) { -+ /* -+ * Check that all bits sets in the phy_address -+ * can be stored in caam_dma_address -+ */ -+ -+ /* Generate a mask of the representable bits */ -+ u64 mask = GENMASK_ULL(sizeof(caam_dma_address) * 8 - 1, 0); -+ -+ /* -+ * Check that the bits not representable of -+ * the physical address are not set -+ */ -+ if ((uintptr_t)phy_address & ~mask) -+ goto exit; -+ } -+ -+ /* Convert address to caam_dma_address */ -+ ptr_conv = (uintptr_t)phy_address; -+ caam_dma_address = (dma_addr_t)ptr_conv; -+ -+exit: -+ return caam_dma_address; -+} -+ -+/** -+ * generate_black_key - Generate a black key from a plaintext or random, -+ * based on the given input: a size for a random black -+ * key, or a plaintext (input key). -+ * -+ * If the memory type is Secure Memory, the key to cover is read -+ * directly by CAAM from Secure Memory without intermediate copy. -+ * The value of the input key (plaintext) must be a physical address -+ * in Secure Memory. -+ * -+ * Notes: -+ * Limited to Class 1 keys, at the present time. -+ * The input and output data are copied to temporary arrays -+ * except for the input key if the memory type is Secure Memory. -+ * For now, we have support for Black keys, stored in General Memory. -+ * -+ * @dev : struct device of the job ring to be used -+ * @info : keyblob_info structure, will be updated with -+ * the black key data from CAAM. -+ * This contains, also, all the data necessary to generate -+ * a black key from plaintext/random like: key encryption -+ * key, memory type, input key, etc. -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+int generate_black_key(struct device *dev, struct keyblob_info *info) -+{ -+ int ret = 0; -+ bool not_random = false; -+ u8 trusted_key, key_enc; -+ u32 *desc = NULL; -+ size_t black_key_length_req = 0; -+ dma_addr_t black_key_dma; -+ u8 *tmp_black_key = NULL; -+ -+ /* Validate device */ -+ if (!dev) -+ return -EINVAL; -+ -+ /* -+ * If an input key (plaintext) is given, -+ * generate a black key from it, not from random -+ */ -+ if (info->key) -+ not_random = true; -+ -+ /* Get trusted key and key encryption type from type */ -+ trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; -+ key_enc = (info->type >> TAG_OBJ_EKT_OFFSET) & 0x1; -+ -+ dev_dbg(dev, "%s input: [key: (%zu) black_key: %p(%zu), key_enc: %x]\n", -+ __func__, info->key_len, info->black_key, info->black_key_len, -+ key_enc); -+ if (not_random) -+ print_hex_dump_debug("input key @" __stringify(__LINE__) ": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, info->key, -+ info->key_len, 1); -+ -+ /* Validate key type - only JDKEK keys are supported */ -+ if (!is_key_type(info->type) || is_trusted_type(info->type)) -+ return -EINVAL; -+ -+ /* -+ * Validate key size, expected values are -+ * between 16 and 64 bytes. -+ * See TODO from cnstr_desc_black_key(). -+ */ -+ if (info->key_len < MIN_KEY_SIZE || info->key_len > MAX_KEY_SIZE) -+ return -EINVAL; -+ -+ /* -+ * Based on key encryption type (ecb or ccm), -+ * compute the black key size -+ */ -+ if (key_enc == KEY_COVER_ECB) -+ /* -+ * ECB-Black Key will be padded with zeros to make it a -+ * multiple of 16 bytes long before it is encrypted, -+ * and the resulting Black Key will be this length. -+ */ -+ black_key_length_req = ECB_BLACK_KEY_SIZE(info->key_len); -+ else if (key_enc == KEY_COVER_CCM) -+ /* -+ * CCM-Black Key will always be at least 12 bytes longer, -+ * since the encapsulation uses a 6-byte nonce and adds -+ * a 6-byte ICV. But first, the key is padded as necessary so -+ * that CCM-Black Key is a multiple of 8 bytes long. -+ */ -+ black_key_length_req = CCM_BLACK_KEY_SIZE(info->key_len); -+ -+ /* Check if there is enough space for black key */ -+ if (info->black_key_len < black_key_length_req) { -+ info->black_key_len = black_key_length_req; -+ return -EINVAL; -+ } -+ -+ /* Black key will have at least the same length as the input key */ -+ info->black_key_len = info->key_len; -+ -+ dev_dbg(dev, "%s processing: [key: (%zu) black_key: %p(%zu)", -+ __func__, info->key_len, info->black_key, info->black_key_len); -+ dev_dbg(dev, "req:%zu, key_enc: 0x%x]\n", black_key_length_req, key_enc); -+ -+ /* Map black key, this will be read from CAAM */ -+ if (map_read_data(dev, black_key_length_req, -+ &black_key_dma, &tmp_black_key)) { -+ dev_err(dev, "Unable to map black key\n"); -+ ret = -ENOMEM; -+ goto exit; -+ } -+ -+ /* Construct descriptor for black key */ -+ if (not_random) -+ ret = cnstr_desc_black_key(&desc, info->key, info->key_len, -+ black_key_dma, info->black_key_len, -+ key_enc, trusted_key); -+ else -+ ret = cnstr_desc_random_black_key(&desc, info->key_len, -+ black_key_dma, -+ info->black_key_len, -+ key_enc, trusted_key); -+ -+ if (ret) { -+ dev_err(dev, -+ "Failed to construct the descriptor for black key\n"); -+ goto unmap_black_key; -+ } -+ -+ /* Execute descriptor and wait for its completion */ -+ ret = caam_jr_run_and_wait_for_completion(dev, desc, -+ caam_key_blob_done); -+ if (ret) { -+ dev_err(dev, "Failed to execute black key descriptor\n"); -+ goto free_desc; -+ } -+ -+ /* Read black key from CAAM */ -+ read_map_data(dev, info->black_key, black_key_dma, -+ tmp_black_key, black_key_length_req); -+ -+ /* Update black key length with the correct size */ -+ info->black_key_len = black_key_length_req; -+ -+free_desc: -+ kfree(desc); -+ -+unmap_black_key: -+ unmap_read_write_data(dev, black_key_dma, tmp_black_key, -+ black_key_length_req, DMA_FROM_DEVICE); -+ -+exit: -+ return ret; -+} -+EXPORT_SYMBOL(generate_black_key); -+ -+/** -+ * caam_blob_encap - Encapsulate a black key into a blob -+ * -+ * If the memory type is Secure Memory, the key to encapsulate is read -+ * directly by CAAM from Secure Memory without intermediate copy. -+ * The value of the key (black key) must be a physical address -+ * in Secure Memory. -+ * -+ * Notes: -+ * For now, we have support for Black keys, stored in General Memory and -+ * encapsulated into black blobs. -+ * -+ * @dev : struct device of the job ring to be used -+ * @info : keyblob_info structure, will be updated with -+ * the blob data from CAAM. -+ * This contains, also, all the data necessary to -+ * encapsulate a black key into a blob: key encryption -+ * key, memory type, color, etc. -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+int caam_blob_encap(struct device *dev, struct keyblob_info *info) -+{ -+ int ret = 0; -+ u32 *desc = NULL; -+ size_t black_key_real_len = 0; -+ size_t blob_req_len = 0; -+ u8 mem_type, color, key_enc, trusted_key; -+ dma_addr_t black_key_dma, blob_dma; -+ unsigned char *blob = info->blob; -+ u8 *tmp_black_key = NULL, *tmp_blob = NULL; -+ -+ /* Validate device */ -+ if (!dev) -+ return -EINVAL; -+ -+ /* -+ * Get memory type, trusted key, key encryption -+ * type and color from type -+ */ -+ mem_type = (info->type >> TAG_OBJ_MEM_OFFSET) & 0x1; -+ color = (info->type >> TAG_OBJ_COLOR_OFFSET) & 0x1; -+ key_enc = (info->type >> TAG_OBJ_EKT_OFFSET) & 0x1; -+ trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; -+ -+ /* Validate input data*/ -+ if (!info->key_mod || !blob) -+ return -EINVAL; -+ -+ /* Validate object type - only JDKEK keys are supported */ -+ if (is_trusted_type(info->type)) -+ return -EINVAL; -+ -+ dev_dbg(dev, "%s input:[black_key: %p (%zu) color: %x, key_enc: %x", -+ __func__, info->black_key, info->black_key_len, color, key_enc); -+ dev_dbg(dev, ", key_mod: %p (%zu)", info->key_mod, info->key_mod_len); -+ dev_dbg(dev, "blob: %p (%zu)]\n", blob, info->blob_len); -+ -+ /* -+ * Based on memory type, the key modifier length -+ * can be 8-byte or 16-byte. -+ */ -+ if (mem_type == DATA_SECMEM) -+ info->key_mod_len = KEYMOD_SIZE_SM; -+ else -+ info->key_mod_len = KEYMOD_SIZE_GM; -+ -+ /* Adapt the size of the black key */ -+ black_key_real_len = info->black_key_len; -+ -+ blob_req_len = CCM_BLACK_KEY_SIZE(info->key_len); -+ -+ /* Check if the blob can be stored */ -+ if (info->blob_len < (blob_req_len + BLOB_OVERHEAD)) -+ return -EINVAL; -+ -+ /* Update the blob length */ -+ info->blob_len = blob_req_len + BLOB_OVERHEAD; -+ -+ dev_dbg(dev, "%s processing: [black_key: %p (%zu) cnstr: %zu", -+ __func__, info->black_key, info->black_key_len, -+ black_key_real_len); -+ dev_dbg(dev, " color: %x key_enc: %x, mem_type: %x,", -+ color, key_enc, mem_type); -+ dev_dbg(dev, ", key_mod: %p (%zu) ", info->key_mod, info->key_mod_len); -+ dev_dbg(dev, "blob: %p (%zu)]\n", blob, info->blob_len); -+ -+ /* Map black key, this will be transferred to CAAM */ -+ if (mem_type == DATA_GENMEM) { -+ if (map_write_data(dev, info->black_key, info->black_key_len, -+ &black_key_dma, &tmp_black_key)) { -+ dev_err(dev, "Unable to map black key for blob\n"); -+ ret = -ENOMEM; -+ goto exit; -+ } -+ } else { -+ black_key_dma = get_caam_dma_addr(info->black_key); -+ if (!black_key_dma) -+ return -ENOMEM; -+ } -+ -+ /* Map blob, this will be read to CAAM */ -+ if (mem_type == DATA_GENMEM) { -+ if (map_read_data(dev, info->blob_len, &blob_dma, &tmp_blob)) { -+ dev_err(dev, "Unable to map blob\n"); -+ ret = -ENOMEM; -+ goto unmap_black_key; -+ } -+ } else { -+ blob_dma = get_caam_dma_addr(info->blob); -+ if (!blob_dma) -+ return -ENOMEM; -+ } -+ -+ /* Construct descriptor for blob encapsulation */ -+ ret = cnstr_desc_blob_encap(&desc, black_key_dma, info->key_len, -+ color, key_enc, trusted_key, mem_type, -+ info->key_mod, info->key_mod_len, -+ blob_dma, info->blob_len); -+ if (ret) { -+ dev_err(dev, -+ "Failed to construct the descriptor for blob encap\n"); -+ goto unmap_blob; -+ } -+ -+ /* Execute descriptor and wait for its completion */ -+ ret = caam_jr_run_and_wait_for_completion(dev, desc, -+ caam_key_blob_done); -+ if (ret) { -+ dev_err(dev, "Failed to execute blob encap descriptor\n"); -+ goto free_desc; -+ } -+ -+ /* Read blob from CAAM */ -+ if (mem_type == DATA_GENMEM) -+ read_map_data(dev, blob, blob_dma, tmp_blob, info->blob_len); -+ -+ print_hex_dump_debug("blob @" __stringify(__LINE__) ": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, blob, -+ info->blob_len, 1); -+free_desc: -+ kfree(desc); -+ -+unmap_blob: -+ if (mem_type == DATA_GENMEM) -+ unmap_read_write_data(dev, blob_dma, tmp_blob, -+ info->blob_len, DMA_FROM_DEVICE); -+ -+unmap_black_key: -+ if (mem_type == DATA_GENMEM) -+ unmap_read_write_data(dev, black_key_dma, tmp_black_key, -+ info->black_key_len, DMA_TO_DEVICE); -+ -+exit: -+ return ret; -+} -+EXPORT_SYMBOL(caam_blob_encap); -+ -+/** -+ * caam_blob_decap - Decapsulate a black key from a blob -+ * -+ * Notes: -+ * For now, we have support for Black blob, stored in General Memory and -+ * can be decapsulated into a black key. -+ * -+ * @dev : struct device of the job ring to be used -+ * @info : keyblob_info structure, will be updated with -+ * the black key decapsulated from the blob. -+ * This contains, also, all the data necessary to -+ * encapsulate a black key into a blob: key encryption -+ * key, memory type, color, etc. -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+int caam_blob_decap(struct device *dev, struct keyblob_info *info) -+{ -+ int ret = 0; -+ u32 *desc = NULL; -+ u8 mem_type, color, key_enc, trusted_key; -+ size_t black_key_real_len; -+ dma_addr_t black_key_dma, blob_dma; -+ unsigned char *blob = info->blob + TAG_OVERHEAD_SIZE; -+ u8 *tmp_black_key = NULL, *tmp_blob = NULL; -+ -+ /* Validate device */ -+ if (!dev) -+ return -EINVAL; -+ -+ /* -+ * Get memory type, trusted key, key encryption -+ * type and color from type -+ */ -+ mem_type = (info->type >> TAG_OBJ_MEM_OFFSET) & 0x1; -+ color = (info->type >> TAG_OBJ_COLOR_OFFSET) & 0x1; -+ key_enc = (info->type >> TAG_OBJ_EKT_OFFSET) & 0x1; -+ trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; -+ -+ /* Validate input data*/ -+ if (!info->key_mod || !blob) -+ return -EINVAL; -+ -+ dev_dbg(dev, "%s input: [blob: %p (%zu), mem_type: %x, color: %x", -+ __func__, blob, info->blob_len, mem_type, color); -+ dev_dbg(dev, " keymod: %p (%zu)", info->key_mod, info->key_mod_len); -+ dev_dbg(dev, " secret: %p (%zu) key_enc: %x]\n", -+ info->black_key, info->black_key_len, key_enc); -+ -+ /* Validate object type - only JDKEK keys are supported */ -+ if (is_trusted_type(info->type)) -+ return -EINVAL; -+ -+ print_hex_dump_debug("blob @" __stringify(__LINE__) ": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, blob, -+ info->blob_len, 1); -+ -+ /* -+ * Based on memory type, the key modifier length -+ * can be 8-byte or 16-byte. -+ */ -+ if (mem_type == DATA_SECMEM) -+ info->key_mod_len = KEYMOD_SIZE_SM; -+ else -+ info->key_mod_len = KEYMOD_SIZE_GM; -+ -+ /* Check if the blob is valid */ -+ if (info->blob_len <= BLOB_OVERHEAD) -+ return -EINVAL; -+ -+ /* Initialize black key length */ -+ black_key_real_len = info->blob_len - BLOB_OVERHEAD; -+ -+ /* Check if the black key has enough space to be stored */ -+ if (info->black_key_len < black_key_real_len) -+ return -EINVAL; -+ -+ /* -+ * Based on key encryption type (ecb or ccm), -+ * compute the black key size -+ */ -+ if (key_enc == KEY_COVER_ECB) -+ /* -+ * ECB-Black Key will be padded with zeros to make it a -+ * multiple of 16 bytes long before it is encrypted, -+ * and the resulting Black Key will be this length. -+ */ -+ black_key_real_len = ECB_BLACK_KEY_SIZE(info->key_len); -+ else if (key_enc == KEY_COVER_CCM) -+ /* -+ * CCM-Black Key will always be at least 12 bytes longer, -+ * since the encapsulation uses a 6-byte nonce and adds -+ * a 6-byte ICV. But first, the key is padded as necessary so -+ * that CCM-Black Key is a multiple of 8 bytes long. -+ */ -+ black_key_real_len = CCM_BLACK_KEY_SIZE(info->key_len); -+ -+ /* Check if there is enough space for black key */ -+ if (info->black_key_len < black_key_real_len) -+ return -EINVAL; -+ -+ /* Update black key length with the one computed based on key_enc */ -+ info->black_key_len = black_key_real_len; -+ -+ dev_dbg(dev, "%s processing: [blob: %p (%zu), mem_type: %x, color: %x,", -+ __func__, blob, info->blob_len, mem_type, color); -+ dev_dbg(dev, " key_mod: %p (%zu), black_key: %p (%zu) real_len: %zu]\n", -+ info->key_mod, info->key_mod_len, info->black_key, -+ info->black_key_len, black_key_real_len); -+ -+ /* Map blob, this will be transferred to CAAM */ -+ if (mem_type == DATA_GENMEM) { -+ if (map_write_data(dev, blob, info->blob_len, -+ &blob_dma, &tmp_blob)) { -+ dev_err(dev, "Unable to map blob for decap\n"); -+ ret = -ENOMEM; -+ goto exit; -+ } -+ } else { -+ blob_dma = get_caam_dma_addr(blob); -+ if (!blob_dma) -+ return -ENOMEM; -+ } -+ -+ /* Map black key, this will be read from CAAM */ -+ if (mem_type == DATA_GENMEM) { -+ if (map_read_data(dev, info->black_key_len, -+ &black_key_dma, &tmp_black_key)) { -+ dev_err(dev, "Unable to map black key for blob decap\n"); -+ ret = -ENOMEM; -+ goto unmap_blob; -+ } -+ } else { -+ black_key_dma = get_caam_dma_addr(info->black_key); -+ if (!black_key_dma) -+ return -ENOMEM; -+ } -+ -+ ret = cnstr_desc_blob_decap(&desc, blob_dma, info->blob_len, -+ info->key_mod, info->key_mod_len, -+ black_key_dma, info->key_len, -+ color, key_enc, trusted_key, mem_type); -+ if (ret) { -+ dev_err(dev, -+ "Failed to construct the descriptor for blob decap\n"); -+ goto unmap_black_key; -+ } -+ -+ ret = caam_jr_run_and_wait_for_completion(dev, desc, -+ caam_key_blob_done); -+ if (ret) { -+ dev_err(dev, "Failed to execute blob decap descriptor\n"); -+ goto free_desc; -+ } -+ -+ /* Read black key from CAAM */ -+ if (mem_type == DATA_GENMEM) -+ read_map_data(dev, info->black_key, black_key_dma, -+ tmp_black_key, info->black_key_len); -+ -+free_desc: -+ kfree(desc); -+ -+unmap_black_key: -+ if (mem_type == DATA_GENMEM) -+ unmap_read_write_data(dev, black_key_dma, tmp_black_key, -+ info->black_key_len, DMA_FROM_DEVICE); -+ -+unmap_blob: -+ if (mem_type == DATA_GENMEM) -+ unmap_read_write_data(dev, blob_dma, tmp_blob, -+ info->blob_len, DMA_TO_DEVICE); -+ -+exit: -+ return ret; -+} -+EXPORT_SYMBOL(caam_blob_decap); -diff --git a/drivers/crypto/caam/caamkeyblob.h b/drivers/crypto/caam/caamkeyblob.h -new file mode 100644 -index 000000000..495b74c29 ---- /dev/null -+++ b/drivers/crypto/caam/caamkeyblob.h -@@ -0,0 +1,82 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * Black key generation and blob encapsulation/decapsualtion for CAAM -+ * -+ * Copyright 2018-2020 NXP -+ */ -+ -+#ifndef _CAAMKEYBLOB_H_ -+#define _CAAMKEYBLOB_H_ -+ -+#include -+#include "caamkeyblob_desc.h" -+ -+/* -+ * Minimum key size to be used is 16 bytes and maximum key size fixed -+ * is 64 bytes. -+ * Blob size to be kept is Maximum key size + tag object header added by CAAM. -+ */ -+ -+#define MIN_KEY_SIZE 16 -+#define MAX_KEY_SIZE 64 -+ -+#define MAX_BLACK_KEY_SIZE (MAX_KEY_SIZE + CCM_OVERHEAD +\ -+ TAG_OVERHEAD_SIZE) -+ -+/* -+ * For blobs a randomly-generated, 256-bit blob key is used to -+ * encrypt the data using the AES-CCM cryptographic algorithm. -+ * Therefore, blob size is max key size, CCM_OVERHEAD, blob header -+ * added by CAAM and the tagged object header size. -+ */ -+#define MAX_BLOB_SIZE (MAX_KEY_SIZE + CCM_OVERHEAD +\ -+ BLOB_OVERHEAD + TAG_OVERHEAD_SIZE) -+ -+/* Key modifier for CAAM blobs, used as a revision number */ -+static const char caam_key_modifier[KEYMOD_SIZE_GM] = { -+ 'C', 'A', 'A', 'M', '_', 'K', 'E', 'Y', -+ '_', 'T', 'Y', 'P', 'E', '_', 'V', '1', -+}; -+ -+/** -+ * struct keyblob_info - Structure that contains all the data necessary -+ * to generate a black key and encapsulate it into a blob -+ * -+ * @key : The plaintext used as input key -+ * for black key generation -+ * @key_len : Size of plaintext or size of key in case of -+ * black key generated from random -+ * @type : The type of data contained (e.g. black key, blob, etc.) -+ * @black_key_len : Length of the generated black key -+ * @black_key : Black key data obtained from CAAM -+ * @blob_len : Length of the blob that encapsulates the black key -+ * @blob : Blob data obtained from CAAM -+ * @key_modifier_len : 8-byte or 16-byte Key_Modifier based on general or -+ * secure memory blob type -+ * @key_modifier : can be either a secret value, or used as a revision -+ * number, revision date or nonce -+ * In this case is used as a revision number. -+ */ -+struct keyblob_info { -+ char *key; -+ size_t key_len; -+ -+ u32 type; -+ -+ size_t black_key_len; -+ unsigned char black_key[MAX_BLACK_KEY_SIZE]; -+ -+ size_t blob_len; -+ unsigned char blob[MAX_BLOB_SIZE]; -+ -+ size_t key_mod_len; -+ const void *key_mod; -+}; -+ -+int generate_black_key(struct device *dev, struct keyblob_info *info); -+ -+int caam_blob_encap(struct device *dev, struct keyblob_info *info); -+ -+int caam_blob_decap(struct device *dev, struct keyblob_info *info); -+ -+#endif /* _CAAMKEYBLOB_H_ */ -diff --git a/drivers/crypto/caam/caamkeyblob_desc.c b/drivers/crypto/caam/caamkeyblob_desc.c -new file mode 100644 -index 000000000..628873167 ---- /dev/null -+++ b/drivers/crypto/caam/caamkeyblob_desc.c -@@ -0,0 +1,446 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Shared descriptors for CAAM black key -+ * and blob encapsulation/decapsulation -+ * -+ * Copyright 2018-2020 NXP -+ */ -+#include "caamkeyblob_desc.h" -+ -+/* Size of tmp buffer for descriptor const. */ -+#define INITIAL_DESCSZ 64 -+ -+/* -+ * Construct a black key conversion job descriptor -+ * -+ * This function constructs a job descriptor capable of performing -+ * a key blackening operation on a plaintext secure memory resident object. -+ * -+ * @desc : Pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * @key : Pointer to the plaintext, which will also hold -+ * the result. Since encryption occurs in place, caller must -+ * ensure that the space is large enough to accommodate the -+ * blackened key -+ * @key_len : Size of the plaintext -+ * @black_key : DMA address of the black key obtained from hardware -+ * @black_key_len : Size of the black key -+ * @key_enc : Encrypted Key Type (AES-ECB or AES-CCM) -+ * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) -+ * or Trusted Descriptor Key Encryption Key (TDKEK) to -+ * decrypt the key to be loaded into a Key Register). -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+int cnstr_desc_black_key(u32 **desc, char *key, size_t key_len, -+ dma_addr_t black_key, size_t black_key_len, -+ u8 key_enc, u8 trusted_key) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize; -+ u32 bk_store; -+ u32 key_length_for_desc = key_len; -+ -+ /* Trusted key not supported */ -+ if (trusted_key != UNTRUSTED_KEY) -+ return -EOPNOTSUPP; -+ -+ memset(tmpdesc, 0, sizeof(tmpdesc)); -+ -+ init_job_desc(tmpdesc, 0); -+ -+ /* -+ * KEY commands seems limited to 32 bytes, so we should use the load -+ * command instead which can load up to 64 bytes. -+ * The size must also be loaded. -+ * -+ * TODO: The KEY command indicate it should be able to load key bigger -+ * than 32bytes but it doesn't work in practice -+ * -+ * TODO: The LOAD command indicate it should be able to load up to 96 -+ * byte keys it doesn't work in practice and is limited to 64 bytes -+ */ -+ -+ /* Load key to class 1 key register */ -+ append_load_as_imm(tmpdesc, (void *)key, key_length_for_desc, -+ LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_KEY); -+ -+ /* Load the size of the key */ -+ append_load_imm_u32(tmpdesc, key_length_for_desc, LDST_CLASS_1_CCB | -+ LDST_IMM | LDST_SRCDST_WORD_KEYSZ_REG); -+ -+ /* ...and write back out via FIFO store*/ -+ bk_store = CLASS_1; -+ if (key_enc == KEY_COVER_ECB) -+ bk_store |= FIFOST_TYPE_KEY_KEK; -+ else -+ bk_store |= FIFOST_TYPE_KEY_CCM_JKEK; -+ -+ /* Save the key as black key in memory */ -+ append_fifo_store(tmpdesc, black_key, black_key_len, bk_store); -+ -+ dsize = desc_bytes(&tmpdesc); -+ -+ /* Now allocate execution buffer and coat it with executable */ -+ tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); -+ if (!tdesc) -+ return -ENOMEM; -+ -+ *desc = tdesc; -+ -+ print_hex_dump_debug("black key desc@" __stringify(__LINE__) ":", -+ DUMP_PREFIX_ADDRESS, 16, 4, *desc, -+ desc_bytes(*desc), 1); -+ -+ return 0; -+} -+EXPORT_SYMBOL(cnstr_desc_black_key); -+ -+/* -+ * Construct a black key using RNG job descriptor -+ * -+ * This function constructs a job descriptor capable of performing -+ * a key blackening operation on RNG generated. -+ * -+ * @desc : Pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * @key_len : Size of the random plaintext -+ * @black_key : DMA address of the black key obtained from hardware -+ * @black_key_len : Size of the black key -+ * @key_enc : Encrypted Key Type (AES-ECB or AES-CCM) -+ * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) -+ * or Trusted Descriptor Key Encryption Key (TDKEK) to -+ * decrypt the key to be loaded into a Key Register). -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+int cnstr_desc_random_black_key(u32 **desc, size_t key_len, -+ dma_addr_t black_key, size_t black_key_len, -+ u8 key_enc, u8 trusted_key) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize; -+ u32 bk_store; -+ -+ memset(tmpdesc, 0, sizeof(tmpdesc)); -+ -+ init_job_desc(tmpdesc, 0); -+ -+ /* Prepare RNG */ -+ append_operation(tmpdesc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); -+ -+ /* Generate RNG and left it in output data fifo */ -+ append_cmd(tmpdesc, CMD_FIFO_STORE | FIFOST_TYPE_RNGFIFO | key_len); -+ -+ /* Copy RNG from outfifo to class 1 Key register */ -+ append_move(tmpdesc, MOVE_SRC_OUTFIFO | MOVE_DEST_CLASS1KEY | -+ MOVE_WAITCOMP | (key_len & MOVE_LEN_MASK)); -+ -+ /* Write the size of the key moved */ -+ append_load_imm_u32(tmpdesc, key_len, LDST_CLASS_1_CCB | -+ LDST_SRCDST_WORD_KEYSZ_REG | LDST_IMM); -+ -+ bk_store = CLASS_1; -+ if (key_enc == KEY_COVER_ECB) -+ bk_store |= FIFOST_TYPE_KEY_KEK; -+ else -+ bk_store |= FIFOST_TYPE_KEY_CCM_JKEK; -+ -+ /* Fifo store to save the key as black key in memory */ -+ append_fifo_store(tmpdesc, black_key, black_key_len, bk_store); -+ -+ dsize = desc_bytes(&tmpdesc); -+ -+ /* Now allocate execution buffer and coat it with executable */ -+ tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); -+ if (!tdesc) -+ return -ENOMEM; -+ -+ *desc = tdesc; -+ -+ print_hex_dump_debug("black key random desc@" __stringify(__LINE__) ":", -+ DUMP_PREFIX_ADDRESS, 16, 4, *desc, -+ desc_bytes(*desc), 1); -+ -+ return 0; -+} -+EXPORT_SYMBOL(cnstr_desc_random_black_key); -+ -+/* -+ * Construct a blob encapsulation job descriptor -+ * -+ * This function dynamically constructs a blob encapsulation job descriptor -+ * from the following arguments: -+ * -+ * @desc : Pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * @black_key : Physical pointer to a secret, normally a black or red key, -+ * possibly residing within an accessible secure memory page, -+ * of the secret to be encapsulated to an output blob. -+ * @black_key_len : Size of input secret, in bytes. This is limited to 65536 -+ * less the size of blob overhead, since the length embeds -+ * into DECO pointer in/out instructions. -+ * @keycolor : Determines if the source data is covered (black key) or -+ * plaintext (red key). RED_KEY or BLACK_KEY are defined in -+ * for this purpose. -+ * @key_enc : If BLACK_KEY source is covered via AES-CCM, specify -+ * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). -+ * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) -+ * or Trusted Descriptor Key Encryption Key (TDKEK) to -+ * decrypt the key to be loaded into a Key Register). -+ * @mem_type : Determine if encapsulated blob should be a secure memory -+ * blob (DATA_SECMEM), with partition data embedded with key -+ * material, or a general memory blob (DATA_GENMEM). -+ * @key_mod : Pointer to a key modifier, which must reside in a -+ * contiguous piece of memory. Modifier will be assumed to be -+ * 8 bytes long for a blob of type DATA_SECMEM, or 16 bytes -+ * long for a blob of type DATA_GENMEM -+ * @key_mod_len : Modifier length is 8 bytes long for a blob of type -+ * DATA_SECMEM, or 16 bytes long for a blob of type DATA_GENMEM -+ * @blob : Physical pointer to the destination buffer to receive the -+ * encapsulated output. This buffer will need to be 48 bytes -+ * larger than the input because of the added encapsulation -+ * data. The generated descriptor will account for the -+ * increase in size, but the caller must also account for -+ * this increase in the buffer allocator. -+ * @blob_len : Size of the destination buffer to receive the -+ * encapsulated output. -+ * Return : '0' on success, error code otherwise -+ * -+ * Upon completion, desc points to a buffer containing a CAAM job -+ * descriptor which encapsulates data into an externally-storable blob -+ * suitable for use across power cycles. -+ * -+ * This is an example of a black key encapsulation job into a general memory -+ * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note -+ * the output 48 bytes longer than the input: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400010 ld: ccb2-key len=16 offs=0 -+ * [02] 08144891 ptr->@0x08144891 -+ * [03] F800003A seqoutptr: len=58 -+ * [04] 01000000 out_ptr->@0x01000000 -+ * [05] F000000A seqinptr: len=10 -+ * [06] 09745090 in_ptr->@0x09745090 -+ * [07] 870D0004 operation: encap blob reg=memory, black, format=normal -+ * -+ * This is an example of a red key encapsulation job for storing a red key -+ * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset -+ * in the LOAD instruction; this accounts for blob permission storage: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400C08 ld: ccb2-key len=8 offs=12 -+ * [02] 087D0784 ptr->@0x087d0784 -+ * [03] F8000050 seqoutptr: len=80 -+ * [04] 09251BB2 out_ptr->@0x09251bb2 -+ * [05] F0000020 seqinptr: len=32 -+ * [06] 40000F31 in_ptr->@0x40000f31 -+ * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, -+ * format=normal -+ */ -+int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, -+ size_t key_len, u8 keycolor, u8 key_enc, -+ u8 trusted_key, u8 mem_type, const void *key_mod, -+ size_t key_mod_len, dma_addr_t blob, size_t blob_len) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize; -+ u32 bk_store; -+ -+ /* Trusted key not supported */ -+ if (trusted_key != UNTRUSTED_KEY) -+ return -EOPNOTSUPP; -+ -+ memset(tmpdesc, 0, sizeof(tmpdesc)); -+ -+ init_job_desc(tmpdesc, 0); -+ -+ /* -+ * Key modifier works differently for secure/general memory blobs -+ * This accounts for the permission/protection data encapsulated -+ * within the blob if a secure memory blob is requested -+ */ -+ if (mem_type == DATA_SECMEM) -+ append_load_as_imm(tmpdesc, key_mod, key_mod_len, -+ LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & -+ LDST_OFFSET_MASK)); -+ else /* is general memory blob */ -+ append_load_as_imm(tmpdesc, key_mod, key_mod_len, -+ LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); -+ -+ /* Input data, should be somewhere in secure memory */ -+ append_seq_in_ptr_intlen(tmpdesc, black_key, key_len, 0); -+ -+ /* -+ * Encapsulation output must include space for blob key encryption -+ * key and MAC tag -+ */ -+ append_seq_out_ptr_intlen(tmpdesc, blob, CCM_BLACK_KEY_SIZE(key_len) + -+ BLOB_OVERHEAD, 0); -+ -+ bk_store = OP_PCLID_BLOB; -+ if (mem_type == DATA_SECMEM) -+ bk_store |= OP_PCL_BLOB_PTXT_SECMEM; -+ -+ if (key_enc == KEY_COVER_CCM) -+ bk_store |= OP_PCL_BLOB_EKT; -+ -+ /* An input black key cannot be stored in a red blob */ -+ if (keycolor == BLACK_KEY) -+ bk_store |= OP_PCL_BLOB_BLACK; -+ -+ /* Set blob encap, then color */ -+ append_operation(tmpdesc, OP_TYPE_ENCAP_PROTOCOL | bk_store); -+ -+ dsize = desc_bytes(&tmpdesc); -+ -+ tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); -+ if (!tdesc) -+ return -ENOMEM; -+ -+ *desc = tdesc; -+ -+ print_hex_dump_debug("blob encap desc@" __stringify(__LINE__) ":", -+ DUMP_PREFIX_ADDRESS, 16, 4, *desc, -+ desc_bytes(*desc), 1); -+ return 0; -+} -+EXPORT_SYMBOL(cnstr_desc_blob_encap); -+ -+/* -+ * Construct a blob decapsulation job descriptor -+ * -+ * This function dynamically constructs a blob decapsulation job descriptor -+ * from the following arguments: -+ * -+ * @desc : Pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * @blob : Physical pointer (into external memory) of the blob to -+ * be decapsulated. Blob must reside in a contiguous memory -+ * segment. -+ * @blob_len : Size of the blob buffer to be decapsulated. -+ * @key_mod : Pointer to a key modifier, which must reside in a -+ * contiguous piece of memory. Modifier will be assumed to be -+ * 8 bytes long for a blob of type DATA_SECMEM, or 16 bytes -+ * long for a blob of type DATA_GENMEM -+ * @key_mod_len : Modifier length is 8 bytes long for a blob of type -+ * DATA_SECMEM, or 16 bytes long for a blob of type DATA_GENMEM -+ * @black_key : Physical pointer of the decapsulated output, possibly into -+ * a location within a secure memory page. Must be contiguous. -+ * @black_key_len : Size of encapsulated secret in bytes (not the size of the -+ * input blob). -+ * @keycolor : Determines if the source data is covered (black key) or -+ * plaintext (red key). RED_KEY or BLACK_KEY are defined in -+ * for this purpose. -+ * @key_enc : If BLACK_KEY source is covered via AES-CCM, specify -+ * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). -+ * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) -+ * or Trusted Descriptor Key Encryption Key (TDKEK) to -+ * decrypt the key to be loaded into a Key Register). -+ * @mem_type : Determine if encapsulated blob should be a secure memory -+ * blob (DATA_SECMEM), with partition data embedded with key -+ * material, or a general memory blob (DATA_GENMEM). -+ * Return : '0' on success, error code otherwise -+ * -+ * Upon completion, desc points to a buffer containing a CAAM job descriptor -+ * that decapsulates a key blob from external memory into a black (encrypted) -+ * key or red (plaintext) content. -+ * -+ * This is an example of a black key decapsulation job from a general memory -+ * blob. Notice the 16-byte key modifier in the LOAD instruction. -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400010 ld: ccb2-key len=16 offs=0 -+ * [02] 08A63B7F ptr->@0x08a63b7f -+ * [03] F8000010 seqoutptr: len=16 -+ * [04] 01000000 out_ptr->@0x01000000 -+ * [05] F000003A seqinptr: len=58 -+ * [06] 01000010 in_ptr->@0x01000010 -+ * [07] 860D0004 operation: decap blob reg=memory, black, format=normal -+ * -+ * This is an example of a red key decapsulation job for restoring a red key -+ * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset -+ * in the LOAD instruction: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400C08 ld: ccb2-key len=8 offs=12 -+ * [02] 01000000 ptr->@0x01000000 -+ * [03] F8000020 seqoutptr: len=32 -+ * [04] 400000E6 out_ptr->@0x400000e6 -+ * [05] F0000050 seqinptr: len=80 -+ * [06] 08F0C0EA in_ptr->@0x08f0c0ea -+ * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, -+ * format=normal -+ */ -+int cnstr_desc_blob_decap(u32 **desc, dma_addr_t blob, size_t blob_len, -+ const void *key_mod, size_t key_mod_len, -+ dma_addr_t black_key, size_t plaintext_len, -+ u8 keycolor, u8 key_enc, u8 trusted_key, u8 mem_type) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize; -+ u32 bk_store; -+ -+ /* Trusted key not supported */ -+ if (trusted_key != UNTRUSTED_KEY) -+ return -EOPNOTSUPP; -+ -+ memset(tmpdesc, 0, sizeof(tmpdesc)); -+ -+ init_job_desc(tmpdesc, 0); -+ -+ /* Load key modifier */ -+ if (mem_type == DATA_SECMEM) -+ append_load_as_imm(tmpdesc, key_mod, key_mod_len, -+ LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & -+ LDST_OFFSET_MASK)); -+ else /* is general memory blob */ -+ append_load_as_imm(tmpdesc, key_mod, key_mod_len, -+ LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); -+ -+ /* Compensate blob header + MAC tag over size of encapsulated secret */ -+ append_seq_in_ptr_intlen(tmpdesc, blob, plaintext_len + BLOB_OVERHEAD, -+ 0); -+ -+ append_seq_out_ptr_intlen(tmpdesc, black_key, plaintext_len, 0); -+ -+ /* Decapsulate from secure memory partition to black blob */ -+ bk_store = OP_PCLID_BLOB; -+ if (mem_type == DATA_SECMEM) -+ bk_store |= OP_PCL_BLOB_PTXT_SECMEM; -+ -+ if (key_enc == KEY_COVER_CCM) -+ bk_store |= OP_PCL_BLOB_EKT; -+ -+ /* An input black key cannot be stored in a red blob */ -+ if (keycolor == BLACK_KEY) -+ bk_store |= OP_PCL_BLOB_BLACK; -+ -+ /* Set blob encap, then color */ -+ append_operation(tmpdesc, OP_TYPE_DECAP_PROTOCOL | bk_store); -+ -+ dsize = desc_bytes(&tmpdesc); -+ -+ tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); -+ if (!tdesc) -+ return -ENOMEM; -+ -+ *desc = tdesc; -+ -+ print_hex_dump_debug("blob decap desc@" __stringify(__LINE__) ":", -+ DUMP_PREFIX_ADDRESS, 16, 4, *desc, -+ desc_bytes(*desc), 1); -+ -+ return 0; -+} -+EXPORT_SYMBOL(cnstr_desc_blob_decap); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("NXP CAAM Black Key and Blob descriptors"); -+MODULE_AUTHOR("NXP Semiconductors"); -diff --git a/drivers/crypto/caam/caamkeyblob_desc.h b/drivers/crypto/caam/caamkeyblob_desc.h -new file mode 100644 -index 000000000..0affbb184 ---- /dev/null -+++ b/drivers/crypto/caam/caamkeyblob_desc.h -@@ -0,0 +1,101 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * Shared descriptors for CAAM black key and blob -+ * -+ * Copyright 2018-2020 NXP -+ */ -+ -+#ifndef _CAAMKEYBLOB_DESC_H_ -+#define _CAAMKEYBLOB_DESC_H_ -+ -+#include -+ -+#include "jr.h" -+#include "regs.h" -+#include "desc.h" -+ -+#include "compat.h" -+#include "tag_object.h" -+#include "desc_constr.h" -+ -+/* Defines for secure memory and general memory blobs */ -+#define DATA_GENMEM 0 -+#define DATA_SECMEM 1 -+ -+/* Encrypted key */ -+#define BLACK_KEY 1 -+ -+/* Define key encryption/covering options */ -+#define KEY_COVER_ECB 0 /* cover key in AES-ECB */ -+#define KEY_COVER_CCM 1 /* cover key with AES-CCM */ -+ -+/* Define the trust in the key, to select either JDKEK or TDKEK */ -+#define UNTRUSTED_KEY 0 -+#define TRUSTED_KEY 1 -+ -+/* Define space required for BKEK + MAC tag storage in any blob */ -+#define BLOB_OVERHEAD (32 + 16) -+ -+#define PAD_16_BYTE(_key_size) (roundup(_key_size, 16)) -+#define PAD_8_BYTE(_key_size) (roundup(_key_size, 8)) -+ -+/* -+ * ECB-Black Key will be padded with zeros to make it a -+ * multiple of 16 bytes long before it is encrypted, -+ * and the resulting Black Key will be this length. -+ */ -+#define ECB_BLACK_KEY_SIZE(_key_size) (PAD_16_BYTE(_key_size)) -+ -+/* -+ * CCM-Black Key will always be at least 12 bytes longer, -+ * since the encapsulation uses a 6-byte nonce and adds -+ * a 6-byte ICV. But first, the key is padded as necessary so -+ * that CCM-Black Key is a multiple of 8 bytes long. -+ */ -+#define NONCE_SIZE 6 -+#define ICV_SIZE 6 -+#define CCM_OVERHEAD (NONCE_SIZE + ICV_SIZE) -+#define CCM_BLACK_KEY_SIZE(_key_size) (PAD_8_BYTE(_key_size) \ -+ + CCM_OVERHEAD) -+ -+static inline int secret_size_in_ccm_black_key(int key_size) -+{ -+ return ((key_size >= CCM_OVERHEAD) ? key_size - CCM_OVERHEAD : 0); -+} -+ -+#define SECRET_SIZE_IN_CCM_BLACK_KEY(_key_size) \ -+ secret_size_in_ccm_black_key(_key_size) -+ -+/* A red key is not encrypted so its size is the same */ -+#define RED_KEY_SIZE(_key_size) (_key_size) -+ -+/* -+ * Based on memory type, the key modifier length -+ * can be either 8-byte or 16-byte. -+ */ -+#define KEYMOD_SIZE_SM 8 -+#define KEYMOD_SIZE_GM 16 -+ -+/* Create job descriptor to cover key */ -+int cnstr_desc_black_key(u32 **desc, char *key, size_t key_len, -+ dma_addr_t black_key, size_t black_key_len, -+ u8 key_enc, u8 trusted_key); -+ -+/* Create job descriptor to generate a random key and cover it */ -+int cnstr_desc_random_black_key(u32 **desc, size_t key_len, -+ dma_addr_t black_key, size_t black_key_len, -+ u8 key_enc, u8 trusted_key); -+ -+/* Encapsulate data in a blob */ -+int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, -+ size_t black_key_len, u8 color, u8 key_enc, -+ u8 trusted_key, u8 mem_type, const void *key_mod, -+ size_t key_mod_len, dma_addr_t blob, size_t blob_len); -+ -+/* Decapsulate data from a blob */ -+int cnstr_desc_blob_decap(u32 **desc, dma_addr_t blob, size_t blob_len, -+ const void *key_mod, size_t key_mod_len, -+ dma_addr_t black_key, size_t black_key_len, -+ u8 keycolor, u8 key_enc, u8 trusted_key, u8 mem_type); -+ -+#endif /* _CAAMKEYBLOB_DESC_H_ */ -diff --git a/drivers/crypto/caam/caamkeyblob_test.c b/drivers/crypto/caam/caamkeyblob_test.c -new file mode 100644 -index 000000000..d4ca4ee3b ---- /dev/null -+++ b/drivers/crypto/caam/caamkeyblob_test.c -@@ -0,0 +1,127 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright 2018-2020 NXP -+ * -+ * Test of black key generation from a plaintext (of different size) -+ * and from random. -+ * The random black key is encapsulated into a blob. -+ * Next, the blob is decapsulated and the new obtained black key is -+ * compared to the random black key. -+ */ -+#include -+#include "caamkeyblob.h" -+ -+#define MAX_INPUT_SIZE 64 -+#define KEY_ENCRYPTION_ECB 1 -+#define KEY_ENCRYPTION_CCM 9 -+ -+static char input[MAX_INPUT_SIZE]; -+ -+static int create_black_key(struct device *dev, struct keyblob_info *info) -+{ -+ int ret; -+ -+ ret = generate_black_key(dev, info); -+ if (ret) -+ dev_err(dev, "black key of size: %zd, type: %d returned %d", -+ info->key_len, info->type, ret); -+ -+ return (ret) ? 1 : 0; -+} -+ -+static int black_key_test(void) -+{ -+ struct device *dev; -+ struct keyblob_info *info; -+ int i, ret = 0, nb_errors = 0; -+ unsigned char tmp_black_key[MAX_BLACK_KEY_SIZE]; -+ size_t tmp_black_key_len = 0; -+ -+ dev = caam_jr_alloc(); -+ if (!dev) -+ return -ENOMEM; -+ -+ info = kmalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return -ENOMEM; -+ -+ info->key = input; -+ -+ for (i = 1; i <= MAX_INPUT_SIZE; i++) { -+ info->key_len = i; -+ -+ /* Create a black key encrypted with AES-ECB */ -+ info->type = KEY_ENCRYPTION_ECB; -+ info->black_key_len = MAX_INPUT_SIZE; -+ nb_errors += create_black_key(dev, info); -+ -+ /* Create a black key encrypted with AES-CCM */ -+ info->type = KEY_ENCRYPTION_CCM; -+ info->black_key_len = MAX_INPUT_SIZE + CCM_OVERHEAD; -+ nb_errors += create_black_key(dev, info); -+ } -+ -+ /* Create, from random, a black key encrypted with AES-ECB */ -+ info->key = NULL; -+ info->type = KEY_ENCRYPTION_ECB; -+ info->black_key_len = MAX_INPUT_SIZE; -+ ret = create_black_key(dev, info); -+ nb_errors += (ret) ? 1 : 0; -+ -+ /* Save it for later to compare it */ -+ tmp_black_key_len = info->black_key_len; -+ memcpy(tmp_black_key, info->black_key, tmp_black_key_len); -+ -+ /* Encapsulate the random black key into a black blob */ -+ info->key = NULL; -+ /* Set key modifier, used as revision number, for blob */ -+ info->key_mod = caam_key_modifier; -+ info->key_mod_len = ARRAY_SIZE(caam_key_modifier); -+ /* Black key, encrypted with ECB-AES, in General Memory */ -+ info->type = KEY_ENCRYPTION_ECB; -+ info->key_len = MAX_INPUT_SIZE; -+ info->blob_len = MAX_BLOB_SIZE; -+ ret = caam_blob_encap(dev, info); -+ nb_errors += (ret) ? 1 : 0; -+ -+ /* Decapsulate the black key from the above black blob */ -+ ret = caam_blob_decap(dev, info); -+ nb_errors += (ret) ? 1 : 0; -+ -+ /* -+ * Compare the generated black key with -+ * the one decapsulated from the blob -+ */ -+ if (info->black_key_len == tmp_black_key_len) -+ ret = memcmp(tmp_black_key, info->black_key, tmp_black_key_len); -+ else -+ ret = 1; -+ nb_errors += ret; -+ -+ /* -+ * Check number of errors. -+ * If nb_errors > 0, at least one operation failed, success otherwise -+ */ -+ pr_info("Nb errors: %d\n", nb_errors); -+ -+ caam_jr_free(dev); -+ kfree(info); -+ -+ return nb_errors; -+} -+ -+static int black_key_test_init(void) -+{ -+ return black_key_test(); -+} -+ -+static void black_key_test_exit(void) -+{ -+} -+ -+module_init(black_key_test_init); -+module_exit(black_key_test_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("NXP CAAM Black Key and Blob Test"); -+MODULE_AUTHOR("NXP Semiconductors"); -diff --git a/drivers/crypto/caam/caamkeygen.c b/drivers/crypto/caam/caamkeygen.c -new file mode 100644 -index 000000000..9d4d909a6 ---- /dev/null -+++ b/drivers/crypto/caam/caamkeygen.c -@@ -0,0 +1,630 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright 2020 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "caamkeyblob.h" -+#include "intern.h" -+#include -+ -+#define DEVICE_NAME "caam-keygen" -+ -+static long caam_keygen_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg); -+ -+/** -+ * tag_black_obj - Tag a black object (key/blob) with a tag object header. -+ * -+ * @info : keyblob_info structure, which contains -+ * the black key/blob, obtained from CAAM, -+ * that needs to be tagged -+ * @black_max_len : The maximum size of the black object (blob/key) -+ * @blob : Used to determine if it's a blob or key object -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int tag_black_obj(struct keyblob_info *info, size_t black_max_len, -+ bool blob) -+{ -+ struct header_conf tag; -+ u32 type; -+ int ret; -+ u32 size_tagged = black_max_len; -+ -+ if (!info) -+ return -EINVAL; -+ -+ type = info->type; -+ -+ /* Prepare and set the tag */ -+ if (blob) { -+ init_tag_object_header(&tag, 0, type, info->key_len, -+ info->blob_len); -+ ret = set_tag_object_header_conf(&tag, info->blob, -+ info->blob_len, -+ &size_tagged); -+ } else { -+ init_tag_object_header(&tag, 0, type, info->key_len, -+ info->black_key_len); -+ ret = set_tag_object_header_conf(&tag, info->black_key, -+ info->black_key_len, -+ &size_tagged); -+ } -+ if (ret) -+ return ret; -+ -+ /* Update the size of the black key tagged */ -+ if (blob) -+ info->blob_len = size_tagged; -+ else -+ info->black_key_len = size_tagged; -+ -+ return ret; -+} -+ -+/** -+ * send_err_msg - Send the error message from kernel to user-space -+ * -+ * @msg : The message to be sent -+ * @output : The output buffer where we want to copy the error msg -+ * @size : The size of output buffer -+ */ -+static void send_err_msg(char *msg, void __user *output, size_t size) -+{ -+ size_t min_s; -+ char null_ch = 0; -+ -+ /* Not enough space to copy any message */ -+ if (size <= 1) -+ return; -+ -+ min_s = min(size - 1, strlen(msg)); -+ /* -+ * Avoid compile and checkpatch warnings, since we don't -+ * care about return value from copy_to_user -+ */ -+ (void)(copy_to_user(output, msg, min_s) + 1); -+ /* Copy null terminator */ -+ (void)(copy_to_user((output + min_s), &null_ch, 1) + 1); -+} -+ -+/** -+ * validate_key_size - Validate the key size from user. -+ * This can be the exact size given by user when -+ * generating a black key from random (with -s), -+ * or the size of the plaintext (with -t). -+ * -+ * @key_len : The size of key we want to validate -+ * @output : The output buffer where we want to copy the error msg -+ * @size : The size of output buffer -+ * -+ *Return : '0' on success, error code otherwise -+ */ -+static int validate_key_size(size_t key_len, void __user *output, size_t size) -+{ -+ char *msg = NULL; -+ -+ if (key_len < MIN_KEY_SIZE || key_len > MAX_KEY_SIZE) { -+ msg = "Invalid key size, expected values are between 16 and 64 bytes.\n"; -+ send_err_msg(msg, output, size); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * validate_input - Validate the input from user and set the -+ * keyblob_info structure. -+ * This contains the input key in case of black key -+ * generated from plaintext or size for random -+ * black key. -+ * -+ * @key_crt : Structure with data from user -+ * @arg : User-space argument from ioctl call -+ * @info : keyblob_info structure, will be updated with all the -+ * data from user-space -+ * @create_key_op : Used to determine if it's a create or import operation -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int validate_input(struct caam_keygen_cmd *key_crt, unsigned long arg, -+ struct keyblob_info *info, bool create_key_op) -+{ -+ char *tmp, *msg; -+ size_t tmp_size; -+ bool random = false; -+ int ret = 0; -+ u32 tmp_len = 0; -+ char null_ch = 0; -+ -+ /* -+ * So far, we only support Black keys, encrypted with JDKEK, -+ * kept in general memory, non-secure state. -+ * Therefore, default value for type is 1. -+ */ -+ u32 type = 1; -+ -+ if (copy_from_user(key_crt, (void __user *)arg, -+ sizeof(struct caam_keygen_cmd))) -+ return -EFAULT; -+ -+ /* Get blob_len from user. */ -+ info->blob_len = key_crt->blob_len; -+ /* Get black_key_len from user. */ -+ info->black_key_len = key_crt->black_key_len; -+ -+ /* -+ * Based on operation type validate a different set of input data. -+ * -+ * For key creation, validate the Encrypted Key Type, -+ * the Key Mode and Key Value -+ */ -+ if (create_key_op) { -+ /* -+ * Validate arguments received from user. -+ * These must be at least 1 since -+ * they have null terminator. -+ */ -+ if (key_crt->key_enc_len < 1 || key_crt->key_mode_len < 1 || -+ key_crt->key_value_len < 1) { -+ msg = "Invalid arguments.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ return -EFAULT; -+ } -+ /* -+ * Allocate memory for temporary buffer used to -+ * get the user arguments from user-space -+ */ -+ tmp_size = max_t(size_t, key_crt->key_enc_len, -+ max_t(size_t, key_crt->key_mode_len, -+ key_crt->key_value_len)) + 1; -+ tmp = kmalloc(tmp_size, GFP_KERNEL); -+ if (!tmp) { -+ msg = "Unable to allocate memory for temporary buffer.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ return -ENOMEM; -+ } -+ /* Add null terminator */ -+ tmp[tmp_size - 1] = null_ch; -+ /* -+ * Validate and set, in type, the Encrypted Key Type -+ * given from user-space. -+ * This must be ecb or ccm. -+ */ -+ if (copy_from_user(tmp, u64_to_user_ptr(key_crt->key_enc), -+ key_crt->key_enc_len)) { -+ msg = "Unable to copy from user the Encrypted Key Type.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ ret = -EFAULT; -+ goto free_resource; -+ } -+ if (!strcmp(tmp, "ccm")) { -+ type |= BIT(TAG_OBJ_EKT_OFFSET); -+ } else if (strcmp(tmp, "ecb")) { -+ msg = "Invalid argument for Encrypted Key Type, expected ecb or ccm.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ ret = -EINVAL; -+ goto free_resource; -+ } -+ /* -+ * Validate the Key Mode given from user-space. -+ * This must be -t (text), for a black key generated -+ * from a plaintext, or -s (size) for a black key -+ * generated from random. -+ */ -+ if (copy_from_user(tmp, u64_to_user_ptr(key_crt->key_mode), -+ key_crt->key_mode_len)) { -+ msg = "Unable to copy from user the Key Mode: random (-s) or plaintext (-t).\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ ret = -EFAULT; -+ goto free_resource; -+ } -+ if (!strcmp(tmp, "-s")) { -+ random = true; /* black key generated from random */ -+ } else if (strcmp(tmp, "-t")) { -+ msg = "Invalid argument for Key Mode, expected -s or -t.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ ret = -EINVAL; -+ goto free_resource; -+ } -+ /* -+ * Validate and set, into keyblob_info structure, -+ * the plaintext or key size, based on Key Mode. -+ */ -+ if (copy_from_user(tmp, u64_to_user_ptr(key_crt->key_value), -+ key_crt->key_value_len)) { -+ msg = "Unable to copy from user the Key Value: size or plaintext.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ ret = -EFAULT; -+ goto free_resource; -+ } -+ /* Black key generated from random, get its size */ -+ if (random) { -+ info->key = NULL; -+ ret = kstrtou32(tmp, 10, &tmp_len); -+ if (ret != 0) { -+ msg = "Invalid key size.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ goto free_resource; -+ } -+ ret = validate_key_size(tmp_len, -+ u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ if (ret) -+ goto free_resource; -+ -+ info->key_len = tmp_len; -+ } else { -+ /* -+ * Black key generated from plaintext, -+ * get the plaintext (input key) and its size -+ */ -+ ret = validate_key_size(strlen(tmp), -+ u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ if (ret) -+ goto free_resource; -+ -+ info->key = tmp; -+ info->key_len = strlen(tmp); -+ } -+ info->type = type; -+ } else { -+ /* For key import, get the blob from user-space */ -+ if (copy_from_user(info->blob, u64_to_user_ptr(key_crt->blob), -+ info->blob_len)) { -+ msg = "Unable to copy from user the blob.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->black_key), -+ key_crt->black_key_len); -+ return -EFAULT; -+ } -+ } -+ -+ goto exit; -+ -+free_resource: -+ kfree(tmp); -+ -+exit: -+ return ret; -+} -+ -+/** -+ * keygen_create_keyblob - Generate key and blob -+ * -+ * @info : keyblob_info structure, will be updated with -+ * the black key and blob data from CAAM -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int keygen_create_keyblob(struct keyblob_info *info) -+{ -+ int ret = 0; -+ struct device *jrdev; -+ -+ /* Allocate caam job ring for operation to be performed from CAAM */ -+ jrdev = caam_jr_alloc(); -+ if (IS_ERR(jrdev)) { -+ pr_err("Job Ring Device allocation failed\n"); -+ return PTR_ERR(jrdev); -+ } -+ -+ /* Create a black key */ -+ ret = generate_black_key(jrdev, info); -+ if (ret) { -+ dev_err(jrdev, "Black key generation failed: (%d)\n", ret); -+ goto free_jr; -+ } -+ -+ /* Clear the input key, if exists */ -+ if (info->key) -+ memset(info->key, 0, info->key_len); -+ -+ /* Set key modifier, used as revision number, for blob */ -+ info->key_mod = caam_key_modifier; -+ info->key_mod_len = ARRAY_SIZE(caam_key_modifier); -+ -+ /* -+ * Encapsulate the key, into a black blob, in general memory -+ * (the only memory type supported, right now) -+ */ -+ ret = caam_blob_encap(jrdev, info); -+ if (ret) { -+ dev_err(jrdev, "Blob encapsulation of black key failed: %d\n", -+ ret); -+ goto free_jr; -+ } -+ -+ /* Tag the black key so it can be passed to CAAM Crypto API */ -+ ret = tag_black_obj(info, sizeof(info->black_key), false); -+ if (ret) { -+ dev_err(jrdev, "Black key tagging failed: %d\n", ret); -+ goto free_jr; -+ } -+ -+ /* Tag the black blob so it can be passed to CAAM Crypto API */ -+ ret = tag_black_obj(info, sizeof(info->blob), true); -+ if (ret) { -+ dev_err(jrdev, "Black blob tagging failed: %d\n", ret); -+ goto free_jr; -+ } -+ -+free_jr: -+ caam_jr_free(jrdev); -+ -+ return ret; -+} -+ -+/** -+ * keygen_import_key - Import a black key from a blob -+ * -+ * @info : keyblob_info structure, will be updated with -+ * the black key obtained after blob decapsulation by CAAM -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int keygen_import_key(struct keyblob_info *info) -+{ -+ int ret = 0; -+ struct device *jrdev; -+ struct header_conf *header; -+ struct tagged_object *tag_obj; -+ -+ /* Allocate CAAM Job Ring for operation to be performed from CAAM */ -+ jrdev = caam_jr_alloc(); -+ if (IS_ERR(jrdev)) { -+ pr_err("Job Ring Device allocation failed\n"); -+ return PTR_ERR(jrdev); -+ } -+ -+ /* Set key modifier, used as revision number, for blob */ -+ info->key_mod = caam_key_modifier; -+ info->key_mod_len = ARRAY_SIZE(caam_key_modifier); -+ -+ print_hex_dump_debug("input blob @ " __stringify(__LINE__) " : ", -+ DUMP_PREFIX_ADDRESS, 16, 4, info->blob, -+ info->blob_len, 1); -+ -+ /* Check if one can retrieve the tag object header configuration */ -+ if (info->blob_len <= TAG_OVERHEAD_SIZE) { -+ dev_err(jrdev, "Invalid blob length\n"); -+ ret = -EINVAL; -+ goto free_jr; -+ } -+ -+ /* Retrieve the tag object */ -+ tag_obj = (struct tagged_object *)info->blob; -+ -+ /* -+ * Check tag object header configuration -+ * and retrieve the tag object header configuration -+ */ -+ if (is_valid_header_conf(&tag_obj->header)) { -+ header = &tag_obj->header; -+ } else { -+ dev_err(jrdev, -+ "Unable to get tag object header configuration for blob\n"); -+ ret = -EINVAL; -+ goto free_jr; -+ } -+ -+ info->key_len = header->red_key_len; -+ -+ /* Validate the red key size extracted from blob */ -+ if (info->key_len < MIN_KEY_SIZE || info->key_len > MAX_KEY_SIZE) { -+ dev_err(jrdev, -+ "Invalid red key length extracted from blob, expected values are between 16 and 64 bytes\n"); -+ ret = -EINVAL; -+ goto free_jr; -+ } -+ -+ info->type = header->type; -+ -+ /* Update blob length by removing the header size */ -+ info->blob_len -= TAG_OVERHEAD_SIZE; -+ -+ /* -+ * Check the received, from user, blob length -+ * with the one from tag header -+ */ -+ if (info->blob_len != header->obj_len) { -+ dev_err(jrdev, "Mismatch between received blob length and the one from tag header\n"); -+ ret = -EINVAL; -+ goto free_jr; -+ } -+ -+ /* -+ * Decapsulate the blob into a black key, -+ * in general memory (the only memory type supported, right now) -+ */ -+ ret = caam_blob_decap(jrdev, info); -+ if (ret) { -+ dev_err(jrdev, "Blob decapsulation failed: %d\n", ret); -+ goto free_jr; -+ } -+ -+ /* Tag the black key so it can be passed to CAAM Crypto API */ -+ ret = tag_black_obj(info, sizeof(info->black_key), false); -+ if (ret) -+ dev_err(jrdev, "Black key tagging failed: %d\n", ret); -+ -+free_jr: -+ caam_jr_free(jrdev); -+ -+ return ret; -+} -+ -+/** -+ * send_output - Send the output data (tagged key and blob) -+ * from kernel to user-space. -+ * -+ * @key_crt : Structure used to transfer data -+ * from user-space to kernel -+ * @info : keyblob_info structure, which contains all -+ * the data obtained from CAAM that needs to -+ * be transferred to user-space -+ * @create_key_op : Used to determine if it's a create or import operation -+ * @err : Error code received from previous operations -+ * -+ * Return : '0' on success, error code otherwise -+ */ -+static int send_output(struct caam_keygen_cmd *key_crt, unsigned long arg, -+ struct keyblob_info *info, bool create_key_op, int err) -+{ -+ int ret = 0; -+ char *msg; -+ -+ /* Free resource used on validate_input */ -+ kfree(info->key); -+ -+ if (err) -+ return err; -+ -+ /* Check if there's enough space to copy black key to user */ -+ if (key_crt->black_key_len < info->black_key_len) { -+ msg = "Not enough space for black key.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ /* Send, to user, the necessary size for key */ -+ key_crt->black_key_len = info->black_key_len; -+ -+ ret = -EINVAL; -+ goto exit; -+ } -+ key_crt->black_key_len = info->black_key_len; -+ -+ /* For key import, copy to user only the black key */ -+ if (copy_to_user(u64_to_user_ptr(key_crt->black_key), -+ info->black_key, info->black_key_len)) -+ return -EFAULT; -+ -+ /* For key creation, copy to user, also, the blob */ -+ if (create_key_op) { -+ /* Check if there's enough space to copy blob user */ -+ if (key_crt->blob_len < info->blob_len) { -+ msg = "Not enough space for blob key.\n"; -+ send_err_msg(msg, u64_to_user_ptr(key_crt->blob), -+ key_crt->blob_len); -+ /* Send, to user, the necessary size for blob */ -+ key_crt->blob_len = info->blob_len; -+ -+ ret = -EINVAL; -+ goto exit; -+ } -+ -+ key_crt->blob_len = info->blob_len; -+ -+ if (copy_to_user(u64_to_user_ptr(key_crt->blob), info->blob, -+ info->blob_len)) -+ return -EFAULT; -+ } -+ -+exit: -+ if (copy_to_user((void __user *)arg, key_crt, -+ sizeof(struct caam_keygen_cmd))) -+ return -EFAULT; -+ -+ return ret; -+} -+ -+static long caam_keygen_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret = 0; -+ struct keyblob_info info = {.key = NULL}; -+ struct caam_keygen_cmd key_crt; -+ /* Used to determine if it's a create or import operation */ -+ bool create_key_op = false; -+ -+ switch (cmd) { -+ case CAAM_KEYGEN_IOCTL_CREATE: -+ { -+ create_key_op = true; -+ -+ /* Validate user-space input */ -+ ret = validate_input(&key_crt, arg, &info, create_key_op); -+ if (ret) -+ break; -+ -+ /* Create tagged key and blob */ -+ ret = keygen_create_keyblob(&info); -+ -+ /* Send data from kernel to user-space */ -+ ret = send_output(&key_crt, arg, &info, create_key_op, ret); -+ -+ break; -+ } -+ case CAAM_KEYGEN_IOCTL_IMPORT: -+ { -+ /* Validate user-space input */ -+ ret = validate_input(&key_crt, arg, &info, create_key_op); -+ if (ret) -+ break; -+ -+ /* Import tagged key from blob */ -+ ret = keygen_import_key(&info); -+ -+ /* Send data from kernel to user-space */ -+ ret = send_output(&key_crt, arg, &info, create_key_op, ret); -+ -+ break; -+ } -+ default: -+ ret = -ENOTTY; -+ } -+ -+ return ret; -+} -+ -+static const struct file_operations fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = caam_keygen_ioctl, -+ .compat_ioctl = compat_ptr_ioctl, -+}; -+ -+static struct miscdevice caam_keygen_dev = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = DEVICE_NAME, -+ .fops = &fops -+}; -+ -+int caam_keygen_init(void) -+{ -+ int ret; -+ -+ ret = misc_register(&caam_keygen_dev); -+ if (ret) { -+ pr_err("Failed to register device %s\n", -+ caam_keygen_dev.name); -+ return ret; -+ } -+ -+ pr_info("Device %s registered\n", caam_keygen_dev.name); -+ -+ return 0; -+} -+ -+void caam_keygen_exit(void) -+{ -+ misc_deregister(&caam_keygen_dev); -+ -+ pr_info("caam_keygen unregistered\n"); -+} -diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c -index dd5f101e4..6f2615336 100644 ---- a/drivers/crypto/caam/caampkc.c -+++ b/drivers/crypto/caam/caampkc.c -@@ -1158,10 +1158,10 @@ int caam_pkc_init(struct device *ctrldev) - - /* Determine public key hardware accelerator presence. */ - if (priv->era < 10) -- pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & -+ pk_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) & - CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT; - else -- pk_inst = rd_reg32(&priv->ctrl->vreg.pkha) & CHA_VER_NUM_MASK; -+ pk_inst = rd_reg32(&priv->jr[0]->vreg.pkha) & CHA_VER_NUM_MASK; - - /* Do not register algorithms if PKHA is not present. */ - if (!pk_inst) -diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c -index 77d048dfe..a550e7230 100644 ---- a/drivers/crypto/caam/caamrng.c -+++ b/drivers/crypto/caam/caamrng.c -@@ -170,6 +170,52 @@ static void caam_cleanup(struct hwrng *rng) - kfifo_free(&ctx->fifo); - } - -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST -+static inline void test_len(struct hwrng *rng, size_t len, bool wait) -+{ -+ u8 *buf; -+ int real_len; -+ struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng); -+ struct device *dev = ctx->ctrldev; -+ -+ buf = kzalloc(sizeof(u8) * len, GFP_KERNEL); -+ real_len = rng->read(rng, buf, len, wait); -+ dev_info(dev, "wanted %zu bytes, got %d\n", len, real_len); -+ if (real_len < 0) -+ dev_err(dev, "READ FAILED\n"); -+ else if (real_len == 0 && wait) -+ dev_err(dev, "WAITING FAILED\n"); -+ if (real_len > 0) -+ print_hex_dump_debug("random bytes@: ", DUMP_PREFIX_ADDRESS, 16, -+ 4, buf, real_len, 1); -+ kfree(buf); -+} -+ -+static inline void test_mode_once(struct hwrng *rng, bool wait) -+{ -+ test_len(rng, 32, wait); -+ test_len(rng, 64, wait); -+ test_len(rng, 128, wait); -+} -+ -+static inline void test_mode(struct hwrng *rng, bool wait) -+{ -+#define TEST_PASS 1 -+ int i; -+ -+ for (i = 0; i < TEST_PASS; i++) -+ test_mode_once(rng, wait); -+} -+ -+static void self_test(struct hwrng *rng) -+{ -+ pr_info("testing without waiting\n"); -+ test_mode(rng, false); -+ pr_info("testing with waiting\n"); -+ test_mode(rng, true); -+} -+#endif -+ - static int caam_init(struct hwrng *rng) - { - struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng); -@@ -224,10 +270,10 @@ int caam_rng_init(struct device *ctrldev) - - /* Check for an instantiated RNG before registration */ - if (priv->era < 10) -- rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & -+ rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) & - CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; - else -- rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK; -+ rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK; - - if (!rng_inst) - return 0; -@@ -256,6 +302,10 @@ int caam_rng_init(struct device *ctrldev) - return ret; - } - -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST -+ self_test(&ctx->rng); -+#endif -+ - devres_close_group(ctrldev, caam_rng_init); - return 0; - } -diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c -index ca0361b2d..1cf3de63f 100644 ---- a/drivers/crypto/caam/ctrl.c -+++ b/drivers/crypto/caam/ctrl.c -@@ -7,6 +7,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -19,6 +20,7 @@ - #include "jr.h" - #include "desc_constr.h" - #include "ctrl.h" -+#include "sm.h" - - bool caam_dpaa2; - EXPORT_SYMBOL(caam_dpaa2); -@@ -79,6 +81,14 @@ static void build_deinstantiation_desc(u32 *desc, int handle) - append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); - } - -+static const struct of_device_id imx8m_machine_match[] = { -+ { .compatible = "fsl,imx8mm", }, -+ { .compatible = "fsl,imx8mn", }, -+ { .compatible = "fsl,imx8mp", }, -+ { .compatible = "fsl,imx8mq", }, -+ { } -+}; -+ - /* - * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of - * the software (no JR/QI used). -@@ -105,10 +115,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, - * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1 - * and the following steps should be performed regardless - */ -- of_machine_is_compatible("fsl,imx8mq") || -- of_machine_is_compatible("fsl,imx8mm") || -- of_machine_is_compatible("fsl,imx8mn") || -- of_machine_is_compatible("fsl,imx8mp")) { -+ of_match_node(imx8m_machine_match, of_root)) { - clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); - - while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && -@@ -342,16 +349,15 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask, - /* - * kick_trng - sets the various parameters for enabling the initialization - * of the RNG4 block in CAAM -- * @pdev - pointer to the platform device -+ * @dev - pointer to the controller device - * @ent_delay - Defines the length (in system clocks) of each entropy sample. - */ --static void kick_trng(struct platform_device *pdev, int ent_delay) -+static void kick_trng(struct device *dev, int ent_delay) - { -- struct device *ctrldev = &pdev->dev; -- struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); - struct caam_ctrl __iomem *ctrl; - struct rng4tst __iomem *r4tst; -- u32 val; -+ u32 val, rtsdctl; - - ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; - r4tst = &ctrl->r4tst[0]; -@@ -367,26 +373,38 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) - * Performance-wise, it does not make sense to - * set the delay to a value that is lower - * than the last one that worked (i.e. the state handles -- * were instantiated properly. Thus, instead of wasting -- * time trying to set the values controlling the sample -- * frequency, the function simply returns. -+ * were instantiated properly). - */ -- val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) -- >> RTSDCTL_ENT_DLY_SHIFT; -- if (ent_delay <= val) -- goto start_rng; -- -- val = rd_reg32(&r4tst->rtsdctl); -- val = (val & ~RTSDCTL_ENT_DLY_MASK) | -- (ent_delay << RTSDCTL_ENT_DLY_SHIFT); -- wr_reg32(&r4tst->rtsdctl, val); -- /* min. freq. count, equal to 1/4 of the entropy sample length */ -- wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); -- /* disable maximum frequency count */ -- wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); -- /* read the control register */ -- val = rd_reg32(&r4tst->rtmctl); --start_rng: -+ rtsdctl = rd_reg32(&r4tst->rtsdctl); -+ val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT; -+ if (ent_delay > val) { -+ val = ent_delay; -+ /* min. freq. count, equal to 1/4 of the entropy sample length */ -+ wr_reg32(&r4tst->rtfrqmin, val >> 2); -+ /* max. freq. count, equal to 16 times the entropy sample length */ -+ wr_reg32(&r4tst->rtfrqmax, val << 4); -+ } -+ -+ wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) | -+ RTSDCTL_SAMP_SIZE_VAL); -+ -+ /* -+ * To avoid reprogramming the self-test parameters over and over again, -+ * use RTSDCTL[SAMP_SIZE] as an indicator. -+ */ -+ if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) { -+ wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32); -+ wr_reg32(&r4tst->rtpkrrng, 570); -+ wr_reg32(&r4tst->rtpkrmax, 1600); -+ wr_reg32(&r4tst->rtscml, (122 << 16) | 317); -+ wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107); -+ wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62); -+ wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39); -+ wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26); -+ wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18); -+ wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17); -+ } -+ - /* - * select raw sampling in both entropy shifter - * and statistical checker; ; put RNG4 into run mode -@@ -395,7 +413,7 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) - RTMCTL_SAMP_MODE_RAW_ES_SC); - } - --static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) -+static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon) - { - static const struct { - u16 ip_id; -@@ -421,12 +439,12 @@ static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) - u16 ip_id; - int i; - -- ccbvid = rd_reg32(&ctrl->perfmon.ccb_id); -+ ccbvid = rd_reg32(&perfmon->ccb_id); - era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT; - if (era) /* This is '0' prior to CAAM ERA-6 */ - return era; - -- id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms); -+ id_ms = rd_reg32(&perfmon->caam_id_ms); - ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT; - maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT; - -@@ -446,7 +464,7 @@ static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) - * - * @ctrl: controller region - */ --static int caam_get_era(struct caam_ctrl __iomem *ctrl) -+static int caam_get_era(struct caam_perfmon __iomem *perfmon) - { - struct device_node *caam_node; - int ret; -@@ -459,7 +477,7 @@ static int caam_get_era(struct caam_ctrl __iomem *ctrl) - if (!ret) - return prop; - else -- return caam_get_era_from_hw(ctrl); -+ return caam_get_era_from_hw(perfmon); - } - - /* -@@ -589,6 +607,214 @@ static void caam_remove_debugfs(void *root) - debugfs_remove_recursive(root); - } - -+static void caam_dma_dev_unregister(void *data) -+{ -+ platform_device_unregister(data); -+} -+ -+static int caam_ctrl_rng_init(struct device *dev) -+{ -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); -+ struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; -+ int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; -+ u8 rng_vid; -+ -+ if (ctrlpriv->era < 10) { -+ struct caam_perfmon __iomem *perfmon; -+ -+ perfmon = ctrlpriv->total_jobrs ? -+ (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon : -+ (struct caam_perfmon *)&ctrl->perfmon; -+ -+ rng_vid = (rd_reg32(&perfmon->cha_id_ls) & -+ CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; -+ } else { -+ struct version_regs __iomem *vreg; -+ -+ vreg = ctrlpriv->total_jobrs ? -+ (struct version_regs *)&ctrlpriv->jr[0]->vreg : -+ (struct version_regs *)&ctrl->vreg; -+ -+ rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >> -+ CHA_VER_VID_SHIFT; -+ } -+ -+ /* -+ * If SEC has RNG version >= 4 and RNG state handle has not been -+ * already instantiated, do RNG instantiation -+ * In case of SoCs with Management Complex, RNG is managed by MC f/w. -+ */ -+ if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) { -+ ctrlpriv->rng4_sh_init = -+ rd_reg32(&ctrl->r4tst[0].rdsta); -+ /* -+ * If the secure keys (TDKEK, JDKEK, TDSK), were already -+ * generated, signal this to the function that is instantiating -+ * the state handles. An error would occur if RNG4 attempts -+ * to regenerate these keys before the next POR. -+ */ -+ gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; -+ ctrlpriv->rng4_sh_init &= RDSTA_MASK; -+ do { -+ int inst_handles = -+ rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK; -+ /* -+ * If either SH were instantiated by somebody else -+ * (e.g. u-boot) then it is assumed that the entropy -+ * parameters are properly set and thus the function -+ * setting these (kick_trng(...)) is skipped. -+ * Also, if a handle was instantiated, do not change -+ * the TRNG parameters. -+ */ -+ if (!(ctrlpriv->rng4_sh_init || inst_handles)) { -+ dev_info(dev, -+ "Entropy delay = %u\n", -+ ent_delay); -+ kick_trng(dev, ent_delay); -+ ent_delay += 400; -+ } -+ /* -+ * if instantiate_rng(...) fails, the loop will rerun -+ * and the kick_trng(...) function will modify the -+ * upper and lower limits of the entropy sampling -+ * interval, leading to a successful initialization of -+ * the RNG. -+ */ -+ ret = instantiate_rng(dev, inst_handles, -+ gen_sk); -+ if (ret == -EAGAIN) -+ /* -+ * if here, the loop will rerun, -+ * so don't hog the CPU -+ */ -+ cpu_relax(); -+ } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); -+ if (ret) { -+ dev_err(dev, "failed to instantiate RNG"); -+ return ret; -+ } -+ /* -+ * Set handles initialized by this module as the complement of -+ * the already initialized ones -+ */ -+ ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK; -+ -+ /* Enable RDB bit so that RNG works faster */ -+ clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+ -+/* Indicate if the internal state of the CAAM is lost during PM */ -+static int caam_off_during_pm(void) -+{ -+ bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") || -+ of_machine_is_compatible("fsl,imx6qp") || -+ of_machine_is_compatible("fsl,imx6dl"); -+ -+ return not_off_during_pm ? 0 : 1; -+} -+ -+static void caam_state_save(struct device *dev) -+{ -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); -+ struct caam_ctl_state *state = &ctrlpriv->state; -+ struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; -+ u32 deco_inst, jr_inst; -+ int i; -+ -+ state->mcr = rd_reg32(&ctrl->mcr); -+ state->scfgr = rd_reg32(&ctrl->scfgr); -+ -+ deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & -+ CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT; -+ for (i = 0; i < deco_inst; i++) { -+ state->deco_mid[i].liodn_ms = -+ rd_reg32(&ctrl->deco_mid[i].liodn_ms); -+ state->deco_mid[i].liodn_ls = -+ rd_reg32(&ctrl->deco_mid[i].liodn_ls); -+ } -+ -+ jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & -+ CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT; -+ for (i = 0; i < jr_inst; i++) { -+ state->jr_mid[i].liodn_ms = -+ rd_reg32(&ctrl->jr_mid[i].liodn_ms); -+ state->jr_mid[i].liodn_ls = -+ rd_reg32(&ctrl->jr_mid[i].liodn_ls); -+ } -+} -+ -+static void caam_state_restore(const struct device *dev) -+{ -+ const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); -+ const struct caam_ctl_state *state = &ctrlpriv->state; -+ struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; -+ u32 deco_inst, jr_inst; -+ int i; -+ -+ wr_reg32(&ctrl->mcr, state->mcr); -+ wr_reg32(&ctrl->scfgr, state->scfgr); -+ -+ deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & -+ CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT; -+ for (i = 0; i < deco_inst; i++) { -+ wr_reg32(&ctrl->deco_mid[i].liodn_ms, -+ state->deco_mid[i].liodn_ms); -+ wr_reg32(&ctrl->deco_mid[i].liodn_ls, -+ state->deco_mid[i].liodn_ls); -+ } -+ -+ jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & -+ CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT; -+ for (i = 0; i < ctrlpriv->total_jobrs; i++) { -+ wr_reg32(&ctrl->jr_mid[i].liodn_ms, -+ state->jr_mid[i].liodn_ms); -+ wr_reg32(&ctrl->jr_mid[i].liodn_ls, -+ state->jr_mid[i].liodn_ls); -+ } -+ -+ if (ctrlpriv->virt_en == 1) -+ clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | -+ JRSTART_JR1_START | JRSTART_JR2_START | -+ JRSTART_JR3_START); -+} -+ -+static int caam_ctrl_suspend(struct device *dev) -+{ -+ const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); -+ -+ if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en && -+ !ctrlpriv->optee_en) -+ caam_state_save(dev); -+ -+ return 0; -+} -+ -+static int caam_ctrl_resume(struct device *dev) -+{ -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); -+ int ret = 0; -+ -+ if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en && -+ !ctrlpriv->optee_en) { -+ caam_state_restore(dev); -+ -+ /* HW and rng will be reset so deinstantiation can be removed */ -+ devm_remove_action(dev, devm_deinstantiate_rng, dev); -+ ret = caam_ctrl_rng_init(dev); -+ } -+ -+ return ret; -+} -+ -+SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume); -+ -+#endif /* CONFIG_PM_SLEEP */ -+ - #ifdef CONFIG_FSL_MC_BUS - static bool check_version(struct fsl_mc_version *mc_version, u32 major, - u32 minor, u32 revision) -@@ -612,19 +838,25 @@ static bool check_version(struct fsl_mc_version *mc_version, u32 major, - /* Probe routine for CAAM top (controller) level */ - static int caam_probe(struct platform_device *pdev) - { -- int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; -+ int ret, ring; - u64 caam_id; - const struct soc_device_attribute *imx_soc_match; -+ static struct platform_device_info caam_dma_pdev_info = { -+ .name = "caam-dma", -+ .id = PLATFORM_DEVID_NONE -+ }; -+ static struct platform_device *caam_dma_dev; - struct device *dev; - struct device_node *nprop, *np; -+ struct resource res_regs; - struct caam_ctrl __iomem *ctrl; - struct caam_drv_private *ctrlpriv; -+ struct caam_perfmon __iomem *perfmon; - struct dentry *dfs_root; - u32 scfgr, comp_params; -- u8 rng_vid; - int pg_size; - int BLOCK_OFFSET = 0; -- bool pr_support = false; -+ bool reg_access = true; - - ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); - if (!ctrlpriv) -@@ -635,9 +867,44 @@ static int caam_probe(struct platform_device *pdev) - nprop = pdev->dev.of_node; - - imx_soc_match = soc_device_match(caam_imx_soc_table); -+ if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root)) -+ return -EPROBE_DEFER; -+ - caam_imx = (bool)imx_soc_match; - -+#ifdef CONFIG_PM_SLEEP -+ ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm(); -+#endif -+ - if (imx_soc_match) { -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu"); -+ -+ if (!np) -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx-sentinel"); -+ -+ ctrlpriv->scu_en = !!np; -+ of_node_put(np); -+ -+ reg_access = !ctrlpriv->scu_en; -+ -+ /* -+ * CAAM clocks cannot be controlled from kernel. -+ * They are automatically turned on by SCU f/w. -+ */ -+ if (ctrlpriv->scu_en) -+ goto iomap_ctrl; -+ -+ /* -+ * Until Layerscape and i.MX OP-TEE get in sync, -+ * only i.MX OP-TEE use cases disallow access to -+ * caam page 0 (controller) registers. -+ */ -+ np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); -+ ctrlpriv->optee_en = !!np; -+ of_node_put(np); -+ -+ reg_access = reg_access && !ctrlpriv->optee_en; -+ - if (!imx_soc_match->data) { - dev_err(dev, "No clock data provided for i.MX SoC"); - return -EINVAL; -@@ -648,7 +915,7 @@ static int caam_probe(struct platform_device *pdev) - return ret; - } - -- -+iomap_ctrl: - /* Get configuration properties from device tree */ - /* First, get register page */ - ctrl = devm_of_iomap(dev, nprop, 0, NULL); -@@ -658,10 +925,38 @@ static int caam_probe(struct platform_device *pdev) - return ret; - } - -- caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & -+ ring = 0; -+ for_each_available_child_of_node(nprop, np) -+ if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || -+ of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { -+ u32 reg; -+ -+ if (of_property_read_u32_index(np, "reg", 0, ®)) { -+ dev_err(dev, "%s read reg property error\n", -+ np->full_name); -+ continue; -+ } -+ -+ ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) -+ ((__force uint8_t *)ctrl + reg); -+ -+ ctrlpriv->total_jobrs++; -+ ring++; -+ } -+ -+ /* -+ * Wherever possible, instead of accessing registers from the global page, -+ * use the alias registers in the first (cf. DT nodes order) -+ * job ring's page. -+ */ -+ perfmon = ring ? (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon : -+ (struct caam_perfmon *)&ctrl->perfmon; -+ -+ caam_little_end = !(bool)(rd_reg32(&perfmon->status) & - (CSTA_PLEND | CSTA_ALT_PLEND)); -- comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); -- if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) -+ comp_params = rd_reg32(&perfmon->comp_parms_ms); -+ if (reg_access && comp_params & CTPR_MS_PS && -+ rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) - caam_ptr_sz = sizeof(u64); - else - caam_ptr_sz = sizeof(u32); -@@ -708,8 +1003,6 @@ static int caam_probe(struct platform_device *pdev) - BLOCK_OFFSET * DECO_BLOCK_NUMBER - ); - -- /* Get the IRQ of the controller (for security violations only) */ -- ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); - np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc"); - ctrlpriv->mc_en = !!np; - of_node_put(np); -@@ -720,12 +1013,44 @@ static int caam_probe(struct platform_device *pdev) - - mc_version = fsl_mc_get_version(); - if (mc_version) -- pr_support = check_version(mc_version, 10, 20, 0); -+ ctrlpriv->pr_support = check_version(mc_version, 10, 20, -+ 0); - else - return -EPROBE_DEFER; - } - #endif - -+ /* Only i.MX SoCs have sm */ -+ if (!imx_soc_match) -+ goto mc_fw; -+ -+ /* Get CAAM-SM node and of_iomap() and save */ -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); -+ if (!np) -+ return -ENODEV; -+ -+ /* Get CAAM SM registers base address from device tree */ -+ ret = of_address_to_resource(np, 0, &res_regs); -+ if (ret) { -+ dev_err(dev, "failed to retrieve registers base from device tree\n"); -+ of_node_put(np); -+ return -ENODEV; -+ } -+ -+ ctrlpriv->sm_phy = res_regs.start; -+ ctrlpriv->sm_base = devm_ioremap_resource(dev, &res_regs); -+ if (IS_ERR(ctrlpriv->sm_base)) { -+ of_node_put(np); -+ return PTR_ERR(ctrlpriv->sm_base); -+ } -+ -+ ctrlpriv->sm_present = 1; -+ of_node_put(np); -+ -+ if (!reg_access) -+ goto set_dma_mask; -+ -+mc_fw: - /* - * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, - * long pointers in master configuration register. -@@ -765,13 +1090,14 @@ static int caam_probe(struct platform_device *pdev) - JRSTART_JR1_START | JRSTART_JR2_START | - JRSTART_JR3_START); - -+set_dma_mask: - ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev)); - if (ret) { - dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); - return ret; - } - -- ctrlpriv->era = caam_get_era(ctrl); -+ ctrlpriv->era = caam_get_era(perfmon); - ctrlpriv->domain = iommu_get_domain_for_dev(dev); - - dfs_root = debugfs_create_dir(dev_name(dev), NULL); -@@ -782,7 +1108,7 @@ static int caam_probe(struct platform_device *pdev) - return ret; - } - -- caam_debugfs_init(ctrlpriv, dfs_root); -+ caam_debugfs_init(ctrlpriv, perfmon, dfs_root); - - /* Check to see if (DPAA 1.x) QI present. If so, enable */ - if (ctrlpriv->qi_present && !caam_dpaa2) { -@@ -801,101 +1127,34 @@ static int caam_probe(struct platform_device *pdev) - #endif - } - -- ring = 0; -- for_each_available_child_of_node(nprop, np) -- if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || -- of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { -- ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) -- ((__force uint8_t *)ctrl + -- (ring + JR_BLOCK_NUMBER) * -- BLOCK_OFFSET -- ); -- ctrlpriv->total_jobrs++; -- ring++; -- } -- - /* If no QI and no rings specified, quit and go home */ - if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { - dev_err(dev, "no queues configured, terminating\n"); - return -ENOMEM; - } - -- if (ctrlpriv->era < 10) -- rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) & -- CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; -- else -- rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >> -- CHA_VER_VID_SHIFT; -- -- /* -- * If SEC has RNG version >= 4 and RNG state handle has not been -- * already instantiated, do RNG instantiation -- * In case of SoCs with Management Complex, RNG is managed by MC f/w. -- */ -- if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) { -- ctrlpriv->rng4_sh_init = -- rd_reg32(&ctrl->r4tst[0].rdsta); -- /* -- * If the secure keys (TDKEK, JDKEK, TDSK), were already -- * generated, signal this to the function that is instantiating -- * the state handles. An error would occur if RNG4 attempts -- * to regenerate these keys before the next POR. -- */ -- gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; -- ctrlpriv->rng4_sh_init &= RDSTA_MASK; -- do { -- int inst_handles = -- rd_reg32(&ctrl->r4tst[0].rdsta) & -- RDSTA_MASK; -- /* -- * If either SH were instantiated by somebody else -- * (e.g. u-boot) then it is assumed that the entropy -- * parameters are properly set and thus the function -- * setting these (kick_trng(...)) is skipped. -- * Also, if a handle was instantiated, do not change -- * the TRNG parameters. -- */ -- if (!(ctrlpriv->rng4_sh_init || inst_handles)) { -- dev_info(dev, -- "Entropy delay = %u\n", -- ent_delay); -- kick_trng(pdev, ent_delay); -- ent_delay += 400; -- } -- /* -- * if instantiate_rng(...) fails, the loop will rerun -- * and the kick_trng(...) function will modify the -- * upper and lower limits of the entropy sampling -- * interval, leading to a successful initialization of -- * the RNG. -- */ -- ret = instantiate_rng(dev, inst_handles, -- gen_sk); -- if (ret == -EAGAIN) -- /* -- * if here, the loop will rerun, -- * so don't hog the CPU -- */ -- cpu_relax(); -- } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); -- if (ret) { -- dev_err(dev, "failed to instantiate RNG"); -+ caam_dma_pdev_info.parent = dev; -+ caam_dma_pdev_info.dma_mask = dma_get_mask(dev); -+ caam_dma_dev = platform_device_register_full(&caam_dma_pdev_info); -+ if (IS_ERR(caam_dma_dev)) { -+ dev_err(dev, "Unable to create and register caam-dma dev\n"); -+ return PTR_ERR(caam_dma_dev); -+ } else { -+ set_dma_ops(&caam_dma_dev->dev, get_dma_ops(dev)); -+ ret = devm_add_action_or_reset(dev, caam_dma_dev_unregister, -+ caam_dma_dev); -+ if (ret) - return ret; -- } -- /* -- * Set handles initialized by this module as the complement of -- * the already initialized ones -- */ -- ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK; -- -- /* Enable RDB bit so that RNG works faster */ -- clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); - } - -- /* NOTE: RTIC detection ought to go here, around Si time */ -+ if (reg_access) { -+ ret = caam_ctrl_rng_init(dev); -+ if (ret) -+ return ret; -+ } - -- caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | -- (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); -+ caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 | -+ (u64)rd_reg32(&perfmon->caam_id_ls); - - /* Report "alive" for developer to see */ - dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, -@@ -914,6 +1173,9 @@ static struct platform_driver caam_driver = { - .driver = { - .name = "caam", - .of_match_table = caam_match, -+#ifdef CONFIG_PM_SLEEP -+ .pm = &caam_ctrl_pm_ops, -+#endif - }, - .probe = caam_probe, - }; -diff --git a/drivers/crypto/caam/debugfs.c b/drivers/crypto/caam/debugfs.c -index 8ebf18398..a34d71ac1 100644 ---- a/drivers/crypto/caam/debugfs.c -+++ b/drivers/crypto/caam/debugfs.c -@@ -42,16 +42,14 @@ void caam_debugfs_qi_init(struct caam_drv_private *ctrlpriv) - } - #endif - --void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry *root) -+void caam_debugfs_init(struct caam_drv_private *ctrlpriv, -+ struct caam_perfmon *perfmon, struct dentry *root) - { -- struct caam_perfmon *perfmon; -- - /* - * FIXME: needs better naming distinction, as some amalgamation of - * "caam" and nprop->full_name. The OF name isn't distinctive, - * but does separate instances - */ -- perfmon = (struct caam_perfmon __force *)&ctrlpriv->ctrl->perfmon; - - ctrlpriv->ctl = debugfs_create_dir("ctl", root); - -@@ -78,6 +76,9 @@ void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry *root) - debugfs_create_file("fault_status", 0444, ctrlpriv->ctl, - &perfmon->status, &caam_fops_u32_ro); - -+ if (ctrlpriv->scu_en || ctrlpriv->optee_en) -+ return; -+ - /* Internal covering keys (useful in non-secure mode only) */ - ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; - ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); -diff --git a/drivers/crypto/caam/debugfs.h b/drivers/crypto/caam/debugfs.h -index 661d768ac..6c566a2b7 100644 ---- a/drivers/crypto/caam/debugfs.h -+++ b/drivers/crypto/caam/debugfs.h -@@ -6,11 +6,14 @@ - - struct dentry; - struct caam_drv_private; -+struct caam_perfmon; - - #ifdef CONFIG_DEBUG_FS --void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry *root); -+void caam_debugfs_init(struct caam_drv_private *ctrlpriv, -+ struct caam_perfmon *perfmon, struct dentry *root); - #else - static inline void caam_debugfs_init(struct caam_drv_private *ctrlpriv, -+ struct caam_perfmon *perfmon, - struct dentry *root) - {} - #endif -diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h -index e13470901..c2c58f818 100644 ---- a/drivers/crypto/caam/desc.h -+++ b/drivers/crypto/caam/desc.h -@@ -43,6 +43,7 @@ - #define CMD_SEQ_LOAD (0x03 << CMD_SHIFT) - #define CMD_FIFO_LOAD (0x04 << CMD_SHIFT) - #define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT) -+#define CMD_MOVEB (0x07 << CMD_SHIFT) - #define CMD_STORE (0x0a << CMD_SHIFT) - #define CMD_SEQ_STORE (0x0b << CMD_SHIFT) - #define CMD_FIFO_STORE (0x0c << CMD_SHIFT) -@@ -152,7 +153,7 @@ - * with the TDKEK if TK is set - */ - #define KEY_ENC 0x00400000 -- -+#define KEY_ENC_OFFSET 22 - /* - * No Write Back - Do not allow key to be FIFO STOREd - */ -@@ -162,11 +163,13 @@ - * Enhanced Encryption of Key - */ - #define KEY_EKT 0x00100000 -+#define KEY_EKT_OFFSET 20 - - /* - * Encrypted with Trusted Key - */ - #define KEY_TK 0x00008000 -+#define KEY_TK_OFFSET 15 - - /* - * KDEST - Key Destination: 0 - class key register, -@@ -363,6 +366,7 @@ - #define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT) - #define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT) - #define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT) -+#define FIFOLD_TYPE_IFIFO (0x0f << FIFOLD_TYPE_SHIFT) - - /* Other types. Need to OR in last/flush bits as desired */ - #define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT) -@@ -403,6 +407,10 @@ - #define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) - #define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) - #define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) -+#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT) -+#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT) -+#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT) -+#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT) - #define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT) - #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) - #define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) -@@ -1136,6 +1144,23 @@ - #define OP_PCL_PKPROT_ECC 0x0002 - #define OP_PCL_PKPROT_F2M 0x0001 - -+/* Blob protocol protinfo bits */ -+#define OP_PCL_BLOB_TK 0x0200 -+#define OP_PCL_BLOB_EKT 0x0100 -+ -+#define OP_PCL_BLOB_K2KR_MEM 0x0000 -+#define OP_PCL_BLOB_K2KR_C1KR 0x0010 -+#define OP_PCL_BLOB_K2KR_C2KR 0x0030 -+#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 -+#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 -+ -+#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 -+#define OP_PCL_BLOB_BLACK 0x0004 -+ -+#define OP_PCL_BLOB_FMT_NORMAL 0x0000 -+#define OP_PCL_BLOB_FMT_MSTR 0x0002 -+#define OP_PCL_BLOB_FMT_TEST 0x0003 -+ - /* For non-protocol/alg-only op commands */ - #define OP_ALG_TYPE_SHIFT 24 - #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) -@@ -1502,6 +1527,7 @@ - #define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT) - #define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT) - #define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT) -+#define MATH_SRC1_ZERO (0x0f << MATH_SRC1_SHIFT) - - /* Destination selectors */ - #define MATH_DEST_SHIFT 8 -@@ -1684,4 +1710,31 @@ - /* Frame Descriptor Command for Replacement Job Descriptor */ - #define FD_CMD_REPLACE_JOB_DESC 0x20000000 - -+/* CHA Control Register bits */ -+#define CCTRL_RESET_CHA_ALL 0x1 -+#define CCTRL_RESET_CHA_AESA 0x2 -+#define CCTRL_RESET_CHA_DESA 0x4 -+#define CCTRL_RESET_CHA_AFHA 0x8 -+#define CCTRL_RESET_CHA_KFHA 0x10 -+#define CCTRL_RESET_CHA_SF8A 0x20 -+#define CCTRL_RESET_CHA_PKHA 0x40 -+#define CCTRL_RESET_CHA_MDHA 0x80 -+#define CCTRL_RESET_CHA_CRCA 0x100 -+#define CCTRL_RESET_CHA_RNG 0x200 -+#define CCTRL_RESET_CHA_SF9A 0x400 -+#define CCTRL_RESET_CHA_ZUCE 0x800 -+#define CCTRL_RESET_CHA_ZUCA 0x1000 -+#define CCTRL_UNLOAD_PK_A0 0x10000 -+#define CCTRL_UNLOAD_PK_A1 0x20000 -+#define CCTRL_UNLOAD_PK_A2 0x40000 -+#define CCTRL_UNLOAD_PK_A3 0x80000 -+#define CCTRL_UNLOAD_PK_B0 0x100000 -+#define CCTRL_UNLOAD_PK_B1 0x200000 -+#define CCTRL_UNLOAD_PK_B2 0x400000 -+#define CCTRL_UNLOAD_PK_B3 0x800000 -+#define CCTRL_UNLOAD_PK_N 0x1000000 -+#define CCTRL_UNLOAD_PK_A 0x4000000 -+#define CCTRL_UNLOAD_PK_B 0x8000000 -+#define CCTRL_UNLOAD_SBOX 0x10000000 -+ - #endif /* DESC_H */ -diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h -index 62ce6421b..f98dec8f2 100644 ---- a/drivers/crypto/caam/desc_constr.h -+++ b/drivers/crypto/caam/desc_constr.h -@@ -240,6 +240,7 @@ static inline u32 *append_##cmd(u32 * const desc, u32 options) \ - APPEND_CMD_RET(jump, JUMP) - APPEND_CMD_RET(move, MOVE) - APPEND_CMD_RET(move_len, MOVE_LEN) -+APPEND_CMD_RET(moveb, MOVEB) - - static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd) - { -@@ -500,6 +501,8 @@ do { \ - * @key_virt: virtual address where algorithm key resides - * @key_inline: true - key can be inlined in the descriptor; false - key is - * referenced by the descriptor -+ * @key_real_len: size of the key to be loaded by the CAAM -+ * @key_cmd_opt: optional parameters for KEY command - */ - struct alginfo { - u32 algtype; -@@ -508,6 +511,8 @@ struct alginfo { - dma_addr_t key_dma; - const void *key_virt; - bool key_inline; -+ u32 key_real_len; -+ u32 key_cmd_opt; - }; - - /** -diff --git a/drivers/crypto/caam/dpseci.c b/drivers/crypto/caam/dpseci.c -index 039df6c57..23dbb87f7 100644 ---- a/drivers/crypto/caam/dpseci.c -+++ b/drivers/crypto/caam/dpseci.c -@@ -5,6 +5,7 @@ - */ - - #include -+#include - #include "dpseci.h" - #include "dpseci_cmd.h" - -@@ -16,8 +17,8 @@ - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an already created -- * object; an object may have been declared statically in the DPL -- * or created dynamically. -+ * object; an object may have been declared in the DPL or by calling the -+ * dpseci_create() function. - * This function returns a unique authentication token, associated with the - * specific object ID and the specific MC portal; this token must be used in all - * subsequent commands for this specific object. -@@ -66,6 +67,85 @@ int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) - return mc_send_command(mc_io, &cmd); - } - -+/** -+ * dpseci_create() - Create the DPSECI object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @dprc_token: Parent container token; '0' for default container -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @obj_id: returned object id -+ * -+ * Create the DPSECI object, allocate required resources and perform required -+ * initialization. -+ * -+ * The object can be created either by declaring it in the DPL file, or by -+ * calling this function. -+ * -+ * The function accepts an authentication token of a parent container that this -+ * object should be assigned to. The token can be '0' so the object will be -+ * assigned to the default container. -+ * The newly created object can be opened with the returned object id and using -+ * the container's associated tokens and MC portals. -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, -+ const struct dpseci_cfg *cfg, u32 *obj_id) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_create *cmd_params; -+ int i, err; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE, -+ cmd_flags, -+ dprc_token); -+ cmd_params = (struct dpseci_cmd_create *)cmd.params; -+ for (i = 0; i < 8; i++) -+ cmd_params->priorities[i] = cfg->priorities[i]; -+ for (i = 0; i < 8; i++) -+ cmd_params->priorities2[i] = cfg->priorities[8 + i]; -+ cmd_params->num_tx_queues = cfg->num_tx_queues; -+ cmd_params->num_rx_queues = cfg->num_rx_queues; -+ cmd_params->options = cpu_to_le32(cfg->options); -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ *obj_id = mc_cmd_read_object_id(&cmd); -+ -+ return 0; -+} -+ -+/** -+ * dpseci_destroy() - Destroy the DPSECI object and release all its resources -+ * @mc_io: Pointer to MC portal's I/O object -+ * @dprc_token: Parent container token; '0' for default container -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @object_id: The object id; it must be a valid id within the container that -+ * created this object -+ * -+ * The function accepts the authentication token of the parent container that -+ * created the object (not the one that currently owns the object). The object -+ * is searched within parent using the provided 'object_id'. -+ * All tokens to the object must be closed before calling destroy. -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, -+ u32 object_id) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_destroy *cmd_params; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY, -+ cmd_flags, -+ dprc_token); -+ cmd_params = (struct dpseci_cmd_destroy *)cmd.params; -+ cmd_params->object_id = cpu_to_le32(object_id); -+ -+ return mc_send_command(mc_io, &cmd); -+} -+ - /** - * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames - * @mc_io: Pointer to MC portal's I/O object -@@ -150,6 +230,198 @@ int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - return 0; - } - -+/** -+ * dpseci_get_irq_enable() - Get overall interrupt state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned Interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u8 *en) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_irq_enable *cmd_params; -+ struct dpseci_rsp_get_irq_enable *rsp_params; -+ int err; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params; -+ cmd_params->irq_index = irq_index; -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ rsp_params = (struct dpseci_rsp_get_irq_enable *)cmd.params; -+ *en = rsp_params->enable_state; -+ -+ return 0; -+} -+ -+/** -+ * dpseci_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. If the interrupt is disabled no causes will cause -+ * an interrupt. -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u8 en) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_irq_enable *cmd_params; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params; -+ cmd_params->irq_index = irq_index; -+ cmd_params->enable_state = en; -+ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+/** -+ * dpseci_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently. -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 *mask) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_irq_mask *cmd_params; -+ int err; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params; -+ cmd_params->irq_index = irq_index; -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ *mask = le32_to_cpu(cmd_params->mask); -+ -+ return 0; -+} -+ -+/** -+ * dpseci_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @irq_index: The interrupt index to configure -+ * @mask: event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 mask) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_irq_mask *cmd_params; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params; -+ cmd_params->mask = cpu_to_le32(mask); -+ cmd_params->irq_index = irq_index; -+ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+/** -+ * dpseci_get_irq_status() - Get the current status of any pending interrupts -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @irq_index: The interrupt index to configure -+ * @status: Returned interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 *status) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_irq_status *cmd_params; -+ int err; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_irq_status *)cmd.params; -+ cmd_params->status = cpu_to_le32(*status); -+ cmd_params->irq_index = irq_index; -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ *status = le32_to_cpu(cmd_params->status); -+ -+ return 0; -+} -+ -+/** -+ * dpseci_clear_irq_status() - Clear a pending interrupt's status -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @irq_index: The interrupt index to configure -+ * @status: bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 status) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_irq_status *cmd_params; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_irq_status *)cmd.params; -+ cmd_params->status = cpu_to_le32(status); -+ cmd_params->irq_index = irq_index; -+ -+ return mc_send_command(mc_io, &cmd); -+} -+ - /** - * dpseci_get_attributes() - Retrieve DPSECI attributes - * @mc_io: Pointer to MC portal's I/O object -@@ -339,6 +611,42 @@ int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - return 0; - } - -+/** -+ * dpseci_get_sec_counters() - Retrieve SEC accelerator counters -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @counters: Returned SEC counters -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ struct dpseci_sec_counters *counters) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_rsp_get_sec_counters *rsp_params; -+ int err; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS, -+ cmd_flags, -+ token); -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ rsp_params = (struct dpseci_rsp_get_sec_counters *)cmd.params; -+ counters->dequeued_requests = -+ le64_to_cpu(rsp_params->dequeued_requests); -+ counters->ob_enc_requests = le64_to_cpu(rsp_params->ob_enc_requests); -+ counters->ib_dec_requests = le64_to_cpu(rsp_params->ib_dec_requests); -+ counters->ob_enc_bytes = le64_to_cpu(rsp_params->ob_enc_bytes); -+ counters->ob_prot_bytes = le64_to_cpu(rsp_params->ob_prot_bytes); -+ counters->ib_dec_bytes = le64_to_cpu(rsp_params->ib_dec_bytes); -+ counters->ib_valid_bytes = le64_to_cpu(rsp_params->ib_valid_bytes); -+ -+ return 0; -+} -+ - /** - * dpseci_get_api_version() - Get Data Path SEC Interface API version - * @mc_io: Pointer to MC portal's I/O object -@@ -368,6 +676,90 @@ int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, - return 0; - } - -+/** -+ * dpseci_set_opr() - Set Order Restoration configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @index: The queue index -+ * @options: Configuration mode options; can be OPR_OPT_CREATE or -+ * OPR_OPT_RETIRE -+ * @cfg: Configuration options for the OPR -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, -+ u8 options, struct opr_cfg *cfg) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_opr *cmd_params; -+ -+ cmd.header = mc_encode_cmd_header( -+ DPSECI_CMDID_SET_OPR, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_opr *)cmd.params; -+ cmd_params->index = index; -+ cmd_params->options = options; -+ cmd_params->oloe = cfg->oloe; -+ cmd_params->oeane = cfg->oeane; -+ cmd_params->olws = cfg->olws; -+ cmd_params->oa = cfg->oa; -+ cmd_params->oprrws = cfg->oprrws; -+ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+/** -+ * dpseci_get_opr() - Retrieve Order Restoration config and query -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSECI object -+ * @index: The queue index -+ * @cfg: Returned OPR configuration -+ * @qry: Returned OPR query -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, -+ struct opr_cfg *cfg, struct opr_qry *qry) -+{ -+ struct fsl_mc_command cmd = { 0 }; -+ struct dpseci_cmd_opr *cmd_params; -+ struct dpseci_rsp_get_opr *rsp_params; -+ int err; -+ -+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR, -+ cmd_flags, -+ token); -+ cmd_params = (struct dpseci_cmd_opr *)cmd.params; -+ cmd_params->index = index; -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ rsp_params = (struct dpseci_rsp_get_opr *)cmd.params; -+ qry->rip = dpseci_get_field(rsp_params->flags, OPR_RIP); -+ qry->enable = dpseci_get_field(rsp_params->flags, OPR_ENABLE); -+ cfg->oloe = rsp_params->oloe; -+ cfg->oeane = rsp_params->oeane; -+ cfg->olws = rsp_params->olws; -+ cfg->oa = rsp_params->oa; -+ cfg->oprrws = rsp_params->oprrws; -+ qry->nesn = le16_to_cpu(rsp_params->nesn); -+ qry->ndsn = le16_to_cpu(rsp_params->ndsn); -+ qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq); -+ qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_TSEQ_NLIS); -+ qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq); -+ qry->hseq_nlis = dpseci_get_field(rsp_params->hseq_nlis, OPR_HSEQ_NLIS); -+ qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr); -+ qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr); -+ qry->opr_vid = le16_to_cpu(rsp_params->opr_vid); -+ qry->opr_id = le16_to_cpu(rsp_params->opr_id); -+ -+ return 0; -+} -+ - /** - * dpseci_set_congestion_notification() - Set congestion group - * notification configuration -diff --git a/drivers/crypto/caam/dpseci.h b/drivers/crypto/caam/dpseci.h -index 6dcd9be81..d453baac7 100644 ---- a/drivers/crypto/caam/dpseci.h -+++ b/drivers/crypto/caam/dpseci.h -@@ -12,6 +12,8 @@ - */ - - struct fsl_mc_io; -+struct opr_cfg; -+struct opr_qry; - - /** - * General DPSECI macros -@@ -37,10 +39,22 @@ int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); - */ - #define DPSECI_OPT_HAS_CG 0x000020 - -+/** -+ * Enable the Order Restoration support -+ */ -+#define DPSECI_OPT_HAS_OPR 0x000040 -+ -+/** -+ * Order Point Records are shared for the entire DPSECI -+ */ -+#define DPSECI_OPT_OPR_SHARED 0x000080 -+ - /** - * struct dpseci_cfg - Structure representing DPSECI configuration -- * @options: Any combination of the following flags: -+ * @options: Any combination of the following options: - * DPSECI_OPT_HAS_CG -+ * DPSECI_OPT_HAS_OPR -+ * DPSECI_OPT_OPR_SHARED - * @num_tx_queues: num of queues towards the SEC - * @num_rx_queues: num of queues back from the SEC - * @priorities: Priorities for the SEC hardware processing; -@@ -55,6 +69,12 @@ struct dpseci_cfg { - u8 priorities[DPSECI_MAX_QUEUE_NUM]; - }; - -+int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, -+ const struct dpseci_cfg *cfg, u32 *obj_id); -+ -+int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, -+ u32 object_id); -+ - int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); - - int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -@@ -64,13 +84,33 @@ int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); - int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - int *en); - -+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u8 *en); -+ -+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u8 en); -+ -+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 *mask); -+ -+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 mask); -+ -+int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 *status); -+ -+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ u8 irq_index, u32 status); -+ - /** - * struct dpseci_attr - Structure representing DPSECI attributes - * @id: DPSECI object ID - * @num_tx_queues: number of queues towards the SEC - * @num_rx_queues: number of queues back from the SEC -- * @options: any combination of the following flags: -+ * @options: any combination of the following options: - * DPSECI_OPT_HAS_CG -+ * DPSECI_OPT_HAS_OPR -+ * DPSECI_OPT_OPR_SHARED - */ - struct dpseci_attr { - int id; -@@ -250,9 +290,39 @@ struct dpseci_sec_attr { - int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - struct dpseci_sec_attr *attr); - -+/** -+ * struct dpseci_sec_counters - Structure representing global SEC counters and -+ * not per dpseci counters -+ * @dequeued_requests: Number of Requests Dequeued -+ * @ob_enc_requests: Number of Outbound Encrypt Requests -+ * @ib_dec_requests: Number of Inbound Decrypt Requests -+ * @ob_enc_bytes: Number of Outbound Bytes Encrypted -+ * @ob_prot_bytes: Number of Outbound Bytes Protected -+ * @ib_dec_bytes: Number of Inbound Bytes Decrypted -+ * @ib_valid_bytes: Number of Inbound Bytes Validated -+ */ -+struct dpseci_sec_counters { -+ u64 dequeued_requests; -+ u64 ob_enc_requests; -+ u64 ib_dec_requests; -+ u64 ob_enc_bytes; -+ u64 ob_prot_bytes; -+ u64 ib_dec_bytes; -+ u64 ib_valid_bytes; -+}; -+ -+int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, -+ struct dpseci_sec_counters *counters); -+ - int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, - u16 *major_ver, u16 *minor_ver); - -+int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, -+ u8 options, struct opr_cfg *cfg); -+ -+int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, -+ struct opr_cfg *cfg, struct opr_qry *qry); -+ - /** - * enum dpseci_congestion_unit - DPSECI congestion units - * @DPSECI_CONGESTION_UNIT_BYTES: bytes units -diff --git a/drivers/crypto/caam/dpseci_cmd.h b/drivers/crypto/caam/dpseci_cmd.h -index 71a007c85..9fec1c92e 100644 ---- a/drivers/crypto/caam/dpseci_cmd.h -+++ b/drivers/crypto/caam/dpseci_cmd.h -@@ -17,6 +17,7 @@ - /* Command versioning */ - #define DPSECI_CMD_BASE_VERSION 1 - #define DPSECI_CMD_BASE_VERSION_V2 2 -+#define DPSECI_CMD_BASE_VERSION_V3 3 - #define DPSECI_CMD_ID_OFFSET 4 - - #define DPSECI_CMD_V1(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ -@@ -25,9 +26,14 @@ - #define DPSECI_CMD_V2(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ - DPSECI_CMD_BASE_VERSION_V2) - -+#define DPSECI_CMD_V3(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ -+ DPSECI_CMD_BASE_VERSION_V3) -+ - /* Command IDs */ - #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800) - #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809) -+#define DPSECI_CMDID_CREATE DPSECI_CMD_V3(0x909) -+#define DPSECI_CMDID_DESTROY DPSECI_CMD_V1(0x989) - #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09) - - #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002) -@@ -36,10 +42,20 @@ - #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005) - #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006) - -+#define DPSECI_CMDID_SET_IRQ_ENABLE DPSECI_CMD_V1(0x012) -+#define DPSECI_CMDID_GET_IRQ_ENABLE DPSECI_CMD_V1(0x013) -+#define DPSECI_CMDID_SET_IRQ_MASK DPSECI_CMD_V1(0x014) -+#define DPSECI_CMDID_GET_IRQ_MASK DPSECI_CMD_V1(0x015) -+#define DPSECI_CMDID_GET_IRQ_STATUS DPSECI_CMD_V1(0x016) -+#define DPSECI_CMDID_CLEAR_IRQ_STATUS DPSECI_CMD_V1(0x017) -+ - #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194) - #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196) - #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197) - #define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198) -+#define DPSECI_CMDID_GET_SEC_COUNTERS DPSECI_CMD_V1(0x199) -+#define DPSECI_CMDID_SET_OPR DPSECI_CMD_V1(0x19A) -+#define DPSECI_CMDID_GET_OPR DPSECI_CMD_V1(0x19B) - #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170) - #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171) - -@@ -58,6 +74,20 @@ struct dpseci_cmd_open { - __le32 dpseci_id; - }; - -+struct dpseci_cmd_create { -+ u8 priorities[8]; -+ u8 num_tx_queues; -+ u8 num_rx_queues; -+ u8 pad0[6]; -+ __le32 options; -+ __le32 pad1; -+ u8 priorities2[8]; -+}; -+ -+struct dpseci_cmd_destroy { -+ __le32 object_id; -+}; -+ - #define DPSECI_ENABLE_SHIFT 0 - #define DPSECI_ENABLE_SIZE 1 - -@@ -65,6 +95,26 @@ struct dpseci_rsp_is_enabled { - u8 is_enabled; - }; - -+struct dpseci_cmd_irq_enable { -+ u8 enable_state; -+ u8 pad[3]; -+ u8 irq_index; -+}; -+ -+struct dpseci_rsp_get_irq_enable { -+ u8 enable_state; -+}; -+ -+struct dpseci_cmd_irq_mask { -+ __le32 mask; -+ u8 irq_index; -+}; -+ -+struct dpseci_cmd_irq_status { -+ __le32 status; -+ u8 irq_index; -+}; -+ - struct dpseci_rsp_get_attributes { - __le32 id; - __le32 pad0; -@@ -126,11 +176,70 @@ struct dpseci_rsp_get_sec_attr { - u8 ptha_acc_num; - }; - -+struct dpseci_rsp_get_sec_counters { -+ __le64 dequeued_requests; -+ __le64 ob_enc_requests; -+ __le64 ib_dec_requests; -+ __le64 ob_enc_bytes; -+ __le64 ob_prot_bytes; -+ __le64 ib_dec_bytes; -+ __le64 ib_valid_bytes; -+}; -+ - struct dpseci_rsp_get_api_version { - __le16 major; - __le16 minor; - }; - -+struct dpseci_cmd_opr { -+ __le16 pad; -+ u8 index; -+ u8 options; -+ u8 pad1[7]; -+ u8 oloe; -+ u8 oeane; -+ u8 olws; -+ u8 oa; -+ u8 oprrws; -+}; -+ -+#define DPSECI_OPR_RIP_SHIFT 0 -+#define DPSECI_OPR_RIP_SIZE 1 -+#define DPSECI_OPR_ENABLE_SHIFT 1 -+#define DPSECI_OPR_ENABLE_SIZE 1 -+#define DPSECI_OPR_TSEQ_NLIS_SHIFT 0 -+#define DPSECI_OPR_TSEQ_NLIS_SIZE 1 -+#define DPSECI_OPR_HSEQ_NLIS_SHIFT 0 -+#define DPSECI_OPR_HSEQ_NLIS_SIZE 1 -+ -+struct dpseci_rsp_get_opr { -+ __le64 pad; -+ u8 flags; -+ u8 pad0[2]; -+ u8 oloe; -+ u8 oeane; -+ u8 olws; -+ u8 oa; -+ u8 oprrws; -+ __le16 nesn; -+ __le16 pad1; -+ __le16 ndsn; -+ __le16 pad2; -+ __le16 ea_tseq; -+ u8 tseq_nlis; -+ u8 pad3; -+ __le16 ea_hseq; -+ u8 hseq_nlis; -+ u8 pad4; -+ __le16 ea_hptr; -+ __le16 pad5; -+ __le16 ea_tptr; -+ __le16 pad6; -+ __le16 opr_vid; -+ __le16 pad7; -+ __le16 opr_id; -+}; -+ - #define DPSECI_CGN_DEST_TYPE_SHIFT 0 - #define DPSECI_CGN_DEST_TYPE_SIZE 4 - #define DPSECI_CGN_UNITS_SHIFT 4 -diff --git a/drivers/crypto/caam/fsl_jr_uio.c b/drivers/crypto/caam/fsl_jr_uio.c -new file mode 100644 -index 000000000..2d3a0554a ---- /dev/null -+++ b/drivers/crypto/caam/fsl_jr_uio.c -@@ -0,0 +1,245 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright 2013 Freescale Semiconductor, Inc. -+ * Copyright 2018 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "regs.h" -+#include "fsl_jr_uio.h" -+ -+static const char jr_uio_version[] = "fsl JR UIO driver v1.0"; -+ -+#define NAME_LENGTH 30 -+#define JR_INDEX_OFFSET 12 -+ -+static const char uio_device_name[] = "fsl-jr"; -+static LIST_HEAD(jr_list); -+ -+struct jr_uio_info { -+ atomic_t ref; /* exclusive, only one open() at a time */ -+ struct uio_info uio; -+ char name[NAME_LENGTH]; -+}; -+ -+struct jr_dev { -+ u32 revision; -+ u32 index; -+ u32 irq; -+ struct caam_job_ring __iomem *global_regs; -+ struct device *dev; -+ struct resource *res; -+ struct jr_uio_info info; -+ struct list_head node; -+ struct list_head jr_list; -+}; -+ -+static int jr_uio_open(struct uio_info *info, struct inode *inode) -+{ -+ struct jr_uio_info *uio_info = container_of(info, -+ struct jr_uio_info, uio); -+ -+ if (!atomic_dec_and_test(&uio_info->ref)) { -+ pr_err("%s: failing non-exclusive open()\n", uio_info->name); -+ atomic_inc(&uio_info->ref); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static int jr_uio_release(struct uio_info *info, struct inode *inode) -+{ -+ struct jr_uio_info *uio_info = container_of(info, -+ struct jr_uio_info, uio); -+ atomic_inc(&uio_info->ref); -+ -+ return 0; -+} -+ -+static irqreturn_t jr_uio_irq_handler(int irq, struct uio_info *dev_info) -+{ -+ struct jr_dev *jrdev = dev_info->priv; -+ u32 irqstate; -+ -+ irqstate = rd_reg32(&jrdev->global_regs->jrintstatus); -+ -+ if (!irqstate) -+ return IRQ_NONE; -+ -+ if (irqstate & JRINT_JR_ERROR) -+ dev_info(jrdev->dev, "uio job ring error - irqstate: %08x\n", -+ irqstate); -+ -+ /*mask valid interrupts */ -+ clrsetbits_32(&jrdev->global_regs->rconfig_lo, 0, JRCFG_IMSK); -+ -+ /* Have valid interrupt at this point, just ACK and trigger */ -+ wr_reg32(&jrdev->global_regs->jrintstatus, irqstate); -+ -+ return IRQ_HANDLED; -+} -+ -+static int jr_uio_irqcontrol(struct uio_info *dev_info, int irqon) -+{ -+ struct jr_dev *jrdev = dev_info->priv; -+ -+ switch (irqon) { -+ case SEC_UIO_SIMULATE_IRQ_CMD: -+ uio_event_notify(dev_info); -+ break; -+ case SEC_UIO_ENABLE_IRQ_CMD: -+ /* Enable Job Ring interrupt */ -+ clrsetbits_32(&jrdev->global_regs->rconfig_lo, JRCFG_IMSK, 0); -+ break; -+ case SEC_UIO_DISABLE_IRQ_CMD: -+ /* Disable Job Ring interrupt */ -+ clrsetbits_32(&jrdev->global_regs->rconfig_lo, 0, JRCFG_IMSK); -+ break; -+ default: -+ break; -+ } -+ return 0; -+} -+ -+static int __init jr_uio_init(struct jr_dev *uio_dev) -+{ -+ int ret; -+ struct jr_uio_info *info; -+ -+ info = &uio_dev->info; -+ atomic_set(&info->ref, 1); -+ info->uio.version = jr_uio_version; -+ info->uio.name = uio_dev->info.name; -+ info->uio.mem[0].name = "JR config space"; -+ info->uio.mem[0].addr = uio_dev->res->start; -+ info->uio.mem[0].size = resource_size(uio_dev->res); -+ info->uio.mem[0].internal_addr = uio_dev->global_regs; -+ info->uio.mem[0].memtype = UIO_MEM_PHYS; -+ info->uio.irq = uio_dev->irq; -+ info->uio.irq_flags = IRQF_SHARED; -+ info->uio.handler = jr_uio_irq_handler; -+ info->uio.irqcontrol = jr_uio_irqcontrol; -+ info->uio.open = jr_uio_open; -+ info->uio.release = jr_uio_release; -+ info->uio.priv = uio_dev; -+ -+ ret = uio_register_device(uio_dev->dev, &info->uio); -+ if (ret) { -+ dev_err(uio_dev->dev, "jr_uio: UIO registration failed\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id jr_ids[] = { -+ { .compatible = "fsl,sec-v4.0-job-ring", }, -+ { .compatible = "fsl,sec-v4.4-job-ring", }, -+ { .compatible = "fsl,sec-v5.0-job-ring", }, -+ { .compatible = "fsl,sec-v6.0-job-ring", }, -+ {}, -+}; -+ -+static int fsl_jr_probe(struct platform_device *dev) -+{ -+ struct jr_dev *jr_dev; -+ struct device_node *jr_node; -+ int ret, count = 0; -+ struct list_head *p; -+ -+ jr_node = dev->dev.of_node; -+ if (!jr_node) { -+ dev_err(&dev->dev, "Device OF-Node is NULL\n"); -+ return -EFAULT; -+ } -+ -+ jr_dev = devm_kzalloc(&dev->dev, sizeof(*jr_dev), GFP_KERNEL); -+ if (!jr_dev) -+ return -ENOMEM; -+ -+ /* Creat name and index */ -+ list_for_each(p, &jr_list) { -+ count++; -+ } -+ jr_dev->index = count; -+ -+ snprintf(jr_dev->info.name, sizeof(jr_dev->info.name) - 1, -+ "%s%d", uio_device_name, jr_dev->index); -+ -+ jr_dev->dev = &dev->dev; -+ platform_set_drvdata(dev, jr_dev); -+ -+ jr_dev->res = platform_get_resource(dev, IORESOURCE_MEM, 0); -+ if (unlikely(!jr_dev->res)) { -+ dev_err(jr_dev->dev, "platform_get_resource() failed\n"); -+ ret = -ENOMEM; -+ goto abort; -+ } -+ -+ jr_dev->global_regs = -+ devm_ioremap(&dev->dev, jr_dev->res->start, -+ resource_size(jr_dev->res)); -+ if (unlikely(jr_dev->global_regs == 0)) { -+ dev_err(jr_dev->dev, "devm_ioremap failed\n"); -+ ret = -EIO; -+ goto abort; -+ } -+ jr_dev->irq = irq_of_parse_and_map(jr_node, 0); -+ dev_dbg(jr_dev->dev, "errirq: %d\n", jr_dev->irq); -+ -+ /* Register UIO */ -+ ret = jr_uio_init(jr_dev); -+ if (ret) { -+ dev_err(&dev->dev, "UIO init Failed\n"); -+ goto abort; -+ } -+ -+ list_add_tail(&jr_dev->node, &jr_list); -+ -+ dev_info(jr_dev->dev, "UIO device full name %s initialized\n", -+ jr_dev->info.name); -+ -+ return 0; -+ -+abort: -+ return ret; -+} -+ -+static int fsl_jr_remove(struct platform_device *dev) -+{ -+ struct jr_dev *jr_dev = platform_get_drvdata(dev); -+ -+ if (!jr_dev) -+ return 0; -+ -+ list_del(&jr_dev->node); -+ uio_unregister_device(&jr_dev->info.uio); -+ -+ return 0; -+} -+ -+MODULE_DEVICE_TABLE(of, jr_ids); -+ -+static struct platform_driver fsl_jr_driver = { -+ .driver = { -+ .name = "fsl-jr-uio", -+ .of_match_table = jr_ids, -+ }, -+ .probe = fsl_jr_probe, -+ .remove = fsl_jr_remove, -+}; -+ -+module_platform_driver(fsl_jr_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("NXP"); -+MODULE_DESCRIPTION("FSL SEC UIO Driver"); -diff --git a/drivers/crypto/caam/fsl_jr_uio.h b/drivers/crypto/caam/fsl_jr_uio.h -new file mode 100644 -index 000000000..2956645e1 ---- /dev/null -+++ b/drivers/crypto/caam/fsl_jr_uio.h -@@ -0,0 +1,25 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * CAAM Job RING UIO support header file -+ * -+ * Copyright 2013 Freescale Semiconductor, Inc -+ * Copyright 2018 NXP -+ */ -+ -+#ifndef FSL_JR_UIO_H -+#define FSL_JR_UIO_H -+ -+/** UIO command used by user-space driver to request -+ * disabling IRQs on a certain job ring -+ */ -+#define SEC_UIO_DISABLE_IRQ_CMD 0 -+/** UIO command used by user-space driver to request -+ * enabling IRQs on a certain job ring -+ */ -+#define SEC_UIO_ENABLE_IRQ_CMD 1 -+/** UIO command used by user-space driver to request SEC kernel driver -+ * to simulate that an IRQ is generated on a certain job ring -+ */ -+#define SEC_UIO_SIMULATE_IRQ_CMD 2 -+ -+#endif -diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h -index 9112279a4..ad83f3a83 100644 ---- a/drivers/crypto/caam/intern.h -+++ b/drivers/crypto/caam/intern.h -@@ -39,6 +39,18 @@ struct caam_jrentry_info { - u32 desc_size; /* Stored size for postprocessing, header derived */ - }; - -+#ifdef CONFIG_PM_SLEEP -+struct caam_jr_state { -+ dma_addr_t inpbusaddr; -+ dma_addr_t outbusaddr; -+}; -+#endif -+ -+struct caam_jr_dequeue_params { -+ struct device *dev; -+ int enable_itr; -+}; -+ - /* Private sub-storage for a single JobR */ - struct caam_drv_private_jr { - struct list_head list_node; /* Job Ring device list */ -@@ -46,6 +58,7 @@ struct caam_drv_private_jr { - int ridx; - struct caam_job_ring __iomem *rregs; /* JobR's register space */ - struct tasklet_struct irqtask; -+ struct caam_jr_dequeue_params tasklet_params; - int irq; /* One per queue */ - bool hwrng; - -@@ -63,18 +76,35 @@ struct caam_drv_private_jr { - int tail; /* entinfo (s/w ring) tail index */ - void *outring; /* Base of output ring, DMA-safe */ - struct crypto_engine *engine; -+ -+#ifdef CONFIG_PM_SLEEP -+ struct caam_jr_state state; /* State of the JR during PM */ -+#endif - }; - -+#ifdef CONFIG_PM_SLEEP -+struct caam_ctl_state { -+ struct masterid deco_mid[16]; -+ struct masterid jr_mid[4]; -+ u32 mcr; -+ u32 scfgr; -+}; -+#endif -+ - /* - * Driver-private storage for a single CAAM block instance - */ - struct caam_drv_private { -+ struct device *smdev; -+ - /* Physical-presence section */ - struct caam_ctrl __iomem *ctrl; /* controller region */ - struct caam_deco __iomem *deco; /* DECO/CCB views */ - struct caam_assurance __iomem *assure; - struct caam_queue_if __iomem *qi; /* QI control region */ - struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ -+ dma_addr_t __iomem *sm_base; /* Secure memory storage base */ -+ phys_addr_t sm_phy; /* Secure memory storage physical */ - - struct iommu_domain *domain; - -@@ -84,8 +114,11 @@ struct caam_drv_private { - */ - u8 total_jobrs; /* Total Job Rings in device */ - u8 qi_present; /* Nonzero if QI present in device */ -+ u8 sm_present; /* Nonzero if Secure Memory is supported */ - u8 mc_en; /* Nonzero if MC f/w is active */ -- int secvio_irq; /* Security violation interrupt number */ -+ u8 scu_en; /* Nonzero if SCU f/w is active */ -+ u8 optee_en; /* Nonzero if OP-TEE f/w is active */ -+ bool pr_support; /* RNG prediction resistance available */ - int virt_en; /* Virtualization enabled in CAAM */ - int era; /* CAAM Era (internal HW revision) */ - -@@ -105,6 +138,11 @@ struct caam_drv_private { - struct dentry *ctl; /* controller dir */ - struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap; - #endif -+ -+#ifdef CONFIG_PM_SLEEP -+ int caam_off_during_pm; /* If the CAAM is reset after suspend */ -+ struct caam_ctl_state state; /* State of the CTL during PM */ -+#endif - }; - - #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API -@@ -195,6 +233,42 @@ static inline void caam_qi_algapi_exit(void) - - #endif /* CONFIG_CAAM_QI */ - -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_SM -+ -+int caam_sm_startup(struct device *dev); -+void caam_sm_shutdown(struct device *dev); -+ -+#else -+ -+static inline int caam_sm_startup(struct device *dev) -+{ -+ return 0; -+} -+ -+static inline void caam_sm_shutdown(struct device *dev) -+{ -+} -+ -+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_SM */ -+ -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API -+ -+int caam_keygen_init(void); -+void caam_keygen_exit(void); -+ -+#else -+ -+static inline int caam_keygen_init(void) -+{ -+ return 0; -+} -+ -+static inline void caam_keygen_exit(void) -+{ -+} -+ -+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ -+ - static inline u64 caam_get_dma_mask(struct device *dev) - { - struct device_node *nprop = dev->of_node; -diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c -index 6f669966b..1572d31c9 100644 ---- a/drivers/crypto/caam/jr.c -+++ b/drivers/crypto/caam/jr.c -@@ -4,7 +4,7 @@ - * JobR backend functionality - * - * Copyright 2008-2012 Freescale Semiconductor, Inc. -- * Copyright 2019 NXP -+ * Copyright 2019-2020 NXP - */ - - #include -@@ -27,8 +27,40 @@ static struct jr_driver_data driver_data; - static DEFINE_MUTEX(algs_lock); - static unsigned int active_devs; - --static void register_algs(struct caam_drv_private_jr *jrpriv, -- struct device *dev) -+static void init_misc_func(struct caam_drv_private_jr *jrpriv, -+ struct device *dev) -+{ -+ mutex_lock(&algs_lock); -+ -+ if (active_devs != 1) -+ goto algs_unlock; -+ -+ jrpriv->hwrng = !caam_rng_init(dev); -+ caam_sm_startup(dev); -+ caam_keygen_init(); -+ -+algs_unlock: -+ mutex_unlock(&algs_lock); -+} -+ -+static void exit_misc_func(struct caam_drv_private_jr *jrpriv, -+ struct device *dev) -+{ -+ mutex_lock(&algs_lock); -+ -+ if (active_devs != 1) -+ goto algs_unlock; -+ -+ caam_keygen_exit(); -+ caam_sm_shutdown(dev); -+ if (jrpriv->hwrng) -+ caam_rng_exit(dev); -+ -+algs_unlock: -+ mutex_unlock(&algs_lock); -+} -+ -+static void register_algs(struct device *dev) - { - mutex_lock(&algs_lock); - -@@ -38,14 +70,13 @@ static void register_algs(struct caam_drv_private_jr *jrpriv, - caam_algapi_init(dev); - caam_algapi_hash_init(dev); - caam_pkc_init(dev); -- jrpriv->hwrng = !caam_rng_init(dev); - caam_qi_algapi_init(dev); - - algs_unlock: - mutex_unlock(&algs_lock); - } - --static void unregister_algs(void) -+static void unregister_algs(struct device *dev) - { - mutex_lock(&algs_lock); - -@@ -62,6 +93,14 @@ static void unregister_algs(void) - mutex_unlock(&algs_lock); - } - -+static int jr_driver_probed; -+ -+int caam_jr_driver_probed(void) -+{ -+ return jr_driver_probed; -+} -+EXPORT_SYMBOL(caam_jr_driver_probed); -+ - static void caam_jr_crypto_engine_exit(void *data) - { - struct device *jrdev = data; -@@ -71,19 +110,27 @@ static void caam_jr_crypto_engine_exit(void *data) - crypto_engine_exit(jrpriv->engine); - } - --static int caam_reset_hw_jr(struct device *dev) -+/* -+ * Put the CAAM in quiesce, ie stop -+ * -+ * Must be called with itr disabled -+ */ -+static int caam_jr_stop_processing(struct device *dev, u32 jrcr_bits) - { - struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); - unsigned int timeout = 100000; - -- /* -- * mask interrupts since we are going to poll -- * for reset completion status -- */ -- clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK); -+ /* Check the current status */ -+ if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS) -+ goto wait_quiesce_completion; - -- /* initiate flush (required prior to reset) */ -- wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); -+ /* Reset the field */ -+ clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0); -+ -+ /* initiate flush / park (required prior to reset) */ -+ wr_reg32(&jrp->rregs->jrcommand, jrcr_bits); -+ -+wait_quiesce_completion: - while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == - JRINT_ERR_HALT_INPROGRESS) && --timeout) - cpu_relax(); -@@ -94,8 +141,56 @@ static int caam_reset_hw_jr(struct device *dev) - return -EIO; - } - -+ return 0; -+} -+ -+/* -+ * Flush the job ring, so the jobs running will be stopped, jobs queued will be -+ * invalidated and the CAAM will no longer fetch fron input ring. -+ * -+ * Must be called with itr disabled -+ */ -+static int caam_jr_flush(struct device *dev) -+{ -+ return caam_jr_stop_processing(dev, JRCR_RESET); -+} -+ -+#ifdef CONFIG_PM_SLEEP -+/* The resume can be used after a park or a flush if CAAM has not been reset */ -+static int caam_jr_restart_processing(struct device *dev) -+{ -+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -+ u32 halt_status = rd_reg32(&jrp->rregs->jrintstatus) & -+ JRINT_ERR_HALT_MASK; -+ -+ /* Check that the flush/park is completed */ -+ if (halt_status != JRINT_ERR_HALT_COMPLETE) -+ return -1; -+ -+ /* Resume processing of jobs */ -+ clrsetbits_32(&jrp->rregs->jrintstatus, 0, JRINT_ERR_HALT_COMPLETE); -+ -+ return 0; -+} -+#endif /* CONFIG_PM_SLEEP */ -+ -+static int caam_reset_hw_jr(struct device *dev) -+{ -+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -+ unsigned int timeout = 100000; -+ int err; -+ -+ /* -+ * mask interrupts since we are going to poll -+ * for reset completion status -+ */ -+ clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK); -+ -+ err = caam_jr_flush(dev); -+ if (err) -+ return err; -+ - /* initiate reset */ -- timeout = 100000; - wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); - while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) - cpu_relax(); -@@ -135,8 +230,7 @@ static int caam_jr_remove(struct platform_device *pdev) - jrdev = &pdev->dev; - jrpriv = dev_get_drvdata(jrdev); - -- if (jrpriv->hwrng) -- caam_rng_exit(jrdev->parent); -+ exit_misc_func(jrpriv, jrdev->parent); - - /* - * Return EBUSY if job ring already allocated. -@@ -147,7 +241,7 @@ static int caam_jr_remove(struct platform_device *pdev) - } - - /* Unregister JR-based RNG & crypto algorithms */ -- unregister_algs(); -+ unregister_algs(jrdev->parent); - - /* Remove the node from Physical JobR list maintained by driver */ - spin_lock(&driver_data.jr_alloc_lock); -@@ -159,6 +253,8 @@ static int caam_jr_remove(struct platform_device *pdev) - if (ret) - dev_err(jrdev, "Failed to shut down job ring\n"); - -+ jr_driver_probed--; -+ - return ret; - } - -@@ -174,7 +270,7 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) - * tasklet if jobs done. - */ - irqstate = rd_reg32(&jrp->rregs->jrintstatus); -- if (!irqstate) -+ if (!(irqstate & JRINT_JR_INT)) - return IRQ_NONE; - - /* -@@ -204,7 +300,8 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) - static void caam_jr_dequeue(unsigned long devarg) - { - int hw_idx, sw_idx, i, head, tail; -- struct device *dev = (struct device *)devarg; -+ struct caam_jr_dequeue_params *params = (void *)devarg; -+ struct device *dev = params->dev; - struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); - void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg); - u32 *userdesc, userstatus; -@@ -278,8 +375,9 @@ static void caam_jr_dequeue(unsigned long devarg) - outring_used--; - } - -- /* reenable / unmask IRQs */ -- clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); -+ if (params->enable_itr) -+ /* reenable / unmask IRQs */ -+ clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); - } - - /** -@@ -322,6 +420,36 @@ struct device *caam_jr_alloc(void) - } - EXPORT_SYMBOL(caam_jr_alloc); - -+/** -+ * caam_jridx_alloc() - Alloc a specific job ring based on its index. -+ * -+ * returns : pointer to the newly allocated physical -+ * JobR dev can be written to if successful. -+ **/ -+struct device *caam_jridx_alloc(int idx) -+{ -+ struct caam_drv_private_jr *jrpriv; -+ struct device *dev = ERR_PTR(-ENODEV); -+ -+ spin_lock(&driver_data.jr_alloc_lock); -+ -+ if (list_empty(&driver_data.jr_list)) -+ goto end; -+ -+ list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) { -+ if (jrpriv->ridx == idx) { -+ atomic_inc(&jrpriv->tfm_count); -+ dev = jrpriv->dev; -+ break; -+ } -+ } -+ -+end: -+ spin_unlock(&driver_data.jr_alloc_lock); -+ return dev; -+} -+EXPORT_SYMBOL(caam_jridx_alloc); -+ - /** - * caam_jr_free() - Free the Job Ring - * @rdev: points to the dev that identifies the Job ring to -@@ -404,8 +532,16 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, - * Guarantee that the descriptor's DMA address has been written to - * the next slot in the ring before the write index is updated, since - * other cores may update this index independently. -+ * -+ * Under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input -+ * ring be updated before the CAAM starts reading it. So, CAAM will -+ * process, again, an old descriptor address and will put it in the -+ * output ring. This will make caam_jr_dequeue() to fail, since this -+ * old descriptor is not in the software ring. -+ * To fix this, use wmb() which works on the full system instead of -+ * inner/outer shareable domains. - */ -- smp_wmb(); -+ wmb(); - - jrp->head = (head + 1) & (JOBR_DEPTH - 1); - -@@ -429,6 +565,80 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, - } - EXPORT_SYMBOL(caam_jr_enqueue); - -+/** -+ * caam_jr_run_and_wait_for_completion() - Enqueue a job and wait for its -+ * completion. Returns 0 if OK, -ENOSPC if the queue is full, -+ * -EIO if it cannot map the caller's descriptor. -+ * @dev: struct device of the job ring to be used -+ * @desc: points to a job descriptor that execute our request. All -+ * descriptors (and all referenced data) must be in a DMAable -+ * region, and all data references must be physical addresses -+ * accessible to CAAM (i.e. within a PAMU window granted -+ * to it). -+ * @cbk: pointer to a callback function to be invoked upon completion -+ * of this request. This has the form: -+ * callback(struct device *dev, u32 *desc, u32 stat, void *arg) -+ * where: -+ * @dev: contains the job ring device that processed this -+ * response. -+ * @desc: descriptor that initiated the request, same as -+ * "desc" being argued to caam_jr_enqueue(). -+ * @status: untranslated status received from CAAM. See the -+ * reference manual for a detailed description of -+ * error meaning, or see the JRSTA definitions in the -+ * register header file -+ * @areq: optional pointer to an argument passed with the -+ * original request -+ **/ -+int caam_jr_run_and_wait_for_completion(struct device *dev, u32 *desc, -+ void (*cbk)(struct device *dev, -+ u32 *desc, u32 status, -+ void *areq)) -+{ -+ int ret = 0; -+ struct jr_job_result jobres = {0}; -+ -+ /* Initialize the completion structure */ -+ init_completion(&jobres.completion); -+ -+ /* Enqueue job for execution */ -+ ret = caam_jr_enqueue(dev, desc, cbk, &jobres); -+ if (ret != -EINPROGRESS) -+ return ret; -+ -+ /* Wait for job completion */ -+ wait_for_completion(&jobres.completion); -+ -+ /* Get return code processed in cbk */ -+ ret = jobres.error; -+ -+ return ret; -+} -+EXPORT_SYMBOL(caam_jr_run_and_wait_for_completion); -+ -+static void caam_jr_init_hw(struct device *dev, dma_addr_t inpbusaddr, -+ dma_addr_t outbusaddr) -+{ -+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -+ -+ wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); -+ wr_reg64(&jrp->rregs->outring_base, outbusaddr); -+ wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); -+ wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); -+ -+ /* Select interrupt coalescing parameters */ -+ clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC | -+ (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | -+ (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); -+} -+ -+static void caam_jr_reset_index(struct caam_drv_private_jr *jrp) -+{ -+ jrp->out_ring_read_index = 0; -+ jrp->head = 0; -+ jrp->tail = 0; -+} -+ - /* - * Init JobR independent of platform property detection - */ -@@ -465,25 +675,16 @@ static int caam_jr_init(struct device *dev) - jrp->entinfo[i].desc_addr_dma = !0; - - /* Setup rings */ -- jrp->out_ring_read_index = 0; -- jrp->head = 0; -- jrp->tail = 0; -- -- wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); -- wr_reg64(&jrp->rregs->outring_base, outbusaddr); -- wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); -- wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); -- -+ caam_jr_reset_index(jrp); - jrp->inpring_avail = JOBR_DEPTH; -+ caam_jr_init_hw(dev, inpbusaddr, outbusaddr); - - spin_lock_init(&jrp->inplock); - -- /* Select interrupt coalescing parameters */ -- clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC | -- (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | -- (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); -- -- tasklet_init(&jrp->irqtask, caam_jr_dequeue, (unsigned long)dev); -+ jrp->tasklet_params.dev = dev; -+ jrp->tasklet_params.enable_itr = 1; -+ tasklet_init(&jrp->irqtask, caam_jr_dequeue, -+ (unsigned long)&jrp->tasklet_params); - - /* Connect job ring interrupt handler. */ - error = devm_request_irq(dev, jrp->irq, caam_jr_interrupt, IRQF_SHARED, -@@ -592,11 +793,138 @@ static int caam_jr_probe(struct platform_device *pdev) - - atomic_set(&jrpriv->tfm_count, 0); - -- register_algs(jrpriv, jrdev->parent); -+ device_init_wakeup(&pdev->dev, 1); -+ device_set_wakeup_enable(&pdev->dev, false); -+ -+ register_algs(jrdev->parent); -+ init_misc_func(jrpriv, jrdev->parent); -+ jr_driver_probed++; - - return 0; - } - -+#ifdef CONFIG_PM_SLEEP -+static void caam_jr_get_hw_state(struct device *dev) -+{ -+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -+ -+ jrp->state.inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); -+ jrp->state.outbusaddr = rd_reg64(&jrp->rregs->outring_base); -+} -+ -+static int caam_jr_suspend(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent); -+ struct caam_jr_dequeue_params suspend_params = { -+ .dev = dev, -+ .enable_itr = 0, -+ }; -+ -+ /* Remove the node from Physical JobR list maintained by driver */ -+ spin_lock(&driver_data.jr_alloc_lock); -+ list_del(&jrpriv->list_node); -+ spin_unlock(&driver_data.jr_alloc_lock); -+ -+ if (jrpriv->hwrng) -+ caam_rng_exit(dev->parent); -+ -+ if (ctrlpriv->caam_off_during_pm) { -+ int err; -+ -+ tasklet_disable(&jrpriv->irqtask); -+ -+ /* mask itr to call flush */ -+ clrsetbits_32(&jrpriv->rregs->rconfig_lo, 0, JRCFG_IMSK); -+ -+ /* Invalid job in process */ -+ err = caam_jr_flush(dev); -+ if (err) { -+ dev_err(dev, "Failed to flush\n"); -+ return err; -+ } -+ -+ /* Dequeing jobs flushed */ -+ caam_jr_dequeue((unsigned long)&suspend_params); -+ -+ /* Save state */ -+ caam_jr_get_hw_state(dev); -+ } else if (device_may_wakeup(&pdev->dev)) { -+ enable_irq_wake(jrpriv->irq); -+ } -+ -+ return 0; -+} -+ -+static int caam_jr_resume(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent); -+ -+ if (ctrlpriv->caam_off_during_pm) { -+ u64 inp_addr; -+ int err; -+ -+ /* -+ * Check if the CAAM has been resetted checking the address of -+ * the input ring -+ */ -+ inp_addr = rd_reg64(&jrpriv->rregs->inpring_base); -+ if (inp_addr != 0) { -+ /* JR still has some configuration */ -+ if (inp_addr == jrpriv->state.inpbusaddr) { -+ /* JR has not been resetted */ -+ err = caam_jr_restart_processing(dev); -+ if (err) { -+ dev_err(dev, -+ "Restart processing failed\n"); -+ return err; -+ } -+ -+ tasklet_enable(&jrpriv->irqtask); -+ -+ clrsetbits_32(&jrpriv->rregs->rconfig_lo, -+ JRCFG_IMSK, 0); -+ -+ goto add_jr; -+ } else if (ctrlpriv->optee_en) { -+ /* JR has been used by OPTEE, reset it */ -+ err = caam_reset_hw_jr(dev); -+ if (err) { -+ dev_err(dev, "Failed to reset JR\n"); -+ return err; -+ } -+ } else { -+ /* No explanation, return error */ -+ return -EIO; -+ } -+ } -+ -+ caam_jr_reset_index(jrpriv); -+ caam_jr_init_hw(dev, jrpriv->state.inpbusaddr, -+ jrpriv->state.outbusaddr); -+ -+ tasklet_enable(&jrpriv->irqtask); -+ } else if (device_may_wakeup(&pdev->dev)) { -+ disable_irq_wake(jrpriv->irq); -+ } -+ -+add_jr: -+ spin_lock(&driver_data.jr_alloc_lock); -+ list_add_tail(&jrpriv->list_node, &driver_data.jr_list); -+ spin_unlock(&driver_data.jr_alloc_lock); -+ -+ if (jrpriv->hwrng) -+ jrpriv->hwrng = !caam_rng_init(dev->parent); -+ -+ return 0; -+} -+ -+SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend, caam_jr_resume); -+#endif /* CONFIG_PM_SLEEP */ -+ - static const struct of_device_id caam_jr_match[] = { - { - .compatible = "fsl,sec-v4.0-job-ring", -@@ -612,6 +940,9 @@ static struct platform_driver caam_jr_driver = { - .driver = { - .name = "caam_jr", - .of_match_table = caam_jr_match, -+#ifdef CONFIG_PM_SLEEP -+ .pm = &caam_jr_pm_ops, -+#endif - }, - .probe = caam_jr_probe, - .remove = caam_jr_remove, -diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h -index eab611530..768df0a6a 100644 ---- a/drivers/crypto/caam/jr.h -+++ b/drivers/crypto/caam/jr.h -@@ -3,17 +3,38 @@ - * CAAM public-level include definitions for the JobR backend - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright 2020 NXP - */ - - #ifndef JR_H - #define JR_H - -+#include -+ -+ /** -+ * struct jr_job_result - Job Ring result structure, used for requests -+ * that need to run and wait for their completion -+ * -+ * @error : The result returned after request was executed -+ * @completion : Structure used to maintain state for a "completion" -+ */ -+struct jr_job_result { -+ int error; -+ struct completion completion; -+}; -+ - /* Prototypes for backend-level services exposed to APIs */ -+int caam_jr_driver_probed(void); - struct device *caam_jr_alloc(void); -+struct device *caam_jridx_alloc(int idx); - void caam_jr_free(struct device *rdev); - int caam_jr_enqueue(struct device *dev, u32 *desc, - void (*cbk)(struct device *dev, u32 *desc, u32 status, - void *areq), - void *areq); -+int caam_jr_run_and_wait_for_completion(struct device *dev, u32 *desc, -+ void (*cbk)(struct device *dev, -+ u32 *desc, u32 status, -+ void *areq)); - - #endif /* JR_H */ -diff --git a/drivers/crypto/caam/qi.c b/drivers/crypto/caam/qi.c -index ec53528d8..f0762c2e3 100644 ---- a/drivers/crypto/caam/qi.c -+++ b/drivers/crypto/caam/qi.c -@@ -9,7 +9,7 @@ - - #include - #include --#include -+#include - - #include "debugfs.h" - #include "regs.h" -@@ -99,23 +99,21 @@ static void *caam_iova_to_virt(struct iommu_domain *domain, - int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req) - { - struct qm_fd fd; -- dma_addr_t addr; - int ret; - int num_retries = 0; - -- qm_fd_clear_fd(&fd); -- qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1])); -- -- addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), -+ fd.cmd = 0; -+ fd.format = qm_fd_compound; -+ fd.cong_weight = caam32_to_cpu(req->fd_sgt[1].length); -+ fd.addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), - DMA_BIDIRECTIONAL); -- if (dma_mapping_error(qidev, addr)) { -+ if (dma_mapping_error(qidev, fd.addr)) { - dev_err(qidev, "DMA mapping error for QI enqueue request\n"); - return -EIO; - } -- qm_fd_addr_set64(&fd, addr); - - do { -- ret = qman_enqueue(req->drv_ctx->req_fq, &fd); -+ ret = qman_enqueue(req->drv_ctx->req_fq, &fd, 0); - if (likely(!ret)) { - refcount_inc(&req->drv_ctx->refcnt); - return 0; -@@ -133,7 +131,7 @@ int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req) - EXPORT_SYMBOL(caam_qi_enqueue); - - static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq, -- const union qm_mr_entry *msg) -+ const struct qm_mr_entry *msg) - { - const struct qm_fd *fd; - struct caam_drv_req *drv_req; -@@ -151,7 +149,7 @@ static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq, - - refcount_dec(&drv_req->drv_ctx->refcnt); - -- if (qm_fd_get_format(fd) != qm_fd_compound) { -+ if (fd->format != qm_fd_compound) { - dev_err(qidev, "Non-compound FD from CAAM\n"); - return; - } -@@ -182,20 +180,22 @@ static struct qman_fq *create_caam_req_fq(struct device *qidev, - req_fq->cb.fqs = NULL; - - ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | -- QMAN_FQ_FLAG_TO_DCPORTAL, req_fq); -+ QMAN_FQ_FLAG_TO_DCPORTAL | QMAN_FQ_FLAG_LOCKED, -+ req_fq); - if (ret) { - dev_err(qidev, "Failed to create session req FQ\n"); - goto create_req_fq_fail; - } - -- memset(&opts, 0, sizeof(opts)); -- opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | -- QM_INITFQ_WE_CONTEXTB | -- QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID); -- opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE); -- qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2); -- opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq)); -- qm_fqd_context_a_set64(&opts.fqd, hwdesc); -+ opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | -+ QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA | -+ QM_INITFQ_WE_CGID; -+ opts.fqd.fq_ctrl = QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE; -+ opts.fqd.dest.channel = qm_channel_caam; -+ opts.fqd.dest.wq = 2; -+ opts.fqd.context_b = qman_fq_fqid(rsp_fq); -+ opts.fqd.context_a.hi = upper_32_bits(hwdesc); -+ opts.fqd.context_a.lo = lower_32_bits(hwdesc); - opts.fqd.cgid = qipriv.cgr.cgrid; - - ret = qman_init_fq(req_fq, fq_sched_flag, &opts); -@@ -209,7 +209,7 @@ static struct qman_fq *create_caam_req_fq(struct device *qidev, - return req_fq; - - init_req_fq_fail: -- qman_destroy_fq(req_fq); -+ qman_destroy_fq(req_fq, 0); - create_req_fq_fail: - kfree(req_fq); - return ERR_PTR(ret); -@@ -277,7 +277,7 @@ static int kill_fq(struct device *qidev, struct qman_fq *fq) - if (ret) - dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid); - -- qman_destroy_fq(fq); -+ qman_destroy_fq(fq, 0); - kfree(fq); - - return ret; -@@ -295,7 +295,7 @@ static int empty_caam_fq(struct qman_fq *fq, struct caam_drv_ctx *drv_ctx) - if (ret) - return ret; - -- if (!qm_mcr_np_get(&np, frm_cnt)) -+ if (!np.frm_cnt) - break; - - msleep(20); -@@ -571,14 +571,13 @@ static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p, - const struct qm_fd *fd; - struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev); - struct caam_drv_private *priv = dev_get_drvdata(qidev); -- u32 status; - - if (caam_qi_napi_schedule(p, caam_napi)) - return qman_cb_dqrr_stop; - - fd = &dqrr->fd; - -- drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd)); -+ drv_req = caam_iova_to_virt(priv->domain, fd->addr); - if (unlikely(!drv_req)) { - dev_err(qidev, - "Can't find original request for caam response\n"); -@@ -587,19 +586,18 @@ static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p, - - refcount_dec(&drv_req->drv_ctx->refcnt); - -- status = be32_to_cpu(fd->status); -- if (unlikely(status)) { -- u32 ssrc = status & JRSTA_SSRC_MASK; -- u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; -+ if (unlikely(fd->status)) { -+ u32 ssrc = fd->status & JRSTA_SSRC_MASK; -+ u8 err_id = fd->status & JRSTA_CCBERR_ERRID_MASK; - - if (ssrc != JRSTA_SSRC_CCB_ERROR || - err_id != JRSTA_CCBERR_ERRID_ICVCHK) - dev_err_ratelimited(qidev, - "Error: %#x in CAAM response FD\n", -- status); -+ fd->status); - } - -- if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) { -+ if (unlikely(fd->format != qm_fd_compound)) { - dev_err(qidev, "Non-compound FD from CAAM\n"); - return qman_cb_dqrr_consume; - } -@@ -607,7 +605,7 @@ static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p, - dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd), - sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL); - -- drv_req->cbk(drv_req, status); -+ drv_req->cbk(drv_req, fd->status); - return qman_cb_dqrr_consume; - } - -@@ -631,17 +629,18 @@ static int alloc_rsp_fq_cpu(struct device *qidev, unsigned int cpu) - return -ENODEV; - } - -- memset(&opts, 0, sizeof(opts)); -- opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | -- QM_INITFQ_WE_CONTEXTB | -- QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID); -- opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING | -- QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE); -- qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3); -+ opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | -+ QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA | -+ QM_INITFQ_WE_CGID; -+ opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING | QM_FQCTRL_CPCSTASH | -+ QM_FQCTRL_CGE; -+ opts.fqd.dest.channel = qman_affine_channel(cpu); -+ opts.fqd.dest.wq = 3; - opts.fqd.cgid = qipriv.cgr.cgrid; - opts.fqd.context_a.stashing.exclusive = QM_STASHING_EXCL_CTX | - QM_STASHING_EXCL_DATA; -- qm_fqd_set_stashing(&opts.fqd, 0, 1, 1); -+ opts.fqd.context_a.stashing.data_cl = 1; -+ opts.fqd.context_a.stashing.context_cl = 1; - - ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); - if (ret) { -@@ -671,8 +670,7 @@ static int init_cgr(struct device *qidev) - - qipriv.cgr.cb = cgr_cb; - memset(&opts, 0, sizeof(opts)); -- opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | -- QM_CGR_WE_MODE); -+ opts.we_mask = QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | QM_CGR_WE_MODE; - opts.cgr.cscn_en = QM_CGR_EN; - opts.cgr.mode = QMAN_CGR_MODE_FRAME; - qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1); -diff --git a/drivers/crypto/caam/qi.h b/drivers/crypto/caam/qi.h -index 5894f16f8..aa68e37c8 100644 ---- a/drivers/crypto/caam/qi.h -+++ b/drivers/crypto/caam/qi.h -@@ -9,7 +9,7 @@ - #ifndef __QI_H__ - #define __QI_H__ - --#include -+#include - #include "compat.h" - #include "desc.h" - #include "desc_constr.h" -diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h -index af61f3a2c..f233ed562 100644 ---- a/drivers/crypto/caam/regs.h -+++ b/drivers/crypto/caam/regs.h -@@ -382,6 +382,12 @@ struct version_regs { - #define CHA_VER_VID_MD_LP512 0x1ull - #define CHA_VER_VID_MD_HP 0x2ull - -+/* -+ * caam_perfmon - Performance Monitor/Secure Memory Status/ -+ * CAAM Global Status/Component Version IDs -+ * -+ * Spans f00-fff wherever instantiated -+ */ - struct sec_vid { - u16 ip_id; - u8 maj_rev; -@@ -412,17 +418,22 @@ struct caam_perfmon { - #define CTPR_MS_PG_SZ_SHIFT 4 - u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ - u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ -- u64 rsvd1[2]; -+ /* Secure Memory State Visibility */ -+ u32 rsvd1; -+ u32 smstatus; /* Secure memory status */ -+ u32 rsvd2; -+ u32 smpartown; /* Secure memory partition owner */ - - /* CAAM Global Status fc0-fdf */ - u64 faultaddr; /* FAR - Fault Address */ - u32 faultliodn; /* FALR - Fault Address LIODN */ - u32 faultdetail; /* FADR - Fault Addr Detail */ -- u32 rsvd2; - #define CSTA_PLEND BIT(10) - #define CSTA_ALT_PLEND BIT(18) -+ u32 rsvd3; - u32 status; /* CSTA - CAAM Status */ -- u64 rsvd3; -+ u32 smpart; /* Secure Memory Partition Parameters */ -+ u32 smvid; /* Secure Memory Version ID */ - - /* Component Instantiation Parameters fe0-fff */ - u32 rtic_id; /* RVID - RTIC Version ID */ -@@ -441,6 +452,62 @@ struct caam_perfmon { - u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ - }; - -+#define SMSTATUS_PART_SHIFT 28 -+#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) -+#define SMSTATUS_PAGE_SHIFT 16 -+#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) -+#define SMSTATUS_MID_SHIFT 8 -+#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) -+#define SMSTATUS_ACCERR_SHIFT 4 -+#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) -+#define SMSTATUS_ACCERR_NONE 0 -+#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ -+#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ -+#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ -+#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ -+#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ -+#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ -+#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ -+#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ -+#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ -+#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ -+#define SMSTATUS_STATE_SHIFT 0 -+#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) -+#define SMSTATUS_STATE_RESET 0 -+#define SMSTATUS_STATE_INIT 1 -+#define SMSTATUS_STATE_NORMAL 2 -+#define SMSTATUS_STATE_FAIL 3 -+ -+/* up to 15 rings, 2 bits shifted by ring number */ -+#define SMPARTOWN_RING_SHIFT 2 -+#define SMPARTOWN_RING_MASK 3 -+#define SMPARTOWN_AVAILABLE 0 -+#define SMPARTOWN_NOEXIST 1 -+#define SMPARTOWN_UNAVAILABLE 2 -+#define SMPARTOWN_OURS 3 -+ -+/* Maximum number of pages possible */ -+#define SMPART_MAX_NUMPG_SHIFT 16 -+#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) -+ -+/* Maximum partition number */ -+#define SMPART_MAX_PNUM_SHIFT 12 -+#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) -+ -+/* Highest possible page number */ -+#define SMPART_MAX_PG_SHIFT 0 -+#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) -+ -+/* Max size of a page */ -+#define SMVID_PG_SIZE_SHIFT 16 -+#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) -+ -+/* Major/Minor Version ID */ -+#define SMVID_MAJ_VERS_SHIFT 8 -+#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) -+#define SMVID_MIN_VERS_SHIFT 0 -+#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) -+ - /* LIODN programming for DMA configuration */ - #define MSTRID_LOCK_LIODN 0x80000000 - #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ -@@ -451,12 +518,6 @@ struct masterid { - u32 liodn_ls; /* LIODN for non-sequence and seq access */ - }; - --/* Partition ID for DMA configuration */ --struct partid { -- u32 rsvd1; -- u32 pidr; /* partition ID, DECO */ --}; -- - /* RNGB test mode (replicated twice in some configurations) */ - /* Padded out to 0x100 */ - struct rngtst { -@@ -515,6 +576,8 @@ struct rng4tst { - #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) - #define RTSDCTL_ENT_DLY_MIN 3200 - #define RTSDCTL_ENT_DLY_MAX 12800 -+#define RTSDCTL_SAMP_SIZE_MASK 0xffff -+#define RTSDCTL_SAMP_SIZE_VAL 512 - u32 rtsdctl; /* seed control register */ - union { - u32 rtsblim; /* PRGM=1: sparse bit limit register */ -@@ -526,7 +589,15 @@ struct rng4tst { - u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ - u32 rtfrqcnt; /* PRGM=0: freq. count register */ - }; -- u32 rsvd1[40]; -+ union { -+ u32 rtscmc; /* statistical check run monobit count */ -+ u32 rtscml; /* statistical check run monobit limit */ -+ }; -+ union { -+ u32 rtscrc[6]; /* statistical check run length count */ -+ u32 rtscrl[6]; /* statistical check run length limit */ -+ }; -+ u32 rsvd1[33]; - #define RDSTA_SKVT 0x80000000 - #define RDSTA_SKVN 0x40000000 - #define RDSTA_PR0 BIT(4) -@@ -572,8 +643,7 @@ struct caam_ctrl { - u32 deco_rsr; /* DECORSR - Deco Request Source */ - u32 rsvd11; - u32 deco_rq; /* DECORR - DECO Request */ -- struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ -- u32 rsvd5[22]; -+ struct masterid deco_mid[16]; /* DECOxLIODNR - 1 per DECO */ - - /* DECO Availability/Reset Section 120-3ff */ - u32 deco_avail; /* DAR - DECO availability */ -@@ -647,6 +717,35 @@ struct caam_ctrl { - #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ - #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ - -+/* Secure Memory Configuration - if you have it */ -+/* Secure Memory Register Offset from JR Base Reg*/ -+#define SM_V1_OFFSET 0x0f4 -+#define SM_V2_OFFSET 0xa00 -+ -+/* Minimum SM Version ID requiring v2 SM register mapping */ -+#define SMVID_V2 0x20105 -+ -+struct caam_secure_mem_v1 { -+ u32 sm_cmd; /* SMCJRx - Secure memory command */ -+ u32 rsvd1; -+ u32 sm_status; /* SMCSJRx - Secure memory status */ -+ u32 rsvd2; -+ -+ u32 sm_perm; /* SMAPJRx - Secure memory access perms */ -+ u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ -+ u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ -+}; -+ -+struct caam_secure_mem_v2 { -+ u32 sm_perm; /* SMAPJRx - Secure memory access perms */ -+ u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ -+ u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ -+ u32 rsvd1[118]; -+ u32 sm_cmd; /* SMCJRx - Secure memory command */ -+ u32 rsvd2; -+ u32 sm_status; /* SMCSJRx - Secure memory status */ -+}; -+ - /* - * caam_job_ring - direct job ring setup - * 1-4 possible per instantiation, base + 1000/2000/3000/4000 -@@ -817,6 +916,62 @@ struct caam_job_ring { - - #define JRCR_RESET 0x01 - -+/* secure memory command */ -+#define SMC_PAGE_SHIFT 16 -+#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) -+#define SMC_PART_SHIFT 8 -+#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) -+#define SMC_CMD_SHIFT 0 -+#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) -+ -+#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ -+#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ -+#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ -+#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ -+ -+/* secure memory (command) status */ -+#define SMCS_PAGE_SHIFT 16 -+#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) -+#define SMCS_CMDERR_SHIFT 14 -+#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) -+#define SMCS_ALCERR_SHIFT 12 -+#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) -+#define SMCS_PGOWN_SHIFT 6 -+#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) -+#define SMCS_PART_SHIFT 0 -+#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) -+ -+#define SMCS_CMDERR_NONE 0 -+#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ -+#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ -+#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ -+ -+#define SMCS_ALCERR_NONE 0 -+#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ -+#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ -+#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ -+ -+#define SMCS_PGOWN_AVAIL 0 /* Page is available */ -+#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ -+#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ -+#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ -+ -+/* secure memory access permissions */ -+#define SMCS_PERM_KEYMOD_SHIFT 16 -+#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) -+#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ -+#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ -+#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ -+#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ -+#define SMCA_PERM_RINGID_SHIFT 10 -+#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) -+#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ -+#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ -+#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ -+#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ -+#define SMCA_PERM_G1_WRITE 0x0002 -+#define SMCA_PERM_G1_READ 0x0001 -+ - /* - * caam_assurance - Assurance Controller View - * base + 0x6000 padded out to 0x1000 -diff --git a/drivers/crypto/caam/secvio.c b/drivers/crypto/caam/secvio.c -new file mode 100644 -index 000000000..d6ebe0af4 ---- /dev/null -+++ b/drivers/crypto/caam/secvio.c -@@ -0,0 +1,341 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * SNVS Security Violation Handler -+ * -+ * Copyright 2012-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2019 NXP -+ */ -+ -+#include "compat.h" -+#include "secvio.h" -+#include "regs.h" -+#include "intern.h" -+#include -+#include -+#include -+ -+/* The driver is matched with node caam_snvs to get regmap -+ * It will then retrieve interruption and tamper alarm configuration from -+ * node caam-secvio searching for the compat string "fsl,imx6q-caam-secvio" -+ */ -+#define DRIVER_NAME "caam-snvs" -+ -+/* -+ * These names are associated with each violation handler. -+ * The source names were taken from MX6, and are based on recommendations -+ * for most common SoCs. -+ */ -+static const u8 *violation_src_name[] = { -+ "CAAM Internal Security Violation", -+ "JTAG Alarm", -+ "Watchdog", -+ "(reserved)", -+ "External Boot", -+ "External Tamper Detect", -+}; -+ -+/* These names help describe security monitor state for the console */ -+static const u8 *snvs_ssm_state_name[] = { -+ "init", -+ "hard fail", -+ "(undef:2)", -+ "soft fail", -+ "(undef:4)", -+ "(undef:5)", -+ "(undef:6)", -+ "(undef:7)", -+ "transition", -+ "check", -+ "(undef:10)", -+ "non-secure", -+ "(undef:12)", -+ "trusted", -+ "(undef:14)", -+ "secure", -+}; -+ -+/* Top-level security violation interrupt */ -+static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev) -+{ -+ struct device *dev = snvsdev; -+ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); -+ -+ clk_enable(svpriv->clk); -+ /* Check the HP secvio status register */ -+ svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) & -+ HP_SECVIOST_SECVIOMASK; -+ -+ if (!svpriv->irqcause) { -+ clk_disable(svpriv->clk); -+ return IRQ_NONE; -+ } -+ -+ /* Now ACK cause */ -+ clrsetbits_32(&svpriv->svregs->hp.secvio_status, 0, svpriv->irqcause); -+ -+ /* And run deferred service */ -+ preempt_disable(); -+ tasklet_schedule(&svpriv->irqtask[smp_processor_id()]); -+ preempt_enable(); -+ -+ clk_disable(svpriv->clk); -+ -+ return IRQ_HANDLED; -+} -+ -+/* Deferred service handler. Tasklet arg is simply the SNVS dev */ -+static void snvs_secvio_dispatch(unsigned long indev) -+{ -+ struct device *dev = (struct device *)indev; -+ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); -+ unsigned long flags; -+ int i; -+ -+ -+ /* Look through stored causes, call each handler if exists */ -+ for (i = 0; i < MAX_SECVIO_SOURCES; i++) -+ if (svpriv->irqcause & (1 << i)) { -+ spin_lock_irqsave(&svpriv->svlock, flags); -+ svpriv->intsrc[i].handler(dev, i, -+ svpriv->intsrc[i].ext); -+ spin_unlock_irqrestore(&svpriv->svlock, flags); -+ }; -+ -+ /* Re-enable now-serviced interrupts */ -+ clrsetbits_32(&svpriv->svregs->hp.secvio_intcfg, 0, svpriv->irqcause); -+} -+ -+/* -+ * Default cause handler, used in lieu of an application-defined handler. -+ * All it does at this time is print a console message. It could force a halt. -+ */ -+static void snvs_secvio_default(struct device *dev, u32 cause, void *ext) -+{ -+ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); -+ -+ dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n", -+ cause, svpriv->intsrc[cause].intname); -+} -+ -+/* -+ * Install an application-defined handler for a specified cause -+ * Arguments: -+ * - dev points to SNVS-owning device -+ * - cause interrupt source cause -+ * - handler application-defined handler, gets called with dev -+ * source cause, and locally-defined handler argument -+ * - cause_description points to a string to override the default cause -+ * name, this can be used as an alternate for error -+ * messages and such. If left NULL, the default -+ * description string is used. -+ * - ext pointer to any extra data needed by the handler. -+ */ -+int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, -+ void (*handler)(struct device *dev, u32 cause, -+ void *ext), -+ u8 *cause_description, void *ext) -+{ -+ unsigned long flags; -+ struct snvs_secvio_drv_private *svpriv; -+ -+ svpriv = dev_get_drvdata(dev); -+ -+ if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5)) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&svpriv->svlock, flags); -+ svpriv->intsrc[cause].handler = handler; -+ if (cause_description != NULL) -+ svpriv->intsrc[cause].intname = cause_description; -+ if (ext != NULL) -+ svpriv->intsrc[cause].ext = ext; -+ spin_unlock_irqrestore(&svpriv->svlock, flags); -+ -+ return 0; -+} -+EXPORT_SYMBOL(snvs_secvio_install_handler); -+ -+/* -+ * Remove an application-defined handler for a specified cause (and, by -+ * implication, restore the "default". -+ * Arguments: -+ * - dev points to SNVS-owning device -+ * - cause interrupt source cause -+ */ -+int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause) -+{ -+ unsigned long flags; -+ struct snvs_secvio_drv_private *svpriv; -+ -+ svpriv = dev_get_drvdata(dev); -+ -+ if (cause > SECVIO_CAUSE_SOURCE_5) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&svpriv->svlock, flags); -+ svpriv->intsrc[cause].intname = violation_src_name[cause]; -+ svpriv->intsrc[cause].handler = snvs_secvio_default; -+ svpriv->intsrc[cause].ext = NULL; -+ spin_unlock_irqrestore(&svpriv->svlock, flags); -+ return 0; -+} -+EXPORT_SYMBOL(snvs_secvio_remove_handler); -+ -+static int snvs_secvio_remove(struct platform_device *pdev) -+{ -+ struct device *svdev; -+ struct snvs_secvio_drv_private *svpriv; -+ int i; -+ -+ svdev = &pdev->dev; -+ svpriv = dev_get_drvdata(svdev); -+ -+ clk_enable(svpriv->clk); -+ /* Set all sources to nonfatal */ -+ wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0); -+ -+ /* Remove tasklets and release interrupt */ -+ for_each_possible_cpu(i) -+ tasklet_kill(&svpriv->irqtask[i]); -+ -+ clk_disable_unprepare(svpriv->clk); -+ free_irq(svpriv->irq, svdev); -+ iounmap(svpriv->svregs); -+ kfree(svpriv); -+ -+ return 0; -+} -+ -+static int snvs_secvio_probe(struct platform_device *pdev) -+{ -+ struct device *svdev; -+ struct snvs_secvio_drv_private *svpriv; -+ struct device_node *np, *npirq; -+ struct snvs_full __iomem *snvsregs; -+ int i, error; -+ u32 hpstate; -+ const void *jtd, *wtd, *itd, *etd; -+ u32 td_en; -+ -+ svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL); -+ if (!svpriv) -+ return -ENOMEM; -+ -+ svdev = &pdev->dev; -+ dev_set_drvdata(svdev, svpriv); -+ svpriv->pdev = pdev; -+ spin_lock_init(&svpriv->svlock); -+ np = pdev->dev.of_node; -+ -+ npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio"); -+ if (!npirq) { -+ dev_err(svdev, "can't find secvio node\n"); -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ svpriv->irq = irq_of_parse_and_map(npirq, 0); -+ if (svpriv->irq <= 0) { -+ dev_err(svdev, "can't identify secvio interrupt\n"); -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ -+ jtd = of_get_property(npirq, "jtag-tamper", NULL); -+ wtd = of_get_property(npirq, "watchdog-tamper", NULL); -+ itd = of_get_property(npirq, "internal-boot-tamper", NULL); -+ etd = of_get_property(npirq, "external-pin-tamper", NULL); -+ if (!jtd | !wtd | !itd | !etd ) { -+ dev_err(svdev, "can't identify all tamper alarm configuration\n"); -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ -+ /* -+ * Configure all sources according to device tree property. -+ * If the property is enabled then the source is ser as -+ * fatal violations except LP section, -+ * source #5 (typically used as an external tamper detect), and -+ * source #3 (typically unused). Whenever the transition to -+ * secure mode has occurred, these will now be "fatal" violations -+ */ -+ td_en = HP_SECVIO_INTEN_SRC0; -+ if (!strcmp(jtd, "enabled")) -+ td_en |= HP_SECVIO_INTEN_SRC1; -+ if (!strcmp(wtd, "enabled")) -+ td_en |= HP_SECVIO_INTEN_SRC2; -+ if (!strcmp(itd, "enabled")) -+ td_en |= HP_SECVIO_INTEN_SRC4; -+ if (!strcmp(etd, "enabled")) -+ td_en |= HP_SECVIO_INTEN_SRC5; -+ -+ snvsregs = of_iomap(np, 0); -+ if (!snvsregs) { -+ dev_err(svdev, "register mapping failed\n"); -+ return -ENOMEM; -+ } -+ svpriv->svregs = (struct snvs_full __force *)snvsregs; -+ -+ svpriv->clk = devm_clk_get_optional(&pdev->dev, "ipg"); -+ if (IS_ERR(svpriv->clk)) -+ return PTR_ERR(svpriv->clk); -+ -+ clk_prepare_enable(svpriv->clk); -+ -+ /* Write the Secvio Enable Config the SVCR */ -+ wr_reg32(&svpriv->svregs->hp.secvio_ctl, td_en); -+ wr_reg32(&svpriv->svregs->hp.secvio_intcfg, td_en); -+ -+ /* Device data set up. Now init interrupt source descriptions */ -+ for (i = 0; i < MAX_SECVIO_SOURCES; i++) { -+ svpriv->intsrc[i].intname = violation_src_name[i]; -+ svpriv->intsrc[i].handler = snvs_secvio_default; -+ } -+ /* Connect main handler */ -+ for_each_possible_cpu(i) -+ tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch, -+ (unsigned long)svdev); -+ -+ error = request_irq(svpriv->irq, snvs_secvio_interrupt, -+ IRQF_SHARED, DRIVER_NAME, svdev); -+ if (error) { -+ dev_err(svdev, "can't connect secvio interrupt\n"); -+ irq_dispose_mapping(svpriv->irq); -+ svpriv->irq = 0; -+ iounmap(svpriv->svregs); -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ -+ hpstate = (rd_reg32(&svpriv->svregs->hp.status) & -+ HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT; -+ dev_info(svdev, "violation handlers armed - %s state\n", -+ snvs_ssm_state_name[hpstate]); -+ -+ clk_disable(svpriv->clk); -+ -+ return 0; -+} -+ -+static struct of_device_id snvs_secvio_match[] = { -+ { -+ .compatible = "fsl,imx6q-caam-snvs", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snvs_secvio_match); -+ -+static struct platform_driver snvs_secvio_driver = { -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = snvs_secvio_match, -+ }, -+ .probe = snvs_secvio_probe, -+ .remove = snvs_secvio_remove, -+}; -+ -+module_platform_driver(snvs_secvio_driver); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("FSL SNVS Security Violation Handler"); -+MODULE_AUTHOR("Freescale Semiconductor - MCU"); -diff --git a/drivers/crypto/caam/secvio.h b/drivers/crypto/caam/secvio.h -new file mode 100644 -index 000000000..a7a245a3d ---- /dev/null -+++ b/drivers/crypto/caam/secvio.h -@@ -0,0 +1,69 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * CAAM Security Violation Handler -+ * -+ * Copyright 2012-2015 Freescale Semiconductor, Inc. -+ * Copyright 2016-2019 NXP -+ */ -+ -+#ifndef SECVIO_H -+#define SECVIO_H -+ -+#include "snvsregs.h" -+ -+ -+/* -+ * Defines the published interfaces to install/remove application-specified -+ * handlers for catching violations -+ */ -+ -+#define MAX_SECVIO_SOURCES 6 -+ -+/* these are the untranslated causes */ -+enum secvio_cause { -+ SECVIO_CAUSE_SOURCE_0, -+ SECVIO_CAUSE_SOURCE_1, -+ SECVIO_CAUSE_SOURCE_2, -+ SECVIO_CAUSE_SOURCE_3, -+ SECVIO_CAUSE_SOURCE_4, -+ SECVIO_CAUSE_SOURCE_5 -+}; -+ -+/* These are common "recommended" cause definitions for most devices */ -+#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0 -+#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1 -+#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2 -+#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4 -+#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5 -+ -+int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, -+ void (*handler)(struct device *dev, u32 cause, -+ void *ext), -+ u8 *cause_description, void *ext); -+int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause); -+ -+/* -+ * Private data definitions for the secvio "driver" -+ */ -+ -+struct secvio_int_src { -+ const u8 *intname; /* Points to a descriptive name for source */ -+ void *ext; /* Extended data to pass to the handler */ -+ void (*handler)(struct device *dev, u32 cause, void *ext); -+}; -+ -+struct snvs_secvio_drv_private { -+ struct platform_device *pdev; -+ spinlock_t svlock ____cacheline_aligned; -+ struct tasklet_struct irqtask[NR_CPUS]; -+ struct snvs_full __iomem *svregs; /* both HP and LP domains */ -+ struct clk *clk; -+ int irq; -+ u32 irqcause; /* stashed cause of violation interrupt */ -+ -+ /* Registered handlers for each violation */ -+ struct secvio_int_src intsrc[MAX_SECVIO_SOURCES]; -+ -+}; -+ -+#endif /* SECVIO_H */ -diff --git a/drivers/crypto/caam/sg_sw_qm.h b/drivers/crypto/caam/sg_sw_qm.h -index d56cc7efb..9465b5773 100644 ---- a/drivers/crypto/caam/sg_sw_qm.h -+++ b/drivers/crypto/caam/sg_sw_qm.h -@@ -7,46 +7,61 @@ - #ifndef __SG_SW_QM_H - #define __SG_SW_QM_H - --#include -+#include - #include "regs.h" - -+static inline void cpu_to_hw_sg(struct qm_sg_entry *qm_sg_ptr) -+{ -+ dma_addr_t addr = qm_sg_ptr->opaque; -+ -+ qm_sg_ptr->opaque = cpu_to_caam64(addr); -+ qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl); -+} -+ - static inline void __dma_to_qm_sg(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, -- u16 offset) -+ u32 len, u16 offset) - { -- qm_sg_entry_set64(qm_sg_ptr, dma); -+ qm_sg_ptr->addr = dma; -+ qm_sg_ptr->length = len; - qm_sg_ptr->__reserved2 = 0; - qm_sg_ptr->bpid = 0; -- qm_sg_ptr->offset = cpu_to_be16(offset & QM_SG_OFF_MASK); -+ qm_sg_ptr->__reserved3 = 0; -+ qm_sg_ptr->offset = offset & QM_SG_OFFSET_MASK; -+ -+ cpu_to_hw_sg(qm_sg_ptr); - } - - static inline void dma_to_qm_sg_one(struct qm_sg_entry *qm_sg_ptr, - dma_addr_t dma, u32 len, u16 offset) - { -- __dma_to_qm_sg(qm_sg_ptr, dma, offset); -- qm_sg_entry_set_len(qm_sg_ptr, len); -+ qm_sg_ptr->extension = 0; -+ qm_sg_ptr->final = 0; -+ __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); - } - - static inline void dma_to_qm_sg_one_last(struct qm_sg_entry *qm_sg_ptr, - dma_addr_t dma, u32 len, u16 offset) - { -- __dma_to_qm_sg(qm_sg_ptr, dma, offset); -- qm_sg_entry_set_f(qm_sg_ptr, len); -+ qm_sg_ptr->extension = 0; -+ qm_sg_ptr->final = 1; -+ __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); - } - - static inline void dma_to_qm_sg_one_ext(struct qm_sg_entry *qm_sg_ptr, - dma_addr_t dma, u32 len, u16 offset) - { -- __dma_to_qm_sg(qm_sg_ptr, dma, offset); -- qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | (len & QM_SG_LEN_MASK)); -+ qm_sg_ptr->extension = 1; -+ qm_sg_ptr->final = 0; -+ __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); - } - - static inline void dma_to_qm_sg_one_last_ext(struct qm_sg_entry *qm_sg_ptr, - dma_addr_t dma, u32 len, - u16 offset) - { -- __dma_to_qm_sg(qm_sg_ptr, dma, offset); -- qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | QM_SG_FIN | -- (len & QM_SG_LEN_MASK)); -+ qm_sg_ptr->extension = 1; -+ qm_sg_ptr->final = 1; -+ __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); - } - - /* -@@ -79,7 +94,10 @@ static inline void sg_to_qm_sg_last(struct scatterlist *sg, int len, - struct qm_sg_entry *qm_sg_ptr, u16 offset) - { - qm_sg_ptr = sg_to_qm_sg(sg, len, qm_sg_ptr, offset); -- qm_sg_entry_set_f(qm_sg_ptr, qm_sg_entry_get_len(qm_sg_ptr)); -+ -+ qm_sg_ptr->sgt_efl = caam32_to_cpu(qm_sg_ptr->sgt_efl); -+ qm_sg_ptr->final = 1; -+ qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl); - } - - #endif /* __SG_SW_QM_H */ -diff --git a/drivers/crypto/caam/sm.h b/drivers/crypto/caam/sm.h -new file mode 100644 -index 000000000..614c9b4d3 ---- /dev/null -+++ b/drivers/crypto/caam/sm.h -@@ -0,0 +1,126 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * CAAM Secure Memory/Keywrap API Definitions -+ * -+ * Copyright 2008-2015 Freescale Semiconductor, Inc. -+ * Copyright 2016-2019 NXP -+ */ -+ -+#ifndef SM_H -+#define SM_H -+ -+ -+/* Storage access permissions */ -+#define SM_PERM_READ 0x01 -+#define SM_PERM_WRITE 0x02 -+#define SM_PERM_BLOB 0x03 -+ -+/* Define treatment of secure memory vs. general memory blobs */ -+#define SM_SECMEM 0 -+#define SM_GENMEM 1 -+ -+/* Define treatment of red/black keys */ -+#define RED_KEY 0 -+#define BLACK_KEY 1 -+ -+/* Define key encryption/covering options */ -+#define KEY_COVER_ECB 0 /* cover key in AES-ECB */ -+#define KEY_COVER_CCM 1 /* cover key with AES-CCM */ -+ -+/* -+ * Round a key size up to an AES blocksize boundary so to allow for -+ * padding out to a full block -+ */ -+#define AES_BLOCK_PAD(x) ((x % 16) ? ((x >> 4) + 1) << 4 : x) -+ -+/* Define space required for BKEK + MAC tag storage in any blob */ -+#define BLOB_OVERHEAD (32 + 16) -+ -+/* Keystore maintenance functions */ -+void sm_init_keystore(struct device *dev); -+u32 sm_detect_keystore_units(struct device *dev); -+int sm_establish_keystore(struct device *dev, u32 unit); -+void sm_release_keystore(struct device *dev, u32 unit); -+int caam_sm_example_init(struct platform_device *pdev); -+ -+/* Keystore accessor functions */ -+extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, -+ u32 *slot); -+extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot); -+extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, -+ const u8 *key_data, u32 key_length); -+extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, -+ u32 key_length, u8 *key_data); -+extern int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, -+ u16 key_length, u8 keyauth); -+extern int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, -+ u8 keycolor, u8 keyauth, u8 *outbuf, -+ u16 keylen, u8 *keymod); -+extern int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, -+ u8 keycolor, u8 keyauth, u8 *inbuf, -+ u16 keylen, u8 *keymod); -+ -+/* Prior functions from legacy API, deprecated */ -+extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, -+ u32 inslot, u32 outslot, u16 secretlen, -+ u8 *keymod, u16 keymodlen); -+extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, -+ u32 inslot, u32 outslot, u16 secretlen, -+ u8 *keymod, u16 keymodlen); -+ -+/* Data structure to hold per-slot information */ -+struct keystore_data_slot_info { -+ u8 allocated; /* Track slot assignments */ -+ u32 key_length; /* Size of the key */ -+}; -+ -+/* Data structure to hold keystore information */ -+struct keystore_data { -+ void *base_address; /* Virtual base of secure memory pages */ -+ void *phys_address; /* Physical base of secure memory pages */ -+ u32 slot_count; /* Number of slots in the keystore */ -+ struct keystore_data_slot_info *slot; /* Per-slot information */ -+}; -+ -+/* store the detected attributes of a secure memory page */ -+struct sm_page_descriptor { -+ u16 phys_pagenum; /* may be discontiguous */ -+ u16 own_part; /* Owning partition */ -+ void *pg_base; /* Calculated virtual address */ -+ void *pg_phys; /* Calculated physical address */ -+ struct keystore_data *ksdata; -+}; -+ -+struct caam_drv_private_sm { -+ struct device *parentdev; /* this ends up as the controller */ -+ struct device *smringdev; /* ring that owns this instance */ -+ struct platform_device *sm_pdev; /* Secure Memory platform device */ -+ spinlock_t kslock ____cacheline_aligned; -+ -+ /* SM Register offset from JR base address */ -+ u32 sm_reg_offset; -+ -+ /* Default parameters for geometry */ -+ u32 max_pages; /* maximum pages this instance can support */ -+ u32 top_partition; /* highest partition number in this instance */ -+ u32 top_page; /* highest page number in this instance */ -+ u32 page_size; /* page size */ -+ u32 slot_size; /* selected size of each storage block */ -+ -+ /* Partition/Page Allocation Map */ -+ u32 localpages; /* Number of pages we can access */ -+ struct sm_page_descriptor *pagedesc; /* Allocated per-page */ -+ -+ /* Installed handlers for keystore access */ -+ int (*data_init)(struct device *dev, u32 unit); -+ void (*data_cleanup)(struct device *dev, u32 unit); -+ int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot); -+ int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot); -+ void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle); -+ void *(*slot_get_physical)(struct device *dev, u32 unit, u32 handle); -+ u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle); -+ u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle); -+ u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle); -+}; -+ -+#endif /* SM_H */ -diff --git a/drivers/crypto/caam/sm_store.c b/drivers/crypto/caam/sm_store.c -new file mode 100644 -index 000000000..88e0706e9 ---- /dev/null -+++ b/drivers/crypto/caam/sm_store.c -@@ -0,0 +1,1270 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * CAAM Secure Memory Storage Interface -+ * -+ * Copyright 2008-2015 Freescale Semiconductor, Inc. -+ * Copyright 2016-2019 NXP -+ * -+ * Loosely based on the SHW Keystore API for SCC/SCC2 -+ * Experimental implementation and NOT intended for upstream use. Expect -+ * this interface to be amended significantly in the future once it becomes -+ * integrated into live applications. -+ * -+ * Known issues: -+ * -+ * - Executes one instance of an secure memory "driver". This is tied to the -+ * fact that job rings can't run as standalone instances in the present -+ * configuration. -+ * -+ * - It does not expose a userspace interface. The value of a userspace -+ * interface for access to secrets is a point for further architectural -+ * discussion. -+ * -+ * - Partition/permission management is not part of this interface. It -+ * depends on some level of "knowledge" agreed upon between bootloader, -+ * provisioning applications, and OS-hosted software (which uses this -+ * driver). -+ * -+ * - No means of identifying the location or purpose of secrets managed by -+ * this interface exists; "slot location" and format of a given secret -+ * needs to be agreed upon between bootloader, provisioner, and OS-hosted -+ * application. -+ */ -+ -+#include "compat.h" -+#include "regs.h" -+#include "jr.h" -+#include "desc.h" -+#include "intern.h" -+#include "error.h" -+#include "sm.h" -+#include -+ -+#define SECMEM_KEYMOD_LEN 8 -+#define GENMEM_KEYMOD_LEN 16 -+ -+#ifdef SM_DEBUG_CONT -+void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ u32 i, *smdata; -+ -+ dev_info(dev, "physical page %d content at 0x%08x\n", -+ pgdesc->phys_pagenum, pgdesc->pg_base); -+ smdata = pgdesc->pg_base; -+ for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4) -+ dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n", -+ (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2], -+ smdata[i+3]); -+} -+#endif -+ -+#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */ -+ -+static __always_inline u32 sm_send_cmd(struct caam_drv_private_sm *smpriv, -+ struct caam_drv_private_jr *jrpriv, -+ u32 cmd, u32 *status) -+{ -+ void __iomem *write_address; -+ void __iomem *read_address; -+ -+ if (smpriv->sm_reg_offset == SM_V1_OFFSET) { -+ struct caam_secure_mem_v1 *sm_regs_v1; -+ -+ sm_regs_v1 = (struct caam_secure_mem_v1 *) -+ ((void *)jrpriv->rregs + SM_V1_OFFSET); -+ write_address = &sm_regs_v1->sm_cmd; -+ read_address = &sm_regs_v1->sm_status; -+ -+ } else if (smpriv->sm_reg_offset == SM_V2_OFFSET) { -+ struct caam_secure_mem_v2 *sm_regs_v2; -+ -+ sm_regs_v2 = (struct caam_secure_mem_v2 *) -+ ((void *)jrpriv->rregs + SM_V2_OFFSET); -+ write_address = &sm_regs_v2->sm_cmd; -+ read_address = &sm_regs_v2->sm_status; -+ -+ } else { -+ return -EINVAL; -+ } -+ -+ wr_reg32(write_address, cmd); -+ -+ udelay(10); -+ -+ /* Read until the command has terminated and the status is correct */ -+ do { -+ *status = rd_reg32(read_address); -+ } while (((*status & SMCS_CMDERR_MASK) >> SMCS_CMDERR_SHIFT) -+ == SMCS_CMDERR_INCOMP); -+ -+ return 0; -+} -+ -+/* -+ * Construct a black key conversion job descriptor -+ * -+ * This function constructs a job descriptor capable of performing -+ * a key blackening operation on a plaintext secure memory resident object. -+ * -+ * - desc pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * - key physical pointer to the plaintext, which will also hold -+ * the result. Since encryption occurs in place, caller must -+ * ensure that the space is large enough to accommodate the -+ * blackened key -+ * - keysz size of the plaintext -+ * - auth if a CCM-covered key is required, use KEY_COVER_CCM, else -+ * use KEY_COVER_ECB. -+ * -+ * KEY to key1 from @key_addr LENGTH 16 BYTES; -+ * FIFO STORE from key1[ecb] TO @key_addr LENGTH 16 BYTES; -+ * -+ * Note that this variant uses the JDKEK only; it does not accommodate the -+ * trusted key encryption key at this time. -+ * -+ */ -+static int blacken_key_jobdesc(u32 **desc, void *key, u16 keysz, bool auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* Load key to class 1 key register */ -+ tmpdesc[idx++] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK); -+ tmpdesc[idx++] = (uintptr_t)key; -+ -+ /* ...and write back out via FIFO store*/ -+ tmpdesc[idx] = CMD_FIFO_STORE | CLASS_1 | (keysz & KEY_LENGTH_MASK); -+ -+ /* plus account for ECB/CCM option in FIFO_STORE */ -+ if (auth == KEY_COVER_ECB) -+ tmpdesc[idx] |= FIFOST_TYPE_KEY_KEK; -+ else -+ tmpdesc[idx] |= FIFOST_TYPE_KEY_CCM_JKEK; -+ -+ idx++; -+ tmpdesc[idx++] = (uintptr_t)key; -+ -+ /* finish off the job header */ -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ /* now allocate execution buffer and coat it with executable */ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ -+ return dsize; -+} -+ -+/* -+ * Construct a blob encapsulation job descriptor -+ * -+ * This function dynamically constructs a blob encapsulation job descriptor -+ * from the following arguments: -+ * -+ * - desc pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * - keymod Physical pointer to a key modifier, which must reside in a -+ * contiguous piece of memory. Modifier will be assumed to be -+ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long -+ * for a blob of type SM_GENMEM (see blobtype argument). -+ * - secretbuf Physical pointer to a secret, normally a black or red key, -+ * possibly residing within an accessible secure memory page, -+ * of the secret to be encapsulated to an output blob. -+ * - outbuf Physical pointer to the destination buffer to receive the -+ * encapsulated output. This buffer will need to be 48 bytes -+ * larger than the input because of the added encapsulation data. -+ * The generated descriptor will account for the increase in size, -+ * but the caller must also account for this increase in the -+ * buffer allocator. -+ * - secretsz Size of input secret, in bytes. This is limited to 65536 -+ * less the size of blob overhead, since the length embeds into -+ * DECO pointer in/out instructions. -+ * - keycolor Determines if the source data is covered (black key) or -+ * plaintext (red key). RED_KEY or BLACK_KEY are defined in -+ * for this purpose. -+ * - blobtype Determine if encapsulated blob should be a secure memory -+ * blob (SM_SECMEM), with partition data embedded with key -+ * material, or a general memory blob (SM_GENMEM). -+ * - auth If BLACK_KEY source is covered via AES-CCM, specify -+ * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). -+ * -+ * Upon completion, desc points to a buffer containing a CAAM job -+ * descriptor which encapsulates data into an externally-storable blob -+ * suitable for use across power cycles. -+ * -+ * This is an example of a black key encapsulation job into a general memory -+ * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note -+ * the output 48 bytes longer than the input: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400010 ld: ccb2-key len=16 offs=0 -+ * [02] 08144891 ptr->@0x08144891 -+ * [03] F800003A seqoutptr: len=58 -+ * [04] 01000000 out_ptr->@0x01000000 -+ * [05] F000000A seqinptr: len=10 -+ * [06] 09745090 in_ptr->@0x09745090 -+ * [07] 870D0004 operation: encap blob reg=memory, black, format=normal -+ * -+ * This is an example of a red key encapsulation job for storing a red key -+ * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset -+ * in the LOAD instruction; this accounts for blob permission storage: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400C08 ld: ccb2-key len=8 offs=12 -+ * [02] 087D0784 ptr->@0x087d0784 -+ * [03] F8000050 seqoutptr: len=80 -+ * [04] 09251BB2 out_ptr->@0x09251bb2 -+ * [05] F0000020 seqinptr: len=32 -+ * [06] 40000F31 in_ptr->@0x40000f31 -+ * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, -+ * format=normal -+ * -+ * Note: this function only generates 32-bit pointers at present, and should -+ * be refactored using a scheme that allows both 32 and 64 bit addressing -+ */ -+ -+static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod, -+ void *secretbuf, dma_addr_t outbuf, -+ u16 secretsz, u8 keycolor, u8 blobtype, u8 auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* -+ * Key modifier works differently for secure/general memory blobs -+ * This accounts for the permission/protection data encapsulated -+ * within the blob if a secure memory blob is requested -+ */ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) -+ | (8 & LDST_LEN_MASK); -+ else /* is general memory blob */ -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); -+ -+ tmpdesc[idx++] = (u32)keymod; -+ -+ /* -+ * Encapsulation output must include space for blob key encryption -+ * key and MAC tag -+ */ -+ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD); -+ tmpdesc[idx++] = (u32)outbuf; -+ -+ /* Input data, should be somewhere in secure memory */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz; -+ tmpdesc[idx++] = (uintptr_t)secretbuf; -+ -+ /* Set blob encap, then color */ -+ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB; -+ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; -+ -+ if (auth == KEY_COVER_CCM) -+ tmpdesc[idx] |= OP_PCL_BLOB_EKT; -+ -+ if (keycolor == BLACK_KEY) -+ tmpdesc[idx] |= OP_PCL_BLOB_BLACK; -+ -+ idx++; -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ return dsize; -+} -+ -+/* -+ * Construct a blob decapsulation job descriptor -+ * -+ * This function dynamically constructs a blob decapsulation job descriptor -+ * from the following arguments: -+ * -+ * - desc pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * - keymod Physical pointer to a key modifier, which must reside in a -+ * contiguous piece of memory. Modifier will be assumed to be -+ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long -+ * for a blob of type SM_GENMEM (see blobtype argument). -+ * - blobbuf Physical pointer (into external memory) of the blob to -+ * be decapsulated. Blob must reside in a contiguous memory -+ * segment. -+ * - outbuf Physical pointer of the decapsulated output, possibly into -+ * a location within a secure memory page. Must be contiguous. -+ * - secretsz Size of encapsulated secret in bytes (not the size of the -+ * input blob). -+ * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY) -+ * or left as plaintext (RED_KEY). -+ * - blobtype Determine if encapsulated blob should be a secure memory -+ * blob (SM_SECMEM), with partition data embedded with key -+ * material, or a general memory blob (SM_GENMEM). -+ * - auth If decapsulation path is specified by BLACK_KEY, then if -+ * AES-CCM is requested for key covering use KEY_COVER_CCM, else -+ * use AES-ECB (KEY_COVER_ECB). -+ * -+ * Upon completion, desc points to a buffer containing a CAAM job descriptor -+ * that decapsulates a key blob from external memory into a black (encrypted) -+ * key or red (plaintext) content. -+ * -+ * This is an example of a black key decapsulation job from a general memory -+ * blob. Notice the 16-byte key modifier in the LOAD instruction. -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400010 ld: ccb2-key len=16 offs=0 -+ * [02] 08A63B7F ptr->@0x08a63b7f -+ * [03] F8000010 seqoutptr: len=16 -+ * [04] 01000000 out_ptr->@0x01000000 -+ * [05] F000003A seqinptr: len=58 -+ * [06] 01000010 in_ptr->@0x01000010 -+ * [07] 860D0004 operation: decap blob reg=memory, black, format=normal -+ * -+ * This is an example of a red key decapsulation job for restoring a red key -+ * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset -+ * in the LOAD instruction: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400C08 ld: ccb2-key len=8 offs=12 -+ * [02] 01000000 ptr->@0x01000000 -+ * [03] F8000020 seqoutptr: len=32 -+ * [04] 400000E6 out_ptr->@0x400000e6 -+ * [05] F0000050 seqinptr: len=80 -+ * [06] 08F0C0EA in_ptr->@0x08f0c0ea -+ * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, -+ * format=normal -+ * -+ * Note: this function only generates 32-bit pointers at present, and should -+ * be refactored using a scheme that allows both 32 and 64 bit addressing -+ */ -+ -+static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf, -+ u8 *outbuf, u16 secretsz, u8 keycolor, -+ u8 blobtype, u8 auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* Load key modifier */ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) -+ | (8 & LDST_LEN_MASK); -+ else /* is general memory blob */ -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); -+ -+ tmpdesc[idx++] = (u32)keymod; -+ -+ /* Compensate BKEK + MAC tag over size of encapsulated secret */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD); -+ tmpdesc[idx++] = (u32)blobbuf; -+ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz; -+ tmpdesc[idx++] = (uintptr_t)outbuf; -+ -+ /* Decapsulate from secure memory partition to black blob */ -+ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB; -+ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; -+ -+ if (auth == KEY_COVER_CCM) -+ tmpdesc[idx] |= OP_PCL_BLOB_EKT; -+ -+ if (keycolor == BLACK_KEY) -+ tmpdesc[idx] |= OP_PCL_BLOB_BLACK; -+ -+ idx++; -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ return dsize; -+} -+ -+/* -+ * Pseudo-synchronous ring access functions for carrying out key -+ * encapsulation and decapsulation -+ */ -+ -+struct sm_key_job_result { -+ int error; -+ struct completion completion; -+}; -+ -+void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context) -+{ -+ struct sm_key_job_result *res = context; -+ -+ if (err) -+ caam_jr_strstatus(dev, err); -+ -+ res->error = err; /* save off the error for postprocessing */ -+ -+ complete(&res->completion); /* mark us complete */ -+} -+ -+static int sm_key_job(struct device *ksdev, u32 *jobdesc) -+{ -+ struct sm_key_job_result testres = {0}; -+ struct caam_drv_private_sm *kspriv; -+ int rtn = 0; -+ -+ kspriv = dev_get_drvdata(ksdev); -+ -+ init_completion(&testres.completion); -+ -+ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done, -+ &testres); -+ if (rtn != -EINPROGRESS) -+ goto exit; -+ -+ wait_for_completion(&testres.completion); -+ rtn = testres.error; -+ -+exit: -+ return rtn; -+} -+ -+/* -+ * Following section establishes the default methods for keystore access -+ * They are NOT intended for use external to this module -+ * -+ * In the present version, these are the only means for the higher-level -+ * interface to deal with the mechanics of accessing the phyiscal keystore -+ */ -+ -+ -+int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ u32 i; -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size); -+#endif -+ -+ if (size > smpriv->slot_size) -+ return -EKEYREJECTED; -+ -+ for (i = 0; i < ksdata->slot_count; i++) { -+ if (ksdata->slot[i].allocated == 0) { -+ ksdata->slot[i].allocated = 1; -+ (*slot) = i; -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_alloc(): new slot %d allocated\n", -+ *slot); -+#endif -+ return 0; -+ } -+ } -+ -+ return -ENOSPC; -+} -+EXPORT_SYMBOL(slot_alloc); -+ -+int slot_dealloc(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ u8 __iomem *slotdata; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot); -+#endif -+ if (slot >= ksdata->slot_count) -+ return -EINVAL; -+ slotdata = ksdata->base_address + slot * smpriv->slot_size; -+ -+ if (ksdata->slot[slot].allocated == 1) { -+ /* Forcibly overwrite the data from the keystore */ -+ memset_io(ksdata->base_address + slot * smpriv->slot_size, 0, -+ smpriv->slot_size); -+ -+ ksdata->slot[slot].allocated = 0; -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_dealloc(): slot %d released\n", slot); -+#endif -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+EXPORT_SYMBOL(slot_dealloc); -+ -+void *slot_get_address(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ if (slot >= ksdata->slot_count) -+ return NULL; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot, -+ (u32)ksdata->base_address + slot * smpriv->slot_size); -+#endif -+ -+ return ksdata->base_address + slot * smpriv->slot_size; -+} -+ -+void *slot_get_physical(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ if (slot >= ksdata->slot_count) -+ return NULL; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "%s: slot %d is 0x%08x\n", __func__, slot, -+ (u32)ksdata->phys_address + slot * smpriv->slot_size); -+#endif -+ -+ return ksdata->phys_address + slot * smpriv->slot_size; -+} -+ -+u32 slot_get_base(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ /* -+ * There could potentially be more than one secure partition object -+ * associated with this keystore. For now, there is just one. -+ */ -+ -+ (void)slot; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n", -+ slot, (u32)ksdata->base_address); -+#endif -+ -+ return (uintptr_t)(ksdata->base_address); -+} -+ -+u32 slot_get_offset(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ if (slot >= ksdata->slot_count) -+ return -EINVAL; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot, -+ slot * smpriv->slot_size); -+#endif -+ -+ return slot * smpriv->slot_size; -+} -+ -+u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot, -+ smpriv->slot_size); -+#endif -+ /* All slots are the same size in the default implementation */ -+ return smpriv->slot_size; -+} -+ -+ -+ -+int kso_init_data(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *keystore_data = NULL; -+ u32 slot_count; -+ u32 keystore_data_size; -+ -+ /* -+ * Calculate the required size of the keystore data structure, based -+ * on the number of keys that can fit in the partition. -+ */ -+ slot_count = smpriv->page_size / smpriv->slot_size; -+#ifdef SM_DEBUG -+ dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count); -+#endif -+ -+ keystore_data_size = sizeof(struct keystore_data) + -+ slot_count * -+ sizeof(struct keystore_data_slot_info); -+ -+ keystore_data = kzalloc(keystore_data_size, GFP_KERNEL); -+ -+ if (!keystore_data) -+ return -ENOMEM; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "kso_init_data: keystore data size = %d\n", -+ keystore_data_size); -+#endif -+ -+ /* -+ * Place the slot information structure directly after the keystore data -+ * structure. -+ */ -+ keystore_data->slot = (struct keystore_data_slot_info *) -+ (keystore_data + 1); -+ keystore_data->slot_count = slot_count; -+ -+ smpriv->pagedesc[unit].ksdata = keystore_data; -+ smpriv->pagedesc[unit].ksdata->base_address = -+ smpriv->pagedesc[unit].pg_base; -+ smpriv->pagedesc[unit].ksdata->phys_address = -+ smpriv->pagedesc[unit].pg_phys; -+ -+ return 0; -+} -+ -+void kso_cleanup_data(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *keystore_data = NULL; -+ -+ if (smpriv->pagedesc[unit].ksdata != NULL) -+ keystore_data = smpriv->pagedesc[unit].ksdata; -+ -+ /* Release the allocated keystore management data */ -+ kfree(smpriv->pagedesc[unit].ksdata); -+ -+ return; -+} -+ -+ -+ -+/* -+ * Keystore management section -+ */ -+ -+void sm_init_keystore(struct device *dev) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+ smpriv->data_init = kso_init_data; -+ smpriv->data_cleanup = kso_cleanup_data; -+ smpriv->slot_alloc = slot_alloc; -+ smpriv->slot_dealloc = slot_dealloc; -+ smpriv->slot_get_address = slot_get_address; -+ smpriv->slot_get_physical = slot_get_physical; -+ smpriv->slot_get_base = slot_get_base; -+ smpriv->slot_get_offset = slot_get_offset; -+ smpriv->slot_get_slot_size = slot_get_slot_size; -+#ifdef SM_DEBUG -+ dev_info(dev, "sm_init_keystore(): handlers installed\n"); -+#endif -+} -+EXPORT_SYMBOL(sm_init_keystore); -+ -+/* Return available pages/units */ -+u32 sm_detect_keystore_units(struct device *dev) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+ return smpriv->localpages; -+} -+EXPORT_SYMBOL(sm_detect_keystore_units); -+ -+/* -+ * Do any keystore specific initializations -+ */ -+int sm_establish_keystore(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit); -+#endif -+ -+ if (smpriv->data_init == NULL) -+ return -EINVAL; -+ -+ /* Call the data_init function for any user setup */ -+ return smpriv->data_init(dev, unit); -+} -+EXPORT_SYMBOL(sm_establish_keystore); -+ -+void sm_release_keystore(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit); -+#endif -+ if ((smpriv != NULL) && (smpriv->data_cleanup != NULL)) -+ smpriv->data_cleanup(dev, unit); -+ -+ return; -+} -+EXPORT_SYMBOL(sm_release_keystore); -+ -+/* -+ * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to -+ * the keystore -+ */ -+int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ -+ spin_lock(&smpriv->kslock); -+ -+ if ((smpriv->slot_alloc == NULL) || -+ (smpriv->pagedesc[unit].ksdata == NULL)) -+ goto out; -+ -+ retval = smpriv->slot_alloc(dev, unit, size, slot); -+ -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_alloc); -+ -+int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ -+ spin_lock(&smpriv->kslock); -+ -+ if ((smpriv->slot_alloc == NULL) || -+ (smpriv->pagedesc[unit].ksdata == NULL)) -+ goto out; -+ -+ retval = smpriv->slot_dealloc(dev, unit, slot); -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_dealloc); -+ -+int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, -+ const u8 *key_data, u32 key_length) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ u32 slot_size; -+ u8 __iomem *slot_location; -+ -+ spin_lock(&smpriv->kslock); -+ -+ slot_size = smpriv->slot_get_slot_size(dev, unit, slot); -+ -+ if (key_length > slot_size) { -+ retval = -EFBIG; -+ goto out; -+ } -+ -+ slot_location = smpriv->slot_get_address(dev, unit, slot); -+ -+ memcpy_toio(slot_location, key_data, key_length); -+ -+ retval = 0; -+ -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_load); -+ -+int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, -+ u32 key_length, u8 *key_data) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ u8 __iomem *slot_addr; -+ u32 slot_size; -+ -+ spin_lock(&smpriv->kslock); -+ -+ slot_addr = smpriv->slot_get_address(dev, unit, slot); -+ slot_size = smpriv->slot_get_slot_size(dev, unit, slot); -+ -+ if (key_length > slot_size) { -+ retval = -EKEYREJECTED; -+ goto out; -+ } -+ -+ memcpy_fromio(key_data, slot_addr, key_length); -+ retval = 0; -+ -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_read); -+ -+/* -+ * Blacken a clear key in a slot. Operates "in place". -+ * Limited to class 1 keys at the present time -+ */ -+int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, -+ u16 key_length, u8 keyauth) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = 0; -+ u8 __iomem *slotaddr; -+ void *slotphys; -+ u32 dsize, jstat; -+ u32 __iomem *coverdesc = NULL; -+ -+ /* Get the address of the object in the slot */ -+ slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); -+ slotphys = (u8 *)smpriv->slot_get_physical(dev, unit, slot); -+ -+ dsize = blacken_key_jobdesc(&coverdesc, slotphys, key_length, keyauth); -+ if (!dsize) -+ return -ENOMEM; -+ jstat = sm_key_job(dev, coverdesc); -+ if (jstat) -+ retval = -EIO; -+ -+ kfree(coverdesc); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_cover_key); -+ -+/* Export a black/red key to a blob in external memory */ -+int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, u8 keycolor, -+ u8 keyauth, u8 *outbuf, u16 keylen, u8 *keymod) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = 0; -+ u8 __iomem *slotaddr, *lkeymod; -+ u8 __iomem *slotphys; -+ dma_addr_t keymod_dma, outbuf_dma; -+ u32 dsize, jstat; -+ u32 __iomem *encapdesc = NULL; -+ struct device *dev_for_dma_op; -+ -+ /* Use the ring as device for DMA operations */ -+ dev_for_dma_op = smpriv->smringdev; -+ -+ /* Get the base address(es) of the specified slot */ -+ slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); -+ slotphys = smpriv->slot_get_physical(dev, unit, slot); -+ -+ /* Allocate memory for key modifier compatible with DMA */ -+ lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); -+ if (!lkeymod) { -+ retval = (-ENOMEM); -+ goto exit; -+ } -+ -+ /* Get DMA address for the key modifier */ -+ keymod_dma = dma_map_single(dev_for_dma_op, lkeymod, -+ SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev_for_dma_op, keymod_dma)) { -+ dev_err(dev, "unable to map keymod: %p\n", lkeymod); -+ retval = (-ENOMEM); -+ goto free_keymod; -+ } -+ -+ /* Copy the keymod and synchronize the DMA */ -+ memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); -+ dma_sync_single_for_device(dev_for_dma_op, keymod_dma, -+ SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); -+ -+ /* Get DMA address for the destination */ -+ outbuf_dma = dma_map_single(dev_for_dma_op, outbuf, -+ keylen + BLOB_OVERHEAD, DMA_FROM_DEVICE); -+ if (dma_mapping_error(dev_for_dma_op, outbuf_dma)) { -+ dev_err(dev, "unable to map outbuf: %p\n", outbuf); -+ retval = (-ENOMEM); -+ goto unmap_keymod; -+ } -+ -+ /* Build the encapsulation job descriptor */ -+ dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, slotphys, outbuf_dma, -+ keylen, keycolor, SM_SECMEM, keyauth); -+ if (!dsize) { -+ dev_err(dev, "can't alloc an encapsulation descriptor\n"); -+ retval = -ENOMEM; -+ goto unmap_outbuf; -+ } -+ -+ /* Run the job */ -+ jstat = sm_key_job(dev, encapdesc); -+ if (jstat) { -+ retval = (-EIO); -+ goto free_desc; -+ } -+ -+ /* Synchronize the data received */ -+ dma_sync_single_for_cpu(dev_for_dma_op, outbuf_dma, -+ keylen + BLOB_OVERHEAD, DMA_FROM_DEVICE); -+ -+free_desc: -+ kfree(encapdesc); -+ -+unmap_outbuf: -+ dma_unmap_single(dev_for_dma_op, outbuf_dma, keylen + BLOB_OVERHEAD, -+ DMA_FROM_DEVICE); -+ -+unmap_keymod: -+ dma_unmap_single(dev_for_dma_op, keymod_dma, SECMEM_KEYMOD_LEN, -+ DMA_TO_DEVICE); -+ -+free_keymod: -+ kfree(lkeymod); -+ -+exit: -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_export); -+ -+/* Import a black/red key from a blob residing in external memory */ -+int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, u8 keycolor, -+ u8 keyauth, u8 *inbuf, u16 keylen, u8 *keymod) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = 0; -+ u8 __iomem *slotaddr, *lkeymod; -+ u8 __iomem *slotphys; -+ dma_addr_t keymod_dma, inbuf_dma; -+ u32 dsize, jstat; -+ u32 __iomem *decapdesc = NULL; -+ struct device *dev_for_dma_op; -+ -+ /* Use the ring as device for DMA operations */ -+ dev_for_dma_op = smpriv->smringdev; -+ -+ /* Get the base address(es) of the specified slot */ -+ slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); -+ slotphys = smpriv->slot_get_physical(dev, unit, slot); -+ -+ /* Allocate memory for key modifier compatible with DMA */ -+ lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); -+ if (!lkeymod) { -+ retval = (-ENOMEM); -+ goto exit; -+ } -+ -+ /* Get DMA address for the key modifier */ -+ keymod_dma = dma_map_single(dev_for_dma_op, lkeymod, -+ SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev_for_dma_op, keymod_dma)) { -+ dev_err(dev, "unable to map keymod: %p\n", lkeymod); -+ retval = (-ENOMEM); -+ goto free_keymod; -+ } -+ -+ /* Copy the keymod and synchronize the DMA */ -+ memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); -+ dma_sync_single_for_device(dev_for_dma_op, keymod_dma, -+ SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); -+ -+ /* Get DMA address for the input */ -+ inbuf_dma = dma_map_single(dev_for_dma_op, inbuf, -+ keylen + BLOB_OVERHEAD, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev_for_dma_op, inbuf_dma)) { -+ dev_err(dev, "unable to map inbuf: %p\n", inbuf); -+ retval = (-ENOMEM); -+ goto unmap_keymod; -+ } -+ -+ /* synchronize the DMA */ -+ dma_sync_single_for_device(dev_for_dma_op, inbuf_dma, -+ keylen + BLOB_OVERHEAD, DMA_TO_DEVICE); -+ -+ /* Build the encapsulation job descriptor */ -+ dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, inbuf_dma, slotphys, -+ keylen, keycolor, SM_SECMEM, keyauth); -+ if (!dsize) { -+ dev_err(dev, "can't alloc a decapsulation descriptor\n"); -+ retval = -ENOMEM; -+ goto unmap_inbuf; -+ } -+ -+ /* Run the job */ -+ jstat = sm_key_job(dev, decapdesc); -+ -+ /* -+ * May want to expand upon error meanings a bit. Any CAAM status -+ * is reported as EIO, but we might want to look for something more -+ * meaningful for something like an ICV error on restore, otherwise -+ * the caller is left guessing. -+ */ -+ if (jstat) { -+ retval = (-EIO); -+ goto free_desc; -+ } -+ -+free_desc: -+ kfree(decapdesc); -+ -+unmap_inbuf: -+ dma_unmap_single(dev_for_dma_op, inbuf_dma, keylen + BLOB_OVERHEAD, -+ DMA_TO_DEVICE); -+ -+unmap_keymod: -+ dma_unmap_single(dev_for_dma_op, keymod_dma, SECMEM_KEYMOD_LEN, -+ DMA_TO_DEVICE); -+ -+free_keymod: -+ kfree(lkeymod); -+ -+exit: -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_import); -+ -+/* -+ * Initialization/shutdown subsystem -+ * Assumes statically-invoked startup/shutdown from the controller driver -+ * for the present time, to be reworked when a device tree becomes -+ * available. This code will not modularize in present form. -+ * -+ * Also, simply uses ring 0 for execution at the present -+ */ -+ -+int caam_sm_startup(struct device *ctrldev) -+{ -+ struct device *smdev; -+ struct caam_drv_private *ctrlpriv; -+ struct caam_drv_private_sm *smpriv; -+ struct caam_drv_private_jr *jrpriv; /* need this for reg page */ -+ struct platform_device *sm_pdev; -+ struct sm_page_descriptor *lpagedesc; -+ u32 page, pgstat, lpagect, detectedpage, smvid, smpart; -+ int ret = 0; -+ -+ struct device_node *np; -+ ctrlpriv = dev_get_drvdata(ctrldev); -+ -+ if (!ctrlpriv->sm_present) -+ return 0; -+ -+ /* -+ * Set up the private block for secure memory -+ * Only one instance is possible -+ */ -+ smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL); -+ if (smpriv == NULL) { -+ dev_err(ctrldev, "can't alloc private mem for secure memory\n"); -+ ret = -ENOMEM; -+ goto exit; -+ } -+ smpriv->parentdev = ctrldev; /* copy of parent dev is handy */ -+ spin_lock_init(&smpriv->kslock); -+ -+ /* Create the dev */ -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); -+ if (np) -+ of_node_clear_flag(np, OF_POPULATED); -+ sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev); -+ -+ if (sm_pdev == NULL) { -+ ret = -EINVAL; -+ goto free_smpriv; -+ } -+ -+ /* Save a pointer to the platform device for Secure Memory */ -+ smpriv->sm_pdev = sm_pdev; -+ smdev = &sm_pdev->dev; -+ dev_set_drvdata(smdev, smpriv); -+ ctrlpriv->smdev = smdev; -+ -+ /* Set the Secure Memory Register Map Version */ -+ smvid = rd_reg32(&ctrlpriv->jr[0]->perfmon.smvid); -+ smpart = rd_reg32(&ctrlpriv->jr[0]->perfmon.smpart); -+ -+ if (smvid < SMVID_V2) -+ smpriv->sm_reg_offset = SM_V1_OFFSET; -+ else -+ smpriv->sm_reg_offset = SM_V2_OFFSET; -+ -+ /* -+ * Collect configuration limit data for reference -+ * This batch comes from the partition data/vid registers in perfmon -+ */ -+ smpriv->max_pages = ((smpart & SMPART_MAX_NUMPG_MASK) >> -+ SMPART_MAX_NUMPG_SHIFT) + 1; -+ smpriv->top_partition = ((smpart & SMPART_MAX_PNUM_MASK) >> -+ SMPART_MAX_PNUM_SHIFT) + 1; -+ smpriv->top_page = ((smpart & SMPART_MAX_PG_MASK) >> -+ SMPART_MAX_PG_SHIFT) + 1; -+ smpriv->page_size = 1024 << ((smvid & SMVID_PG_SIZE_MASK) >> -+ SMVID_PG_SIZE_SHIFT); -+ smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE; -+ -+#ifdef SM_DEBUG -+ dev_info(smdev, "max pages = %d, top partition = %d\n", -+ smpriv->max_pages, smpriv->top_partition); -+ dev_info(smdev, "top page = %d, page size = %d (total = %d)\n", -+ smpriv->top_page, smpriv->page_size, -+ smpriv->top_page * smpriv->page_size); -+ dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size); -+#endif -+ -+ /* -+ * Now probe for partitions/pages to which we have access. Note that -+ * these have likely been set up by a bootloader or platform -+ * provisioning application, so we have to assume that we "inherit" -+ * a configuration and work within the constraints of what it might be. -+ * -+ * Assume use of the zeroth ring in the present iteration (until -+ * we can divorce the controller and ring drivers, and then assign -+ * an SM instance to any ring instance). -+ */ -+ smpriv->smringdev = caam_jr_alloc(); -+ if (!smpriv->smringdev) { -+ dev_err(smdev, "Device for job ring not created\n"); -+ ret = -ENODEV; -+ goto unregister_smpdev; -+ } -+ -+ jrpriv = dev_get_drvdata(smpriv->smringdev); -+ lpagect = 0; -+ pgstat = 0; -+ lpagedesc = kzalloc(sizeof(struct sm_page_descriptor) -+ * smpriv->max_pages, GFP_KERNEL); -+ if (lpagedesc == NULL) { -+ ret = -ENOMEM; -+ goto free_smringdev; -+ } -+ -+ for (page = 0; page < smpriv->max_pages; page++) { -+ u32 page_ownership; -+ -+ if (sm_send_cmd(smpriv, jrpriv, -+ ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) | -+ (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK), -+ &pgstat)) { -+ ret = -EINVAL; -+ goto free_lpagedesc; -+ } -+ -+ page_ownership = (pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT; -+ if ((page_ownership == SMCS_PGOWN_OWNED) -+ || (page_ownership == SMCS_PGOWN_NOOWN)) { -+ /* page allocated */ -+ lpagedesc[page].phys_pagenum = -+ (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT; -+ lpagedesc[page].own_part = -+ (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK; -+ lpagedesc[page].pg_base = (u8 *)ctrlpriv->sm_base + -+ (smpriv->page_size * page); -+ if (ctrlpriv->scu_en) { -+/* FIXME: get different addresses viewed by CPU and CAAM from -+ * platform property -+ */ -+ lpagedesc[page].pg_phys = (u8 *)0x20800000 + -+ (smpriv->page_size * page); -+ } else { -+ lpagedesc[page].pg_phys = -+ (u8 *) ctrlpriv->sm_phy + -+ (smpriv->page_size * page); -+ } -+ lpagect++; -+#ifdef SM_DEBUG -+ dev_info(smdev, -+ "physical page %d, owning partition = %d\n", -+ lpagedesc[page].phys_pagenum, -+ lpagedesc[page].own_part); -+#endif -+ } -+ } -+ -+ smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect, -+ GFP_KERNEL); -+ if (smpriv->pagedesc == NULL) { -+ ret = -ENOMEM; -+ goto free_lpagedesc; -+ } -+ smpriv->localpages = lpagect; -+ -+ detectedpage = 0; -+ for (page = 0; page < smpriv->max_pages; page++) { -+ if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */ -+ memcpy(&smpriv->pagedesc[detectedpage], -+ &lpagedesc[page], -+ sizeof(struct sm_page_descriptor)); -+#ifdef SM_DEBUG_CONT -+ sm_show_page(smdev, &smpriv->pagedesc[detectedpage]); -+#endif -+ detectedpage++; -+ } -+ } -+ -+ kfree(lpagedesc); -+ -+ sm_init_keystore(smdev); -+ -+ goto exit; -+ -+free_lpagedesc: -+ kfree(lpagedesc); -+free_smringdev: -+ caam_jr_free(smpriv->smringdev); -+unregister_smpdev: -+ of_device_unregister(smpriv->sm_pdev); -+free_smpriv: -+ kfree(smpriv); -+ -+exit: -+ return ret; -+} -+ -+void caam_sm_shutdown(struct device *ctrldev) -+{ -+ struct device *smdev; -+ struct caam_drv_private *priv; -+ struct caam_drv_private_sm *smpriv; -+ -+ priv = dev_get_drvdata(ctrldev); -+ if (!priv->sm_present) -+ return; -+ -+ smdev = priv->smdev; -+ -+ /* Return if resource not initialized by startup */ -+ if (smdev == NULL) -+ return; -+ -+ smpriv = dev_get_drvdata(smdev); -+ -+ caam_jr_free(smpriv->smringdev); -+ -+ /* Remove Secure Memory Platform Device */ -+ of_device_unregister(smpriv->sm_pdev); -+ -+ kfree(smpriv->pagedesc); -+ kfree(smpriv); -+} -+EXPORT_SYMBOL(caam_sm_shutdown); -diff --git a/drivers/crypto/caam/sm_test.c b/drivers/crypto/caam/sm_test.c -new file mode 100644 -index 000000000..2a84a91a0 ---- /dev/null -+++ b/drivers/crypto/caam/sm_test.c -@@ -0,0 +1,586 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Secure Memory / Keystore Exemplification Module -+ * -+ * Copyright 2012-2015 Freescale Semiconductor, Inc. -+ * Copyright 2016-2019 NXP -+ * -+ * This module has been overloaded as an example to show: -+ * - Secure memory subsystem initialization/shutdown -+ * - Allocation/deallocation of "slots" in a secure memory page -+ * - Loading and unloading of key material into slots -+ * - Covering of secure memory objects into "black keys" (ECB only at present) -+ * - Verification of key covering (by differentiation only) -+ * - Exportation of keys into secure memory blobs (with display of result) -+ * - Importation of keys from secure memory blobs (with display of result) -+ * - Verification of re-imported keys where possible. -+ * -+ * The module does not show the use of key objects as working key register -+ * source material at this time. -+ * -+ * This module can use a substantial amount of refactoring, which may occur -+ * after the API gets some mileage. Furthermore, expect this module to -+ * eventually disappear once the API is integrated into "real" software. -+ */ -+ -+#include "compat.h" -+#include "regs.h" -+#include "intern.h" -+#include "desc.h" -+#include "error.h" -+#include "jr.h" -+#include "sm.h" -+ -+/* Fixed known pattern for a key modifier */ -+static u8 skeymod[] = { -+ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, -+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 -+}; -+ -+/* Fixed known pattern for a key */ -+static u8 clrkey[] = { -+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07, -+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, -+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, -+ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, -+ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, -+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, -+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, -+ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, -+ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, -+ 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, -+ 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, -+ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, -+ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, -+ 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, -+ 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, -+ 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, -+ 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, -+ 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, -+ 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, -+ 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, -+ 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, -+ 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, -+ 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, -+ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, -+ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, -+ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, -+ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, -+ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, -+ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, -+ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff -+}; -+ -+static void key_display(struct device *dev, const char *label, u16 size, -+ u8 *key) -+{ -+ unsigned i; -+ -+ dev_dbg(dev, "%s", label); -+ for (i = 0; i < size; i += 8) -+ dev_dbg(dev, -+ "[%04d] %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ i, key[i], key[i + 1], key[i + 2], key[i + 3], -+ key[i + 4], key[i + 5], key[i + 6], key[i + 7]); -+} -+ -+int caam_sm_example_init(struct platform_device *pdev) -+{ -+ struct device *ctrldev, *ksdev; -+ struct caam_drv_private *ctrlpriv; -+ struct caam_drv_private_sm *kspriv; -+ u32 unit, units; -+ int rtnval; -+ u8 clrkey8[8], clrkey16[16], clrkey24[24], clrkey32[32]; -+ u8 blkkey8[AES_BLOCK_PAD(8)], blkkey16[AES_BLOCK_PAD(16)]; -+ u8 blkkey24[AES_BLOCK_PAD(24)], blkkey32[AES_BLOCK_PAD(32)]; -+ u8 rstkey8[AES_BLOCK_PAD(8)], rstkey16[AES_BLOCK_PAD(16)]; -+ u8 rstkey24[AES_BLOCK_PAD(24)], rstkey32[AES_BLOCK_PAD(32)]; -+ u8 __iomem *blob8, *blob16, *blob24, *blob32; -+ u32 keyslot8, keyslot16, keyslot24, keyslot32 = 0; -+ -+ blob8 = blob16 = blob24 = blob32 = NULL; -+ -+ /* -+ * 3.5.x and later revs for MX6 should be able to ditch this -+ * and detect via dts property -+ */ -+ ctrldev = &pdev->dev; -+ ctrlpriv = dev_get_drvdata(ctrldev); -+ -+ /* -+ * If ctrlpriv is NULL, it's probably because the caam driver wasn't -+ * properly initialized (e.g. RNG4 init failed). Thus, bail out here. -+ */ -+ if (!ctrlpriv) -+ return -ENODEV; -+ -+ ksdev = ctrlpriv->smdev; -+ kspriv = dev_get_drvdata(ksdev); -+ if (kspriv == NULL) -+ return -ENODEV; -+ -+ /* What keystores are available ? */ -+ units = sm_detect_keystore_units(ksdev); -+ if (!units) -+ dev_err(ksdev, "blkkey_ex: no keystore units available\n"); -+ -+ /* -+ * MX6 bootloader stores some stuff in unit 0, so let's -+ * use 1 or above -+ */ -+ if (units < 2) { -+ dev_err(ksdev, "blkkey_ex: insufficient keystore units\n"); -+ return -ENODEV; -+ } -+ unit = 1; -+ -+ dev_info(ksdev, "blkkey_ex: %d keystore units available\n", units); -+ -+ /* Initialize/Establish Keystore */ -+ sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */ -+ -+ /* -+ * Now let's set up buffers for blobs in DMA-able memory. All are -+ * larger than need to be so that blob size can be seen. -+ */ -+ blob8 = kzalloc(128, GFP_KERNEL | GFP_DMA); -+ blob16 = kzalloc(128, GFP_KERNEL | GFP_DMA); -+ blob24 = kzalloc(128, GFP_KERNEL | GFP_DMA); -+ blob32 = kzalloc(128, GFP_KERNEL | GFP_DMA); -+ -+ if ((blob8 == NULL) || (blob16 == NULL) || (blob24 == NULL) || -+ (blob32 == NULL)) { -+ rtnval = -ENOMEM; -+ dev_err(ksdev, "blkkey_ex: can't get blob buffers\n"); -+ goto freemem; -+ } -+ -+ /* Initialize clear keys with a known and recognizable pattern */ -+ memcpy(clrkey8, clrkey, 8); -+ memcpy(clrkey16, clrkey, 16); -+ memcpy(clrkey24, clrkey, 24); -+ memcpy(clrkey32, clrkey, 32); -+ -+ memset(blkkey8, 0, AES_BLOCK_PAD(8)); -+ memset(blkkey16, 0, AES_BLOCK_PAD(16)); -+ memset(blkkey24, 0, AES_BLOCK_PAD(24)); -+ memset(blkkey32, 0, AES_BLOCK_PAD(32)); -+ -+ memset(rstkey8, 0, AES_BLOCK_PAD(8)); -+ memset(rstkey16, 0, AES_BLOCK_PAD(16)); -+ memset(rstkey24, 0, AES_BLOCK_PAD(24)); -+ memset(rstkey32, 0, AES_BLOCK_PAD(32)); -+ -+ /* -+ * Allocate keyslots. Since we're going to blacken keys in-place, -+ * we want slots big enough to pad out to the next larger AES blocksize -+ * so pad them out. -+ */ -+ rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(8), -+ &keyslot8); -+ if (rtnval) -+ goto freemem; -+ -+ rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(16), -+ &keyslot16); -+ if (rtnval) -+ goto dealloc_slot8; -+ -+ rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(24), -+ &keyslot24); -+ if (rtnval) -+ goto dealloc_slot16; -+ -+ rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(32), -+ &keyslot32); -+ if (rtnval) -+ goto dealloc_slot24; -+ -+ -+ /* Now load clear key data into the newly allocated slots */ -+ rtnval = sm_keystore_slot_load(ksdev, unit, keyslot8, clrkey8, 8); -+ if (rtnval) -+ goto dealloc; -+ -+ rtnval = sm_keystore_slot_load(ksdev, unit, keyslot16, clrkey16, 16); -+ if (rtnval) -+ goto dealloc; -+ -+ rtnval = sm_keystore_slot_load(ksdev, unit, keyslot24, clrkey24, 24); -+ if (rtnval) -+ goto dealloc; -+ -+ rtnval = sm_keystore_slot_load(ksdev, unit, keyslot32, clrkey32, 32); -+ if (rtnval) -+ goto dealloc; -+ -+ /* -+ * All cleartext keys are loaded into slots (in an unprotected -+ * partition at this time) -+ * -+ * Cover keys in-place -+ */ -+ rtnval = sm_keystore_cover_key(ksdev, unit, keyslot8, 8, KEY_COVER_ECB); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't cover 64-bit key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_cover_key(ksdev, unit, keyslot16, 16, -+ KEY_COVER_ECB); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't cover 128-bit key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_cover_key(ksdev, unit, keyslot24, 24, -+ KEY_COVER_ECB); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't cover 192-bit key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_cover_key(ksdev, unit, keyslot32, 32, -+ KEY_COVER_ECB); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't cover 256-bit key\n"); -+ goto dealloc; -+ } -+ -+ /* -+ * Keys should be covered and appear sufficiently "random" -+ * as a result of the covering (blackening) process. Assuming -+ * non-secure mode, read them back out for examination; they should -+ * appear as random data, completely differing from the clear -+ * inputs. So, this will read them back from secure memory and -+ * compare them. If they match the clear key, then the covering -+ * operation didn't occur. -+ */ -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), -+ blkkey8); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't read 64-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot16, -+ AES_BLOCK_PAD(16), blkkey16); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't read 128-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot24, -+ AES_BLOCK_PAD(24), blkkey24); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't read 192-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot32, -+ AES_BLOCK_PAD(32), blkkey32); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't read 256-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = -EINVAL; -+ if (!memcmp(blkkey8, clrkey8, 8)) { -+ dev_err(ksdev, "blkkey_ex: 64-bit key cover failed\n"); -+ goto dealloc; -+ } -+ -+ if (!memcmp(blkkey16, clrkey16, 16)) { -+ dev_err(ksdev, "blkkey_ex: 128-bit key cover failed\n"); -+ goto dealloc; -+ } -+ -+ if (!memcmp(blkkey24, clrkey24, 24)) { -+ dev_err(ksdev, "blkkey_ex: 192-bit key cover failed\n"); -+ goto dealloc; -+ } -+ -+ if (!memcmp(blkkey32, clrkey32, 32)) { -+ dev_err(ksdev, "blkkey_ex: 256-bit key cover failed\n"); -+ goto dealloc; -+ } -+ -+ -+ key_display(ksdev, "64-bit clear key:", 8, clrkey8); -+ key_display(ksdev, "64-bit black key:", AES_BLOCK_PAD(8), blkkey8); -+ -+ key_display(ksdev, "128-bit clear key:", 16, clrkey16); -+ key_display(ksdev, "128-bit black key:", AES_BLOCK_PAD(16), blkkey16); -+ -+ key_display(ksdev, "192-bit clear key:", 24, clrkey24); -+ key_display(ksdev, "192-bit black key:", AES_BLOCK_PAD(24), blkkey24); -+ -+ key_display(ksdev, "256-bit clear key:", 32, clrkey32); -+ key_display(ksdev, "256-bit black key:", AES_BLOCK_PAD(32), blkkey32); -+ -+ /* -+ * Now encapsulate all keys as SM blobs out to external memory -+ * Blobs will appear as random-looking blocks of data different -+ * from the original source key, and 48 bytes longer than the -+ * original key, to account for the extra data encapsulated within. -+ */ -+ key_display(ksdev, "64-bit unwritten blob:", 96, blob8); -+ key_display(ksdev, "128-bit unwritten blob:", 96, blob16); -+ key_display(ksdev, "196-bit unwritten blob:", 96, blob24); -+ key_display(ksdev, "256-bit unwritten blob:", 96, blob32); -+ -+ rtnval = sm_keystore_slot_export(ksdev, unit, keyslot8, BLACK_KEY, -+ KEY_COVER_ECB, blob8, 8, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't encapsulate 64-bit key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_export(ksdev, unit, keyslot16, BLACK_KEY, -+ KEY_COVER_ECB, blob16, 16, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't encapsulate 128-bit key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_export(ksdev, unit, keyslot24, BLACK_KEY, -+ KEY_COVER_ECB, blob24, 24, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't encapsulate 192-bit key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_export(ksdev, unit, keyslot32, BLACK_KEY, -+ KEY_COVER_ECB, blob32, 32, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't encapsulate 256-bit key\n"); -+ goto dealloc; -+ } -+ -+ key_display(ksdev, "64-bit black key in blob:", 96, blob8); -+ key_display(ksdev, "128-bit black key in blob:", 96, blob16); -+ key_display(ksdev, "192-bit black key in blob:", 96, blob24); -+ key_display(ksdev, "256-bit black key in blob:", 96, blob32); -+ -+ /* -+ * Now re-import black keys from secure-memory blobs stored -+ * in general memory from the previous operation. Since we are -+ * working with black keys, and since power has not cycled, the -+ * restored black keys should match the original blackened keys -+ * (this would not be true if the blobs were save in some non-volatile -+ * store, and power was cycled between the save and restore) -+ */ -+ rtnval = sm_keystore_slot_import(ksdev, unit, keyslot8, BLACK_KEY, -+ KEY_COVER_ECB, blob8, 8, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't decapsulate 64-bit blob\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_import(ksdev, unit, keyslot16, BLACK_KEY, -+ KEY_COVER_ECB, blob16, 16, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't decapsulate 128-bit blob\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_import(ksdev, unit, keyslot24, BLACK_KEY, -+ KEY_COVER_ECB, blob24, 24, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't decapsulate 196-bit blob\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_import(ksdev, unit, keyslot32, BLACK_KEY, -+ KEY_COVER_ECB, blob32, 32, skeymod); -+ if (rtnval) { -+ dev_err(ksdev, "blkkey_ex: can't decapsulate 256-bit blob\n"); -+ goto dealloc; -+ } -+ -+ -+ /* -+ * Blobs are now restored as black keys. Read those black keys back -+ * for a comparison with the original black key, they should match -+ */ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), -+ rstkey8); -+ if (rtnval) { -+ dev_err(ksdev, -+ "blkkey_ex: can't read restored 64-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot16, -+ AES_BLOCK_PAD(16), rstkey16); -+ if (rtnval) { -+ dev_err(ksdev, -+ "blkkey_ex: can't read restored 128-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot24, -+ AES_BLOCK_PAD(24), rstkey24); -+ if (rtnval) { -+ dev_err(ksdev, -+ "blkkey_ex: can't read restored 196-bit black key\n"); -+ goto dealloc; -+ } -+ -+ rtnval = sm_keystore_slot_read(ksdev, unit, keyslot32, -+ AES_BLOCK_PAD(32), rstkey32); -+ if (rtnval) { -+ dev_err(ksdev, -+ "blkkey_ex: can't read restored 256-bit black key\n"); -+ goto dealloc; -+ } -+ -+ key_display(ksdev, "restored 64-bit black key:", AES_BLOCK_PAD(8), -+ rstkey8); -+ key_display(ksdev, "restored 128-bit black key:", AES_BLOCK_PAD(16), -+ rstkey16); -+ key_display(ksdev, "restored 192-bit black key:", AES_BLOCK_PAD(24), -+ rstkey24); -+ key_display(ksdev, "restored 256-bit black key:", AES_BLOCK_PAD(32), -+ rstkey32); -+ -+ /* -+ * Compare the restored black keys with the original blackened keys -+ * As long as we're operating within the same power cycle, a black key -+ * restored from a blob should match the original black key IF the -+ * key happens to be of a size that matches a multiple of the AES -+ * blocksize. Any key that is padded to fill the block size will not -+ * match, excepting a key that exceeds a block; only the first full -+ * blocks will match (assuming ECB). -+ * -+ * Therefore, compare the 16 and 32 bit keys, they should match. -+ * The 24 bit key can only match within the first 16 byte block. -+ */ -+ -+ if (memcmp(rstkey16, blkkey16, AES_BLOCK_PAD(16))) { -+ dev_err(ksdev, "blkkey_ex: 128-bit restored key mismatch\n"); -+ rtnval = -EINVAL; -+ } -+ -+ /* Only first AES block will match, remainder subject to padding */ -+ if (memcmp(rstkey24, blkkey24, 16)) { -+ dev_err(ksdev, "blkkey_ex: 192-bit restored key mismatch\n"); -+ rtnval = -EINVAL; -+ } -+ -+ if (memcmp(rstkey32, blkkey32, AES_BLOCK_PAD(32))) { -+ dev_err(ksdev, "blkkey_ex: 256-bit restored key mismatch\n"); -+ rtnval = -EINVAL; -+ } -+ -+ -+ /* Remove keys from keystore */ -+dealloc: -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot32); -+dealloc_slot24: -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot24); -+dealloc_slot16: -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot16); -+dealloc_slot8: -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot8); -+ -+ /* Free resources */ -+freemem: -+ kfree(blob8); -+ kfree(blob16); -+ kfree(blob24); -+ kfree(blob32); -+ -+ /* Disconnect from keystore and leave */ -+ sm_release_keystore(ksdev, unit); -+ -+ return rtnval; -+} -+EXPORT_SYMBOL(caam_sm_example_init); -+ -+void caam_sm_example_shutdown(void) -+{ -+ /* unused in present version */ -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ -+ /* -+ * Do of_find_compatible_node() then of_find_device_by_node() -+ * once a functional device tree is available -+ */ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) -+ return; -+ -+ of_node_get(dev_node); -+ -+} -+ -+static int __init caam_sm_test_init(void) -+{ -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ struct caam_drv_private *priv; -+ int ret; -+ -+ /* -+ * Do of_find_compatible_node() then of_find_device_by_node() -+ * once a functional device tree is available -+ */ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return -ENODEV; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) -+ return -ENODEV; -+ -+ of_node_put(dev_node); -+ -+ priv = dev_get_drvdata(&pdev->dev); -+ if (!priv) { -+ dev_info(&pdev->dev, "SM driver not ready, aborting tests\n"); -+ return -ENODEV; -+ } -+ if (!priv->sm_present) { -+ dev_info(&pdev->dev, "No SM support, skipping tests\n"); -+ return -ENODEV; -+ } -+ if (!priv->smdev) { -+ dev_info(&pdev->dev, "SM not initialized (no job rings?) skipping tests\n"); -+ return -ENODEV; -+ } -+ -+ ret = caam_sm_example_init(pdev); -+ if (ret) -+ dev_err(&pdev->dev, "SM test failed: %d\n", ret); -+ else -+ dev_info(&pdev->dev, "SM test passed\n"); -+ -+ return ret; -+} -+ -+ -+/* Module-based initialization needs to wait for dev tree */ -+#ifdef CONFIG_OF -+module_init(caam_sm_test_init); -+module_exit(caam_sm_example_shutdown); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("FSL CAAM Black Key Usage Example"); -+MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); -+#endif -diff --git a/drivers/crypto/caam/snvsregs.h b/drivers/crypto/caam/snvsregs.h -new file mode 100644 -index 000000000..4a7e76933 ---- /dev/null -+++ b/drivers/crypto/caam/snvsregs.h -@@ -0,0 +1,239 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * SNVS hardware register-level view -+ * -+ * Copyright 2012-2015 Freescale Semiconductor, Inc. -+ * Copyright 2016-2019 NXP -+ */ -+ -+#ifndef SNVSREGS_H -+#define SNVSREGS_H -+ -+#include -+#include -+ -+/* -+ * SNVS High Power Domain -+ * Includes security violations, HA counter, RTC, alarm -+ */ -+struct snvs_hp { -+ u32 lock; /* HPLR - HP Lock */ -+ u32 cmd; /* HPCOMR - HP Command */ -+ u32 ctl; /* HPCR - HP Control */ -+ u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */ -+ u32 secvio_ctl; /* HPSVCR - Security Violation Control */ -+ u32 status; /* HPSR - HP Status */ -+ u32 secvio_status; /* HPSVSR - Security Violation Status */ -+ u32 ha_counteriv; /* High Assurance Counter IV */ -+ u32 ha_counter; /* High Assurance Counter */ -+ u32 rtc_msb; /* Real Time Clock/Counter MSB */ -+ u32 rtc_lsb; /* Real Time Counter LSB */ -+ u32 time_alarm_msb; /* Time Alarm MSB */ -+ u32 time_alarm_lsb; /* Time Alarm LSB */ -+}; -+ -+#define HP_LOCK_HAC_LCK 0x00040000 -+#define HP_LOCK_HPSICR_LCK 0x00020000 -+#define HP_LOCK_HPSVCR_LCK 0x00010000 -+#define HP_LOCK_MKEYSEL_LCK 0x00000200 -+#define HP_LOCK_TAMPCFG_LCK 0x00000100 -+#define HP_LOCK_TAMPFLT_LCK 0x00000080 -+#define HP_LOCK_SECVIO_LCK 0x00000040 -+#define HP_LOCK_GENP_LCK 0x00000020 -+#define HP_LOCK_MONOCTR_LCK 0x00000010 -+#define HP_LOCK_CALIB_LCK 0x00000008 -+#define HP_LOCK_SRTC_LCK 0x00000004 -+#define HP_LOCK_ZMK_RD_LCK 0x00000002 -+#define HP_LOCK_ZMK_WT_LCK 0x00000001 -+ -+#define HP_CMD_NONPRIV_AXS 0x80000000 -+#define HP_CMD_HAC_STOP 0x00080000 -+#define HP_CMD_HAC_CLEAR 0x00040000 -+#define HP_CMD_HAC_LOAD 0x00020000 -+#define HP_CMD_HAC_CFG_EN 0x00010000 -+#define HP_CMD_SNVS_MSTR_KEY 0x00002000 -+#define HP_CMD_PROG_ZMK 0x00001000 -+#define HP_CMD_SW_LPSV 0x00000400 -+#define HP_CMD_SW_FSV 0x00000200 -+#define HP_CMD_SW_SV 0x00000100 -+#define HP_CMD_LP_SWR_DIS 0x00000020 -+#define HP_CMD_LP_SWR 0x00000010 -+#define HP_CMD_SSM_SFNS_DIS 0x00000004 -+#define HP_CMD_SSM_ST_DIS 0x00000002 -+#define HP_CMD_SMM_ST 0x00000001 -+ -+#define HP_CTL_TIME_SYNC 0x00010000 -+#define HP_CTL_CAL_VAL_SHIFT 10 -+#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT) -+#define HP_CTL_CALIB_EN 0x00000100 -+#define HP_CTL_PI_FREQ_SHIFT 4 -+#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT) -+#define HP_CTL_PI_EN 0x00000008 -+#define HP_CTL_TIMEALARM_EN 0x00000002 -+#define HP_CTL_RTC_EN 0x00000001 -+ -+#define HP_SECVIO_INTEN_EN 0x10000000 -+#define HP_SECVIO_INTEN_SRC5 0x00000020 -+#define HP_SECVIO_INTEN_SRC4 0x00000010 -+#define HP_SECVIO_INTEN_SRC3 0x00000008 -+#define HP_SECVIO_INTEN_SRC2 0x00000004 -+#define HP_SECVIO_INTEN_SRC1 0x00000002 -+#define HP_SECVIO_INTEN_SRC0 0x00000001 -+#define HP_SECVIO_INTEN_ALL 0x8000003f -+ -+#define HP_SECVIO_ICTL_CFG_SHIFT 30 -+#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT) -+#define HP_SECVIO_ICTL_CFG5_SHIFT 5 -+#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT) -+#define HP_SECVIO_ICTL_CFG_DISABLE 0 -+#define HP_SECVIO_ICTL_CFG_NONFATAL 1 -+#define HP_SECVIO_ICTL_CFG_FATAL 2 -+#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010 -+#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008 -+#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004 -+#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002 -+#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001 -+ -+#define HP_STATUS_ZMK_ZERO 0x80000000 -+#define HP_STATUS_OTPMK_ZERO 0x08000000 -+#define HP_STATUS_OTPMK_SYN_SHIFT 16 -+#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT) -+#define HP_STATUS_SSM_ST_SHIFT 8 -+#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT) -+#define HP_STATUS_SSM_ST_INIT 0 -+#define HP_STATUS_SSM_ST_HARDFAIL 1 -+#define HP_STATUS_SSM_ST_SOFTFAIL 3 -+#define HP_STATUS_SSM_ST_INITINT 8 -+#define HP_STATUS_SSM_ST_CHECK 9 -+#define HP_STATUS_SSM_ST_NONSECURE 11 -+#define HP_STATUS_SSM_ST_TRUSTED 13 -+#define HP_STATUS_SSM_ST_SECURE 15 -+ -+#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */ -+#define HP_SECVIOST_ZMK_SYN_SHIFT 16 -+#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT) -+#define HP_SECVIOST_SECVIO5 0x00000020 -+#define HP_SECVIOST_SECVIO4 0x00000010 -+#define HP_SECVIOST_SECVIO3 0x00000008 -+#define HP_SECVIOST_SECVIO2 0x00000004 -+#define HP_SECVIOST_SECVIO1 0x00000002 -+#define HP_SECVIOST_SECVIO0 0x00000001 -+#define HP_SECVIOST_SECVIOMASK 0x0000003f -+ -+/* -+ * SNVS Low Power Domain -+ * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK -+ */ -+struct snvs_lp { -+ u32 lock; -+ u32 ctl; -+ u32 mstr_key_ctl; /* Master Key Control */ -+ u32 secvio_ctl; /* Security Violation Control */ -+ u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */ -+ u32 tamper_det_cfg; /* Tamper Detectors Configuration */ -+ u32 status; -+ u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */ -+ u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */ -+ u32 time_alarm; /* Time Alarm */ -+ u32 smc_msb; /* Secure Monotonic Counter MSB */ -+ u32 smc_lsb; /* Secure Monotonic Counter LSB */ -+ u32 pwr_glitch_det; /* Power Glitch Detector */ -+ u32 gen_purpose; -+ u32 zmk[8]; /* Zeroizable Master Key */ -+}; -+ -+#define LP_LOCK_MKEYSEL_LCK 0x00000200 -+#define LP_LOCK_TAMPDET_LCK 0x00000100 -+#define LP_LOCK_TAMPFLT_LCK 0x00000080 -+#define LP_LOCK_SECVIO_LCK 0x00000040 -+#define LP_LOCK_GENP_LCK 0x00000020 -+#define LP_LOCK_MONOCTR_LCK 0x00000010 -+#define LP_LOCK_CALIB_LCK 0x00000008 -+#define LP_LOCK_SRTC_LCK 0x00000004 -+#define LP_LOCK_ZMK_RD_LCK 0x00000002 -+#define LP_LOCK_ZMK_WT_LCK 0x00000001 -+ -+#define LP_CTL_CAL_VAL_SHIFT 10 -+#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT) -+#define LP_CTL_CALIB_EN 0x00000100 -+#define LP_CTL_SRTC_INVAL_EN 0x00000010 -+#define LP_CTL_WAKE_INT_EN 0x00000008 -+#define LP_CTL_MONOCTR_EN 0x00000004 -+#define LP_CTL_TIMEALARM_EN 0x00000002 -+#define LP_CTL_SRTC_EN 0x00000001 -+ -+#define LP_MKEYCTL_ZMKECC_SHIFT 8 -+#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT) -+#define LP_MKEYCTL_ZMKECC_EN 0x00000010 -+#define LP_MKEYCTL_ZMKECC_VAL 0x00000008 -+#define LP_MKEYCTL_ZMKECC_PROG 0x00000004 -+#define LP_MKEYCTL_MKSEL_SHIFT 0 -+#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT) -+#define LP_MKEYCTL_MK_OTP 0 -+#define LP_MKEYCTL_MK_ZMK 2 -+#define LP_MKEYCTL_MK_COMB 3 -+ -+#define LP_SECVIO_CTL_SRC5 0x20 -+#define LP_SECVIO_CTL_SRC4 0x10 -+#define LP_SECVIO_CTL_SRC3 0x08 -+#define LP_SECVIO_CTL_SRC2 0x04 -+#define LP_SECVIO_CTL_SRC1 0x02 -+#define LP_SECVIO_CTL_SRC0 0x01 -+ -+#define LP_TAMPFILT_EXT2_EN 0x80000000 -+#define LP_TAMPFILT_EXT2_SHIFT 24 -+#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT) -+#define LP_TAMPFILT_EXT1_EN 0x00800000 -+#define LP_TAMPFILT_EXT1_SHIFT 16 -+#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT) -+#define LP_TAMPFILT_WM_EN 0x00000080 -+#define LP_TAMPFILT_WM_SHIFT 0 -+#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT) -+ -+#define LP_TAMPDET_OSC_BPS 0x10000000 -+#define LP_TAMPDET_VRC_SHIFT 24 -+#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT) -+#define LP_TAMPDET_HTDC_SHIFT 20 -+#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT) -+#define LP_TAMPDET_LTDC_SHIFT 16 -+#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT) -+#define LP_TAMPDET_POR_OBS 0x00008000 -+#define LP_TAMPDET_PFD_OBS 0x00004000 -+#define LP_TAMPDET_ET2_EN 0x00000400 -+#define LP_TAMPDET_ET1_EN 0x00000200 -+#define LP_TAMPDET_WMT2_EN 0x00000100 -+#define LP_TAMPDET_WMT1_EN 0x00000080 -+#define LP_TAMPDET_VT_EN 0x00000040 -+#define LP_TAMPDET_TT_EN 0x00000020 -+#define LP_TAMPDET_CT_EN 0x00000010 -+#define LP_TAMPDET_MCR_EN 0x00000004 -+#define LP_TAMPDET_SRTCR_EN 0x00000002 -+ -+#define LP_STATUS_SECURE -+#define LP_STATUS_NONSECURE -+#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */ -+#define LP_STATUS_EXT_SECVIO 0x00010000 -+#define LP_STATUS_ET2 0x00000400 -+#define LP_STATUS_ET1 0x00000200 -+#define LP_STATUS_WMT2 0x00000100 -+#define LP_STATUS_WMT1 0x00000080 -+#define LP_STATUS_VTD 0x00000040 -+#define LP_STATUS_TTD 0x00000020 -+#define LP_STATUS_CTD 0x00000010 -+#define LP_STATUS_PGD 0x00000008 -+#define LP_STATUS_MCR 0x00000004 -+#define LP_STATUS_SRTCR 0x00000002 -+#define LP_STATUS_LPTA 0x00000001 -+ -+/* Full SNVS register page, including version/options */ -+struct snvs_full { -+ struct snvs_hp hp; -+ struct snvs_lp lp; -+ u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */ -+ -+ /* Version / Revision / Option ID space - end of register page */ -+ u32 vid; /* 0xbf8 HP Version ID (VID 1) */ -+ u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */ -+}; -+ -+#endif /* SNVSREGS_H */ -diff --git a/drivers/crypto/caam/tag_object.c b/drivers/crypto/caam/tag_object.c -new file mode 100644 -index 000000000..53f70129e ---- /dev/null -+++ b/drivers/crypto/caam/tag_object.c -@@ -0,0 +1,164 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright 2018-2020 NXP -+ */ -+ -+#include -+#include -+#include -+ -+#include "tag_object.h" -+#include "desc.h" -+ -+/** -+ * is_key_type - Check if the object is a key -+ * -+ * @type: The object type -+ * -+ * Return: True if the object is a key (of black or red color), -+ * false otherwise -+ */ -+bool is_key_type(u32 type) -+{ -+ /* Check type bitfield from object type */ -+ return ((type >> TAG_OBJ_TYPE_OFFSET) & TAG_OBJ_TYPE_MASK) == 0; -+} -+EXPORT_SYMBOL(is_key_type); -+ -+/** -+ * is_trusted_type - Check if the object is a trusted key -+ * Trusted Descriptor Key Encryption Key (TDKEK) -+ * -+ * @type: The object type -+ * -+ * Return: True if the object is a trusted key, -+ * false otherwise -+ */ -+bool is_trusted_type(u32 type) -+{ -+ /* Check type bitfield from object type */ -+ return ((type >> TAG_OBJ_TK_OFFSET) & TAG_OBJ_TK_MASK) == 1; -+} -+EXPORT_SYMBOL(is_trusted_type); -+ -+/** -+ * is_black_key - Check if the tag object header is a black key -+ * @header: The tag object header configuration -+ * -+ * Return: True if is a black key, false otherwise -+ */ -+bool is_black_key(const struct header_conf *header) -+{ -+ u32 type = header->type; -+ /* Check type and color bitfields from tag object type */ -+ return (type & (BIT(TAG_OBJ_COLOR_OFFSET) | -+ BIT(TAG_OBJ_TYPE_OFFSET))) == BIT(TAG_OBJ_COLOR_OFFSET); -+} -+EXPORT_SYMBOL(is_black_key); -+ -+/** -+ * is_valid_header_conf - Check if the header configuration is valid -+ * @header: The header configuration -+ * -+ * Return: True if the header of the tag object configuration, -+ * has the TAG_OBJECT_MAGIC number and a valid type, -+ * false otherwise -+ */ -+bool is_valid_header_conf(const struct header_conf *header) -+{ -+ return (header->_magic_number == TAG_OBJECT_MAGIC); -+} -+EXPORT_SYMBOL(is_valid_header_conf); -+ -+/** -+ * get_key_conf - Retrieve the key configuration, -+ * meaning the length of the black key and -+ * the KEY command parameters needed for CAAM -+ * @header: The tag object header configuration -+ * @red_key_len: Red key length -+ * @obj_len: Black/Red key/blob length -+ * @load_param: Load parameters for KEY command: -+ * - indicator for encrypted keys: plaintext or black -+ * - indicator for encryption mode: AES-ECB or AES-CCM -+ * - indicator for encryption keys: JDKEK or TDKEK -+ */ -+void get_key_conf(const struct header_conf *header, -+ u32 *red_key_len, u32 *obj_len, u32 *load_param) -+{ -+ *red_key_len = header->red_key_len; -+ *obj_len = header->obj_len; -+ /* Based on the color of the key, set key encryption bit (ENC) */ -+ *load_param = ((header->type >> TAG_OBJ_COLOR_OFFSET) & -+ TAG_OBJ_COLOR_MASK) << KEY_ENC_OFFSET; -+ /* -+ * For red keys, the TK and EKT bits are ignored. -+ * So we set them anyway, to be valid when the key is black. -+ */ -+ *load_param |= ((header->type >> TAG_OBJ_TK_OFFSET) & -+ TAG_OBJ_TK_MASK) << KEY_TK_OFFSET; -+ *load_param |= ((header->type >> TAG_OBJ_EKT_OFFSET) & -+ TAG_OBJ_EKT_MASK) << KEY_EKT_OFFSET; -+} -+EXPORT_SYMBOL(get_key_conf); -+ -+/** -+ * init_tag_object_header - Initialize the tag object header by setting up -+ * the TAG_OBJECT_MAGIC number, tag object version, -+ * a valid type and the object's length -+ * @header: The header configuration to initialize -+ * @version: The tag object version -+ * @type: The tag object type -+ * @red_key_len: The red key length -+ * @obj_len: The object (actual data) length -+ */ -+void init_tag_object_header(struct header_conf *header, u32 version, -+ u32 type, size_t red_key_len, size_t obj_len) -+{ -+ header->_magic_number = TAG_OBJECT_MAGIC; -+ header->version = version; -+ header->type = type; -+ header->red_key_len = red_key_len; -+ header->obj_len = obj_len; -+} -+EXPORT_SYMBOL(init_tag_object_header); -+ -+/** -+ * set_tag_object_header_conf - Set tag object header configuration -+ * @header: The tag object header configuration to set -+ * @buffer: The buffer needed to be tagged -+ * @buf_size: The buffer size -+ * @tag_obj_size: The tagged object size -+ * -+ * Return: '0' on success, error code otherwise -+ */ -+int set_tag_object_header_conf(const struct header_conf *header, -+ void *buffer, size_t buf_size, u32 *tag_obj_size) -+{ -+ /* Retrieve the tag object */ -+ struct tagged_object *tag_obj = (struct tagged_object *)buffer; -+ /* -+ * Requested size for the tagged object is the buffer size -+ * and the header configuration size (TAG_OVERHEAD_SIZE) -+ */ -+ size_t req_size = buf_size + TAG_OVERHEAD_SIZE; -+ -+ /* -+ * Check if the configuration can be set, -+ * based on the size of the tagged object -+ */ -+ if (*tag_obj_size < req_size) -+ return -EINVAL; -+ -+ /* -+ * Buffers might overlap, use memmove to -+ * copy the buffer into the tagged object -+ */ -+ memmove(&tag_obj->object, buffer, buf_size); -+ /* Copy the tag object header configuration into the tagged object */ -+ memcpy(&tag_obj->header, header, TAG_OVERHEAD_SIZE); -+ /* Set tagged object size */ -+ *tag_obj_size = req_size; -+ -+ return 0; -+} -+EXPORT_SYMBOL(set_tag_object_header_conf); -diff --git a/drivers/crypto/caam/tag_object.h b/drivers/crypto/caam/tag_object.h -new file mode 100644 -index 000000000..6c840c30c ---- /dev/null -+++ b/drivers/crypto/caam/tag_object.h -@@ -0,0 +1,111 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * Copyright 2018-2020 NXP -+ */ -+ -+#ifndef _TAG_OBJECT_H_ -+#define _TAG_OBJECT_H_ -+ -+#include -+#include -+ -+/** -+ * Magic number to identify the tag object structure -+ * 0x54 = 'T' -+ * 0x61 = 'a' -+ * 0x67 = 'g' -+ * 0x4f = 'O' -+ */ -+#define TAG_OBJECT_MAGIC 0x5461674f -+#define TAG_OVERHEAD_SIZE sizeof(struct header_conf) -+#define MIN_KEY_SIZE 16 -+#define TAG_MIN_SIZE (MIN_KEY_SIZE + TAG_OVERHEAD_SIZE) -+/* -+ * Tag object type is a bitfield: -+ * -+ * EKT: Encrypted Key Type (AES-ECB or AES-CCM) -+ * TK: Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) -+ * or Trusted Descriptor Key Encryption Key (TDKEK) to -+ * decrypt the key to be loaded into a Key Register). -+ * -+ *| Denomination | Security state | Memory | EKT | TK | Type | Color | -+ *| ------------ | -------------- | ------- | --- | ----- | ---- | ----- | -+ *| bit(s) | 5-6 | 4 | 3 | 2 | 1 | 0 | -+ *| option 0 | non-secure | general | ECB | JDKEK | key | red | -+ *| option 1 | secure | secure | CCM | TDKEK | blob | black | -+ *| option 2 | trusted | | | | | | -+ * -+ * CAAM supports two different Black Key encapsulation schemes, -+ * one intended for quick decryption (uses AES-ECB encryption), -+ * and another intended for high assurance (uses AES-CCM encryption). -+ * -+ * CAAM implements both Trusted and normal (non-Trusted) Black Keys, -+ * which are encrypted with different key-encryption keys. -+ * Both Trusted and normal Descriptors are allowed to encrypt or decrypt -+ * normal Black Keys, but only Trusted Descriptors are allowed to -+ * encrypt or decrypt Trusted Black Keys. -+ */ -+#define TAG_OBJ_COLOR_OFFSET 0 -+#define TAG_OBJ_COLOR_MASK 0x1 -+#define TAG_OBJ_TYPE_OFFSET 1 -+#define TAG_OBJ_TYPE_MASK 0x1 -+#define TAG_OBJ_TK_OFFSET 2 -+#define TAG_OBJ_TK_MASK 0x1 -+#define TAG_OBJ_EKT_OFFSET 3 -+#define TAG_OBJ_EKT_MASK 0x1 -+#define TAG_OBJ_MEM_OFFSET 4 -+#define TAG_OBJ_MEM_MASK 0x1 -+#define TAG_OBJ_SEC_STATE_OFFSET 5 -+ -+/** -+ * struct header_conf - Header configuration structure, which represents -+ * the metadata (or simply a header) applied to the -+ * actual data (e.g. black key) -+ * @_magic_number : A magic number to identify the structure -+ * @version : The version of the data contained (e.g. tag object) -+ * @type : The type of data contained (e.g. black key, blob, etc.) -+ * @red_key_len : Length of the red key to be loaded by CAAM (for key -+ * generation or blob encapsulation) -+ * @obj_len : The total length of the (black/red) object (key/blob), -+ * after encryption/encapsulation -+ */ -+struct header_conf { -+ u32 _magic_number; -+ u32 version; -+ u32 type; -+ u32 red_key_len; -+ u32 obj_len; -+}; -+ -+/** -+ * struct tagged_object - Tag object structure, which represents the metadata -+ * (or simply a header) and the actual data -+ * (e.g. black key) obtained from hardware -+ * @tag : The configuration of the data (e.g. header) -+ * @object : The actual data (e.g. black key) -+ */ -+struct tagged_object { -+ struct header_conf header; -+ char object; -+}; -+ -+bool is_key_type(u32 type); -+ -+bool is_trusted_type(u32 type); -+ -+bool is_black_key(const struct header_conf * const header); -+ -+bool is_black_key(const struct header_conf * const header); -+ -+bool is_valid_header_conf(const struct header_conf *header); -+ -+void get_key_conf(const struct header_conf *header, -+ u32 *red_key_len, u32 *obj_len, u32 *load_param); -+ -+void init_tag_object_header(struct header_conf *header, u32 version, -+ u32 type, size_t red_key_len, size_t obj_len); -+ -+int set_tag_object_header_conf(const struct header_conf *header, -+ void *buffer, size_t obj_size, u32 *to_size); -+ -+#endif /* _TAG_OBJECT_H_ */ -diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c -index 5edc91cdb..37266abbd 100644 ---- a/drivers/crypto/mxs-dcp.c -+++ b/drivers/crypto/mxs-dcp.c -@@ -16,6 +16,10 @@ - #include - #include - -+#ifdef CONFIG_PM_SLEEP -+#include -+#endif -+ - #include - #include - #include -@@ -123,7 +127,10 @@ struct dcp_export_state { - * design of Linux Crypto API. - */ - static struct dcp *global_sdcp; -- -+#ifdef CONFIG_PM_SLEEP -+static uint32_t ctrl_bak; -+static int dcp_vmi_irq_bak, dcp_irq_bak; -+#endif - /* DCP register layout. */ - #define MXS_DCP_CTRL 0x00 - #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23) -@@ -316,6 +323,9 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) - int init = 0; - bool limit_hit = false; - -+ if (!req->cryptlen) -+ return 0; -+ - actx->fill = 0; - - /* Copy the key from the temporary location. */ -@@ -396,9 +406,15 @@ static int dcp_chan_thread_aes(void *data) - - int ret; - -+#ifdef CONFIG_PM_SLEEP -+ set_freezable(); -+#endif - while (!kthread_should_stop()) { - set_current_state(TASK_INTERRUPTIBLE); - -+#ifdef CONFIG_PM_SLEEP -+ try_to_freeze(); -+#endif - spin_lock(&sdcp->lock[chan]); - backlog = crypto_get_backlog(&sdcp->queue[chan]); - arq = crypto_dequeue_request(&sdcp->queue[chan]); -@@ -436,6 +452,10 @@ static int mxs_dcp_block_fallback(struct skcipher_request *req, int enc) - skcipher_request_set_crypt(&rctx->fallback_req, req->src, req->dst, - req->cryptlen, req->iv); - -+#ifdef CONFIG_PM_SLEEP -+set_freezable(); -+try_to_freeze(); -+#endif - if (enc) - ret = crypto_skcipher_encrypt(&rctx->fallback_req); - else -@@ -692,9 +712,15 @@ static int dcp_chan_thread_sha(void *data) - struct crypto_async_request *arq; - int ret; - -+#ifdef CONFIG_PM_SLEEP -+ set_freezable(); -+#endif - while (!kthread_should_stop()) { - set_current_state(TASK_INTERRUPTIBLE); - -+#ifdef CONFIG_PM_SLEEP -+ try_to_freeze(); -+#endif - spin_lock(&sdcp->lock[chan]); - backlog = crypto_get_backlog(&sdcp->queue[chan]); - arq = crypto_dequeue_request(&sdcp->queue[chan]); -@@ -967,6 +993,49 @@ static irqreturn_t mxs_dcp_irq(int irq, void *context) - return IRQ_HANDLED; - } - -+#ifdef CONFIG_PM_SLEEP -+static int mxs_dcp_resume(struct device *dev) -+{ -+ struct dcp *sdcp = global_sdcp; -+ int ret; -+ -+ /* Restart the DCP block */ -+ ret = stmp_reset_block(sdcp->base); -+ if (ret) { -+ dev_err(dev, "Failed reset\n"); -+ clk_disable_unprepare(sdcp->dcp_clk); -+ return ret; -+ } -+ -+ /* Restore control register */ -+ writel(ctrl_bak, sdcp->base + MXS_DCP_CTRL); -+ /* Enable all DCP DMA channels */ -+ writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK, -+ sdcp->base + MXS_DCP_CHANNELCTRL); -+ -+ /* Re-enable DCP interrupts */ -+ enable_irq(dcp_irq_bak); -+ enable_irq(dcp_vmi_irq_bak); -+ -+ return 0; -+} -+ -+static int mxs_dcp_suspend(struct device *dev) -+{ -+ struct dcp *sdcp = global_sdcp; -+ -+ /* Backup control register */ -+ ctrl_bak = readl(sdcp->base + MXS_DCP_CTRL); -+ /* Temporarily disable DCP interrupts */ -+ disable_irq(dcp_irq_bak); -+ disable_irq(dcp_vmi_irq_bak); -+ -+ return 0; -+} -+ -+SIMPLE_DEV_PM_OPS(mxs_dcp_pm_ops, mxs_dcp_suspend, mxs_dcp_resume); -+#endif -+ - static int mxs_dcp_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -986,7 +1055,10 @@ static int mxs_dcp_probe(struct platform_device *pdev) - dcp_irq = platform_get_irq(pdev, 1); - if (dcp_irq < 0) - return dcp_irq; -- -+#ifdef CONFIG_PM_SLEEP -+ dcp_vmi_irq_bak = dcp_vmi_irq; -+ dcp_irq_bak = dcp_irq; -+#endif - sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); - if (!sdcp) - return -ENOMEM; -@@ -1178,6 +1250,9 @@ static struct platform_driver mxs_dcp_driver = { - .driver = { - .name = "mxs-dcp", - .of_match_table = mxs_dcp_dt_ids, -+#ifdef CONFIG_PM_SLEEP -+ .pm = &mxs_dcp_pm_ops -+#endif - }, - }; - -diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c -index b6ae42d59..665ffe9fd 100644 ---- a/drivers/dma-buf/dma-buf.c -+++ b/drivers/dma-buf/dma-buf.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -25,13 +26,11 @@ - #include - #include - #include -+#include - - #include - #include - --#include "dma-buf-sysfs-stats.h" --#include "dma-buf-process-info.h" -- - static inline int is_dma_buf_file(struct file *); - - struct dma_buf_list { -@@ -82,7 +81,6 @@ static void dma_buf_release(struct dentry *dentry) - if (dmabuf->resv == (struct dma_resv *)&dmabuf[1]) - dma_resv_fini(dmabuf->resv); - -- dma_buf_stats_teardown(dmabuf); - module_put(dmabuf->owner); - kfree(dmabuf->name); - kfree(dmabuf); -@@ -377,6 +375,36 @@ static long dma_buf_ioctl(struct file *file, - dmabuf = file->private_data; - - switch (cmd) { -+ case DMA_BUF_IOCTL_PHYS: { -+ struct dma_buf_attachment *attachment = NULL; -+ struct sg_table *sgt = NULL; -+ unsigned long phys = 0; -+ struct device dev; -+ -+ if (!dmabuf || IS_ERR(dmabuf)) { -+ return -EFAULT; -+ } -+ memset(&dev, 0, sizeof(dev)); -+ device_initialize(&dev); -+ dev.coherent_dma_mask = DMA_BIT_MASK(64); -+ dev.dma_mask = &dev.coherent_dma_mask; -+ arch_setup_dma_ops(&dev, 0, 0, NULL, false); -+ attachment = dma_buf_attach(dmabuf, &dev); -+ if (!attachment || IS_ERR(attachment)) { -+ return -EFAULT; -+ } -+ -+ sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL); -+ if (sgt && !IS_ERR(sgt)) { -+ phys = sg_dma_address(sgt->sgl); -+ dma_buf_unmap_attachment(attachment, sgt, -+ DMA_BIDIRECTIONAL); -+ } -+ dma_buf_detach(dmabuf, attachment); -+ if (copy_to_user((void __user *) arg, &phys, sizeof(phys))) -+ return -EFAULT; -+ return 0; -+ } - case DMA_BUF_IOCTL_SYNC: - if (copy_from_user(&sync, (void __user *) arg, sizeof(sync))) - return -EFAULT; -@@ -583,10 +611,6 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) - file->f_mode |= FMODE_LSEEK; - dmabuf->file = file; - -- ret = dma_buf_stats_setup(dmabuf); -- if (ret) -- goto err_sysfs; -- - mutex_init(&dmabuf->lock); - INIT_LIST_HEAD(&dmabuf->attachments); - -@@ -594,17 +618,8 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) - list_add(&dmabuf->list_node, &db_list.head); - mutex_unlock(&db_list.lock); - -- init_dma_buf_task_info(dmabuf); - return dmabuf; - --err_sysfs: -- /* -- * Set file->f_path.dentry->d_fsdata to NULL so that when -- * dma_buf_release() gets invoked by dentry_ops, it exits -- * early before calling the release() dma_buf op. -- */ -- file->f_path.dentry->d_fsdata = NULL; -- fput(file); - err_dmabuf: - kfree(dmabuf); - err_module: -@@ -1304,10 +1319,8 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused) - return ret; - - seq_puts(s, "\nDma-buf Objects:\n"); -- seq_printf(s, "%-8s\t%-8s\t%-8s\t%-8s\texp_name\t%-8s\t" -- "%-16s\t%-16s\t%-16s\n", -- "size", "flags", "mode", "count", "ino", -- "buf_name", "exp_pid", "exp_task_comm"); -+ seq_printf(s, "%-8s\t%-8s\t%-8s\t%-8s\texp_name\t%-8s\n", -+ "size", "flags", "mode", "count", "ino"); - - list_for_each_entry(buf_obj, &db_list.head, list_node) { - -@@ -1315,16 +1328,13 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused) - if (ret) - goto error_unlock; - -- seq_printf(s, "%08zu\t%08x\t%08x\t%08ld\t%s\t%08lu\t%s\t" -- "%-16d\t%-16s\n", -+ seq_printf(s, "%08zu\t%08x\t%08x\t%08ld\t%s\t%08lu\t%s\n", - buf_obj->size, - buf_obj->file->f_flags, buf_obj->file->f_mode, - file_count(buf_obj->file), - buf_obj->exp_name, - file_inode(buf_obj->file)->i_ino, -- buf_obj->name ?: "NULL", -- dma_buf_exp_pid(buf_obj), -- dma_buf_exp_task_comm(buf_obj) ?: "NULL"); -+ buf_obj->name ?: ""); - - robj = buf_obj->resv; - while (true) { -@@ -1405,7 +1415,6 @@ static int dma_buf_init_debugfs(void) - err = PTR_ERR(d); - } - -- dma_buf_process_info_init_debugfs(dma_buf_debugfs_dir); - return err; - } - -@@ -1423,27 +1432,8 @@ static inline void dma_buf_uninit_debugfs(void) - } - #endif - --#ifdef CONFIG_DMABUF_PROCESS_INFO --struct dma_buf *get_dma_buf_from_file(struct file *f) --{ -- if (IS_ERR_OR_NULL(f)) -- return NULL; -- -- if (!is_dma_buf_file(f)) -- return NULL; -- -- return f->private_data; --} --#endif /* CONFIG_DMABUF_PROCESS_INFO */ -- - static int __init dma_buf_init(void) - { -- int ret; -- -- ret = dma_buf_init_sysfs_statistics(); -- if (ret) -- return ret; -- - dma_buf_mnt = kern_mount(&dma_buf_fs_type); - if (IS_ERR(dma_buf_mnt)) - return PTR_ERR(dma_buf_mnt); -@@ -1451,7 +1441,6 @@ static int __init dma_buf_init(void) - mutex_init(&db_list.lock); - INIT_LIST_HEAD(&db_list.head); - dma_buf_init_debugfs(); -- dma_buf_process_info_init_procfs(); - return 0; - } - subsys_initcall(dma_buf_init); -@@ -1460,7 +1449,5 @@ static void __exit dma_buf_deinit(void) - { - dma_buf_uninit_debugfs(); - kern_unmount(dma_buf_mnt); -- dma_buf_uninit_sysfs_statistics(); -- dma_buf_process_info_uninit_procfs(); - } - __exitcall(dma_buf_deinit); -diff --git a/drivers/dma-buf/dma-heap.c b/drivers/dma-buf/dma-heap.c -index 70e410c64..afd22c9db 100644 ---- a/drivers/dma-buf/dma-heap.c -+++ b/drivers/dma-buf/dma-heap.c -@@ -190,18 +190,6 @@ void *dma_heap_get_drvdata(struct dma_heap *heap) - return heap->priv; - } - --/** -- * dma_heap_get_name() - get heap name -- * @heap: DMA-Heap to retrieve private data for -- * -- * Returns: -- * The char* for the heap name. -- */ --const char *dma_heap_get_name(struct dma_heap *heap) --{ -- return heap->name; --} -- - struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) - { - struct dma_heap *heap, *h, *err_ret; -diff --git a/drivers/dma-buf/heaps/Kconfig b/drivers/dma-buf/heaps/Kconfig -index a5eef06c4..3782eeeb9 100644 ---- a/drivers/dma-buf/heaps/Kconfig -+++ b/drivers/dma-buf/heaps/Kconfig -@@ -12,3 +12,11 @@ config DMABUF_HEAPS_CMA - Choose this option to enable dma-buf CMA heap. This heap is backed - by the Contiguous Memory Allocator (CMA). If your system has these - regions, you should say Y here. -+ -+config DMABUF_HEAPS_DSP -+ tristate "DMA-BUF DSP Heap" -+ depends on DMABUF_HEAPS -+ help -+ Choose this option to enable the dsp dmabuf heap. The dsp heap -+ is allocated by gen allocater. it's allocated according the dts. -+ If in doubt, say Y. -diff --git a/drivers/dma-buf/heaps/Makefile b/drivers/dma-buf/heaps/Makefile -index 6e54cdec3..87fcaf8a0 100644 ---- a/drivers/dma-buf/heaps/Makefile -+++ b/drivers/dma-buf/heaps/Makefile -@@ -2,3 +2,4 @@ - obj-y += heap-helpers.o - obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o - obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o -+obj-$(CONFIG_DMABUF_HEAPS_DSP) += dsp_heap.o -diff --git a/drivers/dma-buf/heaps/dsp_heap.c b/drivers/dma-buf/heaps/dsp_heap.c -new file mode 100644 -index 000000000..2c9bb6698 ---- /dev/null -+++ b/drivers/dma-buf/heaps/dsp_heap.c -@@ -0,0 +1,170 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * DMABUF dsp heap exporter -+ * -+ * Copyright 2021 NXP. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct dsp_heap_buffer { -+ struct dma_heap *heap; -+ struct list_head attachments; -+ struct mutex lock; /* mutex lock */ -+}; -+ -+struct dsp_heap { -+ struct dma_heap *heap; -+ phys_addr_t base; -+ phys_addr_t size; -+}; -+ -+static int dsp_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) -+{ -+ struct dsp_heap_buffer *buffer = dmabuf->priv; -+ struct dsp_heap *dsp_heap = dma_heap_get_drvdata(buffer->heap); -+ unsigned long pfn; -+ size_t size; -+ int ret; -+ -+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); -+ -+ size = dsp_heap->size; -+ pfn = dsp_heap->base >> PAGE_SHIFT; -+ -+ ret = remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+static void dsp_heap_dma_buf_release(struct dma_buf *dmabuf) -+{ -+ struct dsp_heap_buffer *buffer = dmabuf->priv; -+ -+ kfree(buffer); -+} -+ -+static struct sg_table *dsp_heap_map_dma_buf(struct dma_buf_attachment *attachment, -+ enum dma_data_direction direction) -+{ -+ return NULL; -+} -+ -+static void dsp_heap_unmap_dma_buf(struct dma_buf_attachment *attachment, -+ struct sg_table *table, -+ enum dma_data_direction direction) -+{ -+} -+ -+static const struct dma_buf_ops dsp_heap_buf_ops = { -+ .mmap = dsp_heap_mmap, -+ .map_dma_buf = dsp_heap_map_dma_buf, -+ .unmap_dma_buf = dsp_heap_unmap_dma_buf, -+ .release = dsp_heap_dma_buf_release, -+}; -+ -+static int dsp_heap_allocate(struct dma_heap *heap, -+ unsigned long len, -+ unsigned long fd_flags, -+ unsigned long heap_flags) -+{ -+ struct dsp_heap *dsp_heap = dma_heap_get_drvdata(heap); -+ DEFINE_DMA_BUF_EXPORT_INFO(exp_info); -+ struct dsp_heap_buffer *buffer; -+ struct dma_buf *dmabuf; -+ int ret; -+ -+ if (len > dsp_heap->size) -+ return -ENOMEM; -+ -+ buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); -+ if (!buffer) -+ return -ENOMEM; -+ -+ INIT_LIST_HEAD(&buffer->attachments); -+ mutex_init(&buffer->lock); -+ buffer->heap = heap; -+ -+ /* create the dmabuf */ -+ exp_info.ops = &dsp_heap_buf_ops; -+ exp_info.size = len; -+ exp_info.flags = fd_flags; -+ exp_info.priv = buffer; -+ dmabuf = dma_buf_export(&exp_info); -+ if (IS_ERR(dmabuf)) { -+ ret = PTR_ERR(dmabuf); -+ return ret; -+ } -+ -+ ret = dma_buf_fd(dmabuf, fd_flags); -+ if (ret < 0) { -+ dma_buf_put(dmabuf); -+ /* just return, as put will call release and that will free */ -+ return ret; -+ } -+ -+ return ret; -+} -+ -+static const struct dma_heap_ops dsp_heap_ops = { -+ .allocate = dsp_heap_allocate, -+}; -+ -+static int dsp_heap_create(void) -+{ -+ struct dma_heap_export_info exp_info; -+ struct dsp_heap *dsp_heap; -+ struct reserved_mem *rmem; -+ struct device_node np; -+ -+ np.full_name = "dsp_reserved_heap"; -+ np.name = "dsp_reserved_heap"; -+ rmem = of_reserved_mem_lookup(&np); -+ if (!rmem) { -+ pr_err("of_reserved_mem_lookup() returned NULL\n"); -+ return 0; -+ } -+ -+ if (rmem->base == 0 || rmem->size == 0) { -+ pr_err("dsp_data base or size is not correct\n"); -+ return -EINVAL; -+ } -+ -+ dsp_heap = kzalloc(sizeof(*dsp_heap), GFP_KERNEL); -+ if (!dsp_heap) -+ return -ENOMEM; -+ -+ dsp_heap->base = rmem->base; -+ dsp_heap->size = rmem->size; -+ -+ exp_info.name = "dsp"; -+ exp_info.ops = &dsp_heap_ops; -+ exp_info.priv = dsp_heap; -+ dsp_heap->heap = dma_heap_add(&exp_info); -+ if (IS_ERR(dsp_heap->heap)) { -+ int ret = PTR_ERR(dsp_heap->heap); -+ -+ kfree(dsp_heap); -+ return ret; -+ } -+ -+ return 0; -+} -+module_init(dsp_heap_create); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/dma-buf/heaps/heap-helpers.c b/drivers/dma-buf/heaps/heap-helpers.c -index 35aa65bbf..d0696cf93 100644 ---- a/drivers/dma-buf/heaps/heap-helpers.c -+++ b/drivers/dma-buf/heaps/heap-helpers.c -@@ -30,7 +30,6 @@ struct dma_buf *heap_helper_export_dmabuf(struct heap_helper_buffer *buffer, - { - DEFINE_DMA_BUF_EXPORT_INFO(exp_info); - -- exp_info.exp_name = dma_heap_get_name(buffer->heap); - exp_info.ops = &heap_helper_ops; - exp_info.size = buffer->size; - exp_info.flags = fd_flags; -diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig -index 08013345d..a2f6bb12f 100644 ---- a/drivers/dma/Kconfig -+++ b/drivers/dma/Kconfig -@@ -228,6 +228,17 @@ config FSL_QDMA - or dequeuing DMA jobs from, different work queues. - This module can be found on NXP Layerscape SoCs. - The qdma driver only work on SoCs with a DPAA hardware block. -+config FSL_EDMA_V3 -+ tristate "Freescale eDMA v3 engine support" -+ depends on OF -+ select DMA_ENGINE -+ select DMA_VIRTUAL_CHANNELS -+ help -+ Support the Freescale eDMA v3 engine with programmable channel. -+ This driver is based on FSL_EDMA but big changes come such as -+ different interrupt for different channel, different register -+ scope for different channel. -+ This module can be found on Freescale i.MX8QM. - - config FSL_RAID - tristate "Freescale RAID engine Support" -@@ -433,6 +444,8 @@ config MXS_DMA - Support the MXS DMA engine. This engine including APBH-DMA - and APBX-DMA is integrated into some Freescale chips. - -+source "drivers/dma/pxp/Kconfig" -+ - config MX3_IPU - bool "MX3x Image Processing Unit support" - depends on ARCH_MXC -diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile -index 948a8da05..908e0c59b 100644 ---- a/drivers/dma/Makefile -+++ b/drivers/dma/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_EDMA) += dw-edma/ - obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o - obj-$(CONFIG_FSL_DMA) += fsldma.o - obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o -+obj-$(CONFIG_FSL_EDMA_V3) += fsl-edma-v3.o - obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o - obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o - obj-$(CONFIG_FSL_RAID) += fsl_raid.o -diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c -index 930ae268c..7bd002c02 100644 ---- a/drivers/dma/fsl-edma-common.c -+++ b/drivers/dma/fsl-edma-common.c -@@ -4,6 +4,7 @@ - // Copyright (c) 2017 Sysam, Angelo Dureghello - - #include -+#include - #include - #include - #include -@@ -160,11 +161,24 @@ EXPORT_SYMBOL_GPL(fsl_edma_free_desc); - int fsl_edma_terminate_all(struct dma_chan *chan) - { - struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); -+ struct edma_regs *regs = &fsl_chan->edma->regs; -+ u32 ch = fsl_chan->vchan.chan.chan_id; - unsigned long flags; -+ int count = 0; - LIST_HEAD(head); - -- spin_lock_irqsave(&fsl_chan->vchan.lock, flags); - fsl_edma_disable_request(fsl_chan); -+ -+ /* -+ * Checking ACTIVE to ensure minor loop stop indeed to prevent the -+ * potential illegal memory write if channel not stopped with buffer -+ * freed. -+ */ -+ while (count++ < EDMA_MINOR_LOOP_TIMEOUT && (EDMA_TCD_CSR_ACTIVE & -+ edma_readw(fsl_chan->edma, ®s->tcd[ch].csr))) -+ udelay(1); -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); - fsl_chan->edesc = NULL; - fsl_chan->idle = true; - vchan_get_all_descriptors(&fsl_chan->vchan, &head); -@@ -310,6 +324,11 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, - return len; - } - -+void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan) -+{ -+ fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true); -+} -+ - enum dma_status fsl_edma_tx_status(struct dma_chan *chan, - dma_cookie_t cookie, struct dma_tx_state *txstate) - { -@@ -319,8 +338,12 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan, - unsigned long flags; - - status = dma_cookie_status(chan, cookie, txstate); -- if (status == DMA_COMPLETE) -+ if (status == DMA_COMPLETE) { -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ txstate->residue = fsl_chan->chn_real_count; -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); - return status; -+ } - - if (!txstate) - return fsl_chan->status; -diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h -index ec1169741..be4a17901 100644 ---- a/drivers/dma/fsl-edma-common.h -+++ b/drivers/dma/fsl-edma-common.h -@@ -58,6 +58,8 @@ - - #define DMAMUX_NR 2 - -+#define EDMA_MINOR_LOOP_TIMEOUT 500 /* us */ -+ - #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ -@@ -126,6 +128,7 @@ struct fsl_edma_chan { - u32 dma_dev_size; - enum dma_data_direction dma_dir; - char chan_name[16]; -+ u32 chn_real_count; - }; - - struct fsl_edma_desc { -@@ -150,6 +153,7 @@ struct fsl_edma_drvdata { - bool mux_swap; - int (*setup_irq)(struct platform_device *pdev, - struct fsl_edma_engine *fsl_edma); -+ u8 txirq_count; - }; - - struct fsl_edma_engine { -@@ -161,7 +165,7 @@ struct fsl_edma_engine { - struct mutex fsl_edma_mutex; - const struct fsl_edma_drvdata *drvdata; - u32 n_chans; -- int txirq; -+ int *txirqs; - int errirq; - bool big_endian; - struct edma_regs regs; -@@ -182,6 +186,14 @@ static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) - return ioread32(addr); - } - -+static inline u32 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr) -+{ -+ if (edma->big_endian) -+ return ioread16be(addr); -+ else -+ return ioread16(addr); -+} -+ - static inline void edma_writeb(struct fsl_edma_engine *edma, - u8 val, void __iomem *addr) - { -@@ -230,6 +242,7 @@ int fsl_edma_pause(struct dma_chan *chan); - int fsl_edma_resume(struct dma_chan *chan); - int fsl_edma_slave_config(struct dma_chan *chan, - struct dma_slave_config *cfg); -+void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan); - enum dma_status fsl_edma_tx_status(struct dma_chan *chan, - dma_cookie_t cookie, struct dma_tx_state *txstate); - struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( -diff --git a/drivers/dma/fsl-edma-v3.c b/drivers/dma/fsl-edma-v3.c -new file mode 100644 -index 000000000..9a6464c80 ---- /dev/null -+++ b/drivers/dma/fsl-edma-v3.c -@@ -0,0 +1,1341 @@ -+/* -+ * drivers/dma/fsl-edma3-v3.c -+ * -+ * Copyright 2017-2018 NXP . -+ * -+ * Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c -+ * but changed to meet the IP change on i.MX8QM: every dma channel is specific -+ * to hardware. For example, channel 14 for LPUART1 receive request and channel -+ * 13 for transmit requesst. The eDMA block can be found on i.MX8QM -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "virt-dma.h" -+ -+#define EDMA_CH_CSR 0x00 -+#define EDMA_CH_ES 0x04 -+#define EDMA_CH_INT 0x08 -+#define EDMA_CH_SBR 0x0C -+#define EDMA_CH_PRI 0x10 -+#define EDMA_CH_MUX 0x14 -+#define EDMA_TCD_SADDR 0x20 -+#define EDMA_TCD_SOFF 0x24 -+#define EDMA_TCD_ATTR 0x26 -+#define EDMA_TCD_NBYTES 0x28 -+#define EDMA_TCD_SLAST 0x2C -+#define EDMA_TCD_DADDR 0x30 -+#define EDMA_TCD_DOFF 0x34 -+#define EDMA_TCD_CITER_ELINK 0x36 -+#define EDMA_TCD_CITER 0x36 -+#define EDMA_TCD_DLAST_SGA 0x38 -+#define EDMA_TCD_CSR 0x3C -+#define EDMA_TCD_BITER_ELINK 0x3E -+#define EDMA_TCD_BITER 0x3E -+ -+#define EDMA_CH_SBR_RD BIT(22) -+#define EDMA_CH_SBR_WR BIT(21) -+#define EDMA_CH_CSR_ERQ BIT(0) -+#define EDMA_CH_CSR_EARQ BIT(1) -+#define EDMA_CH_CSR_EEI BIT(2) -+#define EDMA_CH_CSR_DONE BIT(30) -+#define EDMA_CH_CSR_ACTIVE BIT(31) -+ -+#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) -+#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) -+#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) -+#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) -+#define EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) -+#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) -+#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) -+#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) -+#define EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) -+#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) -+#define EDMA_TCD_ATTR_SSIZE_64BYTE (0x0600) -+#define EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) -+#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) -+#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) -+#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) -+#define EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) -+#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) -+#define EDMA_TCD_ATTR_DSIZE_64BYTE (0x0006) -+ -+#define EDMA_TCD_SOFF_SOFF(x) (x) -+#define EDMA_TCD_NBYTES_NBYTES(x) (x) -+#define EDMA_TCD_NBYTES_MLOFF(x) (x << 10) -+#define EDMA_TCD_NBYTES_DMLOE (1 << 30) -+#define EDMA_TCD_NBYTES_SMLOE (1 << 31) -+#define EDMA_TCD_SLAST_SLAST(x) (x) -+#define EDMA_TCD_DADDR_DADDR(x) (x) -+#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF) -+#define EDMA_TCD_DOFF_DOFF(x) (x) -+#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) -+#define EDMA_TCD_BITER_BITER(x) ((x) & 0x7FFF) -+ -+#define EDMA_TCD_CSR_START BIT(0) -+#define EDMA_TCD_CSR_INT_MAJOR BIT(1) -+#define EDMA_TCD_CSR_INT_HALF BIT(2) -+#define EDMA_TCD_CSR_D_REQ BIT(3) -+#define EDMA_TCD_CSR_E_SG BIT(4) -+#define EDMA_TCD_CSR_E_LINK BIT(5) -+#define EDMA_TCD_CSR_EEOP BIT(6) -+#define EDMA_TCD_CSR_ESDA BIT(7) -+ -+#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ -+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ -+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ -+ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \ -+ BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)) -+ -+#define ARGS_RX BIT(0) -+#define ARGS_REMOTE BIT(1) -+#define ARGS_DFIFO BIT(2) -+ -+/* channel name template define in dts */ -+#define CHAN_PREFIX "edma0-chan" -+#define CHAN_POSFIX "-tx" -+#define CLK_POSFIX "-clk" -+ -+#define EDMA_MINOR_LOOP_TIMEOUT 500 /* us */ -+ -+struct fsl_edma3_hw_tcd { -+ __le32 saddr; -+ __le16 soff; -+ __le16 attr; -+ __le32 nbytes; -+ __le32 slast; -+ __le32 daddr; -+ __le16 doff; -+ __le16 citer; -+ __le32 dlast_sga; -+ __le16 csr; -+ __le16 biter; -+ /* -+ * Store Dest Address if EDMA_TCD_CSR_ESDA enabled which's used as -+ * 'eeop + cyclic'. -+ */ -+ __le32 sda; -+}; -+ -+struct fsl_edma3_sw_tcd { -+ dma_addr_t ptcd; -+ struct fsl_edma3_hw_tcd *vtcd; -+}; -+ -+struct fsl_edma3_slave_config { -+ enum dma_transfer_direction dir; -+ enum dma_slave_buswidth addr_width; -+ u32 dev_addr; -+ u32 dev2_addr; /* source addr for dev2dev */ -+ u32 burst; -+ u32 attr; -+}; -+ -+struct fsl_edma3_chan { -+ struct virt_dma_chan vchan; -+ enum dma_status status; -+ bool idle; -+ struct fsl_edma3_engine *edma3; -+ struct fsl_edma3_desc *edesc; -+ struct fsl_edma3_slave_config fsc; -+ void __iomem *membase; -+ int txirq; -+ int hw_chanid; -+ int priority; -+ int is_rxchan; -+ int is_remote; -+ int is_dfifo; -+ struct dma_pool *tcd_pool; -+ u32 chn_real_count; -+ char txirq_name[32]; -+ struct platform_device *pdev; -+ struct device *dev; -+ struct work_struct issue_worker; -+ u32 srcid; -+ struct clk *clk; -+}; -+ -+struct fsl_edma3_drvdata { -+ bool has_pd; -+ u32 dmamuxs; -+}; -+ -+struct fsl_edma3_desc { -+ struct virt_dma_desc vdesc; -+ struct fsl_edma3_chan *echan; -+ bool iscyclic; -+ unsigned int n_tcds; -+ u32 curidx; -+ struct fsl_edma3_sw_tcd tcd[]; -+}; -+ -+struct fsl_edma3_reg_save { -+ u32 csr; -+ u32 sbr; -+}; -+ -+struct fsl_edma3_engine { -+ struct dma_device dma_dev; -+ unsigned long irqflag; -+ struct mutex fsl_edma3_mutex; -+ u32 n_chans; -+ int errirq; -+ #define MAX_CHAN_NUM 32 -+ struct fsl_edma3_reg_save edma_regs[MAX_CHAN_NUM]; -+ bool swap; /* remote/local swapped on Audio edma */ -+ const struct fsl_edma3_drvdata *drvdata; -+ struct clk *clk_mp; -+ struct fsl_edma3_chan chans[]; -+}; -+ -+ -+static struct fsl_edma3_drvdata fsl_edma_imx8q = { -+ .has_pd = true, -+ .dmamuxs = 0, -+}; -+ -+static struct fsl_edma3_drvdata fsl_edma_imx8ulp = { -+ .has_pd = false, -+ .dmamuxs = 1, -+}; -+ -+static struct fsl_edma3_chan *to_fsl_edma3_chan(struct dma_chan *chan) -+{ -+ return container_of(chan, struct fsl_edma3_chan, vchan.chan); -+} -+ -+static struct fsl_edma3_desc *to_fsl_edma3_desc(struct virt_dma_desc *vd) -+{ -+ return container_of(vd, struct fsl_edma3_desc, vdesc); -+} -+ -+static void fsl_edma3_enable_request(struct fsl_edma3_chan *fsl_chan) -+{ -+ void __iomem *addr = fsl_chan->membase; -+ u32 val; -+ -+ val = readl(addr + EDMA_CH_SBR); -+ /* Remote/local swapped wrongly on iMX8 QM Audio edma */ -+ if (fsl_chan->edma3->swap) { -+ if (!fsl_chan->is_rxchan) -+ val |= EDMA_CH_SBR_RD; -+ else -+ val |= EDMA_CH_SBR_WR; -+ } else { -+ if (fsl_chan->is_rxchan) -+ val |= EDMA_CH_SBR_RD; -+ else -+ val |= EDMA_CH_SBR_WR; -+ } -+ -+ if (fsl_chan->is_remote) -+ val &= ~(EDMA_CH_SBR_RD | EDMA_CH_SBR_WR); -+ -+ writel(val, addr + EDMA_CH_SBR); -+ -+ if (fsl_chan->srcid && !readl(addr + EDMA_CH_MUX)) -+ writel(fsl_chan->srcid, addr + EDMA_CH_MUX); -+ -+ val = readl(addr + EDMA_CH_CSR); -+ -+ val |= EDMA_CH_CSR_ERQ; -+ writel(val, addr + EDMA_CH_CSR); -+} -+ -+static void fsl_edma3_disable_request(struct fsl_edma3_chan *fsl_chan) -+{ -+ void __iomem *addr = fsl_chan->membase; -+ u32 val = readl(addr + EDMA_CH_CSR); -+ -+ if (fsl_chan->srcid) -+ writel(0, addr + EDMA_CH_MUX); -+ -+ val &= ~EDMA_CH_CSR_ERQ; -+ writel(val, addr + EDMA_CH_CSR); -+} -+ -+static unsigned int fsl_edma3_get_tcd_attr(enum dma_slave_buswidth addr_width) -+{ -+ switch (addr_width) { -+ case 1: -+ return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; -+ case 2: -+ return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; -+ case 4: -+ return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; -+ case 8: -+ return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; -+ case 16: -+ return EDMA_TCD_ATTR_SSIZE_16BYTE | EDMA_TCD_ATTR_DSIZE_16BYTE; -+ case 32: -+ return EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE; -+ case 64: -+ return EDMA_TCD_ATTR_SSIZE_64BYTE | EDMA_TCD_ATTR_DSIZE_64BYTE; -+ default: -+ return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; -+ } -+} -+ -+static void fsl_edma3_free_desc(struct virt_dma_desc *vdesc) -+{ -+ struct fsl_edma3_desc *fsl_desc; -+ int i; -+ -+ fsl_desc = to_fsl_edma3_desc(vdesc); -+ for (i = 0; i < fsl_desc->n_tcds; i++) -+ dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, -+ fsl_desc->tcd[i].ptcd); -+ kfree(fsl_desc); -+} -+ -+static int fsl_edma3_terminate_all(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ unsigned long flags; -+ LIST_HEAD(head); -+ u32 val; -+ -+ fsl_edma3_disable_request(fsl_chan); -+ -+ /* -+ * Checking ACTIVE to ensure minor loop stop indeed to prevent the -+ * potential illegal memory write if channel not stopped with buffer -+ * freed. Ignore tx channel since no such risk. -+ */ -+ if (fsl_chan->is_rxchan) -+ readl_poll_timeout_atomic(fsl_chan->membase + EDMA_CH_CSR, val, -+ !(val & EDMA_CH_CSR_ACTIVE), 2, -+ EDMA_MINOR_LOOP_TIMEOUT); -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ fsl_chan->edesc = NULL; -+ fsl_chan->idle = true; -+ fsl_chan->vchan.cyclic = NULL; -+ vchan_get_all_descriptors(&fsl_chan->vchan, &head); -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ vchan_dma_desc_free_list(&fsl_chan->vchan, &head); -+ -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_allow(fsl_chan->dev); -+ -+ return 0; -+} -+ -+static int fsl_edma3_pause(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ if (fsl_chan->edesc) { -+ fsl_edma3_disable_request(fsl_chan); -+ fsl_chan->status = DMA_PAUSED; -+ fsl_chan->idle = true; -+ } -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ -+ return 0; -+} -+ -+static int fsl_edma3_resume(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ if (fsl_chan->edesc) { -+ fsl_edma3_enable_request(fsl_chan); -+ fsl_chan->status = DMA_IN_PROGRESS; -+ fsl_chan->idle = false; -+ } -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ -+ return 0; -+} -+ -+static int fsl_edma3_slave_config(struct dma_chan *chan, -+ struct dma_slave_config *cfg) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ -+ fsl_chan->fsc.dir = cfg->direction; -+ if (cfg->direction == DMA_DEV_TO_MEM) { -+ fsl_chan->fsc.dev_addr = cfg->src_addr; -+ fsl_chan->fsc.addr_width = cfg->src_addr_width; -+ fsl_chan->fsc.burst = cfg->src_maxburst; -+ fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr -+ (cfg->src_addr_width); -+ } else if (cfg->direction == DMA_MEM_TO_DEV) { -+ fsl_chan->fsc.dev_addr = cfg->dst_addr; -+ fsl_chan->fsc.addr_width = cfg->dst_addr_width; -+ fsl_chan->fsc.burst = cfg->dst_maxburst; -+ fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr -+ (cfg->dst_addr_width); -+ } else if (cfg->direction == DMA_DEV_TO_DEV) { -+ fsl_chan->fsc.dev2_addr = cfg->src_addr; -+ fsl_chan->fsc.dev_addr = cfg->dst_addr; -+ fsl_chan->fsc.addr_width = cfg->dst_addr_width; -+ fsl_chan->fsc.burst = cfg->dst_maxburst; -+ fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr -+ (cfg->dst_addr_width); -+ } else { -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, -+ struct virt_dma_desc *vdesc, bool in_progress) -+{ -+ struct fsl_edma3_desc *edesc = fsl_chan->edesc; -+ void __iomem *addr = fsl_chan->membase; -+ enum dma_transfer_direction dir = fsl_chan->fsc.dir; -+ dma_addr_t cur_addr, dma_addr; -+ size_t len, size; -+ int i; -+ -+ /* calculate the total size in this desc */ -+ for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) -+ len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) -+ * le16_to_cpu(edesc->tcd[i].vtcd->biter); -+ -+ if (!in_progress) -+ return len; -+ -+ if (dir == DMA_MEM_TO_DEV) -+ cur_addr = readl(addr + EDMA_TCD_SADDR); -+ else -+ cur_addr = readl(addr + EDMA_TCD_DADDR); -+ -+ /* skip the tcds before curidx in cyclic case */ -+ if (edesc->iscyclic) -+ len -= edesc->curidx * le32_to_cpu(edesc->tcd[0].vtcd->nbytes) -+ * le16_to_cpu(edesc->tcd[0].vtcd->biter); -+ -+ /* figure out the finished and calculate the residue */ -+ for (i = edesc->curidx; i < fsl_chan->edesc->n_tcds; i++) { -+ if (dir == DMA_DEV_TO_MEM) -+ cur_addr = le32_to_cpu(edesc->tcd[i].vtcd->sda); -+ -+ size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) -+ * le16_to_cpu(edesc->tcd[i].vtcd->biter); -+ if (dir == DMA_MEM_TO_DEV) -+ dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); -+ else -+ dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); -+ -+ len -= size; -+ if (cur_addr > dma_addr && cur_addr <= dma_addr + size) { -+ len += dma_addr + size - cur_addr; -+ /* -+ * mark curidx as the start point in the next time -+ * fsl_edma3_desc_residue(called by fsl_edma3_tx_status -+ * commonly per cyclic interrupt/callback) -+ */ -+ if (edesc->iscyclic) -+ edesc->curidx = (i + 1) % edesc->n_tcds; -+ break; -+ } -+ } -+ -+ return len; -+} -+ -+static enum dma_status fsl_edma3_tx_status(struct dma_chan *chan, -+ dma_cookie_t cookie, struct dma_tx_state *txstate) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ struct virt_dma_desc *vdesc; -+ enum dma_status status; -+ unsigned long flags; -+ -+ status = dma_cookie_status(chan, cookie, txstate); -+ if (status == DMA_COMPLETE) { -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ txstate->residue = fsl_chan->chn_real_count; -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ return status; -+ } -+ -+ if (!txstate) -+ return fsl_chan->status; -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); -+ if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) -+ txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, -+ true); -+ else if (fsl_chan->edesc && vdesc) -+ txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, -+ false); -+ else -+ txstate->residue = 0; -+ -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ -+ return fsl_chan->status; -+} -+ -+static void fsl_edma3_set_tcd_regs(struct fsl_edma3_chan *fsl_chan, -+ struct fsl_edma3_hw_tcd *tcd) -+{ -+ void __iomem *addr = fsl_chan->membase; -+ /* -+ * TCD parameters are stored in struct fsl_edma3_hw_tcd in little -+ * endian format. However, we need to load the TCD registers in -+ * big- or little-endian obeying the eDMA engine model endian. -+ */ -+ writew(0, addr + EDMA_TCD_CSR); -+ writel(le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR); -+ writel(le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR); -+ -+ writew(le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR); -+ writew(le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF); -+ -+ writel(le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES); -+ writel(le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST); -+ -+ writew(le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER); -+ writew(le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER); -+ writew(le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF); -+ -+ writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA); -+ -+ /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */ -+ writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR); -+ -+ writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR); -+} -+ -+static inline -+void fsl_edma3_fill_tcd(struct fsl_edma3_chan *fsl_chan, -+ struct fsl_edma3_sw_tcd *sw_tcd, u32 src, u32 dst, -+ u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, -+ u16 biter, u16 doff, u32 dlast_sga, bool major_int, -+ bool disable_req, bool enable_sg) -+{ -+ struct fsl_edma3_hw_tcd *tcd = sw_tcd->vtcd; -+ u32 slast_sda = sw_tcd->ptcd + offsetof(struct fsl_edma3_hw_tcd, sda); -+ u16 csr = 0; -+ -+ /* -+ * eDMA hardware SGs require the TCDs to be stored in little -+ * endian format irrespective of the register endian model. -+ * So we put the value in little endian in memory, waiting -+ * for fsl_edma3_set_tcd_regs doing the swap. -+ */ -+ tcd->saddr = cpu_to_le32(src); -+ tcd->daddr = cpu_to_le32(dst); -+ -+ tcd->attr = cpu_to_le16(attr); -+ -+ tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff)); -+ -+ if (fsl_chan->is_dfifo) { -+ /* set mloff as -8 */ -+ nbytes |= EDMA_TCD_NBYTES_MLOFF(-8); -+ /* enable DMLOE/SMLOE */ -+ if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { -+ nbytes |= EDMA_TCD_NBYTES_DMLOE; -+ nbytes &= ~EDMA_TCD_NBYTES_SMLOE; -+ } else { -+ nbytes |= EDMA_TCD_NBYTES_SMLOE; -+ nbytes &= ~EDMA_TCD_NBYTES_DMLOE; -+ } -+ } -+ -+ tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes)); -+ -+ if (fsl_chan->is_rxchan) -+ tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast_sda)); -+ else -+ tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast)); -+ -+ tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); -+ tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff)); -+ -+ tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga)); -+ -+ tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); -+ if (major_int) -+ csr |= EDMA_TCD_CSR_INT_MAJOR; -+ -+ if (disable_req) -+ csr |= EDMA_TCD_CSR_D_REQ; -+ -+ if (enable_sg) -+ csr |= EDMA_TCD_CSR_E_SG; -+ -+ if (fsl_chan->is_rxchan) -+ csr |= EDMA_TCD_CSR_EEOP | EDMA_TCD_CSR_ESDA; -+ -+ tcd->csr = cpu_to_le16(csr); -+} -+ -+static struct fsl_edma3_desc *fsl_edma3_alloc_desc(struct fsl_edma3_chan -+ *fsl_chan, int sg_len) -+{ -+ struct fsl_edma3_desc *fsl_desc; -+ int i; -+ -+ fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma3_sw_tcd) -+ * sg_len, GFP_ATOMIC); -+ if (!fsl_desc) -+ return NULL; -+ -+ fsl_desc->echan = fsl_chan; -+ fsl_desc->n_tcds = sg_len; -+ for (i = 0; i < sg_len; i++) { -+ fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, -+ GFP_ATOMIC, &fsl_desc->tcd[i].ptcd); -+ if (!fsl_desc->tcd[i].vtcd) -+ goto err; -+ } -+ return fsl_desc; -+ -+err: -+ while (--i >= 0) -+ dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, -+ fsl_desc->tcd[i].ptcd); -+ kfree(fsl_desc); -+ return NULL; -+} -+ -+static struct dma_async_tx_descriptor *fsl_edma3_prep_dma_cyclic( -+ struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, -+ size_t period_len, enum dma_transfer_direction direction, -+ unsigned long flags) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ struct fsl_edma3_desc *fsl_desc; -+ dma_addr_t dma_buf_next; -+ int sg_len, i; -+ u32 src_addr, dst_addr, last_sg, nbytes; -+ u16 soff, doff, iter; -+ bool major_int = true; -+ -+ sg_len = buf_len / period_len; -+ fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); -+ if (!fsl_desc) -+ return NULL; -+ fsl_desc->iscyclic = true; -+ -+ dma_buf_next = dma_addr; -+ nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; -+ -+ /* -+ * Choose the suitable burst length if period_len is not multiple of -+ * burst length so that the whole transfer length is multiple of minor -+ * loop(burst length). -+ */ -+ if (period_len % nbytes) { -+ u32 width = fsl_chan->fsc.addr_width; -+ -+ for (i = fsl_chan->fsc.burst; i > 1; i--) { -+ if (!(period_len % (i * width))) { -+ nbytes = i * width; -+ break; -+ } -+ } -+ /* if no chance to get suitable burst size, use it as 1 */ -+ if (i == 1) -+ nbytes = width; -+ } -+ -+ iter = period_len / nbytes; -+ -+ for (i = 0; i < sg_len; i++) { -+ if (dma_buf_next >= dma_addr + buf_len) -+ dma_buf_next = dma_addr; -+ -+ /* get next sg's physical address */ -+ last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; -+ -+ if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { -+ src_addr = dma_buf_next; -+ dst_addr = fsl_chan->fsc.dev_addr; -+ soff = fsl_chan->fsc.addr_width; -+ if (fsl_chan->is_dfifo) -+ doff = 4; -+ else -+ doff = 0; -+ } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { -+ src_addr = fsl_chan->fsc.dev_addr; -+ dst_addr = dma_buf_next; -+ if (fsl_chan->is_dfifo) -+ soff = 4; -+ else -+ soff = 0; -+ doff = fsl_chan->fsc.addr_width; -+ } else { -+ /* DMA_DEV_TO_DEV */ -+ src_addr = fsl_chan->fsc.dev2_addr; -+ dst_addr = fsl_chan->fsc.dev_addr; -+ soff = 0; -+ doff = 0; -+ major_int = false; -+ } -+ -+ fsl_edma3_fill_tcd(fsl_chan, &fsl_desc->tcd[i], src_addr, -+ dst_addr, fsl_chan->fsc.attr, soff, nbytes, 0, -+ iter, iter, doff, last_sg, major_int, false, true); -+ dma_buf_next += period_len; -+ } -+ -+ fsl_desc->curidx = 0; -+ -+ return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); -+} -+ -+static struct dma_async_tx_descriptor *fsl_edma3_prep_slave_sg( -+ struct dma_chan *chan, struct scatterlist *sgl, -+ unsigned int sg_len, enum dma_transfer_direction direction, -+ unsigned long flags, void *context) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ struct fsl_edma3_desc *fsl_desc; -+ struct scatterlist *sg; -+ u32 src_addr, dst_addr, last_sg, nbytes; -+ u16 soff, doff, iter; -+ int i; -+ -+ if (!is_slave_direction(fsl_chan->fsc.dir)) -+ return NULL; -+ -+ fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); -+ if (!fsl_desc) -+ return NULL; -+ fsl_desc->iscyclic = false; -+ -+ nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; -+ for_each_sg(sgl, sg, sg_len, i) { -+ /* get next sg's physical address */ -+ last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; -+ -+ if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { -+ src_addr = sg_dma_address(sg); -+ dst_addr = fsl_chan->fsc.dev_addr; -+ soff = fsl_chan->fsc.addr_width; -+ doff = 0; -+ } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { -+ src_addr = fsl_chan->fsc.dev_addr; -+ dst_addr = sg_dma_address(sg); -+ soff = 0; -+ doff = fsl_chan->fsc.addr_width; -+ } else { -+ /* DMA_DEV_TO_DEV */ -+ src_addr = fsl_chan->fsc.dev2_addr; -+ dst_addr = fsl_chan->fsc.dev_addr; -+ soff = 0; -+ doff = 0; -+ } -+ -+ /* -+ * Choose the suitable burst length if sg_dma_len is not -+ * multiple of burst length so that the whole transfer length is -+ * multiple of minor loop(burst length). -+ */ -+ if (sg_dma_len(sg) % nbytes) { -+ u32 width = fsl_chan->fsc.addr_width; -+ int j; -+ -+ for (j = fsl_chan->fsc.burst; j > 1; j--) { -+ if (!(sg_dma_len(sg) % (j * width))) { -+ nbytes = j * width; -+ break; -+ } -+ } -+ /* Set burst size as 1 if there's no suitable one */ -+ if (j == 1) -+ nbytes = width; -+ } -+ -+ iter = sg_dma_len(sg) / nbytes; -+ if (i < sg_len - 1) { -+ last_sg = fsl_desc->tcd[(i + 1)].ptcd; -+ fsl_edma3_fill_tcd(fsl_chan, &fsl_desc->tcd[i], -+ src_addr, dst_addr, fsl_chan->fsc.attr, -+ soff, nbytes, 0, iter, iter, doff, -+ last_sg, false, false, true); -+ } else { -+ last_sg = 0; -+ fsl_edma3_fill_tcd(fsl_chan, &fsl_desc->tcd[i], -+ src_addr, dst_addr, fsl_chan->fsc.attr, -+ soff, nbytes, 0, iter, iter, doff, -+ last_sg, true, true, false); -+ } -+ } -+ -+ return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); -+} -+ -+static void fsl_edma3_xfer_desc(struct fsl_edma3_chan *fsl_chan) -+{ -+ struct virt_dma_desc *vdesc; -+ -+ vdesc = vchan_next_desc(&fsl_chan->vchan); -+ if (!vdesc) -+ return; -+ fsl_chan->edesc = to_fsl_edma3_desc(vdesc); -+ -+ fsl_edma3_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); -+ fsl_edma3_enable_request(fsl_chan); -+ fsl_chan->status = DMA_IN_PROGRESS; -+ fsl_chan->idle = false; -+} -+ -+static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, -+ struct virt_dma_desc *vdesc, bool in_progress); -+ -+static void fsl_edma3_get_realcnt(struct fsl_edma3_chan *fsl_chan) -+{ -+ fsl_chan->chn_real_count = fsl_edma3_desc_residue(fsl_chan, NULL, true); -+} -+ -+static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) -+{ -+ struct fsl_edma3_chan *fsl_chan = dev_id; -+ unsigned int intr; -+ void __iomem *base_addr; -+ -+ spin_lock(&fsl_chan->vchan.lock); -+ -+ /* Ignore this interrupt since channel has been freeed with power off */ -+ if (!fsl_chan->edesc && !fsl_chan->tcd_pool) -+ goto irq_handled; -+ -+ base_addr = fsl_chan->membase; -+ -+ intr = readl(base_addr + EDMA_CH_INT); -+ if (!intr) -+ goto irq_handled; -+ -+ writel(1, base_addr + EDMA_CH_INT); -+ -+ /* Ignore this interrupt since channel has been disabled already */ -+ if (!fsl_chan->edesc) -+ goto irq_handled; -+ -+ if (!fsl_chan->edesc->iscyclic) { -+ fsl_edma3_get_realcnt(fsl_chan); -+ list_del(&fsl_chan->edesc->vdesc.node); -+ vchan_cookie_complete(&fsl_chan->edesc->vdesc); -+ fsl_chan->edesc = NULL; -+ fsl_chan->status = DMA_COMPLETE; -+ fsl_chan->idle = true; -+ } else { -+ vchan_cyclic_callback(&fsl_chan->edesc->vdesc); -+ } -+ -+ if (!fsl_chan->edesc) -+ fsl_edma3_xfer_desc(fsl_chan); -+irq_handled: -+ spin_unlock(&fsl_chan->vchan.lock); -+ -+ return IRQ_HANDLED; -+} -+ -+static void fsl_edma3_issue_pending(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ -+ schedule_work(&fsl_chan->issue_worker); -+} -+ -+static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, -+ struct of_dma *ofdma) -+{ -+ struct fsl_edma3_engine *fsl_edma3 = ofdma->of_dma_data; -+ struct dma_chan *chan, *_chan; -+ struct fsl_edma3_chan *fsl_chan; -+ -+ if (dma_spec->args_count != 3) -+ return NULL; -+ -+ mutex_lock(&fsl_edma3->fsl_edma3_mutex); -+ list_for_each_entry_safe(chan, _chan, &fsl_edma3->dma_dev.channels, -+ device_node) { -+ if (chan->client_count) -+ continue; -+ -+ fsl_chan = to_fsl_edma3_chan(chan); -+ if (fsl_edma3->drvdata->dmamuxs == 0 && -+ fsl_chan->hw_chanid == dma_spec->args[0]) { -+ chan = dma_get_slave_channel(chan); -+ chan->device->privatecnt++; -+ fsl_chan->priority = dma_spec->args[1]; -+ fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; -+ fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; -+ fsl_chan->is_dfifo = dma_spec->args[2] & ARGS_DFIFO; -+ mutex_unlock(&fsl_edma3->fsl_edma3_mutex); -+ return chan; -+ } else if (fsl_edma3->drvdata->dmamuxs && !fsl_chan->srcid) { -+ chan = dma_get_slave_channel(chan); -+ chan->device->privatecnt++; -+ fsl_chan->priority = dma_spec->args[1]; -+ fsl_chan->srcid = dma_spec->args[0]; -+ fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; -+ fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; -+ fsl_chan->is_dfifo = dma_spec->args[2] & ARGS_DFIFO; -+ mutex_unlock(&fsl_edma3->fsl_edma3_mutex); -+ return chan; -+ } -+ } -+ mutex_unlock(&fsl_edma3->fsl_edma3_mutex); -+ return NULL; -+} -+ -+static int fsl_edma3_alloc_chan_resources(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ struct platform_device *pdev = fsl_chan->pdev; -+ int ret; -+ -+ clk_prepare_enable(fsl_chan->clk); -+ -+ fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, -+ sizeof(struct fsl_edma3_hw_tcd), -+ 32, 0); -+ -+ if (fsl_chan->edma3->drvdata->has_pd) { -+ pm_runtime_get_sync(fsl_chan->dev); -+ /* clear meaningless pending irq anyway */ -+ if (readl(fsl_chan->membase + EDMA_CH_INT)) -+ writel(1, fsl_chan->membase + EDMA_CH_INT); -+ } -+ -+ ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, -+ fsl_edma3_tx_handler, fsl_chan->edma3->irqflag, -+ fsl_chan->txirq_name, fsl_chan); -+ if (ret) { -+ dev_err(&pdev->dev, "Can't register %s IRQ.\n", -+ fsl_chan->txirq_name); -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_put_sync_suspend(fsl_chan->dev); -+ -+ return ret; -+ } -+ -+ if (fsl_chan->edma3->drvdata->has_pd) { -+ pm_runtime_mark_last_busy(fsl_chan->dev); -+ pm_runtime_put_autosuspend(fsl_chan->dev); -+ } -+ -+ return 0; -+} -+ -+static void fsl_edma3_free_chan_resources(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ unsigned long flags; -+ LIST_HEAD(head); -+ -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_get_sync(fsl_chan->dev); -+ -+ devm_free_irq(&fsl_chan->pdev->dev, fsl_chan->txirq, fsl_chan); -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ fsl_edma3_disable_request(fsl_chan); -+ fsl_chan->edesc = NULL; -+ vchan_get_all_descriptors(&fsl_chan->vchan, &head); -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ -+ vchan_dma_desc_free_list(&fsl_chan->vchan, &head); -+ dma_pool_destroy(fsl_chan->tcd_pool); -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ fsl_chan->tcd_pool = NULL; -+ fsl_chan->srcid = 0; -+ /* Clear interrupt before power off */ -+ if (readl(fsl_chan->membase + EDMA_CH_INT)) -+ writel(1, fsl_chan->membase + EDMA_CH_INT); -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_put_sync_suspend(fsl_chan->dev); -+ -+ clk_disable_unprepare(fsl_chan->clk); -+} -+ -+static void fsl_edma3_synchronize(struct dma_chan *chan) -+{ -+ struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); -+ -+ vchan_synchronize(&fsl_chan->vchan); -+} -+ -+static struct device *fsl_edma3_attach_pd(struct device *dev, -+ struct device_node *np, int index) -+{ -+ const char *domn = "edma0-chan01"; -+ struct device *pd_chan; -+ struct device_link *link; -+ int ret; -+ -+ ret = of_property_read_string_index(np, "power-domain-names", index, -+ &domn); -+ if (ret) { -+ dev_err(dev, "parse power-domain-names error.(%d)\n", ret); -+ return NULL; -+ } -+ -+ pd_chan = dev_pm_domain_attach_by_name(dev, domn); -+ if (IS_ERR_OR_NULL(pd_chan)) -+ return NULL; -+ -+ link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | -+ DL_FLAG_PM_RUNTIME | -+ DL_FLAG_RPM_ACTIVE); -+ if (IS_ERR(link)) { -+ dev_err(dev, "Failed to add device_link to %s: %ld\n", domn, -+ PTR_ERR(link)); -+ return NULL; -+ } -+ -+ return pd_chan; -+} -+ -+static void fsl_edma3_issue_work(struct work_struct *work) -+{ -+ struct fsl_edma3_chan *fsl_chan = container_of(work, -+ struct fsl_edma3_chan, -+ issue_worker); -+ unsigned long flags; -+ -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_forbid(fsl_chan->dev); -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ -+ if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) -+ fsl_edma3_xfer_desc(fsl_chan); -+ -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+} -+ -+static const struct of_device_id fsl_edma3_dt_ids[] = { -+ { .compatible = "fsl,imx8qm-edma", .data = &fsl_edma_imx8q}, -+ { .compatible = "fsl,imx8qm-adma", .data = &fsl_edma_imx8q}, -+ { .compatible = "fsl,imx8ulp-edma", .data = &fsl_edma_imx8ulp}, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, fsl_edma3_dt_ids); -+ -+static int fsl_edma3_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *of_id = -+ of_match_device(fsl_edma3_dt_ids, &pdev->dev); -+ struct fsl_edma3_engine *fsl_edma3; -+ struct fsl_edma3_chan *fsl_chan; -+ struct resource *res_mp; -+ struct resource *res; -+ int len, chans; -+ int ret, i; -+ -+ if (!of_id) -+ return -EINVAL; -+ -+ ret = of_property_read_u32(np, "dma-channels", &chans); -+ if (ret) { -+ dev_err(&pdev->dev, "Can't get dma-channels.\n"); -+ return ret; -+ } -+ -+ len = sizeof(*fsl_edma3) + sizeof(*fsl_chan) * chans; -+ fsl_edma3 = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); -+ if (!fsl_edma3) -+ return -ENOMEM; -+ -+ /* Audio edma rx/tx channel shared interrupt */ -+ if (of_property_read_bool(np, "shared-interrupt")) -+ fsl_edma3->irqflag = IRQF_SHARED; -+ -+ fsl_edma3->swap = of_device_is_compatible(np, "fsl,imx8qm-adma"); -+ fsl_edma3->n_chans = chans; -+ fsl_edma3->drvdata = (const struct fsl_edma3_drvdata *)of_id->data; -+ -+ INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels); -+ -+ res_mp = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ fsl_edma3->clk_mp = devm_clk_get_optional(&pdev->dev, "edma-mp-clk"); -+ if (IS_ERR(fsl_edma3->clk_mp)) { -+ dev_err(&pdev->dev, "Can't get mp clk.\n"); -+ return PTR_ERR(fsl_edma3->clk_mp); -+ } -+ clk_prepare_enable(fsl_edma3->clk_mp); -+ -+ for (i = 0; i < fsl_edma3->n_chans; i++) { -+ struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; -+ const char *txirq_name; -+ char chanid[3], id_len = 0; -+ char clk_name[18]; -+ char *p = chanid; -+ unsigned long val; -+ -+ fsl_chan->edma3 = fsl_edma3; -+ fsl_chan->pdev = pdev; -+ fsl_chan->idle = true; -+ fsl_chan->srcid = 0; -+ /* Get per channel membase */ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, i + 1); -+ fsl_chan->membase = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(fsl_chan->membase)) -+ return PTR_ERR(fsl_chan->membase); -+ -+ /* Get the hardware chanel id by the channel membase -+ * channel0:0x10000, channel1:0x20000... total 32 channels -+ * Note: skip first res_mp which we don't care. -+ */ -+ fsl_chan->hw_chanid = ((res->start - res_mp->start) >> 16) & 0x3f; -+ fsl_chan->hw_chanid--; -+ -+ ret = of_property_read_string_index(np, "interrupt-names", i, -+ &txirq_name); -+ if (ret) { -+ dev_err(&pdev->dev, "read interrupt-names fail.\n"); -+ return ret; -+ } -+ /* Get channel id length from dts, one-digit or double-digit */ -+ id_len = strlen(txirq_name) - strlen(CHAN_PREFIX) - -+ strlen(CHAN_POSFIX); -+ if (id_len > 2) { -+ dev_err(&pdev->dev, "%s is edmaX-chanX-tx in dts?\n", -+ res->name); -+ return -EINVAL; -+ } -+ /* Grab channel id from txirq_name */ -+ strncpy(p, txirq_name + strlen(CHAN_PREFIX), id_len); -+ *(p + id_len) = '\0'; -+ -+ /* check if the channel id match well with hw_chanid */ -+ ret = kstrtoul(chanid, 0, &val); -+ if (ret || val != fsl_chan->hw_chanid) { -+ dev_err(&pdev->dev, "%s,wrong id?\n", txirq_name); -+ return -EINVAL; -+ } -+ -+ /* request channel irq */ -+ fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name); -+ if (fsl_chan->txirq < 0) { -+ dev_err(&pdev->dev, "Can't get %s irq.\n", txirq_name); -+ return fsl_chan->txirq; -+ } -+ -+ memcpy(fsl_chan->txirq_name, txirq_name, strlen(txirq_name)); -+ -+ strncpy(clk_name, txirq_name, strlen(CHAN_PREFIX) + id_len); -+ strcpy(clk_name + strlen(CHAN_PREFIX) + id_len, CLK_POSFIX); -+ fsl_chan->clk = devm_clk_get_optional(&pdev->dev, -+ (const char *)clk_name); -+ if (IS_ERR(fsl_chan->clk)) -+ return PTR_ERR(fsl_chan->clk); -+ -+ fsl_chan->vchan.desc_free = fsl_edma3_free_desc; -+ vchan_init(&fsl_chan->vchan, &fsl_edma3->dma_dev); -+ -+ INIT_WORK(&fsl_chan->issue_worker, -+ fsl_edma3_issue_work); -+ } -+ -+ mutex_init(&fsl_edma3->fsl_edma3_mutex); -+ -+ dma_cap_set(DMA_PRIVATE, fsl_edma3->dma_dev.cap_mask); -+ dma_cap_set(DMA_SLAVE, fsl_edma3->dma_dev.cap_mask); -+ dma_cap_set(DMA_CYCLIC, fsl_edma3->dma_dev.cap_mask); -+ -+ fsl_edma3->dma_dev.dev = &pdev->dev; -+ fsl_edma3->dma_dev.device_alloc_chan_resources -+ = fsl_edma3_alloc_chan_resources; -+ fsl_edma3->dma_dev.device_free_chan_resources -+ = fsl_edma3_free_chan_resources; -+ fsl_edma3->dma_dev.device_tx_status = fsl_edma3_tx_status; -+ fsl_edma3->dma_dev.device_prep_slave_sg = fsl_edma3_prep_slave_sg; -+ fsl_edma3->dma_dev.device_prep_dma_cyclic = fsl_edma3_prep_dma_cyclic; -+ fsl_edma3->dma_dev.device_config = fsl_edma3_slave_config; -+ fsl_edma3->dma_dev.device_pause = fsl_edma3_pause; -+ fsl_edma3->dma_dev.device_resume = fsl_edma3_resume; -+ fsl_edma3->dma_dev.device_terminate_all = fsl_edma3_terminate_all; -+ fsl_edma3->dma_dev.device_issue_pending = fsl_edma3_issue_pending; -+ fsl_edma3->dma_dev.device_synchronize = fsl_edma3_synchronize; -+ -+ fsl_edma3->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; -+ fsl_edma3->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; -+ fsl_edma3->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | -+ BIT(DMA_MEM_TO_DEV) | -+ BIT(DMA_DEV_TO_DEV); -+ -+ platform_set_drvdata(pdev, fsl_edma3); -+ -+ ret = dma_async_device_register(&fsl_edma3->dma_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n"); -+ return ret; -+ } -+ /* Attach power domains from dts for each dma chanel device */ -+ if (fsl_edma3->drvdata->has_pd) { -+ for (i = 0; i < fsl_edma3->n_chans; i++) { -+ struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; -+ struct device *dev; -+ -+ dev = fsl_edma3_attach_pd(&pdev->dev, np, i); -+ if (!dev) { -+ dev_err(dev, "edma channel attach failed.\n"); -+ return -EINVAL; -+ } -+ -+ fsl_chan->dev = dev; -+ /* clear meaningless pending irq anyway */ -+ writel(1, fsl_chan->membase + EDMA_CH_INT); -+ -+ pm_runtime_use_autosuspend(fsl_chan->dev); -+ pm_runtime_set_autosuspend_delay(fsl_chan->dev, 200); -+ pm_runtime_set_active(fsl_chan->dev); -+ pm_runtime_put_sync_suspend(fsl_chan->dev); -+ } -+ } -+ -+ ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3); -+ if (ret) { -+ dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n"); -+ dma_async_device_unregister(&fsl_edma3->dma_dev); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int fsl_edma3_remove(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct fsl_edma3_engine *fsl_edma3 = platform_get_drvdata(pdev); -+ -+ of_dma_controller_free(np); -+ dma_async_device_unregister(&fsl_edma3->dma_dev); -+ -+ clk_disable_unprepare(fsl_edma3->clk_mp); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+static int fsl_edma3_suspend_late(struct device *dev) -+{ -+ struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); -+ struct fsl_edma3_chan *fsl_chan; -+ unsigned long flags; -+ void __iomem *addr; -+ int i; -+ -+ for (i = 0; i < fsl_edma->n_chans; i++) { -+ fsl_chan = &fsl_edma->chans[i]; -+ addr = fsl_chan->membase; -+ -+ if ((fsl_chan->edma3->drvdata->has_pd && -+ pm_runtime_status_suspended(fsl_chan->dev)) || -+ (!fsl_chan->edma3->drvdata->has_pd && !fsl_chan->srcid)) -+ continue; -+ -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_get_sync(fsl_chan->dev); -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ fsl_edma->edma_regs[i].csr = readl(addr + EDMA_CH_CSR); -+ fsl_edma->edma_regs[i].sbr = readl(addr + EDMA_CH_SBR); -+ /* Make sure chan is idle or will force disable. */ -+ if (unlikely(!fsl_chan->idle)) { -+ dev_warn(dev, "WARN: There is non-idle channel."); -+ fsl_edma3_disable_request(fsl_chan); -+ } -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ -+ if (fsl_chan->edma3->drvdata->has_pd) -+ pm_runtime_put_sync_suspend(fsl_chan->dev); -+ } -+ -+ return 0; -+} -+ -+static int fsl_edma3_resume_early(struct device *dev) -+{ -+ struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); -+ struct fsl_edma3_chan *fsl_chan; -+ void __iomem *addr; -+ unsigned long flags; -+ int i; -+ -+ for (i = 0; i < fsl_edma->n_chans; i++) { -+ fsl_chan = &fsl_edma->chans[i]; -+ addr = fsl_chan->membase; -+ -+ if ((fsl_chan->edma3->drvdata->has_pd && -+ pm_runtime_status_suspended(fsl_chan->dev)) || -+ (!fsl_chan->edma3->drvdata->has_pd && !fsl_chan->srcid)) -+ continue; -+ -+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags); -+ writel(fsl_edma->edma_regs[i].csr, addr + EDMA_CH_CSR); -+ writel(fsl_edma->edma_regs[i].sbr, addr + EDMA_CH_SBR); -+ /* restore tcd if this channel not terminated before suspend */ -+ if (fsl_chan->edesc) -+ fsl_edma3_set_tcd_regs(fsl_chan, -+ fsl_chan->edesc->tcd[0].vtcd); -+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); -+ } -+ -+ return 0; -+} -+#endif -+ -+static const struct dev_pm_ops fsl_edma3_pm_ops = { -+ SET_LATE_SYSTEM_SLEEP_PM_OPS(fsl_edma3_suspend_late, -+ fsl_edma3_resume_early) -+}; -+ -+static struct platform_driver fsl_edma3_driver = { -+ .driver = { -+ .name = "fsl-edma-v3", -+ .of_match_table = fsl_edma3_dt_ids, -+ .pm = &fsl_edma3_pm_ops, -+ }, -+ .probe = fsl_edma3_probe, -+ .remove = fsl_edma3_remove, -+}; -+ -+static int __init fsl_edma3_init(void) -+{ -+ return platform_driver_register(&fsl_edma3_driver); -+} -+fs_initcall(fsl_edma3_init); -+ -+static void __exit fsl_edma3_exit(void) -+{ -+ platform_driver_unregister(&fsl_edma3_driver); -+} -+module_exit(fsl_edma3_exit); -+ -+MODULE_ALIAS("platform:fsl-edma3"); -+MODULE_DESCRIPTION("Freescale eDMA-V3 engine driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c -index 90bb72af3..7ef48624f 100644 ---- a/drivers/dma/fsl-edma.c -+++ b/drivers/dma/fsl-edma.c -@@ -53,6 +53,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) - } - - if (!fsl_chan->edesc->iscyclic) { -+ fsl_edma_get_realcnt(fsl_chan); - list_del(&fsl_chan->edesc->vdesc.node); - vchan_cookie_complete(&fsl_chan->edesc->vdesc); - fsl_chan->edesc = NULL; -@@ -138,23 +139,23 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma - { - int ret; - -- fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); -- if (fsl_edma->txirq < 0) -- return fsl_edma->txirq; -+ *fsl_edma->txirqs = platform_get_irq_byname(pdev, "edma-tx"); -+ if (*fsl_edma->txirqs < 0) -+ return *fsl_edma->txirqs; - - fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); - if (fsl_edma->errirq < 0) - return fsl_edma->errirq; - -- if (fsl_edma->txirq == fsl_edma->errirq) { -- ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, -+ if (*fsl_edma->txirqs == fsl_edma->errirq) { -+ ret = devm_request_irq(&pdev->dev, *fsl_edma->txirqs, - fsl_edma_irq_handler, 0, "eDMA", fsl_edma); - if (ret) { - dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); - return ret; - } - } else { -- ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, -+ ret = devm_request_irq(&pdev->dev, *fsl_edma->txirqs, - fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); - if (ret) { - dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); -@@ -177,14 +178,7 @@ fsl_edma2_irq_init(struct platform_device *pdev, - struct fsl_edma_engine *fsl_edma) - { - int i, ret, irq; -- int count; -- -- count = platform_irq_count(pdev); -- dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); -- if (count <= 2) { -- dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); -- return -EINVAL; -- } -+ int count = fsl_edma->drvdata->txirq_count + 1; - /* - * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. - * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... -@@ -199,15 +193,18 @@ fsl_edma2_irq_init(struct platform_device *pdev, - sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); - - /* The last IRQ is for eDMA err */ -- if (i == count - 1) -+ if (i == count - 1) { -+ fsl_edma->errirq = irq; - ret = devm_request_irq(&pdev->dev, irq, - fsl_edma_err_handler, - 0, "eDMA2-ERR", fsl_edma); -- else -+ } else { -+ fsl_edma->txirqs[i] = irq; - ret = devm_request_irq(&pdev->dev, irq, - fsl_edma_tx_handler, 0, - fsl_edma->chans[i].chan_name, - fsl_edma); -+ } - if (ret) - return ret; - } -@@ -215,15 +212,59 @@ fsl_edma2_irq_init(struct platform_device *pdev, - return 0; - } - -+static int fsl_edma_irq_init_s32(struct platform_device *pdev, -+ struct fsl_edma_engine *fsl_edma) -+{ -+ int i, ret, irq, txirq_count = fsl_edma->drvdata->txirq_count; -+ static const char * const names[] = {"edma-tx_0-15", "edma-tx_16-31", -+ "edma-err"}; -+ -+ for (i = 0; i <= txirq_count; i++) { -+ irq = platform_get_irq_byname(pdev, names[i]); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "Can't get %s IRQ.\n", -+ names[i]); -+ return irq; -+ } -+ -+ if (i == txirq_count) { -+ fsl_edma->errirq = irq; -+ ret = devm_request_irq(&pdev->dev, irq, -+ fsl_edma_err_handler, 0, -+ names[i], fsl_edma); -+ } else { -+ fsl_edma->txirqs[i] = irq; -+ ret = devm_request_irq(&pdev->dev, irq, -+ fsl_edma_tx_handler, 0, -+ names[i], fsl_edma); -+ } -+ -+ if (ret) { -+ dev_err(&pdev->dev, -+ "Can't register %s IRQ.\n", -+ names[i]); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ - static void fsl_edma_irq_exit( - struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) - { -- if (fsl_edma->txirq == fsl_edma->errirq) { -- devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); -- } else { -- devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); -- devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); -+ int i; -+ bool free_errirq = true; -+ u8 count = fsl_edma->drvdata->txirq_count; -+ -+ for (i = 0; i < count; i++) { -+ devm_free_irq(&pdev->dev, fsl_edma->txirqs[i], fsl_edma); -+ if (fsl_edma->txirqs[i] == fsl_edma->errirq) -+ free_errirq = false; - } -+ -+ if (free_errirq) -+ devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); - } - - static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) -@@ -238,6 +279,7 @@ static struct fsl_edma_drvdata vf610_data = { - .version = v1, - .dmamuxs = DMAMUX_NR, - .setup_irq = fsl_edma_irq_init, -+ .txirq_count = 1, - }; - - static struct fsl_edma_drvdata ls1028a_data = { -@@ -245,6 +287,7 @@ static struct fsl_edma_drvdata ls1028a_data = { - .dmamuxs = DMAMUX_NR, - .mux_swap = true, - .setup_irq = fsl_edma_irq_init, -+ .txirq_count = 1, - }; - - static struct fsl_edma_drvdata imx7ulp_data = { -@@ -252,12 +295,22 @@ static struct fsl_edma_drvdata imx7ulp_data = { - .dmamuxs = 1, - .has_dmaclk = true, - .setup_irq = fsl_edma2_irq_init, -+ .txirq_count = 16, -+}; -+ -+static struct fsl_edma_drvdata s32v234_data = { -+ .version = v1, -+ .dmamuxs = DMAMUX_NR, -+ .mux_swap = true, -+ .setup_irq = fsl_edma_irq_init_s32, -+ .txirq_count = 2, - }; - - static const struct of_device_id fsl_edma_dt_ids[] = { - { .compatible = "fsl,vf610-edma", .data = &vf610_data}, - { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, - { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, -+ { .compatible = "fsl,s32v234-edma", .data = &s32v234_data}, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); -@@ -365,6 +418,12 @@ static int fsl_edma_probe(struct platform_device *pdev) - } - - edma_writel(fsl_edma, ~0, regs->intl); -+ -+ fsl_edma->txirqs = devm_kzalloc(&pdev->dev, -+ drvdata->txirq_count * sizeof(*fsl_edma->txirqs), GFP_KERNEL); -+ if (!fsl_edma->txirqs) -+ return -ENOMEM; -+ - ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); - if (ret) - return ret; -diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c -index 306f93e4b..3df4e89fd 100644 ---- a/drivers/dma/imx-sdma.c -+++ b/drivers/dma/imx-sdma.c -@@ -23,10 +23,12 @@ - #include - #include - #include -+#include - #include - #include - #include - #include -+#include - #include - #include - #include -@@ -74,6 +76,9 @@ - #define SDMA_CHNENBL0_IMX35 0x200 - #define SDMA_CHNENBL0_IMX31 0x080 - #define SDMA_CHNPRI_0 0x100 -+#define SDMA_DONE0_CONFIG 0x1000 -+#define SDMA_DONE0_CONFIG_DONE_SEL 0x7 -+#define SDMA_DONE0_CONFIG_DONE_DIS 0x6 - - /* - * Buffer descriptor status values. -@@ -168,6 +173,8 @@ - #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) - #define SDMA_WATERMARK_LEVEL_SP BIT(11) - #define SDMA_WATERMARK_LEVEL_DP BIT(12) -+#define SDMA_WATERMARK_LEVEL_SD BIT(13) -+#define SDMA_WATERMARK_LEVEL_DD BIT(14) - #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) - #define SDMA_WATERMARK_LEVEL_LWE BIT(28) - #define SDMA_WATERMARK_LEVEL_HWE BIT(29) -@@ -175,12 +182,19 @@ - - #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ -+ BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) - - #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ - BIT(DMA_MEM_TO_DEV) | \ - BIT(DMA_DEV_TO_DEV)) - -+#define SDMA_WATERMARK_LEVEL_FIFOS_OFF 12 -+#define SDMA_WATERMARK_LEVEL_FIFO_OFF_OFF 16 -+#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23) -+#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF 24 -+#define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO_OFF 28 -+ - /* - * Mode/Count of data node descriptors - IPCv2 - */ -@@ -364,8 +378,9 @@ struct sdma_channel { - struct sdma_desc *desc; - struct sdma_engine *sdma; - unsigned int channel; -- enum dma_transfer_direction direction; -+ enum dma_transfer_direction direction; - struct dma_slave_config slave_config; -+ struct sdma_audio_config *audio_config; - enum sdma_peripheral_type peripheral_type; - unsigned int event_id0; - unsigned int event_id1; -@@ -381,6 +396,9 @@ struct sdma_channel { - enum dma_status status; - struct imx_dma_data data; - struct work_struct terminate_worker; -+ struct list_head terminated; -+ bool is_ram_script; -+ int prio; - }; - - #define IMX_DMA_SG_LOOP BIT(0) -@@ -390,6 +408,15 @@ struct sdma_channel { - #define MXC_SDMA_MIN_PRIORITY 1 - #define MXC_SDMA_MAX_PRIORITY 7 - -+/* -+ * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are reserved and -+ * can't be accessed. Skip these register touch in suspend/resume. Also below -+ * two macros are only used on i.mx6sx. -+ */ -+#define MXC_SDMA_RESERVED_REG (SDMA_CHNPRI_0 - SDMA_XTRIG_CONF2 - 4) -+#define MXC_SDMA_SAVED_REG_NUM (((SDMA_CHNENBL0_IMX35 + 4 * 48) - \ -+ MXC_SDMA_RESERVED_REG) / 4) -+ - #define SDMA_FIRMWARE_MAGIC 0x414d4453 - - /** -@@ -421,15 +448,29 @@ struct sdma_driver_data { - int num_events; - struct sdma_script_start_addrs *script_addrs; - bool check_ratio; -+ /* -+ * ecspi ERR009165 fixed should be done in sdma script -+ * and it be fixed in soc from i.mx6ul. -+ * please get more information from below link: -+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf -+ */ -+ bool ecspi_fixed; -+ bool has_done0; -+ bool pm_runtime; - }; - - struct sdma_engine { - struct device *dev; - struct sdma_channel channel[MAX_DMA_CHANNELS]; - struct sdma_channel_control *channel_control; -+ u32 save_regs[MXC_SDMA_SAVED_REG_NUM]; -+ u32 save_done0_regs[2]; -+ const char *fw_name; - void __iomem *regs; - struct sdma_context_data *context; - dma_addr_t context_phys; -+ dma_addr_t ccb_phys; -+ bool is_on; - struct dma_device dma_device; - struct clk *clk_ipg; - struct clk *clk_ahb; -@@ -444,6 +485,11 @@ struct sdma_engine { - struct sdma_buffer_descriptor *bd0; - /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ - bool clk_ratio; -+ struct gen_pool *iram_pool; -+ bool fw_loaded; -+ u32 fw_fail; -+ u8 *fw_data; -+ unsigned short ram_code_start; - }; - - static int sdma_config_write(struct dma_chan *chan, -@@ -540,6 +586,31 @@ static struct sdma_driver_data sdma_imx6q = { - .script_addrs = &sdma_script_imx6q, - }; - -+static struct sdma_script_start_addrs sdma_script_imx6sx = { -+ .ap_2_ap_addr = 642, -+ .uart_2_mcu_addr = 817, -+ .mcu_2_app_addr = 747, -+ .uartsh_2_mcu_addr = 1032, -+ .mcu_2_shp_addr = 960, -+ .app_2_mcu_addr = 683, -+ .shp_2_mcu_addr = 891, -+ .spdif_2_mcu_addr = 1100, -+ .mcu_2_spdif_addr = 1134, -+}; -+ -+static struct sdma_driver_data sdma_imx6sx = { -+ .chnenbl0 = SDMA_CHNENBL0_IMX35, -+ .num_events = 48, -+ .script_addrs = &sdma_script_imx6sx, -+}; -+ -+static struct sdma_driver_data sdma_imx6ul = { -+ .chnenbl0 = SDMA_CHNENBL0_IMX35, -+ .num_events = 48, -+ .script_addrs = &sdma_script_imx6sx, -+ .ecspi_fixed = true, -+}; -+ - static struct sdma_script_start_addrs sdma_script_imx7d = { - .ap_2_ap_addr = 644, - .uart_2_mcu_addr = 819, -@@ -565,6 +636,16 @@ static struct sdma_driver_data sdma_imx8mq = { - .check_ratio = 1, - }; - -+static struct sdma_driver_data sdma_imx8mp = { -+ .chnenbl0 = SDMA_CHNENBL0_IMX35, -+ .num_events = 48, -+ .script_addrs = &sdma_script_imx7d, -+ .check_ratio = 1, -+ .ecspi_fixed = true, -+ .has_done0 = true, -+ .pm_runtime = true, -+}; -+ - static const struct platform_device_id sdma_devtypes[] = { - { - .name = "imx25-sdma", -@@ -584,12 +665,21 @@ static const struct platform_device_id sdma_devtypes[] = { - }, { - .name = "imx6q-sdma", - .driver_data = (unsigned long)&sdma_imx6q, -+ }, { -+ .name = "imx6sx-sdma", -+ .driver_data = (unsigned long)&sdma_imx6sx, - }, { - .name = "imx7d-sdma", - .driver_data = (unsigned long)&sdma_imx7d, -+ }, { -+ .name = "imx6ul-sdma", -+ .driver_data = (unsigned long)&sdma_imx6ul, - }, { - .name = "imx8mq-sdma", - .driver_data = (unsigned long)&sdma_imx8mq, -+ }, { -+ .name = "imx8mp-sdma", -+ .driver_data = (unsigned long)&sdma_imx8mp, - }, { - /* sentinel */ - } -@@ -603,8 +693,11 @@ static const struct of_device_id sdma_dt_ids[] = { - { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, - { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, - { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, -+ { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, }, - { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, -+ { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, }, - { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, -+ { .compatible = "fsl,imx8mp-sdma", .data = &sdma_imx8mp, }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, sdma_dt_ids); -@@ -672,7 +765,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma) - sdma_enable_channel(sdma, 0); - - ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, -- reg, !(reg & 1), 1, 500); -+ reg, !(reg & 1), 1, 5000); - if (ret) - dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); - -@@ -686,36 +779,80 @@ static int sdma_run_channel0(struct sdma_engine *sdma) - return ret; - } - --static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, -- u32 address) -+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 -+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 -+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 47 -+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 48 -+ -+static void sdma_add_scripts(struct sdma_engine *sdma, -+ const struct sdma_script_start_addrs *addr) -+{ -+ s32 *addr_arr = (u32 *)addr; -+ s32 *saddr_arr = (u32 *)sdma->script_addrs; -+ int i; -+ -+ /* use the default firmware in ROM if missing external firmware */ -+ if (!sdma->script_number) -+ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; -+ -+ if (sdma->script_number > sizeof(struct sdma_script_start_addrs) -+ / sizeof(s32)) { -+ dev_err(sdma->dev, -+ "SDMA script number %d not match with firmware.\n", -+ sdma->script_number); -+ return; -+ } -+ -+ for (i = 0; i < sdma->script_number; i++) -+ if (addr_arr[i] > 0) -+ saddr_arr[i] = addr_arr[i]; -+} -+ -+static int sdma_load_script(struct sdma_engine *sdma) - { - struct sdma_buffer_descriptor *bd0 = sdma->bd0; -+ const struct sdma_script_start_addrs *addr; -+ struct sdma_firmware_header *header; -+ unsigned short *ram_code; - void *buf_virt; - dma_addr_t buf_phys; - int ret; - unsigned long flags; - -- buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); -- if (!buf_virt) { -+ header = (struct sdma_firmware_header *)sdma->fw_data; -+ -+ addr = (void *)header + header->script_addrs_start; -+ ram_code = (void *)header + header->ram_code_start; -+ sdma->ram_code_start = header->ram_code_start; -+ -+ buf_virt = dma_alloc_coherent(sdma->dev, header->ram_code_size, -+ &buf_phys, GFP_KERNEL); -+ if (!buf_virt) - return -ENOMEM; -- } - - spin_lock_irqsave(&sdma->channel_0_lock, flags); - - bd0->mode.command = C0_SETPM; - bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; -- bd0->mode.count = size / 2; -+ bd0->mode.count = header->ram_code_size / 2; - bd0->buffer_addr = buf_phys; -- bd0->ext_buffer_addr = address; -+ bd0->ext_buffer_addr = addr->ram_code_start_addr; - -- memcpy(buf_virt, buf, size); -+ memcpy(buf_virt, ram_code, header->ram_code_size); - - ret = sdma_run_channel0(sdma); - - spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - -- dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); -+ dma_free_coherent(sdma->dev, header->ram_code_size, buf_virt, buf_phys); -+ -+ sdma_add_scripts(sdma, addr); -+ -+ sdma->fw_loaded = true; - -+ dev_info_once(sdma->dev, "loaded firmware %d.%d\n", -+ header->version_major, -+ header->version_minor); - return ret; - } - -@@ -729,6 +866,38 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) - val = readl_relaxed(sdma->regs + chnenbl); - __set_bit(channel, &val); - writel_relaxed(val, sdma->regs + chnenbl); -+ -+ /* Set SDMA_DONEx_CONFIG is sw_done enabled */ -+ if (sdmac->audio_config && sdmac->audio_config->sw_done_sel & BIT(31)) { -+ u32 sw_done_sel = sdmac->audio_config->sw_done_sel & 0xff; -+ u32 offset = SDMA_DONE0_CONFIG + sw_done_sel / 4; -+ u32 done_sel = SDMA_DONE0_CONFIG_DONE_SEL + -+ ((sw_done_sel % 4) << 3); -+ u32 sw_done_dis = SDMA_DONE0_CONFIG_DONE_DIS + -+ ((sw_done_sel % 4) << 3); -+ -+ val = readl_relaxed(sdma->regs + offset); -+ __set_bit(done_sel, &val); -+ __clear_bit(sw_done_dis, &val); -+ writel_relaxed(val, sdma->regs + offset); -+ } -+ -+} -+ -+static int sdma_set_channel_priority(struct sdma_channel *sdmac, -+ unsigned int priority) -+{ -+ struct sdma_engine *sdma = sdmac->sdma; -+ int channel = sdmac->channel; -+ -+ if (priority < MXC_SDMA_MIN_PRIORITY -+ || priority > MXC_SDMA_MAX_PRIORITY) { -+ return -EINVAL; -+ } -+ -+ writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); -+ -+ return 0; - } - - static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) -@@ -773,6 +942,7 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac) - struct sdma_buffer_descriptor *bd; - int error = 0; - enum dma_status old_status = sdmac->status; -+ int count = 0; - - /* - * loop mode. Iterate over descriptors, re-setup them and -@@ -783,6 +953,17 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac) - - bd = &desc->bd[desc->buf_tail]; - -+ /* -+ * re-enable HSTART_HE if all bds consumed at the last time, -+ * that happens in high loading case which sdma_handle_channel_ -+ * loop can't be handled in time while all bds run out in sdma -+ * side, then sdma script clear HE and cause channel stop. -+ */ -+ if (count == desc->num_bd) { -+ dev_warn(sdmac->sdma->dev, "All bds consumed,restart now.\n"); -+ sdma_enable_channel(sdmac->sdma, sdmac->channel); -+ } -+ - if (bd->mode.status & BD_DONE) - break; - -@@ -795,13 +976,20 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac) - /* - * We use bd->mode.count to calculate the residue, since contains - * the number of bytes present in the current buffer descriptor. -+ * Note: in IMX_DMATYPE_MULTI_SAI case, bd->mode.count used as -+ * remaining bytes instead so that one register could be saved. -+ * so chn_real_count = desc->period_len - bd->mode.count. - */ -+ if (sdmac->peripheral_type == IMX_DMATYPE_MULTI_SAI) -+ desc->chn_real_count = desc->period_len - bd->mode.count; -+ else -+ desc->chn_real_count = bd->mode.count; - -- desc->chn_real_count = bd->mode.count; - bd->mode.status |= BD_DONE; - bd->mode.count = desc->period_len; - desc->buf_ptail = desc->buf_tail; - desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; -+ count++; - - /* - * The callback is called from the interrupt context in order -@@ -848,6 +1036,13 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) - struct sdma_engine *sdma = dev_id; - unsigned long stat; - -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdma->dev); -+ else { -+ clk_enable(sdma->clk_ipg); -+ clk_enable(sdma->clk_ahb); -+ } -+ - stat = readl_relaxed(sdma->regs + SDMA_H_INTR); - writel_relaxed(stat, sdma->regs + SDMA_H_INTR); - /* channel 0 is special and not handled here, see run_channel0() */ -@@ -862,7 +1057,10 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) - desc = sdmac->desc; - if (desc) { - if (sdmac->flags & IMX_DMA_SG_LOOP) { -- sdma_update_channel_loop(sdmac); -+ if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) -+ sdma_update_channel_loop(sdmac); -+ else -+ vchan_cyclic_callback(&desc->vd); - } else { - mxc_sdma_handle_channel_normal(sdmac); - vchan_cookie_complete(&desc->vd); -@@ -874,6 +1072,14 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) - __clear_bit(channel, &stat); - } - -+ if (sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdma->dev); -+ pm_runtime_put_autosuspend(sdma->dev); -+ } else { -+ clk_disable(sdma->clk_ipg); -+ clk_disable(sdma->clk_ahb); -+ } -+ - return IRQ_HANDLED; - } - -@@ -921,6 +1127,10 @@ static void sdma_get_pc(struct sdma_channel *sdmac, - emi_2_per = sdma->script_addrs->mcu_2_ata_addr; - break; - case IMX_DMATYPE_CSPI: -+ per_2_emi = sdma->script_addrs->app_2_mcu_addr; -+ emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; -+ sdmac->is_ram_script = true; -+ break; - case IMX_DMATYPE_EXT: - case IMX_DMATYPE_SSI: - case IMX_DMATYPE_SAI: -@@ -930,6 +1140,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac, - case IMX_DMATYPE_SSI_DUAL: - per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; - emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; -+ sdmac->is_ram_script = true; - break; - case IMX_DMATYPE_SSI_SP: - case IMX_DMATYPE_MMC: -@@ -944,11 +1155,13 @@ static void sdma_get_pc(struct sdma_channel *sdmac, - per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; - emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; - per_2_per = sdma->script_addrs->per_2_per_addr; -+ sdmac->is_ram_script = true; - break; - case IMX_DMATYPE_ASRC_SP: - per_2_emi = sdma->script_addrs->shp_2_mcu_addr; - emi_2_per = sdma->script_addrs->mcu_2_shp_addr; - per_2_per = sdma->script_addrs->per_2_per_addr; -+ sdmac->is_ram_script = true; - break; - case IMX_DMATYPE_MSHC: - per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; -@@ -964,6 +1177,19 @@ static void sdma_get_pc(struct sdma_channel *sdmac, - case IMX_DMATYPE_IPU_MEMORY: - emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; - break; -+ case IMX_DMATYPE_HDMI: -+ emi_2_per = sdma->script_addrs->hdmi_dma_addr; -+ sdmac->is_ram_script = true; -+ break; -+ case IMX_DMATYPE_MULTI_SAI: -+ per_2_emi = sdma->script_addrs->sai_2_mcu_addr; -+ emi_2_per = sdma->script_addrs->mcu_2_sai_addr; -+ sdmac->is_ram_script = true; -+ break; -+ case IMX_DMATYPE_I2C: -+ per_2_emi = sdma->script_addrs->i2c_2_mcu_addr; -+ emi_2_per = sdma->script_addrs->mcu_2_i2c_addr; -+ sdmac->is_ram_script = true; - default: - break; - } -@@ -1011,11 +1237,16 @@ static int sdma_load_context(struct sdma_channel *sdmac) - /* Send by context the event mask,base address for peripheral - * and watermark level - */ -- context->gReg[0] = sdmac->event_mask[1]; -- context->gReg[1] = sdmac->event_mask[0]; -- context->gReg[2] = sdmac->per_addr; -- context->gReg[6] = sdmac->shp_addr; -- context->gReg[7] = sdmac->watermark_level; -+ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { -+ context->gReg[4] = sdmac->per_addr; -+ context->gReg[6] = sdmac->shp_addr; -+ } else { -+ context->gReg[0] = sdmac->event_mask[1]; -+ context->gReg[1] = sdmac->event_mask[0]; -+ context->gReg[2] = sdmac->per_addr; -+ context->gReg[6] = sdmac->shp_addr; -+ context->gReg[7] = sdmac->watermark_level; -+ } - - bd0->mode.command = C0_SETDM; - bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; -@@ -1029,6 +1260,31 @@ static int sdma_load_context(struct sdma_channel *sdmac) - return ret; - } - -+static int sdma_save_restore_context(struct sdma_engine *sdma, bool save) -+{ -+ struct sdma_context_data *context = sdma->context; -+ struct sdma_buffer_descriptor *bd0 = sdma->bd0; -+ unsigned long flags; -+ int ret; -+ -+ spin_lock_irqsave(&sdma->channel_0_lock, flags); -+ -+ if (save) -+ bd0->mode.command = C0_GETDM; -+ else -+ bd0->mode.command = C0_SETDM; -+ -+ bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; -+ bd0->mode.count = MAX_DMA_CHANNELS * sizeof(*context) / 4; -+ bd0->buffer_addr = sdma->context_phys; -+ bd0->ext_buffer_addr = 2048; -+ ret = sdma_run_channel0(sdma); -+ -+ spin_unlock_irqrestore(&sdma->channel_0_lock, flags); -+ -+ return ret; -+} -+ - static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) - { - return container_of(chan, struct sdma_channel, vc.chan); -@@ -1049,9 +1305,6 @@ static void sdma_channel_terminate_work(struct work_struct *work) - { - struct sdma_channel *sdmac = container_of(work, struct sdma_channel, - terminate_worker); -- unsigned long flags; -- LIST_HEAD(head); -- - /* - * According to NXP R&D team a delay of one BD SDMA cost time - * (maximum is 1ms) should be added after disable of the channel -@@ -1060,10 +1313,7 @@ static void sdma_channel_terminate_work(struct work_struct *work) - */ - usleep_range(1000, 2000); - -- spin_lock_irqsave(&sdmac->vc.lock, flags); -- vchan_get_all_descriptors(&sdmac->vc, &head); -- spin_unlock_irqrestore(&sdmac->vc.lock, flags); -- vchan_dma_desc_free_list(&sdmac->vc, &head); -+ vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated); - } - - static int sdma_terminate_all(struct dma_chan *chan) -@@ -1071,18 +1321,33 @@ static int sdma_terminate_all(struct dma_chan *chan) - struct sdma_channel *sdmac = to_sdma_chan(chan); - unsigned long flags; - -+ if (sdmac->sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdmac->sdma->dev); -+ - spin_lock_irqsave(&sdmac->vc.lock, flags); - - sdma_disable_channel(chan); - - if (sdmac->desc) { - vchan_terminate_vdesc(&sdmac->desc->vd); -+ /* -+ * move out current descriptor into terminated list so that -+ * it could be free in sdma_channel_terminate_work alone -+ * later without potential involving next descriptor raised -+ * up before the last descriptor terminated. -+ */ -+ vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated); - sdmac->desc = NULL; - schedule_work(&sdmac->terminate_worker); - } - - spin_unlock_irqrestore(&sdmac->vc.lock, flags); - -+ if (sdmac->sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdmac->sdma->dev); -+ pm_runtime_put_autosuspend(sdmac->sdma->dev); -+ } -+ - return 0; - } - -@@ -1133,6 +1398,49 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) - sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; - - sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; -+ -+ if (sdmac->audio_config->src_fifo_num > 1) -+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD; -+ if (sdmac->audio_config->dst_fifo_num > 1) -+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD; -+} -+ -+static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac) -+{ -+ u8 fifo_num = sdmac->audio_config->src_fifo_num | -+ sdmac->audio_config->dst_fifo_num; -+ u8 fifo_offset = sdmac->audio_config->src_fifo_off | -+ sdmac->audio_config->dst_fifo_off; -+ u8 words_per_fifo = sdmac->audio_config->words_per_fifo; -+ -+ sdmac->watermark_level &= ~(0xFF << SDMA_WATERMARK_LEVEL_FIFOS_OFF | -+ SDMA_WATERMARK_LEVEL_SW_DONE | -+ 0xf << SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF | -+ 0xf << SDMA_WATERMARK_LEVEL_FIFO_OFF_OFF | -+ 0xf << SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO_OFF); -+ -+ if (sdmac->audio_config->sw_done_sel & BIT(31)) -+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE | -+ (sdmac->audio_config->sw_done_sel & 0xff) << -+ SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF; -+ -+ /* For fifo_num -+ * bit 12-15 is the fifo number; -+ * bit 16-19 is the fifo offset, -+ * bit 28-31 is the channels per fifo. -+ * so here only need to shift left fifo_num 12 bit for watermake_level -+ */ -+ if (fifo_num) -+ sdmac->watermark_level |= fifo_num << -+ SDMA_WATERMARK_LEVEL_FIFOS_OFF; -+ -+ if (fifo_offset) -+ sdmac->watermark_level |= fifo_offset << -+ SDMA_WATERMARK_LEVEL_FIFO_OFF_OFF; -+ -+ if (words_per_fifo) -+ sdmac->watermark_level |= (words_per_fifo - 1) << -+ SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO_OFF; - } - - static int sdma_config_channel(struct dma_chan *chan) -@@ -1158,6 +1466,12 @@ static int sdma_config_channel(struct dma_chan *chan) - break; - } - -+ sdma_set_channel_priority(sdmac, sdmac->prio); -+ -+ sdma_event_enable(sdmac, sdmac->event_id0); -+ if (sdmac->event_id1) -+ sdma_event_enable(sdmac, sdmac->event_id1); -+ - sdma_get_pc(sdmac, sdmac->peripheral_type); - - if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && -@@ -1167,8 +1481,21 @@ static int sdma_config_channel(struct dma_chan *chan) - if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || - sdmac->peripheral_type == IMX_DMATYPE_ASRC) - sdma_set_watermarklevel_for_p2p(sdmac); -- } else -+ } else { -+ /* -+ * ERR009165 fixed from i.mx6ul, no errata need, -+ * set bit31 to let sdma script skip the errata. -+ */ -+ if (sdmac->peripheral_type == IMX_DMATYPE_CSPI && -+ sdmac->direction == DMA_MEM_TO_DEV && -+ sdmac->sdma->drvdata->ecspi_fixed) -+ __set_bit(31, &sdmac->watermark_level); -+ else if (sdmac->peripheral_type == -+ IMX_DMATYPE_MULTI_SAI) -+ sdma_set_watermarklevel_for_sais(sdmac); -+ - __set_bit(sdmac->event_id0, sdmac->event_mask); -+ } - - /* Address */ - sdmac->shp_addr = sdmac->per_address; -@@ -1180,28 +1507,18 @@ static int sdma_config_channel(struct dma_chan *chan) - return 0; - } - --static int sdma_set_channel_priority(struct sdma_channel *sdmac, -- unsigned int priority) --{ -- struct sdma_engine *sdma = sdmac->sdma; -- int channel = sdmac->channel; -- -- if (priority < MXC_SDMA_MIN_PRIORITY -- || priority > MXC_SDMA_MAX_PRIORITY) { -- return -EINVAL; -- } -- -- writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); -- -- return 0; --} -- - static int sdma_request_channel0(struct sdma_engine *sdma) - { - int ret = -EBUSY; - -- sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, -- GFP_NOWAIT); -+ if (sdma->iram_pool) -+ sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, -+ sizeof(struct sdma_buffer_descriptor), -+ &sdma->bd0_phys); -+ else -+ sdma->bd0 = dma_alloc_coherent(sdma->dev, -+ sizeof(struct sdma_buffer_descriptor), -+ &sdma->bd0_phys, GFP_NOWAIT); - if (!sdma->bd0) { - ret = -ENOMEM; - goto out; -@@ -1221,10 +1538,15 @@ static int sdma_request_channel0(struct sdma_engine *sdma) - static int sdma_alloc_bd(struct sdma_desc *desc) - { - u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); -+ struct sdma_engine *sdma = desc->sdmac->sdma; - int ret = 0; - -- desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, -- &desc->bd_phys, GFP_NOWAIT); -+ if (sdma->iram_pool) -+ desc->bd = gen_pool_dma_alloc(sdma->iram_pool, bd_size, -+ &desc->bd_phys); -+ else -+ desc->bd = dma_alloc_coherent(sdma->dev, bd_size, -+ &desc->bd_phys, GFP_NOWAIT); - if (!desc->bd) { - ret = -ENOMEM; - goto out; -@@ -1236,9 +1558,14 @@ static int sdma_alloc_bd(struct sdma_desc *desc) - static void sdma_free_bd(struct sdma_desc *desc) - { - u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); -+ struct sdma_engine *sdma = desc->sdmac->sdma; - -- dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, -- desc->bd_phys); -+ if (sdma->iram_pool) -+ gen_pool_free(sdma->iram_pool, (unsigned long)desc->bd, -+ bd_size); -+ else -+ dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, -+ desc->bd_phys); - } - - static void sdma_desc_free(struct virt_dma_desc *vd) -@@ -1249,12 +1576,122 @@ static void sdma_desc_free(struct virt_dma_desc *vd) - kfree(desc); - } - -+static int sdma_runtime_suspend(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct sdma_engine *sdma = platform_get_drvdata(pdev); -+ -+ if (!sdma->is_on) -+ return 0; -+ -+ sdma->fw_loaded = false; -+ sdma->is_on = false; -+ -+ clk_disable(sdma->clk_ipg); -+ clk_disable(sdma->clk_ahb); -+ -+ /* free channel0 bd */ -+ if (sdma->iram_pool) -+ gen_pool_free(sdma->iram_pool, (unsigned long)sdma->bd0, -+ sizeof(struct sdma_buffer_descriptor)); -+ else -+ dma_free_coherent(sdma->dev, -+ sizeof(struct sdma_buffer_descriptor), -+ sdma->bd0, sdma->bd0_phys); -+ -+ return 0; -+} -+ -+static int sdma_runtime_resume(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct sdma_engine *sdma = platform_get_drvdata(pdev); -+ int i, ret = 0; -+ -+ ret = clk_enable(sdma->clk_ipg); -+ if (ret) -+ return ret; -+ ret = clk_enable(sdma->clk_ahb); -+ if (ret) -+ goto disable_clk_ipg; -+ -+ /* Do nothing at HW level if audiomix which shared with audio driver -+ * not off indeed. -+ */ -+ if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) { -+ if (sdma->iram_pool) -+ sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, -+ sizeof(struct sdma_buffer_descriptor), -+ &sdma->bd0_phys); -+ else -+ sdma->bd0 = dma_alloc_coherent(sdma->dev, -+ sizeof(struct sdma_buffer_descriptor), -+ &sdma->bd0_phys, GFP_NOWAIT); -+ if (!sdma->bd0) -+ ret = -ENOMEM; -+ -+ sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; -+ sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; -+ -+ sdma->is_on = true; -+ sdma->fw_loaded = true; -+ -+ return ret; -+ } -+ -+ /* Be sure SDMA has not started yet */ -+ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); -+ -+ /* disable all channels */ -+ for (i = 0; i < sdma->drvdata->num_events; i++) -+ writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); -+ -+ /* All channels have priority 0 */ -+ for (i = 0; i < MAX_DMA_CHANNELS; i++) -+ writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); -+ -+ ret = sdma_request_channel0(sdma); -+ if (ret) -+ return ret; -+ -+ sdma_config_ownership(&sdma->channel[0], false, true, false); -+ -+ /* Set Command Channel (Channel Zero) */ -+ writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); -+ -+ /* Set bits of CONFIG register but with static context switching */ -+ if (sdma->clk_ratio) -+ writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); -+ else -+ writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); -+ -+ writel_relaxed(sdma->ccb_phys, sdma->regs + SDMA_H_C0PTR); -+ -+ /* Initializes channel's priorities */ -+ sdma_set_channel_priority(&sdma->channel[0], 7); -+ -+ if (!sdma->fw_data) -+ dev_dbg(sdma->dev, "firmware not ready.\n"); -+ else if (sdma_load_script(sdma)) -+ dev_warn(sdma->dev, "failed to load script.\n"); -+ -+ sdma->is_on = true; -+ -+ return 0; -+ -+disable_clk_ipg: -+ clk_disable(sdma->clk_ipg); -+ dev_err(sdma->dev, "initialisation failed with %d\n", ret); -+ -+ return ret; -+} -+ - static int sdma_alloc_chan_resources(struct dma_chan *chan) - { - struct sdma_channel *sdmac = to_sdma_chan(chan); - struct imx_dma_data *data = chan->private; - struct imx_dma_data mem_data; -- int prio, ret; -+ int prio; - - /* - * MEMCPY may never setup chan->private by filter function such as -@@ -1292,31 +1729,31 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan) - sdmac->peripheral_type = data->peripheral_type; - sdmac->event_id0 = data->dma_request; - sdmac->event_id1 = data->dma_request2; -- -- ret = clk_enable(sdmac->sdma->clk_ipg); -- if (ret) -- return ret; -- ret = clk_enable(sdmac->sdma->clk_ahb); -- if (ret) -- goto disable_clk_ipg; -- -- ret = sdma_set_channel_priority(sdmac, prio); -- if (ret) -- goto disable_clk_ahb; -+ sdmac->prio = prio; - - return 0; -- --disable_clk_ahb: -- clk_disable(sdmac->sdma->clk_ahb); --disable_clk_ipg: -- clk_disable(sdmac->sdma->clk_ipg); -- return ret; - } - - static void sdma_free_chan_resources(struct dma_chan *chan) - { - struct sdma_channel *sdmac = to_sdma_chan(chan); -- struct sdma_engine *sdma = sdmac->sdma; -+ -+ /* -+ * Per fw_data is null which means firmware not loaded and sdma -+ * not initialized, directly return. This happens in below case: -+ * -+ * -- driver request dma chan in probe phase, after that driver -+ * fall into -EPROBE_DEFER and free channel again without -+ * anything else about dma, so just return directly, otherwise -+ * kernel could hang since dma hardware not ready if drvdata-> -+ * pm_runtime is false. -+ * -+ */ -+ if (unlikely(!sdmac->sdma->fw_data)) -+ return; -+ -+ if (sdmac->sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdmac->sdma->dev); - - sdma_terminate_all(chan); - -@@ -1331,8 +1768,13 @@ static void sdma_free_chan_resources(struct dma_chan *chan) - - sdma_set_channel_priority(sdmac, 0); - -- clk_disable(sdma->clk_ipg); -- clk_disable(sdma->clk_ahb); -+ kfree(sdmac->audio_config); -+ sdmac->audio_config = NULL; -+ -+ if (sdmac->sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdmac->sdma->dev); -+ pm_runtime_put_autosuspend(sdmac->sdma->dev); -+ } - } - - static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, -@@ -1340,6 +1782,11 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, - { - struct sdma_desc *desc; - -+ if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { -+ dev_err(sdmac->sdma->dev, "sdma firmware not ready!\n"); -+ goto err_out; -+ } -+ - desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); - if (!desc) - goto err_out; -@@ -1355,7 +1802,7 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, - desc->sdmac = sdmac; - desc->num_bd = bds; - -- if (sdma_alloc_bd(desc)) -+ if (bds && sdma_alloc_bd(desc)) - goto err_desc_out; - - /* No slave_config called in MEMCPY case, so do here */ -@@ -1391,10 +1838,16 @@ static struct dma_async_tx_descriptor *sdma_prep_memcpy( - dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", - &dma_src, &dma_dst, len, channel); - -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdmac->sdma->dev); -+ - desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, - len / SDMA_BD_MAX_CNT + 1); -- if (!desc) -+ if (!desc) { -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_put_sync_suspend(sdmac->sdma->dev); - return NULL; -+ } - - do { - count = min_t(size_t, len, SDMA_BD_MAX_CNT); -@@ -1426,6 +1879,11 @@ static struct dma_async_tx_descriptor *sdma_prep_memcpy( - bd->mode.status = param; - } while (len); - -+ if (sdmac->sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdmac->sdma->dev); -+ pm_runtime_put_autosuspend(sdmac->sdma->dev); -+ } -+ - return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); - } - -@@ -1441,6 +1899,9 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg( - struct scatterlist *sg; - struct sdma_desc *desc; - -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdmac->sdma->dev); -+ - sdma_config_write(chan, &sdmac->slave_config, direction); - - desc = sdma_transfer_init(sdmac, direction, sg_len); -@@ -1476,6 +1937,9 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg( - if (count & 3 || sg->dma_address & 3) - goto err_bd_out; - break; -+ case DMA_SLAVE_BUSWIDTH_3_BYTES: -+ bd->mode.command = 3; -+ break; - case DMA_SLAVE_BUSWIDTH_2_BYTES: - bd->mode.command = 2; - if (count & 1 || sg->dma_address & 1) -@@ -1504,12 +1968,19 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg( - bd->mode.status = param; - } - -+ if (sdmac->sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdmac->sdma->dev); -+ pm_runtime_put_autosuspend(sdmac->sdma->dev); -+ } -+ - return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); - err_bd_out: - sdma_free_bd(desc); - kfree(desc); - err_out: - sdmac->status = DMA_ERROR; -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_put_sync_suspend(sdmac->sdma->dev); - return NULL; - } - -@@ -1520,13 +1991,19 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( - { - struct sdma_channel *sdmac = to_sdma_chan(chan); - struct sdma_engine *sdma = sdmac->sdma; -- int num_periods = buf_len / period_len; -+ int num_periods = 0; - int channel = sdmac->channel; - int i = 0, buf = 0; - struct sdma_desc *desc; - - dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); - -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdmac->sdma->dev); -+ -+ if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) -+ num_periods = buf_len / period_len; -+ - sdma_config_write(chan, &sdmac->slave_config, direction); - - desc = sdma_transfer_init(sdmac, direction, num_periods); -@@ -1543,6 +2020,9 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( - goto err_bd_out; - } - -+ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) -+ return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); -+ - while (buf < buf_len) { - struct sdma_buffer_descriptor *bd = &desc->bd[i]; - int param; -@@ -1575,12 +2055,19 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( - i++; - } - -+ if (sdmac->sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdmac->sdma->dev); -+ pm_runtime_put_autosuspend(sdmac->sdma->dev); -+ } -+ - return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); - err_bd_out: - sdma_free_bd(desc); - kfree(desc); - err_out: - sdmac->status = DMA_ERROR; -+ if (sdma->drvdata->pm_runtime) -+ pm_runtime_put_sync_suspend(sdmac->sdma->dev); - return NULL; - } - -@@ -1590,6 +2077,9 @@ static int sdma_config_write(struct dma_chan *chan, - { - struct sdma_channel *sdmac = to_sdma_chan(chan); - -+ sdmac->watermark_level = 0; -+ sdmac->is_ram_script = false; -+ - if (direction == DMA_DEV_TO_MEM) { - sdmac->per_address = dmaengine_cfg->src_addr; - sdmac->watermark_level = dmaengine_cfg->src_maxburst * -@@ -1603,6 +2093,10 @@ static int sdma_config_write(struct dma_chan *chan, - sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & - SDMA_WATERMARK_LEVEL_HWML; - sdmac->word_size = dmaengine_cfg->dst_addr_width; -+ } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { -+ sdmac->per_address = dmaengine_cfg->dst_addr; -+ sdmac->per_address2 = dmaengine_cfg->src_addr; -+ sdmac->watermark_level = 0; - } else { - sdmac->per_address = dmaengine_cfg->dst_addr; - sdmac->watermark_level = dmaengine_cfg->dst_maxburst * -@@ -1617,19 +2111,31 @@ static int sdma_config(struct dma_chan *chan, - struct dma_slave_config *dmaengine_cfg) - { - struct sdma_channel *sdmac = to_sdma_chan(chan); -+ void *tmp; - - memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); - -+ /* Allocate special sdma_audio_config if it's used */ -+ if (dmaengine_cfg->peripheral_config) { -+ tmp = krealloc(sdmac->audio_config, -+ dmaengine_cfg->peripheral_size, GFP_NOWAIT); -+ if (!tmp) -+ return -ENOMEM; -+ -+ sdmac->audio_config = (struct sdma_audio_config *)tmp; -+ -+ memcpy(tmp, dmaengine_cfg->peripheral_config, -+ dmaengine_cfg->peripheral_size); -+ } -+ - /* Set ENBLn earlier to make sure dma request triggered after that */ - if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) - return -EINVAL; -- sdma_event_enable(sdmac, sdmac->event_id0); - -- if (sdmac->event_id1) { -- if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) -- return -EINVAL; -- sdma_event_enable(sdmac, sdmac->event_id1); -- } -+ -+ if (sdmac->event_id1 && -+ sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) -+ return -EINVAL; - - return 0; - } -@@ -1680,55 +2186,41 @@ static void sdma_issue_pending(struct dma_chan *chan) - struct sdma_channel *sdmac = to_sdma_chan(chan); - unsigned long flags; - -+ if (sdmac->sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdmac->sdma->dev); -+ - spin_lock_irqsave(&sdmac->vc.lock, flags); - if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) - sdma_start_desc(sdmac); - spin_unlock_irqrestore(&sdmac->vc.lock, flags); --} -- --#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 --#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 --#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 --#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 -- --static void sdma_add_scripts(struct sdma_engine *sdma, -- const struct sdma_script_start_addrs *addr) --{ -- s32 *addr_arr = (u32 *)addr; -- s32 *saddr_arr = (u32 *)sdma->script_addrs; -- int i; - -- /* use the default firmware in ROM if missing external firmware */ -- if (!sdma->script_number) -- sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; -- -- if (sdma->script_number > sizeof(struct sdma_script_start_addrs) -- / sizeof(s32)) { -- dev_err(sdma->dev, -- "SDMA script number %d not match with firmware.\n", -- sdma->script_number); -- return; -+ if (sdmac->sdma->drvdata->pm_runtime) { -+ pm_runtime_mark_last_busy(sdmac->sdma->dev); -+ pm_runtime_put_autosuspend(sdmac->sdma->dev); - } -- -- for (i = 0; i < sdma->script_number; i++) -- if (addr_arr[i] > 0) -- saddr_arr[i] = addr_arr[i]; - } - - static void sdma_load_firmware(const struct firmware *fw, void *context) - { - struct sdma_engine *sdma = context; - const struct sdma_firmware_header *header; -- const struct sdma_script_start_addrs *addr; -- unsigned short *ram_code; - - if (!fw) { -- dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); -- /* In this case we just use the ROM firmware. */ -+ /* Load firmware once more time if timeout */ -+ if (sdma->fw_fail) -+ dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); -+ else { -+ request_firmware_nowait(THIS_MODULE, -+ FW_ACTION_HOTPLUG, sdma->fw_name, -+ sdma->dev, GFP_KERNEL, sdma, -+ sdma_load_firmware); -+ sdma->fw_fail++; -+ } -+ - return; - } - -- if (fw->size < sizeof(*header)) -+ if (fw->size < sizeof(*header) || sdma->fw_loaded) - goto err_firmware; - - header = (struct sdma_firmware_header *)fw->data; -@@ -1755,23 +2247,18 @@ static void sdma_load_firmware(const struct firmware *fw, void *context) - goto err_firmware; - } - -- addr = (void *)header + header->script_addrs_start; -- ram_code = (void *)header + header->ram_code_start; -+ dev_info(sdma->dev, "firmware found.\n"); - -- clk_enable(sdma->clk_ipg); -- clk_enable(sdma->clk_ahb); -- /* download the RAM image for SDMA */ -- sdma_load_script(sdma, ram_code, -- header->ram_code_size, -- addr->ram_code_start_addr); -- clk_disable(sdma->clk_ipg); -- clk_disable(sdma->clk_ahb); -+ if (!sdma->fw_data) { -+ sdma->fw_data = kmalloc(fw->size, GFP_KERNEL); -+ if (!sdma->fw_data) -+ goto err_firmware; - -- sdma_add_scripts(sdma, addr); -+ memcpy(sdma->fw_data, fw->data, fw->size); - -- dev_info(sdma->dev, "loaded firmware %d.%d\n", -- header->version_major, -- header->version_minor); -+ if (!sdma->drvdata->pm_runtime) -+ pm_runtime_get_sync(sdma->dev); -+ } - - err_firmware: - release_firmware(fw); -@@ -1855,79 +2342,34 @@ static int sdma_get_firmware(struct sdma_engine *sdma, - return ret; - } - --static int sdma_init(struct sdma_engine *sdma) -+static int sdma_init_sw(struct sdma_engine *sdma) - { -- int i, ret; -- dma_addr_t ccb_phys; -- -- ret = clk_enable(sdma->clk_ipg); -- if (ret) -- return ret; -- ret = clk_enable(sdma->clk_ahb); -- if (ret) -- goto disable_clk_ipg; -+ int ret, ccbsize; - - if (sdma->drvdata->check_ratio && - (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) - sdma->clk_ratio = 1; - -- /* Be sure SDMA has not started yet */ -- writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); -- -- sdma->channel_control = dma_alloc_coherent(sdma->dev, -- MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + -- sizeof(struct sdma_context_data), -- &ccb_phys, GFP_KERNEL); -+ ccbsize = MAX_DMA_CHANNELS * (sizeof(struct sdma_channel_control) -+ + sizeof(struct sdma_context_data)); - -+ if (sdma->iram_pool) -+ sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, -+ ccbsize, &sdma->ccb_phys); -+ else -+ sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, -+ &sdma->ccb_phys, GFP_KERNEL); - if (!sdma->channel_control) { - ret = -ENOMEM; -- goto err_dma_alloc; -+ return ret; - } - - sdma->context = (void *)sdma->channel_control + - MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); -- sdma->context_phys = ccb_phys + -+ sdma->context_phys = sdma->ccb_phys + - MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); - -- /* disable all channels */ -- for (i = 0; i < sdma->drvdata->num_events; i++) -- writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); -- -- /* All channels have priority 0 */ -- for (i = 0; i < MAX_DMA_CHANNELS; i++) -- writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); -- -- ret = sdma_request_channel0(sdma); -- if (ret) -- goto err_dma_alloc; -- -- sdma_config_ownership(&sdma->channel[0], false, true, false); -- -- /* Set Command Channel (Channel Zero) */ -- writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); -- -- /* Set bits of CONFIG register but with static context switching */ -- if (sdma->clk_ratio) -- writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); -- else -- writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); -- -- writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); -- -- /* Initializes channel's priorities */ -- sdma_set_channel_priority(&sdma->channel[0], 7); -- -- clk_disable(sdma->clk_ipg); -- clk_disable(sdma->clk_ahb); -- - return 0; -- --err_dma_alloc: -- clk_disable(sdma->clk_ahb); --disable_clk_ipg: -- clk_disable(sdma->clk_ipg); -- dev_err(sdma->dev, "initialisation failed with %d\n", ret); -- return ret; - } - - static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) -@@ -1954,9 +2396,11 @@ static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, - if (dma_spec->args_count != 3) - return NULL; - -+ memset(&data, 0, sizeof(data)); -+ - data.dma_request = dma_spec->args[0]; - data.peripheral_type = dma_spec->args[1]; -- data.priority = dma_spec->args[2]; -+ data.priority = dma_spec->args[2] & 0xff; - /* - * init dma_request2 to zero, which is not used by the dts. - * For P2P, dma_request2 is init from dma_request_channel(), -@@ -2066,6 +2510,7 @@ static int sdma_probe(struct platform_device *pdev) - - sdmac->channel = i; - sdmac->vc.desc_free = sdma_desc_free; -+ INIT_LIST_HEAD(&sdmac->terminated); - INIT_WORK(&sdmac->terminate_worker, - sdma_channel_terminate_work); - /* -@@ -2077,7 +2522,13 @@ static int sdma_probe(struct platform_device *pdev) - vchan_init(&sdmac->vc, &sdma->dma_device); - } - -- ret = sdma_init(sdma); -+ if (np) { -+ sdma->iram_pool = of_gen_pool_get(np, "iram", 0); -+ if (sdma->iram_pool) -+ dev_info(&pdev->dev, "alloc bd from iram.\n"); -+ } -+ -+ ret = sdma_init_sw(sdma); - if (ret) - goto err_init; - -@@ -2133,16 +2584,8 @@ static int sdma_probe(struct platform_device *pdev) - of_node_put(spba_bus); - } - -- /* -- * Kick off firmware loading as the very last step: -- * attempt to load firmware only if we're not on the error path, because -- * the firmware callback requires a fully functional and allocated sdma -- * instance. -- */ - if (pdata) { -- ret = sdma_get_firmware(sdma, pdata->fw_name); -- if (ret) -- dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); -+ sdma->fw_name = pdata->fw_name; - } else { - /* - * Because that device tree does not encode ROM script address, -@@ -2151,15 +2594,26 @@ static int sdma_probe(struct platform_device *pdev) - */ - ret = of_property_read_string(np, "fsl,sdma-ram-script-name", - &fw_name); -- if (ret) { -+ if (ret) - dev_warn(&pdev->dev, "failed to get firmware name\n"); -- } else { -- ret = sdma_get_firmware(sdma, fw_name); -- if (ret) -- dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); -- } -+ else -+ sdma->fw_name = fw_name; -+ -+ ret = sdma_get_firmware(sdma, sdma->fw_name); -+ if (ret) -+ dev_warn(sdma->dev, "failed to get firmware.\n"); -+ } -+ -+ /* enable autosuspend for pm_runtime */ -+ if (sdma->drvdata->pm_runtime) { -+ pm_runtime_set_autosuspend_delay(&pdev->dev, 8000); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ pm_runtime_mark_last_busy(&pdev->dev); -+ pm_runtime_set_active(&pdev->dev); - } - -+ pm_runtime_enable(&pdev->dev); -+ - return 0; - - err_register: -@@ -2181,6 +2635,7 @@ static int sdma_remove(struct platform_device *pdev) - devm_free_irq(&pdev->dev, sdma->irq, sdma); - dma_async_device_unregister(&sdma->dma_device); - kfree(sdma->script_addrs); -+ kfree(sdma->fw_data); - clk_unprepare(sdma->clk_ahb); - clk_unprepare(sdma->clk_ipg); - /* Kill the tasklet */ -@@ -2191,14 +2646,127 @@ static int sdma_remove(struct platform_device *pdev) - sdma_free_chan_resources(&sdmac->vc.chan); - } - -+ pm_runtime_disable(&pdev->dev); -+ pm_runtime_set_suspended(&pdev->dev); -+ pm_runtime_dont_use_autosuspend(&pdev->dev); -+ - platform_set_drvdata(pdev, NULL); - return 0; - } - -+#ifdef CONFIG_PM_SLEEP -+static int sdma_suspend(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct sdma_engine *sdma = platform_get_drvdata(pdev); -+ int i, ret = 0; -+ -+ /* Do nothing if not i.MX6SX or i.MX7D, i.MX8MP */ -+ if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d -+ && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) -+ return 0; -+ -+ if (!sdma->is_on) -+ return 0; -+ -+ ret = sdma_save_restore_context(sdma, true); -+ if (ret) { -+ dev_err(sdma->dev, "save context error!\n"); -+ return ret; -+ } -+ -+ /* save regs */ -+ for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { -+ /* -+ * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are -+ * reserved and can't be touched. Skip these regs. -+ */ -+ if (i > SDMA_XTRIG_CONF2 / 4) -+ sdma->save_regs[i] = readl_relaxed(sdma->regs + -+ MXC_SDMA_RESERVED_REG -+ + 4 * i); -+ else -+ sdma->save_regs[i] = readl_relaxed(sdma->regs + 4 * i); -+ } -+ -+ if (sdma->drvdata->has_done0) { -+ for (i = 0; i < 2; i++) -+ sdma->save_done0_regs[i] = -+ readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG + 4 * i); -+ } -+ -+ return 0; -+} -+ -+static int sdma_resume(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct sdma_engine *sdma = platform_get_drvdata(pdev); -+ int i, ret; -+ -+ /* Do nothing if not i.MX6SX or i.MX7D, i.MX8MP*/ -+ if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d -+ && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) -+ return 0; -+ -+ if (!sdma->is_on) -+ return 0; -+ -+ /* Do nothing if mega/fast mix not turned off */ -+ if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) -+ return 0; -+ -+ /* Firmware was lost, mark as "not ready" */ -+ sdma->fw_loaded = false; -+ -+ /* restore regs and load firmware */ -+ for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { -+ /* -+ * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are -+ * reserved and can't be touched. Skip these regs. -+ */ -+ if (i > SDMA_XTRIG_CONF2 / 4) -+ writel_relaxed(sdma->save_regs[i], sdma->regs + -+ MXC_SDMA_RESERVED_REG + 4 * i); -+ /* set static context switch mode before channel0 running */ -+ else if (i == SDMA_H_CONFIG / 4) -+ writel_relaxed(sdma->save_regs[i] & ~SDMA_H_CONFIG_CSM, -+ sdma->regs + SDMA_H_CONFIG); -+ else -+ writel_relaxed(sdma->save_regs[i], sdma->regs + 4 * i); -+ } -+ -+ /* restore SDMA_DONEx_CONFIG */ -+ if (sdma->drvdata->has_done0) { -+ for (i = 0; i < 2; i++) -+ writel_relaxed(sdma->save_done0_regs[i], -+ sdma->regs + SDMA_DONE0_CONFIG + 4 * i); -+ } -+ -+ /* prepare priority for channel0 to start */ -+ sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_MAX_PRIORITY); -+ -+ if (sdma_load_script(sdma)) -+ dev_warn(sdma->dev, "failed to load firmware.\n"); -+ -+ ret = sdma_save_restore_context(sdma, false); -+ if (ret) -+ dev_err(sdma->dev, "restore context error!\n"); -+ -+ return ret; -+} -+#endif -+ -+static const struct dev_pm_ops sdma_pm_ops = { -+ SET_LATE_SYSTEM_SLEEP_PM_OPS(sdma_suspend, sdma_resume) -+ SET_RUNTIME_PM_OPS(sdma_runtime_suspend, sdma_runtime_resume, NULL) -+}; -+ - static struct platform_driver sdma_driver = { - .driver = { - .name = "imx-sdma", - .of_match_table = sdma_dt_ids, -+ .pm = &sdma_pm_ops, - }, - .id_table = sdma_devtypes, - .remove = sdma_remove, -diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c -index 65f816b40..9067f543c 100644 ---- a/drivers/dma/mxs-dma.c -+++ b/drivers/dma/mxs-dma.c -@@ -25,6 +25,8 @@ - #include - #include - #include -+#include -+#include - - #include - -@@ -39,6 +41,8 @@ - #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) - #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) - -+#define MXS_DMA_RPM_TIMEOUT 50 /* ms */ -+ - #define HW_APBHX_CTRL0 0x000 - #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) - #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) -@@ -118,6 +122,7 @@ struct mxs_dma_chan { - enum dma_status status; - unsigned int flags; - bool reset; -+ struct dma_pool *ccw_pool; - #define MXS_DMA_SG_LOOP (1 << 0) - #define MXS_DMA_USE_SEMAPHORE (1 << 1) - }; -@@ -415,11 +420,13 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) - { - struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); - struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; -+ struct device *dev = &mxs_dma->pdev->dev; - int ret; - -- mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, -- CCW_BLOCK_SIZE, -- &mxs_chan->ccw_phys, GFP_KERNEL); -+ mxs_chan->ccw = dma_pool_zalloc(mxs_chan->ccw_pool, -+ GFP_ATOMIC, -+ &mxs_chan->ccw_phys); -+ - if (!mxs_chan->ccw) { - ret = -ENOMEM; - goto err_alloc; -@@ -430,9 +437,11 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) - if (ret) - goto err_irq; - -- ret = clk_prepare_enable(mxs_dma->clk); -- if (ret) -+ ret = pm_runtime_get_sync(dev); -+ if (ret < 0) { -+ dev_err(dev, "Failed to enable clock\n"); - goto err_clk; -+ } - - mxs_dma_reset_chan(chan); - -@@ -447,8 +456,8 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) - err_clk: - free_irq(mxs_chan->chan_irq, mxs_dma); - err_irq: -- dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, -- mxs_chan->ccw, mxs_chan->ccw_phys); -+ dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, -+ mxs_chan->ccw_phys); - err_alloc: - return ret; - } -@@ -457,15 +466,18 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan) - { - struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); - struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; -+ struct device *dev = &mxs_dma->pdev->dev; - - mxs_dma_disable_chan(chan); - - free_irq(mxs_chan->chan_irq, mxs_dma); - -- dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, -- mxs_chan->ccw, mxs_chan->ccw_phys); -+ dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, -+ mxs_chan->ccw_phys); -+ -+ pm_runtime_mark_last_busy(dev); -+ pm_runtime_put_autosuspend(dev); - -- clk_disable_unprepare(mxs_dma->clk); - } - - /* -@@ -688,14 +700,32 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, - return mxs_chan->status; - } - --static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) -+static int mxs_dma_init_rpm(struct mxs_dma_engine *mxs_dma) -+{ -+ struct device *dev = &mxs_dma->pdev->dev; -+ -+ pm_runtime_enable(dev); -+ pm_runtime_set_autosuspend_delay(dev, MXS_DMA_RPM_TIMEOUT); -+ pm_runtime_use_autosuspend(dev); -+ -+ return 0; -+} -+ -+static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) - { -+ struct device *dev = &mxs_dma->pdev->dev; - int ret; - -- ret = clk_prepare_enable(mxs_dma->clk); -+ ret = mxs_dma_init_rpm(mxs_dma); - if (ret) - return ret; - -+ ret = pm_runtime_get_sync(dev); -+ if (ret < 0) { -+ dev_err(dev, "Failed to enable clock\n"); -+ return ret; -+ } -+ - ret = stmp_reset_block(mxs_dma->base); - if (ret) - goto err_out; -@@ -713,7 +743,8 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) - mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); - - err_out: -- clk_disable_unprepare(mxs_dma->clk); -+ pm_runtime_mark_last_busy(dev); -+ pm_runtime_put_autosuspend(dev); - return ret; - } - -@@ -728,6 +759,12 @@ static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) - struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; - int chan_irq; - -+ if (strcmp(chan->device->dev->driver->name, "mxs-dma")) -+ return false; -+ -+ if (!mxs_dma) -+ return false; -+ - if (chan->chan_id != param->chan_id) - return false; - -@@ -759,7 +796,7 @@ static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, - ofdma->of_node); - } - --static int __init mxs_dma_probe(struct platform_device *pdev) -+static int mxs_dma_probe(struct platform_device *pdev) - { - struct device_node *np = pdev->dev.of_node; - const struct platform_device_id *id_entry; -@@ -767,6 +804,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev) - const struct mxs_dma_type *dma_type; - struct mxs_dma_engine *mxs_dma; - struct resource *iores; -+ struct dma_pool *ccw_pool; - int ret, i; - - mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); -@@ -813,19 +851,31 @@ static int __init mxs_dma_probe(struct platform_device *pdev) - - tasklet_setup(&mxs_chan->tasklet, mxs_dma_tasklet); - -- - /* Add the channel to mxs_chan list */ - list_add_tail(&mxs_chan->chan.device_node, - &mxs_dma->dma_device.channels); - } - -+ platform_set_drvdata(pdev, mxs_dma); -+ mxs_dma->pdev = pdev; -+ - ret = mxs_dma_init(mxs_dma); - if (ret) - return ret; - -- mxs_dma->pdev = pdev; - mxs_dma->dma_device.dev = &pdev->dev; - -+ /* create the dma pool */ -+ ccw_pool = dma_pool_create("ccw_pool", -+ mxs_dma->dma_device.dev, -+ CCW_BLOCK_SIZE, 32, 0); -+ -+ for (i = 0; i < MXS_DMA_CHANNELS; i++) { -+ struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; -+ -+ mxs_chan->ccw_pool = ccw_pool; -+ } -+ - /* mxs_dma gets 65535 bytes maximum sg size */ - dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); - -@@ -860,16 +910,83 @@ static int __init mxs_dma_probe(struct platform_device *pdev) - return 0; - } - -+static int mxs_dma_remove(struct platform_device *pdev) -+{ -+ struct mxs_dma_engine *mxs_dma = platform_get_drvdata(pdev); -+ int i; -+ -+ dma_async_device_unregister(&mxs_dma->dma_device); -+ dma_pool_destroy(mxs_dma->mxs_chans[0].ccw_pool); -+ -+ for (i = 0; i < MXS_DMA_CHANNELS; i++) { -+ struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; -+ -+ tasklet_kill(&mxs_chan->tasklet); -+ mxs_chan->ccw_pool = NULL; -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+static int mxs_dma_pm_suspend(struct device *dev) -+{ -+ int ret; -+ -+ ret = pm_runtime_force_suspend(dev); -+ -+ return ret; -+} -+ -+static int mxs_dma_pm_resume(struct device *dev) -+{ -+ struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = mxs_dma_init(mxs_dma); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+#endif -+ -+int mxs_dma_runtime_suspend(struct device *dev) -+{ -+ struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(mxs_dma->clk); -+ -+ return 0; -+} -+ -+int mxs_dma_runtime_resume(struct device *dev) -+{ -+ struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = clk_prepare_enable(mxs_dma->clk); -+ if (ret) { -+ dev_err(&mxs_dma->pdev->dev, "failed to enable the clock\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops mxs_dma_pm_ops = { -+ SET_RUNTIME_PM_OPS(mxs_dma_runtime_suspend, mxs_dma_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(mxs_dma_pm_suspend, mxs_dma_pm_resume) -+}; -+ - static struct platform_driver mxs_dma_driver = { - .driver = { - .name = "mxs-dma", -+ .pm = &mxs_dma_pm_ops, - .of_match_table = mxs_dma_dt_ids, - }, - .id_table = mxs_dma_ids, -+ .remove = mxs_dma_remove, -+ .probe = mxs_dma_probe, - }; -- --static int __init mxs_dma_module_init(void) --{ -- return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); --} --subsys_initcall(mxs_dma_module_init); -+module_platform_driver(mxs_dma_driver); -diff --git a/drivers/dma/pxp/Kconfig b/drivers/dma/pxp/Kconfig -new file mode 100644 -index 000000000..ece36cb18 ---- /dev/null -+++ b/drivers/dma/pxp/Kconfig -@@ -0,0 +1,21 @@ -+config MXC_PXP_V2 -+ bool "MXC PxP V2 support" -+ depends on ARM -+ select DMA_ENGINE -+ help -+ Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite. -+ If unsure, select N. -+ -+config MXC_PXP_V3 -+ bool "MXC PxP V3 support" -+ select DMA_ENGINE -+ help -+ Support the PxP V3(Pixel Pipeline) on i.MX7D. The PxP V3 supports -+ more functions than PxP V2, dithering, reagl/-D and etc. -+ If unsure, select N. -+ -+config MXC_PXP_CLIENT_DEVICE -+ bool "MXC PxP Client Device" -+ default y -+ depends on MXC_PXP_V2 || MXC_PXP_V3 -+ -diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile -new file mode 100644 -index 000000000..42e4ace02 ---- /dev/null -+++ b/drivers/dma/pxp/Makefile -@@ -0,0 +1,3 @@ -+obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o -+obj-$(CONFIG_MXC_PXP_V3) += pxp_dma_v3.o -+obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o -diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c -new file mode 100644 -index 000000000..6a8b95858 ---- /dev/null -+++ b/drivers/dma/pxp/pxp_device.c -@@ -0,0 +1,1120 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BUFFER_HASH_ORDER 4 -+ -+static struct pxp_buffer_hash bufhash; -+static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; -+static int major; -+static struct class *pxp_class; -+static struct device *pxp_dev; -+ -+static int pxp_ht_create(struct pxp_buffer_hash *hash, int order) -+{ -+ unsigned long i; -+ unsigned long table_size; -+ -+ table_size = 1U << order; -+ -+ hash->order = order; -+ hash->hash_table = kmalloc(sizeof(*hash->hash_table) * table_size, GFP_KERNEL); -+ -+ if (!hash->hash_table) { -+ pr_err("%s: Out of memory for hash table\n", __func__); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < table_size; i++) -+ INIT_HLIST_HEAD(&hash->hash_table[i]); -+ -+ return 0; -+} -+ -+static int pxp_ht_insert_item(struct pxp_buffer_hash *hash, -+ struct pxp_buf_obj *new) -+{ -+ unsigned long hashkey; -+ struct hlist_head *h_list; -+ -+ hashkey = hash_long(new->offset >> PAGE_SHIFT, hash->order); -+ h_list = &hash->hash_table[hashkey]; -+ -+ spin_lock(&hash->hash_lock); -+ hlist_add_head_rcu(&new->item, h_list); -+ spin_unlock(&hash->hash_lock); -+ -+ return 0; -+} -+ -+static int pxp_ht_remove_item(struct pxp_buffer_hash *hash, -+ struct pxp_buf_obj *obj) -+{ -+ spin_lock(&hash->hash_lock); -+ hlist_del_init_rcu(&obj->item); -+ spin_unlock(&hash->hash_lock); -+ return 0; -+} -+ -+static struct hlist_node *pxp_ht_find_key(struct pxp_buffer_hash *hash, -+ unsigned long key) -+{ -+ struct pxp_buf_obj *entry; -+ struct hlist_head *h_list; -+ unsigned long hashkey; -+ -+ hashkey = hash_long(key, hash->order); -+ h_list = &hash->hash_table[hashkey]; -+ -+ hlist_for_each_entry_rcu(entry, h_list, item) { -+ if (entry->offset >> PAGE_SHIFT == key) -+ return &entry->item; -+ } -+ -+ return NULL; -+} -+ -+static void pxp_ht_destroy(struct pxp_buffer_hash *hash) -+{ -+ kfree(hash->hash_table); -+ hash->hash_table = NULL; -+} -+ -+static int pxp_buffer_handle_create(struct pxp_file *file_priv, -+ struct pxp_buf_obj *obj, -+ uint32_t *handlep) -+{ -+ int ret; -+ -+ idr_preload(GFP_KERNEL); -+ spin_lock(&file_priv->buffer_lock); -+ -+ ret = idr_alloc(&file_priv->buffer_idr, obj, 1, 0, GFP_NOWAIT); -+ -+ spin_unlock(&file_priv->buffer_lock); -+ idr_preload_end(); -+ -+ if (ret < 0) -+ return ret; -+ -+ *handlep = ret; -+ -+ return 0; -+} -+ -+static struct pxp_buf_obj * -+pxp_buffer_object_lookup(struct pxp_file *file_priv, -+ uint32_t handle) -+{ -+ struct pxp_buf_obj *obj; -+ -+ spin_lock(&file_priv->buffer_lock); -+ -+ obj = idr_find(&file_priv->buffer_idr, handle); -+ if (!obj) { -+ spin_unlock(&file_priv->buffer_lock); -+ return NULL; -+ } -+ -+ spin_unlock(&file_priv->buffer_lock); -+ -+ return obj; -+} -+ -+static int pxp_buffer_handle_delete(struct pxp_file *file_priv, -+ uint32_t handle) -+{ -+ struct pxp_buf_obj *obj; -+ -+ spin_lock(&file_priv->buffer_lock); -+ -+ obj = idr_find(&file_priv->buffer_idr, handle); -+ if (!obj) { -+ spin_unlock(&file_priv->buffer_lock); -+ return -EINVAL; -+ } -+ -+ idr_remove(&file_priv->buffer_idr, handle); -+ spin_unlock(&file_priv->buffer_lock); -+ -+ return 0; -+} -+ -+static int pxp_channel_handle_create(struct pxp_file *file_priv, -+ struct pxp_chan_obj *obj, -+ uint32_t *handlep) -+{ -+ int ret; -+ -+ idr_preload(GFP_KERNEL); -+ spin_lock(&file_priv->channel_lock); -+ -+ ret = idr_alloc(&file_priv->channel_idr, obj, 0, 0, GFP_NOWAIT); -+ -+ spin_unlock(&file_priv->channel_lock); -+ idr_preload_end(); -+ -+ if (ret < 0) -+ return ret; -+ -+ *handlep = ret; -+ -+ return 0; -+} -+ -+static struct pxp_chan_obj * -+pxp_channel_object_lookup(struct pxp_file *file_priv, -+ uint32_t handle) -+{ -+ struct pxp_chan_obj *obj; -+ -+ spin_lock(&file_priv->channel_lock); -+ -+ obj = idr_find(&file_priv->channel_idr, handle); -+ if (!obj) { -+ spin_unlock(&file_priv->channel_lock); -+ return NULL; -+ } -+ -+ spin_unlock(&file_priv->channel_lock); -+ -+ return obj; -+} -+ -+static int pxp_channel_handle_delete(struct pxp_file *file_priv, -+ uint32_t handle) -+{ -+ struct pxp_chan_obj *obj; -+ -+ spin_lock(&file_priv->channel_lock); -+ -+ obj = idr_find(&file_priv->channel_idr, handle); -+ if (!obj) { -+ spin_unlock(&file_priv->channel_lock); -+ return -EINVAL; -+ } -+ -+ idr_remove(&file_priv->channel_idr, handle); -+ spin_unlock(&file_priv->channel_lock); -+ -+ return 0; -+} -+ -+static int pxp_alloc_dma_buffer(struct pxp_buf_obj *obj) -+{ -+ obj->virtual = dma_alloc_coherent(pxp_dev, PAGE_ALIGN(obj->size), -+ (dma_addr_t *) (&obj->offset), -+ GFP_DMA | GFP_KERNEL); -+ pr_debug("[ALLOC] mem alloc phys_addr = 0x%lx\n", obj->offset); -+ -+ if (obj->virtual == NULL) { -+ printk(KERN_ERR "Physical memory allocation error!\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static void pxp_free_dma_buffer(struct pxp_buf_obj *obj) -+{ -+ if (obj->virtual != NULL) { -+ dma_free_coherent(pxp_dev, PAGE_ALIGN(obj->size), -+ obj->virtual, (dma_addr_t)obj->offset); -+ } -+} -+ -+static int -+pxp_buffer_object_free(int id, void *ptr, void *data) -+{ -+ struct pxp_file *file_priv = data; -+ struct pxp_buf_obj *obj = ptr; -+ int ret; -+ -+ ret = pxp_buffer_handle_delete(file_priv, obj->handle); -+ if (ret < 0) -+ return ret; -+ -+ pxp_ht_remove_item(&bufhash, obj); -+ pxp_free_dma_buffer(obj); -+ kfree(obj); -+ -+ return 0; -+} -+ -+static int -+pxp_channel_object_free(int id, void *ptr, void *data) -+{ -+ struct pxp_file *file_priv = data; -+ struct pxp_chan_obj *obj = ptr; -+ int chan_id; -+ -+ chan_id = obj->chan->chan_id; -+ wait_event(irq_info[chan_id].waitq, -+ atomic_read(&irq_info[chan_id].irq_pending) == 0); -+ -+ pxp_channel_handle_delete(file_priv, obj->handle); -+ dma_release_channel(obj->chan); -+ kfree(obj); -+ -+ return 0; -+} -+ -+static void pxp_free_buffers(struct pxp_file *file_priv) -+{ -+ idr_for_each(&file_priv->buffer_idr, -+ &pxp_buffer_object_free, file_priv); -+ idr_destroy(&file_priv->buffer_idr); -+} -+ -+static void pxp_free_channels(struct pxp_file *file_priv) -+{ -+ idr_for_each(&file_priv->channel_idr, -+ &pxp_channel_object_free, file_priv); -+ idr_destroy(&file_priv->channel_idr); -+} -+ -+/* Callback function triggered after PxP receives an EOF interrupt */ -+static void pxp_dma_done(void *arg) -+{ -+ struct pxp_tx_desc *tx_desc = to_tx_desc(arg); -+ struct dma_chan *chan = tx_desc->txd.chan; -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ int chan_id = pxp_chan->dma_chan.chan_id; -+ -+ pr_debug("DMA Done ISR, chan_id %d\n", chan_id); -+ -+ atomic_dec(&irq_info[chan_id].irq_pending); -+ irq_info[chan_id].hist_status = tx_desc->hist_status; -+ -+ wake_up(&(irq_info[chan_id].waitq)); -+} -+ -+static int pxp_ioc_config_chan(struct pxp_file *priv, unsigned long arg) -+{ -+ struct scatterlist *sg; -+ struct pxp_tx_desc *desc; -+ struct dma_async_tx_descriptor *txd; -+ struct pxp_config_data *pxp_conf; -+ dma_cookie_t cookie; -+ int handle, chan_id; -+ struct dma_chan *chan; -+ struct pxp_chan_obj *obj; -+ int i = 0, j = 0, k = 0, m = 0, length, ret, sg_len; -+ -+ pxp_conf = kzalloc(sizeof(*pxp_conf), GFP_KERNEL); -+ if (!pxp_conf) -+ return -ENOMEM; -+ -+ ret = copy_from_user(pxp_conf, -+ (struct pxp_config_data *)arg, -+ sizeof(struct pxp_config_data)); -+ if (ret) { -+ kfree(pxp_conf); -+ return -EFAULT; -+ } -+ -+ handle = pxp_conf->handle; -+ obj = pxp_channel_object_lookup(priv, handle); -+ if (!obj) { -+ kfree(pxp_conf); -+ return -EINVAL; -+ } -+ chan = obj->chan; -+ chan_id = chan->chan_id; -+ -+ sg_len = 3; -+ if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) -+ sg_len += 4; -+ if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) -+ sg_len += 4; -+ if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) -+ sg_len += 4; -+ -+ sg = kmalloc(sizeof(*sg) * sg_len, GFP_KERNEL); -+ if (!sg) { -+ kfree(pxp_conf); -+ return -ENOMEM; -+ } -+ -+ sg_init_table(sg, sg_len); -+ -+ txd = chan->device->device_prep_slave_sg(chan, -+ sg, sg_len, -+ DMA_TO_DEVICE, -+ DMA_PREP_INTERRUPT, -+ NULL); -+ if (!txd) { -+ pr_err("Error preparing a DMA transaction descriptor.\n"); -+ kfree(pxp_conf); -+ kfree(sg); -+ return -EIO; -+ } -+ -+ txd->callback_param = txd; -+ txd->callback = pxp_dma_done; -+ -+ desc = to_tx_desc(txd); -+ -+ length = desc->len; -+ for (i = 0; i < length; i++) { -+ if (i == 0) { /* S0 */ -+ memcpy(&desc->proc_data, -+ &pxp_conf->proc_data, -+ sizeof(struct pxp_proc_data)); -+ memcpy(&desc->layer_param.s0_param, -+ &pxp_conf->s0_param, -+ sizeof(struct pxp_layer_param)); -+ desc = desc->next; -+ } else if (i == 1) { /* Output */ -+ memcpy(&desc->layer_param.out_param, -+ &pxp_conf->out_param, -+ sizeof(struct pxp_layer_param)); -+ desc = desc->next; -+ } else if (i == 2) { -+ /* OverLay */ -+ memcpy(&desc->layer_param.ol_param, -+ &pxp_conf->ol_param, -+ sizeof(struct pxp_layer_param)); -+ desc = desc->next; -+ } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) && (j < 4)) { -+ for (j = 0; j < 4; j++) { -+ if (j == 0) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_a_fetch_param[0], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH0; -+ } else if (j == 1) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_a_fetch_param[1], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH1; -+ } else if (j == 2) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_a_store_param[0], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE0; -+ } else if (j == 3) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_a_store_param[1], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE1; -+ } -+ -+ desc = desc->next; -+ } -+ -+ i += 4; -+ -+ } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) && (m < 4)) { -+ for (m = 0; m < 4; m++) { -+ if (m == 0) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_b_fetch_param[0], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH0; -+ } else if (m == 1) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_b_fetch_param[1], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH1; -+ } else if (m == 2) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_b_store_param[0], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE0; -+ } else if (m == 3) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->wfe_b_store_param[1], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE1; -+ } -+ -+ desc = desc->next; -+ } -+ -+ i += 4; -+ -+ } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) && (k < 4)) { -+ for (k = 0; k < 4; k++) { -+ if (k == 0) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->dither_fetch_param[0], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH0; -+ } else if (k == 1) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->dither_fetch_param[1], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH1; -+ } else if (k == 2) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->dither_store_param[0], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE0; -+ } else if (k == 3) { -+ memcpy(&desc->layer_param.processing_param, -+ &pxp_conf->dither_store_param[1], -+ sizeof(struct pxp_layer_param)); -+ desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE1; -+ } -+ -+ desc = desc->next; -+ } -+ -+ i += 4; -+ } -+ } -+ -+ cookie = txd->tx_submit(txd); -+ if (cookie < 0) { -+ pr_err("Error tx_submit\n"); -+ kfree(pxp_conf); -+ kfree(sg); -+ return -EIO; -+ } -+ -+ atomic_inc(&irq_info[chan_id].irq_pending); -+ -+ kfree(pxp_conf); -+ kfree(sg); -+ -+ return 0; -+} -+ -+static int pxp_device_open(struct inode *inode, struct file *filp) -+{ -+ struct pxp_file *priv; -+ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ -+ if (!priv) -+ return -ENOMEM; -+ -+ filp->private_data = priv; -+ priv->filp = filp; -+ -+ idr_init(&priv->buffer_idr); -+ spin_lock_init(&priv->buffer_lock); -+ -+ idr_init(&priv->channel_idr); -+ spin_lock_init(&priv->channel_lock); -+ -+ return 0; -+} -+ -+static int pxp_device_release(struct inode *inode, struct file *filp) -+{ -+ struct pxp_file *priv = filp->private_data; -+ -+ if (priv) { -+ pxp_free_channels(priv); -+ pxp_free_buffers(priv); -+ kfree(priv); -+ filp->private_data = NULL; -+ } -+ -+ return 0; -+} -+ -+static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ int request_size; -+ struct hlist_node *node; -+ struct pxp_buf_obj *obj; -+ -+ request_size = vma->vm_end - vma->vm_start; -+ -+ pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", -+ (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), -+ request_size); -+ -+ node = pxp_ht_find_key(&bufhash, vma->vm_pgoff); -+ if (!node) -+ return -EINVAL; -+ -+ obj = list_entry(node, struct pxp_buf_obj, item); -+ if (obj->offset + (obj->size >> PAGE_SHIFT) < -+ (vma->vm_pgoff + vma_pages(vma))) -+ return -ENOMEM; -+ -+ switch (obj->mem_type) { -+ case MEMORY_TYPE_UNCACHED: -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ break; -+ case MEMORY_TYPE_WC: -+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); -+ break; -+ case MEMORY_TYPE_CACHED: -+ break; -+ default: -+ pr_err("%s: invalid memory type!\n", __func__); -+ return -EINVAL; -+ } -+ -+ return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, -+ request_size, vma->vm_page_prot) ? -EAGAIN : 0; -+} -+ -+static bool chan_filter(struct dma_chan *chan, void *arg) -+{ -+ if (imx_dma_is_pxp(chan)) -+ return true; -+ else -+ return false; -+} -+ -+/*********************************************/ -+/* DMABUF ops for exporters */ -+/*********************************************/ -+ -+static struct sg_table *pxp_get_base_sgt(struct pxp_buf_obj *obj) -+{ -+ int ret; -+ struct sg_table *sgt; -+ -+ sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); -+ if (!sgt) { -+ dev_err(pxp_dev, "failed to alloc sg table\n"); -+ return NULL; -+ } -+ -+ ret = dma_get_sgtable_attrs(pxp_dev, sgt, obj->virtual, -+ (dma_addr_t)obj->offset, -+ PAGE_ALIGN(obj->size), obj->attrs); -+ if (ret < 0) { -+ dev_err(pxp_dev, "failed to get scatterlist from DMA API\n"); -+ kfree(sgt); -+ return NULL; -+ } -+ -+ return sgt; -+} -+ -+ -+static int pxp_dmabuf_ops_attach(struct dma_buf *dbuf, -+ struct dma_buf_attachment *dbuf_attach) -+{ -+ struct pxp_attachment *attach; -+ struct sg_table *sgt; -+ struct scatterlist *rd, *wr; -+ struct pxp_buf_obj *obj = dbuf->priv; -+ int ret, i; -+ -+ attach = kzalloc(sizeof(*attach), GFP_KERNEL); -+ if (!attach) -+ return -ENOMEM; -+ -+ sgt = &attach->sgt; -+ ret = sg_alloc_table(sgt, obj->sgt_base->orig_nents, GFP_KERNEL); -+ if (ret) { -+ kfree(attach); -+ return -ENOMEM; -+ } -+ -+ rd = obj->sgt_base->sgl; -+ wr = sgt->sgl; -+ for (i = 0; i < sgt->orig_nents; ++i) { -+ sg_set_page(wr, sg_page(rd), rd->length, rd->offset); -+ rd = sg_next(rd); -+ wr = sg_next(wr); -+ } -+ -+ attach->dma_dir = DMA_NONE; -+ dbuf_attach->priv = attach; -+ -+ return 0; -+} -+ -+static void pxp_dmabuf_ops_detach(struct dma_buf *dbuf, -+ struct dma_buf_attachment *db_attach) -+{ -+ struct pxp_attachment *attach = db_attach->priv; -+ struct sg_table *sgt; -+ -+ if (!attach) -+ return; -+ -+ sgt = &attach->sgt; -+ -+ if (attach->dma_dir != DMA_NONE) -+ dma_unmap_sgtable(db_attach->dev, sgt, attach->dma_dir, -+ DMA_ATTR_SKIP_CPU_SYNC); -+ sg_free_table(sgt); -+ kfree(attach); -+ db_attach->priv = NULL; -+} -+ -+static struct sg_table *pxp_dmabuf_ops_map( -+ struct dma_buf_attachment *db_attach, enum dma_data_direction dma_dir) -+{ -+ struct pxp_attachment *attach = db_attach->priv; -+ struct mutex *lock = &db_attach->dmabuf->lock; -+ struct sg_table *sgt; -+ -+ mutex_lock(lock); -+ -+ sgt = &attach->sgt; -+ /* return previously mapped sg table */ -+ if (attach->dma_dir == dma_dir) { -+ mutex_unlock(lock); -+ return sgt; -+ } -+ -+ /* release any previous cache */ -+ if (attach->dma_dir != DMA_NONE) { -+ dma_unmap_sgtable(db_attach->dev, sgt, attach->dma_dir, -+ DMA_ATTR_SKIP_CPU_SYNC); -+ attach->dma_dir = DMA_NONE; -+ } -+ -+ /* -+ * mapping to the client with new direction, no cache sync -+ * required see comment in vb2_dc_dmabuf_ops_detach() -+ */ -+ if (dma_map_sgtable(db_attach->dev, sgt, dma_dir, -+ DMA_ATTR_SKIP_CPU_SYNC)) { -+ pr_err("failed to map scatterlist\n"); -+ mutex_unlock(lock); -+ return ERR_PTR(-EIO); -+ } -+ -+ attach->dma_dir = dma_dir; -+ -+ mutex_unlock(lock); -+ -+ return sgt; -+} -+ -+static void pxp_dmabuf_ops_unmap(struct dma_buf_attachment *db_attach, -+ struct sg_table *sgt, -+ enum dma_data_direction dma_dir) -+{ -+ /* nothing to be done here */ -+} -+ -+static void pxp_dmabuf_ops_release(struct dma_buf *dbuf) -+{ -+ /* nothing to be done here */ -+} -+ -+static int -+pxp_dmabuf_ops_begin_cpu_access(struct dma_buf *dbuf, -+ enum dma_data_direction direction) -+{ -+ return 0; -+} -+ -+static int -+pxp_dmabuf_ops_end_cpu_access(struct dma_buf *dbuf, -+ enum dma_data_direction direction) -+{ -+ return 0; -+} -+ -+static void *pxp_dmabuf_ops_vmap(struct dma_buf *dbuf) -+{ -+ struct pxp_buf_obj *obj = dbuf->priv; -+ -+ return obj->virtual; -+} -+ -+static int pxp_dmabuf_ops_mmap(struct dma_buf *dbuf, -+ struct vm_area_struct *vma) -+{ -+ /* Don't support so far */ -+ return 0; -+} -+ -+static const struct dma_buf_ops pxp_dmabuf_ops = { -+ .attach = pxp_dmabuf_ops_attach, -+ .detach = pxp_dmabuf_ops_detach, -+ .map_dma_buf = pxp_dmabuf_ops_map, -+ .unmap_dma_buf = pxp_dmabuf_ops_unmap, -+ .begin_cpu_access = pxp_dmabuf_ops_begin_cpu_access, -+ .end_cpu_access = pxp_dmabuf_ops_end_cpu_access, -+ .vmap = pxp_dmabuf_ops_vmap, -+ .mmap = pxp_dmabuf_ops_mmap, -+ .release = pxp_dmabuf_ops_release, -+}; -+ -+static long pxp_device_ioctl(struct file *filp, -+ unsigned int cmd, unsigned long arg) -+{ -+ int ret = 0; -+ struct pxp_file *file_priv = filp->private_data; -+ -+ switch (cmd) { -+ case PXP_IOC_GET_CHAN: -+ { -+ int ret; -+ struct dma_chan *chan = NULL; -+ dma_cap_mask_t mask; -+ struct pxp_chan_obj *obj = NULL; -+ -+ pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); -+ -+ dma_cap_zero(mask); -+ dma_cap_set(DMA_SLAVE, mask); -+ dma_cap_set(DMA_PRIVATE, mask); -+ -+ chan = dma_request_channel(mask, chan_filter, NULL); -+ if (!chan) { -+ pr_err("Unsccessfully received channel!\n"); -+ return -EBUSY; -+ } -+ -+ pr_debug("Successfully received channel." -+ "chan_id %d\n", chan->chan_id); -+ -+ obj = kzalloc(sizeof(*obj), GFP_KERNEL); -+ if (!obj) { -+ dma_release_channel(chan); -+ return -ENOMEM; -+ } -+ obj->chan = chan; -+ -+ ret = pxp_channel_handle_create(file_priv, obj, -+ &obj->handle); -+ if (ret) { -+ dma_release_channel(chan); -+ kfree(obj); -+ return ret; -+ } -+ -+ init_waitqueue_head(&(irq_info[chan->chan_id].waitq)); -+ if (put_user(obj->handle, (u32 __user *) arg)) { -+ pxp_channel_handle_delete(file_priv, obj->handle); -+ dma_release_channel(chan); -+ kfree(obj); -+ return -EFAULT; -+ } -+ -+ break; -+ } -+ case PXP_IOC_PUT_CHAN: -+ { -+ int handle; -+ struct pxp_chan_obj *obj; -+ -+ if (get_user(handle, (u32 __user *) arg)) -+ return -EFAULT; -+ -+ pr_debug("%d release handle %d\n", __LINE__, handle); -+ -+ obj = pxp_channel_object_lookup(file_priv, handle); -+ if (!obj) -+ return -EINVAL; -+ -+ pxp_channel_handle_delete(file_priv, obj->handle); -+ dma_release_channel(obj->chan); -+ kfree(obj); -+ -+ break; -+ } -+ case PXP_IOC_CONFIG_CHAN: -+ { -+ int ret; -+ -+ ret = pxp_ioc_config_chan(file_priv, arg); -+ if (ret) -+ return ret; -+ -+ break; -+ } -+ case PXP_IOC_START_CHAN: -+ { -+ int handle; -+ struct pxp_chan_obj *obj = NULL; -+ -+ if (get_user(handle, (u32 __user *) arg)) -+ return -EFAULT; -+ -+ obj = pxp_channel_object_lookup(file_priv, handle); -+ if (!obj) -+ return -EINVAL; -+ -+ dma_async_issue_pending(obj->chan); -+ -+ break; -+ } -+ case PXP_IOC_GET_PHYMEM: -+ { -+ struct pxp_mem_desc buffer; -+ struct pxp_buf_obj *obj; -+ -+ ret = copy_from_user(&buffer, -+ (struct pxp_mem_desc *)arg, -+ sizeof(struct pxp_mem_desc)); -+ if (ret) -+ return -EFAULT; -+ -+ pr_debug("[ALLOC] mem alloc size = 0x%x\n", -+ buffer.size); -+ -+ obj = kzalloc(sizeof(*obj), GFP_KERNEL); -+ if (!obj) -+ return -ENOMEM; -+ obj->size = buffer.size; -+ obj->mem_type = buffer.mtype; -+ -+ ret = pxp_alloc_dma_buffer(obj); -+ if (ret == -1) { -+ printk(KERN_ERR -+ "Physical memory allocation error!\n"); -+ kfree(obj); -+ return ret; -+ } -+ -+ ret = pxp_buffer_handle_create(file_priv, obj, &obj->handle); -+ if (ret) { -+ pxp_free_dma_buffer(obj); -+ kfree(obj); -+ return ret; -+ } -+ buffer.handle = obj->handle; -+ buffer.phys_addr = obj->offset; -+ -+ ret = copy_to_user((void __user *)arg, &buffer, -+ sizeof(struct pxp_mem_desc)); -+ if (ret) { -+ pxp_buffer_handle_delete(file_priv, buffer.handle); -+ pxp_free_dma_buffer(obj); -+ kfree(obj); -+ return -EFAULT; -+ } -+ -+ pxp_ht_insert_item(&bufhash, obj); -+ -+ break; -+ } -+ case PXP_IOC_PUT_PHYMEM: -+ { -+ struct pxp_mem_desc pxp_mem; -+ struct pxp_buf_obj *obj; -+ -+ ret = copy_from_user(&pxp_mem, -+ (struct pxp_mem_desc *)arg, -+ sizeof(struct pxp_mem_desc)); -+ if (ret) -+ return -EACCES; -+ -+ obj = pxp_buffer_object_lookup(file_priv, pxp_mem.handle); -+ if (!obj) -+ return -EINVAL; -+ -+ if (obj->sgt_base) { -+ sg_free_table(obj->sgt_base); -+ kfree(obj->sgt_base); -+ } -+ -+ ret = pxp_buffer_handle_delete(file_priv, obj->handle); -+ if (ret) -+ return ret; -+ -+ pxp_ht_remove_item(&bufhash, obj); -+ pxp_free_dma_buffer(obj); -+ kfree(obj); -+ -+ break; -+ } -+ case PXP_IOC_FLUSH_PHYMEM: -+ { -+ int ret; -+ struct pxp_mem_flush flush; -+ struct pxp_buf_obj *obj; -+ -+ ret = copy_from_user(&flush, -+ (struct pxp_mem_flush *)arg, -+ sizeof(struct pxp_mem_flush)); -+ if (ret) -+ return -EACCES; -+ -+ obj = pxp_buffer_object_lookup(file_priv, flush.handle); -+ if (!obj) -+ return -EINVAL; -+ -+ switch (flush.type) { -+ case CACHE_CLEAN: -+ dma_sync_single_for_device(pxp_dev, obj->offset, -+ obj->size, DMA_TO_DEVICE); -+ break; -+ case CACHE_INVALIDATE: -+ dma_sync_single_for_device(pxp_dev, obj->offset, -+ obj->size, DMA_FROM_DEVICE); -+ break; -+ case CACHE_FLUSH: -+ dma_sync_single_for_device(pxp_dev, obj->offset, -+ obj->size, DMA_TO_DEVICE); -+ dma_sync_single_for_device(pxp_dev, obj->offset, -+ obj->size, DMA_FROM_DEVICE); -+ break; -+ default: -+ pr_err("%s: invalid cache flush type\n", __func__); -+ return -EINVAL; -+ } -+ -+ break; -+ } -+ case PXP_IOC_WAIT4CMPLT: -+ { -+ struct pxp_chan_handle chan_handle; -+ int ret, chan_id, handle; -+ struct pxp_chan_obj *obj = NULL; -+ -+ ret = copy_from_user(&chan_handle, -+ (struct pxp_chan_handle *)arg, -+ sizeof(struct pxp_chan_handle)); -+ if (ret) -+ return -EFAULT; -+ -+ handle = chan_handle.handle; -+ obj = pxp_channel_object_lookup(file_priv, handle); -+ if (!obj) -+ return -EINVAL; -+ chan_id = obj->chan->chan_id; -+ -+ ret = wait_event_interruptible -+ (irq_info[chan_id].waitq, -+ (atomic_read(&irq_info[chan_id].irq_pending) == 0)); -+ if (ret < 0) -+ return -ERESTARTSYS; -+ -+ chan_handle.hist_status = irq_info[chan_id].hist_status; -+ ret = copy_to_user((struct pxp_chan_handle *)arg, -+ &chan_handle, -+ sizeof(struct pxp_chan_handle)); -+ if (ret) -+ return -EFAULT; -+ break; -+ } -+ case PXP_IOC_EXPBUF: -+ { -+ struct pxp_mem_desc buffer; -+ struct dma_buf *dbuf; -+ struct pxp_buf_obj *obj; -+ DEFINE_DMA_BUF_EXPORT_INFO(pxp_exp_info); -+ -+ ret = copy_from_user(&buffer, (struct pxp_mem_desc *)arg, -+ sizeof(struct pxp_mem_desc)); -+ if (ret) -+ return -EFAULT; -+ -+ obj = pxp_buffer_object_lookup(file_priv, buffer.handle); -+ if (!obj) -+ return -EINVAL; -+ -+ if (!obj->sgt_base) -+ obj->sgt_base = pxp_get_base_sgt(obj); -+ -+ if (WARN_ON(!obj->sgt_base)) -+ return -EINVAL; -+ -+ pxp_exp_info.ops = &pxp_dmabuf_ops; -+ pxp_exp_info.flags = buffer.flags; -+ pxp_exp_info.size = obj->size; -+ pxp_exp_info.priv = obj; -+ -+ dbuf = dma_buf_export(&pxp_exp_info); -+ if (IS_ERR(dbuf)) -+ return PTR_ERR(dbuf); -+ -+ /* need to check buffer.flags */ -+ ret = dma_buf_fd(dbuf, buffer.flags & ~O_ACCMODE); -+ if (ret < 0) -+ return ret; -+ buffer.fd = ret; -+ -+ ret = copy_to_user((void __user *)arg, &buffer, -+ sizeof(struct pxp_mem_desc)); -+ if (ret) -+ return -EFAULT; -+ break; -+ } -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static const struct file_operations pxp_device_fops = { -+ .open = pxp_device_open, -+ .release = pxp_device_release, -+ .unlocked_ioctl = pxp_device_ioctl, -+ .mmap = pxp_device_mmap, -+}; -+ -+int register_pxp_device(void) -+{ -+ int ret; -+ -+ if (!major) { -+ major = register_chrdev(0, "pxp_device", &pxp_device_fops); -+ if (major < 0) { -+ printk(KERN_ERR "Unable to register pxp device\n"); -+ ret = major; -+ goto register_cdev_fail; -+ } -+ -+ pxp_class = class_create(THIS_MODULE, "pxp_device"); -+ if (IS_ERR(pxp_class)) { -+ ret = PTR_ERR(pxp_class); -+ goto pxp_class_fail; -+ } -+ -+ pxp_dev = device_create(pxp_class, NULL, MKDEV(major, 0), -+ NULL, "pxp_device"); -+ if (IS_ERR(pxp_dev)) { -+ ret = PTR_ERR(pxp_dev); -+ goto dev_create_fail; -+ } -+ pxp_dev->dma_mask = kmalloc(sizeof(*pxp_dev->dma_mask), -+ GFP_KERNEL); -+ *pxp_dev->dma_mask = DMA_BIT_MASK(32); -+ pxp_dev->coherent_dma_mask = DMA_BIT_MASK(32); -+ } -+ -+ ret = pxp_ht_create(&bufhash, BUFFER_HASH_ORDER); -+ if (ret) { -+ goto ht_create_fail; -+ } -+ spin_lock_init(&(bufhash.hash_lock)); -+ -+ pr_debug("PxP_Device registered Successfully\n"); -+ return 0; -+ -+ht_create_fail: -+ device_destroy(pxp_class, MKDEV(major, 0)); -+dev_create_fail: -+ class_destroy(pxp_class); -+pxp_class_fail: -+ unregister_chrdev(major, "pxp_device"); -+register_cdev_fail: -+ return ret; -+} -+ -+void unregister_pxp_device(void) -+{ -+ pxp_ht_destroy(&bufhash); -+ if (major) { -+ device_destroy(pxp_class, MKDEV(major, 0)); -+ class_destroy(pxp_class); -+ unregister_chrdev(major, "pxp_device"); -+ major = 0; -+ } -+} -diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c -new file mode 100644 -index 000000000..5f26f4b2e ---- /dev/null -+++ b/drivers/dma/pxp/pxp_dma_v2.c -@@ -0,0 +1,1849 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017-2019 NXP -+ */ -+/* -+ * Based on STMP378X PxP driver -+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "regs-pxp_v2.h" -+ -+#define PXP_DOWNSCALE_THRESHOLD 0x4000 -+ -+static LIST_HEAD(head); -+static int timeout_in_ms = 600; -+static unsigned int block_size; -+static struct kmem_cache *tx_desc_cache; -+ -+struct pxp_dma { -+ struct dma_device dma; -+}; -+ -+struct pxps { -+ struct platform_device *pdev; -+ struct clk *clk; -+ struct clk *clk_disp_axi; /* may exist on some SoC for gating */ -+ void __iomem *base; -+ int irq; /* PXP IRQ to the CPU */ -+ -+ spinlock_t lock; -+ struct mutex clk_mutex; -+ int clk_stat; -+#define CLK_STAT_OFF 0 -+#define CLK_STAT_ON 1 -+ int pxp_ongoing; -+ int lut_state; -+ -+ struct device *dev; -+ struct pxp_dma pxp_dma; -+ struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; -+ struct work_struct work; -+ -+ /* describes most recent processing configuration */ -+ struct pxp_config_data pxp_conf_state; -+ -+ /* to turn clock off when pxp is inactive */ -+ struct timer_list clk_timer; -+ -+ /* for pxp config dispatch asynchronously*/ -+ struct task_struct *dispatch; -+ wait_queue_head_t thread_waitq; -+ struct completion complete; -+}; -+ -+#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) -+#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) -+#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) -+#define to_pxp(id) container_of(id, struct pxps, pxp_dma) -+ -+#define PXP_DEF_BUFS 2 -+#define PXP_MIN_PIX 8 -+ -+/* -+ * PXP common functions -+ */ -+static void dump_pxp_reg(struct pxps *pxp) -+{ -+ dev_dbg(pxp->dev, "PXP_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CTRL)); -+ dev_dbg(pxp->dev, "PXP_STAT 0x%x", -+ __raw_readl(pxp->base + HW_PXP_STAT)); -+ dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); -+ dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_BUF)); -+ dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); -+ dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); -+ dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_LRC)); -+ dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); -+ dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); -+ dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); -+ dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); -+ dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_CTRL)); -+ dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_BUF)); -+ dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_UBUF)); -+ dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_VBUF)); -+ dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_PITCH)); -+ dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND)); -+ dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_SCALE)); -+ dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); -+ dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW)); -+ dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH)); -+ dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_CTRL)); -+ dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_BUF)); -+ dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_PITCH)); -+ dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW)); -+ dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH)); -+ dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); -+ dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); -+ dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); -+ dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); -+ dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); -+ dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); -+ dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_DATA)); -+ dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); -+ dev_dbg(pxp->dev, "PXP_CFA 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CFA)); -+ dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); -+ dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); -+ dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); -+ dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); -+ dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); -+ dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); -+ dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); -+ dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); -+ dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", -+ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); -+ dev_dbg(pxp->dev, "PXP_POWER 0x%x", -+ __raw_readl(pxp->base + HW_PXP_POWER)); -+ dev_dbg(pxp->dev, "PXP_NEXT 0x%x", -+ __raw_readl(pxp->base + HW_PXP_NEXT)); -+ dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); -+ dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", -+ __raw_readl(pxp->base + HW_PXP_DEBUG)); -+ dev_dbg(pxp->dev, "PXP_VERSION 0x%x", -+ __raw_readl(pxp->base + HW_PXP_VERSION)); -+} -+ -+static bool is_yuv(u32 pix_fmt) -+{ -+ switch (pix_fmt) { -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_YVYU: -+ case PXP_PIX_FMT_VYUY: -+ case PXP_PIX_FMT_Y41P: -+ case PXP_PIX_FMT_VUY444: -+ case PXP_PIX_FMT_NV12: -+ case PXP_PIX_FMT_NV21: -+ case PXP_PIX_FMT_NV16: -+ case PXP_PIX_FMT_NV61: -+ case PXP_PIX_FMT_GREY: -+ case PXP_PIX_FMT_GY04: -+ case PXP_PIX_FMT_YVU410P: -+ case PXP_PIX_FMT_YUV410P: -+ case PXP_PIX_FMT_YVU420P: -+ case PXP_PIX_FMT_YUV420P: -+ case PXP_PIX_FMT_YUV420P2: -+ case PXP_PIX_FMT_YVU422P: -+ case PXP_PIX_FMT_YUV422P: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static void pxp_soft_reset(struct pxps *pxp) -+{ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); -+ __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); -+ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); -+ while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) -+ dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); -+ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); -+ __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); -+} -+ -+static void pxp_set_ctrl(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ u32 ctrl; -+ u32 fmt_ctrl; -+ int need_swap = 0; /* to support YUYV and YVYU formats */ -+ -+ /* Configure S0 input format */ -+ switch (pxp_conf->s0_param.pixel_fmt) { -+ case PXP_PIX_FMT_XRGB32: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; -+ break; -+ case PXP_PIX_FMT_RGB565: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; -+ break; -+ case PXP_PIX_FMT_RGB555: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; -+ break; -+ case PXP_PIX_FMT_YUV420P: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; -+ break; -+ case PXP_PIX_FMT_YVU420P: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; -+ break; -+ case PXP_PIX_FMT_GREY: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; -+ break; -+ case PXP_PIX_FMT_GY04: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; -+ break; -+ case PXP_PIX_FMT_VUY444: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; -+ break; -+ case PXP_PIX_FMT_YUV422P: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; -+ break; -+ case PXP_PIX_FMT_UYVY: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; -+ break; -+ case PXP_PIX_FMT_YUYV: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; -+ need_swap = 1; -+ break; -+ case PXP_PIX_FMT_VYUY: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; -+ break; -+ case PXP_PIX_FMT_YVYU: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; -+ need_swap = 1; -+ break; -+ case PXP_PIX_FMT_NV12: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; -+ break; -+ case PXP_PIX_FMT_NV21: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; -+ break; -+ case PXP_PIX_FMT_NV16: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; -+ break; -+ case PXP_PIX_FMT_NV61: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; -+ break; -+ default: -+ fmt_ctrl = 0; -+ } -+ -+ ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); -+ __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET); -+ -+ /* Configure output format based on out_channel format */ -+ switch (pxp_conf->out_param.pixel_fmt) { -+ case PXP_PIX_FMT_XRGB32: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; -+ break; -+ case PXP_PIX_FMT_BGRA32: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; -+ break; -+ case PXP_PIX_FMT_RGB24: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; -+ break; -+ case PXP_PIX_FMT_RGB565: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; -+ break; -+ case PXP_PIX_FMT_RGB555: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; -+ break; -+ case PXP_PIX_FMT_GREY: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; -+ break; -+ case PXP_PIX_FMT_GY04: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; -+ break; -+ case PXP_PIX_FMT_UYVY: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; -+ break; -+ case PXP_PIX_FMT_VYUY: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; -+ break; -+ case PXP_PIX_FMT_NV12: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; -+ break; -+ case PXP_PIX_FMT_NV21: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; -+ break; -+ case PXP_PIX_FMT_NV16: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; -+ break; -+ case PXP_PIX_FMT_NV61: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; -+ break; -+ default: -+ fmt_ctrl = 0; -+ } -+ -+ ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); -+ __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL); -+ -+ ctrl = 0; -+ if (proc_data->scaling) -+ ; -+ if (proc_data->vflip) -+ ctrl |= BM_PXP_CTRL_VFLIP; -+ if (proc_data->hflip) -+ ctrl |= BM_PXP_CTRL_HFLIP; -+ if (proc_data->rotate) -+ ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); -+ -+ /* In default, the block size is set to 8x8 -+ * But block size can be set to 16x16 due to -+ * blocksize variable modification -+ */ -+ ctrl |= block_size << 23; -+ -+ __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); -+} -+ -+static int pxp_start(struct pxps *pxp) -+{ -+ __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); -+ __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); -+ dump_pxp_reg(pxp); -+ -+ return 0; -+} -+ -+static void pxp_set_outbuf(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *out_params = &pxp_conf->out_param; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ -+ __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF); -+ -+ if ((out_params->pixel_fmt == PXP_PIX_FMT_NV12) || -+ (out_params->pixel_fmt == PXP_PIX_FMT_NV21) || -+ (out_params->pixel_fmt == PXP_PIX_FMT_NV16) || -+ (out_params->pixel_fmt == PXP_PIX_FMT_NV61)) { -+ dma_addr_t Y, U; -+ -+ Y = out_params->paddr; -+ U = Y + (out_params->width * out_params->height); -+ -+ __raw_writel(U, pxp->base + HW_PXP_OUT_BUF2); -+ } -+ -+ if (proc_data->rotate == 90 || proc_data->rotate == 270) -+ __raw_writel(BF_PXP_OUT_LRC_X(out_params->height - 1) | -+ BF_PXP_OUT_LRC_Y(out_params->width - 1), -+ pxp->base + HW_PXP_OUT_LRC); -+ else -+ __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) | -+ BF_PXP_OUT_LRC_Y(out_params->height - 1), -+ pxp->base + HW_PXP_OUT_LRC); -+ -+ if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) { -+ __raw_writel(out_params->stride * 3, -+ pxp->base + HW_PXP_OUT_PITCH); -+ } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 || -+ out_params->pixel_fmt == PXP_PIX_FMT_XRGB32) { -+ __raw_writel(out_params->stride << 2, -+ pxp->base + HW_PXP_OUT_PITCH); -+ } else if ((out_params->pixel_fmt == PXP_PIX_FMT_RGB565) || -+ (out_params->pixel_fmt == PXP_PIX_FMT_RGB555)) { -+ __raw_writel(out_params->stride << 1, -+ pxp->base + HW_PXP_OUT_PITCH); -+ } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY || -+ (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) { -+ __raw_writel(out_params->stride << 1, -+ pxp->base + HW_PXP_OUT_PITCH); -+ } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY || -+ out_params->pixel_fmt == PXP_PIX_FMT_NV12 || -+ out_params->pixel_fmt == PXP_PIX_FMT_NV21 || -+ out_params->pixel_fmt == PXP_PIX_FMT_NV16 || -+ out_params->pixel_fmt == PXP_PIX_FMT_NV61) { -+ __raw_writel(out_params->stride, -+ pxp->base + HW_PXP_OUT_PITCH); -+ } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) { -+ __raw_writel(out_params->stride >> 1, -+ pxp->base + HW_PXP_OUT_PITCH); -+ } else { -+ __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH); -+ } -+ -+ /* set global alpha if necessary */ -+ if (out_params->global_alpha_enable) { -+ __raw_writel(out_params->global_alpha << 24, -+ pxp->base + HW_PXP_OUT_CTRL_SET); -+ __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, -+ pxp->base + HW_PXP_OUT_CTRL_SET); -+ } -+} -+ -+static void pxp_set_s0colorkey(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *s0_params = &pxp_conf->s0_param; -+ -+ /* Low and high are set equal. V4L does not allow a chromakey range */ -+ if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { -+ /* disable color key */ -+ __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW); -+ __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH); -+ } else { -+ __raw_writel(s0_params->color_key, -+ pxp->base + HW_PXP_PS_CLRKEYLOW); -+ __raw_writel(s0_params->color_key, -+ pxp->base + HW_PXP_PS_CLRKEYHIGH); -+ } -+} -+ -+static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; -+ -+ /* Low and high are set equal. V4L does not allow a chromakey range */ -+ if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { -+ __raw_writel(ol_params->color_key, -+ pxp->base + HW_PXP_AS_CLRKEYLOW); -+ __raw_writel(ol_params->color_key, -+ pxp->base + HW_PXP_AS_CLRKEYHIGH); -+ } else { -+ /* disable color key */ -+ __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW); -+ __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH); -+ } -+} -+ -+static void pxp_set_oln(int layer_no, struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; -+ dma_addr_t phys_addr = olparams_data->paddr; -+ u32 pitch = olparams_data->stride ? olparams_data->stride : -+ olparams_data->width; -+ -+ __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF); -+ -+ /* Fixme */ -+ if (olparams_data->width == 0 && olparams_data->height == 0) { -+ __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); -+ __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); -+ } else { -+ __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC); -+ __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) | -+ BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1), -+ pxp->base + HW_PXP_OUT_AS_LRC); -+ } -+ -+ if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) || -+ (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32)) { -+ __raw_writel(pitch << 2, -+ pxp->base + HW_PXP_AS_PITCH); -+ } else if ((olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) || -+ (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555)) { -+ __raw_writel(pitch << 1, -+ pxp->base + HW_PXP_AS_PITCH); -+ } else { -+ __raw_writel(0, pxp->base + HW_PXP_AS_PITCH); -+ } -+} -+ -+static void pxp_set_olparam(int layer_no, struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; -+ u32 olparam; -+ -+ olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha); -+ if (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32) { -+ olparam |= -+ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888); -+ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) { -+ olparam |= -+ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888); -+ if (!olparams_data->combine_enable) { -+ olparam |= -+ BF_PXP_AS_CTRL_ALPHA_CTRL -+ (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); -+ olparam |= 0x3 << 16; -+ } -+ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) { -+ olparam |= -+ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565); -+ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555) { -+ olparam |= -+ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB555); -+ } -+ -+ if (olparams_data->global_alpha_enable) { -+ if (olparams_data->global_override) { -+ olparam |= -+ BF_PXP_AS_CTRL_ALPHA_CTRL -+ (BV_PXP_AS_CTRL_ALPHA_CTRL__Override); -+ } else { -+ olparam |= -+ BF_PXP_AS_CTRL_ALPHA_CTRL -+ (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply); -+ } -+ if (olparams_data->alpha_invert) -+ olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT; -+ } -+ if (olparams_data->color_key_enable) -+ olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY; -+ -+ __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL); -+} -+ -+static void pxp_set_s0param(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ struct pxp_layer_param *out_params = &pxp_conf->out_param; -+ u32 s0param_ulc, s0param_lrc; -+ -+ /* contains the coordinate for the PS in the OUTPUT buffer. */ -+ if ((pxp_conf->s0_param).width == 0 && -+ (pxp_conf->s0_param).height == 0) { -+ __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC); -+ __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC); -+ } else { -+ switch (proc_data->rotate) { -+ case 0: -+ s0param_ulc = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left); -+ s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top); -+ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); -+ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); -+ break; -+ case 90: -+ s0param_ulc = BF_PXP_OUT_PS_ULC_Y(out_params->width - (proc_data->drect.left + proc_data->drect.width)); -+ s0param_ulc |= BF_PXP_OUT_PS_ULC_X(proc_data->drect.top); -+ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); -+ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); -+ break; -+ case 180: -+ s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->width - (proc_data->drect.left + proc_data->drect.width)); -+ s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(out_params->height - (proc_data->drect.top + proc_data->drect.height)); -+ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); -+ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); -+ break; -+ case 270: -+ s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->height - (proc_data->drect.top + proc_data->drect.height)); -+ s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.left); -+ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); -+ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); -+ break; -+ default: -+ return; -+ } -+ __raw_writel(s0param_ulc, pxp->base + HW_PXP_OUT_PS_ULC); -+ __raw_writel(s0param_lrc, pxp->base + HW_PXP_OUT_PS_LRC); -+ } -+ -+ /* Since user apps always pass the rotated drect -+ * to this driver, we need to first swap the width -+ * and height which is used to calculate the scale -+ * factors later. -+ */ -+ if (proc_data->rotate == 90 || proc_data->rotate == 270) { -+ int temp; -+ temp = proc_data->drect.width; -+ proc_data->drect.width = proc_data->drect.height; -+ proc_data->drect.height = temp; -+ } -+} -+ -+/* crop behavior is re-designed in h/w. */ -+static void pxp_set_s0crop(struct pxps *pxp) -+{ -+ /* -+ * place-holder, it's implemented in other functions in this driver. -+ * Refer to "Clipping source images" section in RM for detail. -+ */ -+} -+ -+static int pxp_set_scaling(struct pxps *pxp) -+{ -+ int ret = 0; -+ u32 xscale, yscale, s0scale; -+ u32 decx, decy, xdec = 0, ydec = 0; -+ struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *s0_params = &pxp_conf->s0_param; -+ struct pxp_layer_param *out_params = &pxp_conf->out_param; -+ -+ proc_data->scaling = 1; -+ -+ if (!proc_data->drect.width || !proc_data->drect.height) { -+ pr_err("Invalid drect width and height passed in\n"); -+ return -EINVAL; -+ } -+ -+ decx = proc_data->srect.width / proc_data->drect.width; -+ decy = proc_data->srect.height / proc_data->drect.height; -+ if (decx > 1) { -+ if (decx >= 2 && decx < 4) { -+ decx = 2; -+ xdec = 1; -+ } else if (decx >= 4 && decx < 8) { -+ decx = 4; -+ xdec = 2; -+ } else if (decx >= 8) { -+ decx = 8; -+ xdec = 3; -+ } -+ xscale = proc_data->srect.width * 0x1000 / -+ (proc_data->drect.width * decx); -+ } else { -+ if (!is_yuv(s0_params->pixel_fmt) || -+ (is_yuv(s0_params->pixel_fmt) == -+ is_yuv(out_params->pixel_fmt)) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)) { -+ if ((proc_data->srect.width > 1) && -+ (proc_data->drect.width > 1)) -+ xscale = (proc_data->srect.width - 1) * 0x1000 / -+ (proc_data->drect.width - 1); -+ else -+ xscale = proc_data->srect.width * 0x1000 / -+ proc_data->drect.width; -+ } else { -+ if ((proc_data->srect.width > 2) && -+ (proc_data->drect.width > 1)) -+ xscale = (proc_data->srect.width - 2) * 0x1000 / -+ (proc_data->drect.width - 1); -+ else -+ xscale = proc_data->srect.width * 0x1000 / -+ proc_data->drect.width; -+ } -+ } -+ if (decy > 1) { -+ if (decy >= 2 && decy < 4) { -+ decy = 2; -+ ydec = 1; -+ } else if (decy >= 4 && decy < 8) { -+ decy = 4; -+ ydec = 2; -+ } else if (decy >= 8) { -+ decy = 8; -+ ydec = 3; -+ } -+ yscale = proc_data->srect.height * 0x1000 / -+ (proc_data->drect.height * decy); -+ } else { -+ if ((proc_data->srect.height > 1) && -+ (proc_data->drect.height > 1)) -+ yscale = (proc_data->srect.height - 1) * 0x1000 / -+ (proc_data->drect.height - 1); -+ else -+ yscale = proc_data->srect.height * 0x1000 / -+ proc_data->drect.height; -+ } -+ -+ __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL); -+ -+ if (xscale > PXP_DOWNSCALE_THRESHOLD) -+ xscale = PXP_DOWNSCALE_THRESHOLD; -+ if (yscale > PXP_DOWNSCALE_THRESHOLD) -+ yscale = PXP_DOWNSCALE_THRESHOLD; -+ s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | -+ BF_PXP_PS_SCALE_XSCALE(xscale); -+ __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE); -+ -+ pxp_set_ctrl(pxp); -+ -+ return ret; -+} -+ -+static void pxp_set_bg(struct pxps *pxp) -+{ -+ __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, -+ pxp->base + HW_PXP_PS_BACKGROUND); -+} -+ -+static void pxp_set_lut(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ int lut_op = pxp_conf->proc_data.lut_transform; -+ u32 reg_val; -+ int i; -+ bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; -+ u8 *cmap = pxp_conf->proc_data.lut_map; -+ u32 entry_src; -+ u32 pix_val; -+ u8 entry[4]; -+ -+ /* -+ * If LUT already configured as needed, return... -+ * Unless CMAP is needed and it has been updated. -+ */ -+ if ((pxp->lut_state == lut_op) && -+ !(use_cmap && pxp_conf->proc_data.lut_map_updated)) -+ return; -+ -+ if (lut_op == PXP_LUT_NONE) { -+ __raw_writel(BM_PXP_LUT_CTRL_BYPASS, -+ pxp->base + HW_PXP_LUT_CTRL); -+ } else if (((lut_op & PXP_LUT_INVERT) != 0) -+ && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { -+ /* Fill out LUT table with inverted monochromized values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) { -+ entry_src = use_cmap ? -+ cmap[pix_val + i] : pix_val + i; -+ entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; -+ } -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } else if ((lut_op & PXP_LUT_INVERT) != 0) { -+ /* Fill out LUT table with 8-bit inverted values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) { -+ entry_src = use_cmap ? -+ cmap[pix_val + i] : pix_val + i; -+ entry[i] = ~entry_src & 0xFF; -+ } -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { -+ /* Fill out LUT table with 8-bit monochromized values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) { -+ entry_src = use_cmap ? -+ cmap[pix_val + i] : pix_val + i; -+ entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; -+ } -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } else if (use_cmap) { -+ /* Fill out LUT table using colormap values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) -+ entry[i] = cmap[pix_val + i]; -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } -+ -+ pxp->lut_state = lut_op; -+} -+ -+static void pxp_set_csc(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *s0_params = &pxp_conf->s0_param; -+ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; -+ struct pxp_layer_param *out_params = &pxp_conf->out_param; -+ -+ bool input_is_YUV = is_yuv(s0_params->pixel_fmt); -+ bool output_is_YUV = is_yuv(out_params->pixel_fmt); -+ -+ if (input_is_YUV && output_is_YUV) { -+ /* -+ * Input = YUV, Output = YUV -+ * No CSC unless we need to do combining -+ */ -+ if (ol_params->combine_enable) { -+ /* Must convert to RGB for combining with RGB overlay */ -+ -+ /* CSC1 - YUV->RGB */ -+ __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0); -+ __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1); -+ __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2); -+ -+ /* CSC2 - RGB->YUV */ -+ __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); -+ __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); -+ __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); -+ __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); -+ __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); -+ __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); -+ } else { -+ /* Input & Output both YUV, so bypass both CSCs */ -+ -+ /* CSC1 - Bypass */ -+ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); -+ -+ /* CSC2 - Bypass */ -+ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); -+ } -+ } else if (input_is_YUV && !output_is_YUV) { -+ /* -+ * Input = YUV, Output = RGB -+ * Use CSC1 to convert to RGB -+ */ -+ -+ /* CSC1 - YUV->RGB */ -+ __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0); -+ __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1); -+ __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2); -+ -+ /* CSC2 - Bypass */ -+ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); -+ } else if (!input_is_YUV && output_is_YUV) { -+ /* -+ * Input = RGB, Output = YUV -+ * Use CSC2 to convert to YUV -+ */ -+ -+ /* CSC1 - Bypass */ -+ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); -+ -+ /* CSC2 - RGB->YUV */ -+ __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); -+ __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); -+ __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); -+ __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); -+ __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); -+ __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); -+ } else { -+ /* -+ * Input = RGB, Output = RGB -+ * Input & Output both RGB, so bypass both CSCs -+ */ -+ -+ /* CSC1 - Bypass */ -+ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); -+ -+ /* CSC2 - Bypass */ -+ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); -+ } -+ -+ /* YCrCb colorspace */ -+ /* Not sure when we use this...no YCrCb formats are defined for PxP */ -+ /* -+ __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); -+ __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); -+ __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); -+ */ -+ -+} -+ -+static void pxp_set_s0buf(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *s0_params = &pxp_conf->s0_param; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ dma_addr_t Y, U, V; -+ dma_addr_t Y1, U1, V1; -+ u32 offset, bpp = 1; -+ u32 pitch = s0_params->stride ? s0_params->stride : -+ s0_params->width; -+ -+ Y = s0_params->paddr; -+ -+ if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) -+ bpp = 2; -+ else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32) -+ bpp = 4; -+ offset = (proc_data->srect.top * s0_params->width + -+ proc_data->srect.left) * bpp; -+ /* clipping or cropping */ -+ Y1 = Y + offset; -+ __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF); -+ if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) { -+ /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ -+ int s = 2; -+ if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) -+ s = 1; -+ -+ offset = proc_data->srect.top * s0_params->width / 4 + -+ proc_data->srect.left / 2; -+ U = Y + (s0_params->width * s0_params->height); -+ U1 = U + offset; -+ V = U + ((s0_params->width * s0_params->height) >> s); -+ V1 = V + offset; -+ if (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) { -+ __raw_writel(V1, pxp->base + HW_PXP_PS_UBUF); -+ __raw_writel(U1, pxp->base + HW_PXP_PS_VBUF); -+ } else { -+ __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); -+ __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF); -+ } -+ } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) { -+ int s = 2; -+ if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) -+ s = 1; -+ -+ offset = (proc_data->srect.top * s0_params->width + -+ proc_data->srect.left) / s; -+ U = Y + (s0_params->width * s0_params->height); -+ U1 = U + offset; -+ -+ __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); -+ } -+ -+ /* TODO: only support RGB565, Y8, Y4, YUV420 */ -+ if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY || -+ s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P || -+ s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P || -+ s0_params->pixel_fmt == PXP_PIX_FMT_NV12 || -+ s0_params->pixel_fmt == PXP_PIX_FMT_NV21 || -+ s0_params->pixel_fmt == PXP_PIX_FMT_NV16 || -+ s0_params->pixel_fmt == PXP_PIX_FMT_NV61 || -+ s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) { -+ __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH); -+ } -+ else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) -+ __raw_writel(pitch >> 1, -+ pxp->base + HW_PXP_PS_PITCH); -+ else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32 || -+ s0_params->pixel_fmt == PXP_PIX_FMT_VUY444) -+ __raw_writel(pitch << 2, -+ pxp->base + HW_PXP_PS_PITCH); -+ else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY || -+ s0_params->pixel_fmt == PXP_PIX_FMT_YUYV || -+ s0_params->pixel_fmt == PXP_PIX_FMT_VYUY || -+ s0_params->pixel_fmt == PXP_PIX_FMT_YVYU) -+ __raw_writel(pitch << 1, -+ pxp->base + HW_PXP_PS_PITCH); -+ else if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || -+ (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) -+ __raw_writel(pitch << 1, -+ pxp->base + HW_PXP_PS_PITCH); -+ else -+ __raw_writel(0, pxp->base + HW_PXP_PS_PITCH); -+} -+ -+/** -+ * pxp_config() - configure PxP for a processing task -+ * @pxps: PXP context. -+ * @pxp_chan: PXP channel. -+ * @return: 0 on success or negative error code on failure. -+ */ -+static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) -+{ -+ /* Configure PxP regs */ -+ pxp_set_ctrl(pxp); -+ pxp_set_s0param(pxp); -+ pxp_set_s0crop(pxp); -+ pxp_set_scaling(pxp); -+ pxp_set_s0colorkey(pxp); -+ -+ pxp_set_oln(0, pxp); -+ pxp_set_olparam(0, pxp); -+ pxp_set_olcolorkey(0, pxp); -+ -+ pxp_set_csc(pxp); -+ pxp_set_bg(pxp); -+ pxp_set_lut(pxp); -+ -+ pxp_set_s0buf(pxp); -+ pxp_set_outbuf(pxp); -+ -+ return 0; -+} -+ -+static void pxp_clk_enable(struct pxps *pxp) -+{ -+ mutex_lock(&pxp->clk_mutex); -+ -+ if (pxp->clk_stat == CLK_STAT_ON) { -+ mutex_unlock(&pxp->clk_mutex); -+ return; -+ } -+ -+ pm_runtime_get_sync(pxp->dev); -+ -+ if (pxp->clk_disp_axi) -+ clk_prepare_enable(pxp->clk_disp_axi); -+ clk_prepare_enable(pxp->clk); -+ pxp->clk_stat = CLK_STAT_ON; -+ -+ mutex_unlock(&pxp->clk_mutex); -+} -+ -+static void pxp_clk_disable(struct pxps *pxp) -+{ -+ unsigned long flags; -+ -+ mutex_lock(&pxp->clk_mutex); -+ -+ if (pxp->clk_stat == CLK_STAT_OFF) { -+ mutex_unlock(&pxp->clk_mutex); -+ return; -+ } -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ clk_disable_unprepare(pxp->clk); -+ if (pxp->clk_disp_axi) -+ clk_disable_unprepare(pxp->clk_disp_axi); -+ pxp->clk_stat = CLK_STAT_OFF; -+ pm_runtime_put_sync_suspend(pxp->dev); -+ } else -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ mutex_unlock(&pxp->clk_mutex); -+} -+ -+static inline void clkoff_callback(struct work_struct *w) -+{ -+ struct pxps *pxp = container_of(w, struct pxps, work); -+ -+ pxp_clk_disable(pxp); -+} -+ -+static void pxp_clkoff_timer(struct timer_list *t) -+{ -+ struct pxps *pxp = from_timer(pxp, t, clk_timer); -+ -+ if ((pxp->pxp_ongoing == 0) && list_empty(&head)) -+ schedule_work(&pxp->work); -+ else -+ mod_timer(&pxp->clk_timer, -+ jiffies + msecs_to_jiffies(timeout_in_ms)); -+} -+ -+static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) -+{ -+ return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); -+} -+ -+/* called with pxp_chan->lock held */ -+static void __pxpdma_dostart(struct pxp_channel *pxp_chan) -+{ -+ struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); -+ struct pxps *pxp = to_pxp(pxp_dma); -+ struct pxp_tx_desc *desc; -+ struct pxp_tx_desc *child; -+ int i = 0; -+ -+ memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); -+ memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); -+ memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); -+ memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); -+ /* S0 */ -+ desc = list_first_entry(&head, struct pxp_tx_desc, list); -+ memcpy(&pxp->pxp_conf_state.s0_param, -+ &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); -+ memcpy(&pxp->pxp_conf_state.proc_data, -+ &desc->proc_data, sizeof(struct pxp_proc_data)); -+ -+ /* Save PxP configuration */ -+ list_for_each_entry(child, &desc->tx_list, list) { -+ if (i == 0) { /* Output */ -+ memcpy(&pxp->pxp_conf_state.out_param, -+ &child->layer_param.out_param, -+ sizeof(struct pxp_layer_param)); -+ } else { /* Overlay */ -+ memcpy(&pxp->pxp_conf_state.ol_param[i - 1], -+ &child->layer_param.ol_param, -+ sizeof(struct pxp_layer_param)); -+ } -+ -+ i++; -+ } -+ pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, -+ pxp->pxp_conf_state.s0_param.width, -+ pxp->pxp_conf_state.s0_param.height, -+ pxp->pxp_conf_state.s0_param.paddr); -+ pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, -+ pxp->pxp_conf_state.out_param.width, -+ pxp->pxp_conf_state.out_param.height, -+ pxp->pxp_conf_state.out_param.paddr); -+} -+ -+static void pxpdma_dostart_work(struct pxps *pxp) -+{ -+ struct pxp_channel *pxp_chan = NULL; -+ unsigned long flags; -+ struct pxp_tx_desc *desc = NULL; -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ -+ desc = list_entry(head.next, struct pxp_tx_desc, list); -+ pxp_chan = to_pxp_channel(desc->txd.chan); -+ -+ __pxpdma_dostart(pxp_chan); -+ -+ /* Configure PxP */ -+ pxp_config(pxp, pxp_chan); -+ -+ pxp_start(pxp); -+ -+ spin_unlock_irqrestore(&pxp->lock, flags); -+} -+ -+static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) -+{ -+ unsigned long flags; -+ struct pxp_tx_desc *desc = NULL; -+ -+ do { -+ desc = pxpdma_first_queued(pxp_chan); -+ spin_lock_irqsave(&pxp->lock, flags); -+ list_move_tail(&desc->list, &head); -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ } while (!list_empty(&pxp_chan->queue)); -+} -+ -+static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) -+{ -+ struct pxp_tx_desc *desc = to_tx_desc(tx); -+ struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); -+ dma_cookie_t cookie; -+ -+ dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); -+ -+ /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ -+ spin_lock(&pxp_chan->lock); -+ -+ cookie = pxp_chan->dma_chan.cookie; -+ -+ if (++cookie < 0) -+ cookie = 1; -+ -+ /* from dmaengine.h: "last cookie value returned to client" */ -+ pxp_chan->dma_chan.cookie = cookie; -+ tx->cookie = cookie; -+ -+ /* Here we add the tx descriptor to our PxP task queue. */ -+ list_add_tail(&desc->list, &pxp_chan->queue); -+ -+ spin_unlock(&pxp_chan->lock); -+ -+ dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); -+ -+ return cookie; -+} -+ -+/** -+ * pxp_init_channel() - initialize a PXP channel. -+ * @pxp_dma: PXP DMA context. -+ * @pchan: pointer to the channel object. -+ * @return 0 on success or negative error code on failure. -+ */ -+static int pxp_init_channel(struct pxp_dma *pxp_dma, -+ struct pxp_channel *pxp_chan) -+{ -+ int ret = 0; -+ -+ /* -+ * We are using _virtual_ channel here. -+ * Each channel contains all parameters of corresponding layers -+ * for one transaction; each layer is represented as one descriptor -+ * (i.e., pxp_tx_desc) here. -+ */ -+ -+ INIT_LIST_HEAD(&pxp_chan->queue); -+ -+ return ret; -+} -+ -+static irqreturn_t pxp_irq(int irq, void *dev_id) -+{ -+ struct pxps *pxp = dev_id; -+ struct pxp_channel *pxp_chan; -+ struct pxp_tx_desc *desc; -+ struct pxp_tx_desc *child, *_child; -+ dma_async_tx_callback callback; -+ void *callback_param; -+ unsigned long flags; -+ u32 hist_status; -+ -+ dump_pxp_reg(pxp); -+ -+ hist_status = -+ __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; -+ -+ __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); -+ -+ /* set the SFTRST bit to be 1 to reset -+ * the PXP block to its default state. -+ */ -+ pxp_soft_reset(pxp); -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ -+ if (list_empty(&head)) { -+ pxp->pxp_ongoing = 0; -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ return IRQ_NONE; -+ } -+ -+ /* Get descriptor and call callback */ -+ desc = list_entry(head.next, struct pxp_tx_desc, list); -+ pxp_chan = to_pxp_channel(desc->txd.chan); -+ -+ pxp_chan->completed = desc->txd.cookie; -+ -+ callback = desc->txd.callback; -+ callback_param = desc->txd.callback_param; -+ -+ /* Send histogram status back to caller */ -+ desc->hist_status = hist_status; -+ -+ if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) -+ callback(callback_param); -+ -+ pxp_chan->status = PXP_CHANNEL_INITIALIZED; -+ -+ list_for_each_entry_safe(child, _child, &desc->tx_list, list) { -+ list_del_init(&child->list); -+ kmem_cache_free(tx_desc_cache, (void *)child); -+ } -+ list_del_init(&desc->list); -+ kmem_cache_free(tx_desc_cache, (void *)desc); -+ -+ complete(&pxp->complete); -+ pxp->pxp_ongoing = 0; -+ mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); -+ -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ return IRQ_HANDLED; -+} -+ -+/* allocate/free dma tx descriptor dynamically*/ -+static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) -+{ -+ struct pxp_tx_desc *desc = NULL; -+ struct dma_async_tx_descriptor *txd = NULL; -+ -+ desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); -+ if (desc == NULL) -+ return NULL; -+ -+ INIT_LIST_HEAD(&desc->list); -+ INIT_LIST_HEAD(&desc->tx_list); -+ txd = &desc->txd; -+ dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); -+ txd->tx_submit = pxp_tx_submit; -+ -+ return desc; -+} -+ -+/* Allocate and initialise a transfer descriptor. */ -+static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, -+ struct scatterlist -+ *sgl, -+ unsigned int sg_len, -+ enum -+ dma_transfer_direction -+ direction, -+ unsigned long tx_flags, -+ void *context) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); -+ struct pxps *pxp = to_pxp(pxp_dma); -+ struct pxp_tx_desc *pos = NULL, *next = NULL; -+ struct pxp_tx_desc *desc = NULL; -+ struct pxp_tx_desc *first = NULL, *prev = NULL; -+ struct scatterlist *sg; -+ dma_addr_t phys_addr; -+ int i; -+ -+ if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { -+ dev_err(chan->device->dev, "Invalid DMA direction %d!\n", -+ direction); -+ return NULL; -+ } -+ -+ if (unlikely(sg_len < 2)) -+ return NULL; -+ -+ for_each_sg(sgl, sg, sg_len, i) { -+ desc = pxpdma_desc_alloc(pxp_chan); -+ if (!desc) { -+ dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); -+ -+ if (first) { -+ list_for_each_entry_safe(pos, next, &first->tx_list, list) { -+ list_del_init(&pos->list); -+ kmem_cache_free(tx_desc_cache, (void*)pos); -+ } -+ list_del_init(&first->list); -+ kmem_cache_free(tx_desc_cache, (void*)first); -+ } -+ -+ return NULL; -+ } -+ -+ phys_addr = sg_dma_address(sg); -+ -+ if (!first) { -+ first = desc; -+ -+ desc->layer_param.s0_param.paddr = phys_addr; -+ } else { -+ list_add_tail(&desc->list, &first->tx_list); -+ prev->next = desc; -+ desc->next = NULL; -+ -+ if (i == 1) -+ desc->layer_param.out_param.paddr = phys_addr; -+ else -+ desc->layer_param.ol_param.paddr = phys_addr; -+ } -+ -+ prev = desc; -+ } -+ -+ pxp->pxp_conf_state.layer_nr = sg_len; -+ first->txd.flags = tx_flags; -+ first->len = sg_len; -+ pr_debug("%s:%d first %p, first->len %d, flags %08x\n", -+ __func__, __LINE__, first, first->len, first->txd.flags); -+ -+ return &first->txd; -+} -+ -+static void pxp_issue_pending(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); -+ struct pxps *pxp = to_pxp(pxp_dma); -+ -+ spin_lock(&pxp_chan->lock); -+ -+ if (list_empty(&pxp_chan->queue)) { -+ spin_unlock(&pxp_chan->lock); -+ return; -+ } -+ -+ pxpdma_dequeue(pxp_chan, pxp); -+ pxp_chan->status = PXP_CHANNEL_READY; -+ -+ spin_unlock(&pxp_chan->lock); -+ -+ pxp_clk_enable(pxp); -+ wake_up_interruptible(&pxp->thread_waitq); -+} -+ -+static void __pxp_terminate_all(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ pxp_chan->status = PXP_CHANNEL_INITIALIZED; -+} -+ -+static int pxp_device_terminate_all(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ spin_lock(&pxp_chan->lock); -+ __pxp_terminate_all(chan); -+ spin_unlock(&pxp_chan->lock); -+ -+ return 0; -+} -+ -+static int pxp_alloc_chan_resources(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); -+ int ret; -+ -+ /* dmaengine.c now guarantees to only offer free channels */ -+ BUG_ON(chan->client_count > 1); -+ WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); -+ -+ chan->cookie = 1; -+ pxp_chan->completed = -ENXIO; -+ -+ pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); -+ ret = pxp_init_channel(pxp_dma, pxp_chan); -+ if (ret < 0) -+ goto err_chan; -+ -+ pxp_chan->status = PXP_CHANNEL_INITIALIZED; -+ -+ dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", -+ chan->chan_id, pxp_chan->eof_irq); -+ -+ return ret; -+ -+err_chan: -+ return ret; -+} -+ -+static void pxp_free_chan_resources(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ spin_lock(&pxp_chan->lock); -+ -+ __pxp_terminate_all(chan); -+ -+ pxp_chan->status = PXP_CHANNEL_FREE; -+ -+ spin_unlock(&pxp_chan->lock); -+} -+ -+static enum dma_status pxp_tx_status(struct dma_chan *chan, -+ dma_cookie_t cookie, -+ struct dma_tx_state *txstate) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ if (cookie != chan->cookie) -+ return DMA_ERROR; -+ -+ if (txstate) { -+ txstate->last = pxp_chan->completed; -+ txstate->used = chan->cookie; -+ txstate->residue = 0; -+ } -+ return DMA_COMPLETE; -+} -+ -+static int pxp_dma_init(struct pxps *pxp) -+{ -+ struct pxp_dma *pxp_dma = &pxp->pxp_dma; -+ struct dma_device *dma = &pxp_dma->dma; -+ int i; -+ -+ dma_cap_set(DMA_SLAVE, dma->cap_mask); -+ dma_cap_set(DMA_PRIVATE, dma->cap_mask); -+ -+ /* Compulsory common fields */ -+ dma->dev = pxp->dev; -+ dma->device_alloc_chan_resources = pxp_alloc_chan_resources; -+ dma->device_free_chan_resources = pxp_free_chan_resources; -+ dma->device_tx_status = pxp_tx_status; -+ dma->device_issue_pending = pxp_issue_pending; -+ -+ /* Compulsory for DMA_SLAVE fields */ -+ dma->device_prep_slave_sg = pxp_prep_slave_sg; -+ dma->device_terminate_all = pxp_device_terminate_all; -+ -+ /* Initialize PxP Channels */ -+ INIT_LIST_HEAD(&dma->channels); -+ for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { -+ struct pxp_channel *pxp_chan = pxp->channel + i; -+ struct dma_chan *dma_chan = &pxp_chan->dma_chan; -+ -+ spin_lock_init(&pxp_chan->lock); -+ -+ /* Only one EOF IRQ for PxP, shared by all channels */ -+ pxp_chan->eof_irq = pxp->irq; -+ pxp_chan->status = PXP_CHANNEL_FREE; -+ pxp_chan->completed = -ENXIO; -+ snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), -+ "PXP EOF %d", i); -+ -+ dma_chan->device = &pxp_dma->dma; -+ dma_chan->cookie = 1; -+ dma_chan->chan_id = i; -+ list_add_tail(&dma_chan->device_node, &dma->channels); -+ } -+ -+ return dma_async_device_register(&pxp_dma->dma); -+} -+ -+static ssize_t clk_off_timeout_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", timeout_in_ms); -+} -+ -+static ssize_t clk_off_timeout_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ int val; -+ if (sscanf(buf, "%d", &val) > 0) { -+ timeout_in_ms = val; -+ return count; -+ } -+ return -EINVAL; -+} -+ -+static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, -+ clk_off_timeout_store); -+ -+static ssize_t block_size_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ return sprintf(buf, "%d\n", block_size); -+} -+ -+static ssize_t block_size_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ char **last = NULL; -+ -+ block_size = simple_strtoul(buf, last, 0); -+ if (block_size > 1) -+ block_size = 1; -+ -+ return count; -+} -+static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, -+ block_size_show, block_size_store); -+ -+static const struct of_device_id imx_pxpdma_dt_ids[] = { -+ { .compatible = "fsl,imx6dl-pxp-dma", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); -+ -+static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) -+{ -+ int found; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ found = !list_empty(&head); -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ return found; -+} -+ -+static int pxp_dispatch_thread(void *argv) -+{ -+ struct pxps *pxp = (struct pxps *)argv; -+ struct pxp_channel *pending = NULL; -+ unsigned long flags; -+ -+ set_freezable(); -+ -+ while (!kthread_should_stop()) { -+ int ret; -+ ret = wait_event_freezable(pxp->thread_waitq, -+ has_pending_task(pxp, pending) || -+ kthread_should_stop()); -+ if (ret < 0) -+ continue; -+ -+ if (kthread_should_stop()) -+ break; -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ pxp->pxp_ongoing = 1; -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ init_completion(&pxp->complete); -+ pxpdma_dostart_work(pxp); -+ ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); -+ if (ret == 0) { -+ printk(KERN_EMERG "%s: task is timeout\n\n", __func__); -+ break; -+ } -+ } -+ -+ return 0; -+} -+ -+static int pxp_probe(struct platform_device *pdev) -+{ -+ struct pxps *pxp; -+ struct resource *res; -+ int irq; -+ int err = 0; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ irq = platform_get_irq(pdev, 0); -+ if (!res || irq < 0) { -+ err = -ENODEV; -+ goto exit; -+ } -+ -+ pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); -+ if (!pxp) { -+ dev_err(&pdev->dev, "failed to allocate control object\n"); -+ err = -ENOMEM; -+ goto exit; -+ } -+ -+ pxp->dev = &pdev->dev; -+ -+ platform_set_drvdata(pdev, pxp); -+ pxp->irq = irq; -+ -+ spin_lock_init(&pxp->lock); -+ mutex_init(&pxp->clk_mutex); -+ -+ pxp->base = devm_ioremap_resource(&pdev->dev, res); -+ if (pxp->base == NULL) { -+ dev_err(&pdev->dev, "Couldn't ioremap regs\n"); -+ err = -ENODEV; -+ goto exit; -+ } -+ -+ pxp->pdev = pdev; -+ -+ pxp->clk_disp_axi = devm_clk_get(&pdev->dev, "disp-axi"); -+ if (IS_ERR(pxp->clk_disp_axi)) -+ pxp->clk_disp_axi = NULL; -+ pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi"); -+ -+ err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0, -+ "pxp-dmaengine", pxp); -+ if (err) -+ goto exit; -+ /* Initialize DMA engine */ -+ err = pxp_dma_init(pxp); -+ if (err < 0) -+ goto exit; -+ -+ if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) { -+ dev_err(&pdev->dev, -+ "Unable to create file from clk_off_timeout\n"); -+ goto exit; -+ } -+ -+ device_create_file(&pdev->dev, &dev_attr_block_size); -+ pxp_clk_enable(pxp); -+ dump_pxp_reg(pxp); -+ pxp_clk_disable(pxp); -+ -+ INIT_WORK(&pxp->work, clkoff_callback); -+ timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); -+ -+ init_waitqueue_head(&pxp->thread_waitq); -+ /* allocate a kernel thread to dispatch pxp conf */ -+ pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); -+ if (IS_ERR(pxp->dispatch)) { -+ err = PTR_ERR(pxp->dispatch); -+ goto exit; -+ } -+ tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), -+ 0, SLAB_HWCACHE_ALIGN, NULL); -+ if (!tx_desc_cache) { -+ err = -ENOMEM; -+ goto exit; -+ } -+ -+ register_pxp_device(); -+ -+ pm_runtime_enable(pxp->dev); -+ -+exit: -+ if (err) -+ dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); -+ return err; -+} -+ -+static int pxp_remove(struct platform_device *pdev) -+{ -+ struct pxps *pxp = platform_get_drvdata(pdev); -+ -+ unregister_pxp_device(); -+ kmem_cache_destroy(tx_desc_cache); -+ kthread_stop(pxp->dispatch); -+ cancel_work_sync(&pxp->work); -+ del_timer_sync(&pxp->clk_timer); -+ clk_disable_unprepare(pxp->clk); -+ if (pxp->clk_disp_axi) -+ clk_disable_unprepare(pxp->clk_disp_axi); -+ device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); -+ device_remove_file(&pdev->dev, &dev_attr_block_size); -+ dma_async_device_unregister(&(pxp->pxp_dma.dma)); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+static int pxp_suspend(struct device *dev) -+{ -+ struct pxps *pxp = dev_get_drvdata(dev); -+ -+ pxp_clk_enable(pxp); -+ while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) -+ ; -+ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); -+ pxp_clk_disable(pxp); -+ -+ return 0; -+} -+ -+static int pxp_resume(struct device *dev) -+{ -+ struct pxps *pxp = dev_get_drvdata(dev); -+ -+ pxp_clk_enable(pxp); -+ /* Pull PxP out of reset */ -+ __raw_writel(0, pxp->base + HW_PXP_CTRL); -+ pxp_clk_disable(pxp); -+ -+ return 0; -+} -+#else -+#define pxp_suspend NULL -+#define pxp_resume NULL -+#endif -+ -+#ifdef CONFIG_PM -+static int pxp_runtime_suspend(struct device *dev) -+{ -+ dev_dbg(dev, "pxp busfreq high release.\n"); -+ return 0; -+} -+ -+static int pxp_runtime_resume(struct device *dev) -+{ -+ dev_dbg(dev, "pxp busfreq high request.\n"); -+ return 0; -+} -+#else -+#define pxp_runtime_suspend NULL -+#define pxp_runtime_resume NULL -+#endif -+ -+static const struct dev_pm_ops pxp_pm_ops = { -+ SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) -+}; -+ -+static struct platform_driver pxp_driver = { -+ .driver = { -+ .name = "imx-pxp", -+ .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), -+ .pm = &pxp_pm_ops, -+ }, -+ .probe = pxp_probe, -+ .remove = pxp_remove, -+}; -+ -+module_platform_driver(pxp_driver); -+ -+ -+MODULE_DESCRIPTION("i.MX PxP driver"); -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c -new file mode 100644 -index 000000000..9b6b02ab2 ---- /dev/null -+++ b/drivers/dma/pxp/pxp_dma_v3.c -@@ -0,0 +1,8197 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. -+ * -+ * Copyright 2017-2019 NXP -+ */ -+/* -+ * Based on STMP378X PxP driver -+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "regs-pxp_v3.h" -+#include "reg_bitfields.h" -+ -+#ifdef CONFIG_MXC_FPGA_M4_TEST -+#include "cm4_image.c" -+#define FPGA_TCML_ADDR 0x0C7F8000 -+#define PINCTRL 0x0C018000 -+#define PIN_DOUT 0x700 -+void __iomem *fpga_tcml_base; -+void __iomem *pinctrl_base; -+#endif -+ -+#define PXP_FILL_TIMEOUT 3000 -+#define busy_wait(cond) \ -+ ({ \ -+ unsigned long end_jiffies = jiffies + \ -+ msecs_to_jiffies(PXP_FILL_TIMEOUT); \ -+ bool succeeded = false; \ -+ do { \ -+ if (cond) { \ -+ succeeded = true; \ -+ break; \ -+ } \ -+ cpu_relax(); \ -+ } while (time_after(end_jiffies, jiffies)); \ -+ succeeded; \ -+ }) -+ -+#define PXP_DOWNSCALE_THRESHOLD 0x4000 -+ -+#define CONFIG_FB_MXC_EINK_FPGA -+ -+/* define all the pxp 2d nodes */ -+#define PXP_2D_PS 0 -+#define PXP_2D_AS 1 -+#define PXP_2D_INPUT_FETCH0 2 -+#define PXP_2D_INPUT_FETCH1 3 -+#define PXP_2D_CSC1 4 -+#define PXP_2D_ROTATION1 5 -+#define PXP_2D_ALPHA0_S0 6 -+#define PXP_2D_ALPHA0_S1 7 -+#define PXP_2D_ALPHA1_S0 8 -+#define PXP_2D_ALPHA1_S1 9 -+#define PXP_2D_CSC2 10 -+#define PXP_2D_LUT 11 -+#define PXP_2D_ROTATION0 12 -+#define PXP_2D_OUT 13 -+#define PXP_2D_INPUT_STORE0 14 -+#define PXP_2D_INPUT_STORE1 15 -+#define PXP_2D_NUM 16 -+ -+#define PXP_2D_ALPHA0_S0_S1 0xaa -+#define PXP_2D_ALPHA1_S0_S1 0xbb -+ -+#define PXP_2D_MUX_BASE 50 -+#define PXP_2D_MUX_MUX0 (PXP_2D_MUX_BASE + 0) -+#define PXP_2D_MUX_MUX1 (PXP_2D_MUX_BASE + 1) -+#define PXP_2D_MUX_MUX2 (PXP_2D_MUX_BASE + 2) -+#define PXP_2D_MUX_MUX3 (PXP_2D_MUX_BASE + 3) -+#define PXP_2D_MUX_MUX4 (PXP_2D_MUX_BASE + 4) -+#define PXP_2D_MUX_MUX5 (PXP_2D_MUX_BASE + 5) -+#define PXP_2D_MUX_MUX6 (PXP_2D_MUX_BASE + 6) -+#define PXP_2D_MUX_MUX7 (PXP_2D_MUX_BASE + 7) -+#define PXP_2D_MUX_MUX8 (PXP_2D_MUX_BASE + 8) -+#define PXP_2D_MUX_MUX9 (PXP_2D_MUX_BASE + 9) -+#define PXP_2D_MUX_MUX10 (PXP_2D_MUX_BASE + 10) -+#define PXP_2D_MUX_MUX11 (PXP_2D_MUX_BASE + 11) -+#define PXP_2D_MUX_MUX12 (PXP_2D_MUX_BASE + 12) -+#define PXP_2D_MUX_MUX13 (PXP_2D_MUX_BASE + 13) -+#define PXP_2D_MUX_MUX14 (PXP_2D_MUX_BASE + 14) -+#define PXP_2D_MUX_MUX15 (PXP_2D_MUX_BASE + 15) -+ -+/* define pxp 2d node types */ -+#define PXP_2D_TYPE_INPUT 1 -+#define PXP_2D_TYPE_ALU 2 -+#define PXP_2D_TYPE_OUTPUT 3 -+ -+#define DISTANCE_INFINITY 0xffff -+#define NO_PATH_NODE 0xffffffff -+ -+#define PXP_MAX_INPUT_NUM 2 -+#define PXP_MAX_OUTPUT_NUM 2 -+ -+#define FETCH_NOOP 0x01 -+#define FETCH_EXPAND 0x02 -+#define FETCH_SHIFT 0x04 -+ -+#define STORE_NOOP 0x01 -+#define STORE_SHIFT 0x02 -+#define STORE_SHRINK 0x04 -+ -+#define NEED_YUV_SWAP 0x02 -+ -+#define IN_NEED_COMPOSITE (0x01 | IN_NEED_FMT_UNIFIED) -+#define IN_NEED_CSC (0x02 | IN_NEED_FMT_UNIFIED) -+#define IN_NEED_SCALE (0x04 | IN_NEED_FMT_UNIFIED) -+#define IN_NEED_ROTATE_FLIP (0x08 | IN_NEED_FMT_UNIFIED) -+#define IN_NEED_FMT_UNIFIED 0x10 -+#define IN_NEED_SHIFT 0x20 -+#define IN_NEED_LUT (0x40 | IN_NEED_UNIFIED) -+ -+#define OUT_NEED_SHRINK 0x100 -+#define OUT_NEED_SHIFT 0x200 -+ -+#define PXP_ROTATE_0 0 -+#define PXP_ROTATE_90 1 -+#define PXP_ROTATE_180 2 -+#define PXP_ROTATE_270 3 -+ -+#define PXP_H_FLIP 1 -+#define PXP_V_FLIP 2 -+ -+#define PXP_OP_TYPE_2D 0x001 -+#define PXP_OP_TYPE_DITHER 0x002 -+#define PXP_OP_TYPE_WFE_A 0x004 -+#define PXP_OP_TYPE_WFE_B 0x008 -+ -+/* define store engine output mode */ -+#define STORE_MODE_NORMAL 1 -+#define STORE_MODE_BYPASS 2 -+#define STORE_MODE_DUAL 3 -+#define STORE_MODE_HANDSHAKE 4 -+ -+/* define fetch engine input mode */ -+#define FETCH_MODE_NORMAL 1 -+#define FETCH_MODE_BYPASS 2 -+#define FETCH_MODE_HANDSHAKE 3 -+ -+#define COMMON_FMT_BPP 32 -+ -+#define R_COMP 0 -+#define G_COMP 1 -+#define B_COMP 2 -+#define A_COMP 3 -+ -+#define Y_COMP 0 -+#define U_COMP 1 -+#define V_COMP 2 -+#define Y1_COMP 4 -+ -+static LIST_HEAD(head); -+static int timeout_in_ms = 600; -+static unsigned int block_size; -+static struct kmem_cache *tx_desc_cache; -+static struct kmem_cache *edge_node_cache; -+static struct pxp_collision_info col_info; -+static bool v3p_flag; -+static int alpha_blending_version; -+static bool pxp_legacy; -+ -+struct pxp_dma { -+ struct dma_device dma; -+}; -+ -+enum pxp_alpha_blending_version { -+ PXP_ALPHA_BLENDING_NONE = 0x0, -+ PXP_ALPHA_BLENDING_V1 = 0x1, -+ PXP_ALPHA_BLENDING_V2 = 0x2, -+}; -+ -+struct pxp_alpha_global { -+ unsigned int color_key_enable; -+ bool combine_enable; -+ bool global_alpha_enable; -+ bool global_override; -+ bool alpha_invert; -+ bool local_alpha_enable; -+ unsigned char global_alpha; -+ int comp_mask; -+}; -+ -+struct rectangle { -+ uint16_t x; -+ uint16_t y; -+ uint16_t width; -+ uint16_t height; -+}; -+ -+struct pxp_alpha_info { -+ uint8_t alpha_mode; -+ uint8_t rop_type; -+ -+ struct pxp_alpha s0_alpha; -+ struct pxp_alpha s1_alpha; -+}; -+ -+struct pxp_op_info{ -+ uint16_t op_type; -+ uint16_t rotation; -+ uint8_t flip; -+ uint8_t fill_en; -+ uint32_t fill_data; -+ uint8_t alpha_blending; -+ struct pxp_alpha_info alpha_info; -+ -+ /* Dithering specific data */ -+ uint32_t dither_mode; -+ uint32_t quant_bit; -+ -+ /* -+ * partial: -+ * 0 - full update -+ * 1 - partial update -+ * alpha_en: -+ * 0 - upd is {Y4[3:0],4'b0000} format -+ * 1 - upd is {Y4[3:0],3'b000,alpha} format -+ * reagl_en: -+ * 0 - use normal waveform algorithm -+ * 1 - enable reagl/-d waveform algorithm -+ * detection_only: -+ * 0 - write working buffer -+ * 1 - do no write working buffer, detection only -+ * lut: -+ * valid value 0-63 -+ * set to the lut used for next update -+ */ -+ bool partial_update; -+ bool alpha_en; -+ bool lut_update; -+ bool reagl_en; /* enable reagl/-d */ -+ bool reagl_d_en; /* enable reagl or reagl-d */ -+ bool detection_only; -+ int lut; -+ uint32_t lut_status_1; -+ uint32_t lut_status_2; -+}; -+ -+struct pxp_pixmap { -+ uint8_t channel_id; -+ uint8_t bpp; -+ int32_t pitch; -+ uint16_t width; -+ uint16_t height; -+ struct rectangle crop; -+ uint32_t rotate; -+ uint8_t flip; -+ uint32_t format; /* fourcc pixmap format */ -+ uint32_t flags; -+ bool valid; -+ dma_addr_t paddr; -+ struct pxp_alpha_global g_alpha; -+}; -+ -+struct pxp_task_info { -+ uint8_t input_num; -+ uint8_t output_num; -+ struct pxp_pixmap input[PXP_MAX_INPUT_NUM]; -+ struct pxp_pixmap output[PXP_MAX_OUTPUT_NUM]; -+ struct pxp_op_info op_info; -+ uint32_t pxp_2d_flags; -+}; -+ -+struct pxps { -+ struct platform_device *pdev; -+ struct clk *ipg_clk; -+ struct clk *axi_clk; -+ void __iomem *base; -+ int irq; /* PXP IRQ to the CPU */ -+ -+ spinlock_t lock; -+ struct mutex clk_mutex; -+ int clk_stat; -+#define CLK_STAT_OFF 0 -+#define CLK_STAT_ON 1 -+ int pxp_ongoing; -+ int lut_state; -+ -+ struct device *dev; -+ struct pxp_dma pxp_dma; -+ struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; -+ struct work_struct work; -+ -+ const struct pxp_devdata *devdata; -+ struct pxp_task_info task; -+ -+ /* describes most recent processing configuration */ -+ struct pxp_config_data pxp_conf_state; -+ -+ /* to turn clock off when pxp is inactive */ -+ struct timer_list clk_timer; -+ -+ /* for pxp config dispatch asynchronously*/ -+ struct task_struct *dispatch; -+ wait_queue_head_t thread_waitq; -+ struct completion complete; -+}; -+ -+#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) -+#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) -+#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) -+#define to_pxp(id) container_of(id, struct pxps, pxp_dma) -+ -+#define to_pxp_task_info(op) container_of((op), struct pxp_task_info, op_info) -+#define to_pxp_from_task(task) container_of((task), struct pxps, task) -+ -+#define PXP_DEF_BUFS 2 -+#define PXP_MIN_PIX 8 -+ -+static uint8_t active_bpp(uint8_t bpp) -+{ -+ switch(bpp) { -+ case 8: -+ return 0x0; -+ case 16: -+ return 0x1; -+ case 32: -+ return 0x2; -+ case 64: -+ return 0x3; -+ default: -+ return 0xff; -+ } -+} -+ -+static uint8_t rotate_map(uint32_t degree) -+{ -+ switch (degree) { -+ case 0: -+ return PXP_ROTATE_0; -+ case 90: -+ return PXP_ROTATE_90; -+ case 180: -+ return PXP_ROTATE_180; -+ case 270: -+ return PXP_ROTATE_270; -+ default: -+ return 0; -+ } -+} -+ -+static uint8_t expand_format(uint32_t format) -+{ -+ switch (format) { -+ case PXP_PIX_FMT_RGB565: -+ case PXP_PIX_FMT_BGR565: -+ return 0x0; -+ case PXP_PIX_FMT_RGB555: -+ return 0x1; -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_YVYU: -+ return 0x5; -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_VYUY: -+ return 0x6; -+ case PXP_PIX_FMT_NV16: -+ return 0x7; -+ default: -+ return 0xff; -+ } -+} -+ -+struct color_component { -+ uint8_t id; -+ uint8_t offset; -+ uint8_t length; -+ uint8_t mask; -+}; -+ -+struct color { -+ uint32_t format; -+ struct color_component comp[4]; -+}; -+ -+struct color rgb_colors[] = { -+ { -+ .format = PXP_PIX_FMT_RGB565, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, -+ { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, -+ { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, -+ { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_BGR565, -+ .comp = { -+ { .id = R_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, -+ { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, -+ { .id = B_COMP, .offset = 11, .length = 6, .mask = 0x3f, }, -+ { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_ARGB555, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, -+ { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, -+ { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, -+ { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_XRGB555, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, -+ { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, -+ { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, -+ { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_RGB555, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, -+ { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, -+ { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, -+ { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_RGBA555, -+ .comp = { -+ { .id = A_COMP, .offset = 0, .length = 1, .mask = 0x1, }, -+ { .id = B_COMP, .offset = 1, .length = 5, .mask = 0x1f, }, -+ { .id = G_COMP, .offset = 6, .length = 5, .mask = 0x1f, }, -+ { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_ARGB444, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, -+ { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, -+ { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, -+ { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_XRGB444, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, -+ { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, -+ { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, -+ { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_RGBA444, -+ .comp = { -+ { .id = A_COMP, .offset = 0, .length = 4, .mask = 0xf, }, -+ { .id = B_COMP, .offset = 4, .length = 4, .mask = 0xf, }, -+ { .id = G_COMP, .offset = 8, .length = 4, .mask = 0xf, }, -+ { .id = R_COMP, .offset = 12, .length = 4, .mask = 0xf, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_RGB24, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_BGR24, -+ .comp = { -+ { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_XRGB32, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_RGBX32, -+ .comp = { -+ { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_XBGR32, -+ .comp = { -+ { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_BGRX32, -+ .comp = { -+ { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_ARGB32, -+ .comp = { -+ { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_ABGR32, -+ .comp = { -+ { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_RGBA32, -+ .comp = { -+ { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_BGRA32, -+ .comp = { -+ { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, -+}; -+ -+/* only one plane yuv formats */ -+struct color yuv_colors[] = { -+ { -+ .format = PXP_PIX_FMT_GREY, -+ .comp = { -+ { .id = Y_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = U_COMP, .offset = 8, .length = 0, .mask = 0x00, }, -+ { .id = V_COMP, .offset = 16, .length = 0, .mask = 0x00, }, -+ { .id = A_COMP, .offset = 24, .length = 0, .mask = 0x00, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_YUYV, -+ .comp = { -+ { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = U_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_UYVY, -+ .comp = { -+ { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = U_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_YVYU, -+ .comp = { -+ { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = V_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_VYUY, -+ .comp = { -+ { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = V_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_YUV444, -+ .comp = { -+ { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, { -+ .format = PXP_PIX_FMT_YVU444, -+ .comp = { -+ { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, -+ { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, -+ { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, -+ { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, -+ }, -+ }, -+}; -+ -+/* 4 to 1 mux */ -+struct mux { -+ uint32_t id; -+ uint8_t mux_inputs[4]; -+ uint8_t mux_outputs[2]; -+}; -+ -+/* Adjacent list structure */ -+struct edge_node { -+ uint32_t adjvex; -+ uint32_t prev_vnode; -+ struct edge_node *next; -+ uint32_t mux_used; -+ struct mux_config muxes; -+}; -+ -+struct vetex_node { -+ uint8_t type; -+ struct edge_node *first; -+}; -+ -+struct path_node { -+ struct list_head node; -+ uint32_t id; -+ uint32_t distance; -+ uint32_t prev_node; -+}; -+ -+static struct vetex_node adj_list[PXP_2D_NUM]; -+static struct path_node path_table[PXP_2D_NUM][PXP_2D_NUM]; -+ -+static bool adj_array_v3[PXP_2D_NUM][PXP_2D_NUM] = { -+ /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ -+ {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ -+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ -+ {0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0}, /* 2 */ -+ {0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1}, /* 3 */ -+ {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ -+ {0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0}, /* 5 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 8 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 9 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0}, /* 10 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0}, /* 11 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ -+}; -+ -+ -+static struct mux muxes_v3[16] = { -+ { -+ /* mux0 */ -+ .id = 0, -+ .mux_inputs = {PXP_2D_CSC1, PXP_2D_INPUT_FETCH0, PXP_2D_INPUT_FETCH1, 0xff}, -+ .mux_outputs = {PXP_2D_ROTATION1, 0xff}, -+ }, { -+ /* mux1 */ -+ .id = 1, -+ .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_ROTATION1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_ALPHA1_S1, PXP_2D_MUX_MUX5}, -+ }, { -+ /* mux2 */ -+ .id = 2, -+ .mux_inputs = {PXP_2D_INPUT_FETCH1, PXP_2D_ROTATION1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_ALPHA1_S0, 0xff}, -+ }, { -+ /* mux3 */ -+ .id = 3, -+ .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, -+ }, { -+ /* mux4 is not used in ULT1 */ -+ .id = 4, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux5 */ -+ .id = 5, -+ .mux_inputs = {PXP_2D_MUX_MUX1, PXP_2D_ALPHA1_S0_S1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX7, 0xff}, -+ }, { -+ /* mux6 */ -+ .id = 6, -+ .mux_inputs = {PXP_2D_ALPHA1_S0_S1, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_CSC2, 0xff}, -+ }, { -+ /* mux7 */ -+ .id = 7, -+ .mux_inputs = {PXP_2D_MUX_MUX5, PXP_2D_CSC2, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX10}, -+ }, { -+ /* mux8 */ -+ .id = 8, -+ .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, -+ }, { -+ /* mux9 */ -+ .id = 9, -+ .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_MUX_MUX8, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_LUT, 0xff}, -+ }, { -+ /* mux10 */ -+ .id = 10, -+ .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_LUT, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX15}, -+ }, { -+ /* mux11 */ -+ .id = 11, -+ .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX14}, -+ }, { -+ /* mux12 */ -+ .id = 12, -+ .mux_inputs = {PXP_2D_MUX_MUX10, PXP_2D_MUX_MUX11, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_ROTATION0, 0xff}, -+ }, { -+ /* mux13 */ -+ .id = 13, -+ .mux_inputs = {PXP_2D_INPUT_FETCH1, 0xff, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_INPUT_STORE1, 0xff}, -+ }, { -+ /* mux14 */ -+ .id = 14, -+ .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_OUT, 0xff}, -+ }, { -+ /* mux15 */ -+ .id = 15, -+ .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_MUX_MUX10, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_INPUT_STORE0, 0xff}, -+ }, -+}; -+ -+static bool adj_array_v3p[PXP_2D_NUM][PXP_2D_NUM] = { -+ /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ -+ {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ -+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 3 */ -+ {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ -+ {0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 5 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 8 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 9 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0}, /* 10 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0}, /* 11 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ -+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ -+}; -+ -+static struct mux muxes_v3p[16] = { -+ { -+ /* mux0 */ -+ .id = 0, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux1 */ -+ .id = 1, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux2 */ -+ .id = 2, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux3 */ -+ .id = 3, -+ .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, -+ }, { -+ /* mux4 is not used in ULT1 */ -+ .id = 4, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux5 */ -+ .id = 5, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux6 */ -+ .id = 6, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux7 */ -+ .id = 7, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux8 */ -+ .id = 8, -+ .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, -+ }, { -+ /* mux9 */ -+ .id = 9, -+ .mux_inputs = {0xff, PXP_2D_MUX_MUX8, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_LUT, 0xff}, -+ }, { -+ /* mux10 */ -+ .id = 10, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux11 */ -+ .id = 11, -+ .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_ROTATION0}, -+ }, { -+ /* mux12 */ -+ .id = 12, -+ .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_MUX_MUX14, 0xff}, -+ }, { -+ /* mux13 */ -+ .id = 13, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, { -+ /* mux14 */ -+ .id = 14, -+ .mux_inputs = {0xff, PXP_2D_MUX_MUX12, 0xff, 0xff}, -+ .mux_outputs = {PXP_2D_OUT, 0xff}, -+ }, { -+ /* mux15 */ -+ .id = 15, -+ .mux_inputs = {0xff, 0xff, 0xff, 0xff}, -+ .mux_outputs = {0xff, 0xff}, -+ }, -+}; -+ -+static void __iomem *pxp_reg_base; -+ -+#define pxp_writel(val, reg) writel(val, pxp_reg_base + (reg)) -+ -+static __attribute__((aligned (1024*4))) unsigned int active_matrix_data_8x8[64]={ -+ 0x06050100, 0x04030207, 0x06050100, 0x04030207, -+ 0x00040302, 0x07060501, 0x00040302, 0x07060501, -+ 0x02070605, 0x01000403, 0x02070605, 0x01000403, -+ 0x05010004, 0x03020706, 0x05010004, 0x03020706, -+ 0x04030207, 0x06050100, 0x04030207, 0x06050100, -+ 0x07060501, 0x00040302, 0x07060501, 0x00040302, -+ 0x01000403, 0x02070605, 0x01000403, 0x02070605, -+ 0x03020706, 0x05010004, 0x03020706, 0x05010004, -+ 0x06050100, 0x04030207, 0x06050100, 0x04030207, -+ 0x00040302, 0x07060501, 0x00040302, 0x07060501, -+ 0x02070605, 0x01000403, 0x02070605, 0x01000403, -+ 0x05010004, 0x03020706, 0x05010004, 0x03020706, -+ 0x04030207, 0x06050100, 0x04030207, 0x06050100, -+ 0x07060501, 0x00040302, 0x07060501, 0x00040302, -+ 0x01000403, 0x02070605, 0x01000403, 0x02070605, -+ 0x03020706, 0x05010004, 0x03020706, 0x05010004 -+ }; -+ -+static __attribute__((aligned (1024*4))) unsigned int bit1_dither_data_8x8[64] = { -+ -+ 1, 49*2, 13*2, 61*2, 4*2, 52*2, 16*2, 64*2, -+ 33*2, 17*2, 45*2, 29*2, 36*2, 20*2, 48*2, 32*2, -+ 9*2, 57*2, 5*2, 53*2, 12*2, 60*2, 8*2, 56*2, -+ 41*2, 25*2, 37*2, 21*2, 44*2, 28*2, 40*2, 24*2, -+ 3*2, 51*2, 15*2, 63*2, 2*2, 50*2, 14*2, 62*2, -+ 35*2, 19*2, 47*2, 31*2, 34*2, 18*2, 46*2, 30*2, -+ 11*2, 59*2, 7*2, 55*2, 10*2, 58*2, 6*2, 54*2, -+ 43*2, 27*2, 39*2, 23*2, 42*2, 26*2, 38*2, 22*2 -+}; -+ -+static __attribute__((aligned (1024*4))) unsigned int bit2_dither_data_8x8[64] = { -+ -+ 1, 49, 13, 61, 4, 52, 16, 64, -+ 33, 17, 45, 29, 36, 20, 48, 32, -+ 9, 57, 5, 53, 12, 60, 8, 56, -+ 41, 25, 37, 21, 44, 28, 40, 24, -+ 3, 51, 15, 63, 2, 50, 14, 62, -+ 35, 19, 47, 31, 34, 18, 46, 30, -+ 11, 59, 7, 55, 10, 58, 6, 54, -+ 43, 27, 39, 23, 42, 26, 38, 22 -+}; -+ -+static __attribute__((aligned (1024*4))) unsigned int bit4_dither_data_8x8[64] = { -+ -+ 1, 49/4, 13/4, 61/4, 4/4, 52/4, 16/4, 64/4, -+ 33/4, 17/4, 45/4, 29/4, 36/4, 20/4, 48/4, 32/4, -+ 9/4, 57/4, 5/4, 53/4, 12/4, 60/4, 8/4, 56/4, -+ 41/4, 25/4, 37/4, 21/4, 44/4, 28/4, 40/4, 24/4, -+ 3/4, 51/4, 15/4, 63/4, 2/4, 50/4, 14/4, 62/4, -+ 35/4, 19/4, 47/4, 31/4, 34/4, 18/4, 46/4, 30/4, -+ 11/4, 59/4, 7/4, 55/4, 10/4, 58/4, 6/4, 54/4, -+ 43/4, 27/4, 39/4, 23/4, 42/4, 26/4, 38/4, 22/4 -+}; -+ -+static void pxp_dithering_configure(struct pxps *pxp); -+static void pxp_dithering_configure_v3p(struct pxps *pxp); -+static void pxp_dithering_process(struct pxps *pxp); -+static void pxp_wfe_a_process(struct pxps *pxp); -+static void pxp_wfe_a_process_v3p(struct pxps *pxp); -+static void pxp_wfe_a_configure(struct pxps *pxp); -+static void pxp_wfe_a_configure_v3p(struct pxps *pxp); -+static void pxp_wfe_b_process(struct pxps *pxp); -+static void pxp_wfe_b_configure(struct pxps *pxp); -+static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut); -+static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut); -+static void pxp_lut_status_clr(unsigned int lut); -+static void pxp_lut_status_clr_v3p(unsigned int lut); -+static void pxp_start2(struct pxps *pxp); -+static void pxp_data_path_config_v3p(struct pxps *pxp); -+static void pxp_soft_reset(struct pxps *pxp); -+static void pxp_collision_detection_disable(struct pxps *pxp); -+static void pxp_collision_detection_enable(struct pxps *pxp, -+ unsigned int width, -+ unsigned int height); -+static void pxp_luts_activate(struct pxps *pxp, u64 lut_status); -+static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info); -+static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status); -+static void pxp_histogram_enable(struct pxps *pxp, -+ unsigned int width, -+ unsigned int height); -+static void pxp_histogram_disable(struct pxps *pxp); -+static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set); -+static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set); -+static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status); -+static void pxp_set_colorkey(struct pxps *pxp); -+static void pxp_software_restart(struct pxps *pxp); -+ -+enum { -+ DITHER0_LUT = 0x0, /* Select the LUT memory for access */ -+ DITHER0_ERR0 = 0x1, /* Select the ERR0 memory for access */ -+ DITHER0_ERR1 = 0x2, /* Select the ERR1 memory for access */ -+ DITHER1_LUT = 0x3, /* Select the LUT memory for access */ -+ DITHER2_LUT = 0x4, /* Select the LUT memory for access */ -+ ALU_A = 0x5, /* Select the ALU instr memory for access */ -+ ALU_B = 0x6, /* Select the ALU instr memory for access */ -+ WFE_A = 0x7, /* Select the WFE_A instr memory for access */ -+ WFE_B = 0x8, /* Select the WFE_B instr memory for access */ -+ RESERVED = 0x15, -+}; -+ -+enum pxp_devtype { -+ PXP_V3, -+ PXP_V3P, /* minor changes over V3, use WFE_B to replace WFE_A */ -+ PXP_V3_8ULP, /* PXP V3 version for iMX8ULP */ -+}; -+ -+#define pxp_is_v3(pxp) ((pxp->devdata->version == 30) || \ -+ (pxp->devdata->version == 32)) -+#define pxp_is_v3p(pxp) (pxp->devdata->version == 31) -+ -+struct pxp_devdata { -+ void (*pxp_wfe_a_configure)(struct pxps *pxp); -+ void (*pxp_wfe_a_process)(struct pxps *pxp); -+ void (*pxp_lut_status_set)(struct pxps *pxp, unsigned int lut); -+ void (*pxp_lut_status_clr)(unsigned int lut); -+ void (*pxp_dithering_configure)(struct pxps *pxp); -+ void (*pxp_lut_cleanup_multiple)(struct pxps *pxp, u64 lut, bool set); -+ void (*pxp_data_path_config)(struct pxps *pxp); -+ void (*pxp_restart)(struct pxps *pxp); -+ unsigned int version; -+}; -+ -+static const struct pxp_devdata pxp_devdata[] = { -+ [PXP_V3] = { -+ .pxp_wfe_a_configure = pxp_wfe_a_configure, -+ .pxp_wfe_a_process = pxp_wfe_a_process, -+ .pxp_lut_status_set = pxp_lut_status_set, -+ .pxp_lut_status_clr = pxp_lut_status_clr, -+ .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, -+ .pxp_dithering_configure = pxp_dithering_configure, -+ .pxp_data_path_config = NULL, -+ .pxp_restart = NULL, -+ .version = 30, -+ }, -+ [PXP_V3P] = { -+ .pxp_wfe_a_configure = pxp_wfe_a_configure_v3p, -+ .pxp_wfe_a_process = pxp_wfe_a_process_v3p, -+ .pxp_lut_status_set = pxp_lut_status_set_v3p, -+ .pxp_lut_status_clr = pxp_lut_status_clr_v3p, -+ .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple_v3p, -+ .pxp_dithering_configure = pxp_dithering_configure_v3p, -+ .pxp_data_path_config = pxp_data_path_config_v3p, -+ .pxp_restart = NULL, -+ .version = 31, -+ }, -+ [PXP_V3_8ULP] = { -+ .pxp_wfe_a_configure = pxp_wfe_a_configure, -+ .pxp_wfe_a_process = pxp_wfe_a_process, -+ .pxp_lut_status_set = pxp_lut_status_set, -+ .pxp_lut_status_clr = pxp_lut_status_clr, -+ .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, -+ .pxp_dithering_configure = pxp_dithering_configure, -+ .pxp_data_path_config = NULL, -+ .pxp_restart = pxp_software_restart, -+ .version = 32, -+ }, -+}; -+ -+/* -+ * PXP common functions -+ */ -+static void dump_pxp_reg(struct pxps *pxp) -+{ -+ dev_dbg(pxp->dev, "PXP_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CTRL)); -+ dev_dbg(pxp->dev, "PXP_STAT 0x%x", -+ __raw_readl(pxp->base + HW_PXP_STAT)); -+ dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); -+ dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_BUF)); -+ dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); -+ dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); -+ dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_LRC)); -+ dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); -+ dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); -+ dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); -+ dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", -+ __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); -+ dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_CTRL)); -+ dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_BUF)); -+ dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_UBUF)); -+ dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_VBUF)); -+ dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_PITCH)); -+ dev_dbg(pxp->dev, "PXP_PS_BACKGROUND_0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND_0)); -+ dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_SCALE)); -+ dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); -+ dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW_0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW_0)); -+ dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH_0)); -+ dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_CTRL)); -+ dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_BUF)); -+ dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_PITCH)); -+ dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW_0)); -+ dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", -+ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH_0)); -+ dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); -+ dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); -+ dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); -+ dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); -+ dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); -+ dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); -+ dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); -+ dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_DATA)); -+ dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", -+ __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); -+ dev_dbg(pxp->dev, "PXP_CFA 0x%x", -+ __raw_readl(pxp->base + HW_PXP_CFA)); -+ dev_dbg(pxp->dev, "PXP_ALPHA_A_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_ALPHA_A_CTRL)); -+ dev_dbg(pxp->dev, "PXP_ALPHA_B_CTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_ALPHA_B_CTRL)); -+ dev_dbg(pxp->dev, "PXP_POWER_REG0 0x%x", -+ __raw_readl(pxp->base + HW_PXP_POWER_REG0)); -+ dev_dbg(pxp->dev, "PXP_NEXT 0x%x", -+ __raw_readl(pxp->base + HW_PXP_NEXT)); -+ dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", -+ __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); -+ dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", -+ __raw_readl(pxp->base + HW_PXP_DEBUG)); -+ dev_dbg(pxp->dev, "PXP_VERSION 0x%x", -+ __raw_readl(pxp->base + HW_PXP_VERSION)); -+} -+ -+static void dump_pxp_reg2(struct pxps *pxp) -+{ -+#ifdef DEBUG -+ int i = 0; -+ -+ for (i=0; i< ((0x33C0/0x10) + 1);i++) { -+ printk("0x%08x: 0x%08x\n", 0x10*i, __raw_readl(pxp->base + 0x10*i)); -+ } -+#endif -+} -+ -+static void print_param(struct pxp_layer_param *p, char *s) -+{ -+ pr_debug("%s: t/l/w/h/s %d/%d/%d/%d/%d, addr %p\n", s, -+ p->top, p->left, p->width, p->height, p->stride, (void *)p->paddr); -+} -+ -+/* when it is, return yuv plane number */ -+static uint8_t is_yuv(uint32_t format) -+{ -+ switch (format) { -+ case PXP_PIX_FMT_GREY: -+ case PXP_PIX_FMT_GY04: -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_YVYU: -+ case PXP_PIX_FMT_VYUY: -+ case PXP_PIX_FMT_YUV444: -+ case PXP_PIX_FMT_YVU444: -+ case PXP_PIX_FMT_VUY444: -+ return 1; -+ case PXP_PIX_FMT_NV12: -+ case PXP_PIX_FMT_NV21: -+ case PXP_PIX_FMT_NV16: -+ case PXP_PIX_FMT_NV61: -+ return 2; -+ case PXP_PIX_FMT_YUV420P: -+ case PXP_PIX_FMT_YUV422P: -+ case PXP_PIX_FMT_YVU420P: -+ case PXP_PIX_FMT_YVU422P: -+ return 3; -+ default: -+ return 0; -+ } -+} -+ -+static u32 get_bpp_from_fmt(u32 pix_fmt) -+{ -+ unsigned int bpp = 0; -+ -+ switch (pix_fmt) { -+ case PXP_PIX_FMT_GREY: -+ case PXP_PIX_FMT_NV16: -+ case PXP_PIX_FMT_NV61: -+ case PXP_PIX_FMT_NV12: -+ case PXP_PIX_FMT_NV21: -+ case PXP_PIX_FMT_YUV422P: -+ case PXP_PIX_FMT_YVU422P: -+ case PXP_PIX_FMT_YUV420P: -+ case PXP_PIX_FMT_YVU420P: -+ bpp = 8; -+ break; -+ case PXP_PIX_FMT_RGB555: -+ case PXP_PIX_FMT_ARGB555: -+ case PXP_PIX_FMT_XRGB555: -+ case PXP_PIX_FMT_RGBA555: -+ case PXP_PIX_FMT_ARGB444: -+ case PXP_PIX_FMT_XRGB444: -+ case PXP_PIX_FMT_RGBA444: -+ case PXP_PIX_FMT_RGB565: -+ case PXP_PIX_FMT_BGR565: -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_YVYU: -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_VYUY: -+ bpp = 16; -+ break; -+ case PXP_PIX_FMT_RGB24: -+ case PXP_PIX_FMT_BGR24: -+ bpp = 24; -+ break; -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_RGBX32: -+ case PXP_PIX_FMT_XBGR32: -+ case PXP_PIX_FMT_BGRX32: -+ case PXP_PIX_FMT_ARGB32: -+ case PXP_PIX_FMT_RGBA32: -+ case PXP_PIX_FMT_ABGR32: -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_YUV444: -+ case PXP_PIX_FMT_YVU444: -+ case PXP_PIX_FMT_VUY444: -+ bpp = 32; -+ break; -+ default: -+ pr_err("%s: pix_fmt unsupport yet: 0x%x\n", __func__, pix_fmt); -+ break; -+ } -+ -+ return bpp; -+} -+ -+static uint32_t pxp_parse_ps_fmt(uint32_t format) -+{ -+ uint32_t fmt_ctrl; -+ -+ switch (format) { -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_ARGB32: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; -+ break; -+ case PXP_PIX_FMT_RGB565: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; -+ break; -+ case PXP_PIX_FMT_RGB555: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; -+ break; -+ case PXP_PIX_FMT_YUV420P: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; -+ break; -+ case PXP_PIX_FMT_YVU420P: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; -+ break; -+ case PXP_PIX_FMT_GREY: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; -+ break; -+ case PXP_PIX_FMT_GY04: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; -+ break; -+ case PXP_PIX_FMT_VUY444: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; -+ break; -+ case PXP_PIX_FMT_YUV422P: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; -+ break; -+ case PXP_PIX_FMT_UYVY: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; -+ break; -+ case PXP_PIX_FMT_YUYV: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; -+ break; -+ case PXP_PIX_FMT_VYUY: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; -+ break; -+ case PXP_PIX_FMT_YVYU: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; -+ break; -+ case PXP_PIX_FMT_NV12: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; -+ break; -+ case PXP_PIX_FMT_NV21: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; -+ break; -+ case PXP_PIX_FMT_NV16: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; -+ break; -+ case PXP_PIX_FMT_NV61: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; -+ break; -+ case PXP_PIX_FMT_RGBA32: -+ case PXP_PIX_FMT_RGBX32: -+ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGBA888; -+ break; -+ default: -+ pr_debug("PS doesn't support this format\n"); -+ fmt_ctrl = 0; -+ } -+ -+ return fmt_ctrl; -+} -+ -+static void pxp_set_colorkey(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_layer_param *s0_params = &pxp_conf->s0_param; -+ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; -+ -+ /* Low and high are set equal. V4L does not allow a chromakey range */ -+ if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { -+ /* disable color key */ -+ pxp_writel(0xFFFFFF, HW_PXP_PS_CLRKEYLOW_0); -+ pxp_writel(0, HW_PXP_PS_CLRKEYHIGH_0); -+ } else { -+ pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYLOW_0); -+ pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYHIGH_0); -+ } -+ -+ if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { -+ pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYLOW_0); -+ pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYHIGH_0); -+ } else { -+ /* disable color key */ -+ pxp_writel(0xFFFFFF, HW_PXP_AS_CLRKEYLOW_0); -+ pxp_writel(0, HW_PXP_AS_CLRKEYHIGH_0); -+ } -+} -+ -+static void pxp_software_restart(struct pxps *pxp) -+{ -+ pxp_soft_reset(pxp); -+ pxp_writel(0x0, HW_PXP_CTRL); -+ -+ if (pxp->devdata && pxp->devdata->pxp_data_path_config) -+ pxp->devdata->pxp_data_path_config(pxp); -+ __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); -+} -+ -+static uint32_t pxp_parse_as_fmt(uint32_t format) -+{ -+ uint32_t fmt_ctrl; -+ -+ switch (format) { -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_ARGB32: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB8888; -+ break; -+ case PXP_PIX_FMT_RGBA32: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA8888; -+ break; -+ case PXP_PIX_FMT_XRGB32: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB888; -+ break; -+ case PXP_PIX_FMT_ARGB555: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB1555; -+ break; -+ case PXP_PIX_FMT_ARGB444: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB4444; -+ break; -+ case PXP_PIX_FMT_RGBA555: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA5551; -+ break; -+ case PXP_PIX_FMT_RGBA444: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA4444; -+ break; -+ case PXP_PIX_FMT_RGB555: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB555; -+ break; -+ case PXP_PIX_FMT_RGB444: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB444; -+ break; -+ case PXP_PIX_FMT_RGB565: -+ fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB565; -+ break; -+ default: -+ pr_debug("AS doesn't support this format\n"); -+ fmt_ctrl = 0xf; -+ break; -+ } -+ -+ return fmt_ctrl; -+} -+ -+static uint32_t pxp_parse_out_fmt(uint32_t format) -+{ -+ uint32_t fmt_ctrl; -+ -+ switch (format) { -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_ARGB32: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; -+ break; -+ case PXP_PIX_FMT_XRGB32: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; -+ break; -+ case PXP_PIX_FMT_RGB24: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; -+ break; -+ case PXP_PIX_FMT_RGB565: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; -+ break; -+ case PXP_PIX_FMT_RGB555: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; -+ break; -+ case PXP_PIX_FMT_GREY: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; -+ break; -+ case PXP_PIX_FMT_GY04: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; -+ break; -+ case PXP_PIX_FMT_UYVY: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; -+ break; -+ case PXP_PIX_FMT_VYUY: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; -+ break; -+ case PXP_PIX_FMT_NV12: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; -+ break; -+ case PXP_PIX_FMT_NV21: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; -+ break; -+ case PXP_PIX_FMT_NV16: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; -+ break; -+ case PXP_PIX_FMT_NV61: -+ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; -+ break; -+ default: -+ pr_debug("OUT doesn't support this format\n"); -+ fmt_ctrl = 0; -+ } -+ -+ return fmt_ctrl; -+} -+ -+static void set_mux(struct mux_config *path_ctrl) -+{ -+ struct mux_config *mux = path_ctrl; -+ -+ *(uint32_t *)path_ctrl = 0xFFFFFFFF; -+ -+ mux->mux0_sel = 0; -+ mux->mux3_sel = 1; -+ mux->mux6_sel = 1; -+ mux->mux8_sel = 0; -+ mux->mux9_sel = 1; -+ mux->mux11_sel = 0; -+ mux->mux12_sel = 1; -+ mux->mux14_sel = 0; -+} -+ -+static void set_mux_val(struct mux_config *muxes, -+ uint32_t mux_id, -+ uint32_t mux_val) -+{ -+ BUG_ON(!muxes); -+ BUG_ON(mux_id > 15); -+ -+ switch (mux_id) { -+ case 0: -+ muxes->mux0_sel = mux_val; -+ break; -+ case 1: -+ muxes->mux1_sel = mux_val; -+ break; -+ case 2: -+ muxes->mux2_sel = mux_val; -+ break; -+ case 3: -+ muxes->mux3_sel = mux_val; -+ break; -+ case 4: -+ muxes->mux4_sel = mux_val; -+ break; -+ case 5: -+ muxes->mux5_sel = mux_val; -+ break; -+ case 6: -+ muxes->mux6_sel = mux_val; -+ break; -+ case 7: -+ muxes->mux7_sel = mux_val; -+ break; -+ case 8: -+ muxes->mux8_sel = mux_val; -+ break; -+ case 9: -+ muxes->mux9_sel = mux_val; -+ break; -+ case 10: -+ muxes->mux10_sel = mux_val; -+ break; -+ case 11: -+ muxes->mux11_sel = mux_val; -+ break; -+ case 12: -+ muxes->mux12_sel = mux_val; -+ break; -+ case 13: -+ muxes->mux13_sel = mux_val; -+ break; -+ case 14: -+ muxes->mux14_sel = mux_val; -+ break; -+ case 15: -+ muxes->mux15_sel = mux_val; -+ break; -+ default: -+ break; -+ } -+} -+ -+static uint32_t get_mux_val(struct mux_config *muxes, -+ uint32_t mux_id) -+{ -+ BUG_ON(!muxes); -+ BUG_ON(mux_id > 15); -+ -+ switch (mux_id) { -+ case 0: -+ return muxes->mux0_sel; -+ case 1: -+ return muxes->mux1_sel; -+ case 2: -+ return muxes->mux2_sel; -+ case 3: -+ return muxes->mux3_sel; -+ case 4: -+ return muxes->mux4_sel; -+ case 5: -+ return muxes->mux5_sel; -+ case 6: -+ return muxes->mux6_sel; -+ case 7: -+ return muxes->mux7_sel; -+ case 8: -+ return muxes->mux8_sel; -+ case 9: -+ return muxes->mux9_sel; -+ case 10: -+ return muxes->mux10_sel; -+ case 11: -+ return muxes->mux11_sel; -+ case 12: -+ return muxes->mux12_sel; -+ case 13: -+ return muxes->mux13_sel; -+ case 14: -+ return muxes->mux14_sel; -+ case 15: -+ return muxes->mux15_sel; -+ default: -+ return -EINVAL; -+ } -+} -+ -+static uint32_t pxp_store_ctrl_config(struct pxp_pixmap *out, uint8_t mode, -+ uint8_t fill_en, uint8_t combine_2ch) -+{ -+ struct store_ctrl ctrl; -+ uint8_t output_active_bpp; -+ -+ memset((void*)&ctrl, 0x0, sizeof(ctrl)); -+ -+ if (combine_2ch) { -+ ctrl.combine_2channel = 1; -+ if (out) { -+ output_active_bpp = active_bpp(out->bpp); -+ ctrl.pack_in_sel = (output_active_bpp < 0x3) ? 1 : 0; -+ ctrl.store_memory_en = 1; -+ } -+ } else { -+ if (fill_en) { -+ ctrl.fill_data_en = 1; -+ ctrl.wr_num_bytes = 2; -+ } -+ ctrl.store_memory_en = 1; -+ } -+ -+ if (out && (out->rotate || out->flip)) -+ ctrl.block_en = 1; -+ -+ ctrl.ch_en = 1; -+ -+ return *(uint32_t *)&ctrl; -+} -+ -+static uint32_t pxp_store_size_config(struct pxp_pixmap *out) -+{ -+ struct store_size size; -+ -+ memset((void*)&size, 0x0, sizeof(size)); -+ -+ size.out_height = out->height - 1; -+ size.out_width = out->width - 1; -+ -+ return *(uint32_t *)&size; -+} -+ -+static uint32_t pxp_store_pitch_config(struct pxp_pixmap *out0, -+ struct pxp_pixmap *out1) -+{ -+ struct store_pitch pitch; -+ -+ memset((void*)&pitch, 0x0, sizeof(pitch)); -+ -+ pitch.ch0_out_pitch = out0->pitch; -+ pitch.ch1_out_pitch = out1 ? out1->pitch : 0; -+ -+ return *(uint32_t *)&pitch; -+} -+ -+static struct color *pxp_find_rgb_color(uint32_t format) -+{ -+ int i; -+ -+ for (i = 0; i < sizeof(rgb_colors) / sizeof(struct color); i++) { -+ if (rgb_colors[i].format == format) -+ return &rgb_colors[i]; -+ } -+ -+ return NULL; -+} -+ -+static struct color_component *pxp_find_comp(struct color *color, uint8_t id) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ if (id == color->comp[i].id) -+ return &color->comp[i]; -+ } -+ -+ return NULL; -+} -+ -+static struct color *pxp_find_yuv_color(uint32_t format) -+{ -+ int i; -+ -+ for (i = 0; i < sizeof(yuv_colors) / sizeof(struct color); i++) { -+ if (yuv_colors[i].format == format) -+ return &yuv_colors[i]; -+ } -+ -+ return NULL; -+} -+ -+static uint64_t pxp_store_d_shift_calc(uint32_t in_fmt, uint32_t out_fmt, -+ struct store_d_mask *d_mask) -+{ -+ int i, shift_width, shift_flag, drop = 0; -+ struct store_d_shift d_shift; -+ struct color *input_color, *output_color; -+ struct color_component *input_comp, *output_comp; -+ -+ BUG_ON((in_fmt == out_fmt)); -+ memset((void*)&d_shift, 0x0, sizeof(d_shift)); -+ memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); -+ -+ if (!is_yuv(in_fmt)) { -+ input_color = pxp_find_rgb_color(in_fmt); -+ output_color = pxp_find_rgb_color(out_fmt); -+ } else { -+ input_color = pxp_find_yuv_color(in_fmt); -+ output_color = pxp_find_yuv_color(out_fmt); -+ } -+ -+ for (i = 0; i < 4; i++) { -+ input_comp = &input_color->comp[i]; -+ if (!input_comp->length) -+ continue; -+ -+ output_comp = pxp_find_comp(output_color, input_comp->id); -+ if (!output_comp->length) -+ continue; -+ -+ /* only rgb format can drop color bits */ -+ if (input_comp->length > output_comp->length) { -+ drop = input_comp->length - output_comp->length; -+ input_comp->offset += drop; -+ } -+ d_mask[i].d_mask_l = output_comp->mask << input_comp->offset; -+ -+ shift_width = input_comp->offset - output_comp->offset; -+ if (shift_width > 0) -+ shift_flag = 0; /* right shift */ -+ else if (shift_width < 0) { -+ shift_flag = 1; /* left shift */ -+ shift_width = -shift_width; -+ } else -+ shift_width = shift_flag = 0; /* no shift require */ -+ -+ switch (i) { -+ case 0: -+ d_shift.d_shift_width0 = shift_width; -+ d_shift.d_shift_flag0 = shift_flag; -+ break; -+ case 1: -+ d_shift.d_shift_width1 = shift_width; -+ d_shift.d_shift_flag1 = shift_flag; -+ break; -+ case 2: -+ d_shift.d_shift_width2 = shift_width; -+ d_shift.d_shift_flag2 = shift_flag; -+ break; -+ case 3: -+ d_shift.d_shift_width3 = shift_width; -+ d_shift.d_shift_flag3 = shift_flag; -+ break; -+ default: -+ printk(KERN_ERR "unsupport d shift\n"); -+ break; -+ } -+ -+ input_comp->offset -= drop; -+ } -+ -+ return *(uint64_t *)&d_shift; -+} -+ -+static uint32_t pxp_store_shift_ctrl_config(struct pxp_pixmap *out, -+ uint8_t shift_bypass) -+{ -+ struct store_shift_ctrl shift_ctrl; -+ -+ memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); -+ -+ shift_ctrl.output_active_bpp = active_bpp(out->bpp); -+ /* Not general data */ -+ if (!shift_bypass) { -+ switch(out->format) { -+ case PXP_PIX_FMT_YUYV: -+ shift_bypass = 1; -+ fallthrough; -+ case PXP_PIX_FMT_YVYU: -+ shift_ctrl.out_yuv422_1p_en = 1; -+ break; -+ case PXP_PIX_FMT_NV16: -+ shift_bypass = 1; -+ fallthrough; -+ case PXP_PIX_FMT_NV61: -+ shift_ctrl.out_yuv422_2p_en = 1; -+ break; -+ default: -+ break; -+ } -+ } -+ shift_ctrl.shift_bypass = shift_bypass; -+ -+ return *(uint32_t *)&shift_ctrl; -+} -+ -+static uint32_t pxp_fetch_ctrl_config(struct pxp_pixmap *in, -+ uint8_t mode) -+{ -+ struct fetch_ctrl ctrl; -+ -+ memset((void*)&ctrl, 0x0, sizeof(ctrl)); -+ -+ if (mode == FETCH_MODE_NORMAL) -+ ctrl.bypass_pixel_en = 0; -+ -+ if (in->flip == PXP_H_FLIP) -+ ctrl.hflip = 1; -+ else if (in->flip == PXP_V_FLIP) -+ ctrl.vflip = 1; -+ -+ ctrl.rotation_angle = rotate_map(in->rotate); -+ -+ if (in->rotate || in->flip) -+ ctrl.block_en = 1; -+ -+ ctrl.ch_en = 1; -+ -+ return *(uint32_t *)&ctrl; -+} -+ -+static uint32_t pxp_fetch_active_size_ulc(struct pxp_pixmap *in) -+{ -+ struct fetch_active_size_ulc size_ulc; -+ -+ memset((void*)&size_ulc, 0x0, sizeof(size_ulc)); -+ -+ size_ulc.active_size_ulc_x = 0; -+ size_ulc.active_size_ulc_y = 0; -+ -+ return *(uint32_t *)&size_ulc; -+} -+ -+static uint32_t pxp_fetch_active_size_lrc(struct pxp_pixmap *in) -+{ -+ struct fetch_active_size_lrc size_lrc; -+ -+ memset((void*)&size_lrc, 0x0, sizeof(size_lrc)); -+ -+ size_lrc.active_size_lrc_x = in->crop.width - 1; -+ size_lrc.active_size_lrc_y = in->crop.height - 1; -+ -+ return *(uint32_t *)&size_lrc; -+} -+ -+static uint32_t pxp_fetch_pitch_config(struct pxp_pixmap *in0, -+ struct pxp_pixmap *in1) -+{ -+ struct fetch_pitch pitch; -+ -+ memset((void*)&pitch, 0x0, sizeof(pitch)); -+ -+ if (in0) -+ pitch.ch0_input_pitch = in0->pitch; -+ if (in1) -+ pitch.ch1_input_pitch = in1->pitch; -+ -+ return *(uint32_t *)&pitch; -+} -+ -+static uint32_t pxp_fetch_shift_ctrl_config(struct pxp_pixmap *in, -+ uint8_t shift_bypass, -+ uint8_t need_expand) -+{ -+ uint8_t input_expand_format; -+ struct fetch_shift_ctrl shift_ctrl; -+ -+ memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); -+ -+ shift_ctrl.input_active_bpp = active_bpp(in->bpp); -+ shift_ctrl.shift_bypass = shift_bypass; -+ -+ if (in->bpp == 32) -+ need_expand = 0; -+ -+ if (need_expand) { -+ input_expand_format = expand_format(in->format); -+ -+ if (input_expand_format <= 0x7) { -+ shift_ctrl.expand_en = 1; -+ shift_ctrl.expand_format = input_expand_format; -+ } -+ } -+ -+ return *(uint32_t *)&shift_ctrl; -+} -+ -+static uint32_t pxp_fetch_shift_calc(uint32_t in_fmt, uint32_t out_fmt, -+ struct fetch_shift_width *shift_width) -+{ -+ int i; -+ struct fetch_shift_offset shift_offset; -+ struct color *input_color, *output_color; -+ struct color_component *input_comp, *output_comp; -+ -+ memset((void*)&shift_offset, 0x0, sizeof(shift_offset)); -+ memset((void*)shift_width, 0x0, sizeof(*shift_width)); -+ -+ if (!is_yuv(in_fmt)) { -+ input_color = pxp_find_rgb_color(in_fmt); -+ output_color = pxp_find_rgb_color(out_fmt); -+ } else { -+ input_color = pxp_find_yuv_color(in_fmt); -+ output_color = pxp_find_yuv_color(out_fmt); -+ } -+ -+ for(i = 0; i < 4; i++) { -+ output_comp = &output_color->comp[i]; -+ if (!output_comp->length) -+ continue; -+ -+ input_comp = pxp_find_comp(input_color, output_comp->id); -+ switch (i) { -+ case 0: -+ shift_offset.offset0 = input_comp->offset; -+ shift_width->width0 = input_comp->length; -+ break; -+ case 1: -+ shift_offset.offset1 = input_comp->offset; -+ shift_width->width1 = input_comp->length; -+ break; -+ case 2: -+ shift_offset.offset2 = input_comp->offset; -+ shift_width->width2 = input_comp->length; -+ break; -+ case 3: -+ shift_offset.offset3 = input_comp->offset; -+ shift_width->width3 = input_comp->length; -+ break; -+ } -+ } -+ -+ return *(uint32_t *)&shift_offset; -+} -+ -+static int pxp_start(struct pxps *pxp) -+{ -+ __raw_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE | -+ BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT | -+ BM_PXP_CTRL_ENABLE_PS_AS_OUT | BM_PXP_CTRL_ENABLE_ROTATE0, -+ pxp->base + HW_PXP_CTRL_SET); -+ dump_pxp_reg(pxp); -+ -+ return 0; -+} -+ -+static bool fmt_ps_support(uint32_t format) -+{ -+ switch (format) { -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_ARGB32: -+ case PXP_PIX_FMT_RGB555: -+ case PXP_PIX_FMT_XRGB555: -+ case PXP_PIX_FMT_ARGB555: -+ case PXP_PIX_FMT_RGB444: -+ case PXP_PIX_FMT_XRGB444: -+ case PXP_PIX_FMT_ARGB444: -+ case PXP_PIX_FMT_RGB565: -+ case PXP_PIX_FMT_YUV444: -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_VUY444: -+ /* need word byte swap */ -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_VYUY: -+ /* need word byte swap */ -+ case PXP_PIX_FMT_YVYU: -+ case PXP_PIX_FMT_GREY: -+ case PXP_PIX_FMT_GY04: -+ case PXP_PIX_FMT_NV16: -+ case PXP_PIX_FMT_NV12: -+ case PXP_PIX_FMT_NV61: -+ case PXP_PIX_FMT_NV21: -+ case PXP_PIX_FMT_YUV422P: -+ case PXP_PIX_FMT_YUV420P: -+ case PXP_PIX_FMT_YVU420P: -+ case PXP_PIX_FMT_RGBA32: -+ case PXP_PIX_FMT_RGBX32: -+ case PXP_PIX_FMT_RGBA555: -+ case PXP_PIX_FMT_RGBA444: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool fmt_as_support(uint32_t format) -+{ -+ switch (format) { -+ case PXP_PIX_FMT_ARGB32: -+ case PXP_PIX_FMT_RGBA32: -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_ARGB555: -+ case PXP_PIX_FMT_ARGB444: -+ case PXP_PIX_FMT_RGBA555: -+ case PXP_PIX_FMT_RGBA444: -+ case PXP_PIX_FMT_RGB555: -+ case PXP_PIX_FMT_RGB444: -+ case PXP_PIX_FMT_RGB565: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool fmt_out_support(uint32_t format) -+{ -+ switch (format) { -+ case PXP_PIX_FMT_ARGB32: -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_RGB24: -+ case PXP_PIX_FMT_ARGB555: -+ case PXP_PIX_FMT_ARGB444: -+ case PXP_PIX_FMT_RGB555: -+ case PXP_PIX_FMT_RGB444: -+ case PXP_PIX_FMT_RGB565: -+ case PXP_PIX_FMT_YUV444: -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_VYUY: -+ case PXP_PIX_FMT_GREY: -+ case PXP_PIX_FMT_GY04: -+ case PXP_PIX_FMT_NV16: -+ case PXP_PIX_FMT_NV12: -+ case PXP_PIX_FMT_NV61: -+ case PXP_PIX_FMT_NV21: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+/* common means 'ARGB32/XRGB32/YUV444' */ -+static uint8_t fmt_fetch_to_common(uint32_t in) -+{ -+ switch (in) { -+ case PXP_PIX_FMT_ARGB32: -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_YUV444: -+ return FETCH_NOOP; -+ -+ case PXP_PIX_FMT_RGB565: -+ case PXP_PIX_FMT_RGB555: -+ case PXP_PIX_FMT_ARGB555: -+ case PXP_PIX_FMT_RGB444: -+ case PXP_PIX_FMT_ARGB444: -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_UYVY: -+ case PXP_PIX_FMT_NV16: -+ return FETCH_EXPAND; -+ -+ case PXP_PIX_FMT_RGBA32: -+ case PXP_PIX_FMT_RGBX32: -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_BGRX32: -+ case PXP_PIX_FMT_ABGR32: -+ case PXP_PIX_FMT_XBGR32: -+ case PXP_PIX_FMT_YVU444: -+ return FETCH_SHIFT; -+ -+ case PXP_PIX_FMT_BGR565: -+ case PXP_PIX_FMT_YVYU: -+ case PXP_PIX_FMT_VYUY: -+ return FETCH_EXPAND | FETCH_SHIFT; -+ -+ default: -+ return 0; -+ } -+} -+ -+static uint8_t fmt_store_from_common(uint32_t out) -+{ -+ switch (out) { -+ case PXP_PIX_FMT_ARGB32: -+ case PXP_PIX_FMT_XRGB32: -+ case PXP_PIX_FMT_YUV444: -+ return STORE_NOOP; -+ -+ case PXP_PIX_FMT_YUYV: -+ case PXP_PIX_FMT_NV16: -+ return STORE_SHRINK; -+ -+ case PXP_PIX_FMT_RGBA32: -+ case PXP_PIX_FMT_RGBX32: -+ case PXP_PIX_FMT_BGRA32: -+ case PXP_PIX_FMT_BGRX32: -+ case PXP_PIX_FMT_ABGR32: -+ case PXP_PIX_FMT_XBGR32: -+ case PXP_PIX_FMT_YVU444: -+ case PXP_PIX_FMT_RGB565: -+ case PXP_PIX_FMT_RGB555: -+ case PXP_PIX_FMT_ARGB555: -+ case PXP_PIX_FMT_RGB444: -+ case PXP_PIX_FMT_ARGB444: -+ case PXP_PIX_FMT_GREY: -+ return STORE_SHIFT; -+ -+ case PXP_PIX_FMT_YVYU: -+ case PXP_PIX_FMT_NV61: -+ return STORE_SHIFT | STORE_SHRINK; -+ -+ default: -+ return 0; -+ } -+} -+ -+static void filter_possible_inputs(struct pxp_pixmap *input, -+ size_t *possible) -+{ -+ uint8_t clear = 0xff; -+ uint8_t position = 0; -+ -+ do { -+ position = find_next_bit((unsigned long *)possible, 32, position); -+ if (position >= sizeof(uint32_t) * 8) -+ break; -+ -+ switch (position) { -+ case PXP_2D_PS: -+ if (!fmt_ps_support(input->format)) -+ clear = PXP_2D_PS; -+ break; -+ case PXP_2D_AS: -+ if (!fmt_as_support(input->format)) -+ clear = PXP_2D_AS; -+ break; -+ case PXP_2D_INPUT_FETCH0: -+ case PXP_2D_INPUT_FETCH1: -+ if ((is_yuv(input->format) == 3)) { -+ clear = position; -+ break; -+ } -+ if ((input->flags & IN_NEED_FMT_UNIFIED) || -+ is_yuv(input->format) == 2) -+ if (!fmt_fetch_to_common(input->format)) -+ clear = position; -+ break; -+ default: -+ pr_err("invalid input node: %d\n", position); -+ clear = position; -+ break; -+ } -+ -+ if (clear != 0xff) { -+ clear_bit(clear, (unsigned long*)possible); -+ clear = 0xff; -+ } -+ -+ position++; -+ } while (1); -+} -+ -+static void filter_possible_outputs(struct pxp_pixmap *output, -+ size_t *possible) -+{ -+ uint8_t clear = 0xff; -+ uint8_t position = 0; -+ -+ do { -+ position = find_next_bit((unsigned long *)possible, 32, position); -+ if (position >= sizeof(uint32_t) * 8) -+ break; -+ -+ switch (position) { -+ case PXP_2D_OUT: -+ if (!fmt_out_support(output->format)) -+ clear = PXP_2D_OUT; -+ break; -+ case PXP_2D_INPUT_STORE0: -+ case PXP_2D_INPUT_STORE1: -+ if (output->flags) { -+ if (!fmt_store_from_common(output->format)) -+ clear = position; -+ } -+ break; -+ default: -+ pr_err("invalid output node: %d\n", position); -+ clear = position; -+ break; -+ } -+ -+ if (clear != 0xff) { -+ clear_bit(clear, (unsigned long*)possible); -+ clear = 0xff; -+ } -+ -+ position++; -+ } while (1); -+} -+ -+static uint32_t calc_shortest_path(size_t *nodes_used) -+{ -+ uint32_t distance = 0; -+ uint32_t from = 0, to = 0, bypass, end; -+ -+ do { -+ from = find_next_bit((unsigned long *)nodes_used, 32, from); -+ if (from >= sizeof(uint32_t) * 8) -+ break; -+ -+ if (to != 0) { -+ if (path_table[to][from].distance == DISTANCE_INFINITY) -+ return DISTANCE_INFINITY; -+ -+ distance += path_table[to][from].distance; -+ /* backtrace */ -+ end = from; -+ while (1) { -+ bypass = path_table[to][end].prev_node; -+ if (bypass == to) -+ break; -+ set_bit(bypass, (unsigned long*)nodes_used); -+ end = bypass; -+ } -+ } -+ -+ to = find_next_bit((unsigned long *)nodes_used, 32, from + 1); -+ if (to >= sizeof(uint32_t) * 8) -+ break; -+ -+ if (path_table[from][to].distance == DISTANCE_INFINITY) -+ return DISTANCE_INFINITY; -+ -+ distance += path_table[from][to].distance; -+ /* backtrace */ -+ end = to; -+ while (1) { -+ bypass = path_table[from][end].prev_node; -+ if (bypass == from) -+ break; -+ set_bit(bypass, (unsigned long*)nodes_used); -+ end = bypass; -+ } -+ -+ from = to + 1; -+ } while (1); -+ -+ return distance; -+} -+ -+static uint32_t find_best_path(uint32_t inputs, -+ uint32_t outputs, -+ struct pxp_pixmap *in, -+ size_t *nodes_used) -+{ -+ size_t outs; -+ size_t nodes_add, best_nodes_used = 0; -+ uint8_t in_pos = 0, out_pos = 0; -+ size_t nodes_in_path, best_nodes_in_path = 0; -+ uint32_t best_distance = DISTANCE_INFINITY, distance; -+ -+ do { -+ outs = outputs; -+ in_pos = find_next_bit((unsigned long *)&inputs, 32, in_pos); -+ if (in_pos >= sizeof(uint32_t) * 8) -+ break; -+ nodes_add = 0; -+ set_bit(in_pos, (unsigned long *)&nodes_add); -+ -+ switch (in_pos) { -+ case PXP_2D_PS: -+ if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) { -+ if (is_yuv(in->format)) -+ set_bit(PXP_2D_CSC1, -+ (unsigned long *)&nodes_add); -+ else -+ set_bit(PXP_2D_CSC2, -+ (unsigned long *)&nodes_add); -+ } -+ if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) -+ set_bit(PXP_2D_ROTATION1, -+ (unsigned long *)&nodes_add); -+ clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); -+ break; -+ case PXP_2D_AS: -+ if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) -+ set_bit(PXP_2D_CSC2, -+ (unsigned long *)&nodes_add); -+ if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) -+ set_bit(PXP_2D_ROTATION0, -+ (unsigned long *)&nodes_add); -+ clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); -+ break; -+ case PXP_2D_INPUT_FETCH0: -+ case PXP_2D_INPUT_FETCH1: -+ if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) -+ set_bit(PXP_2D_CSC2, -+ (unsigned long *)&nodes_add); -+ clear_bit(PXP_2D_OUT, (unsigned long *)&outs); -+ if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) -+ set_bit(PXP_2D_ROTATION1, -+ (unsigned long *)&nodes_add); -+ break; -+ default: -+ /* alph0_s0/s1, alpha1_s0/s1 */ -+ break; -+ } -+ -+ nodes_add |= *nodes_used; -+ -+ do { -+ out_pos = find_next_bit((unsigned long *)&outs, 32, out_pos); -+ if (out_pos >= sizeof(uint32_t) * 8) -+ break; -+ set_bit(out_pos, (unsigned long *)&nodes_add); -+ -+ switch(out_pos) { -+ case PXP_2D_ALPHA0_S0: -+ case PXP_2D_ALPHA0_S1: -+ case PXP_2D_ALPHA1_S0: -+ case PXP_2D_ALPHA1_S1: -+ clear_bit(PXP_2D_CSC2, (unsigned long *)&nodes_add); -+ clear_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_add); -+ clear_bit(PXP_2D_LUT, (unsigned long *)&nodes_add); -+ break; -+ default: -+ break; -+ } -+ -+ nodes_in_path = nodes_add; -+ distance = calc_shortest_path(&nodes_in_path); -+ if (best_distance > distance) { -+ best_distance = distance; -+ best_nodes_used = nodes_add; -+ best_nodes_in_path = nodes_in_path; -+ } -+ pr_debug("%s: out_pos = %d, nodes_in_path = 0x%x, nodes_add = 0x%x, distance = 0x%x\n", -+ __func__, out_pos, (u32)nodes_in_path, (u32)nodes_add, distance); -+ -+ clear_bit(out_pos, (unsigned long *)&nodes_add); -+ -+ out_pos++; -+ } while (1); -+ -+ in_pos++; -+ } while (1); -+ -+ *nodes_used = best_nodes_used; -+ -+ return best_nodes_in_path; -+} -+ -+static uint32_t ps_calc_scaling(struct pxp_pixmap *input, -+ struct pxp_pixmap *output, -+ struct ps_ctrl *ctrl) -+{ -+ struct ps_scale scale; -+ uint32_t decx, decy; -+ -+ memset((void*)&scale, 0x0, sizeof(scale)); -+ -+ if (!output->crop.width || !output->crop.height) { -+ pr_err("Invalid drect width and height passed in\n"); -+ return 0; -+ } -+ -+ if ((input->rotate == 90) || (input->rotate == 270)) -+ swap(output->crop.width, output->crop.height); -+ -+ decx = input->crop.width / output->crop.width; -+ decy = input->crop.height / output->crop.height; -+ -+ if (decx > 1) { -+ if (decx >= 2 && decx < 4) { -+ decx = 2; -+ ctrl->decx = 1; -+ } else if (decx >= 4 && decx < 8) { -+ decx = 4; -+ ctrl->decx = 2; -+ } else if (decx >= 8) { -+ decx = 8; -+ ctrl->decx = 3; -+ } -+ scale.xscale = input->crop.width * 0x1000 / -+ (output->crop.width * decx); -+ -+ /* A factor greater than 2 is not supported -+ * with the bilinear filter, so correct it in -+ * driver -+ */ -+ if (((scale.xscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { -+ scale.xscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); -+ scale.xscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); -+ pr_warn("%s: scale.xscale is larger than 2, forcing to 2" -+ "input w/h=(%d,%d), output w/h=(%d, %d)\n", -+ __func__, input->crop.width, input->crop.height, -+ output->crop.width, output->crop.height); -+ } -+ } else { -+ if (!is_yuv(input->format) || -+ (is_yuv(input->format) == is_yuv(output->format)) || -+ (input->format == PXP_PIX_FMT_GREY) || -+ (input->format == PXP_PIX_FMT_GY04) || -+ (input->format == PXP_PIX_FMT_VUY444)) { -+ if ((input->crop.width > 1) && -+ (output->crop.width > 1)) -+ scale.xscale = (input->crop.width - 1) * 0x1000 / -+ (output->crop.width - 1); -+ else -+ scale.xscale = input->crop.width * 0x1000 / -+ output->crop.width; -+ } else { -+ if ((input->crop.width > 2) && -+ (output->crop.width > 1)) -+ scale.xscale = (input->crop.width - 2) * 0x1000 / -+ (output->crop.width - 1); -+ else -+ scale.xscale = input->crop.width * 0x1000 / -+ output->crop.width; -+ } -+ } -+ -+ if (decy > 1) { -+ if (decy >= 2 && decy < 4) { -+ decy = 2; -+ ctrl->decy = 1; -+ } else if (decy >= 4 && decy < 8) { -+ decy = 4; -+ ctrl->decy = 2; -+ } else if (decy >= 8) { -+ decy = 8; -+ ctrl->decy = 3; -+ } -+ scale.yscale = input->crop.height * 0x1000 / -+ (output->crop.height * decy); -+ -+ /* A factor greater than 2 is not supported -+ * with the bilinear filter, so correct it in -+ * driver -+ */ -+ if (((scale.yscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { -+ scale.yscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); -+ scale.yscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); -+ pr_warn("%s: scale.yscale is larger than 2, forcing to 2" -+ "input w/h=(%d,%d), output w/h=(%d, %d)\n", -+ __func__, input->crop.width, input->crop.height, -+ output->crop.width, output->crop.height); -+ } -+ } else { -+ if ((input->crop.height > 1) && (output->crop.height > 1)) -+ scale.yscale = (input->crop.height - 1) * 0x1000 / -+ (output->crop.height - 1); -+ else -+ scale.yscale = input->crop.height * 0x1000 / -+ output->crop.height; -+ } -+ -+ return *(uint32_t *)&scale; -+} -+ -+static int pxp_ps_config(struct pxp_pixmap *input, -+ struct pxp_pixmap *output) -+{ -+ uint32_t offset, U, V; -+ struct ps_ctrl ctrl; -+ struct coordinate out_ps_ulc, out_ps_lrc; -+ -+ memset((void*)&ctrl, 0x0, sizeof(ctrl)); -+ -+ ctrl.format = pxp_parse_ps_fmt(input->format); -+ -+ switch (output->rotate) { -+ case 0: -+ out_ps_ulc.x = output->crop.x; -+ out_ps_ulc.y = output->crop.y; -+ out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; -+ out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; -+ break; -+ case 90: -+ out_ps_ulc.x = output->crop.y; -+ out_ps_ulc.y = output->width - (output->crop.x + output->crop.width); -+ out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; -+ out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; -+ break; -+ case 180: -+ out_ps_ulc.x = output->width - (output->crop.x + output->crop.width); -+ out_ps_ulc.y = output->height - (output->crop.y + output->crop.height); -+ out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; -+ out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; -+ break; -+ case 270: -+ out_ps_ulc.x = output->height - (output->crop.y + output->crop.height); -+ out_ps_ulc.y = output->crop.x; -+ out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; -+ out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; -+ break; -+ default: -+ pr_err("PxP only support rotate 0 90 180 270\n"); -+ return -EINVAL; -+ break; -+ } -+ -+ if ((input->format == PXP_PIX_FMT_YUYV) || -+ (input->format == PXP_PIX_FMT_YVYU)) -+ ctrl.wb_swap = 1; -+ -+ pxp_writel(ps_calc_scaling(input, output, &ctrl), -+ HW_PXP_PS_SCALE); -+ pxp_writel(*(uint32_t *)&ctrl, HW_PXP_PS_CTRL); -+ -+ offset = input->crop.y * input->pitch + -+ input->crop.x * (input->bpp >> 3); -+ -+ pxp_writel(input->paddr + offset, HW_PXP_PS_BUF); -+ -+ switch (is_yuv(input->format)) { -+ case 0: /* RGB */ -+ case 1: /* 1 Plane YUV */ -+ break; -+ case 2: /* NV16,NV61,NV12,NV21 */ -+ if ((input->format == PXP_PIX_FMT_NV16) || -+ (input->format == PXP_PIX_FMT_NV61)) { -+ U = input->paddr + input->width * input->height; -+ pxp_writel(U + offset, HW_PXP_PS_UBUF); -+ } -+ else { -+ U = input->paddr + input->width * input->height; -+ pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); -+ } -+ break; -+ case 3: /* YUV422P, YUV420P */ -+ if (input->format == PXP_PIX_FMT_YUV422P) { -+ U = input->paddr + input->width * input->height; -+ pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); -+ V = U + (input->width * input->height >> 1); -+ pxp_writel(V + (offset >> 1), HW_PXP_PS_VBUF); -+ } else if (input->format == PXP_PIX_FMT_YUV420P) { -+ U = input->paddr + input->width * input->height; -+ pxp_writel(U + (offset >> 2), HW_PXP_PS_UBUF); -+ V = U + (input->width * input->height >> 2); -+ pxp_writel(V + (offset >> 2), HW_PXP_PS_VBUF); -+ } else if (input->format == PXP_PIX_FMT_YVU420P) { -+ U = input->paddr + input->width * input->height; -+ V = U + (input->width * input->height >> 2); -+ pxp_writel(U + (offset >> 2), HW_PXP_PS_VBUF); -+ pxp_writel(V + (offset >> 2), HW_PXP_PS_UBUF); -+ } -+ -+ break; -+ default: -+ break; -+ } -+ -+ pxp_writel(input->pitch, HW_PXP_PS_PITCH); -+ pxp_writel(*(uint32_t *)&out_ps_ulc, HW_PXP_OUT_PS_ULC); -+ pxp_writel(*(uint32_t *)&out_ps_lrc, HW_PXP_OUT_PS_LRC); -+ -+ pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | -+ BF_PXP_CTRL_IRQ_ENABLE(1), -+ HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_as_config(struct pxp_pixmap *input, -+ struct pxp_pixmap *output) -+{ -+ uint32_t offset; -+ struct as_ctrl ctrl; -+ struct coordinate out_as_ulc, out_as_lrc; -+ -+ memset((void*)&ctrl, 0x0, sizeof(ctrl)); -+ -+ ctrl.format = pxp_parse_as_fmt(input->format); -+ -+ if (alpha_blending_version == PXP_ALPHA_BLENDING_V1) { -+ if (input->format == PXP_PIX_FMT_BGRA32) { -+ if (!input->g_alpha.combine_enable) { -+ ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs; -+ ctrl.rop = 0x3; -+ } -+ } -+ -+ if (input->g_alpha.global_alpha_enable) { -+ if (input->g_alpha.global_override) -+ ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Override; -+ else -+ ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply; -+ -+ if (input->g_alpha.alpha_invert) -+ ctrl.alpha0_invert = 0x1; -+ } -+ -+ if (input->g_alpha.color_key_enable) { -+ ctrl.enable_colorkey = 1; -+ } -+ -+ ctrl.alpha = input->g_alpha.global_alpha; -+ } -+ -+ out_as_ulc.x = out_as_ulc.y = 0; -+ if (input->g_alpha.combine_enable) { -+ out_as_lrc.x = input->width - 1; -+ out_as_lrc.y = input->height - 1; -+ } else { -+ out_as_lrc.x = output->crop.width - 1; -+ out_as_lrc.y = output->crop.height - 1; -+ } -+ -+ offset = input->crop.y * input->pitch + -+ input->crop.x * (input->bpp >> 3); -+ pxp_writel(input->paddr + offset, HW_PXP_AS_BUF); -+ -+ pxp_writel(input->pitch, HW_PXP_AS_PITCH); -+ pxp_writel(*(uint32_t *)&out_as_ulc, HW_PXP_OUT_AS_ULC); -+ pxp_writel(*(uint32_t *)&out_as_lrc, HW_PXP_OUT_AS_LRC); -+ -+ pxp_writel(*(uint32_t *)&ctrl, HW_PXP_AS_CTRL); -+ pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | -+ BF_PXP_CTRL_IRQ_ENABLE(1), -+ HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static uint32_t pxp_fetch_size_config(struct pxp_pixmap *input) -+{ -+ struct fetch_size total_size; -+ -+ memset((void*)&total_size, 0x0, sizeof(total_size)); -+ -+ total_size.input_total_width = input->width - 1; -+ total_size.input_total_height = input->height - 1; -+ -+ return *(uint32_t *)&total_size; -+} -+ -+static int pxp_fetch_config(struct pxp_pixmap *input, -+ uint32_t fetch_index) -+{ -+ uint8_t shift_bypass = 1, expand_en = 0; -+ uint32_t flags, pitch = 0, offset, UV = 0; -+ uint32_t in_fmt, out_fmt; -+ uint32_t size_ulc, size_lrc; -+ uint32_t fetch_ctrl, total_size; -+ uint32_t shift_ctrl, shift_offset = 0; -+ struct fetch_shift_width shift_width; -+ -+ memset((unsigned int *)&shift_width, 0x0, sizeof(shift_width)); -+ fetch_ctrl = pxp_fetch_ctrl_config(input, FETCH_MODE_NORMAL); -+ size_ulc = pxp_fetch_active_size_ulc(input); -+ size_lrc = pxp_fetch_active_size_lrc(input); -+ total_size = pxp_fetch_size_config(input); -+ -+ if (input->flags) { -+ flags = fmt_fetch_to_common(input->format); -+ shift_bypass = (flags & FETCH_SHIFT) ? 0 : 1; -+ expand_en = (flags & FETCH_EXPAND) ? 1 : 0; -+ -+ if (!shift_bypass) { -+ if (expand_en) { -+ if (is_yuv(input->format)) { -+ in_fmt = PXP_PIX_FMT_YVU444; -+ out_fmt = PXP_PIX_FMT_YUV444; -+ } else { -+ in_fmt = PXP_PIX_FMT_ABGR32; -+ out_fmt = PXP_PIX_FMT_ARGB32; -+ } -+ } else { -+ in_fmt = input->format; -+ out_fmt = is_yuv(input->format) ? -+ PXP_PIX_FMT_YUV444 : -+ PXP_PIX_FMT_ARGB32; -+ } -+ -+ shift_offset = pxp_fetch_shift_calc(in_fmt, out_fmt, -+ &shift_width); -+ } -+ } -+ shift_ctrl = pxp_fetch_shift_ctrl_config(input, shift_bypass, expand_en); -+ -+ offset = input->crop.y * input->pitch + -+ input->crop.x * (input->bpp >> 3); -+ if (is_yuv(input->format) == 2) -+ UV = input->paddr + input->width * input->height; -+ -+ switch (fetch_index) { -+ case PXP_2D_INPUT_FETCH0: -+ pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); -+ pitch |= pxp_fetch_pitch_config(input, NULL); -+ pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH0); -+ pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); -+ pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); -+ pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH0); -+ pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); -+ pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH0); -+ if (UV) -+ pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH0); -+ pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); -+ if (shift_offset) -+ pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0); -+ pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0); -+ break; -+ case PXP_2D_INPUT_FETCH1: -+ pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); -+ pitch |= pxp_fetch_pitch_config(NULL, input); -+ pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH1); -+ pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1); -+ pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1); -+ pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH1); -+ pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); -+ pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH1); -+ if (UV) -+ pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH1); -+ pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); -+ if (shift_offset) -+ pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1); -+ pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1); -+ break; -+ default: -+ break; -+ } -+ -+ pxp_writel(pitch, HW_PXP_INPUT_FETCH_PITCH); -+ pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_csc1_config(struct pxp_pixmap *input, -+ bool is_ycbcr) -+{ -+ BUG_ON(!is_yuv(input->format)); -+ -+ if (!is_ycbcr) { -+ /* YUV -> RGB */ -+ pxp_writel(0x04030000, HW_PXP_CSC1_COEF0); -+ pxp_writel(0x01230208, HW_PXP_CSC1_COEF1); -+ pxp_writel(0x076b079c, HW_PXP_CSC1_COEF2); -+ -+ return 0; -+ } -+ -+ /* YCbCr -> RGB */ -+ pxp_writel(0x84ab01f0, HW_PXP_CSC1_COEF0); -+ pxp_writel(0x01980204, HW_PXP_CSC1_COEF1); -+ pxp_writel(0x0730079c, HW_PXP_CSC1_COEF2); -+ -+ return 0; -+} -+ -+static int pxp_rotation1_config(struct pxp_pixmap *input) -+{ -+ uint8_t rotate; -+ -+ if (input->flip == PXP_H_FLIP) -+ pxp_writel(BF_PXP_CTRL_HFLIP1(1), HW_PXP_CTRL_SET); -+ else if (input->flip == PXP_V_FLIP) -+ pxp_writel(BF_PXP_CTRL_VFLIP1(1), HW_PXP_CTRL_SET); -+ -+ rotate = rotate_map(input->rotate); -+ pxp_writel(BF_PXP_CTRL_ROTATE1(rotate), HW_PXP_CTRL_SET); -+ -+ pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE1(1), HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_rotation0_config(struct pxp_pixmap *input) -+{ -+ uint8_t rotate; -+ -+ if (input->flip == PXP_H_FLIP) -+ pxp_writel(BF_PXP_CTRL_HFLIP0(1), HW_PXP_CTRL_SET); -+ else if (input->flip == PXP_V_FLIP) -+ pxp_writel(BF_PXP_CTRL_VFLIP0(1), HW_PXP_CTRL_SET); -+ -+ rotate = rotate_map(input->rotate); -+ pxp_writel(BF_PXP_CTRL_ROTATE0(rotate), HW_PXP_CTRL_SET); -+ -+ pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE0(1), HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_csc2_config(struct pxp_pixmap *output) -+{ -+ if (is_yuv(output->format)) { -+ /* RGB -> YUV */ -+ pxp_writel(0x4, HW_PXP_CSC2_CTRL); -+ pxp_writel(0x0096004D, HW_PXP_CSC2_COEF0); -+ pxp_writel(0x05DA001D, HW_PXP_CSC2_COEF1); -+ pxp_writel(0x007005B6, HW_PXP_CSC2_COEF2); -+ pxp_writel(0x057C009E, HW_PXP_CSC2_COEF3); -+ pxp_writel(0x000005E6, HW_PXP_CSC2_COEF4); -+ pxp_writel(0x00000000, HW_PXP_CSC2_COEF5); -+ } -+ -+ pxp_writel(BF_PXP_CTRL_ENABLE_CSC2(1), HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_out_config(struct pxp_pixmap *output) -+{ -+ uint32_t offset, UV; -+ struct out_ctrl ctrl; -+ struct coordinate out_lrc; -+ -+ memset((void*)&ctrl, 0x0, sizeof(ctrl)); -+ -+ ctrl.format = pxp_parse_out_fmt(output->format); -+ offset = output->crop.y * output->pitch + -+ output->crop.x * (output->bpp >> 3); -+ -+ pxp_writel(*(uint32_t *)&ctrl, HW_PXP_OUT_CTRL); -+ -+ pxp_writel(output->paddr, HW_PXP_OUT_BUF); -+ if (is_yuv(output->format) == 2) { -+ UV = output->paddr + output->width * output->height; -+ if ((output->format == PXP_PIX_FMT_NV16) || -+ (output->format == PXP_PIX_FMT_NV61)) -+ pxp_writel(UV + offset, HW_PXP_OUT_BUF2); -+ else -+ pxp_writel(UV + (offset >> 1), HW_PXP_OUT_BUF2); -+ } -+ -+ if (output->rotate == 90 || output->rotate == 270) { -+ out_lrc.y = output->width - 1; -+ out_lrc.x = output->height - 1; -+ } else { -+ out_lrc.x = output->width - 1; -+ out_lrc.y = output->height - 1; -+ } -+ -+ pxp_writel(*(uint32_t *)&out_lrc, HW_PXP_OUT_LRC); -+ -+ pxp_writel(output->pitch, HW_PXP_OUT_PITCH); -+ -+ /* set global alpha if necessary */ -+ if (output->g_alpha.global_alpha_enable) { -+ pxp_writel(output->g_alpha.global_alpha << 24, HW_PXP_OUT_CTRL_SET); -+ pxp_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, HW_PXP_OUT_CTRL_SET); -+ } -+ -+ pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | -+ BF_PXP_CTRL_IRQ_ENABLE(1), -+ HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_store_config(struct pxp_pixmap *output, -+ struct pxp_op_info *op) -+{ -+ uint8_t combine_2ch, flags; -+ uint32_t in_fmt, out_fmt, offset, UV = 0; -+ uint64_t d_shift = 0; -+ struct store_d_mask d_mask[8]; -+ uint32_t store_ctrl, store_size, store_pitch, shift_ctrl; -+ -+ memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); -+ combine_2ch = (output->bpp == 64) ? 1 : 0; -+ store_ctrl = pxp_store_ctrl_config(output, STORE_MODE_NORMAL, -+ op->fill_en, combine_2ch); -+ store_size = pxp_store_size_config(output); -+ store_pitch = pxp_store_pitch_config(output, NULL); -+ -+ pxp_writel(store_ctrl, HW_PXP_INPUT_STORE_CTRL_CH0); -+ -+ if (output->flags) { -+ flags = fmt_store_from_common(output->format); -+ if (flags == STORE_NOOP) -+ shift_ctrl = pxp_store_shift_ctrl_config(output, 1); -+ else if (flags & STORE_SHIFT) { -+ in_fmt = is_yuv(output->format) ? PXP_PIX_FMT_YUV444 : -+ PXP_PIX_FMT_ARGB32; -+ out_fmt = (flags & STORE_SHRINK) ? PXP_PIX_FMT_YVU444 : -+ output->format; -+ d_shift = pxp_store_d_shift_calc(in_fmt, out_fmt, d_mask); -+ shift_ctrl = pxp_store_shift_ctrl_config(output, 0); -+ } else -+ shift_ctrl = pxp_store_shift_ctrl_config(output, 0); -+ -+ if (flags & STORE_SHIFT) { -+ pxp_writel((uint32_t)d_shift, HW_PXP_INPUT_STORE_D_SHIFT_L_CH0); -+ /* TODO use only 4 masks */ -+ pxp_writel(d_mask[0].d_mask_l, HW_PXP_INPUT_STORE_D_MASK0_L_CH0); -+ pxp_writel(d_mask[0].d_mask_h, HW_PXP_INPUT_STORE_D_MASK0_H_CH0); -+ pxp_writel(d_mask[1].d_mask_l, HW_PXP_INPUT_STORE_D_MASK1_L_CH0); -+ pxp_writel(d_mask[1].d_mask_h, HW_PXP_INPUT_STORE_D_MASK1_H_CH0); -+ pxp_writel(d_mask[2].d_mask_l, HW_PXP_INPUT_STORE_D_MASK2_L_CH0); -+ pxp_writel(d_mask[2].d_mask_h, HW_PXP_INPUT_STORE_D_MASK2_H_CH0); -+ pxp_writel(d_mask[3].d_mask_l, HW_PXP_INPUT_STORE_D_MASK3_L_CH0); -+ pxp_writel(d_mask[3].d_mask_h, HW_PXP_INPUT_STORE_D_MASK3_H_CH0); -+ } -+ } else -+ shift_ctrl = pxp_store_shift_ctrl_config(output, 1); -+ -+ pxp_writel(shift_ctrl, HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0); -+ pxp_writel(store_size, HW_PXP_INPUT_STORE_SIZE_CH0); -+ pxp_writel(store_pitch, HW_PXP_INPUT_STORE_PITCH); -+ if (op->fill_en) { -+ uint32_t lrc; -+ -+ lrc = (output->width - 1) | ((output->height - 1) << 16); -+ pxp_writel(op->fill_data, HW_PXP_INPUT_STORE_FILL_DATA_CH0); -+ -+ pxp_writel(0x1, HW_PXP_INPUT_FETCH_CTRL_CH0); -+ pxp_writel(0, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); -+ pxp_writel(lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); -+ } -+ -+ offset = output->crop.y * output->pitch + -+ output->crop.x * (output->bpp >> 3); -+ if (is_yuv(output->format == 2)) { -+ UV = output->paddr + output->width * output->height; -+ pxp_writel(UV + offset, HW_PXP_INPUT_STORE_ADDR_1_CH0); -+ } -+ pxp_writel(output->paddr + offset, HW_PXP_INPUT_STORE_ADDR_0_CH0); -+ -+ pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); -+ -+ return 0; -+} -+ -+static int pxp_alpha_config(struct pxp_op_info *op, -+ uint8_t alpha_node) -+{ -+ uint32_t as_ctrl; -+ struct pxp_alpha_ctrl alpha_ctrl; -+ struct pxp_alpha_info *alpha = &op->alpha_info; -+ struct pxp_alpha *s0_alpha, *s1_alpha; -+ -+ memset((void*)&alpha_ctrl, 0x0, sizeof(alpha_ctrl)); -+ -+ if (alpha_blending_version != PXP_ALPHA_BLENDING_V1) { -+ if (alpha->alpha_mode == ALPHA_MODE_ROP) { -+ switch (alpha_node) { -+ case PXP_2D_ALPHA0_S0: -+ as_ctrl = __raw_readl(pxp_reg_base + HW_PXP_AS_CTRL); -+ as_ctrl |= BF_PXP_AS_CTRL_ALPHA_CTRL(BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); -+ as_ctrl |= BF_PXP_AS_CTRL_ROP(alpha->rop_type); -+ pxp_writel(as_ctrl, HW_PXP_AS_CTRL); -+ break; -+ case PXP_2D_ALPHA1_S0: -+ pxp_writel(BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE | -+ BF_PXP_ALPHA_B_CTRL_1_ROP(alpha->rop_type), -+ HW_PXP_ALPHA_B_CTRL_1); -+ pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+ } -+ -+ s0_alpha = &alpha->s0_alpha; -+ s1_alpha = &alpha->s1_alpha; -+ -+ alpha_ctrl.poter_duff_enable = 1; -+ -+ alpha_ctrl.s0_s1_factor_mode = s1_alpha->factor_mode; -+ alpha_ctrl.s0_global_alpha_mode = s0_alpha->global_alpha_mode; -+ alpha_ctrl.s0_alpha_mode = s0_alpha->alpha_mode; -+ alpha_ctrl.s0_color_mode = s0_alpha->color_mode; -+ -+ alpha_ctrl.s1_s0_factor_mode = s0_alpha->factor_mode; -+ alpha_ctrl.s1_global_alpha_mode = s1_alpha->global_alpha_mode; -+ alpha_ctrl.s1_alpha_mode = s1_alpha->alpha_mode; -+ alpha_ctrl.s1_color_mode = s1_alpha->color_mode; -+ -+ alpha_ctrl.s0_global_alpha = s0_alpha->global_alpha_value; -+ alpha_ctrl.s1_global_alpha = s1_alpha->global_alpha_value; -+ -+ switch (alpha_node) { -+ case PXP_2D_ALPHA0_S0: -+ pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_A_CTRL); -+ break; -+ case PXP_2D_ALPHA1_S0: -+ pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_B_CTRL); -+ pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); -+ break; -+ default: -+ break; -+ } -+ } -+ -+ return 0; -+} -+ -+static void pxp_lut_config(struct pxp_op_info *op) -+{ -+ struct pxp_task_info *task = to_pxp_task_info(op); -+ struct pxps *pxp = to_pxp_from_task(task); -+ struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; -+ int lut_op = proc_data->lut_transform; -+ u32 reg_val; -+ int i; -+ bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; -+ u8 *cmap = proc_data->lut_map; -+ u32 entry_src; -+ u32 pix_val; -+ u8 entry[4]; -+ -+ /* -+ * If LUT already configured as needed, return... -+ * Unless CMAP is needed and it has been updated. -+ */ -+ if ((pxp->lut_state == lut_op) && -+ !(use_cmap && proc_data->lut_map_updated)) -+ return; -+ -+ if (lut_op == PXP_LUT_NONE) { -+ __raw_writel(BM_PXP_LUT_CTRL_BYPASS, -+ pxp->base + HW_PXP_LUT_CTRL); -+ } else if (((lut_op & PXP_LUT_INVERT) != 0) -+ && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { -+ /* Fill out LUT table with inverted monochromized values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) { -+ entry_src = use_cmap ? -+ cmap[pix_val + i] : pix_val + i; -+ entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; -+ } -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } else if ((lut_op & PXP_LUT_INVERT) != 0) { -+ /* Fill out LUT table with 8-bit inverted values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) { -+ entry_src = use_cmap ? -+ cmap[pix_val + i] : pix_val + i; -+ entry[i] = ~entry_src & 0xFF; -+ } -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { -+ /* Fill out LUT table with 8-bit monochromized values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) { -+ entry_src = use_cmap ? -+ cmap[pix_val + i] : pix_val + i; -+ entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; -+ } -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } else if (use_cmap) { -+ /* Fill out LUT table using colormap values */ -+ -+ /* clear bypass bit, set lookup mode & out mode */ -+ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE -+ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | -+ BF_PXP_LUT_CTRL_OUT_MODE -+ (BV_PXP_LUT_CTRL_OUT_MODE__Y8), -+ pxp->base + HW_PXP_LUT_CTRL); -+ -+ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ -+ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); -+ -+ /* LUT address pointer auto-increments after each data write */ -+ for (pix_val = 0; pix_val < 256; pix_val += 4) { -+ for (i = 0; i < 4; i++) -+ entry[i] = cmap[pix_val + i]; -+ reg_val = (entry[3] << 24) | (entry[2] << 16) | -+ (entry[1] << 8) | entry[0]; -+ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); -+ } -+ } -+ -+ pxp_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE_ROTATE0 | -+ BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT, -+ HW_PXP_CTRL_SET); -+ -+ pxp->lut_state = lut_op; -+} -+ -+static int pxp_2d_task_config(struct pxp_pixmap *input, -+ struct pxp_pixmap *output, -+ struct pxp_op_info *op, -+ size_t nodes_used) -+{ -+ uint8_t position = 0; -+ -+ -+ do { -+ position = find_next_bit((unsigned long *)&nodes_used, 32, position); -+ if (position >= sizeof(uint32_t) * 8) -+ break; -+ -+ switch (position) { -+ case PXP_2D_PS: -+ pxp_ps_config(input, output); -+ break; -+ case PXP_2D_AS: -+ pxp_as_config(input, output); -+ break; -+ case PXP_2D_INPUT_FETCH0: -+ case PXP_2D_INPUT_FETCH1: -+ pxp_fetch_config(input, position); -+ break; -+ case PXP_2D_CSC1: -+ pxp_csc1_config(input, true); -+ break; -+ case PXP_2D_ROTATION1: -+ pxp_rotation1_config(input); -+ break; -+ case PXP_2D_ALPHA0_S0: -+ case PXP_2D_ALPHA1_S0: -+ pxp_alpha_config(op, position); -+ break; -+ case PXP_2D_ALPHA0_S1: -+ case PXP_2D_ALPHA1_S1: -+ break; -+ case PXP_2D_CSC2: -+ pxp_csc2_config(output); -+ break; -+ case PXP_2D_LUT: -+ pxp_lut_config(op); -+ break; -+ case PXP_2D_ROTATION0: -+ pxp_rotation0_config(input); -+ break; -+ case PXP_2D_OUT: -+ pxp_out_config(output); -+ break; -+ case PXP_2D_INPUT_STORE0: -+ case PXP_2D_INPUT_STORE1: -+ pxp_store_config(output, op); -+ break; -+ default: -+ break; -+ } -+ -+ position++; -+ } while (1); -+ -+ return 0; -+} -+ -+static void mux_config_helper(struct mux_config *path_ctrl, -+ struct edge_node *enode) -+{ -+ uint32_t mux_val, mux_pos = 0; -+ -+ if (enode->mux_used) { -+ do { -+ mux_pos = find_next_bit((unsigned long *)&enode->mux_used, -+ 32, mux_pos); -+ if (mux_pos >= 16) -+ break; -+ -+ mux_val = get_mux_val(&enode->muxes, mux_pos); -+ pr_debug("%s: mux_pos = %d, mux_val = %d\n", -+ __func__, mux_pos, mux_val); -+ set_mux_val(path_ctrl, mux_pos, mux_val); -+ -+ mux_pos++; -+ } while (1); -+ } -+} -+ -+static void pxp_2d_calc_mux(uint32_t nodes, struct mux_config *path_ctrl) -+{ -+ struct edge_node *enode; -+ uint8_t from = 0, to = 0; -+ -+ do { -+ from = find_next_bit((unsigned long *)&nodes, 32, from); -+ if (from >= sizeof(uint32_t) * 8) -+ break; -+ -+ if (to != 0) { -+ enode = adj_list[to].first; -+ while (enode) { -+ if (enode->adjvex == from) { -+ mux_config_helper(path_ctrl, enode); -+ break; -+ } -+ enode = enode->next; -+ } -+ } -+ -+ to = find_next_bit((unsigned long *)&nodes, 32, from + 1); -+ if (to >= sizeof(uint32_t) * 8) -+ break; -+ -+ enode = adj_list[from].first; -+ while (enode) { -+ if (enode->adjvex == to) { -+ mux_config_helper(path_ctrl, enode); -+ break; -+ } -+ enode = enode->next; -+ } -+ -+ from = to + 1; -+ } while (1); -+} -+ -+static int pxp_2d_op_handler(struct pxps *pxp) -+{ -+ struct mux_config path_ctrl0; -+ struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; -+ struct pxp_task_info *task = &pxp->task; -+ struct pxp_op_info *op = &task->op_info; -+ struct pxp_pixmap *input, *output, *input_s0, *input_s1; -+ size_t possible_inputs, possible_outputs; -+ size_t possible_inputs_s0, possible_inputs_s1; -+ size_t inputs_filter_s0, inputs_filter_s1; -+ size_t nodes_used = 0, nodes_in_path; -+ size_t partial_nodes_used = 0; -+ size_t nodes_used_s0 = 0, nodes_used_s1 = 0; -+ size_t nodes_in_path_s0, nodes_in_path_s1; -+ uint32_t val; -+ -+ output = &task->output[0]; -+ if (!output->pitch) -+ return -EINVAL; -+ -+ *(unsigned int*)&path_ctrl0 = 0xffffffff; -+ -+reparse: -+ switch (task->input_num) { -+ case 0: -+ /* Fill operation: use input store engine */ -+ if (is_yuv(output->format) > 1) -+ return -EINVAL; -+ -+ if (output->bpp > 32) -+ return -EINVAL; -+ -+ nodes_used = 1 << PXP_2D_INPUT_STORE0; -+ pxp_2d_task_config(NULL, output, op, nodes_used); -+ break; -+ case 1: -+ /* No Composite */ -+ possible_inputs = (1 << PXP_2D_PS) | -+ (1 << PXP_2D_AS) | -+ (1 << PXP_2D_INPUT_FETCH0); -+ possible_outputs = (1 << PXP_2D_OUT) | -+ (1 << PXP_2D_INPUT_STORE0); -+ -+ input = &task->input[0]; -+ if (!input->pitch) -+ return -EINVAL; -+ -+ if (input->rotate || input->flip) { -+ input->flags |= IN_NEED_ROTATE_FLIP; -+ output->rotate = input->rotate; -+ output->flip = input->flip; -+ } -+ -+ if (!is_yuv(input->format) != !is_yuv(output->format)) -+ input->flags |= IN_NEED_CSC; -+ else if (input->format != output->format) -+ input->flags |= IN_NEED_FMT_UNIFIED; -+ -+ if ((input->rotate == 90) || (input->rotate == 270)) { -+ if ((input->crop.width != output->crop.height) || -+ (input->crop.height != output->crop.width)) -+ input->flags |= IN_NEED_SCALE; -+ } else { -+ if ((input->crop.width != output->crop.width) || -+ (input->crop.height != output->crop.height)) -+ input->flags |= IN_NEED_SCALE; -+ } -+ -+ if (input->flags) { -+ /* only ps has scaling function */ -+ if ((input->flags & IN_NEED_SCALE) == IN_NEED_SCALE) -+ possible_inputs = 1 << PXP_2D_PS; -+ output->flags |= (output->bpp < 32) ? OUT_NEED_SHRINK : -+ OUT_NEED_SHIFT; -+ } -+ -+ filter_possible_inputs(input, &possible_inputs); -+ filter_possible_outputs(output, &possible_outputs); -+ -+ if (!possible_inputs || !possible_outputs) { -+ dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); -+ return -EINVAL; -+ } -+ -+ if (proc_data->lut_transform) -+ nodes_used |= (1 << PXP_2D_LUT); -+ -+ nodes_in_path = find_best_path(possible_inputs, -+ possible_outputs, -+ input, &nodes_used); -+ -+ if (nodes_in_path & (1 << PXP_2D_ROTATION1)) { -+ clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path); -+ set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path); -+ } -+ -+ if (nodes_used & (1 << PXP_2D_ROTATION1)) { -+ clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used); -+ set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used); -+ } -+ -+ pr_debug("%s: nodes_in_path = 0x%x, nodes_used = 0x%x\n", -+ __func__, (u32)nodes_in_path, (u32)nodes_used); -+ if (!nodes_used) { -+ dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); -+ return -EINVAL; -+ } -+ -+ /* If use input fetch0, should use -+ * alpha b instead of alpha a */ -+ if (nodes_in_path & (1 << PXP_2D_ALPHA0_S0)) { -+ if (nodes_in_path & (1 << PXP_2D_INPUT_FETCH0)) { -+ clear_bit(PXP_2D_ALPHA0_S0, -+ (unsigned long *)&nodes_in_path); -+ set_bit(PXP_2D_ALPHA1_S1, -+ (unsigned long *)&nodes_in_path); -+ } -+ } -+ -+ /* In this case input read in -+ * by input fetch engine -+ */ -+ if ((nodes_in_path & (1 << PXP_2D_ALPHA1_S1)) || -+ (nodes_in_path & (1 << PXP_2D_ALPHA1_S0))) { -+ memcpy(&task->input[1], input, sizeof(*input)); -+ if (input->rotate == 90 || input->rotate == 270) { -+ uint32_t temp; -+ -+ input = &task->input[1]; -+ input->rotate = 0; -+ input->flags = 0; -+ temp = input->width; -+ input->width = input->height; -+ input->height = temp; -+ input->pitch = input->width * (input->bpp >> 3); -+ temp = input->crop.width; -+ input->crop.width = input->crop.height; -+ input->crop.height = temp; -+ } -+ -+ op->alpha_info.alpha_mode = ALPHA_MODE_ROP; -+ /* s0 AND s1 */ -+ op->alpha_info.rop_type = 0x0; -+ task->input_num = 2; -+ goto reparse; -+ } -+ -+ pxp_2d_calc_mux(nodes_in_path, &path_ctrl0); -+ pr_debug("%s: path_ctrl0 = 0x%x\n", -+ __func__, *(uint32_t *)&path_ctrl0); -+ pxp_2d_task_config(input, output, op, nodes_used); -+ -+ if (is_yuv(input->format) && is_yuv(output->format)) { -+ val = readl(pxp_reg_base + HW_PXP_CSC1_COEF0); -+ val |= (BF_PXP_CSC1_COEF0_YCBCR_MODE(1) | -+ BF_PXP_CSC1_COEF0_BYPASS(1)); -+ pxp_writel(val, HW_PXP_CSC1_COEF0); -+ } -+ break; -+ case 2: -+ /* Composite */ -+ input_s0 = &task->input[0]; -+ input_s1 = &task->input[1]; -+ if (!input_s0->pitch || !input_s1->pitch) -+ return -EINVAL; -+ -+ possible_inputs_s0 = (1 << PXP_2D_PS) | -+ (1 << PXP_2D_INPUT_FETCH0) | -+ (1 << PXP_2D_INPUT_FETCH1); -+ possible_inputs_s1 = (1 << PXP_2D_AS) | -+ (1 << PXP_2D_INPUT_FETCH0); -+ possible_outputs = (1 << PXP_2D_OUT) | -+ (1 << PXP_2D_INPUT_STORE0); -+ -+ if (input_s0->rotate || input_s0->flip) { -+ input_s0->flags |= IN_NEED_ROTATE_FLIP; -+ output->rotate = input_s0->rotate; -+ output->flip = input_s0->flip; -+ } -+ if (input_s1->rotate || input_s1->flip) { -+ input_s1->flags |= IN_NEED_ROTATE_FLIP; -+ clear_bit(PXP_2D_AS, -+ (unsigned long *)&possible_inputs_s1); -+ } -+ -+ if (is_yuv(input_s0->format) && is_yuv(input_s1->format)) -+ return -EINVAL; -+ -+ if (is_yuv(input_s0->format)){ -+ /* need do yuv -> rgb conversion by csc1 */ -+ possible_inputs_s0 = 1 << PXP_2D_PS; -+ input_s0->flags |= IN_NEED_CSC; -+ } else if (is_yuv(input_s1->format)) { -+ possible_inputs_s1 = 1 << PXP_2D_PS; -+ input_s1->flags |= IN_NEED_CSC; -+ } -+ -+ filter_possible_inputs(input_s0, &possible_inputs_s0); -+ filter_possible_inputs(input_s1, &possible_inputs_s1); -+ -+ if (!possible_inputs_s0 || !possible_inputs_s1) -+ return -EINVAL; -+ -+ filter_possible_outputs(output, &possible_outputs); -+ if (!possible_outputs) -+ return -EINVAL; -+ -+ pr_debug("%s: poss_s0 = 0x%x, poss_s1 = 0x%x, poss_out = 0x%x\n", -+ __func__, (u32)possible_inputs_s0, (u32)possible_inputs_s1, (u32)possible_outputs); -+ -+ inputs_filter_s0 = possible_inputs_s0; -+ inputs_filter_s1 = possible_inputs_s1; -+ -+ /* Using alpha0, possible cases: -+ * 1. PS --> S0, AS --> S1; -+ */ -+ if (possible_inputs_s1 & (1 << PXP_2D_AS)) { -+ clear_bit(PXP_2D_INPUT_FETCH0, -+ (unsigned long *)&possible_inputs_s0); -+ clear_bit(PXP_2D_INPUT_FETCH1, -+ (unsigned long *)&possible_inputs_s0); -+ clear_bit(PXP_2D_INPUT_STORE0, -+ (unsigned long *)&possible_outputs); -+ -+ if (!possible_inputs_s0 || !possible_outputs) -+ goto alpha1; -+ -+ nodes_in_path_s0 = find_best_path(possible_inputs_s0, -+ 1 << PXP_2D_ALPHA0_S0, -+ input_s0, -+ &partial_nodes_used); -+ if (!nodes_in_path_s0) -+ goto alpha1; -+ -+ nodes_used_s0 |= partial_nodes_used; -+ partial_nodes_used = 0; -+ -+ if (is_yuv(output->format)) -+ set_bit(PXP_2D_CSC2, -+ (unsigned long *)&partial_nodes_used); -+ if (output->rotate || output->flip) -+ set_bit(PXP_2D_ROTATION0, -+ (unsigned long *)&partial_nodes_used); -+ -+ nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA0_S0, -+ possible_outputs, -+ input_s0, -+ &partial_nodes_used); -+ if (!(nodes_in_path_s0 & possible_outputs)) -+ goto alpha1; -+ nodes_used_s0 |= partial_nodes_used; -+ -+ possible_inputs_s1 = (1 << PXP_2D_AS); -+ nodes_in_path_s1 = find_best_path(possible_inputs_s1, -+ 1 << PXP_2D_ALPHA0_S1, -+ input_s1, -+ &nodes_used_s1); -+ if (!nodes_in_path_s1) -+ goto alpha1; -+ -+ goto config; -+ } -+alpha1: -+ partial_nodes_used = 0; -+ possible_inputs_s0 = inputs_filter_s0; -+ possible_inputs_s1 = inputs_filter_s1; -+ -+ /* Using alpha1, possible cases: -+ * 1. FETCH1 --> S0, FETCH0 --> S1; -+ */ -+ clear_bit(PXP_2D_PS, -+ (unsigned long *)&possible_inputs_s0); -+ clear_bit(PXP_2D_INPUT_FETCH0, -+ (unsigned long *)&possible_inputs_s0); -+ clear_bit(PXP_2D_OUT, -+ (unsigned long *)&possible_outputs); -+ -+ if (!possible_inputs_s0 || !possible_outputs) -+ return -EINVAL; -+ -+ nodes_in_path_s0 = find_best_path(possible_inputs_s0, -+ 1 << PXP_2D_ALPHA1_S0, -+ input_s0, -+ &partial_nodes_used); -+ pr_debug("%s: nodes_in_path_s0 = 0x%x\n", __func__, (u32)nodes_in_path_s0); -+ BUG_ON(!nodes_in_path_s0); -+ -+ nodes_used_s0 |= partial_nodes_used; -+ if ((nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH0)) || -+ (nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH1))) -+ clear_bit(PXP_2D_OUT, (unsigned long *)&possible_outputs); -+ else -+ clear_bit(PXP_2D_INPUT_STORE0, -+ (unsigned long *)&possible_outputs); -+ partial_nodes_used = 0; -+ -+ if (is_yuv(output->format)) -+ set_bit(PXP_2D_CSC2, -+ (unsigned long *)&partial_nodes_used); -+ if (output->rotate || output->flip) -+ set_bit(PXP_2D_ROTATION0, -+ (unsigned long *)&partial_nodes_used); -+ -+ nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA1_S0, -+ possible_outputs, -+ input_s0, -+ &partial_nodes_used); -+ BUG_ON(!(nodes_in_path_s0 & possible_outputs)); -+ nodes_used_s0 |= partial_nodes_used; -+ pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x\n", -+ __func__, (u32)nodes_in_path_s0, (u32)nodes_used_s0); -+ -+ clear_bit(PXP_2D_AS, -+ (unsigned long *)&possible_inputs_s1); -+ BUG_ON(!possible_inputs_s1); -+ -+ nodes_in_path_s1 = find_best_path(possible_inputs_s1, -+ 1 << PXP_2D_ALPHA1_S1, -+ input_s1, -+ &nodes_used_s1); -+ pr_debug("%s: poss_s1 = 0x%x, nodes_used_s1 = 0x%x\n", -+ __func__, (u32)possible_inputs_s1, (u32)nodes_used_s1); -+ BUG_ON(!nodes_in_path_s1); -+ /* To workaround an IC bug */ -+ path_ctrl0.mux4_sel = 0x0; -+config: -+ if (nodes_in_path_s0 & (1 << PXP_2D_ROTATION1)) { -+ clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path_s0); -+ set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path_s0); -+ } -+ -+ pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x, nodes_in_path_s1 = 0x%x, nodes_used_s1 = 0x%x\n", -+ __func__, (u32)nodes_in_path_s0, (u32)nodes_used_s0, (u32)nodes_in_path_s1, (u32)nodes_used_s1); -+ pxp_2d_calc_mux(nodes_in_path_s0, &path_ctrl0); -+ pxp_2d_calc_mux(nodes_in_path_s1, &path_ctrl0); -+ -+ pr_debug("%s: s0 paddr = 0x%p, s1 paddr = 0x%p, out paddr = 0x%p\n", -+ __func__, (void *)input_s0->paddr, (void *)input_s1->paddr, (void *)output->paddr); -+ -+ if (nodes_used_s0 & (1 << PXP_2D_ROTATION1)) { -+ clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used_s0); -+ set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used_s0); -+ } -+ -+ pxp_2d_task_config(input_s0, output, op, nodes_used_s0); -+ pxp_2d_task_config(input_s1, output, op, nodes_used_s1); -+ break; -+ default: -+ break; -+ } -+ -+ __raw_writel(proc_data->bgcolor, -+ pxp->base + HW_PXP_PS_BACKGROUND_0); -+ pxp_set_colorkey(pxp); -+ -+ if (proc_data->lut_transform && pxp_is_v3(pxp)) -+ set_mux(&path_ctrl0); -+ -+ pr_debug("%s: path_ctrl0 = 0x%x\n", -+ __func__, *(uint32_t *)&path_ctrl0); -+ pxp_writel(*(uint32_t *)&path_ctrl0, HW_PXP_DATA_PATH_CTRL0); -+ -+ return 0; -+} -+ -+/** -+ * pxp_config() - configure PxP for a processing task -+ * @pxps: PXP context. -+ * @pxp_chan: PXP channel. -+ * @return: 0 on success or negative error code on failure. -+ */ -+static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) -+{ -+ int ret = 0; -+ struct pxp_task_info *task = &pxp->task; -+ struct pxp_op_info *op = &task->op_info; -+ struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf_data->proc_data; -+ -+ switch (op->op_type) { -+ case PXP_OP_TYPE_2D: -+ pxp_writel(0xffffffff, HW_PXP_OUT_AS_ULC); -+ pxp_writel(0x0, HW_PXP_OUT_AS_LRC); -+ pxp_writel(0xffffffff, HW_PXP_OUT_PS_ULC); -+ pxp_writel(0x0, HW_PXP_OUT_PS_LRC); -+ pxp_writel(0x0, HW_PXP_INPUT_FETCH_PITCH); -+ pxp_writel(0x40000000, HW_PXP_CSC1_COEF0); -+ ret = pxp_2d_op_handler(pxp); -+ break; -+ case PXP_OP_TYPE_DITHER: -+ pxp_dithering_process(pxp); -+ if (pxp_is_v3p(pxp)) { -+ __raw_writel( -+ BM_PXP_CTRL_ENABLE | -+ BM_PXP_CTRL_ENABLE_DITHER | -+ BM_PXP_CTRL_ENABLE_CSC2 | -+ BM_PXP_CTRL_ENABLE_LUT | -+ BM_PXP_CTRL_ENABLE_ROTATE0 | -+ BM_PXP_CTRL_ENABLE_PS_AS_OUT, -+ pxp->base + HW_PXP_CTRL_SET); -+ return 0; -+ } -+ break; -+ case PXP_OP_TYPE_WFE_A: -+ pxp_luts_deactivate(pxp, proc_data->lut_sels); -+ -+ if (proc_data->lut_cleanup == 0) { -+ /* We should enable histogram in standard mode -+ * in wfe_a processing for waveform mode selection -+ */ -+ pxp_histogram_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, -+ pxp_conf_data->wfe_a_fetch_param[0].height); -+ -+ pxp_luts_activate(pxp, (u64)proc_data->lut_status_1 | -+ ((u64)proc_data->lut_status_2 << 32)); -+ -+ /* collision detection should be always enable in standard mode */ -+ pxp_collision_detection_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, -+ pxp_conf_data->wfe_a_fetch_param[0].height); -+ } -+ -+ if (pxp->devdata && pxp->devdata->pxp_wfe_a_configure) -+ pxp->devdata->pxp_wfe_a_configure(pxp); -+ if (pxp->devdata && pxp->devdata->pxp_wfe_a_process) -+ pxp->devdata->pxp_wfe_a_process(pxp); -+ break; -+ case PXP_OP_TYPE_WFE_B: -+ pxp_wfe_b_configure(pxp); -+ pxp_wfe_b_process(pxp); -+ break; -+ default: -+ /* Unsupport */ -+ ret = -EINVAL; -+ pr_err("Invalid pxp operation type passed\n"); -+ break; -+ } -+ -+ return ret; -+} -+ -+static void pxp_clk_enable(struct pxps *pxp) -+{ -+ mutex_lock(&pxp->clk_mutex); -+ -+ if (pxp->clk_stat == CLK_STAT_ON) { -+ mutex_unlock(&pxp->clk_mutex); -+ return; -+ } -+ -+ pm_runtime_get_sync(pxp->dev); -+ -+ clk_prepare_enable(pxp->ipg_clk); -+ clk_prepare_enable(pxp->axi_clk); -+ -+ if (pxp->devdata && pxp->devdata->pxp_restart) -+ pxp->devdata->pxp_restart(pxp); -+ -+ pxp->clk_stat = CLK_STAT_ON; -+ -+ mutex_unlock(&pxp->clk_mutex); -+} -+ -+static void pxp_clk_disable(struct pxps *pxp) -+{ -+ unsigned long flags; -+ -+ mutex_lock(&pxp->clk_mutex); -+ -+ if (pxp->clk_stat == CLK_STAT_OFF) { -+ mutex_unlock(&pxp->clk_mutex); -+ return; -+ } -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { -+ pxp->clk_stat = CLK_STAT_OFF; -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ clk_disable_unprepare(pxp->ipg_clk); -+ clk_disable_unprepare(pxp->axi_clk); -+ pm_runtime_put_sync_suspend(pxp->dev); -+ } else -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ mutex_unlock(&pxp->clk_mutex); -+} -+ -+static inline void clkoff_callback(struct work_struct *w) -+{ -+ struct pxps *pxp = container_of(w, struct pxps, work); -+ -+ pxp_clk_disable(pxp); -+} -+ -+static void pxp_clkoff_timer(struct timer_list *t) -+{ -+ struct pxps *pxp = from_timer(pxp, t, clk_timer); -+ -+ if ((pxp->pxp_ongoing == 0) && list_empty(&head)) -+ schedule_work(&pxp->work); -+ else -+ mod_timer(&pxp->clk_timer, -+ jiffies + msecs_to_jiffies(timeout_in_ms)); -+} -+ -+static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) -+{ -+ return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); -+} -+ -+static int convert_param_to_pixmap(struct pxp_pixmap *pixmap, -+ struct pxp_layer_param *param) -+{ -+ if (!param->width || !param->height) -+ return -EINVAL; -+ -+ pixmap->width = param->width; -+ pixmap->height = param->height; -+ pixmap->format = param->pixel_fmt; -+ pixmap->paddr = param->paddr; -+ pixmap->bpp = get_bpp_from_fmt(pixmap->format); -+ -+ if (pxp_legacy) { -+ pixmap->pitch = (param->stride) ? (param->stride * pixmap->bpp >> 3) : -+ (param->width * pixmap->bpp >> 3); -+ } else { -+ if (!param->stride || (param->stride == param->width)) -+ pixmap->pitch = param->width * pixmap->bpp >> 3; -+ else -+ pixmap->pitch = param->stride; -+ } -+ -+ pixmap->crop.x = param->crop.left; -+ pixmap->crop.y = param->crop.top; -+ pixmap->crop.width = param->crop.width; -+ pixmap->crop.height = param->crop.height; -+ -+ pixmap->g_alpha.color_key_enable = param->color_key_enable; -+ pixmap->g_alpha.combine_enable = param->combine_enable; -+ pixmap->g_alpha.global_alpha_enable = param->global_alpha_enable; -+ pixmap->g_alpha.global_override = param->global_override; -+ pixmap->g_alpha.global_alpha = param->global_alpha; -+ pixmap->g_alpha.alpha_invert = param->alpha_invert; -+ pixmap->g_alpha.local_alpha_enable = param->local_alpha_enable; -+ pixmap->g_alpha.comp_mask = param->comp_mask; -+ -+ return 0; -+} -+ -+/* called with pxp_chan->lock held */ -+static void __pxpdma_dostart(struct pxp_channel *pxp_chan) -+{ -+ struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); -+ struct pxps *pxp = to_pxp(pxp_dma); -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &config_data->proc_data; -+ struct pxp_tx_desc *desc; -+ struct pxp_tx_desc *child; -+ struct pxp_task_info *task = &pxp->task; -+ struct pxp_op_info *op = &task->op_info; -+ struct pxp_alpha_info *alpha = &op->alpha_info; -+ struct pxp_layer_param *param = NULL; -+ struct pxp_pixmap *input, *output; -+ int i = 0, ret; -+ bool combine_enable = false; -+ int delta_x, delta_y; -+ -+ memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); -+ memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); -+ memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); -+ memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); -+ -+ memset(task, 0, sizeof(*task)); -+ /* S0 */ -+ desc = list_first_entry(&head, struct pxp_tx_desc, list); -+ memcpy(&pxp->pxp_conf_state.s0_param, -+ &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); -+ memcpy(&pxp->pxp_conf_state.proc_data, -+ &desc->proc_data, sizeof(struct pxp_proc_data)); -+ -+ if (proc_data->combine_enable) -+ alpha_blending_version = PXP_ALPHA_BLENDING_V2; -+ else -+ alpha_blending_version = PXP_ALPHA_BLENDING_NONE; -+ -+ pxp_legacy = (proc_data->pxp_legacy) ? true : false; -+ -+ param = &pxp->pxp_conf_state.s0_param; -+ if (param->pixel_fmt == PXP_PIX_FMT_YUV420P || -+ param->pixel_fmt == PXP_PIX_FMT_YVU420P) { -+ delta_x = proc_data->srect.left - ALIGN_DOWN(proc_data->srect.left, 2); -+ delta_y = proc_data->srect.top - ALIGN_DOWN(proc_data->srect.top, 2); -+ -+ proc_data->srect.left = ALIGN_DOWN(proc_data->srect.left, 2); -+ proc_data->srect.top = ALIGN_DOWN(proc_data->srect.top, 2); -+ -+ proc_data->srect.width = proc_data->srect.width + delta_x; -+ proc_data->srect.height = proc_data->srect.height + delta_y; -+ } -+ -+ /* Save PxP configuration */ -+ list_for_each_entry(child, &desc->tx_list, list) { -+ if (i == 0) { /* Output */ -+ memcpy(&pxp->pxp_conf_state.out_param, -+ &child->layer_param.out_param, -+ sizeof(struct pxp_layer_param)); -+ } else if (i == 1) { /* Overlay */ -+ memcpy(&pxp->pxp_conf_state.ol_param[i - 1], -+ &child->layer_param.ol_param, -+ sizeof(struct pxp_layer_param)); -+ if (pxp->pxp_conf_state.ol_param[i - 1].width != 0 && -+ pxp->pxp_conf_state.ol_param[i - 1].height != 0) { -+ if (pxp->pxp_conf_state.ol_param[i - 1].combine_enable) -+ alpha_blending_version = PXP_ALPHA_BLENDING_V1; -+ } -+ } -+ -+ if (proc_data->engine_enable & PXP_ENABLE_DITHER) { -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH0) -+ memcpy(&pxp->pxp_conf_state.dither_fetch_param[0], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH1) -+ memcpy(&pxp->pxp_conf_state.dither_fetch_param[1], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE0) -+ memcpy(&pxp->pxp_conf_state.dither_store_param[0], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE1) -+ memcpy(&pxp->pxp_conf_state.dither_store_param[1], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ op->op_type = PXP_OP_TYPE_DITHER; -+ } -+ -+ if (proc_data->engine_enable & PXP_ENABLE_WFE_A) { -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH0) -+ memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[0], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH1) -+ memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[1], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE0) -+ memcpy(&pxp->pxp_conf_state.wfe_a_store_param[0], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE1) -+ memcpy(&pxp->pxp_conf_state.wfe_a_store_param[1], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ op->op_type = PXP_OP_TYPE_WFE_A; -+ } -+ -+ if (proc_data->engine_enable & PXP_ENABLE_WFE_B) { -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH0) -+ memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[0], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH1) -+ memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[1], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE0) -+ memcpy(&pxp->pxp_conf_state.wfe_b_store_param[0], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE1) -+ memcpy(&pxp->pxp_conf_state.wfe_b_store_param[1], -+ &child->layer_param.processing_param, -+ sizeof(struct pxp_layer_param)); -+ op->op_type = PXP_OP_TYPE_WFE_B; -+ } -+ -+ i++; -+ } -+ -+ if (!op->op_type) { -+ op->op_type = PXP_OP_TYPE_2D; -+ -+ if ((alpha_blending_version == PXP_ALPHA_BLENDING_V1) || -+ (alpha_blending_version == PXP_ALPHA_BLENDING_V2)) -+ combine_enable = true; -+ -+ if (combine_enable) -+ task->input_num = 2; -+ else if (proc_data->fill_en) -+ task->input_num = 0; -+ else -+ task->input_num = 1; -+ -+ output = &task->output[0]; -+ switch (task->input_num) { -+ case 0: -+ op->fill_en = 1; -+ op->fill_data = proc_data->bgcolor; -+ break; -+ case 1: -+ param = &pxp->pxp_conf_state.s0_param; -+ input = &task->input[0]; -+ -+ ret = convert_param_to_pixmap(input, param); -+ if (ret < 0) { -+ param = &pxp->pxp_conf_state.ol_param[0]; -+ ret = convert_param_to_pixmap(input, param); -+ BUG_ON(ret < 0); -+ } else { -+ input->crop.x = proc_data->srect.left; -+ input->crop.y = proc_data->srect.top; -+ input->crop.width = proc_data->srect.width; -+ input->crop.height = proc_data->srect.height; -+ } -+ -+ input->rotate = proc_data->rotate; -+ input->flip = (proc_data->hflip) ? PXP_H_FLIP : -+ (proc_data->vflip) ? PXP_V_FLIP : 0; -+ break; -+ case 2: -+ /* s0 */ -+ param = &pxp->pxp_conf_state.s0_param; -+ input = &task->input[0]; -+ -+ ret = convert_param_to_pixmap(input, param); -+ BUG_ON(ret < 0); -+ input->crop.x = proc_data->srect.left; -+ input->crop.y = proc_data->srect.top; -+ input->crop.width = proc_data->srect.width; -+ input->crop.height = proc_data->srect.height; -+ alpha->s0_alpha = param->alpha; -+ -+ input->rotate = proc_data->rotate; -+ input->flip = (proc_data->hflip) ? PXP_H_FLIP : -+ (proc_data->vflip) ? PXP_V_FLIP : 0; -+ -+ /* overlay */ -+ param = &pxp->pxp_conf_state.ol_param[0]; -+ input = &task->input[1]; -+ -+ ret = convert_param_to_pixmap(input, param); -+ BUG_ON(ret < 0); -+ alpha->s1_alpha = param->alpha; -+ alpha->alpha_mode = proc_data->alpha_mode; -+ break; -+ } -+ -+ param = &pxp->pxp_conf_state.out_param; -+ ret = convert_param_to_pixmap(output, param); -+ BUG_ON(ret < 0); -+ -+ output->crop.x = proc_data->drect.left; -+ output->crop.y = proc_data->drect.top; -+ output->crop.width = proc_data->drect.width; -+ output->crop.height = proc_data->drect.height; -+ } -+ -+ pr_debug("%s:%d S0 w/h %d/%d paddr %p\n", __func__, __LINE__, -+ pxp->pxp_conf_state.s0_param.width, -+ pxp->pxp_conf_state.s0_param.height, -+ (void *)pxp->pxp_conf_state.s0_param.paddr); -+ pr_debug("%s:%d S0 crop (top, left)=(%d, %d), (width, height)=(%d, %d)\n", -+ __func__, __LINE__, -+ pxp->pxp_conf_state.s0_param.crop.top, -+ pxp->pxp_conf_state.s0_param.crop.left, -+ pxp->pxp_conf_state.s0_param.crop.width, -+ pxp->pxp_conf_state.s0_param.crop.height); -+ pr_debug("%s:%d OUT w/h %d/%d paddr %p\n", __func__, __LINE__, -+ pxp->pxp_conf_state.out_param.width, -+ pxp->pxp_conf_state.out_param.height, -+ (void *)pxp->pxp_conf_state.out_param.paddr); -+} -+ -+static int pxpdma_dostart_work(struct pxps *pxp) -+{ -+ int ret; -+ struct pxp_channel *pxp_chan = NULL; -+ unsigned long flags; -+ dma_async_tx_callback callback; -+ void *callback_param; -+ struct pxp_tx_desc *desc = NULL; -+ struct pxp_tx_desc *child, *_child; -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &config_data->proc_data; -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ -+ desc = list_entry(head.next, struct pxp_tx_desc, list); -+ pxp_chan = to_pxp_channel(desc->txd.chan); -+ -+ __pxpdma_dostart(pxp_chan); -+ -+ /* Configure PxP */ -+ ret = pxp_config(pxp, pxp_chan); -+ if (ret) { -+ callback = desc->txd.callback; -+ callback_param = desc->txd.callback_param; -+ -+ callback(callback_param); -+ -+ /* Unsupport operation */ -+ list_for_each_entry_safe(child, _child, &desc->tx_list, list) { -+ list_del_init(&child->list); -+ kmem_cache_free(tx_desc_cache, (void *)child); -+ } -+ list_del_init(&desc->list); -+ kmem_cache_free(tx_desc_cache, (void *)desc); -+ -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ return -EINVAL; -+ } -+ -+ if (proc_data->working_mode & PXP_MODE_STANDARD) { -+ if(!pxp_is_v3p(pxp) || !(proc_data->engine_enable & PXP_ENABLE_DITHER)) -+ pxp_start2(pxp); -+ } else -+ pxp_start(pxp); -+ -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ return 0; -+} -+ -+static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) -+{ -+ unsigned long flags; -+ struct pxp_tx_desc *desc = NULL; -+ -+ do { -+ desc = pxpdma_first_queued(pxp_chan); -+ spin_lock_irqsave(&pxp->lock, flags); -+ list_move_tail(&desc->list, &head); -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ } while (!list_empty(&pxp_chan->queue)); -+} -+ -+static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) -+{ -+ struct pxp_tx_desc *desc = to_tx_desc(tx); -+ struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); -+ dma_cookie_t cookie; -+ -+ dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); -+ -+ /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ -+ spin_lock(&pxp_chan->lock); -+ -+ cookie = pxp_chan->dma_chan.cookie; -+ -+ if (++cookie < 0) -+ cookie = 1; -+ -+ /* from dmaengine.h: "last cookie value returned to client" */ -+ pxp_chan->dma_chan.cookie = cookie; -+ tx->cookie = cookie; -+ -+ /* Here we add the tx descriptor to our PxP task queue. */ -+ list_add_tail(&desc->list, &pxp_chan->queue); -+ -+ spin_unlock(&pxp_chan->lock); -+ -+ dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); -+ -+ return cookie; -+} -+ -+/** -+ * pxp_init_channel() - initialize a PXP channel. -+ * @pxp_dma: PXP DMA context. -+ * @pchan: pointer to the channel object. -+ * @return 0 on success or negative error code on failure. -+ */ -+static int pxp_init_channel(struct pxp_dma *pxp_dma, -+ struct pxp_channel *pxp_chan) -+{ -+ int ret = 0; -+ -+ /* -+ * We are using _virtual_ channel here. -+ * Each channel contains all parameters of corresponding layers -+ * for one transaction; each layer is represented as one descriptor -+ * (i.e., pxp_tx_desc) here. -+ */ -+ -+ INIT_LIST_HEAD(&pxp_chan->queue); -+ -+ return ret; -+} -+ -+static irqreturn_t pxp_irq(int irq, void *dev_id) -+{ -+ struct pxps *pxp = dev_id; -+ struct pxp_channel *pxp_chan; -+ struct pxp_tx_desc *desc; -+ struct pxp_tx_desc *child, *_child; -+ dma_async_tx_callback callback; -+ void *callback_param; -+ unsigned long flags; -+ u32 hist_status; -+ int pxp_irq_status = 0; -+ -+ dump_pxp_reg(pxp); -+ -+ if (__raw_readl(pxp->base + HW_PXP_STAT) & BM_PXP_STAT_IRQ0) -+ __raw_writel(BM_PXP_STAT_IRQ0, pxp->base + HW_PXP_STAT_CLR); -+ else { -+ int irq_clr = 0; -+ -+ pxp_irq_status = __raw_readl(pxp->base + HW_PXP_IRQ); -+ BUG_ON(!pxp_irq_status); -+ -+ if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) -+ irq_clr |= BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) -+ irq_clr |= BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_FIRST_CH0_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_FIRST_CH1_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_FIRST_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_FIRST_STORE_IRQ; -+ -+ if (pxp_irq_status & BM_PXP_IRQ_WFE_B_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_WFE_B_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_WFE_A_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_WFE_A_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_DITHER_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_DITHER_STORE_IRQ; -+ -+ if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ; -+ -+ if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ; -+ -+ if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) -+ irq_clr |= BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) -+ irq_clr |= BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_DITHER_CH0_STORE_IRQ; -+ if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) -+ irq_clr |= BM_PXP_IRQ_DITHER_CH1_STORE_IRQ; -+ /*XXX other irqs status clear should be added below */ -+ -+ __raw_writel(irq_clr, pxp->base + HW_PXP_IRQ_CLR); -+ -+ pxp_writel(BM_PXP_CTRL_ENABLE, HW_PXP_CTRL_CLR); -+ } -+ pxp_collision_status_report(pxp, &col_info); -+ pxp_histogram_status_report(pxp, &hist_status); -+ /*XXX before a new update operation, we should -+ * always clear all the collision information -+ */ -+ pxp_collision_detection_disable(pxp); -+ pxp_histogram_disable(pxp); -+ -+ pxp_writel(0x0, HW_PXP_CTRL); -+ pxp_soft_reset(pxp); -+ if (pxp->devdata && pxp->devdata->pxp_data_path_config) -+ pxp->devdata->pxp_data_path_config(pxp); -+ __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ if (list_empty(&head)) { -+ pxp->pxp_ongoing = 0; -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ return IRQ_NONE; -+ } -+ -+ /* Get descriptor and call callback */ -+ desc = list_entry(head.next, struct pxp_tx_desc, list); -+ pxp_chan = to_pxp_channel(desc->txd.chan); -+ -+ pxp_chan->completed = desc->txd.cookie; -+ -+ callback = desc->txd.callback; -+ callback_param = desc->txd.callback_param; -+ -+ /* Send histogram status back to caller */ -+ desc->hist_status = hist_status; -+ -+ if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) -+ callback(callback_param); -+ -+ pxp_chan->status = PXP_CHANNEL_INITIALIZED; -+ -+ list_for_each_entry_safe(child, _child, &desc->tx_list, list) { -+ list_del_init(&child->list); -+ kmem_cache_free(tx_desc_cache, (void *)child); -+ } -+ list_del_init(&desc->list); -+ kmem_cache_free(tx_desc_cache, (void *)desc); -+ -+ complete(&pxp->complete); -+ pxp->pxp_ongoing = 0; -+ mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); -+ -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ return IRQ_HANDLED; -+} -+ -+/* allocate/free dma tx descriptor dynamically*/ -+static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) -+{ -+ struct pxp_tx_desc *desc = NULL; -+ struct dma_async_tx_descriptor *txd = NULL; -+ -+ desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); -+ if (desc == NULL) -+ return NULL; -+ -+ INIT_LIST_HEAD(&desc->list); -+ INIT_LIST_HEAD(&desc->tx_list); -+ txd = &desc->txd; -+ dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); -+ txd->tx_submit = pxp_tx_submit; -+ -+ return desc; -+} -+ -+ -+/* Allocate and initialise a transfer descriptor. */ -+static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, -+ struct scatterlist -+ *sgl, -+ unsigned int sg_len, -+ enum -+ dma_transfer_direction -+ direction, -+ unsigned long tx_flags, -+ void *context) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); -+ struct pxps *pxp = to_pxp(pxp_dma); -+ struct pxp_tx_desc *pos = NULL, *next = NULL; -+ struct pxp_tx_desc *desc = NULL; -+ struct pxp_tx_desc *first = NULL, *prev = NULL; -+ struct scatterlist *sg; -+ dma_addr_t phys_addr; -+ int i; -+ -+ if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { -+ dev_err(chan->device->dev, "Invalid DMA direction %d!\n", -+ direction); -+ return NULL; -+ } -+ -+ if (unlikely(sg_len < 2)) -+ return NULL; -+ -+ for_each_sg(sgl, sg, sg_len, i) { -+ desc = pxpdma_desc_alloc(pxp_chan); -+ if (!desc) { -+ dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); -+ -+ if (first) { -+ list_for_each_entry_safe(pos, next, &first->tx_list, list) { -+ list_del_init(&pos->list); -+ kmem_cache_free(tx_desc_cache, (void*)pos); -+ } -+ list_del_init(&first->list); -+ kmem_cache_free(tx_desc_cache, (void*)first); -+ } -+ -+ return NULL; -+ } -+ -+ phys_addr = sg_dma_address(sg); -+ -+ if (!first) { -+ first = desc; -+ -+ desc->layer_param.s0_param.paddr = phys_addr; -+ } else { -+ list_add_tail(&desc->list, &first->tx_list); -+ prev->next = desc; -+ desc->next = NULL; -+ -+ if (i == 1) -+ desc->layer_param.out_param.paddr = phys_addr; -+ else -+ desc->layer_param.ol_param.paddr = phys_addr; -+ } -+ -+ prev = desc; -+ } -+ -+ pxp->pxp_conf_state.layer_nr = sg_len; -+ first->txd.flags = tx_flags; -+ first->len = sg_len; -+ pr_debug("%s:%d first %p, first->len %d, flags %08x\n", -+ __func__, __LINE__, first, first->len, first->txd.flags); -+ -+ return &first->txd; -+} -+ -+static void pxp_issue_pending(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); -+ struct pxps *pxp = to_pxp(pxp_dma); -+ -+ spin_lock(&pxp_chan->lock); -+ -+ if (list_empty(&pxp_chan->queue)) { -+ spin_unlock(&pxp_chan->lock); -+ return; -+ } -+ -+ pxpdma_dequeue(pxp_chan, pxp); -+ pxp_chan->status = PXP_CHANNEL_READY; -+ -+ spin_unlock(&pxp_chan->lock); -+ -+ pxp_clk_enable(pxp); -+ wake_up_interruptible(&pxp->thread_waitq); -+} -+ -+static void __pxp_terminate_all(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ pxp_chan->status = PXP_CHANNEL_INITIALIZED; -+} -+ -+static int pxp_device_terminate_all(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ spin_lock(&pxp_chan->lock); -+ __pxp_terminate_all(chan); -+ spin_unlock(&pxp_chan->lock); -+ -+ return 0; -+} -+ -+static int pxp_alloc_chan_resources(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); -+ int ret; -+ -+ /* dmaengine.c now guarantees to only offer free channels */ -+ BUG_ON(chan->client_count > 1); -+ WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); -+ -+ chan->cookie = 1; -+ pxp_chan->completed = -ENXIO; -+ -+ pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); -+ ret = pxp_init_channel(pxp_dma, pxp_chan); -+ if (ret < 0) -+ goto err_chan; -+ -+ pxp_chan->status = PXP_CHANNEL_INITIALIZED; -+ -+ dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", -+ chan->chan_id, pxp_chan->eof_irq); -+ -+ return ret; -+ -+err_chan: -+ return ret; -+} -+ -+static void pxp_free_chan_resources(struct dma_chan *chan) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ spin_lock(&pxp_chan->lock); -+ -+ __pxp_terminate_all(chan); -+ -+ pxp_chan->status = PXP_CHANNEL_FREE; -+ -+ spin_unlock(&pxp_chan->lock); -+} -+ -+static enum dma_status pxp_tx_status(struct dma_chan *chan, -+ dma_cookie_t cookie, -+ struct dma_tx_state *txstate) -+{ -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ -+ if (cookie != chan->cookie) -+ return DMA_ERROR; -+ -+ if (txstate) { -+ txstate->last = pxp_chan->completed; -+ txstate->used = chan->cookie; -+ txstate->residue = 0; -+ } -+ return DMA_COMPLETE; -+} -+ -+static void pxp_data_path_config_v3p(struct pxps *pxp) -+{ -+ u32 val = 0; -+ -+ __raw_writel( -+ BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)| -+ BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)| -+ BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)| -+ BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0), -+ pxp->base + HW_PXP_DATA_PATH_CTRL0); -+ -+ /* -+ * MUX17: HIST_B as histogram: 0: output buffer, 1: wfe_store -+ * MUX16: HIST_A as collision: 0: output buffer, 1: wfe_store -+ */ -+ if (pxp_is_v3(pxp)) -+ val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| -+ BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(0); -+ else if (pxp_is_v3p(pxp)) -+ val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| -+ BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1); -+ __raw_writel(val, pxp->base + HW_PXP_DATA_PATH_CTRL1); -+} -+ -+static void pxp_soft_reset(struct pxps *pxp) -+{ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); -+ __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); -+ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); -+ while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) -+ dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); -+ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); -+ __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); -+} -+ -+static void pxp_sram_init(struct pxps *pxp, u32 select, -+ void *buffer_addr, u32 length) -+{ -+ u32 i; -+ -+ __raw_writel( -+ BF_PXP_INIT_MEM_CTRL_ADDR(0) | -+ BF_PXP_INIT_MEM_CTRL_SELECT(select) | -+ BF_PXP_INIT_MEM_CTRL_START(1), -+ pxp->base + HW_PXP_INIT_MEM_CTRL); -+ -+ if ((select == WFE_A) || (select == WFE_B)) { -+ for (i = 0; i < length / 2; i++) { -+ __raw_writel(*(((u32*)buffer_addr) + 2 * i + 1), -+ pxp->base + HW_PXP_INIT_MEM_DATA_HIGH); -+ -+ __raw_writel(*(((u32*)buffer_addr) + 2 * i), -+ pxp->base + HW_PXP_INIT_MEM_DATA); -+ } -+ } else { -+ for (i = 0; i < length; i++) { -+ __raw_writel(*(((u32*) buffer_addr) + i), -+ pxp->base + HW_PXP_INIT_MEM_DATA); -+ } -+ } -+ -+ __raw_writel( -+ BF_PXP_INIT_MEM_CTRL_ADDR(0) | -+ BF_PXP_INIT_MEM_CTRL_SELECT(select) | -+ BF_PXP_INIT_MEM_CTRL_START(0), -+ pxp->base + HW_PXP_INIT_MEM_CTRL); -+} -+ -+/* -+ * wfe a configuration -+ * configure wfe a engine for waveform processing -+ * including its fetch and store module -+ */ -+static void pxp_wfe_a_configure(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ -+ /* FETCH */ -+ __raw_writel( -+ BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFA_FETCH_CTRL); -+ -+ __raw_writel( -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1) | -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(0) | -+ BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3), -+ pxp->base + HW_PXP_WFA_ARRAY_PIXEL0_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(1) | -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(4) | -+ BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFA_ARRAY_PIXEL1_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(1) | -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(8) | -+ BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFA_ARRAY_PIXEL2_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(1) | -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(10) | -+ BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(15), -+ pxp->base + HW_PXP_WFA_ARRAY_PIXEL3_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(0) | -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(4) | -+ BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFA_ARRAY_PIXEL4_MASK); -+ -+ __raw_writel(1, pxp->base + HW_PXP_WFA_ARRAY_REG2); -+ -+ /* STORE */ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(8)| -+ BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | -+ BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), -+ pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), -+ pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0); -+ -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), -+ pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), -+ pxp->base + HW_PXP_WFE_A_STORE_FILL_DATA_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ -+ pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| -+ BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), -+ pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | -+ BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), -+ pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| -+ BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), -+ pxp->base + HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(0)| -+ BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(0)| -+ BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(0)| -+ BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(0), -+ pxp->base + HW_PXP_WFE_A_STORE_F_MASK_H_CH0); -+ -+ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1) | -+ BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2) | -+ BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4) | -+ BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8), -+ pxp->base + HW_PXP_WFE_A_STORE_F_MASK_L_CH0); -+ -+ /* ALU */ -+ __raw_writel(BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(0), -+ pxp->base + HW_PXP_ALU_A_INST_ENTRY); -+ -+ __raw_writel(BF_PXP_ALU_A_PARAM_PARAM0(0) | -+ BF_PXP_ALU_A_PARAM_PARAM1(0), -+ pxp->base + HW_PXP_ALU_A_PARAM); -+ -+ __raw_writel(BF_PXP_ALU_A_CONFIG_BUF_ADDR(0), -+ pxp->base + HW_PXP_ALU_A_CONFIG); -+ -+ __raw_writel(BF_PXP_ALU_A_LUT_CONFIG_MODE(0) | -+ BF_PXP_ALU_A_LUT_CONFIG_EN(0), -+ pxp->base + HW_PXP_ALU_A_LUT_CONFIG); -+ -+ __raw_writel(BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(0), -+ pxp->base + HW_PXP_ALU_A_LUT_DATA0); -+ -+ __raw_writel(BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(0), -+ pxp->base + HW_PXP_ALU_A_LUT_DATA1); -+ -+ __raw_writel(BF_PXP_ALU_A_CTRL_BYPASS (1) | -+ BF_PXP_ALU_A_CTRL_ENABLE (1) | -+ BF_PXP_ALU_A_CTRL_START (0) | -+ BF_PXP_ALU_A_CTRL_SW_RESET (0), -+ pxp->base + HW_PXP_ALU_A_CTRL); -+ -+ /* WFE A */ -+ __raw_writel(0x3F3F0303, pxp->base + HW_PXP_WFE_A_STAGE1_MUX0); -+ __raw_writel(0x0C00000C, pxp->base + HW_PXP_WFE_A_STAGE1_MUX1); -+ __raw_writel(0x01040000, pxp->base + HW_PXP_WFE_A_STAGE1_MUX2); -+ __raw_writel(0x0A0A0904, pxp->base + HW_PXP_WFE_A_STAGE1_MUX3); -+ __raw_writel(0x00000B0B, pxp->base + HW_PXP_WFE_A_STAGE1_MUX4); -+ -+ __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX0); -+ __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX1); -+ __raw_writel(0x280E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX2); -+ __raw_writel(0x00011800, pxp->base + HW_PXP_WFE_A_STAGE2_MUX3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX4); -+ __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX5); -+ __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX6); -+ __raw_writel(0x1A0E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX7); -+ __raw_writel(0x1B012911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX8); -+ __raw_writel(0x00002911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX9); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX10); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX11); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX12); -+ -+ __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_A_STAGE3_MUX0); -+ __raw_writel(0x3F3F3F08, pxp->base + HW_PXP_WFE_A_STAGE3_MUX1); -+ __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_A_STAGE3_MUX2); -+ __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_A_STAGE3_MUX3); -+ -+ __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_MASKS_0); -+ __raw_writel(0x3f030100, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_ADDR_0); -+ -+ __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT0); -+ __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT1); -+ __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT2); -+ __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT3); -+ __raw_writel(0x071F1F1F, pxp->base + HW_PXP_WFE_A_STG2_5X1_MASKS); -+ -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_2); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_3); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_4); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_5); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_6); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_7); -+ -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_0); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_1); -+ __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_2); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_3); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_4); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_5); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_6); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_7); -+ -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_0); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_1); -+ __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_2); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_3); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_4); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_5); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_6); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_7); -+ -+ __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_0); -+ __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_1); -+ __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_2); -+ __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_3); -+ __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_4); -+ __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_5); -+ __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_6); -+ __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_7); -+ -+ if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) -+ pxp->devdata->pxp_lut_cleanup_multiple(pxp, -+ proc_data->lut_sels, 1); -+} -+ -+static void pxp_wfe_a_configure_v3p(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ -+ /* FETCH */ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFB_FETCH_CTRL); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(3), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(4) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(8) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(10) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(15), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(4) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); -+ -+ __raw_writel(1, pxp->base + HW_PXP_WFB_ARRAY_REG2); -+ -+ /* STORE */ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(8)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), -+ pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), -+ pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); -+ -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), -+ pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), -+ pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_L_CH0); -+ -+ __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_H_CH0); -+ __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_L_CH0); -+ __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_H_CH0); -+ __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_L_CH0); -+ __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_H_CH0); -+ __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), -+ pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), -+ pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x1) | -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0x2) | -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0x4) | -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0x8), -+ pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0x0)| -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0x0)| -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0x0)| -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); -+ -+ -+ /* ALU */ -+ __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), -+ pxp->base + HW_PXP_ALU_B_INST_ENTRY); -+ -+ __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | -+ BF_PXP_ALU_B_PARAM_PARAM1(0), -+ pxp->base + HW_PXP_ALU_B_PARAM); -+ -+ __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), -+ pxp->base + HW_PXP_ALU_B_CONFIG); -+ -+ __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | -+ BF_PXP_ALU_B_LUT_CONFIG_EN(0), -+ pxp->base + HW_PXP_ALU_B_LUT_CONFIG); -+ -+ __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), -+ pxp->base + HW_PXP_ALU_B_LUT_DATA0); -+ -+ __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), -+ pxp->base + HW_PXP_ALU_B_LUT_DATA1); -+ -+ __raw_writel(BF_PXP_ALU_B_CTRL_BYPASS (1) | -+ BF_PXP_ALU_B_CTRL_ENABLE (1) | -+ BF_PXP_ALU_B_CTRL_START (0) | -+ BF_PXP_ALU_B_CTRL_SW_RESET (0), -+ pxp->base + HW_PXP_ALU_B_CTRL); -+ -+ /* WFE A */ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); -+ __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); -+ __raw_writel(0x00000003, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); -+ __raw_writel(0x04000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); -+ __raw_writel(0x0A090401, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); -+ __raw_writel(0x000B0B0A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); -+ -+ __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); -+ __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); -+ __raw_writel(0x290C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); -+ __raw_writel(0x00021901, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); -+ __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); -+ __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); -+ __raw_writel(0x1B0C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); -+ __raw_writel(0x1C022A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); -+ __raw_writel(0x02002A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); -+ -+ __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); -+ __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); -+ __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); -+ __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); -+ __raw_writel(0x3b202c1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); -+ __raw_writel(0x003b202d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); -+ __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); -+ __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); -+ __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); -+ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); -+ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); -+ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); -+ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); -+ -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); -+ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); -+ -+ __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); -+ __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); -+ __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); -+ __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); -+ __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); -+ -+ __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); -+ __raw_writel(0x3f232120, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); -+ -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); -+ __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); -+ __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); -+ -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); -+ __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); -+ __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); -+ -+ __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_0); -+ __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_1); -+ __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_2); -+ __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_3); -+ __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_4); -+ __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_5); -+ __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_6); -+ __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_7); -+ -+ __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); -+ -+ __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); -+ -+ __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); -+ -+ __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_7); -+ -+ __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_7); -+ -+ if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) -+ pxp->devdata->pxp_lut_cleanup_multiple(pxp, -+ proc_data->lut_sels, 1); -+} -+ -+/* -+ * wfe a processing -+ * use wfe a to process an update -+ * x,y,width,height: -+ * coordinate and size of the update region -+ * wb: -+ * working buffer, 16bpp -+ * upd: -+ * update buffer, in Y4 with or without alpha, 8bpp -+ * twb: -+ * temp working buffer, 16bpp -+ * only used when reagl_en is 1 -+ * y4c: -+ * y4c buffer, {Y4[3:0],3'b000,collision}, 8bpp -+ * lut: -+ * valid value 0-63 -+ * set to the lut used for next update -+ * partial: -+ * 0 - full update -+ * 1 - partial update -+ * reagl_en: -+ * 0 - use normal waveform algorithm -+ * 1 - enable reagl/-d waveform algorithm -+ * detection_only: -+ * 0 - write working buffer -+ * 1 - do no write working buffer, detection only -+ * alpha_en: -+ * 0 - upd is {Y4[3:0],4'b0000} format -+ * 1 - upd is {Y4[3:0],3'b000,alpha} format -+ */ -+static void pxp_wfe_a_process(struct pxps *pxp) -+{ -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &config_data->proc_data; -+ struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; -+ struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; -+ struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; -+ struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; -+ int v; -+ -+ if (fetch_ch0->width != fetch_ch1->width || -+ fetch_ch0->height != fetch_ch1->height) { -+ dev_err(pxp->dev, "width/height should be same for two fetch " -+ "channels\n"); -+ } -+ -+ print_param(fetch_ch0, "wfe_a fetch_ch0"); -+ print_param(fetch_ch1, "wfe_a fetch_ch1"); -+ print_param(store_ch0, "wfe_a store_ch0"); -+ print_param(store_ch1, "wfe_a store_ch1"); -+ -+ /* Fetch */ -+ __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF1_ADDR); -+ -+ __raw_writel(BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | -+ BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), -+ pxp->base + HW_PXP_WFA_FETCH_BUF1_CORD); -+ -+ __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFA_FETCH_BUF1_PITCH); -+ -+ __raw_writel(BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | -+ BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), -+ pxp->base + HW_PXP_WFA_FETCH_BUF1_SIZE); -+ -+ __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF2_ADDR); -+ -+ __raw_writel(BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | -+ BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), -+ pxp->base + HW_PXP_WFA_FETCH_BUF2_CORD); -+ -+ __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFA_FETCH_BUF2_PITCH); -+ -+ __raw_writel(BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | -+ BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), -+ pxp->base + HW_PXP_WFA_FETCH_BUF2_SIZE); -+ -+ /* Store */ -+ __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | -+ BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), -+ pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH0); -+ -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | -+ BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), -+ pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH1); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | -+ BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), -+ pxp->base + HW_PXP_WFE_A_STORE_PITCH); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), -+ pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH0); -+ __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH0); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( -+ store_ch1->paddr + (store_ch1->left + store_ch1->top * -+ store_ch1->stride) * 2), -+ pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH1); -+ -+ __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH1); -+ -+ /* ALU */ -+ __raw_writel(BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | -+ BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), -+ pxp->base + HW_PXP_ALU_A_BUF_SIZE); -+ -+ /* WFE */ -+ __raw_writel(BF_PXP_WFE_A_DIMENSIONS_WIDTH(fetch_ch0->width) | -+ BF_PXP_WFE_A_DIMENSIONS_HEIGHT(fetch_ch0->height), -+ pxp->base + HW_PXP_WFE_A_DIMENSIONS); -+ -+ /* Here it should be fetch_ch1 */ -+ __raw_writel(BF_PXP_WFE_A_OFFSET_X_OFFSET(fetch_ch1->left) | -+ BF_PXP_WFE_A_OFFSET_Y_OFFSET(fetch_ch1->top), -+ pxp->base + HW_PXP_WFE_A_OFFSET); -+ -+ __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, -+ pxp->base + HW_PXP_WFE_A_SW_DATA_REGS); -+ __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), -+ pxp->base + HW_PXP_WFE_A_SW_FLAG_REGS); -+ -+ __raw_writel( -+ BF_PXP_WFE_A_CTRL_ENABLE(1) | -+ BF_PXP_WFE_A_CTRL_SW_RESET(1), -+ pxp->base + HW_PXP_WFE_A_CTRL); -+ -+ if (proc_data->alpha_en) { -+ __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), -+ pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); -+ } else { -+ __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | -+ BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), -+ pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); -+ } -+ -+ /* disable CH1 when only doing detection */ -+ v = __raw_readl(pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); -+ if (proc_data->detection_only) { -+ v &= ~BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); -+ printk(KERN_EMERG "%s: detection only happens\n", __func__); -+ } else -+ v |= BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); -+ __raw_writel(v, pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); -+} -+ -+static void pxp_wfe_a_process_v3p(struct pxps *pxp) -+{ -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &config_data->proc_data; -+ struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; -+ struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; -+ struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; -+ struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; -+ int v; -+ -+ if (fetch_ch0->width != fetch_ch1->width || -+ fetch_ch0->height != fetch_ch1->height) { -+ dev_err(pxp->dev, "width/height should be same for two fetch " -+ "channels\n"); -+ } -+ -+ print_param(fetch_ch0, "wfe_a fetch_ch0"); -+ print_param(fetch_ch1, "wfe_a fetch_ch1"); -+ print_param(store_ch0, "wfe_a store_ch0"); -+ print_param(store_ch1, "wfe_a store_ch1"); -+ -+ /* Fetch */ -+ __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); -+ -+ __raw_writel(BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | -+ BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), -+ pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); -+ -+ __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); -+ -+ __raw_writel(BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | -+ BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), -+ pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); -+ -+ __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); -+ -+ __raw_writel(BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | -+ BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), -+ pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); -+ -+ __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); -+ -+ __raw_writel(BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | -+ BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), -+ pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); -+ -+ /* Store */ -+ __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | -+ BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), -+ pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); -+ -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | -+ BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), -+ pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | -+ BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), -+ pxp->base + HW_PXP_WFE_B_STORE_PITCH); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( -+ store_ch1->paddr + (store_ch1->left + store_ch1->top * -+ store_ch1->stride) * 2), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); -+ -+ /* ALU */ -+ __raw_writel(BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | -+ BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), -+ pxp->base + HW_PXP_ALU_B_BUF_SIZE); -+ -+ /* WFE */ -+ __raw_writel(BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | -+ BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), -+ pxp->base + HW_PXP_WFE_B_DIMENSIONS); -+ -+ /* Here it should be fetch_ch1 */ -+ __raw_writel(BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch1->left) | -+ BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch1->top), -+ pxp->base + HW_PXP_WFE_B_OFFSET); -+ -+ __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, -+ pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); -+ __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), -+ pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_CTRL_ENABLE(1) | -+ BF_PXP_WFE_B_CTRL_SW_RESET(1), -+ pxp->base + HW_PXP_WFE_B_CTRL); -+ -+ if (proc_data->alpha_en) { -+ __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); -+ } else { -+ __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(2) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); -+ } -+ -+ /* disable CH1 when only doing detection */ -+ v = __raw_readl(pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); -+ if (proc_data->detection_only) { -+ v &= ~BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); -+ printk(KERN_EMERG "%s: detection only happens\n", __func__); -+ } else -+ v |= BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); -+ __raw_writel(v, pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); -+} -+ -+/* -+ * wfe b configuration -+ * -+ * configure wfe b engnine for reagl/-d waveform processing -+ */ -+static void pxp_wfe_b_configure(struct pxps *pxp) -+{ -+ /* Fetch */ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFB_FETCH_CTRL); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(10) | -+ BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(15), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(2) | -+ BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(1) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(1) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(1) | -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL5_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(1) | -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(1) | -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL6_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(1) | -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(0) | -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(0) | -+ BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(7), -+ pxp->base + HW_PXP_WFB_ARRAY_PIXEL7_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(8) | -+ BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(8), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(9) | -+ BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG1_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(1) | -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(1) | -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(8) | -+ BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(8), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG2_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(1) | -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(1) | -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(9) | -+ BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG3_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(1) | -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(8) | -+ BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(8), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG4_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(1) | -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(9) | -+ BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG5_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(1) | -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(1) | -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(8) | -+ BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(8), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG6_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(1) | -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(1) | -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(9) | -+ BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG7_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(1) | -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(8) | -+ BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(8), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG8_MASK); -+ -+ __raw_writel( -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(0) | -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(1) | -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(0) | -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(1) | -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(9) | -+ BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(9), -+ pxp->base + HW_PXP_WFB_ARRAY_FLAG9_MASK); -+ -+ pxp_sram_init(pxp, WFE_B, active_matrix_data_8x8, 64); -+ -+ /* Store */ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(32), -+ pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), -+ pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), -+ pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(0), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), -+ pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xff), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); -+ -+ __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(2)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(6)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); -+ -+ /* ALU */ -+ __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), -+ pxp->base + HW_PXP_ALU_B_INST_ENTRY); -+ -+ __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | -+ BF_PXP_ALU_B_PARAM_PARAM1(0), -+ pxp->base + HW_PXP_ALU_B_PARAM); -+ -+ __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), -+ pxp->base + HW_PXP_ALU_B_CONFIG); -+ -+ __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | -+ BF_PXP_ALU_B_LUT_CONFIG_EN(0), -+ pxp->base + HW_PXP_ALU_B_LUT_CONFIG); -+ -+ __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), -+ pxp->base + HW_PXP_ALU_B_LUT_DATA0); -+ -+ __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), -+ pxp->base + HW_PXP_ALU_B_LUT_DATA1); -+ -+ __raw_writel( -+ BF_PXP_ALU_B_CTRL_BYPASS (1) | -+ BF_PXP_ALU_B_CTRL_ENABLE (1) | -+ BF_PXP_ALU_B_CTRL_START (0) | -+ BF_PXP_ALU_B_CTRL_SW_RESET (0), -+ pxp->base + HW_PXP_ALU_B_CTRL); -+ -+ /* WFE */ -+ __raw_writel(0x00000402, pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); -+ -+ __raw_writel(0x02040608, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); -+ __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); -+ __raw_writel(0x050A040A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); -+ __raw_writel(0x070A060A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); -+ __raw_writel(0x0000000A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); -+ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); -+ __raw_writel(0x1C1E2022, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); -+ __raw_writel(0x1215181A, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); -+ __raw_writel(0x00000C0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); -+ __raw_writel(0x01000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); -+ __raw_writel(0x000C010B, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); -+ -+ __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); -+ __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); -+ __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); -+ __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); -+ __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); -+ __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); -+ __raw_writel(0x00001211, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); -+ -+ __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); -+ __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); -+ __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); -+ __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); -+ -+ __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); -+ __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); -+ __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); -+ __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); -+ -+ __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); -+ -+ __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); -+ __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); -+ __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); -+ -+ __raw_writel(0x00008000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); -+ __raw_writel(0x0000FFFE, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); -+ __raw_writel(0x00000F0F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); -+ -+ __raw_writel(0x00007F7F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); -+ __raw_writel(0x00FF00FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); -+ __raw_writel(0x000000FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); -+ -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); -+ __raw_writel(0xFF3FFF3F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); -+ __raw_writel(0xFFFFFF1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_CTRL_ENABLE(1) | -+ BF_PXP_WFE_B_CTRL_SW_RESET(1), -+ pxp->base + HW_PXP_WFE_B_CTRL); -+} -+ -+/* wfe b processing -+ * use wfe b to process an update -+ * call this function only after pxp_wfe_a_processing -+ * x,y,width,height: -+ * coordinate and size of the update region -+ * twb: -+ * temp working buffer, 16bpp -+ * only used when reagl_en is 1 -+ * wb: -+ * working buffer, 16bpp -+ * lut: -+ * lut buffer, 8bpp -+ * lut_update: -+ * 0 - wfe_b is used for reagl/reagl-d operation -+ * 1 - wfe_b is used for lut update operation -+ * reagl_d_en: -+ * 0 - use reagl waveform algorithm -+ * 1 - use reagl/-d waveform algorithm -+ */ -+static void pxp_wfe_b_process(struct pxps *pxp) -+{ -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &config_data->proc_data; -+ struct pxp_layer_param *fetch_ch0 = &config_data->wfe_b_fetch_param[0]; -+ struct pxp_layer_param *fetch_ch1 = &config_data->wfe_b_fetch_param[1]; -+ struct pxp_layer_param *store_ch0 = &config_data->wfe_b_store_param[0]; -+ struct pxp_layer_param *store_ch1 = &config_data->wfe_b_store_param[1]; -+ static int comp_mask; -+ /* Fetch */ -+ -+ print_param(fetch_ch0, "wfe_b fetch_ch0"); -+ print_param(fetch_ch1, "wfe_b fetch_ch1"); -+ print_param(store_ch0, "wfe_b store_ch0"); -+ print_param(store_ch1, "wfe_b store_ch1"); -+ -+ __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); -+ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | -+ BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), -+ pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); -+ -+ __raw_writel(fetch_ch0->stride, -+ pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); -+ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height-1) | -+ BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width-1), -+ pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); -+ -+ __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); -+ -+ __raw_writel(fetch_ch1->stride * 2, -+ pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); -+ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | -+ BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), -+ pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); -+ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height-1) | -+ BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width-1), -+ pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); -+ -+ if (!proc_data->lut_update) { -+ __raw_writel( -+ BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFB_FETCH_CTRL); -+ } else { -+ __raw_writel( -+ BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFB_FETCH_CTRL); -+ } -+ -+#ifdef CONFIG_REAGLD_ALGO_CHECK -+ __raw_writel( -+ (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((fetch_ch0->comp_mask&0x000000FF)<<16), -+ pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); -+#else -+ __raw_writel( -+ (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((comp_mask&0x000000FF)<<16), -+ pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); -+ -+ /* comp_mask only need to be updated upon REAGL-D, 0,1,...7, 0,1,... */ -+ if (proc_data->reagl_d_en) { -+ comp_mask++; -+ if (comp_mask>7) -+ comp_mask = 0; -+ } -+#endif -+ -+ /* Store */ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| -+ BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), -+ pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width-1)| -+ BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height-1), -+ pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride * 2)| -+ BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), -+ pxp->base + HW_PXP_WFE_B_STORE_PITCH); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr -+ + (store_ch0->left + store_ch0->top * store_ch0->stride) * 2), -+ pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); -+ -+ if (proc_data->lut_update) { -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x3f0000), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x30)| -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(4)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); -+ } else { -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), -+ pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(3)| -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| -+ BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| -+ BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), -+ pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); -+ } -+ -+ /* ALU */ -+ __raw_writel( -+ BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | -+ BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), -+ pxp->base + HW_PXP_ALU_B_BUF_SIZE); -+ -+ /* WFE */ -+ __raw_writel( -+ BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | -+ BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), -+ pxp->base + HW_PXP_WFE_B_DIMENSIONS); -+ -+ __raw_writel( /*TODO check*/ -+ BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch0->left) | -+ BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch0->top), -+ pxp->base + HW_PXP_WFE_B_OFFSET); -+ -+ __raw_writel(proc_data->reagl_d_en, pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); -+} -+ -+void pxp_fill( -+ u32 bpp, -+ u32 value, -+ u32 width, -+ u32 height, -+ u32 output_buffer, -+ u32 output_pitch) -+{ -+ u32 active_bpp; -+ u32 pitch; -+ -+ if (bpp == 8) { -+ active_bpp = 0; -+ pitch = output_pitch; -+ } else if(bpp == 16) { -+ active_bpp = 1; -+ pitch = output_pitch * 2; -+ } else { -+ active_bpp = 2; -+ pitch = output_pitch * 4; -+ } -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| -+ BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | -+ BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(0)| -+ BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(width-1)| -+ BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(height-1), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(width-1)| -+ BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(height-1), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(pitch)| -+ BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(pitch), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_PITCH); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(active_bpp)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(active_bpp)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| -+ BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(output_buffer), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(output_buffer), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(value), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x000000ff), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x00000000), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x000000ff), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x00000000), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x000000ff), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(40)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| -+ BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), -+ pxp_reg_base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_CTRL2_ENABLE (1) | -+ BF_PXP_CTRL2_ROTATE0 (0) | -+ BF_PXP_CTRL2_HFLIP0 (0) | -+ BF_PXP_CTRL2_VFLIP0 (0) | -+ BF_PXP_CTRL2_ROTATE1 (0) | -+ BF_PXP_CTRL2_HFLIP1 (0) | -+ BF_PXP_CTRL2_VFLIP1 (0) | -+ BF_PXP_CTRL2_ENABLE_DITHER (0) | -+ BF_PXP_CTRL2_ENABLE_WFE_A (0) | -+ BF_PXP_CTRL2_ENABLE_WFE_B (1) | -+ BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | -+ BF_PXP_CTRL2_ENABLE_ALPHA_B (0) | -+ BF_PXP_CTRL2_BLOCK_SIZE (0) | -+ BF_PXP_CTRL2_ENABLE_CSC2 (0) | -+ BF_PXP_CTRL2_ENABLE_LUT (0) | -+ BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | -+ BF_PXP_CTRL2_ENABLE_ROTATE1 (0), -+ pxp_reg_base + HW_PXP_CTRL2); -+ -+ if (busy_wait(BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ & -+ __raw_readl(pxp_reg_base + HW_PXP_IRQ)) == false) -+ printk("%s: wait for completion timeout\n", __func__); -+} -+EXPORT_SYMBOL(pxp_fill); -+ -+static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ -+ if (of_machine_is_compatible("fsl,imx8ulp")) -+ return; -+ -+ if (proc_data->lut_cleanup == 1) { -+ if (set) { -+ __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0 + 0x4); -+ __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1 + 0x4); -+ } else { -+ pxp_luts_deactivate(pxp, lut); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); -+ } -+ } -+} -+ -+static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ -+ if (proc_data->lut_cleanup == 1) { -+ if (set) { -+ __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0 + 0x4); -+ __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1 + 0x4); -+ } else { -+ pxp_luts_deactivate(pxp, lut); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); -+ __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); -+ } -+ } -+} -+ -+#ifdef CONFIG_MXC_FPGA_M4_TEST -+void m4_process(void) -+{ -+ __raw_writel(0x7, pinctrl_base + PIN_DOUT); /* M4 Start */ -+ -+ while (!(__raw_readl(pxp_reg_base + HW_PXP_HANDSHAKE_CPU_STORE) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY)); -+ -+ __raw_writel(0x3, pinctrl_base + PIN_DOUT); /* M4 Stop */ -+ -+ -+} -+#else -+void m4_process(void) {} -+#endif -+EXPORT_SYMBOL(m4_process); -+ -+static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut) -+{ -+ if(lut<32) -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) | (1 << lut), -+ pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); -+ else { -+ lut = lut -32; -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) | (1 << lut), -+ pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); -+ } -+} -+ -+static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut) -+{ -+ if(lut<32) -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) | (1 << lut), -+ pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); -+ else { -+ lut = lut -32; -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) | (1 << lut), -+ pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); -+ } -+} -+ -+static void pxp_luts_activate(struct pxps *pxp, u64 lut_status) -+{ -+ int i = 0; -+ -+ if (!lut_status) -+ return; -+ -+ for (i = 0; i < 64; i++) { -+ if (lut_status & (1ULL << i)) -+ if (pxp->devdata && pxp->devdata->pxp_lut_status_set) -+ pxp->devdata->pxp_lut_status_set(pxp, i); -+ } -+} -+ -+static void pxp_lut_status_clr(unsigned int lut) -+{ -+ if(lut<32) -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) & (~(1 << lut)), -+ pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); -+ else -+ { -+ lut = lut -32; -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) & (~(1 << lut)), -+ pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); -+ } -+} -+ -+static void pxp_lut_status_clr_v3p(unsigned int lut) -+{ -+ if(lut<32) -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) & (~(1 << lut)), -+ pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); -+ else -+ { -+ lut = lut -32; -+ __raw_writel( -+ __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) & (~(1 << lut)), -+ pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); -+ } -+} -+ -+/* this function should be called in the epdc -+ * driver explicitly when some epdc lut becomes -+ * idle. So it should be exported. -+ */ -+static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status) -+{ -+ int i = 0; -+ -+ if (!lut_status) -+ return; -+ -+ for (i = 0; i < 64; i++) { -+ if (lut_status & (1ULL << i)) -+ if (pxp->devdata && pxp->devdata->pxp_lut_status_clr) -+ pxp->devdata->pxp_lut_status_clr(i); -+ } -+} -+ -+/* use histogram_B engine to calculate histogram status */ -+static void pxp_histogram_enable(struct pxps *pxp, -+ unsigned int width, -+ unsigned int height) -+{ -+ u32 val = 0; -+ -+ __raw_writel( -+ BF_PXP_HIST_B_BUF_SIZE_HEIGHT(height)| -+ BF_PXP_HIST_B_BUF_SIZE_WIDTH(width), -+ pxp->base + HW_PXP_HIST_B_BUF_SIZE); -+ -+ if (pxp_is_v3(pxp)) -+ val = 64; -+ else if (pxp_is_v3p(pxp)) -+ val = 64 + 4; -+ -+ __raw_writel( -+ BF_PXP_HIST_B_MASK_MASK_EN(1)| -+ BF_PXP_HIST_B_MASK_MASK_MODE(0)| -+ BF_PXP_HIST_B_MASK_MASK_OFFSET(val)| -+ BF_PXP_HIST_B_MASK_MASK_WIDTH(0)| -+ BF_PXP_HIST_B_MASK_MASK_VALUE0(1) | -+ BF_PXP_HIST_B_MASK_MASK_VALUE1(0), -+ pxp->base + HW_PXP_HIST_B_MASK); -+ -+ __raw_writel( -+ BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| -+ BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(8)| -+ BF_PXP_HIST_B_CTRL_CLEAR(0)| -+ BF_PXP_HIST_B_CTRL_ENABLE(1), -+ pxp->base + HW_PXP_HIST_B_CTRL); -+} -+ -+static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status) -+{ -+ BUG_ON(!hist_status); -+ -+ *hist_status = (__raw_readl(pxp->base + HW_PXP_HIST_B_CTRL) & BM_PXP_HIST_B_CTRL_STATUS) -+ >> BP_PXP_HIST_B_CTRL_STATUS; -+ dev_dbg(pxp->dev, "%d pixels are used to calculate histogram status %d\n", -+ __raw_readl(pxp->base + HW_PXP_HIST_B_TOTAL_PIXEL), *hist_status); -+} -+ -+static void pxp_histogram_disable(struct pxps *pxp) -+{ -+ __raw_writel( -+ BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| -+ BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(4)| -+ BF_PXP_HIST_B_CTRL_CLEAR(1)| -+ BF_PXP_HIST_B_CTRL_ENABLE(0), -+ pxp->base + HW_PXP_HIST_B_CTRL); -+} -+ -+/* the collision detection function will be -+ * called by epdc driver when required -+ */ -+static void pxp_collision_detection_enable(struct pxps *pxp, -+ unsigned int width, -+ unsigned int height) -+{ -+ u32 val = 0; -+ -+ __raw_writel( -+ BF_PXP_HIST_A_BUF_SIZE_HEIGHT(height)| -+ BF_PXP_HIST_A_BUF_SIZE_WIDTH(width), -+ pxp_reg_base + HW_PXP_HIST_A_BUF_SIZE); -+ -+ if (pxp_is_v3(pxp)) -+ val = 65; -+ else if (pxp_is_v3p(pxp)) -+ val = 65 + 4; -+ -+ __raw_writel( -+ BF_PXP_HIST_A_MASK_MASK_EN(1)| -+ BF_PXP_HIST_A_MASK_MASK_MODE(0)| -+ BF_PXP_HIST_A_MASK_MASK_OFFSET(val)| -+ BF_PXP_HIST_A_MASK_MASK_WIDTH(0)| -+ BF_PXP_HIST_A_MASK_MASK_VALUE0(1) | -+ BF_PXP_HIST_A_MASK_MASK_VALUE1(0), -+ pxp_reg_base + HW_PXP_HIST_A_MASK); -+ -+ __raw_writel( -+ BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| -+ BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| -+ BF_PXP_HIST_A_CTRL_CLEAR(0)| -+ BF_PXP_HIST_A_CTRL_ENABLE(1), -+ pxp_reg_base + HW_PXP_HIST_A_CTRL); -+} -+ -+static void pxp_collision_detection_disable(struct pxps *pxp) -+{ -+ __raw_writel( -+ BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| -+ BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| -+ BF_PXP_HIST_A_CTRL_CLEAR(1)| -+ BF_PXP_HIST_A_CTRL_ENABLE(0), -+ pxp_reg_base + HW_PXP_HIST_A_CTRL); -+} -+ -+/* this function can be called in the epdc callback -+ * function in the pxp_irq() to let the epdc know -+ * the collision information for the previous working -+ * buffer update. -+ */ -+static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info) -+{ -+ unsigned int count; -+ -+ BUG_ON(!info); -+ memset(info, 0x0, sizeof(*info)); -+ -+ info->pixel_cnt = count = __raw_readl(pxp->base + HW_PXP_HIST_A_TOTAL_PIXEL); -+ if (!count) -+ return false; -+ -+ dev_dbg(pxp->dev, "%s: pixel_cnt = %d\n", __func__, info->pixel_cnt); -+ info->rect_min_x = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) & 0xffff; -+ dev_dbg(pxp->dev, "%s: rect_min_x = %d\n", __func__, info->rect_min_x); -+ info->rect_max_x = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) >> 16) & 0xffff; -+ dev_dbg(pxp->dev, "%s: rect_max_x = %d\n", __func__, info->rect_max_x); -+ info->rect_min_y = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) & 0xffff; -+ dev_dbg(pxp->dev, "%s: rect_min_y = %d\n", __func__, info->rect_min_y); -+ info->rect_max_y = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) >> 16) & 0xffff; -+ dev_dbg(pxp->dev, "%s: rect_max_y = %d\n", __func__, info->rect_max_y); -+ -+ info->victim_luts[0] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT0); -+ dev_dbg(pxp->dev, "%s: victim_luts[0] = 0x%x\n", __func__, info->victim_luts[0]); -+ info->victim_luts[1] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT1); -+ dev_dbg(pxp->dev, "%s: victim_luts[1] = 0x%x\n", __func__, info->victim_luts[1]); -+ -+ return true; -+} -+ -+void pxp_get_collision_info(struct pxp_collision_info *info) -+{ -+ BUG_ON(!info); -+ -+ memcpy(info, &col_info, sizeof(struct pxp_collision_info)); -+} -+EXPORT_SYMBOL(pxp_get_collision_info); -+ -+static void dither_prefetch_config(struct pxps *pxp) -+{ -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; -+ struct pxp_layer_param *fetch_ch1 = &config_data->dither_fetch_param[1]; -+ -+ print_param(fetch_ch0, "dither fetch_ch0"); -+ print_param(fetch_ch1, "dither fetch_ch1"); -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(2) | -+ BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(0), -+ pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(0) | -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(0), -+ pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0); -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(fetch_ch0->width - 1) | -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(fetch_ch0->height - 1), -+ pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(0) | -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(0), -+ pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1); -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(fetch_ch1->width - 1) | -+ BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(fetch_ch1->height - 1), -+ pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1); -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(fetch_ch0->width - 1) | -+ BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(fetch_ch0->height - 1), -+ pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(fetch_ch1->width - 1) | -+ BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(fetch_ch1->height - 1), -+ pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(fetch_ch0->stride) | -+ BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(fetch_ch1->stride), -+ pxp->base + HW_PXP_DITHER_FETCH_PITCH); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), -+ pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(1), -+ pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(0), -+ pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(0) | -+ BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(0), -+ pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(7) | -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(7) | -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(7) | -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(7), -+ pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(7) | -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(7) | -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(7) | -+ BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(7), -+ pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(fetch_ch0->paddr), -+ pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(fetch_ch1->paddr), -+ pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH1); -+} -+ -+static void dither_store_config(struct pxps *pxp) -+{ -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; -+ struct pxp_layer_param *store_ch1 = &config_data->dither_store_param[1]; -+ -+ print_param(store_ch0, "dither store_ch0"); -+ print_param(store_ch1, "dither store_ch1"); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(32), -+ pxp->base + HW_PXP_DITHER_STORE_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | -+ BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), -+ pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | -+ BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), -+ pxp->base + HW_PXP_DITHER_STORE_SIZE_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | -+ BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride), -+ pxp->base + HW_PXP_DITHER_STORE_PITCH); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), -+ pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(0)| -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| -+ BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), -+ pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), -+ pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(store_ch1->paddr), -+ pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), -+ pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), -+ pxp->base + HW_PXP_DITHER_STORE_FILL_DATA_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0xffffff), -+ pxp->base + HW_PXP_DITHER_STORE_D_MASK0_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x0), -+ pxp->base + HW_PXP_DITHER_STORE_D_MASK0_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), -+ pxp->base + HW_PXP_DITHER_STORE_D_MASK1_H_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xff), -+ pxp->base + HW_PXP_DITHER_STORE_D_MASK1_L_CH0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(0)| -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| -+ BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), -+ pxp->base + HW_PXP_DITHER_STORE_D_SHIFT_L_CH0); -+} -+ -+static void pxp_set_final_lut_data(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ -+ if (proc_data->quant_bit < 2) { -+ pxp_sram_init(pxp, DITHER0_LUT, bit1_dither_data_8x8, 64); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xf0)| -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xf0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); -+ } else if (proc_data->quant_bit < 4) { -+ pxp_sram_init(pxp, DITHER0_LUT, bit2_dither_data_8x8, 64); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x50) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x50) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x50), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xa0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xa0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xa0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); -+ } else { -+ pxp_sram_init(pxp, DITHER0_LUT, bit4_dither_data_8x8, 64); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x10) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x20) | -+ BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x30), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x40) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x60) | -+ BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x70), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0x80) | -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0x90) | -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| -+ BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xb0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); -+ -+ __raw_writel( -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xc0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xd0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xe0) | -+ BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), -+ pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); -+ } -+} -+ -+static void pxp_dithering_process(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ u32 val = 0; -+ -+ if (pxp->devdata && pxp->devdata->pxp_dithering_configure) -+ pxp->devdata->pxp_dithering_configure(pxp); -+ -+ if (pxp_is_v3(pxp)) -+ val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | -+ BF_PXP_DITHER_CTRL_ENABLE1 (0) | -+ BF_PXP_DITHER_CTRL_ENABLE2 (0) | -+ BF_PXP_DITHER_CTRL_DITHER_MODE2 (0) | -+ BF_PXP_DITHER_CTRL_DITHER_MODE1 (0) | -+ BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | -+ BF_PXP_DITHER_CTRL_LUT_MODE (0) | -+ BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | -+ BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (0) | -+ BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (0) | -+ BF_PXP_DITHER_CTRL_BUSY2 (0) | -+ BF_PXP_DITHER_CTRL_BUSY1 (0) | -+ BF_PXP_DITHER_CTRL_BUSY0 (0); -+ else if (pxp_is_v3p(pxp)) { -+ if (proc_data->dither_mode != 0 && -+ proc_data->dither_mode != 3) { -+ dev_err(pxp->dev, "Not supported dithering mode. " -+ "Forced to be Orderred mode!\n"); -+ proc_data->dither_mode = 3; -+ } -+ -+ val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | -+ BF_PXP_DITHER_CTRL_ENABLE1 (1) | -+ BF_PXP_DITHER_CTRL_ENABLE2 (1) | -+ BF_PXP_DITHER_CTRL_DITHER_MODE2(proc_data->dither_mode) | -+ BF_PXP_DITHER_CTRL_DITHER_MODE1(proc_data->dither_mode) | -+ BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | -+ BF_PXP_DITHER_CTRL_LUT_MODE (0) | -+ BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | -+ BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (1) | -+ BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (1) | -+ BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE (0) | -+ BF_PXP_DITHER_CTRL_BUSY2 (0) | -+ BF_PXP_DITHER_CTRL_BUSY1 (0) | -+ BF_PXP_DITHER_CTRL_BUSY0 (0); -+ } -+ __raw_writel(val, pxp->base + HW_PXP_DITHER_CTRL); -+ -+ switch(proc_data->dither_mode) { -+ case PXP_DITHER_PASS_THROUGH: -+ /* no more settings required */ -+ break; -+ case PXP_DITHER_FLOYD: -+ case PXP_DITHER_ATKINSON: -+ case PXP_DITHER_ORDERED: -+ if(!proc_data->quant_bit || proc_data->quant_bit > 7) { -+ dev_err(pxp->dev, "unsupported quantization bit number!\n"); -+ return; -+ } -+ __raw_writel( -+ BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(1) | -+ BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), -+ pxp->base + HW_PXP_DITHER_CTRL_SET); -+ pxp_set_final_lut_data(pxp); -+ -+ break; -+ case PXP_DITHER_QUANT_ONLY: -+ if(!proc_data->quant_bit || proc_data->quant_bit > 7) { -+ dev_err(pxp->dev, "unsupported quantization bit number!\n"); -+ return; -+ } -+ __raw_writel( -+ BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), -+ pxp->base + HW_PXP_DITHER_CTRL_SET); -+ break; -+ default: -+ /* unknown mode */ -+ dev_err(pxp->dev, "unknown dithering mode passed!\n"); -+ __raw_writel(0x0, pxp->base + HW_PXP_DITHER_CTRL); -+ return; -+ } -+} -+ -+static void pxp_dithering_configure(struct pxps *pxp) -+{ -+ dither_prefetch_config(pxp); -+ dither_store_config(pxp); -+} -+ -+static void pxp_dithering_configure_v3p(struct pxps *pxp) -+{ -+ struct pxp_config_data *config_data = &pxp->pxp_conf_state; -+ struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; -+ struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; -+ -+ __raw_writel(BF_PXP_CTRL_BLOCK_SIZE(BV_PXP_CTRL_BLOCK_SIZE__8X8) | -+ BF_PXP_CTRL_ROTATE0(BV_PXP_CTRL_ROTATE0__ROT_0) | -+ BM_PXP_CTRL_IRQ_ENABLE, -+ pxp->base + HW_PXP_CTRL); -+ -+ __raw_writel(BF_PXP_PS_CTRL_DECX(BV_PXP_PS_CTRL_DECX__DISABLE) | -+ BF_PXP_PS_CTRL_DECY(BV_PXP_PS_CTRL_DECY__DISABLE) | -+ BF_PXP_PS_CTRL_FORMAT(BV_PXP_PS_CTRL_FORMAT__Y8), -+ pxp->base + HW_PXP_PS_CTRL); -+ -+ __raw_writel(BF_PXP_OUT_CTRL_FORMAT(BV_PXP_OUT_CTRL_FORMAT__Y8), -+ pxp->base + HW_PXP_OUT_CTRL); -+ -+ __raw_writel(BF_PXP_PS_SCALE_YSCALE(4096) | -+ BF_PXP_PS_SCALE_XSCALE(4096), -+ pxp->base + HW_PXP_PS_SCALE); -+ -+ __raw_writel(store_ch0->paddr, pxp->base + HW_PXP_OUT_BUF); -+ -+ __raw_writel(store_ch0->stride, pxp->base + HW_PXP_OUT_PITCH); -+ -+ __raw_writel(BF_PXP_OUT_LRC_X(store_ch0->width - 1) | -+ BF_PXP_OUT_LRC_Y(store_ch0->height - 1), -+ pxp->base + HW_PXP_OUT_LRC); -+ -+ __raw_writel(BF_PXP_OUT_AS_ULC_X(1) | -+ BF_PXP_OUT_AS_ULC_Y(1), -+ pxp->base + HW_PXP_OUT_AS_ULC); -+ -+ __raw_writel(BF_PXP_OUT_AS_LRC_X(0) | -+ BF_PXP_OUT_AS_LRC_Y(0), -+ pxp->base + HW_PXP_OUT_AS_LRC); -+ -+ __raw_writel(BF_PXP_OUT_PS_ULC_X(0) | -+ BF_PXP_OUT_PS_ULC_Y(0), -+ pxp->base + HW_PXP_OUT_PS_ULC); -+ -+ __raw_writel(BF_PXP_OUT_PS_LRC_X(fetch_ch0->width - 1) | -+ BF_PXP_OUT_PS_LRC_Y(fetch_ch0->height - 1), -+ pxp->base + HW_PXP_OUT_PS_LRC); -+ -+ __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_PS_BUF); -+ -+ __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_PS_PITCH); -+ -+ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); -+ -+ __raw_writel(BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| -+ BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), -+ pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); -+ -+ __raw_writel(BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1), -+ pxp->base + HW_PXP_DATA_PATH_CTRL0_CLR); -+} -+ -+static void pxp_start2(struct pxps *pxp) -+{ -+ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; -+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data; -+ int dither_wfe_a_handshake = 0; -+ int wfe_a_b_handshake = 0; -+ int count = 0; -+ -+ int wfe_a_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_A) == PXP_ENABLE_WFE_A); -+ int wfe_b_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_B) == PXP_ENABLE_WFE_B); -+ int dither_enable = ((proc_data->engine_enable & PXP_ENABLE_DITHER) == PXP_ENABLE_DITHER); -+ int handshake = ((proc_data->engine_enable & PXP_ENABLE_HANDSHAKE) == PXP_ENABLE_HANDSHAKE); -+ int dither_bypass = ((proc_data->engine_enable & PXP_ENABLE_DITHER_BYPASS) == PXP_ENABLE_DITHER_BYPASS); -+ u32 val = 0; -+ -+ if (dither_enable) -+ count++; -+ if (wfe_a_enable) -+ count++; -+ if (wfe_b_enable) -+ count++; -+ -+ if (count == 0) -+ return; -+ if (handshake && (count == 1)) { -+ dev_warn(pxp->dev, "Warning: Can not use handshake mode when " -+ "only one sub-block is enabled!\n"); -+ handshake = 0; -+ } -+ -+ if (handshake && wfe_b_enable && (wfe_a_enable == 0)) { -+ dev_err(pxp->dev, "WFE_B only works when WFE_A is enabled!\n"); -+ return; -+ } -+ -+ if (handshake && dither_enable && wfe_a_enable) -+ dither_wfe_a_handshake = 1; -+ if (handshake && wfe_a_enable && wfe_b_enable) -+ wfe_a_b_handshake = 1; -+ -+ dev_dbg(pxp->dev, "handshake %d, dither_wfe_a_handshake %d, " -+ "wfe_a_b_handshake %d, dither_bypass %d\n", -+ handshake, -+ dither_wfe_a_handshake, -+ wfe_a_b_handshake, -+ dither_bypass); -+ -+ if (handshake) { -+ /* for handshake, we only enable the last completion INT */ -+ if (wfe_b_enable) -+ __raw_writel(0x8000, pxp->base + HW_PXP_IRQ_MASK); -+ else if (wfe_a_enable) -+ __raw_writel(0x4000, pxp->base + HW_PXP_IRQ_MASK); -+ -+ /* Dither fetch */ -+ __raw_writel( -+ BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | -+ BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); -+ -+ if (dither_bypass) { -+ /* Dither store */ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); -+ -+ /* WFE_A fetch */ -+ __raw_writel( -+ BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(2) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFA_FETCH_CTRL); -+ -+ } else if (dither_wfe_a_handshake) { -+ /* Dither store */ -+ __raw_writel( -+ BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| -+ BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | -+ BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), -+ pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); -+ -+ /* WFE_A fetch */ -+ __raw_writel( -+ BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFA_FETCH_CTRL); -+ } -+ -+ if (wfe_a_b_handshake) { -+ /* WFE_A Store */ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), -+ pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); -+ -+ /* WFE_B fetch */ -+ __raw_writel( -+ BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | -+ BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), -+ pxp->base + HW_PXP_WFB_FETCH_CTRL); -+ } else { -+ /* WFE_A Store */ -+ __raw_writel( -+ BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| -+ BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), -+ pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); -+ } -+ -+ if (pxp_is_v3(pxp)) -+ val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | -+ BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable); -+ else if (pxp_is_v3p(pxp)) -+ val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | -+ wfe_b_enable); -+ -+ /* trigger operation */ -+ __raw_writel( -+ BF_PXP_CTRL_ENABLE(1) | -+ BF_PXP_CTRL_IRQ_ENABLE(0) | -+ BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | -+ BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | -+ BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(1) | -+ BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(1) | -+ BF_PXP_CTRL_ROTATE0(0) | -+ BF_PXP_CTRL_HFLIP0(0) | -+ BF_PXP_CTRL_VFLIP0(0) | -+ BF_PXP_CTRL_ROTATE1(0) | -+ BF_PXP_CTRL_HFLIP1(0) | -+ BF_PXP_CTRL_VFLIP1(0) | -+ BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | -+ BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | -+ BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | -+ BF_PXP_CTRL_ENABLE_ALPHA_B(0) | -+ BF_PXP_CTRL_BLOCK_SIZE(1) | -+ BF_PXP_CTRL_ENABLE_CSC2(0) | -+ BF_PXP_CTRL_ENABLE_LUT(1) | -+ BF_PXP_CTRL_ENABLE_ROTATE0(0) | -+ BF_PXP_CTRL_ENABLE_ROTATE1(0) | -+ BF_PXP_CTRL_EN_REPEAT(0) | -+ val, -+ pxp->base + HW_PXP_CTRL); -+ -+ return; -+ } -+ -+ if (pxp_is_v3(pxp)) -+ val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | -+ BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable) | -+ BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | -+ BF_PXP_CTRL_ENABLE_ALPHA_B(0); -+ else if (pxp_is_v3p(pxp)) -+ val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | -+ wfe_b_enable); -+ -+ __raw_writel( -+ BF_PXP_CTRL_ENABLE(1) | -+ BF_PXP_CTRL_IRQ_ENABLE(0) | -+ BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | -+ BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | -+ BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(0) | -+ BF_PXP_CTRL_ROTATE0(0) | -+ BF_PXP_CTRL_HFLIP0(0) | -+ BF_PXP_CTRL_VFLIP0(0) | -+ BF_PXP_CTRL_ROTATE1(0) | -+ BF_PXP_CTRL_HFLIP1(0) | -+ BF_PXP_CTRL_VFLIP1(0) | -+ BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | -+ BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | -+ BF_PXP_CTRL_BLOCK_SIZE(0) | -+ BF_PXP_CTRL_ENABLE_CSC2(0) | -+ BF_PXP_CTRL_ENABLE_LUT(0) | -+ BF_PXP_CTRL_ENABLE_ROTATE0(0) | -+ BF_PXP_CTRL_ENABLE_ROTATE1(0) | -+ BF_PXP_CTRL_EN_REPEAT(0) | -+ val, -+ pxp->base + HW_PXP_CTRL); -+ -+ if (pxp_is_v3(pxp)) -+ val = BF_PXP_CTRL2_ENABLE_WFE_A (0) | -+ BF_PXP_CTRL2_ENABLE_WFE_B (0) | -+ BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | -+ BF_PXP_CTRL2_ENABLE_ALPHA_B (0); -+ else if (pxp_is_v3p(pxp)) -+ val = BF_PXP_CTRL2_ENABLE_WFE_B(0); -+ -+ __raw_writel( -+ BF_PXP_CTRL2_ENABLE (0) | -+ BF_PXP_CTRL2_ROTATE0 (0) | -+ BF_PXP_CTRL2_HFLIP0 (0) | -+ BF_PXP_CTRL2_VFLIP0 (0) | -+ BF_PXP_CTRL2_ROTATE1 (0) | -+ BF_PXP_CTRL2_HFLIP1 (0) | -+ BF_PXP_CTRL2_VFLIP1 (0) | -+ BF_PXP_CTRL2_ENABLE_DITHER (0) | -+ BF_PXP_CTRL2_BLOCK_SIZE (0) | -+ BF_PXP_CTRL2_ENABLE_CSC2 (0) | -+ BF_PXP_CTRL2_ENABLE_LUT (0) | -+ BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | -+ BF_PXP_CTRL2_ENABLE_ROTATE1 (0), -+ pxp->base + HW_PXP_CTRL2); -+ -+ dump_pxp_reg2(pxp); -+} -+ -+static int pxp_dma_init(struct pxps *pxp) -+{ -+ struct pxp_dma *pxp_dma = &pxp->pxp_dma; -+ struct dma_device *dma = &pxp_dma->dma; -+ int i; -+ -+ dma_cap_set(DMA_SLAVE, dma->cap_mask); -+ dma_cap_set(DMA_PRIVATE, dma->cap_mask); -+ -+ /* Compulsory common fields */ -+ dma->dev = pxp->dev; -+ dma->device_alloc_chan_resources = pxp_alloc_chan_resources; -+ dma->device_free_chan_resources = pxp_free_chan_resources; -+ dma->device_tx_status = pxp_tx_status; -+ dma->device_issue_pending = pxp_issue_pending; -+ -+ /* Compulsory for DMA_SLAVE fields */ -+ dma->device_prep_slave_sg = pxp_prep_slave_sg; -+ dma->device_terminate_all = pxp_device_terminate_all; -+ -+ /* Initialize PxP Channels */ -+ INIT_LIST_HEAD(&dma->channels); -+ for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { -+ struct pxp_channel *pxp_chan = pxp->channel + i; -+ struct dma_chan *dma_chan = &pxp_chan->dma_chan; -+ -+ spin_lock_init(&pxp_chan->lock); -+ -+ /* Only one EOF IRQ for PxP, shared by all channels */ -+ pxp_chan->eof_irq = pxp->irq; -+ pxp_chan->status = PXP_CHANNEL_FREE; -+ pxp_chan->completed = -ENXIO; -+ snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), -+ "PXP EOF %d", i); -+ -+ dma_chan->device = &pxp_dma->dma; -+ dma_chan->cookie = 1; -+ dma_chan->chan_id = i; -+ list_add_tail(&dma_chan->device_node, &dma->channels); -+ } -+ -+ return dma_async_device_register(&pxp_dma->dma); -+} -+ -+static ssize_t clk_off_timeout_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", timeout_in_ms); -+} -+ -+static ssize_t clk_off_timeout_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ int val; -+ if (sscanf(buf, "%d", &val) > 0) { -+ timeout_in_ms = val; -+ return count; -+ } -+ return -EINVAL; -+} -+ -+static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, -+ clk_off_timeout_store); -+ -+static ssize_t block_size_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ return sprintf(buf, "%d\n", block_size); -+} -+ -+static ssize_t block_size_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ char **last = NULL; -+ -+ block_size = simple_strtoul(buf, last, 0); -+ if (block_size > 1) -+ block_size = 1; -+ -+ return count; -+} -+static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, -+ block_size_show, block_size_store); -+ -+static struct platform_device_id imx_pxpdma_devtype[] = { -+ { -+ .name = "imx7d-pxp-dma", -+ .driver_data = PXP_V3, -+ }, { -+ .name = "imx6ull-pxp-dma", -+ .driver_data = PXP_V3P, -+ }, { -+ .name = "imx8ulp-pxp-dma", -+ .driver_data = PXP_V3_8ULP, -+ }, { -+ /* sentinel */ -+ } -+}; -+MODULE_DEVICE_TABLE(platform, imx_pxpdma_devtype); -+ -+static const struct of_device_id imx_pxpdma_dt_ids[] = { -+ { .compatible = "fsl,imx7d-pxp-dma", .data = &imx_pxpdma_devtype[0], }, -+ { .compatible = "fsl,imx6ull-pxp-dma", .data = &imx_pxpdma_devtype[1], }, -+ { .compatible = "fsl,imx8ulp-pxp-dma", .data = &imx_pxpdma_devtype[2], }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); -+ -+static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) -+{ -+ int found; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ found = !list_empty(&head); -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ -+ return found; -+} -+ -+static int pxp_dispatch_thread(void *argv) -+{ -+ struct pxps *pxp = (struct pxps *)argv; -+ struct pxp_channel *pending = NULL; -+ unsigned long flags; -+ -+ set_freezable(); -+ -+ while (!kthread_should_stop()) { -+ int ret; -+ ret = wait_event_freezable(pxp->thread_waitq, -+ has_pending_task(pxp, pending) || -+ kthread_should_stop()); -+ if (ret < 0) -+ continue; -+ -+ if (kthread_should_stop()) -+ break; -+ -+ spin_lock_irqsave(&pxp->lock, flags); -+ pxp->pxp_ongoing = 1; -+ spin_unlock_irqrestore(&pxp->lock, flags); -+ init_completion(&pxp->complete); -+ ret = pxpdma_dostart_work(pxp); -+ if (ret) { -+ pxp->pxp_ongoing = 0; -+ continue; -+ } -+ ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); -+ if (ret == 0) { -+ printk(KERN_EMERG "%s: task is timeout\n\n", __func__); -+ break; -+ } -+ if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) -+ pxp->devdata->pxp_lut_cleanup_multiple(pxp, 0, 0); -+ } -+ -+ return 0; -+} -+ -+static int pxp_init_interrupt(struct platform_device *pdev) -+{ -+ int legacy_irq, std_irq, err; -+ struct pxps *pxp = platform_get_drvdata(pdev); -+ int irq_cnt = 0; -+ -+ irq_cnt = platform_irq_count(pdev); -+ switch (irq_cnt) { -+ case 2: -+ std_irq = platform_get_irq(pdev, 1); -+ if (std_irq < 0) { -+ dev_err(&pdev->dev, "failed to get pxp standard irq: %d\n", -+ std_irq); -+ return std_irq; -+ } -+ err = devm_request_irq(&pdev->dev, std_irq, pxp_irq, 0, -+ "pxp-dmaengine-std", pxp); -+ if (err) { -+ dev_err(&pdev->dev, "Request pxp standard irq failed: %d\n", -+ err); -+ return err; -+ } -+ fallthrough; -+ case 1: -+ legacy_irq = platform_get_irq(pdev, 0); -+ if (legacy_irq < 0) { -+ dev_err(&pdev->dev, "failed to get pxp legacy irq: %d\n", -+ legacy_irq); -+ return legacy_irq; -+ } -+ err = devm_request_irq(&pdev->dev, legacy_irq, pxp_irq, 0, -+ "pxp-dmaengine-legacy", pxp); -+ if (err) { -+ dev_err(&pdev->dev, "Request pxp legacy irq failed: %d\n", err); -+ return -ENXIO; -+ } -+ break; -+ default: -+ pr_err("failed to get pxp irq count=(%d)\n", irq_cnt); -+ return -EINVAL; -+ } -+ -+ pxp->irq = legacy_irq; -+ -+ /* enable all the possible irq raised by PXP */ -+ __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); -+ -+ return 0; -+} -+ -+static int pxp_create_attrs(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ if ((ret = device_create_file(&pdev->dev, &dev_attr_clk_off_timeout))) { -+ dev_err(&pdev->dev, -+ "Unable to create file from clk_off_timeout\n"); -+ return ret; -+ } -+ -+ if ((ret = device_create_file(&pdev->dev, &dev_attr_block_size))) { -+ device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); -+ -+ dev_err(&pdev->dev, -+ "Unable to create file from block_size\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void pxp_remove_attrs(struct platform_device *pdev) -+{ -+ device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); -+ device_remove_file(&pdev->dev, &dev_attr_block_size); -+} -+ -+static void pxp_init_timer(struct pxps *pxp) -+{ -+ INIT_WORK(&pxp->work, clkoff_callback); -+ -+ timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); -+} -+ -+static bool is_mux_node(uint32_t node_id) -+{ -+ if ((node_id < PXP_2D_MUX_MUX0) || -+ (node_id > PXP_2D_MUX_MUX15)) -+ return false; -+ -+ return true; -+} -+ -+static bool search_mux_chain(uint32_t mux_id, -+ struct edge_node *enode) -+{ -+ bool found = false; -+ uint32_t i, j, next_mux = 0; -+ uint32_t output; -+ struct mux *muxes; -+ -+ muxes = (v3p_flag) ? muxes_v3p : muxes_v3; -+ -+ for (i = 0; i < 2; i++) { -+ output = muxes[mux_id].mux_outputs[i]; -+ if (output == 0xff) -+ break; -+ -+ if ((output == enode->adjvex)) { -+ /* found */ -+ found = true; -+ break; -+ } else if (is_mux_node(output)) { -+ next_mux = output - PXP_2D_MUX_BASE; -+ found = search_mux_chain(next_mux, enode); -+ -+ if (found) { -+ for (j = 0; j < 4; j++) { -+ if (muxes[next_mux].mux_inputs[j] == -+ (mux_id + PXP_2D_MUX_BASE)) -+ break; -+ } -+ -+ set_bit(next_mux, (unsigned long *)&enode->mux_used); -+ set_mux_val(&enode->muxes, next_mux, j); -+ break; -+ } -+ } -+ } -+ -+ return found; -+} -+ -+static void enode_mux_config(unsigned int vnode_id, -+ struct edge_node *enode) -+{ -+ uint32_t i, j; -+ bool via_mux = false, need_search = false; -+ struct mux *muxes; -+ -+ BUG_ON(vnode_id >= PXP_2D_NUM); -+ BUG_ON(enode->adjvex >= PXP_2D_NUM); -+ -+ muxes = (v3p_flag) ? muxes_v3p : muxes_v3; -+ -+ for (i = 0; i < 16; i++) { -+ for (j = 0; j < 4; j++) { -+ if (muxes[i].mux_inputs[j] == 0xff) -+ break; -+ -+ if (muxes[i].mux_inputs[j] == vnode_id) -+ need_search = true; -+ else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA0_S0_S1) { -+ if ((vnode_id == PXP_2D_ALPHA0_S0) || -+ (vnode_id == PXP_2D_ALPHA0_S1)) -+ need_search = true; -+ } else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA1_S0_S1) { -+ if ((vnode_id == PXP_2D_ALPHA1_S0) || -+ (vnode_id == PXP_2D_ALPHA1_S1)) -+ need_search = true; -+ } -+ -+ if (need_search) { -+ via_mux = search_mux_chain(i, enode); -+ need_search = false; -+ break; -+ } -+ } -+ -+ if (via_mux) { -+ set_bit(i, (unsigned long *)&enode->mux_used); -+ set_mux_val(&enode->muxes, i, j); -+ break; -+ } -+ } -+} -+ -+static int pxp_create_initial_graph(struct platform_device *pdev) -+{ -+ int i, j, first; -+ static bool (*adj_array)[PXP_2D_NUM]; -+ struct edge_node *enode, *curr = NULL; -+ -+ adj_array = (v3p_flag) ? adj_array_v3p : adj_array_v3; -+ -+ for (i = 0; i < PXP_2D_NUM; i++) { -+ switch (i) { -+ case PXP_2D_PS: -+ case PXP_2D_AS: -+ case PXP_2D_INPUT_FETCH0: -+ case PXP_2D_INPUT_FETCH1: -+ adj_list[i].type = PXP_2D_TYPE_INPUT; -+ break; -+ case PXP_2D_OUT: -+ case PXP_2D_INPUT_STORE0: -+ case PXP_2D_INPUT_STORE1: -+ adj_list[i].type = PXP_2D_TYPE_OUTPUT; -+ break; -+ default: -+ adj_list[i].type = PXP_2D_TYPE_ALU; -+ break; -+ } -+ -+ first = -1; -+ -+ for (j = 0; j < PXP_2D_NUM; j++) { -+ if (adj_array[i][j]) { -+ enode = kmem_cache_alloc(edge_node_cache, -+ GFP_KERNEL | __GFP_ZERO); -+ if (!enode) { -+ dev_err(&pdev->dev, "allocate edge node failed\n"); -+ return -ENOMEM; -+ } -+ enode->adjvex = j; -+ enode->prev_vnode = i; -+ -+ if (unlikely(first == -1)) { -+ first = j; -+ adj_list[i].first = enode; -+ } else -+ curr->next = enode; -+ -+ curr = enode; -+ enode_mux_config(i, enode); -+ dev_dbg(&pdev->dev, "(%d -> %d): mux_used 0x%x, mux_config 0x%x\n\n", -+ i, j, enode->mux_used, *(unsigned int*)&enode->muxes); -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+/* Calculate the shortest paths start via -+ * 'from' node to other nodes -+ */ -+static void pxp_find_shortest_path(unsigned int from) -+{ -+ int i; -+ struct edge_node *enode; -+ struct path_node *pnode, *adjnode; -+ struct list_head queue; -+ -+ INIT_LIST_HEAD(&queue); -+ list_add_tail(&path_table[from][from].node, &queue); -+ -+ while(!list_empty(&queue)) { -+ pnode = list_entry(queue.next, struct path_node, node); -+ enode = adj_list[pnode->id].first; -+ while (enode) { -+ adjnode = &path_table[from][enode->adjvex]; -+ -+ if (adjnode->distance == DISTANCE_INFINITY) { -+ adjnode->distance = pnode->distance + 1; -+ adjnode->prev_node = pnode->id; -+ list_add_tail(&adjnode->node, &queue); -+ } -+ -+ enode = enode->next; -+ } -+ list_del_init(&pnode->node); -+ } -+ -+ for (i = 0; i < PXP_2D_NUM; i++) -+ pr_debug("From %u: to %d (id = %d, distance = 0x%x, prev_node = %d\n", -+ from, i, path_table[from][i].id, path_table[from][i].distance, -+ path_table[from][i].prev_node); -+} -+ -+static int pxp_gen_shortest_paths(struct platform_device *pdev) -+{ -+ int i, j; -+ -+ for (i = 0; i < PXP_2D_NUM; i++) { -+ for (j = 0; j < PXP_2D_NUM; j++) { -+ path_table[i][j].id = j; -+ path_table[i][j].distance = DISTANCE_INFINITY; -+ path_table[i][j].prev_node = NO_PATH_NODE; -+ INIT_LIST_HEAD(&path_table[i][j].node); -+ } -+ -+ path_table[i][i].distance = 0; -+ -+ pxp_find_shortest_path(i); -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_MXC_FPGA_M4_TEST -+static void pxp_config_m4(struct platform_device *pdev) -+{ -+ fpga_tcml_base = ioremap(FPGA_TCML_ADDR, SZ_32K); -+ if (fpga_tcml_base == NULL) { -+ dev_err(&pdev->dev, -+ "get fpga_tcml_base error.\n"); -+ goto exit; -+ } -+ pinctrl_base = ioremap(PINCTRL, SZ_4K); -+ if (pinctrl_base == NULL) { -+ dev_err(&pdev->dev, -+ "get fpga_tcml_base error.\n"); -+ goto exit; -+ } -+ -+ __raw_writel(0xC0000000, pinctrl_base + 0x08); -+ __raw_writel(0x3, pinctrl_base + PIN_DOUT); -+ int i; -+ -+ for (i = 0; i < 1024 * 32 / 4; i++) -+ *(((unsigned int *)(fpga_tcml_base)) + i) = cm4_image[i]; -+} -+#endif -+ -+static int pxp_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *of_id = -+ of_match_device(imx_pxpdma_dt_ids, &pdev->dev); -+ struct pxps *pxp; -+ struct resource *res; -+ int err = 0; -+ -+ if (of_id) -+ pdev->id_entry = of_id->data; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); -+ if (!pxp) { -+ dev_err(&pdev->dev, "failed to allocate control object\n"); -+ err = -ENOMEM; -+ goto exit; -+ } -+ -+ pxp->dev = &pdev->dev; -+ -+ platform_set_drvdata(pdev, pxp); -+ -+ spin_lock_init(&pxp->lock); -+ mutex_init(&pxp->clk_mutex); -+ -+ pxp->base = devm_ioremap_resource(&pdev->dev, res); -+ if (pxp->base == NULL) { -+ dev_err(&pdev->dev, "Couldn't ioremap regs\n"); -+ err = -ENODEV; -+ goto exit; -+ } -+ pxp_reg_base = pxp->base; -+ -+ pxp->pdev = pdev; -+ pxp->devdata = &pxp_devdata[pdev->id_entry->driver_data]; -+ -+ v3p_flag = (pxp_is_v3p(pxp)) ? true : false; -+ -+ pxp->ipg_clk = devm_clk_get(&pdev->dev, "pxp_ipg"); -+ pxp->axi_clk = devm_clk_get(&pdev->dev, "pxp_axi"); -+ -+ if (IS_ERR(pxp->ipg_clk) || IS_ERR(pxp->axi_clk)) { -+ dev_err(&pdev->dev, "pxp clocks invalid\n"); -+ err = -EINVAL; -+ goto exit; -+ } -+ -+ pxp_clk_enable(pxp); -+ pxp_soft_reset(pxp); -+ pxp_writel(0x0, HW_PXP_CTRL); -+ /* Initialize DMA engine */ -+ err = pxp_dma_init(pxp); -+ if (err < 0) -+ goto exit; -+ -+ pxp_soft_reset(pxp); -+ -+ /* Initialize PXP Interrupt */ -+ err = pxp_init_interrupt(pdev); -+ if (err < 0) -+ goto exit; -+ -+ if (pxp->devdata && pxp->devdata->pxp_data_path_config) -+ pxp->devdata->pxp_data_path_config(pxp); -+ /* enable all the possible irq raised by PXP */ -+ __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); -+ -+ dump_pxp_reg(pxp); -+ pxp_clk_disable(pxp); -+ -+ pxp_init_timer(pxp); -+ -+ init_waitqueue_head(&pxp->thread_waitq); -+ /* allocate a kernel thread to dispatch pxp conf */ -+ pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); -+ if (IS_ERR(pxp->dispatch)) { -+ err = PTR_ERR(pxp->dispatch); -+ goto exit; -+ } -+ tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), -+ 0, SLAB_HWCACHE_ALIGN, NULL); -+ if (!tx_desc_cache) { -+ err = -ENOMEM; -+ goto exit; -+ } -+ -+ edge_node_cache = kmem_cache_create("edge_node", sizeof(struct edge_node), -+ 0, SLAB_HWCACHE_ALIGN, NULL); -+ if (!edge_node_cache) { -+ err = -ENOMEM; -+ kmem_cache_destroy(tx_desc_cache); -+ goto exit; -+ } -+ -+ err = pxp_create_attrs(pdev); -+ if (err) { -+ kmem_cache_destroy(tx_desc_cache); -+ kmem_cache_destroy(edge_node_cache); -+ goto exit; -+ } -+ -+ if ((err = pxp_create_initial_graph(pdev))) { -+ kmem_cache_destroy(tx_desc_cache); -+ kmem_cache_destroy(edge_node_cache); -+ goto exit; -+ } -+ -+ pxp_gen_shortest_paths(pdev); -+ -+#ifdef CONFIG_MXC_FPGA_M4_TEST -+ pxp_config_m4(pdev); -+#endif -+ register_pxp_device(); -+ pm_runtime_enable(pxp->dev); -+ -+exit: -+ if (err) -+ dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); -+ return err; -+} -+ -+static int pxp_remove(struct platform_device *pdev) -+{ -+ struct pxps *pxp = platform_get_drvdata(pdev); -+ -+ unregister_pxp_device(); -+ kmem_cache_destroy(tx_desc_cache); -+ kmem_cache_destroy(edge_node_cache); -+ kthread_stop(pxp->dispatch); -+ cancel_work_sync(&pxp->work); -+ del_timer_sync(&pxp->clk_timer); -+ clk_disable_unprepare(pxp->ipg_clk); -+ clk_disable_unprepare(pxp->axi_clk); -+ pxp_remove_attrs(pdev); -+ dma_async_device_unregister(&(pxp->pxp_dma.dma)); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+static int pxp_suspend(struct device *dev) -+{ -+ struct pxps *pxp = dev_get_drvdata(dev); -+ -+ pxp_clk_enable(pxp); -+ while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) -+ ; -+ -+ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); -+ pxp_clk_disable(pxp); -+ -+ return 0; -+} -+ -+static int pxp_resume(struct device *dev) -+{ -+ struct pxps *pxp = dev_get_drvdata(dev); -+ -+ pxp_clk_enable(pxp); -+ /* Pull PxP out of reset */ -+ pxp_soft_reset(pxp); -+ if (pxp->devdata && pxp->devdata->pxp_data_path_config) -+ pxp->devdata->pxp_data_path_config(pxp); -+ /* enable all the possible irq raised by PXP */ -+ __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); -+ pxp_clk_disable(pxp); -+ -+ return 0; -+} -+#else -+#define pxp_suspend NULL -+#define pxp_resume NULL -+#endif -+ -+#ifdef CONFIG_PM -+static int pxp_runtime_suspend(struct device *dev) -+{ -+ dev_dbg(dev, "pxp busfreq high release.\n"); -+ -+ return 0; -+} -+ -+static int pxp_runtime_resume(struct device *dev) -+{ -+ dev_dbg(dev, "pxp busfreq high request.\n"); -+ -+ return 0; -+} -+#else -+#define pxp_runtime_suspend NULL -+#define pxp_runtime_resume NULL -+#endif -+ -+static const struct dev_pm_ops pxp_pm_ops = { -+ SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) -+}; -+ -+static struct platform_driver pxp_driver = { -+ .driver = { -+ .name = "imx-pxp-v3", -+ .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), -+ .pm = &pxp_pm_ops, -+ }, -+ .probe = pxp_probe, -+ .remove = pxp_remove, -+}; -+ -+static int __init pxp_init(void) -+{ -+ return platform_driver_register(&pxp_driver); -+} -+late_initcall(pxp_init); -+ -+static void __exit pxp_exit(void) -+{ -+ platform_driver_unregister(&pxp_driver); -+} -+module_exit(pxp_exit); -+ -+ -+MODULE_DESCRIPTION("i.MX PxP driver"); -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/dma/pxp/reg_bitfields.h b/drivers/dma/pxp/reg_bitfields.h -new file mode 100644 -index 000000000..0acb83d8e ---- /dev/null -+++ b/drivers/dma/pxp/reg_bitfields.h -@@ -0,0 +1,266 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _REG_BITFIELDS_H -+#define _REG_BITFIELDS_H -+struct mux_config { -+ uint32_t mux0_sel : 2; -+ uint32_t mux1_sel : 2; -+ uint32_t mux2_sel : 2; -+ uint32_t mux3_sel : 2; -+ uint32_t mux4_sel : 2; -+ uint32_t mux5_sel : 2; -+ uint32_t mux6_sel : 2; -+ uint32_t mux7_sel : 2; -+ uint32_t mux8_sel : 2; -+ uint32_t mux9_sel : 2; -+ uint32_t mux10_sel : 2; -+ uint32_t mux11_sel : 2; -+ uint32_t mux12_sel : 2; -+ uint32_t mux13_sel : 2; -+ uint32_t mux14_sel : 2; -+ uint32_t mux15_sel : 2; -+}; -+ -+/* legacy engine registers */ -+struct ps_ctrl { -+ uint32_t format : 6; -+ uint32_t wb_swap : 1; -+ uint32_t rsvd0 : 1; -+ uint32_t decy : 2; -+ uint32_t decx : 2; -+ uint32_t rsvd1 : 20; -+}; -+ -+struct ps_scale { -+ uint32_t xscale : 15; -+ uint32_t rsvd1 : 1; -+ uint32_t yscale : 15; -+ uint32_t rsvd2 : 1; -+}; -+ -+struct ps_offset { -+ uint32_t xoffset : 12; -+ uint32_t rsvd1 : 4; -+ uint32_t yoffset : 12; -+ uint32_t rsvd2 : 4; -+}; -+ -+struct as_ctrl { -+ uint32_t rsvd0 : 1; -+ uint32_t alpha_ctrl : 2; -+ uint32_t enable_colorkey : 1; -+ uint32_t format : 4; -+ uint32_t alpha : 8; -+ uint32_t rop : 4; -+ uint32_t alpha0_invert : 1; -+ uint32_t alpha1_invert : 1; -+ uint32_t rsvd1 : 10; -+}; -+ -+struct out_ctrl { -+ uint32_t format : 5; -+ uint32_t rsvd0 : 3; -+ uint32_t interlaced_output : 2; -+ uint32_t rsvd1 : 13; -+ uint32_t alpha_output : 1; -+ uint32_t alpha : 8; -+}; -+ -+struct coordinate { -+ uint32_t y : 14; -+ uint32_t rsvd0 : 2; -+ uint32_t x : 14; -+ uint32_t rsvd1 : 2; -+}; -+ -+struct pxp_alpha_ctrl { -+ uint32_t poter_duff_enable : 1; -+ uint32_t s0_s1_factor_mode : 2; -+ uint32_t s0_global_alpha_mode : 2; -+ uint32_t s0_alpha_mode : 1; -+ uint32_t s0_color_mode : 1; -+ uint32_t rsvd1 : 1; -+ uint32_t s1_s0_factor_mode : 2; -+ uint32_t s1_global_alpha_mode : 2; -+ uint32_t s1_alpha_mode : 1; -+ uint32_t s1_color_mode : 1; -+ uint32_t rsvd0 : 2; -+ uint32_t s0_global_alpha : 8; -+ uint32_t s1_global_alpha : 8; -+}; -+ -+/* store engine registers */ -+struct store_ctrl { -+ uint32_t ch_en : 1; -+ uint32_t block_en : 1; -+ uint32_t block_16 : 1; -+ uint32_t handshake_en : 1; -+ uint32_t array_en : 1; -+ uint32_t array_line_num : 2; -+ uint32_t rsvd3 : 1; -+ uint32_t store_bypass_en : 1; -+ uint32_t store_memory_en : 1; -+ uint32_t pack_in_sel : 1; -+ uint32_t fill_data_en : 1; -+ uint32_t rsvd2 : 4; -+ uint32_t wr_num_bytes : 2; -+ uint32_t rsvd1 : 6; -+ uint32_t combine_2channel : 1; -+ uint32_t rsvd0 : 6; -+ uint32_t arbit_en : 1; -+}; -+ -+struct store_size { -+ uint32_t out_width : 16; -+ uint32_t out_height : 16; -+}; -+ -+struct store_pitch { -+ uint32_t ch0_out_pitch : 16; -+ uint32_t ch1_out_pitch : 16; -+}; -+ -+struct store_shift_ctrl { -+ uint32_t rsvd2 : 2; -+ uint32_t output_active_bpp : 2; -+ uint32_t out_yuv422_1p_en : 1; -+ uint32_t out_yuv422_2p_en : 1; -+ uint32_t rsvd1 : 1; -+ uint32_t shift_bypass : 1; -+ uint32_t rsvd0 : 24; -+}; -+ -+struct store_d_shift { -+ uint64_t d_shift_width0 : 6; -+ uint64_t rsvd3 : 1; -+ uint64_t d_shift_flag0 : 1; -+ uint64_t d_shift_width1 : 6; -+ uint64_t rsvd2 : 1; -+ uint64_t d_shift_flag1 : 1; -+ uint64_t d_shift_width2 : 6; -+ uint64_t rsvd1 : 1; -+ uint64_t d_shift_flag2 : 1; -+ uint64_t d_shift_width3 : 6; -+ uint64_t rsvd0 : 1; -+ uint64_t d_shift_flag3 : 1; -+ -+ uint64_t d_shift_width4 : 6; -+ uint64_t rsvd7 : 1; -+ uint64_t d_shift_flag4 : 1; -+ uint64_t d_shift_width5 : 6; -+ uint64_t rsvd6 : 1; -+ uint64_t d_shift_flag5 : 1; -+ uint64_t d_shift_width6 : 6; -+ uint64_t rsvd5 : 1; -+ uint64_t d_shift_flag6 : 1; -+ uint64_t d_shift_width7 : 6; -+ uint64_t rsvd4 : 1; -+ uint64_t d_shift_flag7 : 1; -+}; -+ -+struct store_f_shift { -+ uint64_t f_shift_width0 : 6; -+ uint64_t rsvd3 : 1; -+ uint64_t f_shift_flag0 : 1; -+ uint64_t f_shift_width1 : 6; -+ uint64_t rsvd2 : 1; -+ uint64_t f_shift_flag1 : 1; -+ uint64_t f_shift_width2 : 6; -+ uint64_t rsvd1 : 1; -+ uint64_t f_shift_flag2 : 1; -+ uint64_t f_shift_width3 : 6; -+ uint64_t rsvd0 : 1; -+ uint64_t f_shift_flag3 : 1; -+ -+ uint64_t f_shift_width4 : 6; -+ uint64_t rsvd7 : 1; -+ uint64_t f_shift_flag4 : 1; -+ uint64_t f_shift_width5 : 6; -+ uint64_t rsvd6 : 1; -+ uint64_t f_shift_flag5 : 1; -+ uint64_t f_shift_width6 : 6; -+ uint64_t rsvd5 : 1; -+ uint64_t f_shift_flag6 : 1; -+ uint64_t f_shift_width7 : 6; -+ uint64_t rsvd4 : 1; -+ uint64_t f_shift_flag7 : 1; -+}; -+ -+struct store_d_mask { -+ uint64_t d_mask_l : 32; -+ uint64_t d_mask_h : 32; -+}; -+ -+/* fetch engine registers */ -+struct fetch_ctrl { -+ uint32_t ch_en : 1; -+ uint32_t block_en : 1; -+ uint32_t block_16 : 1; -+ uint32_t handshake_en : 1; -+ uint32_t bypass_pixel_en : 1; -+ uint32_t high_byte : 1; -+ uint32_t rsvd4 : 3; -+ uint32_t hflip : 1; -+ uint32_t vflip : 1; -+ uint32_t rsvd3 : 1; -+ uint32_t rotation_angle : 2; -+ uint32_t rsvd2 : 2; -+ uint32_t rd_num_bytes : 2; -+ uint32_t rsvd1 : 6; -+ uint32_t handshake_scan_line_num : 2; -+ uint32_t rsvd0 : 5; -+ uint32_t arbit_en : 1; -+}; -+ -+struct fetch_active_size_ulc { -+ uint32_t active_size_ulc_x : 16; -+ uint32_t active_size_ulc_y : 16; -+}; -+ -+struct fetch_active_size_lrc { -+ uint32_t active_size_lrc_x : 16; -+ uint32_t active_size_lrc_y : 16; -+}; -+ -+struct fetch_size { -+ uint32_t input_total_width : 16; -+ uint32_t input_total_height : 16; -+}; -+ -+struct fetch_pitch { -+ uint32_t ch0_input_pitch : 16; -+ uint32_t ch1_input_pitch : 16; -+}; -+ -+struct fetch_shift_ctrl { -+ uint32_t input_active_bpp : 2; -+ uint32_t rsvd1 : 6; -+ uint32_t expand_format : 3; -+ uint32_t expand_en : 1; -+ uint32_t shift_bypass : 1; -+ uint32_t rsvd0 : 19; -+}; -+ -+struct fetch_shift_offset { -+ uint32_t offset0 : 5; -+ uint32_t rsvd3 : 3; -+ uint32_t offset1 : 5; -+ uint32_t rsvd2 : 3; -+ uint32_t offset2 : 5; -+ uint32_t rsvd1 : 3; -+ uint32_t offset3 : 5; -+ uint32_t rsvd0 : 3; -+}; -+ -+struct fetch_shift_width { -+ uint32_t width0 : 4; -+ uint32_t width1 : 4; -+ uint32_t width2 : 4; -+ uint32_t width3 : 4; -+ uint32_t rsvd0 : 16; -+}; -+#endif -diff --git a/drivers/dma/pxp/regs-pxp_v2.h b/drivers/dma/pxp/regs-pxp_v2.h -new file mode 100644 -index 000000000..0e2ef8933 ---- /dev/null -+++ b/drivers/dma/pxp/regs-pxp_v2.h -@@ -0,0 +1,1139 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Freescale PXP Register Definitions -+ * -+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ * -+ * This file is created by xml file. Don't Edit it. -+ * -+ * Xml Revision: 1.29 -+ * Template revision: 1.3 -+ */ -+ -+#ifndef __ARCH_ARM___PXP_H -+#define __ARCH_ARM___PXP_H -+ -+#define HW_PXP_CTRL (0x00000000) -+#define HW_PXP_CTRL_SET (0x00000004) -+#define HW_PXP_CTRL_CLR (0x00000008) -+#define HW_PXP_CTRL_TOG (0x0000000c) -+ -+#define BM_PXP_CTRL_SFTRST 0x80000000 -+#define BM_PXP_CTRL_CLKGATE 0x40000000 -+#define BM_PXP_CTRL_RSVD4 0x20000000 -+#define BM_PXP_CTRL_EN_REPEAT 0x10000000 -+#define BP_PXP_CTRL_RSVD3 26 -+#define BM_PXP_CTRL_RSVD3 0x0C000000 -+#define BF_PXP_CTRL_RSVD3(v) \ -+ (((v) << 26) & BM_PXP_CTRL_RSVD3) -+#define BP_PXP_CTRL_INTERLACED_INPUT 24 -+#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 -+#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ -+ (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) -+#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 -+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 -+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 -+#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 -+#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 -+#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 -+#define BM_PXP_CTRL_ROT_POS 0x00400000 -+#define BM_PXP_CTRL_IN_PLACE 0x00200000 -+#define BP_PXP_CTRL_RSVD1 12 -+#define BM_PXP_CTRL_RSVD1 0x001FF000 -+#define BF_PXP_CTRL_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_CTRL_RSVD1) -+#define BM_PXP_CTRL_VFLIP 0x00000800 -+#define BM_PXP_CTRL_HFLIP 0x00000400 -+#define BP_PXP_CTRL_ROTATE 8 -+#define BM_PXP_CTRL_ROTATE 0x00000300 -+#define BF_PXP_CTRL_ROTATE(v) \ -+ (((v) << 8) & BM_PXP_CTRL_ROTATE) -+#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 -+#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 -+#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 -+#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 -+#define BP_PXP_CTRL_RSVD0 5 -+#define BM_PXP_CTRL_RSVD0 0x000000E0 -+#define BF_PXP_CTRL_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_CTRL_RSVD0) -+#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010 -+#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 -+#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 -+#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -+#define BM_PXP_CTRL_ENABLE 0x00000001 -+ -+#define HW_PXP_STAT (0x00000010) -+#define HW_PXP_STAT_SET (0x00000014) -+#define HW_PXP_STAT_CLR (0x00000018) -+#define HW_PXP_STAT_TOG (0x0000001c) -+ -+#define BP_PXP_STAT_BLOCKX 24 -+#define BM_PXP_STAT_BLOCKX 0xFF000000 -+#define BF_PXP_STAT_BLOCKX(v) \ -+ (((v) << 24) & BM_PXP_STAT_BLOCKX) -+#define BP_PXP_STAT_BLOCKY 16 -+#define BM_PXP_STAT_BLOCKY 0x00FF0000 -+#define BF_PXP_STAT_BLOCKY(v) \ -+ (((v) << 16) & BM_PXP_STAT_BLOCKY) -+#define BP_PXP_STAT_RSVD2 9 -+#define BM_PXP_STAT_RSVD2 0x0000FE00 -+#define BF_PXP_STAT_RSVD2(v) \ -+ (((v) << 9) & BM_PXP_STAT_RSVD2) -+#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 -+#define BP_PXP_STAT_AXI_ERROR_ID 4 -+#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 -+#define BF_PXP_STAT_AXI_ERROR_ID(v) \ -+ (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) -+#define BM_PXP_STAT_NEXT_IRQ 0x00000008 -+#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 -+#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 -+#define BM_PXP_STAT_IRQ 0x00000001 -+ -+#define HW_PXP_OUT_CTRL (0x00000020) -+#define HW_PXP_OUT_CTRL_SET (0x00000024) -+#define HW_PXP_OUT_CTRL_CLR (0x00000028) -+#define HW_PXP_OUT_CTRL_TOG (0x0000002c) -+ -+#define BP_PXP_OUT_CTRL_ALPHA 24 -+#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 -+#define BF_PXP_OUT_CTRL_ALPHA(v) \ -+ (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) -+#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 -+#define BP_PXP_OUT_CTRL_RSVD1 10 -+#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 -+#define BF_PXP_OUT_CTRL_RSVD1(v) \ -+ (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) -+#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 -+#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 -+#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ -+ (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 -+#define BP_PXP_OUT_CTRL_RSVD0 5 -+#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 -+#define BF_PXP_OUT_CTRL_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) -+#define BP_PXP_OUT_CTRL_FORMAT 0 -+#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F -+#define BF_PXP_OUT_CTRL_FORMAT(v) \ -+ (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) -+#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 -+#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 -+#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 -+#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 -+#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 -+#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC -+#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD -+#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE -+#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 -+#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 -+#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 -+#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 -+#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 -+#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 -+#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 -+#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A -+#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B -+ -+#define HW_PXP_OUT_BUF (0x00000030) -+ -+#define BP_PXP_OUT_BUF_ADDR 0 -+#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_OUT_BUF_ADDR(v) (v) -+ -+#define HW_PXP_OUT_BUF2 (0x00000040) -+ -+#define BP_PXP_OUT_BUF2_ADDR 0 -+#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF -+#define BF_PXP_OUT_BUF2_ADDR(v) (v) -+ -+#define HW_PXP_OUT_PITCH (0x00000050) -+ -+#define BP_PXP_OUT_PITCH_RSVD 16 -+#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_OUT_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) -+#define BP_PXP_OUT_PITCH_PITCH 0 -+#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_OUT_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) -+ -+#define HW_PXP_OUT_LRC (0x00000060) -+ -+#define BP_PXP_OUT_LRC_RSVD1 30 -+#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_LRC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) -+#define BP_PXP_OUT_LRC_X 16 -+#define BM_PXP_OUT_LRC_X 0x3FFF0000 -+#define BF_PXP_OUT_LRC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_LRC_X) -+#define BP_PXP_OUT_LRC_RSVD0 14 -+#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_LRC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) -+#define BP_PXP_OUT_LRC_Y 0 -+#define BM_PXP_OUT_LRC_Y 0x00003FFF -+#define BF_PXP_OUT_LRC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_LRC_Y) -+ -+#define HW_PXP_OUT_PS_ULC (0x00000070) -+ -+#define BP_PXP_OUT_PS_ULC_RSVD1 30 -+#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) -+#define BP_PXP_OUT_PS_ULC_X 16 -+#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 -+#define BF_PXP_OUT_PS_ULC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_PS_ULC_X) -+#define BP_PXP_OUT_PS_ULC_RSVD0 14 -+#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) -+#define BP_PXP_OUT_PS_ULC_Y 0 -+#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF -+#define BF_PXP_OUT_PS_ULC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) -+ -+#define HW_PXP_OUT_PS_LRC (0x00000080) -+ -+#define BP_PXP_OUT_PS_LRC_RSVD1 30 -+#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) -+#define BP_PXP_OUT_PS_LRC_X 16 -+#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 -+#define BF_PXP_OUT_PS_LRC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_PS_LRC_X) -+#define BP_PXP_OUT_PS_LRC_RSVD0 14 -+#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) -+#define BP_PXP_OUT_PS_LRC_Y 0 -+#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF -+#define BF_PXP_OUT_PS_LRC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) -+ -+#define HW_PXP_OUT_AS_ULC (0x00000090) -+ -+#define BP_PXP_OUT_AS_ULC_RSVD1 30 -+#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) -+#define BP_PXP_OUT_AS_ULC_X 16 -+#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 -+#define BF_PXP_OUT_AS_ULC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_AS_ULC_X) -+#define BP_PXP_OUT_AS_ULC_RSVD0 14 -+#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) -+#define BP_PXP_OUT_AS_ULC_Y 0 -+#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF -+#define BF_PXP_OUT_AS_ULC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) -+ -+#define HW_PXP_OUT_AS_LRC (0x000000a0) -+ -+#define BP_PXP_OUT_AS_LRC_RSVD1 30 -+#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) -+#define BP_PXP_OUT_AS_LRC_X 16 -+#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 -+#define BF_PXP_OUT_AS_LRC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_AS_LRC_X) -+#define BP_PXP_OUT_AS_LRC_RSVD0 14 -+#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) -+#define BP_PXP_OUT_AS_LRC_Y 0 -+#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF -+#define BF_PXP_OUT_AS_LRC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) -+ -+#define HW_PXP_PS_CTRL (0x000000b0) -+#define HW_PXP_PS_CTRL_SET (0x000000b4) -+#define HW_PXP_PS_CTRL_CLR (0x000000b8) -+#define HW_PXP_PS_CTRL_TOG (0x000000bc) -+ -+#define BP_PXP_PS_CTRL_RSVD1 12 -+#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 -+#define BF_PXP_PS_CTRL_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) -+#define BP_PXP_PS_CTRL_DECX 10 -+#define BM_PXP_PS_CTRL_DECX 0x00000C00 -+#define BF_PXP_PS_CTRL_DECX(v) \ -+ (((v) << 10) & BM_PXP_PS_CTRL_DECX) -+#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 -+#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 -+#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 -+#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 -+#define BP_PXP_PS_CTRL_DECY 8 -+#define BM_PXP_PS_CTRL_DECY 0x00000300 -+#define BF_PXP_PS_CTRL_DECY(v) \ -+ (((v) << 8) & BM_PXP_PS_CTRL_DECY) -+#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 -+#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 -+#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 -+#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 -+#define BP_PXP_PS_CTRL_SWAP 5 -+#define BM_PXP_PS_CTRL_SWAP 0x000000E0 -+#define BF_PXP_PS_CTRL_SWAP(v) \ -+ (((v) << 5) & BM_PXP_PS_CTRL_SWAP) -+#define BP_PXP_PS_CTRL_FORMAT 0 -+#define BM_PXP_PS_CTRL_FORMAT 0x0000001F -+#define BF_PXP_PS_CTRL_FORMAT(v) \ -+ (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) -+#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 -+#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC -+#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD -+#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE -+#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 -+#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 -+#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 -+#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 -+#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 -+#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 -+#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 -+#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A -+#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B -+#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E -+#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F -+ -+#define HW_PXP_PS_BUF (0x000000c0) -+ -+#define BP_PXP_PS_BUF_ADDR 0 -+#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_PS_BUF_ADDR(v) (v) -+ -+#define HW_PXP_PS_UBUF (0x000000d0) -+ -+#define BP_PXP_PS_UBUF_ADDR 0 -+#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF -+#define BF_PXP_PS_UBUF_ADDR(v) (v) -+ -+#define HW_PXP_PS_VBUF (0x000000e0) -+ -+#define BP_PXP_PS_VBUF_ADDR 0 -+#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF -+#define BF_PXP_PS_VBUF_ADDR(v) (v) -+ -+#define HW_PXP_PS_PITCH (0x000000f0) -+ -+#define BP_PXP_PS_PITCH_RSVD 16 -+#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_PS_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_PS_PITCH_RSVD) -+#define BP_PXP_PS_PITCH_PITCH 0 -+#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_PS_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_PS_PITCH_PITCH) -+ -+#define HW_PXP_PS_BACKGROUND (0x00000100) -+ -+#define BP_PXP_PS_BACKGROUND_RSVD 24 -+#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000 -+#define BF_PXP_PS_BACKGROUND_RSVD(v) \ -+ (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD) -+#define BP_PXP_PS_BACKGROUND_COLOR 0 -+#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF -+#define BF_PXP_PS_BACKGROUND_COLOR(v) \ -+ (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR) -+ -+#define HW_PXP_PS_SCALE (0x00000110) -+ -+#define BM_PXP_PS_SCALE_RSVD2 0x80000000 -+#define BP_PXP_PS_SCALE_YSCALE 16 -+#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 -+#define BF_PXP_PS_SCALE_YSCALE(v) \ -+ (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) -+#define BM_PXP_PS_SCALE_RSVD1 0x00008000 -+#define BP_PXP_PS_SCALE_XSCALE 0 -+#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF -+#define BF_PXP_PS_SCALE_XSCALE(v) \ -+ (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) -+ -+#define HW_PXP_PS_OFFSET (0x00000120) -+ -+#define BP_PXP_PS_OFFSET_RSVD2 28 -+#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 -+#define BF_PXP_PS_OFFSET_RSVD2(v) \ -+ (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) -+#define BP_PXP_PS_OFFSET_YOFFSET 16 -+#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 -+#define BF_PXP_PS_OFFSET_YOFFSET(v) \ -+ (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) -+#define BP_PXP_PS_OFFSET_RSVD1 12 -+#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 -+#define BF_PXP_PS_OFFSET_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) -+#define BP_PXP_PS_OFFSET_XOFFSET 0 -+#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF -+#define BF_PXP_PS_OFFSET_XOFFSET(v) \ -+ (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) -+ -+#define HW_PXP_PS_CLRKEYLOW (0x00000130) -+ -+#define BP_PXP_PS_CLRKEYLOW_RSVD1 24 -+#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000 -+#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1) -+#define BP_PXP_PS_CLRKEYLOW_PIXEL 0 -+#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF -+#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL) -+ -+#define HW_PXP_PS_CLRKEYHIGH (0x00000140) -+ -+#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24 -+#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000 -+#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1) -+#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0 -+#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF -+#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL) -+ -+#define HW_PXP_AS_CTRL (0x00000150) -+ -+#define BP_PXP_AS_CTRL_RSVD1 21 -+#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000 -+#define BF_PXP_AS_CTRL_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_AS_CTRL_RSVD1) -+#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000 -+#define BP_PXP_AS_CTRL_ROP 16 -+#define BM_PXP_AS_CTRL_ROP 0x000F0000 -+#define BF_PXP_AS_CTRL_ROP(v) \ -+ (((v) << 16) & BM_PXP_AS_CTRL_ROP) -+#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 -+#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 -+#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 -+#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 -+#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 -+#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 -+#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 -+#define BV_PXP_AS_CTRL_ROP__NOT 0x7 -+#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 -+#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 -+#define BV_PXP_AS_CTRL_ROP__XORAS 0xA -+#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB -+#define BP_PXP_AS_CTRL_ALPHA 8 -+#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 -+#define BF_PXP_AS_CTRL_ALPHA(v) \ -+ (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) -+#define BP_PXP_AS_CTRL_FORMAT 4 -+#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 -+#define BF_PXP_AS_CTRL_FORMAT(v) \ -+ (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) -+#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 -+#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 -+#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 -+#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 -+#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC -+#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD -+#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE -+#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 -+#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 -+#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 -+#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ -+ (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 -+#define BM_PXP_AS_CTRL_RSVD0 0x00000001 -+ -+#define HW_PXP_AS_BUF (0x00000160) -+ -+#define BP_PXP_AS_BUF_ADDR 0 -+#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_AS_BUF_ADDR(v) (v) -+ -+#define HW_PXP_AS_PITCH (0x00000170) -+ -+#define BP_PXP_AS_PITCH_RSVD 16 -+#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_AS_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_AS_PITCH_RSVD) -+#define BP_PXP_AS_PITCH_PITCH 0 -+#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_AS_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_AS_PITCH_PITCH) -+ -+#define HW_PXP_AS_CLRKEYLOW (0x00000180) -+ -+#define BP_PXP_AS_CLRKEYLOW_RSVD1 24 -+#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000 -+#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1) -+#define BP_PXP_AS_CLRKEYLOW_PIXEL 0 -+#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF -+#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL) -+ -+#define HW_PXP_AS_CLRKEYHIGH (0x00000190) -+ -+#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24 -+#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000 -+#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1) -+#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0 -+#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF -+#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL) -+ -+#define HW_PXP_CSC1_COEF0 (0x000001a0) -+ -+#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 -+#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 -+#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 -+#define BP_PXP_CSC1_COEF0_C0 18 -+#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 -+#define BF_PXP_CSC1_COEF0_C0(v) \ -+ (((v) << 18) & BM_PXP_CSC1_COEF0_C0) -+#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 -+#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 -+#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ -+ (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) -+#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 -+#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF -+#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) -+ -+#define HW_PXP_CSC1_COEF1 (0x000001b0) -+ -+#define BP_PXP_CSC1_COEF1_RSVD1 27 -+#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 -+#define BF_PXP_CSC1_COEF1_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) -+#define BP_PXP_CSC1_COEF1_C1 16 -+#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 -+#define BF_PXP_CSC1_COEF1_C1(v) \ -+ (((v) << 16) & BM_PXP_CSC1_COEF1_C1) -+#define BP_PXP_CSC1_COEF1_RSVD0 11 -+#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 -+#define BF_PXP_CSC1_COEF1_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) -+#define BP_PXP_CSC1_COEF1_C4 0 -+#define BM_PXP_CSC1_COEF1_C4 0x000007FF -+#define BF_PXP_CSC1_COEF1_C4(v) \ -+ (((v) << 0) & BM_PXP_CSC1_COEF1_C4) -+ -+#define HW_PXP_CSC1_COEF2 (0x000001c0) -+ -+#define BP_PXP_CSC1_COEF2_RSVD1 27 -+#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 -+#define BF_PXP_CSC1_COEF2_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) -+#define BP_PXP_CSC1_COEF2_C2 16 -+#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 -+#define BF_PXP_CSC1_COEF2_C2(v) \ -+ (((v) << 16) & BM_PXP_CSC1_COEF2_C2) -+#define BP_PXP_CSC1_COEF2_RSVD0 11 -+#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 -+#define BF_PXP_CSC1_COEF2_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) -+#define BP_PXP_CSC1_COEF2_C3 0 -+#define BM_PXP_CSC1_COEF2_C3 0x000007FF -+#define BF_PXP_CSC1_COEF2_C3(v) \ -+ (((v) << 0) & BM_PXP_CSC1_COEF2_C3) -+ -+#define HW_PXP_CSC2_CTRL (0x000001d0) -+ -+#define BP_PXP_CSC2_CTRL_RSVD 3 -+#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 -+#define BF_PXP_CSC2_CTRL_RSVD(v) \ -+ (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) -+#define BP_PXP_CSC2_CTRL_CSC_MODE 1 -+#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 -+#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ -+ (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) -+#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 -+#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 -+#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 -+#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 -+#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 -+ -+#define HW_PXP_CSC2_COEF0 (0x000001e0) -+ -+#define BP_PXP_CSC2_COEF0_RSVD1 27 -+#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF0_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) -+#define BP_PXP_CSC2_COEF0_A2 16 -+#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 -+#define BF_PXP_CSC2_COEF0_A2(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF0_A2) -+#define BP_PXP_CSC2_COEF0_RSVD0 11 -+#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF0_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) -+#define BP_PXP_CSC2_COEF0_A1 0 -+#define BM_PXP_CSC2_COEF0_A1 0x000007FF -+#define BF_PXP_CSC2_COEF0_A1(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF0_A1) -+ -+#define HW_PXP_CSC2_COEF1 (0x000001f0) -+ -+#define BP_PXP_CSC2_COEF1_RSVD1 27 -+#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF1_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) -+#define BP_PXP_CSC2_COEF1_B1 16 -+#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 -+#define BF_PXP_CSC2_COEF1_B1(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF1_B1) -+#define BP_PXP_CSC2_COEF1_RSVD0 11 -+#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF1_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) -+#define BP_PXP_CSC2_COEF1_A3 0 -+#define BM_PXP_CSC2_COEF1_A3 0x000007FF -+#define BF_PXP_CSC2_COEF1_A3(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF1_A3) -+ -+#define HW_PXP_CSC2_COEF2 (0x00000200) -+ -+#define BP_PXP_CSC2_COEF2_RSVD1 27 -+#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF2_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) -+#define BP_PXP_CSC2_COEF2_B3 16 -+#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 -+#define BF_PXP_CSC2_COEF2_B3(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF2_B3) -+#define BP_PXP_CSC2_COEF2_RSVD0 11 -+#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF2_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) -+#define BP_PXP_CSC2_COEF2_B2 0 -+#define BM_PXP_CSC2_COEF2_B2 0x000007FF -+#define BF_PXP_CSC2_COEF2_B2(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF2_B2) -+ -+#define HW_PXP_CSC2_COEF3 (0x00000210) -+ -+#define BP_PXP_CSC2_COEF3_RSVD1 27 -+#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF3_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) -+#define BP_PXP_CSC2_COEF3_C2 16 -+#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 -+#define BF_PXP_CSC2_COEF3_C2(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF3_C2) -+#define BP_PXP_CSC2_COEF3_RSVD0 11 -+#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF3_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) -+#define BP_PXP_CSC2_COEF3_C1 0 -+#define BM_PXP_CSC2_COEF3_C1 0x000007FF -+#define BF_PXP_CSC2_COEF3_C1(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF3_C1) -+ -+#define HW_PXP_CSC2_COEF4 (0x00000220) -+ -+#define BP_PXP_CSC2_COEF4_RSVD1 25 -+#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 -+#define BF_PXP_CSC2_COEF4_RSVD1(v) \ -+ (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) -+#define BP_PXP_CSC2_COEF4_D1 16 -+#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 -+#define BF_PXP_CSC2_COEF4_D1(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF4_D1) -+#define BP_PXP_CSC2_COEF4_RSVD0 11 -+#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF4_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) -+#define BP_PXP_CSC2_COEF4_C3 0 -+#define BM_PXP_CSC2_COEF4_C3 0x000007FF -+#define BF_PXP_CSC2_COEF4_C3(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF4_C3) -+ -+#define HW_PXP_CSC2_COEF5 (0x00000230) -+ -+#define BP_PXP_CSC2_COEF5_RSVD1 25 -+#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 -+#define BF_PXP_CSC2_COEF5_RSVD1(v) \ -+ (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) -+#define BP_PXP_CSC2_COEF5_D3 16 -+#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 -+#define BF_PXP_CSC2_COEF5_D3(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF5_D3) -+#define BP_PXP_CSC2_COEF5_RSVD0 9 -+#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 -+#define BF_PXP_CSC2_COEF5_RSVD0(v) \ -+ (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) -+#define BP_PXP_CSC2_COEF5_D2 0 -+#define BM_PXP_CSC2_COEF5_D2 0x000001FF -+#define BF_PXP_CSC2_COEF5_D2(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF5_D2) -+ -+#define HW_PXP_LUT_CTRL (0x00000240) -+ -+#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 -+#define BP_PXP_LUT_CTRL_RSVD3 26 -+#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 -+#define BF_PXP_LUT_CTRL_RSVD3(v) \ -+ (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) -+#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 -+#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 -+#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ -+ (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 -+#define BP_PXP_LUT_CTRL_RSVD2 18 -+#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 -+#define BF_PXP_LUT_CTRL_RSVD2(v) \ -+ (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) -+#define BP_PXP_LUT_CTRL_OUT_MODE 16 -+#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 -+#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ -+ (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) -+#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 -+#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 -+#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 -+#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 -+#define BP_PXP_LUT_CTRL_RSVD1 11 -+#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 -+#define BF_PXP_LUT_CTRL_RSVD1(v) \ -+ (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) -+#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 -+#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 -+#define BM_PXP_LUT_CTRL_INVALID 0x00000100 -+#define BP_PXP_LUT_CTRL_RSVD0 1 -+#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE -+#define BF_PXP_LUT_CTRL_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) -+#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 -+ -+#define HW_PXP_LUT_ADDR (0x00000250) -+ -+#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 -+#define BP_PXP_LUT_ADDR_NUM_BYTES 16 -+#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 -+#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) -+#define BP_PXP_LUT_ADDR_RSVD1 14 -+#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 -+#define BF_PXP_LUT_ADDR_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) -+#define BP_PXP_LUT_ADDR_ADDR 0 -+#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF -+#define BF_PXP_LUT_ADDR_ADDR(v) \ -+ (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) -+ -+#define HW_PXP_LUT_DATA (0x00000260) -+ -+#define BP_PXP_LUT_DATA_DATA 0 -+#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF -+#define BF_PXP_LUT_DATA_DATA(v) (v) -+ -+#define HW_PXP_LUT_EXTMEM (0x00000270) -+ -+#define BP_PXP_LUT_EXTMEM_ADDR 0 -+#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF -+#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) -+ -+#define HW_PXP_CFA (0x00000280) -+ -+#define BP_PXP_CFA_DATA 0 -+#define BM_PXP_CFA_DATA 0xFFFFFFFF -+#define BF_PXP_CFA_DATA(v) (v) -+ -+#define HW_PXP_HIST_CTRL (0x00000290) -+ -+#define BP_PXP_HIST_CTRL_RSVD 6 -+#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 -+#define BF_PXP_HIST_CTRL_RSVD(v) \ -+ (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) -+#define BP_PXP_HIST_CTRL_PANEL_MODE 4 -+#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 -+#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ -+ (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) -+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 -+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 -+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 -+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 -+#define BP_PXP_HIST_CTRL_STATUS 0 -+#define BM_PXP_HIST_CTRL_STATUS 0x0000000F -+#define BF_PXP_HIST_CTRL_STATUS(v) \ -+ (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) -+ -+#define HW_PXP_HIST2_PARAM (0x000002a0) -+ -+#define BP_PXP_HIST2_PARAM_RSVD 16 -+#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 -+#define BF_PXP_HIST2_PARAM_RSVD(v) \ -+ (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) -+#define BP_PXP_HIST2_PARAM_RSVD1 13 -+#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 -+#define BF_PXP_HIST2_PARAM_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) -+#define BP_PXP_HIST2_PARAM_VALUE1 8 -+#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 -+#define BF_PXP_HIST2_PARAM_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) -+#define BP_PXP_HIST2_PARAM_RSVD0 5 -+#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 -+#define BF_PXP_HIST2_PARAM_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) -+#define BP_PXP_HIST2_PARAM_VALUE0 0 -+#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F -+#define BF_PXP_HIST2_PARAM_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) -+ -+#define HW_PXP_HIST4_PARAM (0x000002b0) -+ -+#define BP_PXP_HIST4_PARAM_RSVD3 29 -+#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 -+#define BF_PXP_HIST4_PARAM_RSVD3(v) \ -+ (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) -+#define BP_PXP_HIST4_PARAM_VALUE3 24 -+#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 -+#define BF_PXP_HIST4_PARAM_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) -+#define BP_PXP_HIST4_PARAM_RSVD2 21 -+#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 -+#define BF_PXP_HIST4_PARAM_RSVD2(v) \ -+ (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) -+#define BP_PXP_HIST4_PARAM_VALUE2 16 -+#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 -+#define BF_PXP_HIST4_PARAM_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) -+#define BP_PXP_HIST4_PARAM_RSVD1 13 -+#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 -+#define BF_PXP_HIST4_PARAM_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) -+#define BP_PXP_HIST4_PARAM_VALUE1 8 -+#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 -+#define BF_PXP_HIST4_PARAM_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) -+#define BP_PXP_HIST4_PARAM_RSVD0 5 -+#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 -+#define BF_PXP_HIST4_PARAM_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) -+#define BP_PXP_HIST4_PARAM_VALUE0 0 -+#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F -+#define BF_PXP_HIST4_PARAM_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) -+ -+#define HW_PXP_HIST8_PARAM0 (0x000002c0) -+ -+#define BP_PXP_HIST8_PARAM0_RSVD3 29 -+#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 -+#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ -+ (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) -+#define BP_PXP_HIST8_PARAM0_VALUE3 24 -+#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 -+#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) -+#define BP_PXP_HIST8_PARAM0_RSVD2 21 -+#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 -+#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ -+ (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) -+#define BP_PXP_HIST8_PARAM0_VALUE2 16 -+#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 -+#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) -+#define BP_PXP_HIST8_PARAM0_RSVD1 13 -+#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 -+#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) -+#define BP_PXP_HIST8_PARAM0_VALUE1 8 -+#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 -+#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) -+#define BP_PXP_HIST8_PARAM0_RSVD0 5 -+#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 -+#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) -+#define BP_PXP_HIST8_PARAM0_VALUE0 0 -+#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F -+#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) -+ -+#define HW_PXP_HIST8_PARAM1 (0x000002d0) -+ -+#define BP_PXP_HIST8_PARAM1_RSVD7 29 -+#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 -+#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ -+ (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) -+#define BP_PXP_HIST8_PARAM1_VALUE7 24 -+#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 -+#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ -+ (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) -+#define BP_PXP_HIST8_PARAM1_RSVD6 21 -+#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 -+#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ -+ (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) -+#define BP_PXP_HIST8_PARAM1_VALUE6 16 -+#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 -+#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ -+ (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) -+#define BP_PXP_HIST8_PARAM1_RSVD5 13 -+#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 -+#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ -+ (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) -+#define BP_PXP_HIST8_PARAM1_VALUE5 8 -+#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 -+#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ -+ (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) -+#define BP_PXP_HIST8_PARAM1_RSVD4 5 -+#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 -+#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ -+ (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) -+#define BP_PXP_HIST8_PARAM1_VALUE4 0 -+#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F -+#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ -+ (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) -+ -+#define HW_PXP_HIST16_PARAM0 (0x000002e0) -+ -+#define BP_PXP_HIST16_PARAM0_RSVD3 29 -+#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 -+#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ -+ (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) -+#define BP_PXP_HIST16_PARAM0_VALUE3 24 -+#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 -+#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) -+#define BP_PXP_HIST16_PARAM0_RSVD2 21 -+#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 -+#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ -+ (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) -+#define BP_PXP_HIST16_PARAM0_VALUE2 16 -+#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 -+#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) -+#define BP_PXP_HIST16_PARAM0_RSVD1 13 -+#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 -+#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) -+#define BP_PXP_HIST16_PARAM0_VALUE1 8 -+#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 -+#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) -+#define BP_PXP_HIST16_PARAM0_RSVD0 5 -+#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 -+#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) -+#define BP_PXP_HIST16_PARAM0_VALUE0 0 -+#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F -+#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) -+ -+#define HW_PXP_HIST16_PARAM1 (0x000002f0) -+ -+#define BP_PXP_HIST16_PARAM1_RSVD7 29 -+#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 -+#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ -+ (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) -+#define BP_PXP_HIST16_PARAM1_VALUE7 24 -+#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 -+#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) -+#define BP_PXP_HIST16_PARAM1_RSVD6 21 -+#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 -+#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ -+ (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) -+#define BP_PXP_HIST16_PARAM1_VALUE6 16 -+#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 -+#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) -+#define BP_PXP_HIST16_PARAM1_RSVD5 13 -+#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 -+#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ -+ (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) -+#define BP_PXP_HIST16_PARAM1_VALUE5 8 -+#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 -+#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) -+#define BP_PXP_HIST16_PARAM1_RSVD4 5 -+#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 -+#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ -+ (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) -+#define BP_PXP_HIST16_PARAM1_VALUE4 0 -+#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F -+#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) -+ -+#define HW_PXP_HIST16_PARAM2 (0x00000300) -+ -+#define BP_PXP_HIST16_PARAM2_RSVD11 29 -+#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 -+#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ -+ (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) -+#define BP_PXP_HIST16_PARAM2_VALUE11 24 -+#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 -+#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) -+#define BP_PXP_HIST16_PARAM2_RSVD10 21 -+#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 -+#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ -+ (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) -+#define BP_PXP_HIST16_PARAM2_VALUE10 16 -+#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 -+#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) -+#define BP_PXP_HIST16_PARAM2_RSVD9 13 -+#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 -+#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ -+ (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) -+#define BP_PXP_HIST16_PARAM2_VALUE9 8 -+#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 -+#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) -+#define BP_PXP_HIST16_PARAM2_RSVD8 5 -+#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 -+#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ -+ (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) -+#define BP_PXP_HIST16_PARAM2_VALUE8 0 -+#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F -+#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) -+ -+#define HW_PXP_HIST16_PARAM3 (0x00000310) -+ -+#define BP_PXP_HIST16_PARAM3_RSVD15 29 -+#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 -+#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ -+ (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) -+#define BP_PXP_HIST16_PARAM3_VALUE15 24 -+#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 -+#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) -+#define BP_PXP_HIST16_PARAM3_RSVD14 21 -+#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 -+#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ -+ (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) -+#define BP_PXP_HIST16_PARAM3_VALUE14 16 -+#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 -+#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) -+#define BP_PXP_HIST16_PARAM3_RSVD13 13 -+#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 -+#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ -+ (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) -+#define BP_PXP_HIST16_PARAM3_VALUE13 8 -+#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 -+#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) -+#define BP_PXP_HIST16_PARAM3_RSVD12 5 -+#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 -+#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ -+ (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) -+#define BP_PXP_HIST16_PARAM3_VALUE12 0 -+#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F -+#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) -+ -+#define HW_PXP_POWER (0x00000320) -+ -+#define BP_PXP_POWER_CTRL 12 -+#define BM_PXP_POWER_CTRL 0xFFFFF000 -+#define BF_PXP_POWER_CTRL(v) \ -+ (((v) << 12) & BM_PXP_POWER_CTRL) -+#define BP_PXP_POWER_ROT_MEM_LP_STATE 9 -+#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00 -+#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \ -+ (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE) -+#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6 -+#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0 -+#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \ -+ (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN) -+#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4 -+#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3 -+#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038 -+#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \ -+ (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN) -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4 -+#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0 -+#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007 -+#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \ -+ (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0) -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2 -+#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4 -+ -+#define HW_PXP_NEXT (0x00000400) -+ -+#define BP_PXP_NEXT_POINTER 2 -+#define BM_PXP_NEXT_POINTER 0xFFFFFFFC -+#define BF_PXP_NEXT_POINTER(v) \ -+ (((v) << 2) & BM_PXP_NEXT_POINTER) -+#define BM_PXP_NEXT_RSVD 0x00000002 -+#define BM_PXP_NEXT_ENABLED 0x00000001 -+ -+#define HW_PXP_DEBUGCTRL (0x00000410) -+ -+#define BP_PXP_DEBUGCTRL_RSVD 12 -+#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 -+#define BF_PXP_DEBUGCTRL_RSVD(v) \ -+ (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) -+#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 -+#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 -+#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ -+ (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 -+#define BP_PXP_DEBUGCTRL_SELECT 0 -+#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF -+#define BF_PXP_DEBUGCTRL_SELECT(v) \ -+ (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) -+#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 -+#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 -+#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 -+#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 -+#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 -+#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 -+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 -+#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 -+#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 -+#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 -+ -+#define HW_PXP_DEBUG (0x00000420) -+ -+#define BP_PXP_DEBUG_DATA 0 -+#define BM_PXP_DEBUG_DATA 0xFFFFFFFF -+#define BF_PXP_DEBUG_DATA(v) (v) -+ -+#define HW_PXP_VERSION (0x00000430) -+ -+#define BP_PXP_VERSION_MAJOR 24 -+#define BM_PXP_VERSION_MAJOR 0xFF000000 -+#define BF_PXP_VERSION_MAJOR(v) \ -+ (((v) << 24) & BM_PXP_VERSION_MAJOR) -+#define BP_PXP_VERSION_MINOR 16 -+#define BM_PXP_VERSION_MINOR 0x00FF0000 -+#define BF_PXP_VERSION_MINOR(v) \ -+ (((v) << 16) & BM_PXP_VERSION_MINOR) -+#define BP_PXP_VERSION_STEP 0 -+#define BM_PXP_VERSION_STEP 0x0000FFFF -+#define BF_PXP_VERSION_STEP(v) \ -+ (((v) << 0) & BM_PXP_VERSION_STEP) -+#endif /* __ARCH_ARM___PXP_H */ -diff --git a/drivers/dma/pxp/regs-pxp_v3.h b/drivers/dma/pxp/regs-pxp_v3.h -new file mode 100644 -index 000000000..2fef8e9a1 ---- /dev/null -+++ b/drivers/dma/pxp/regs-pxp_v3.h -@@ -0,0 +1,26939 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Freescale PXP Register Definitions -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. -+ * -+ * This file is created by xml file. Don't Edit it. -+ * -+ * Xml Revision: 1.77 -+ * Template revision: 1.3 -+ */ -+ -+#ifndef __ARCH_ARM___PXP_H -+#define __ARCH_ARM___PXP_H -+ -+ -+#define HW_PXP_CTRL (0x00000000) -+#define HW_PXP_CTRL_SET (0x00000004) -+#define HW_PXP_CTRL_CLR (0x00000008) -+#define HW_PXP_CTRL_TOG (0x0000000c) -+ -+#define BM_PXP_CTRL_SFTRST 0x80000000 -+#define BF_PXP_CTRL_SFTRST(v) \ -+ (((v) << 31) & BM_PXP_CTRL_SFTRST) -+#define BM_PXP_CTRL_CLKGATE 0x40000000 -+#define BF_PXP_CTRL_CLKGATE(v) \ -+ (((v) << 30) & BM_PXP_CTRL_CLKGATE) -+#define BM_PXP_CTRL_RSVD4 0x20000000 -+#define BF_PXP_CTRL_RSVD4(v) \ -+ (((v) << 29) & BM_PXP_CTRL_RSVD4) -+#define BM_PXP_CTRL_EN_REPEAT 0x10000000 -+#define BF_PXP_CTRL_EN_REPEAT(v) \ -+ (((v) << 28) & BM_PXP_CTRL_EN_REPEAT) -+#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000 -+#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ -+ (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1) -+#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000 -+#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ -+ (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0) -+#define BM_PXP_CTRL_ENABLE_LUT 0x02000000 -+#define BF_PXP_CTRL_ENABLE_LUT(v) \ -+ (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT) -+#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000 -+#define BF_PXP_CTRL_ENABLE_CSC2(v) \ -+ (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2) -+#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 -+#define BF_PXP_CTRL_BLOCK_SIZE(v) \ -+ (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE) -+#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 -+#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 -+#define BM_PXP_CTRL_RSVD1 0x00400000 -+#define BF_PXP_CTRL_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_CTRL_RSVD1) -+#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000 -+#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \ -+ (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B) -+#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000 -+#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \ -+ (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE) -+#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000 -+#define BF_PXP_CTRL_ENABLE_WFE_B(v) \ -+ (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B) -+#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000 -+#define BF_PXP_CTRL_ENABLE_WFE_A(v) \ -+ (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A) -+#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000 -+#define BF_PXP_CTRL_ENABLE_DITHER(v) \ -+ (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER) -+#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000 -+#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \ -+ (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT) -+#define BM_PXP_CTRL_VFLIP1 0x00008000 -+#define BF_PXP_CTRL_VFLIP1(v) \ -+ (((v) << 15) & BM_PXP_CTRL_VFLIP1) -+#define BM_PXP_CTRL_HFLIP1 0x00004000 -+#define BF_PXP_CTRL_HFLIP1(v) \ -+ (((v) << 14) & BM_PXP_CTRL_HFLIP1) -+#define BP_PXP_CTRL_ROTATE1 12 -+#define BM_PXP_CTRL_ROTATE1 0x00003000 -+#define BF_PXP_CTRL_ROTATE1(v) \ -+ (((v) << 12) & BM_PXP_CTRL_ROTATE1) -+#define BV_PXP_CTRL_ROTATE1__ROT_0 0x0 -+#define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 -+#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2 -+#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3 -+#define BM_PXP_CTRL_VFLIP0 0x00000800 -+#define BF_PXP_CTRL_VFLIP0(v) \ -+ (((v) << 11) & BM_PXP_CTRL_VFLIP0) -+#define BM_PXP_CTRL_HFLIP0 0x00000400 -+#define BF_PXP_CTRL_HFLIP0(v) \ -+ (((v) << 10) & BM_PXP_CTRL_HFLIP0) -+#define BP_PXP_CTRL_ROTATE0 8 -+#define BM_PXP_CTRL_ROTATE0 0x00000300 -+#define BF_PXP_CTRL_ROTATE0(v) \ -+ (((v) << 8) & BM_PXP_CTRL_ROTATE0) -+#define BV_PXP_CTRL_ROTATE0__ROT_0 0x0 -+#define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 -+#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2 -+#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3 -+#define BP_PXP_CTRL_RSVD0 6 -+#define BM_PXP_CTRL_RSVD0 0x000000C0 -+#define BF_PXP_CTRL_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_CTRL_RSVD0) -+#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020 -+#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \ -+ (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP) -+#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010 -+#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \ -+ (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE) -+#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 -+#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \ -+ (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE) -+#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 -+#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \ -+ (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE) -+#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -+#define BF_PXP_CTRL_IRQ_ENABLE(v) \ -+ (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE) -+#define BM_PXP_CTRL_ENABLE 0x00000001 -+#define BF_PXP_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_CTRL_ENABLE) -+ -+#define HW_PXP_STAT (0x00000010) -+#define HW_PXP_STAT_SET (0x00000014) -+#define HW_PXP_STAT_CLR (0x00000018) -+#define HW_PXP_STAT_TOG (0x0000001c) -+ -+#define BP_PXP_STAT_BLOCKX 24 -+#define BM_PXP_STAT_BLOCKX 0xFF000000 -+#define BF_PXP_STAT_BLOCKX(v) \ -+ (((v) << 24) & BM_PXP_STAT_BLOCKX) -+#define BP_PXP_STAT_BLOCKY 16 -+#define BM_PXP_STAT_BLOCKY 0x00FF0000 -+#define BF_PXP_STAT_BLOCKY(v) \ -+ (((v) << 16) & BM_PXP_STAT_BLOCKY) -+#define BP_PXP_STAT_AXI_ERROR_ID_1 12 -+#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000 -+#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \ -+ (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1) -+#define BM_PXP_STAT_RSVD2 0x00000800 -+#define BF_PXP_STAT_RSVD2(v) \ -+ (((v) << 11) & BM_PXP_STAT_RSVD2) -+#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400 -+#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \ -+ (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1) -+#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200 -+#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \ -+ (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1) -+#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 -+#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \ -+ (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ) -+#define BP_PXP_STAT_AXI_ERROR_ID_0 4 -+#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0 -+#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \ -+ (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0) -+#define BM_PXP_STAT_NEXT_IRQ 0x00000008 -+#define BF_PXP_STAT_NEXT_IRQ(v) \ -+ (((v) << 3) & BM_PXP_STAT_NEXT_IRQ) -+#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004 -+#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \ -+ (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0) -+#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002 -+#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \ -+ (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0) -+#define BM_PXP_STAT_IRQ0 0x00000001 -+#define BF_PXP_STAT_IRQ0(v) \ -+ (((v) << 0) & BM_PXP_STAT_IRQ0) -+ -+#define HW_PXP_OUT_CTRL (0x00000020) -+#define HW_PXP_OUT_CTRL_SET (0x00000024) -+#define HW_PXP_OUT_CTRL_CLR (0x00000028) -+#define HW_PXP_OUT_CTRL_TOG (0x0000002c) -+ -+#define BP_PXP_OUT_CTRL_ALPHA 24 -+#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 -+#define BF_PXP_OUT_CTRL_ALPHA(v) \ -+ (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) -+#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 -+#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \ -+ (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT) -+#define BP_PXP_OUT_CTRL_RSVD1 10 -+#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 -+#define BF_PXP_OUT_CTRL_RSVD1(v) \ -+ (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) -+#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 -+#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 -+#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ -+ (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 -+#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 -+#define BP_PXP_OUT_CTRL_RSVD0 5 -+#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 -+#define BF_PXP_OUT_CTRL_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) -+#define BP_PXP_OUT_CTRL_FORMAT 0 -+#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F -+#define BF_PXP_OUT_CTRL_FORMAT(v) \ -+ (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) -+#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 -+#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 -+#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 -+#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 -+#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 -+#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC -+#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD -+#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE -+#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 -+#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 -+#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 -+#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 -+#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 -+#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 -+#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 -+#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A -+#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B -+ -+#define HW_PXP_OUT_BUF (0x00000030) -+ -+#define BP_PXP_OUT_BUF_ADDR 0 -+#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_OUT_BUF_ADDR(v) (v) -+ -+#define HW_PXP_OUT_BUF2 (0x00000040) -+ -+#define BP_PXP_OUT_BUF2_ADDR 0 -+#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF -+#define BF_PXP_OUT_BUF2_ADDR(v) (v) -+ -+#define HW_PXP_OUT_PITCH (0x00000050) -+ -+#define BP_PXP_OUT_PITCH_RSVD 16 -+#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_OUT_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) -+#define BP_PXP_OUT_PITCH_PITCH 0 -+#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_OUT_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) -+ -+#define HW_PXP_OUT_LRC (0x00000060) -+ -+#define BP_PXP_OUT_LRC_RSVD1 30 -+#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_LRC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) -+#define BP_PXP_OUT_LRC_X 16 -+#define BM_PXP_OUT_LRC_X 0x3FFF0000 -+#define BF_PXP_OUT_LRC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_LRC_X) -+#define BP_PXP_OUT_LRC_RSVD0 14 -+#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_LRC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) -+#define BP_PXP_OUT_LRC_Y 0 -+#define BM_PXP_OUT_LRC_Y 0x00003FFF -+#define BF_PXP_OUT_LRC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_LRC_Y) -+ -+#define HW_PXP_OUT_PS_ULC (0x00000070) -+ -+#define BP_PXP_OUT_PS_ULC_RSVD1 30 -+#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) -+#define BP_PXP_OUT_PS_ULC_X 16 -+#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 -+#define BF_PXP_OUT_PS_ULC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_PS_ULC_X) -+#define BP_PXP_OUT_PS_ULC_RSVD0 14 -+#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) -+#define BP_PXP_OUT_PS_ULC_Y 0 -+#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF -+#define BF_PXP_OUT_PS_ULC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) -+ -+#define HW_PXP_OUT_PS_LRC (0x00000080) -+ -+#define BP_PXP_OUT_PS_LRC_RSVD1 30 -+#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) -+#define BP_PXP_OUT_PS_LRC_X 16 -+#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 -+#define BF_PXP_OUT_PS_LRC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_PS_LRC_X) -+#define BP_PXP_OUT_PS_LRC_RSVD0 14 -+#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) -+#define BP_PXP_OUT_PS_LRC_Y 0 -+#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF -+#define BF_PXP_OUT_PS_LRC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) -+ -+#define HW_PXP_OUT_AS_ULC (0x00000090) -+ -+#define BP_PXP_OUT_AS_ULC_RSVD1 30 -+#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) -+#define BP_PXP_OUT_AS_ULC_X 16 -+#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 -+#define BF_PXP_OUT_AS_ULC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_AS_ULC_X) -+#define BP_PXP_OUT_AS_ULC_RSVD0 14 -+#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) -+#define BP_PXP_OUT_AS_ULC_Y 0 -+#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF -+#define BF_PXP_OUT_AS_ULC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) -+ -+#define HW_PXP_OUT_AS_LRC (0x000000a0) -+ -+#define BP_PXP_OUT_AS_LRC_RSVD1 30 -+#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 -+#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ -+ (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) -+#define BP_PXP_OUT_AS_LRC_X 16 -+#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 -+#define BF_PXP_OUT_AS_LRC_X(v) \ -+ (((v) << 16) & BM_PXP_OUT_AS_LRC_X) -+#define BP_PXP_OUT_AS_LRC_RSVD0 14 -+#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 -+#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) -+#define BP_PXP_OUT_AS_LRC_Y 0 -+#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF -+#define BF_PXP_OUT_AS_LRC_Y(v) \ -+ (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) -+ -+#define HW_PXP_PS_CTRL (0x000000b0) -+#define HW_PXP_PS_CTRL_SET (0x000000b4) -+#define HW_PXP_PS_CTRL_CLR (0x000000b8) -+#define HW_PXP_PS_CTRL_TOG (0x000000bc) -+ -+#define BP_PXP_PS_CTRL_RSVD1 12 -+#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 -+#define BF_PXP_PS_CTRL_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) -+#define BP_PXP_PS_CTRL_DECX 10 -+#define BM_PXP_PS_CTRL_DECX 0x00000C00 -+#define BF_PXP_PS_CTRL_DECX(v) \ -+ (((v) << 10) & BM_PXP_PS_CTRL_DECX) -+#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 -+#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 -+#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 -+#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 -+#define BP_PXP_PS_CTRL_DECY 8 -+#define BM_PXP_PS_CTRL_DECY 0x00000300 -+#define BF_PXP_PS_CTRL_DECY(v) \ -+ (((v) << 8) & BM_PXP_PS_CTRL_DECY) -+#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 -+#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 -+#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 -+#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 -+#define BM_PXP_PS_CTRL_RSVD0 0x00000080 -+#define BF_PXP_PS_CTRL_RSVD0(v) \ -+ (((v) << 7) & BM_PXP_PS_CTRL_RSVD0) -+#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040 -+#define BF_PXP_PS_CTRL_WB_SWAP(v) \ -+ (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP) -+#define BP_PXP_PS_CTRL_FORMAT 0 -+#define BM_PXP_PS_CTRL_FORMAT 0x0000003F -+#define BF_PXP_PS_CTRL_FORMAT(v) \ -+ (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) -+#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 -+#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC -+#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD -+#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE -+#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 -+#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 -+#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 -+#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 -+#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 -+#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 -+#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 -+#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A -+#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B -+#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E -+#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F -+#define BV_PXP_PS_CTRL_FORMAT__RGBA888 0x24 -+ -+#define HW_PXP_PS_BUF (0x000000c0) -+ -+#define BP_PXP_PS_BUF_ADDR 0 -+#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_PS_BUF_ADDR(v) (v) -+ -+#define HW_PXP_PS_UBUF (0x000000d0) -+ -+#define BP_PXP_PS_UBUF_ADDR 0 -+#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF -+#define BF_PXP_PS_UBUF_ADDR(v) (v) -+ -+#define HW_PXP_PS_VBUF (0x000000e0) -+ -+#define BP_PXP_PS_VBUF_ADDR 0 -+#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF -+#define BF_PXP_PS_VBUF_ADDR(v) (v) -+ -+#define HW_PXP_PS_PITCH (0x000000f0) -+ -+#define BP_PXP_PS_PITCH_RSVD 16 -+#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_PS_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_PS_PITCH_RSVD) -+#define BP_PXP_PS_PITCH_PITCH 0 -+#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_PS_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_PS_PITCH_PITCH) -+ -+#define HW_PXP_PS_BACKGROUND_0 (0x00000100) -+ -+#define BP_PXP_PS_BACKGROUND_0_RSVD 24 -+#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000 -+#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \ -+ (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD) -+#define BP_PXP_PS_BACKGROUND_0_COLOR 0 -+#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF -+#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \ -+ (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR) -+ -+#define HW_PXP_PS_SCALE (0x00000110) -+ -+#define BM_PXP_PS_SCALE_RSVD2 0x80000000 -+#define BF_PXP_PS_SCALE_RSVD2(v) \ -+ (((v) << 31) & BM_PXP_PS_SCALE_RSVD2) -+#define BP_PXP_PS_SCALE_YSCALE 16 -+#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 -+#define BF_PXP_PS_SCALE_YSCALE(v) \ -+ (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) -+#define BM_PXP_PS_SCALE_RSVD1 0x00008000 -+#define BF_PXP_PS_SCALE_RSVD1(v) \ -+ (((v) << 15) & BM_PXP_PS_SCALE_RSVD1) -+#define BP_PXP_PS_SCALE_XSCALE 0 -+#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF -+#define BF_PXP_PS_SCALE_XSCALE(v) \ -+ (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) -+ -+#define BP_PXP_PS_SCALE_OFFSET 12 -+ -+#define HW_PXP_PS_OFFSET (0x00000120) -+ -+#define BP_PXP_PS_OFFSET_RSVD2 28 -+#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 -+#define BF_PXP_PS_OFFSET_RSVD2(v) \ -+ (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) -+#define BP_PXP_PS_OFFSET_YOFFSET 16 -+#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 -+#define BF_PXP_PS_OFFSET_YOFFSET(v) \ -+ (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) -+#define BP_PXP_PS_OFFSET_RSVD1 12 -+#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 -+#define BF_PXP_PS_OFFSET_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) -+#define BP_PXP_PS_OFFSET_XOFFSET 0 -+#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF -+#define BF_PXP_PS_OFFSET_XOFFSET(v) \ -+ (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) -+ -+#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130) -+ -+#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24 -+#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000 -+#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1) -+#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0 -+#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF -+#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL) -+ -+#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140) -+ -+#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24 -+#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000 -+#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1) -+#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0 -+#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF -+#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL) -+ -+#define HW_PXP_AS_CTRL (0x00000150) -+ -+#define BP_PXP_AS_CTRL_RSVD1 22 -+#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000 -+#define BF_PXP_AS_CTRL_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_AS_CTRL_RSVD1) -+#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000 -+#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \ -+ (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT) -+#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000 -+#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \ -+ (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT) -+#define BP_PXP_AS_CTRL_ROP 16 -+#define BM_PXP_AS_CTRL_ROP 0x000F0000 -+#define BF_PXP_AS_CTRL_ROP(v) \ -+ (((v) << 16) & BM_PXP_AS_CTRL_ROP) -+#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 -+#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 -+#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 -+#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 -+#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 -+#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 -+#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 -+#define BV_PXP_AS_CTRL_ROP__NOT 0x7 -+#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 -+#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 -+#define BV_PXP_AS_CTRL_ROP__XORAS 0xA -+#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB -+#define BP_PXP_AS_CTRL_ALPHA 8 -+#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 -+#define BF_PXP_AS_CTRL_ALPHA(v) \ -+ (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) -+#define BP_PXP_AS_CTRL_FORMAT 4 -+#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 -+#define BF_PXP_AS_CTRL_FORMAT(v) \ -+ (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) -+#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 -+#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 -+#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 -+#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 -+#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 -+#define BV_PXP_AS_CTRL_FORMAT__RGBA5551 0xA -+#define BV_PXP_AS_CTRL_FORMAT__RGBA4444 0xB -+#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC -+#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD -+#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE -+#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 -+#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \ -+ (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY) -+#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 -+#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 -+#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ -+ (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 -+#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 -+#define BM_PXP_AS_CTRL_RSVD0 0x00000001 -+#define BF_PXP_AS_CTRL_RSVD0(v) \ -+ (((v) << 0) & BM_PXP_AS_CTRL_RSVD0) -+ -+#define HW_PXP_AS_BUF (0x00000160) -+ -+#define BP_PXP_AS_BUF_ADDR 0 -+#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_AS_BUF_ADDR(v) (v) -+ -+#define HW_PXP_AS_PITCH (0x00000170) -+ -+#define BP_PXP_AS_PITCH_RSVD 16 -+#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_AS_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_AS_PITCH_RSVD) -+#define BP_PXP_AS_PITCH_PITCH 0 -+#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_AS_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_AS_PITCH_PITCH) -+ -+#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180) -+ -+#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24 -+#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000 -+#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1) -+#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0 -+#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF -+#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL) -+ -+#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190) -+ -+#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24 -+#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000 -+#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1) -+#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0 -+#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF -+#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL) -+ -+#define HW_PXP_CSC1_COEF0 (0x000001a0) -+ -+#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 -+#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \ -+ (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE) -+#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 -+#define BF_PXP_CSC1_COEF0_BYPASS(v) \ -+ (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS) -+#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 -+#define BF_PXP_CSC1_COEF0_RSVD1(v) \ -+ (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1) -+#define BP_PXP_CSC1_COEF0_C0 18 -+#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 -+#define BF_PXP_CSC1_COEF0_C0(v) \ -+ (((v) << 18) & BM_PXP_CSC1_COEF0_C0) -+#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 -+#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 -+#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ -+ (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) -+#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 -+#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF -+#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) -+ -+#define HW_PXP_CSC1_COEF1 (0x000001b0) -+ -+#define BP_PXP_CSC1_COEF1_RSVD1 27 -+#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 -+#define BF_PXP_CSC1_COEF1_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) -+#define BP_PXP_CSC1_COEF1_C1 16 -+#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 -+#define BF_PXP_CSC1_COEF1_C1(v) \ -+ (((v) << 16) & BM_PXP_CSC1_COEF1_C1) -+#define BP_PXP_CSC1_COEF1_RSVD0 11 -+#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 -+#define BF_PXP_CSC1_COEF1_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) -+#define BP_PXP_CSC1_COEF1_C4 0 -+#define BM_PXP_CSC1_COEF1_C4 0x000007FF -+#define BF_PXP_CSC1_COEF1_C4(v) \ -+ (((v) << 0) & BM_PXP_CSC1_COEF1_C4) -+ -+#define HW_PXP_CSC1_COEF2 (0x000001c0) -+ -+#define BP_PXP_CSC1_COEF2_RSVD1 27 -+#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 -+#define BF_PXP_CSC1_COEF2_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) -+#define BP_PXP_CSC1_COEF2_C2 16 -+#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 -+#define BF_PXP_CSC1_COEF2_C2(v) \ -+ (((v) << 16) & BM_PXP_CSC1_COEF2_C2) -+#define BP_PXP_CSC1_COEF2_RSVD0 11 -+#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 -+#define BF_PXP_CSC1_COEF2_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) -+#define BP_PXP_CSC1_COEF2_C3 0 -+#define BM_PXP_CSC1_COEF2_C3 0x000007FF -+#define BF_PXP_CSC1_COEF2_C3(v) \ -+ (((v) << 0) & BM_PXP_CSC1_COEF2_C3) -+ -+#define HW_PXP_CSC2_CTRL (0x000001d0) -+ -+#define BP_PXP_CSC2_CTRL_RSVD 3 -+#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 -+#define BF_PXP_CSC2_CTRL_RSVD(v) \ -+ (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) -+#define BP_PXP_CSC2_CTRL_CSC_MODE 1 -+#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 -+#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ -+ (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) -+#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 -+#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 -+#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 -+#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 -+#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 -+#define BF_PXP_CSC2_CTRL_BYPASS(v) \ -+ (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS) -+ -+#define HW_PXP_CSC2_COEF0 (0x000001e0) -+ -+#define BP_PXP_CSC2_COEF0_RSVD1 27 -+#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF0_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) -+#define BP_PXP_CSC2_COEF0_A2 16 -+#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 -+#define BF_PXP_CSC2_COEF0_A2(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF0_A2) -+#define BP_PXP_CSC2_COEF0_RSVD0 11 -+#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF0_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) -+#define BP_PXP_CSC2_COEF0_A1 0 -+#define BM_PXP_CSC2_COEF0_A1 0x000007FF -+#define BF_PXP_CSC2_COEF0_A1(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF0_A1) -+ -+#define HW_PXP_CSC2_COEF1 (0x000001f0) -+ -+#define BP_PXP_CSC2_COEF1_RSVD1 27 -+#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF1_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) -+#define BP_PXP_CSC2_COEF1_B1 16 -+#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 -+#define BF_PXP_CSC2_COEF1_B1(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF1_B1) -+#define BP_PXP_CSC2_COEF1_RSVD0 11 -+#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF1_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) -+#define BP_PXP_CSC2_COEF1_A3 0 -+#define BM_PXP_CSC2_COEF1_A3 0x000007FF -+#define BF_PXP_CSC2_COEF1_A3(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF1_A3) -+ -+#define HW_PXP_CSC2_COEF2 (0x00000200) -+ -+#define BP_PXP_CSC2_COEF2_RSVD1 27 -+#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF2_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) -+#define BP_PXP_CSC2_COEF2_B3 16 -+#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 -+#define BF_PXP_CSC2_COEF2_B3(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF2_B3) -+#define BP_PXP_CSC2_COEF2_RSVD0 11 -+#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF2_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) -+#define BP_PXP_CSC2_COEF2_B2 0 -+#define BM_PXP_CSC2_COEF2_B2 0x000007FF -+#define BF_PXP_CSC2_COEF2_B2(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF2_B2) -+ -+#define HW_PXP_CSC2_COEF3 (0x00000210) -+ -+#define BP_PXP_CSC2_COEF3_RSVD1 27 -+#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 -+#define BF_PXP_CSC2_COEF3_RSVD1(v) \ -+ (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) -+#define BP_PXP_CSC2_COEF3_C2 16 -+#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 -+#define BF_PXP_CSC2_COEF3_C2(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF3_C2) -+#define BP_PXP_CSC2_COEF3_RSVD0 11 -+#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF3_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) -+#define BP_PXP_CSC2_COEF3_C1 0 -+#define BM_PXP_CSC2_COEF3_C1 0x000007FF -+#define BF_PXP_CSC2_COEF3_C1(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF3_C1) -+ -+#define HW_PXP_CSC2_COEF4 (0x00000220) -+ -+#define BP_PXP_CSC2_COEF4_RSVD1 25 -+#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 -+#define BF_PXP_CSC2_COEF4_RSVD1(v) \ -+ (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) -+#define BP_PXP_CSC2_COEF4_D1 16 -+#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 -+#define BF_PXP_CSC2_COEF4_D1(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF4_D1) -+#define BP_PXP_CSC2_COEF4_RSVD0 11 -+#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 -+#define BF_PXP_CSC2_COEF4_RSVD0(v) \ -+ (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) -+#define BP_PXP_CSC2_COEF4_C3 0 -+#define BM_PXP_CSC2_COEF4_C3 0x000007FF -+#define BF_PXP_CSC2_COEF4_C3(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF4_C3) -+ -+#define HW_PXP_CSC2_COEF5 (0x00000230) -+ -+#define BP_PXP_CSC2_COEF5_RSVD1 25 -+#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 -+#define BF_PXP_CSC2_COEF5_RSVD1(v) \ -+ (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) -+#define BP_PXP_CSC2_COEF5_D3 16 -+#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 -+#define BF_PXP_CSC2_COEF5_D3(v) \ -+ (((v) << 16) & BM_PXP_CSC2_COEF5_D3) -+#define BP_PXP_CSC2_COEF5_RSVD0 9 -+#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 -+#define BF_PXP_CSC2_COEF5_RSVD0(v) \ -+ (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) -+#define BP_PXP_CSC2_COEF5_D2 0 -+#define BM_PXP_CSC2_COEF5_D2 0x000001FF -+#define BF_PXP_CSC2_COEF5_D2(v) \ -+ (((v) << 0) & BM_PXP_CSC2_COEF5_D2) -+ -+#define HW_PXP_LUT_CTRL (0x00000240) -+ -+#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 -+#define BF_PXP_LUT_CTRL_BYPASS(v) \ -+ (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS) -+#define BP_PXP_LUT_CTRL_RSVD3 26 -+#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 -+#define BF_PXP_LUT_CTRL_RSVD3(v) \ -+ (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) -+#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 -+#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 -+#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ -+ (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 -+#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 -+#define BP_PXP_LUT_CTRL_RSVD2 18 -+#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 -+#define BF_PXP_LUT_CTRL_RSVD2(v) \ -+ (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) -+#define BP_PXP_LUT_CTRL_OUT_MODE 16 -+#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 -+#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ -+ (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) -+#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 -+#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 -+#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 -+#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 -+#define BP_PXP_LUT_CTRL_RSVD1 11 -+#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 -+#define BF_PXP_LUT_CTRL_RSVD1(v) \ -+ (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) -+#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 -+#define BF_PXP_LUT_CTRL_SEL_8KB(v) \ -+ (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB) -+#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 -+#define BF_PXP_LUT_CTRL_LRU_UPD(v) \ -+ (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD) -+#define BM_PXP_LUT_CTRL_INVALID 0x00000100 -+#define BF_PXP_LUT_CTRL_INVALID(v) \ -+ (((v) << 8) & BM_PXP_LUT_CTRL_INVALID) -+#define BP_PXP_LUT_CTRL_RSVD0 1 -+#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE -+#define BF_PXP_LUT_CTRL_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) -+#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 -+#define BF_PXP_LUT_CTRL_DMA_START(v) \ -+ (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START) -+ -+#define HW_PXP_LUT_ADDR (0x00000250) -+ -+#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 -+#define BF_PXP_LUT_ADDR_RSVD2(v) \ -+ (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2) -+#define BP_PXP_LUT_ADDR_NUM_BYTES 16 -+#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 -+#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) -+#define BP_PXP_LUT_ADDR_RSVD1 14 -+#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 -+#define BF_PXP_LUT_ADDR_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) -+#define BP_PXP_LUT_ADDR_ADDR 0 -+#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF -+#define BF_PXP_LUT_ADDR_ADDR(v) \ -+ (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) -+ -+#define HW_PXP_LUT_DATA (0x00000260) -+ -+#define BP_PXP_LUT_DATA_DATA 0 -+#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF -+#define BF_PXP_LUT_DATA_DATA(v) (v) -+ -+#define HW_PXP_LUT_EXTMEM (0x00000270) -+ -+#define BP_PXP_LUT_EXTMEM_ADDR 0 -+#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF -+#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) -+ -+#define HW_PXP_CFA (0x00000280) -+ -+#define BP_PXP_CFA_DATA 0 -+#define BM_PXP_CFA_DATA 0xFFFFFFFF -+#define BF_PXP_CFA_DATA(v) (v) -+ -+#define HW_PXP_ALPHA_A_CTRL (0x00000290) -+ -+#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24 -+#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000 -+#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \ -+ (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA) -+#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16 -+#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 -+#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \ -+ (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA) -+#define BP_PXP_ALPHA_A_CTRL_RSVD0 14 -+#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000 -+#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0) -+#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000 -+#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \ -+ (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1 -+#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000 -+#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \ -+ (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1 -+#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10 -+#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 -+#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ -+ (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0 -+#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8 -+#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300 -+#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \ -+ (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1 -+#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2 -+#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3 -+#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080 -+#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \ -+ (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1) -+#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040 -+#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \ -+ (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1 -+#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020 -+#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \ -+ (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1 -+#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3 -+#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 -+#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ -+ (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 -+#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 -+#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 -+#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1 -+#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006 -+#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \ -+ (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE) -+#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1 -+#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2 -+#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3 -+#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001 -+#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE) -+#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0 -+#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1 -+ -+#define HW_PXP_ALPHA_B_CTRL (0x000002a0) -+ -+#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24 -+#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000 -+#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \ -+ (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA) -+#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16 -+#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 -+#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \ -+ (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA) -+#define BP_PXP_ALPHA_B_CTRL_RSVD0 14 -+#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000 -+#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0) -+#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000 -+#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \ -+ (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1 -+#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000 -+#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \ -+ (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1 -+#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10 -+#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 -+#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ -+ (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1 -+#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2 -+#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3 -+#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8 -+#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300 -+#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \ -+ (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1 -+#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2 -+#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3 -+#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080 -+#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \ -+ (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1) -+#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040 -+#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \ -+ (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1 -+#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020 -+#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \ -+ (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1 -+#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3 -+#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 -+#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ -+ (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 -+#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 -+#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 -+#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1 -+#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006 -+#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \ -+ (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE) -+#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1 -+#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2 -+#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3 -+#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001 -+#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE) -+#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0 -+#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1 -+ -+#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0) -+ -+#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8 -+#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00 -+#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \ -+ (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0) -+#define BP_PXP_ALPHA_B_CTRL_1_ROP 4 -+#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0 -+#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \ -+ (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP) -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9 -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA -+#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB -+#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2 -+#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C -+#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \ -+ (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1) -+#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002 -+#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \ -+ (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE) -+#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001 -+#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE) -+ -+#define HW_PXP_PS_BACKGROUND_1 (0x000002c0) -+ -+#define BP_PXP_PS_BACKGROUND_1_RSVD 24 -+#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000 -+#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \ -+ (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD) -+#define BP_PXP_PS_BACKGROUND_1_COLOR 0 -+#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF -+#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \ -+ (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR) -+ -+#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0) -+ -+#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24 -+#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000 -+#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1) -+#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0 -+#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF -+#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL) -+ -+#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0) -+ -+#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24 -+#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000 -+#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1) -+#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0 -+#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF -+#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL) -+ -+#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0) -+ -+#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24 -+#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000 -+#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1) -+#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0 -+#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF -+#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL) -+ -+#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300) -+ -+#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24 -+#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000 -+#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1) -+#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0 -+#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF -+#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL) -+ -+#define HW_PXP_CTRL2 (0x00000310) -+#define HW_PXP_CTRL2_SET (0x00000314) -+#define HW_PXP_CTRL2_CLR (0x00000318) -+#define HW_PXP_CTRL2_TOG (0x0000031c) -+ -+#define BP_PXP_CTRL2_RSVD3 28 -+#define BM_PXP_CTRL2_RSVD3 0xF0000000 -+#define BF_PXP_CTRL2_RSVD3(v) \ -+ (((v) << 28) & BM_PXP_CTRL2_RSVD3) -+#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000 -+#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \ -+ (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1) -+#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000 -+#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \ -+ (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0) -+#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000 -+#define BF_PXP_CTRL2_ENABLE_LUT(v) \ -+ (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT) -+#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000 -+#define BF_PXP_CTRL2_ENABLE_CSC2(v) \ -+ (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2) -+#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000 -+#define BF_PXP_CTRL2_BLOCK_SIZE(v) \ -+ (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE) -+#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0 -+#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1 -+#define BM_PXP_CTRL2_RSVD2 0x00400000 -+#define BF_PXP_CTRL2_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_CTRL2_RSVD2) -+#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000 -+#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \ -+ (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B) -+#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000 -+#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \ -+ (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE) -+#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000 -+#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \ -+ (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B) -+#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000 -+#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \ -+ (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A) -+#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000 -+#define BF_PXP_CTRL2_ENABLE_DITHER(v) \ -+ (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER) -+#define BM_PXP_CTRL2_RSVD1 0x00010000 -+#define BF_PXP_CTRL2_RSVD1(v) \ -+ (((v) << 16) & BM_PXP_CTRL2_RSVD1) -+#define BM_PXP_CTRL2_VFLIP1 0x00008000 -+#define BF_PXP_CTRL2_VFLIP1(v) \ -+ (((v) << 15) & BM_PXP_CTRL2_VFLIP1) -+#define BM_PXP_CTRL2_HFLIP1 0x00004000 -+#define BF_PXP_CTRL2_HFLIP1(v) \ -+ (((v) << 14) & BM_PXP_CTRL2_HFLIP1) -+#define BP_PXP_CTRL2_ROTATE1 12 -+#define BM_PXP_CTRL2_ROTATE1 0x00003000 -+#define BF_PXP_CTRL2_ROTATE1(v) \ -+ (((v) << 12) & BM_PXP_CTRL2_ROTATE1) -+#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0 -+#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1 -+#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2 -+#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3 -+#define BM_PXP_CTRL2_VFLIP0 0x00000800 -+#define BF_PXP_CTRL2_VFLIP0(v) \ -+ (((v) << 11) & BM_PXP_CTRL2_VFLIP0) -+#define BM_PXP_CTRL2_HFLIP0 0x00000400 -+#define BF_PXP_CTRL2_HFLIP0(v) \ -+ (((v) << 10) & BM_PXP_CTRL2_HFLIP0) -+#define BP_PXP_CTRL2_ROTATE0 8 -+#define BM_PXP_CTRL2_ROTATE0 0x00000300 -+#define BF_PXP_CTRL2_ROTATE0(v) \ -+ (((v) << 8) & BM_PXP_CTRL2_ROTATE0) -+#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0 -+#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1 -+#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2 -+#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3 -+#define BP_PXP_CTRL2_RSVD0 1 -+#define BM_PXP_CTRL2_RSVD0 0x000000FE -+#define BF_PXP_CTRL2_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_CTRL2_RSVD0) -+#define BM_PXP_CTRL2_ENABLE 0x00000001 -+#define BF_PXP_CTRL2_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_CTRL2_ENABLE) -+ -+#define HW_PXP_POWER_REG0 (0x00000320) -+ -+#define BP_PXP_POWER_REG0_CTRL 12 -+#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000 -+#define BF_PXP_POWER_REG0_CTRL(v) \ -+ (((v) << 12) & BM_PXP_POWER_REG0_CTRL) -+#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9 -+#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00 -+#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \ -+ (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE) -+#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6 -+#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0 -+#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \ -+ (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN) -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4 -+#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3 -+#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038 -+#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \ -+ (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN) -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4 -+#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0 -+#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007 -+#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \ -+ (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0) -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2 -+#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4 -+ -+#define HW_PXP_POWER_REG1 (0x00000330) -+ -+#define BP_PXP_POWER_REG1_RSVD0 24 -+#define BM_PXP_POWER_REG1_RSVD0 0xFF000000 -+#define BF_PXP_POWER_REG1_RSVD0(v) \ -+ (((v) << 24) & BM_PXP_POWER_REG1_RSVD0) -+#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21 -+#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000 -+#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \ -+ (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18 -+#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000 -+#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \ -+ (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15 -+#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000 -+#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \ -+ (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12 -+#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000 -+#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \ -+ (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9 -+#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00 -+#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \ -+ (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6 -+#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0 -+#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \ -+ (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3 -+#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038 -+#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \ -+ (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4 -+#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0 -+#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007 -+#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \ -+ (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE) -+#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0 -+#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1 -+#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2 -+#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4 -+ -+#define HW_PXP_DATA_PATH_CTRL0 (0x00000340) -+#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344) -+#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348) -+#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c) -+ -+#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30 -+#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \ -+ (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28 -+#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \ -+ (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26 -+#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \ -+ (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24 -+#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \ -+ (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22 -+#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \ -+ (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20 -+#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \ -+ (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18 -+#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \ -+ (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16 -+#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \ -+ (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14 -+#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \ -+ (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12 -+#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000 -+#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \ -+ (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10 -+#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00 -+#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \ -+ (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8 -+#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300 -+#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \ -+ (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6 -+#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0 -+#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \ -+ (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4 -+#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030 -+#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \ -+ (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2 -+#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C -+#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \ -+ (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0 -+#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003 -+#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \ -+ (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL) -+#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3 -+ -+#define HW_PXP_DATA_PATH_CTRL1 (0x00000350) -+#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354) -+#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358) -+#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c) -+ -+#define BP_PXP_DATA_PATH_CTRL1_RSVD0 4 -+#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0 -+#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \ -+ (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0) -+#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2 -+#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C -+#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \ -+ (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL) -+#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3 -+#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0 -+#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003 -+#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \ -+ (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL) -+#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0 -+#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1 -+#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2 -+#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3 -+ -+#define HW_PXP_INIT_MEM_CTRL (0x00000360) -+#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364) -+#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368) -+#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c) -+ -+#define BM_PXP_INIT_MEM_CTRL_START 0x80000000 -+#define BF_PXP_INIT_MEM_CTRL_START(v) \ -+ (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START) -+#define BP_PXP_INIT_MEM_CTRL_SELECT 27 -+#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000 -+#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \ -+ (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT) -+#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8 -+#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15 -+#define BP_PXP_INIT_MEM_CTRL_RSVD0 16 -+#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000 -+#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0) -+#define BP_PXP_INIT_MEM_CTRL_ADDR 0 -+#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF -+#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \ -+ (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR) -+ -+#define HW_PXP_INIT_MEM_DATA (0x00000370) -+ -+#define BP_PXP_INIT_MEM_DATA_DATA 0 -+#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF -+#define BF_PXP_INIT_MEM_DATA_DATA(v) (v) -+ -+#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380) -+ -+#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0 -+#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF -+#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v) -+ -+#define HW_PXP_IRQ_MASK (0x00000390) -+#define HW_PXP_IRQ_MASK_SET (0x00000394) -+#define HW_PXP_IRQ_MASK_CLR (0x00000398) -+#define HW_PXP_IRQ_MASK_TOG (0x0000039c) -+ -+#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000 -+#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \ -+ (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN) -+#define BP_PXP_IRQ_MASK_RSVD1 16 -+#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000 -+#define BF_PXP_IRQ_MASK_RSVD1(v) \ -+ (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1) -+#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000 -+#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \ -+ (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000 -+#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \ -+ (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000 -+#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \ -+ (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000 -+#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \ -+ (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800 -+#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \ -+ (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400 -+#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \ -+ (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200 -+#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \ -+ (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100 -+#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \ -+ (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080 -+#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \ -+ (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040 -+#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \ -+ (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020 -+#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \ -+ (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN) -+#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010 -+#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \ -+ (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN) -+#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008 -+#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \ -+ (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004 -+#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \ -+ (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN) -+#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002 -+#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \ -+ (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN) -+#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001 -+#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \ -+ (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN) -+ -+#define HW_PXP_IRQ (0x000003a0) -+#define HW_PXP_IRQ_SET (0x000003a4) -+#define HW_PXP_IRQ_CLR (0x000003a8) -+#define HW_PXP_IRQ_TOG (0x000003ac) -+ -+#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000 -+#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \ -+ (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ) -+#define BP_PXP_IRQ_RSVD1 16 -+#define BM_PXP_IRQ_RSVD1 0x7FFF0000 -+#define BF_PXP_IRQ_RSVD1(v) \ -+ (((v) << 16) & BM_PXP_IRQ_RSVD1) -+#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000 -+#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \ -+ (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ) -+#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000 -+#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \ -+ (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ) -+#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000 -+#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \ -+ (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ) -+#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000 -+#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \ -+ (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ) -+#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800 -+#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \ -+ (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) -+#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400 -+#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \ -+ (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) -+#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200 -+#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \ -+ (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) -+#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100 -+#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \ -+ (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) -+#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080 -+#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \ -+ (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) -+#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040 -+#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \ -+ (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) -+#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020 -+#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \ -+ (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) -+#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010 -+#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \ -+ (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) -+#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008 -+#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \ -+ (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) -+#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004 -+#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \ -+ (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) -+#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002 -+#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \ -+ (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) -+#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001 -+#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \ -+ (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) -+ -+#define HW_PXP_NEXT (0x00000400) -+ -+#define BP_PXP_NEXT_POINTER 2 -+#define BM_PXP_NEXT_POINTER 0xFFFFFFFC -+#define BF_PXP_NEXT_POINTER(v) \ -+ (((v) << 2) & BM_PXP_NEXT_POINTER) -+#define BM_PXP_NEXT_RSVD 0x00000002 -+#define BF_PXP_NEXT_RSVD(v) \ -+ (((v) << 1) & BM_PXP_NEXT_RSVD) -+#define BM_PXP_NEXT_ENABLED 0x00000001 -+#define BF_PXP_NEXT_ENABLED(v) \ -+ (((v) << 0) & BM_PXP_NEXT_ENABLED) -+ -+#define HW_PXP_DEBUGCTRL (0x00000410) -+ -+#define BP_PXP_DEBUGCTRL_RSVD 12 -+#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 -+#define BF_PXP_DEBUGCTRL_RSVD(v) \ -+ (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) -+#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 -+#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 -+#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ -+ (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 -+#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 -+#define BP_PXP_DEBUGCTRL_SELECT 0 -+#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF -+#define BF_PXP_DEBUGCTRL_SELECT(v) \ -+ (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) -+#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 -+#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 -+#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 -+#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 -+#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 -+#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 -+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 -+#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 -+#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 -+#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 -+#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 -+ -+#define HW_PXP_DEBUG (0x00000420) -+ -+#define BP_PXP_DEBUG_DATA 0 -+#define BM_PXP_DEBUG_DATA 0xFFFFFFFF -+#define BF_PXP_DEBUG_DATA(v) (v) -+ -+#define HW_PXP_VERSION (0x00000430) -+ -+#define BP_PXP_VERSION_MAJOR 24 -+#define BM_PXP_VERSION_MAJOR 0xFF000000 -+#define BF_PXP_VERSION_MAJOR(v) \ -+ (((v) << 24) & BM_PXP_VERSION_MAJOR) -+#define BP_PXP_VERSION_MINOR 16 -+#define BM_PXP_VERSION_MINOR 0x00FF0000 -+#define BF_PXP_VERSION_MINOR(v) \ -+ (((v) << 16) & BM_PXP_VERSION_MINOR) -+#define BP_PXP_VERSION_STEP 0 -+#define BM_PXP_VERSION_STEP 0x0000FFFF -+#define BF_PXP_VERSION_STEP(v) \ -+ (((v) << 0) & BM_PXP_VERSION_STEP) -+ -+#define HW_PXP_INPUT_FETCH_CTRL_CH0 (0x00000450) -+#define HW_PXP_INPUT_FETCH_CTRL_CH0_SET (0x00000454) -+#define HW_PXP_INPUT_FETCH_CTRL_CH0_CLR (0x00000458) -+#define HW_PXP_INPUT_FETCH_CTRL_CH0_TOG (0x0000045c) -+ -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(v) \ -+ (((v) << 31) & BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 26 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 0x7C000000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(v) \ -+ (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0) -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ -+ (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 18 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 0x00FC0000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1) -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 16 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 14 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 0x0000C000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2) -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 12 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ -+ (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3 0x00000800 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD3(v) \ -+ (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3) -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP 0x00000400 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_VFLIP(v) \ -+ (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP 0x00000200 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_HFLIP(v) \ -+ (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__1 0x1 -+#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 6 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 0x000001C0 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(v) \ -+ (((v) << 6) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4) -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE(v) \ -+ (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ -+ (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16 0x00000004 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN 0x00000001 -+#define BF_PXP_INPUT_FETCH_CTRL_CH0_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__1 0x1 -+ -+#define HW_PXP_INPUT_FETCH_CTRL_CH1 (0x00000460) -+#define HW_PXP_INPUT_FETCH_CTRL_CH1_SET (0x00000464) -+#define HW_PXP_INPUT_FETCH_CTRL_CH1_CLR (0x00000468) -+#define HW_PXP_INPUT_FETCH_CTRL_CH1_TOG (0x0000046c) -+ -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 26 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 0xFC000000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(v) \ -+ (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0) -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ -+ (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 18 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 0x00FC0000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1) -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 16 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 14 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 0x0000C000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2) -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 12 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ -+ (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3 0x00000800 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD3(v) \ -+ (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3) -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP 0x00000400 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_VFLIP(v) \ -+ (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP 0x00000200 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_HFLIP(v) \ -+ (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__1 0x1 -+#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 5 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 0x000001E0 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(v) \ -+ (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4) -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ -+ (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16 0x00000004 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 -+#define BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN 0x00000001 -+#define BF_PXP_INPUT_FETCH_CTRL_CH1_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN) -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__1 0x1 -+ -+#define HW_PXP_INPUT_FETCH_STATUS_CH0 (0x00000470) -+ -+#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 -+#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) -+#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 -+#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) -+ -+#define HW_PXP_INPUT_FETCH_STATUS_CH1 (0x00000480) -+ -+#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 -+#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) -+#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 -+#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) -+ -+#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000490) -+ -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) -+ -+#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000004a0) -+ -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) -+ -+#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000004b0) -+ -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) -+ -+#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000004c0) -+ -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) -+#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 -+#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) -+ -+#define HW_PXP_INPUT_FETCH_SIZE_CH0 (0x000004d0) -+ -+#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 -+#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) -+#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 -+#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) -+ -+#define HW_PXP_INPUT_FETCH_SIZE_CH1 (0x000004e0) -+ -+#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 -+#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) -+#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 -+#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) -+ -+#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 (0x000004f0) -+ -+#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 -+#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF -+#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) -+ -+#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 (0x00000500) -+ -+#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 -+#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF -+#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) -+ -+#define HW_PXP_INPUT_FETCH_PITCH (0x00000510) -+ -+#define BP_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 16 -+#define BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH) -+#define BP_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0 -+#define BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF -+#define BF_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH) -+ -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 (0x00000520) -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET (0x00000524) -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR (0x00000528) -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG (0x0000052c) -+ -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 13 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ -+ (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0) -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ -+ (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ -+ (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ -+ (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 2 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ -+ (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1) -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 -+ -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 (0x00000530) -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET (0x00000534) -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR (0x00000538) -+#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG (0x0000053c) -+ -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 13 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ -+ (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0) -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ -+ (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ -+ (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ -+ (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 2 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ -+ (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1) -+#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 -+#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 -+#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 -+ -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 (0x00000540) -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET (0x00000544) -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000548) -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000054c) -+ -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ -+ (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ -+ (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ -+ (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0) -+ -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 (0x00000550) -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET (0x00000554) -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000558) -+#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000055c) -+ -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ -+ (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ -+ (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ -+ (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3) -+#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 -+#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F -+#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0) -+ -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 (0x00000560) -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET (0x00000564) -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000568) -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000056c) -+ -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ -+ (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ -+ (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ -+ (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0) -+ -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 (0x00000570) -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET (0x00000574) -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000578) -+#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000057c) -+ -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ -+ (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ -+ (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ -+ (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1) -+#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 -+#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F -+#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0) -+ -+#define HW_PXP_INPUT_FETCH_ADDR_0_CH0 (0x00000580) -+ -+#define BP_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 -+#define BM_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_INPUT_FETCH_ADDR_1_CH0 (0x00000590) -+ -+#define BP_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 -+#define BM_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_INPUT_FETCH_ADDR_0_CH1 (0x000005a0) -+ -+#define BP_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 -+#define BM_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_INPUT_FETCH_ADDR_1_CH1 (0x000005b0) -+ -+#define BP_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 -+#define BM_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_INPUT_STORE_CTRL_CH0 (0x000005c0) -+#define HW_PXP_INPUT_STORE_CTRL_CH0_SET (0x000005c4) -+#define HW_PXP_INPUT_STORE_CTRL_CH0_CLR (0x000005c8) -+#define HW_PXP_INPUT_STORE_CTRL_CH0_TOG (0x000005cc) -+ -+#define BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN 0x80000000 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(v) \ -+ (((v) << 31) & BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__1 0x1 -+#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD0 25 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0 0x7E000000 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD0(v) \ -+ (((v) << 25) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0) -+#define BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 -+#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD1 18 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1 0x00FC0000 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1) -+#define BP_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 16 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD2 12 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2 0x0000F000 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD2(v) \ -+ (((v) << 12) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2) -+#define BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(v) \ -+ (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3 0x00000080 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3) -+#define BP_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN 0x00000010 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16 0x00000004 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN 0x00000002 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN 0x00000001 -+#define BF_PXP_INPUT_STORE_CTRL_CH0_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__1 0x1 -+ -+#define HW_PXP_INPUT_STORE_CTRL_CH1 (0x000005d0) -+#define HW_PXP_INPUT_STORE_CTRL_CH1_SET (0x000005d4) -+#define HW_PXP_INPUT_STORE_CTRL_CH1_CLR (0x000005d8) -+#define HW_PXP_INPUT_STORE_CTRL_CH1_TOG (0x000005dc) -+ -+#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD0 18 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0 0xFFFC0000 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD0(v) \ -+ (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0) -+#define BP_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 16 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD1 11 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1 0x0000F800 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD1(v) \ -+ (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1) -+#define BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3 0x00000080 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3) -+#define BP_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN 0x00000010 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16 0x00000004 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN 0x00000002 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN 0x00000001 -+#define BF_PXP_INPUT_STORE_CTRL_CH1_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN) -+#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__1 0x1 -+ -+#define HW_PXP_INPUT_STORE_STATUS_CH0 (0x000005e0) -+ -+#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 16 -+#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y) -+#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0 -+#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X) -+ -+#define HW_PXP_INPUT_STORE_STATUS_CH1 (0x000005f0) -+ -+#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 16 -+#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y) -+#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0 -+#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X) -+ -+#define HW_PXP_INPUT_STORE_SIZE_CH0 (0x00000600) -+ -+#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 16 -+#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT) -+#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0 -+#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH) -+ -+#define HW_PXP_INPUT_STORE_SIZE_CH1 (0x00000610) -+ -+#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 16 -+#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT) -+#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0 -+#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH) -+ -+#define HW_PXP_INPUT_STORE_PITCH (0x00000620) -+ -+#define BP_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 16 -+#define BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 -+#define BF_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH) -+#define BP_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0 -+#define BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF -+#define BF_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH) -+ -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 (0x00000630) -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET (0x00000634) -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR (0x00000638) -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG (0x0000063c) -+ -+#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 8 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0) -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ -+ (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1) -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2) -+ -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 (0x00000640) -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET (0x00000644) -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR (0x00000648) -+#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG (0x0000064c) -+ -+#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 6 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0) -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0 -+#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 -+#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2) -+ -+#define HW_PXP_INPUT_STORE_ADDR_0_CH0 (0x00000690) -+ -+#define BP_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 -+#define BM_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_ADDR_1_CH0 (0x000006a0) -+ -+#define BP_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 -+#define BM_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_INPUT_STORE_FILL_DATA_CH0 (0x000006b0) -+ -+#define BP_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 -+#define BM_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_ADDR_0_CH1 (0x000006c0) -+ -+#define BP_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 -+#define BM_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_ADDR_1_CH1 (0x000006d0) -+ -+#define BP_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 -+#define BM_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK0_H_CH0 (0x000006e0) -+ -+#define BP_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK0_L_CH0 (0x000006f0) -+ -+#define BP_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK1_H_CH0 (0x00000700) -+ -+#define BP_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK1_L_CH0 (0x00000710) -+ -+#define BP_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK2_H_CH0 (0x00000720) -+ -+#define BP_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK2_L_CH0 (0x00000730) -+ -+#define BP_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK3_H_CH0 (0x00000740) -+ -+#define BP_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK3_L_CH0 (0x00000750) -+ -+#define BP_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK4_H_CH0 (0x00000760) -+ -+#define BP_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK4_L_CH0 (0x00000770) -+ -+#define BP_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK5_H_CH0 (0x00000780) -+ -+#define BP_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK5_L_CH0 (0x00000790) -+ -+#define BP_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK6_H_CH0 (0x000007a0) -+ -+#define BP_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK6_L_CH0 (0x000007b0) -+ -+#define BP_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK7_H_CH0 (0x000007c0) -+ -+#define BP_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_MASK7_L_CH0 (0x000007e0) -+ -+#define BP_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 -+#define BM_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF -+#define BF_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) -+ -+#define HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 (0x000007f0) -+ -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ -+ (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0) -+#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ -+ (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1) -+#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ -+ (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2) -+#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3) -+#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 -+#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) -+ -+#define HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 (0x00000800) -+ -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ -+ (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0) -+#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ -+ (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1) -+#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ -+ (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2) -+#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3) -+#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 -+#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) -+ -+#define HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 (0x00000810) -+ -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ -+ (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) -+#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ -+ (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) -+#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ -+ (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) -+#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3) -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ -+ (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) -+#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 -+#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) -+ -+#define HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 (0x00000820) -+ -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ -+ (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) -+#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ -+ (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) -+#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ -+ (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) -+#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3) -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ -+ (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) -+#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 -+#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) -+ -+#define HW_PXP_INPUT_STORE_F_MASK_L_CH0 (0x00000830) -+ -+#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 24 -+#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 -+#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3) -+#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 16 -+#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 -+#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2) -+#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 8 -+#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 -+#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1) -+#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0 -+#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF -+#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0) -+ -+#define HW_PXP_INPUT_STORE_F_MASK_H_CH0 (0x00000840) -+ -+#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 24 -+#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 -+#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(v) \ -+ (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7) -+#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 16 -+#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 -+#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(v) \ -+ (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6) -+#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 8 -+#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 -+#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(v) \ -+ (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5) -+#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0 -+#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF -+#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(v) \ -+ (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4) -+ -+#define HW_PXP_DITHER_FETCH_CTRL_CH0 (0x00000850) -+#define HW_PXP_DITHER_FETCH_CTRL_CH0_SET (0x00000854) -+#define HW_PXP_DITHER_FETCH_CTRL_CH0_CLR (0x00000858) -+#define HW_PXP_DITHER_FETCH_CTRL_CH0_TOG (0x0000085c) -+ -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(v) \ -+ (((v) << 31) & BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 26 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 0x7C000000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(v) \ -+ (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0) -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 18 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 0x00FC0000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1) -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 16 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 14 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 0x0000C000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2) -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 12 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ -+ (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3 0x00000800 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD3(v) \ -+ (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3) -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP 0x00000400 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(v) \ -+ (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP 0x00000200 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(v) \ -+ (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__1 0x1 -+#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 6 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 0x000001C0 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(v) \ -+ (((v) << 6) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4) -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(v) \ -+ (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ -+ (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16 0x00000004 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN 0x00000001 -+#define BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__1 0x1 -+ -+#define HW_PXP_DITHER_FETCH_CTRL_CH1 (0x00000860) -+#define HW_PXP_DITHER_FETCH_CTRL_CH1_SET (0x00000864) -+#define HW_PXP_DITHER_FETCH_CTRL_CH1_CLR (0x00000868) -+#define HW_PXP_DITHER_FETCH_CTRL_CH1_TOG (0x0000086c) -+ -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 26 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 0xFC000000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(v) \ -+ (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0) -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 18 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 0x00FC0000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1) -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 16 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 14 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 0x0000C000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2) -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 12 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ -+ (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3 0x00000800 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD3(v) \ -+ (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3) -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP 0x00000400 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(v) \ -+ (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP 0x00000200 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(v) \ -+ (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__1 0x1 -+#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 5 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 0x000001E0 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(v) \ -+ (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4) -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ -+ (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16 0x00000004 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 -+#define BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN 0x00000001 -+#define BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN) -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__1 0x1 -+ -+#define HW_PXP_DITHER_FETCH_STATUS_CH0 (0x00000870) -+ -+#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 -+#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) -+#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 -+#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) -+ -+#define HW_PXP_DITHER_FETCH_STATUS_CH1 (0x00000880) -+ -+#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 -+#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) -+#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 -+#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) -+ -+#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000890) -+ -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) -+ -+#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000008a0) -+ -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) -+ -+#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000008b0) -+ -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) -+ -+#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000008c0) -+ -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) -+#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 -+#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) -+ -+#define HW_PXP_DITHER_FETCH_SIZE_CH0 (0x000008d0) -+ -+#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 -+#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) -+#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 -+#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) -+ -+#define HW_PXP_DITHER_FETCH_SIZE_CH1 (0x000008e0) -+ -+#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 -+#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) -+#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 -+#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) -+ -+#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 (0x000008f0) -+ -+#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 -+#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF -+#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) -+ -+#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 (0x00000900) -+ -+#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 -+#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF -+#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) -+ -+#define HW_PXP_DITHER_FETCH_PITCH (0x00000910) -+ -+#define BP_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 16 -+#define BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH) -+#define BP_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0 -+#define BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF -+#define BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH) -+ -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 (0x00000920) -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET (0x00000924) -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR (0x00000928) -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG (0x0000092c) -+ -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 13 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ -+ (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0) -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ -+ (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ -+ (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 2 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ -+ (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1) -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 -+ -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 (0x00000930) -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET (0x00000934) -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR (0x00000938) -+#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG (0x0000093c) -+ -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 13 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ -+ (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0) -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ -+ (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ -+ (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 2 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ -+ (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1) -+#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 -+#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 -+#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 -+ -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 (0x00000940) -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET (0x00000944) -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000948) -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000094c) -+ -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ -+ (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0) -+ -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 (0x00000950) -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET (0x00000954) -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000958) -+#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000095c) -+ -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ -+ (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3) -+#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 -+#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F -+#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0) -+ -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 (0x00000960) -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET (0x00000964) -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000968) -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000096c) -+ -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ -+ (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ -+ (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0) -+ -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 (0x00000970) -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET (0x00000974) -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000978) -+#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000097c) -+ -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ -+ (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ -+ (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1) -+#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 -+#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F -+#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0) -+ -+#define HW_PXP_DITHER_FETCH_ADDR_0_CH0 (0x00000980) -+ -+#define BP_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 -+#define BM_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_DITHER_FETCH_ADDR_1_CH0 (0x00000990) -+ -+#define BP_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 -+#define BM_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_DITHER_FETCH_ADDR_0_CH1 (0x000009a0) -+ -+#define BP_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 -+#define BM_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_DITHER_FETCH_ADDR_1_CH1 (0x000009b0) -+ -+#define BP_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 -+#define BM_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_DITHER_STORE_CTRL_CH0 (0x000009c0) -+#define HW_PXP_DITHER_STORE_CTRL_CH0_SET (0x000009c4) -+#define HW_PXP_DITHER_STORE_CTRL_CH0_CLR (0x000009c8) -+#define HW_PXP_DITHER_STORE_CTRL_CH0_TOG (0x000009cc) -+ -+#define BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN 0x80000000 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(v) \ -+ (((v) << 31) & BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__1 0x1 -+#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD0 25 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0 0x7E000000 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD0(v) \ -+ (((v) << 25) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0) -+#define BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 -+#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD1 18 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1 0x00FC0000 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1) -+#define BP_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 16 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD2 12 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2 0x0000F000 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD2(v) \ -+ (((v) << 12) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2) -+#define BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(v) \ -+ (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3 0x00000080 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3) -+#define BP_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN 0x00000010 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16 0x00000004 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN 0x00000002 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN 0x00000001 -+#define BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__1 0x1 -+ -+#define HW_PXP_DITHER_STORE_CTRL_CH1 (0x000009d0) -+#define HW_PXP_DITHER_STORE_CTRL_CH1_SET (0x000009d4) -+#define HW_PXP_DITHER_STORE_CTRL_CH1_CLR (0x000009d8) -+#define HW_PXP_DITHER_STORE_CTRL_CH1_TOG (0x000009dc) -+ -+#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD0 18 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0 0xFFFC0000 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD0(v) \ -+ (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0) -+#define BP_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 16 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD1 11 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1 0x0000F800 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD1(v) \ -+ (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1) -+#define BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3 0x00000080 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3) -+#define BP_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN 0x00000010 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16 0x00000004 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN 0x00000002 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN 0x00000001 -+#define BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN) -+#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__1 0x1 -+ -+#define HW_PXP_DITHER_STORE_STATUS_CH0 (0x000009e0) -+ -+#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 16 -+#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y) -+#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0 -+#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X) -+ -+#define HW_PXP_DITHER_STORE_STATUS_CH1 (0x000009f0) -+ -+#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 16 -+#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y) -+#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0 -+#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X) -+ -+#define HW_PXP_DITHER_STORE_SIZE_CH0 (0x00000a00) -+ -+#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 16 -+#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT) -+#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0 -+#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH) -+ -+#define HW_PXP_DITHER_STORE_SIZE_CH1 (0x00000a10) -+ -+#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 16 -+#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT) -+#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0 -+#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH) -+ -+#define HW_PXP_DITHER_STORE_PITCH (0x00000a20) -+ -+#define BP_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 16 -+#define BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 -+#define BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH) -+#define BP_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0 -+#define BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF -+#define BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH) -+ -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 (0x00000a30) -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET (0x00000a34) -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR (0x00000a38) -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG (0x00000a3c) -+ -+#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 8 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0) -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ -+ (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1) -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2) -+ -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 (0x00000a40) -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET (0x00000a44) -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR (0x00000a48) -+#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG (0x00000a4c) -+ -+#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 6 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0) -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0 -+#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 -+#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2) -+ -+#define HW_PXP_DITHER_STORE_ADDR_0_CH0 (0x00000a90) -+ -+#define BP_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 -+#define BM_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_ADDR_1_CH0 (0x00000aa0) -+ -+#define BP_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 -+#define BM_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_DITHER_STORE_FILL_DATA_CH0 (0x00000ab0) -+ -+#define BP_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 -+#define BM_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_ADDR_0_CH1 (0x00000ac0) -+ -+#define BP_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 -+#define BM_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_ADDR_1_CH1 (0x00000ad0) -+ -+#define BP_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 -+#define BM_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK0_H_CH0 (0x00000ae0) -+ -+#define BP_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK0_L_CH0 (0x00000af0) -+ -+#define BP_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK1_H_CH0 (0x00000b00) -+ -+#define BP_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK1_L_CH0 (0x00000b10) -+ -+#define BP_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK2_H_CH0 (0x00000b20) -+ -+#define BP_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK2_L_CH0 (0x00000b30) -+ -+#define BP_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK3_H_CH0 (0x00000b40) -+ -+#define BP_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK3_L_CH0 (0x00000b50) -+ -+#define BP_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK4_H_CH0 (0x00000b60) -+ -+#define BP_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK4_L_CH0 (0x00000b70) -+ -+#define BP_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK5_H_CH0 (0x00000b80) -+ -+#define BP_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK5_L_CH0 (0x00000b90) -+ -+#define BP_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK6_H_CH0 (0x00000ba0) -+ -+#define BP_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK6_L_CH0 (0x00000bb0) -+ -+#define BP_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK7_H_CH0 (0x00000bc0) -+ -+#define BP_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_MASK7_L_CH0 (0x00000bd0) -+ -+#define BP_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 -+#define BM_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF -+#define BF_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) -+ -+#define HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 (0x00000be0) -+ -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ -+ (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0) -+#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ -+ (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1) -+#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ -+ (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2) -+#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3) -+#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 -+#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) -+ -+#define HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 (0x00000bf0) -+ -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ -+ (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0) -+#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ -+ (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1) -+#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ -+ (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2) -+#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3) -+#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 -+#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) -+ -+#define HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 (0x00000c00) -+ -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ -+ (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) -+#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ -+ (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) -+#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ -+ (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) -+#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3) -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ -+ (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) -+#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 -+#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) -+ -+#define HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 (0x00000c10) -+ -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ -+ (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) -+#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ -+ (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) -+#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ -+ (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) -+#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3) -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ -+ (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) -+#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 -+#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) -+ -+#define HW_PXP_DITHER_STORE_F_MASK_L_CH0 (0x00000c20) -+ -+#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 24 -+#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 -+#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3) -+#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 16 -+#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 -+#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2) -+#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 8 -+#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 -+#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1) -+#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0 -+#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF -+#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0) -+ -+#define HW_PXP_DITHER_STORE_F_MASK_H_CH0 (0x00000c30) -+ -+#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 24 -+#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 -+#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(v) \ -+ (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7) -+#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 16 -+#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 -+#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(v) \ -+ (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6) -+#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 8 -+#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 -+#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(v) \ -+ (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5) -+#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0 -+#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF -+#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(v) \ -+ (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4) -+ -+#define HW_PXP_WFA_FETCH_CTRL (0x00000c40) -+#define HW_PXP_WFA_FETCH_CTRL_SET (0x00000c44) -+#define HW_PXP_WFA_FETCH_CTRL_CLR (0x00000c48) -+#define HW_PXP_WFA_FETCH_CTRL_TOG (0x00000c4c) -+ -+#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 -+#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ -+ (((v) << 31) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN) -+#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 -+#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ -+ (((v) << 30) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN) -+#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 -+#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ(v) \ -+ (((v) << 29) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ) -+#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 -+#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ(v) \ -+ (((v) << 28) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ) -+#define BP_PXP_WFA_FETCH_CTRL_RSVD0 24 -+#define BM_PXP_WFA_FETCH_CTRL_RSVD0 0x0F000000 -+#define BF_PXP_WFA_FETCH_CTRL_RSVD0(v) \ -+ (((v) << 24) & BM_PXP_WFA_FETCH_CTRL_RSVD0) -+#define BP_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 22 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(v) \ -+ (((v) << 22) & BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__1 0x1 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__2 0x2 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__3 0x3 -+#define BP_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 20 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 0x00300000 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(v) \ -+ (((v) << 20) & BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP) -+#define BP_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 18 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(v) \ -+ (((v) << 18) & BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__1 0x1 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__2 0x2 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__3 0x3 -+#define BP_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 16 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 0x00030000 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP) -+#define BP_PXP_WFA_FETCH_CTRL_RSVD1 14 -+#define BM_PXP_WFA_FETCH_CTRL_RSVD1 0x0000C000 -+#define BF_PXP_WFA_FETCH_CTRL_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFA_FETCH_CTRL_RSVD1) -+#define BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE(v) \ -+ (((v) << 13) & BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN 0x00001000 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(v) \ -+ (((v) << 12) & BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(v) \ -+ (((v) << 11) & BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE 0x00000400 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(v) \ -+ (((v) << 10) & BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF 0x00000200 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(v) \ -+ (((v) << 9) & BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF2_EN 0x00000100 -+#define BF_PXP_WFA_FETCH_CTRL_BF2_EN(v) \ -+ (((v) << 8) & BM_PXP_WFA_FETCH_CTRL_BF2_EN) -+#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__1 0x1 -+#define BP_PXP_WFA_FETCH_CTRL_RSVD2 6 -+#define BM_PXP_WFA_FETCH_CTRL_RSVD2 0x000000C0 -+#define BF_PXP_WFA_FETCH_CTRL_RSVD2(v) \ -+ (((v) << 6) & BM_PXP_WFA_FETCH_CTRL_RSVD2) -+#define BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE(v) \ -+ (((v) << 5) & BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN 0x00000010 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(v) \ -+ (((v) << 4) & BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(v) \ -+ (((v) << 3) & BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE 0x00000004 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(v) \ -+ (((v) << 2) & BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF 0x00000002 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(v) \ -+ (((v) << 1) & BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__1 0x1 -+#define BM_PXP_WFA_FETCH_CTRL_BF1_EN 0x00000001 -+#define BF_PXP_WFA_FETCH_CTRL_BF1_EN(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_CTRL_BF1_EN) -+#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__0 0x0 -+#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__1 0x1 -+ -+#define HW_PXP_WFA_FETCH_BUF1_ADDR (0x00000c50) -+ -+#define BP_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0 -+#define BM_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) -+ -+#define HW_PXP_WFA_FETCH_BUF1_PITCH (0x00000c60) -+ -+#define BP_PXP_WFA_FETCH_BUF1_PITCH_RSVD 16 -+#define BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_WFA_FETCH_BUF1_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD) -+#define BP_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0 -+#define BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_WFA_FETCH_BUF1_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH) -+ -+#define HW_PXP_WFA_FETCH_BUF1_SIZE (0x00000c70) -+ -+#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 30 -+#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 0xC0000000 -+#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0) -+#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 16 -+#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 0x3FFF0000 -+#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT) -+#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 14 -+#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 0x0000C000 -+#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1) -+#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0 -+#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0x00003FFF -+#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH) -+ -+#define HW_PXP_WFA_FETCH_BUF2_ADDR (0x00000c80) -+ -+#define BP_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0 -+#define BM_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) -+ -+#define HW_PXP_WFA_FETCH_BUF2_PITCH (0x00000c90) -+ -+#define BP_PXP_WFA_FETCH_BUF2_PITCH_RSVD 16 -+#define BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_WFA_FETCH_BUF2_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD) -+#define BP_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0 -+#define BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_WFA_FETCH_BUF2_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH) -+ -+#define HW_PXP_WFA_FETCH_BUF2_SIZE (0x00000ca0) -+ -+#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 30 -+#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 0xC0000000 -+#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0) -+#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 16 -+#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 0x3FFF0000 -+#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT) -+#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 14 -+#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 0x0000C000 -+#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1) -+#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0 -+#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0x00003FFF -+#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL0_MASK (0x00000cb0) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL1_MASK (0x00000cc0) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL2_MASK (0x00000cd0) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL3_MASK (0x00000ce0) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL4_MASK (0x00000cf0) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL5_MASK (0x00000d00) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL6_MASK (0x00000d10) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_PIXEL7_MASK (0x00000d20) -+ -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG0_MASK (0x00000d30) -+ -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG1_MASK (0x00000d40) -+ -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG2_MASK (0x00000d50) -+ -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG3_MASK (0x00000d60) -+ -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG4_MASK (0x00000d70) -+ -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG5_MASK (0x00000d80) -+ -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG6_MASK (0x00000d90) -+ -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG7_MASK (0x00000da0) -+ -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS) -+ -+#define HW_PXP_WFA_FETCH_BUF1_CORD (0x00000db0) -+ -+#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD0 30 -+#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0 0xC0000000 -+#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0) -+#define BP_PXP_WFA_FETCH_BUF1_CORD_YCORD 16 -+#define BM_PXP_WFA_FETCH_BUF1_CORD_YCORD 0x3FFF0000 -+#define BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_CORD_YCORD) -+#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD1 14 -+#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1 0x0000C000 -+#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1) -+#define BP_PXP_WFA_FETCH_BUF1_CORD_XCORD 0 -+#define BM_PXP_WFA_FETCH_BUF1_CORD_XCORD 0x00003FFF -+#define BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_CORD_XCORD) -+ -+#define HW_PXP_WFA_FETCH_BUF2_CORD (0x00000dc0) -+ -+#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD0 30 -+#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0 0xC0000000 -+#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0) -+#define BP_PXP_WFA_FETCH_BUF2_CORD_YCORD 16 -+#define BM_PXP_WFA_FETCH_BUF2_CORD_YCORD 0x3FFF0000 -+#define BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(v) \ -+ (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_CORD_YCORD) -+#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD1 14 -+#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1 0x0000C000 -+#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1) -+#define BP_PXP_WFA_FETCH_BUF2_CORD_XCORD 0 -+#define BM_PXP_WFA_FETCH_BUF2_CORD_XCORD 0x00003FFF -+#define BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(v) \ -+ (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_CORD_XCORD) -+ -+#define HW_PXP_WFA_ARRAY_FLAG8_MASK (0x00000dd0) -+ -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG9_MASK (0x00000de0) -+ -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG10_MASK (0x00000df0) -+ -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG11_MASK (0x00000e00) -+ -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG12_MASK (0x00000e10) -+ -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG13_MASK (0x00000e20) -+ -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG14_MASK (0x00000e30) -+ -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_FLAG15_MASK (0x00000e40) -+ -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 30 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 28 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL) -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 26 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1) -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y) -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X) -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 22 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 20 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 18 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 16 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 13 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 8 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 5 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5) -+#define BP_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0 -+#define BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS) -+ -+#define HW_PXP_WFA_ARRAY_REG0 (0x00000e50) -+ -+#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE3 24 -+#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3 0xFF000000 -+#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE3(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3) -+#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE2 16 -+#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2 0x00FF0000 -+#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE2(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2) -+#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE1 8 -+#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1 0x0000FF00 -+#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE1(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1) -+#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0 -+#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0x000000FF -+#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE0(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0) -+ -+#define HW_PXP_WFA_ARRAY_REG1 (0x00000e60) -+ -+#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE7 24 -+#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7 0xFF000000 -+#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE7(v) \ -+ (((v) << 24) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7) -+#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE6 16 -+#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6 0x00FF0000 -+#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE6(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6) -+#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE5 8 -+#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5 0x0000FF00 -+#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE5(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5) -+#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0 -+#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0x000000FF -+#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE4(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4) -+ -+#define HW_PXP_WFA_ARRAY_REG2 (0x00000e70) -+ -+#define BP_PXP_WFA_ARRAY_REG2_RSVD0 16 -+#define BM_PXP_WFA_ARRAY_REG2_RSVD0 0xFFFF0000 -+#define BF_PXP_WFA_ARRAY_REG2_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_WFA_ARRAY_REG2_RSVD0) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG15 0x00008000 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG15(v) \ -+ (((v) << 15) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG15) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG14 0x00004000 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG14(v) \ -+ (((v) << 14) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG14) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG13 0x00002000 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG13(v) \ -+ (((v) << 13) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG13) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG12 0x00001000 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG12(v) \ -+ (((v) << 12) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG12) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG11 0x00000800 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG11(v) \ -+ (((v) << 11) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG11) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG10 0x00000400 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG10(v) \ -+ (((v) << 10) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG10) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG9 0x00000200 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG9(v) \ -+ (((v) << 9) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG9) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG8 0x00000100 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG8(v) \ -+ (((v) << 8) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG8) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG7 0x00000080 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG7(v) \ -+ (((v) << 7) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG7) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG6 0x00000040 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG6(v) \ -+ (((v) << 6) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG6) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG5 0x00000020 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG5(v) \ -+ (((v) << 5) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG5) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG4 0x00000010 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG4(v) \ -+ (((v) << 4) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG4) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG3 0x00000008 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG3(v) \ -+ (((v) << 3) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG3) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG2 0x00000004 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG2(v) \ -+ (((v) << 2) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG2) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG1 0x00000002 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG1(v) \ -+ (((v) << 1) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG1) -+#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG0 0x00000001 -+#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG0(v) \ -+ (((v) << 0) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG0) -+ -+#define HW_PXP_WFE_A_STORE_CTRL_CH0 (0x00000e80) -+#define HW_PXP_WFE_A_STORE_CTRL_CH0_SET (0x00000e84) -+#define HW_PXP_WFE_A_STORE_CTRL_CH0_CLR (0x00000e88) -+#define HW_PXP_WFE_A_STORE_CTRL_CH0_TOG (0x00000e8c) -+ -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN 0x80000000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__1 0x1 -+#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 25 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 0x7E000000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD0(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0) -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 -+#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 18 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 0x00FC0000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1) -+#define BP_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 16 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 12 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 0x0000F000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD2(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2) -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3 0x00000080 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3) -+#define BP_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN 0x00000010 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16 0x00000004 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN 0x00000002 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN 0x00000001 -+#define BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__1 0x1 -+ -+#define HW_PXP_WFE_A_STORE_CTRL_CH1 (0x00000e90) -+#define HW_PXP_WFE_A_STORE_CTRL_CH1_SET (0x00000e94) -+#define HW_PXP_WFE_A_STORE_CTRL_CH1_CLR (0x00000e98) -+#define HW_PXP_WFE_A_STORE_CTRL_CH1_TOG (0x00000e9c) -+ -+#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 18 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 0xFFFC0000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD0(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0) -+#define BP_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 16 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 11 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 0x0000F800 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD1(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1) -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3 0x00000080 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3) -+#define BP_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN 0x00000010 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16 0x00000004 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN 0x00000002 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN 0x00000001 -+#define BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN) -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__1 0x1 -+ -+#define HW_PXP_WFE_A_STORE_STATUS_CH0 (0x00000ea0) -+ -+#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 16 -+#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y) -+#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0 -+#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X) -+ -+#define HW_PXP_WFE_A_STORE_STATUS_CH1 (0x00000eb0) -+ -+#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 16 -+#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y) -+#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0 -+#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X) -+ -+#define HW_PXP_WFE_A_STORE_SIZE_CH0 (0x00000ec0) -+ -+#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 16 -+#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT) -+#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0 -+#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH) -+ -+#define HW_PXP_WFE_A_STORE_SIZE_CH1 (0x00000ed0) -+ -+#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 16 -+#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT) -+#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0 -+#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH) -+ -+#define HW_PXP_WFE_A_STORE_PITCH (0x00000ee0) -+ -+#define BP_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 16 -+#define BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 -+#define BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH) -+#define BP_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0 -+#define BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF -+#define BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH) -+ -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0 (0x00000ef0) -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET (0x00000ef4) -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR (0x00000ef8) -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG (0x00000efc) -+ -+#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 8 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0) -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1) -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2) -+ -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1 (0x00000f00) -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET (0x00000f04) -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR (0x00000f08) -+#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG (0x00000f0c) -+ -+#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 6 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0) -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0 -+#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 -+#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2) -+ -+#define HW_PXP_WFE_A_STORE_ADDR_0_CH0 (0x00000f50) -+ -+#define BP_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 -+#define BM_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_ADDR_1_CH0 (0x00000f60) -+ -+#define BP_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 -+#define BM_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_FILL_DATA_CH0 (0x00000f70) -+ -+#define BP_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 -+#define BM_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_ADDR_0_CH1 (0x00000f80) -+ -+#define BP_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 -+#define BM_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_ADDR_1_CH1 (0x00000f90) -+ -+#define BP_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 -+#define BM_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK0_H_CH0 (0x00000fa0) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK0_L_CH0 (0x00000fb0) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK1_H_CH0 (0x00000fc0) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK1_L_CH0 (0x00000fd0) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK2_H_CH0 (0x00000fe0) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK2_L_CH0 (0x00000ff0) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK3_H_CH0 (0x00001000) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK3_L_CH0 (0x00001010) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK4_H_CH0 (0x00001020) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK4_L_CH0 (0x00001030) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK5_H_CH0 (0x00001040) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK5_L_CH0 (0x00001050) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK6_H_CH0 (0x00001060) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK6_L_CH0 (0x00001070) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK7_H_CH0 (0x00001080) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_MASK7_L_CH0 (0x00001090) -+ -+#define BP_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 -+#define BM_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0 (0x000010a0) -+ -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) -+ -+#define HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0 (0x000010b0) -+ -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3) -+#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 -+#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) -+ -+#define HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0 (0x000010c0) -+ -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) -+ -+#define HW_PXP_WFE_A_STORE_F_SHIFT_H_CH0 (0x000010d0) -+ -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3) -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) -+#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 -+#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) -+ -+#define HW_PXP_WFE_A_STORE_F_MASK_L_CH0 (0x000010e0) -+ -+#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 24 -+#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 -+#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3) -+#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 16 -+#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 -+#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2) -+#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 8 -+#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 -+#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1) -+#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0 -+#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF -+#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0) -+ -+#define HW_PXP_WFE_A_STORE_F_MASK_H_CH0 (0x000010f0) -+ -+#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 24 -+#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 -+#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7) -+#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 16 -+#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 -+#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6) -+#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 8 -+#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 -+#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5) -+#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0 -+#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF -+#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4) -+ -+#define HW_PXP_WFB_FETCH_CTRL (0x00001100) -+#define HW_PXP_WFB_FETCH_CTRL_SET (0x00001104) -+#define HW_PXP_WFB_FETCH_CTRL_CLR (0x00001108) -+#define HW_PXP_WFB_FETCH_CTRL_TOG (0x0000110c) -+ -+#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 -+#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ -+ (((v) << 31) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN) -+#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 -+#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ -+ (((v) << 30) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN) -+#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 -+#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(v) \ -+ (((v) << 29) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ) -+#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 -+#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(v) \ -+ (((v) << 28) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ) -+#define BP_PXP_WFB_FETCH_CTRL_RSVD0 24 -+#define BM_PXP_WFB_FETCH_CTRL_RSVD0 0x0F000000 -+#define BF_PXP_WFB_FETCH_CTRL_RSVD0(v) \ -+ (((v) << 24) & BM_PXP_WFB_FETCH_CTRL_RSVD0) -+#define BP_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 22 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(v) \ -+ (((v) << 22) & BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__1 0x1 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__2 0x2 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__3 0x3 -+#define BP_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 20 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 0x00300000 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(v) \ -+ (((v) << 20) & BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP) -+#define BP_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 18 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(v) \ -+ (((v) << 18) & BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__1 0x1 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__2 0x2 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__3 0x3 -+#define BP_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 16 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 0x00030000 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP) -+#define BP_PXP_WFB_FETCH_CTRL_RSVD1 14 -+#define BM_PXP_WFB_FETCH_CTRL_RSVD1 0x0000C000 -+#define BF_PXP_WFB_FETCH_CTRL_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFB_FETCH_CTRL_RSVD1) -+#define BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(v) \ -+ (((v) << 13) & BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN 0x00001000 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(v) \ -+ (((v) << 12) & BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(v) \ -+ (((v) << 11) & BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE 0x00000400 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(v) \ -+ (((v) << 10) & BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF 0x00000200 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(v) \ -+ (((v) << 9) & BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF2_EN 0x00000100 -+#define BF_PXP_WFB_FETCH_CTRL_BF2_EN(v) \ -+ (((v) << 8) & BM_PXP_WFB_FETCH_CTRL_BF2_EN) -+#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__1 0x1 -+#define BP_PXP_WFB_FETCH_CTRL_RSVD2 6 -+#define BM_PXP_WFB_FETCH_CTRL_RSVD2 0x000000C0 -+#define BF_PXP_WFB_FETCH_CTRL_RSVD2(v) \ -+ (((v) << 6) & BM_PXP_WFB_FETCH_CTRL_RSVD2) -+#define BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(v) \ -+ (((v) << 5) & BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN 0x00000010 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(v) \ -+ (((v) << 4) & BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(v) \ -+ (((v) << 3) & BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE 0x00000004 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(v) \ -+ (((v) << 2) & BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF 0x00000002 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(v) \ -+ (((v) << 1) & BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__1 0x1 -+#define BM_PXP_WFB_FETCH_CTRL_BF1_EN 0x00000001 -+#define BF_PXP_WFB_FETCH_CTRL_BF1_EN(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_CTRL_BF1_EN) -+#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__0 0x0 -+#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__1 0x1 -+ -+#define HW_PXP_WFB_FETCH_BUF1_ADDR (0x00001110) -+ -+#define BP_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0 -+#define BM_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) -+ -+#define HW_PXP_WFB_FETCH_BUF1_PITCH (0x00001120) -+ -+#define BP_PXP_WFB_FETCH_BUF1_PITCH_RSVD 16 -+#define BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_WFB_FETCH_BUF1_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD) -+#define BP_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0 -+#define BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_WFB_FETCH_BUF1_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH) -+ -+#define HW_PXP_WFB_FETCH_BUF1_SIZE (0x00001130) -+ -+#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 16 -+#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 0xFFFF0000 -+#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT) -+#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0 -+#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0x0000FFFF -+#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH) -+ -+#define HW_PXP_WFB_FETCH_BUF2_ADDR (0x00001140) -+ -+#define BP_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0 -+#define BM_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) -+ -+#define HW_PXP_WFB_FETCH_BUF2_PITCH (0x00001150) -+ -+#define BP_PXP_WFB_FETCH_BUF2_PITCH_RSVD 16 -+#define BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 -+#define BF_PXP_WFB_FETCH_BUF2_PITCH_RSVD(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD) -+#define BP_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0 -+#define BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0x0000FFFF -+#define BF_PXP_WFB_FETCH_BUF2_PITCH_PITCH(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH) -+ -+#define HW_PXP_WFB_FETCH_BUF2_SIZE (0x00001160) -+ -+#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 16 -+#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 0xFFFF0000 -+#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT) -+#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0 -+#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0x0000FFFF -+#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL0_MASK (0x00001170) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL1_MASK (0x00001180) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL2_MASK (0x00001190) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL3_MASK (0x000011a0) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL4_MASK (0x000011b0) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL5_MASK (0x000011c0) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL6_MASK (0x000011d0) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_PIXEL7_MASK (0x000011e0) -+ -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG0_MASK (0x000011f0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG1_MASK (0x00001200) -+ -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG2_MASK (0x00001210) -+ -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG3_MASK (0x00001220) -+ -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG4_MASK (0x00001230) -+ -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG5_MASK (0x00001240) -+ -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG6_MASK (0x00001250) -+ -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG7_MASK (0x00001260) -+ -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS) -+ -+#define HW_PXP_WFB_FETCH_BUF1_CORD (0x00001270) -+ -+#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD0 30 -+#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0 0xC0000000 -+#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0) -+#define BP_PXP_WFB_FETCH_BUF1_CORD_YCORD 16 -+#define BM_PXP_WFB_FETCH_BUF1_CORD_YCORD 0x3FFF0000 -+#define BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_CORD_YCORD) -+#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD1 14 -+#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1 0x0000C000 -+#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1) -+#define BP_PXP_WFB_FETCH_BUF1_CORD_XCORD 0 -+#define BM_PXP_WFB_FETCH_BUF1_CORD_XCORD 0x00003FFF -+#define BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_CORD_XCORD) -+ -+#define HW_PXP_WFB_FETCH_BUF2_CORD (0x00001280) -+ -+#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD0 30 -+#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0 0xC0000000 -+#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0) -+#define BP_PXP_WFB_FETCH_BUF2_CORD_YCORD 16 -+#define BM_PXP_WFB_FETCH_BUF2_CORD_YCORD 0x3FFF0000 -+#define BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(v) \ -+ (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_CORD_YCORD) -+#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD1 14 -+#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1 0x0000C000 -+#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1) -+#define BP_PXP_WFB_FETCH_BUF2_CORD_XCORD 0 -+#define BM_PXP_WFB_FETCH_BUF2_CORD_XCORD 0x00003FFF -+#define BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(v) \ -+ (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_CORD_XCORD) -+ -+#define HW_PXP_WFB_ARRAY_FLAG8_MASK (0x00001290) -+ -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG9_MASK (0x000012a0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG10_MASK (0x000012b0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG11_MASK (0x000012c0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG12_MASK (0x000012d0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG13_MASK (0x000012e0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG14_MASK (0x000012f0) -+ -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_FLAG15_MASK (0x00001300) -+ -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 30 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 28 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL) -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 26 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1(v) \ -+ (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1) -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(v) \ -+ (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y) -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X) -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 -+#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 22 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 20 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ -+ (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 18 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3(v) \ -+ (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 16 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 13 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 8 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 5 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5) -+#define BP_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0 -+#define BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0x0000001F -+#define BF_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS) -+ -+#define HW_PXP_WFB_ARRAY_REG0 (0x00001310) -+ -+#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE3 24 -+#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3 0xFF000000 -+#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE3(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3) -+#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE2 16 -+#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2 0x00FF0000 -+#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE2(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2) -+#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE1 8 -+#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1 0x0000FF00 -+#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE1(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1) -+#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0 -+#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0x000000FF -+#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE0(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0) -+ -+#define HW_PXP_WFB_ARRAY_REG1 (0x00001320) -+ -+#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE7 24 -+#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7 0xFF000000 -+#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE7(v) \ -+ (((v) << 24) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7) -+#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE6 16 -+#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6 0x00FF0000 -+#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE6(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6) -+#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE5 8 -+#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5 0x0000FF00 -+#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE5(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5) -+#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0 -+#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0x000000FF -+#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE4(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4) -+ -+#define HW_PXP_WFB_ARRAY_REG2 (0x00001330) -+ -+#define BP_PXP_WFB_ARRAY_REG2_RSVD0 16 -+#define BM_PXP_WFB_ARRAY_REG2_RSVD0 0xFFFF0000 -+#define BF_PXP_WFB_ARRAY_REG2_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_WFB_ARRAY_REG2_RSVD0) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG15 0x00008000 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG15(v) \ -+ (((v) << 15) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG15) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG14 0x00004000 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG14(v) \ -+ (((v) << 14) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG14) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG13 0x00002000 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG13(v) \ -+ (((v) << 13) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG13) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG12 0x00001000 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG12(v) \ -+ (((v) << 12) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG12) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG11 0x00000800 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG11(v) \ -+ (((v) << 11) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG11) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG10 0x00000400 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG10(v) \ -+ (((v) << 10) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG10) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG9 0x00000200 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG9(v) \ -+ (((v) << 9) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG9) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG8 0x00000100 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG8(v) \ -+ (((v) << 8) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG8) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG7 0x00000080 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG7(v) \ -+ (((v) << 7) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG7) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG6 0x00000040 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG6(v) \ -+ (((v) << 6) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG6) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG5 0x00000020 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG5(v) \ -+ (((v) << 5) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG5) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG4 0x00000010 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG4(v) \ -+ (((v) << 4) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG4) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG3 0x00000008 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG3(v) \ -+ (((v) << 3) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG3) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG2 0x00000004 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG2(v) \ -+ (((v) << 2) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG2) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG1 0x00000002 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG1(v) \ -+ (((v) << 1) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG1) -+#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG0 0x00000001 -+#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG0(v) \ -+ (((v) << 0) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG0) -+ -+#define HW_PXP_WFE_B_STORE_CTRL_CH0 (0x00001340) -+#define HW_PXP_WFE_B_STORE_CTRL_CH0_SET (0x00001344) -+#define HW_PXP_WFE_B_STORE_CTRL_CH0_CLR (0x00001348) -+#define HW_PXP_WFE_B_STORE_CTRL_CH0_TOG (0x0000134c) -+ -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN 0x80000000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__1 0x1 -+#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 25 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 0x7E000000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD0(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0) -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 -+#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 18 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 0x00FC0000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD1(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1) -+#define BP_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 16 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 12 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 0x0000F000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD2(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2) -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3 0x00000080 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3) -+#define BP_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN 0x00000010 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16 0x00000004 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN 0x00000002 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN 0x00000001 -+#define BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__1 0x1 -+ -+#define HW_PXP_WFE_B_STORE_CTRL_CH1 (0x00001350) -+#define HW_PXP_WFE_B_STORE_CTRL_CH1_SET (0x00001354) -+#define HW_PXP_WFE_B_STORE_CTRL_CH1_CLR (0x00001358) -+#define HW_PXP_WFE_B_STORE_CTRL_CH1_TOG (0x0000135c) -+ -+#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 18 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 0xFFFC0000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD0(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0) -+#define BP_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 16 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 -+#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 11 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 0x0000F800 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD1(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1) -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3 0x00000080 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3) -+#define BP_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN 0x00000010 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16 0x00000004 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN 0x00000002 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN 0x00000001 -+#define BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN) -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__1 0x1 -+ -+#define HW_PXP_WFE_B_STORE_STATUS_CH0 (0x00001360) -+ -+#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 16 -+#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y) -+#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0 -+#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X) -+ -+#define HW_PXP_WFE_B_STORE_STATUS_CH1 (0x00001370) -+ -+#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 16 -+#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 -+#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y) -+#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0 -+#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF -+#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X) -+ -+#define HW_PXP_WFE_B_STORE_SIZE_CH0 (0x00001380) -+ -+#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 16 -+#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT) -+#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0 -+#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH) -+ -+#define HW_PXP_WFE_B_STORE_SIZE_CH1 (0x00001390) -+ -+#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 16 -+#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 -+#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT) -+#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0 -+#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF -+#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH) -+ -+#define HW_PXP_WFE_B_STORE_PITCH (0x000013a0) -+ -+#define BP_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 16 -+#define BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 -+#define BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH) -+#define BP_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0 -+#define BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF -+#define BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH) -+ -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0 (0x000013b0) -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET (0x000013b4) -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR (0x000013b8) -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG (0x000013bc) -+ -+#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 8 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0) -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1) -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2) -+ -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1 (0x000013c0) -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET (0x000013c4) -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR (0x000013c8) -+#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG (0x000013cc) -+ -+#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 6 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0) -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 -+#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 -+#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 -+#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0 -+#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 -+#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2) -+ -+#define HW_PXP_WFE_B_STORE_ADDR_0_CH0 (0x00001410) -+ -+#define BP_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 -+#define BM_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_ADDR_1_CH0 (0x00001420) -+ -+#define BP_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 -+#define BM_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_FILL_DATA_CH0 (0x00001430) -+ -+#define BP_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 -+#define BM_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_ADDR_0_CH1 (0x00001440) -+ -+#define BP_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 -+#define BM_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_ADDR_1_CH1 (0x00001450) -+ -+#define BP_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 -+#define BM_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK0_H_CH0 (0x00001460) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK0_L_CH0 (0x00001470) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK1_H_CH0 (0x00001480) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK1_L_CH0 (0x00001490) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK2_H_CH0 (0x000014a0) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK2_L_CH0 (0x000014b0) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK3_H_CH0 (0x000014c0) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK3_L_CH0 (0x000014d0) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK4_H_CH0 (0x000014e0) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK4_L_CH0 (0x000014f0) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK5_H_CH0 (0x00001500) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK5_L_CH0 (0x00001510) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK6_H_CH0 (0x00001520) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK6_L_CH0 (0x00001530) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK7_H_CH0 (0x00001540) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_MASK7_L_CH0 (0x00001550) -+ -+#define BP_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 -+#define BM_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF -+#define BF_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) -+ -+#define HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0 (0x00001560) -+ -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) -+ -+#define HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0 (0x00001570) -+ -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3) -+#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 -+#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) -+ -+#define HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0 (0x00001580) -+ -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F -+#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) -+ -+#define HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0 (0x00001590) -+ -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3) -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) -+#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 -+#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F -+#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) -+ -+#define HW_PXP_WFE_B_STORE_F_MASK_L_CH0 (0x000015a0) -+ -+#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 24 -+#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 -+#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3) -+#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 16 -+#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 -+#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2) -+#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 8 -+#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 -+#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1) -+#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0 -+#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF -+#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0) -+ -+#define HW_PXP_WFE_B_STORE_F_MASK_H_CH0 (0x000015b0) -+ -+#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 24 -+#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 -+#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7) -+#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 16 -+#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 -+#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6) -+#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 8 -+#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 -+#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5) -+#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0 -+#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF -+#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4) -+ -+#define HW_PXP_FETCH_WFE_A_DEBUG (0x000015c0) -+ -+#define BP_PXP_FETCH_WFE_A_DEBUG_RSVD 29 -+#define BM_PXP_FETCH_WFE_A_DEBUG_RSVD 0xE0000000 -+#define BF_PXP_FETCH_WFE_A_DEBUG_RSVD(v) \ -+ (((v) << 29) & BM_PXP_FETCH_WFE_A_DEBUG_RSVD) -+#define BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL 0x10000000 -+#define BF_PXP_FETCH_WFE_A_DEBUG_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL) -+#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF0 0x0 -+#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF1 0x1 -+#define BP_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 24 -+#define BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 0x0F000000 -+#define BF_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL(v) \ -+ (((v) << 24) & BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL) -+#define BP_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0 -+#define BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0x00FFFFFF -+#define BF_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE(v) \ -+ (((v) << 0) & BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE) -+ -+#define HW_PXP_FETCH_WFE_B_DEBUG (0x000015d0) -+ -+#define BP_PXP_FETCH_WFE_B_DEBUG_RSVD 29 -+#define BM_PXP_FETCH_WFE_B_DEBUG_RSVD 0xE0000000 -+#define BF_PXP_FETCH_WFE_B_DEBUG_RSVD(v) \ -+ (((v) << 29) & BM_PXP_FETCH_WFE_B_DEBUG_RSVD) -+#define BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL 0x10000000 -+#define BF_PXP_FETCH_WFE_B_DEBUG_BUF_SEL(v) \ -+ (((v) << 28) & BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL) -+#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF0 0x0 -+#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF1 0x1 -+#define BP_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 24 -+#define BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 0x0F000000 -+#define BF_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(v) \ -+ (((v) << 24) & BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL) -+#define BP_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0 -+#define BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0x00FFFFFF -+#define BF_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(v) \ -+ (((v) << 0) & BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE) -+ -+#define HW_PXP_DITHER_CTRL (0x00001670) -+#define HW_PXP_DITHER_CTRL_SET (0x00001674) -+#define HW_PXP_DITHER_CTRL_CLR (0x00001678) -+#define HW_PXP_DITHER_CTRL_TOG (0x0000167c) -+ -+#define BM_PXP_DITHER_CTRL_BUSY0 0x80000000 -+#define BF_PXP_DITHER_CTRL_BUSY0(v) \ -+ (((v) << 31) & BM_PXP_DITHER_CTRL_BUSY0) -+#define BM_PXP_DITHER_CTRL_BUSY1 0x40000000 -+#define BF_PXP_DITHER_CTRL_BUSY1(v) \ -+ (((v) << 30) & BM_PXP_DITHER_CTRL_BUSY1) -+#define BM_PXP_DITHER_CTRL_BUSY2 0x20000000 -+#define BF_PXP_DITHER_CTRL_BUSY2(v) \ -+ (((v) << 29) & BM_PXP_DITHER_CTRL_BUSY2) -+#define BP_PXP_DITHER_CTRL_RSVD0 25 -+#define BM_PXP_DITHER_CTRL_RSVD0 0x1E000000 -+#define BF_PXP_DITHER_CTRL_RSVD0(v) \ -+ (((v) << 25) & BM_PXP_DITHER_CTRL_RSVD0) -+#define BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE 0x01000000 -+#define BF_PXP_DITHER_CTRL_ORDERED_ROUND_MODE(v) \ -+ (((v) << 24) & BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE) -+#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__0 0x0 -+#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__1 0x1 -+#define BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE 0x00800000 -+#define BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(v) \ -+ (((v) << 23) & BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE) -+#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Disabled 0x0 -+#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Enabled 0x1 -+#define BP_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 21 -+#define BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 0x00600000 -+#define BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(v) \ -+ (((v) << 21) & BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE) -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__0 0x0 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__1 0x1 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__2 0x2 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__3 0x3 -+#define BP_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 19 -+#define BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 0x00180000 -+#define BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(v) \ -+ (((v) << 19) & BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE) -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__0 0x0 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__1 0x1 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__2 0x2 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__3 0x3 -+#define BP_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 17 -+#define BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 0x00060000 -+#define BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(v) \ -+ (((v) << 17) & BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE) -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__0 0x0 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__1 0x1 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__2 0x2 -+#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__3 0x3 -+#define BP_PXP_DITHER_CTRL_LUT_MODE 15 -+#define BM_PXP_DITHER_CTRL_LUT_MODE 0x00018000 -+#define BF_PXP_DITHER_CTRL_LUT_MODE(v) \ -+ (((v) << 15) & BM_PXP_DITHER_CTRL_LUT_MODE) -+#define BV_PXP_DITHER_CTRL_LUT_MODE__0 0x0 -+#define BV_PXP_DITHER_CTRL_LUT_MODE__1 0x1 -+#define BV_PXP_DITHER_CTRL_LUT_MODE__2 0x2 -+#define BV_PXP_DITHER_CTRL_LUT_MODE__3 0x3 -+#define BP_PXP_DITHER_CTRL_NUM_QUANT_BIT 12 -+#define BM_PXP_DITHER_CTRL_NUM_QUANT_BIT 0x00007000 -+#define BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(v) \ -+ (((v) << 12) & BM_PXP_DITHER_CTRL_NUM_QUANT_BIT) -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__0 0x0 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__1 0x1 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__2 0x2 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__3 0x3 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__4 0x4 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__5 0x5 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__6 0x6 -+#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__7 0x7 -+#define BP_PXP_DITHER_CTRL_DITHER_MODE2 9 -+#define BM_PXP_DITHER_CTRL_DITHER_MODE2 0x00000E00 -+#define BF_PXP_DITHER_CTRL_DITHER_MODE2(v) \ -+ (((v) << 9) & BM_PXP_DITHER_CTRL_DITHER_MODE2) -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__0 0x0 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__1 0x1 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__2 0x2 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__3 0x3 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__4 0x4 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__5 0x5 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__6 0x6 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE2__7 0x7 -+#define BP_PXP_DITHER_CTRL_DITHER_MODE1 6 -+#define BM_PXP_DITHER_CTRL_DITHER_MODE1 0x000001C0 -+#define BF_PXP_DITHER_CTRL_DITHER_MODE1(v) \ -+ (((v) << 6) & BM_PXP_DITHER_CTRL_DITHER_MODE1) -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__0 0x0 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__1 0x1 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__2 0x2 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__3 0x3 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__4 0x4 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__5 0x5 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__6 0x6 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE1__7 0x7 -+#define BP_PXP_DITHER_CTRL_DITHER_MODE0 3 -+#define BM_PXP_DITHER_CTRL_DITHER_MODE0 0x00000038 -+#define BF_PXP_DITHER_CTRL_DITHER_MODE0(v) \ -+ (((v) << 3) & BM_PXP_DITHER_CTRL_DITHER_MODE0) -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__0 0x0 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__1 0x1 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__2 0x2 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__3 0x3 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__4 0x4 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__5 0x5 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__6 0x6 -+#define BV_PXP_DITHER_CTRL_DITHER_MODE0__7 0x7 -+#define BM_PXP_DITHER_CTRL_ENABLE2 0x00000004 -+#define BF_PXP_DITHER_CTRL_ENABLE2(v) \ -+ (((v) << 2) & BM_PXP_DITHER_CTRL_ENABLE2) -+#define BV_PXP_DITHER_CTRL_ENABLE2__Disabled 0x0 -+#define BV_PXP_DITHER_CTRL_ENABLE2__Enabled 0x1 -+#define BM_PXP_DITHER_CTRL_ENABLE1 0x00000002 -+#define BF_PXP_DITHER_CTRL_ENABLE1(v) \ -+ (((v) << 1) & BM_PXP_DITHER_CTRL_ENABLE1) -+#define BV_PXP_DITHER_CTRL_ENABLE1__Disabled 0x0 -+#define BV_PXP_DITHER_CTRL_ENABLE1__Enabled 0x1 -+#define BM_PXP_DITHER_CTRL_ENABLE0 0x00000001 -+#define BF_PXP_DITHER_CTRL_ENABLE0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_CTRL_ENABLE0) -+#define BV_PXP_DITHER_CTRL_ENABLE0__Disabled 0x0 -+#define BV_PXP_DITHER_CTRL_ENABLE0__Enabled 0x1 -+ -+#define HW_PXP_DITHER_FINAL_LUT_DATA0 (0x00001680) -+#define HW_PXP_DITHER_FINAL_LUT_DATA0_SET (0x00001684) -+#define HW_PXP_DITHER_FINAL_LUT_DATA0_CLR (0x00001688) -+#define HW_PXP_DITHER_FINAL_LUT_DATA0_TOG (0x0000168c) -+ -+#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA3 24 -+#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3 0xFF000000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3) -+#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA2 16 -+#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2 0x00FF0000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2) -+#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA1 8 -+#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1 0x0000FF00 -+#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1) -+#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0 -+#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0x000000FF -+#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0) -+ -+#define HW_PXP_DITHER_FINAL_LUT_DATA1 (0x00001690) -+#define HW_PXP_DITHER_FINAL_LUT_DATA1_SET (0x00001694) -+#define HW_PXP_DITHER_FINAL_LUT_DATA1_CLR (0x00001698) -+#define HW_PXP_DITHER_FINAL_LUT_DATA1_TOG (0x0000169c) -+ -+#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA7 24 -+#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7 0xFF000000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7) -+#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA6 16 -+#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6 0x00FF0000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6) -+#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA5 8 -+#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5 0x0000FF00 -+#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5) -+#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0 -+#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0x000000FF -+#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4) -+ -+#define HW_PXP_DITHER_FINAL_LUT_DATA2 (0x000016a0) -+#define HW_PXP_DITHER_FINAL_LUT_DATA2_SET (0x000016a4) -+#define HW_PXP_DITHER_FINAL_LUT_DATA2_CLR (0x000016a8) -+#define HW_PXP_DITHER_FINAL_LUT_DATA2_TOG (0x000016ac) -+ -+#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA11 24 -+#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11 0xFF000000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11) -+#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA10 16 -+#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10 0x00FF0000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10) -+#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA9 8 -+#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9 0x0000FF00 -+#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9) -+#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0 -+#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0x000000FF -+#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8) -+ -+#define HW_PXP_DITHER_FINAL_LUT_DATA3 (0x000016b0) -+#define HW_PXP_DITHER_FINAL_LUT_DATA3_SET (0x000016b4) -+#define HW_PXP_DITHER_FINAL_LUT_DATA3_CLR (0x000016b8) -+#define HW_PXP_DITHER_FINAL_LUT_DATA3_TOG (0x000016bc) -+ -+#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA15 24 -+#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15 0xFF000000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(v) \ -+ (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15) -+#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA14 16 -+#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14 0x00FF0000 -+#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(v) \ -+ (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14) -+#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA13 8 -+#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13 0x0000FF00 -+#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(v) \ -+ (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13) -+#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0 -+#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0x000000FF -+#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(v) \ -+ (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12) -+ -+#define HW_PXP_WFE_A_CTRL (0x000016c0) -+#define HW_PXP_WFE_A_CTRL_SET (0x000016c4) -+#define HW_PXP_WFE_A_CTRL_CLR (0x000016c8) -+#define HW_PXP_WFE_A_CTRL_TOG (0x000016cc) -+ -+#define BM_PXP_WFE_A_CTRL_DONE 0x80000000 -+#define BF_PXP_WFE_A_CTRL_DONE(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_CTRL_DONE) -+#define BP_PXP_WFE_A_CTRL_RSVD0 3 -+#define BM_PXP_WFE_A_CTRL_RSVD0 0x7FFFFFF8 -+#define BF_PXP_WFE_A_CTRL_RSVD0(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_CTRL_RSVD0) -+#define BM_PXP_WFE_A_CTRL_SW_RESET 0x00000004 -+#define BF_PXP_WFE_A_CTRL_SW_RESET(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_CTRL_SW_RESET) -+#define BM_PXP_WFE_A_CTRL_RSVD1 0x00000002 -+#define BF_PXP_WFE_A_CTRL_RSVD1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_CTRL_RSVD1) -+#define BM_PXP_WFE_A_CTRL_ENABLE 0x00000001 -+#define BF_PXP_WFE_A_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_CTRL_ENABLE) -+#define BV_PXP_WFE_A_CTRL_ENABLE__0 0x0 -+#define BV_PXP_WFE_A_CTRL_ENABLE__1 0x1 -+ -+#define HW_PXP_WFE_A_DIMENSIONS (0x000016d0) -+ -+#define BP_PXP_WFE_A_DIMENSIONS_RSVD0 28 -+#define BM_PXP_WFE_A_DIMENSIONS_RSVD0 0xF0000000 -+#define BF_PXP_WFE_A_DIMENSIONS_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_DIMENSIONS_RSVD0) -+#define BP_PXP_WFE_A_DIMENSIONS_HEIGHT 16 -+#define BM_PXP_WFE_A_DIMENSIONS_HEIGHT 0x0FFF0000 -+#define BF_PXP_WFE_A_DIMENSIONS_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_DIMENSIONS_HEIGHT) -+#define BP_PXP_WFE_A_DIMENSIONS_RSVD1 12 -+#define BM_PXP_WFE_A_DIMENSIONS_RSVD1 0x0000F000 -+#define BF_PXP_WFE_A_DIMENSIONS_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_DIMENSIONS_RSVD1) -+#define BP_PXP_WFE_A_DIMENSIONS_WIDTH 0 -+#define BM_PXP_WFE_A_DIMENSIONS_WIDTH 0x00000FFF -+#define BF_PXP_WFE_A_DIMENSIONS_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_DIMENSIONS_WIDTH) -+ -+#define HW_PXP_WFE_A_OFFSET (0x000016e0) -+ -+#define BP_PXP_WFE_A_OFFSET_RSVD0 28 -+#define BM_PXP_WFE_A_OFFSET_RSVD0 0xF0000000 -+#define BF_PXP_WFE_A_OFFSET_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_OFFSET_RSVD0) -+#define BP_PXP_WFE_A_OFFSET_Y_OFFSET 16 -+#define BM_PXP_WFE_A_OFFSET_Y_OFFSET 0x0FFF0000 -+#define BF_PXP_WFE_A_OFFSET_Y_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_OFFSET_Y_OFFSET) -+#define BP_PXP_WFE_A_OFFSET_RSVD1 12 -+#define BM_PXP_WFE_A_OFFSET_RSVD1 0x0000F000 -+#define BF_PXP_WFE_A_OFFSET_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_OFFSET_RSVD1) -+#define BP_PXP_WFE_A_OFFSET_X_OFFSET 0 -+#define BM_PXP_WFE_A_OFFSET_X_OFFSET 0x00000FFF -+#define BF_PXP_WFE_A_OFFSET_X_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_OFFSET_X_OFFSET) -+ -+#define HW_PXP_WFE_A_SW_DATA_REGS (0x000016f0) -+ -+#define BP_PXP_WFE_A_SW_DATA_REGS_VAL3 24 -+#define BM_PXP_WFE_A_SW_DATA_REGS_VAL3 0xFF000000 -+#define BF_PXP_WFE_A_SW_DATA_REGS_VAL3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_SW_DATA_REGS_VAL3) -+#define BP_PXP_WFE_A_SW_DATA_REGS_VAL2 16 -+#define BM_PXP_WFE_A_SW_DATA_REGS_VAL2 0x00FF0000 -+#define BF_PXP_WFE_A_SW_DATA_REGS_VAL2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_SW_DATA_REGS_VAL2) -+#define BP_PXP_WFE_A_SW_DATA_REGS_VAL1 8 -+#define BM_PXP_WFE_A_SW_DATA_REGS_VAL1 0x0000FF00 -+#define BF_PXP_WFE_A_SW_DATA_REGS_VAL1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_SW_DATA_REGS_VAL1) -+#define BP_PXP_WFE_A_SW_DATA_REGS_VAL0 0 -+#define BM_PXP_WFE_A_SW_DATA_REGS_VAL0 0x000000FF -+#define BF_PXP_WFE_A_SW_DATA_REGS_VAL0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_SW_DATA_REGS_VAL0) -+ -+#define HW_PXP_WFE_A_SW_FLAG_REGS (0x00001700) -+ -+#define BP_PXP_WFE_A_SW_FLAG_REGS_RSVD 4 -+#define BM_PXP_WFE_A_SW_FLAG_REGS_RSVD 0xFFFFFFF0 -+#define BF_PXP_WFE_A_SW_FLAG_REGS_RSVD(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_SW_FLAG_REGS_RSVD) -+#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL3 0x00000008 -+#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL3) -+#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL2 0x00000004 -+#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL2) -+#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL1 0x00000002 -+#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL1) -+#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL0 0x00000001 -+#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL0) -+ -+#define HW_PXP_WFE_A_STAGE1_MUX0 (0x00001710) -+#define HW_PXP_WFE_A_STAGE1_MUX0_SET (0x00001714) -+#define HW_PXP_WFE_A_STAGE1_MUX0_CLR (0x00001718) -+#define HW_PXP_WFE_A_STAGE1_MUX0_TOG (0x0000171c) -+ -+#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD0) -+#define BP_PXP_WFE_A_STAGE1_MUX0_MUX3 24 -+#define BM_PXP_WFE_A_STAGE1_MUX0_MUX3 0x3F000000 -+#define BF_PXP_WFE_A_STAGE1_MUX0_MUX3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX0_MUX3) -+#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD1) -+#define BP_PXP_WFE_A_STAGE1_MUX0_MUX2 16 -+#define BM_PXP_WFE_A_STAGE1_MUX0_MUX2 0x003F0000 -+#define BF_PXP_WFE_A_STAGE1_MUX0_MUX2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX0_MUX2) -+#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD2) -+#define BP_PXP_WFE_A_STAGE1_MUX0_MUX1 8 -+#define BM_PXP_WFE_A_STAGE1_MUX0_MUX1 0x00003F00 -+#define BF_PXP_WFE_A_STAGE1_MUX0_MUX1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX0_MUX1) -+#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD3) -+#define BP_PXP_WFE_A_STAGE1_MUX0_MUX0 0 -+#define BM_PXP_WFE_A_STAGE1_MUX0_MUX0 0x0000003F -+#define BF_PXP_WFE_A_STAGE1_MUX0_MUX0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX0_MUX0) -+ -+#define HW_PXP_WFE_A_STAGE1_MUX1 (0x00001720) -+#define HW_PXP_WFE_A_STAGE1_MUX1_SET (0x00001724) -+#define HW_PXP_WFE_A_STAGE1_MUX1_CLR (0x00001728) -+#define HW_PXP_WFE_A_STAGE1_MUX1_TOG (0x0000172c) -+ -+#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD0) -+#define BP_PXP_WFE_A_STAGE1_MUX1_MUX7 24 -+#define BM_PXP_WFE_A_STAGE1_MUX1_MUX7 0x3F000000 -+#define BF_PXP_WFE_A_STAGE1_MUX1_MUX7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX1_MUX7) -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__INC 0x0 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__DEC 0x1 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__ADD 0x2 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__MINUS 0x3 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__AND 0x4 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__OR 0x5 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__XOR 0x6 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTLEFT 0x7 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTRIGHT 0x8 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_AND 0x9 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_OR 0xa -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_CMP 0xb -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__NOP 0xc -+#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD1) -+#define BP_PXP_WFE_A_STAGE1_MUX1_MUX6 16 -+#define BM_PXP_WFE_A_STAGE1_MUX1_MUX6 0x003F0000 -+#define BF_PXP_WFE_A_STAGE1_MUX1_MUX6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX1_MUX6) -+#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD2) -+#define BP_PXP_WFE_A_STAGE1_MUX1_MUX5 8 -+#define BM_PXP_WFE_A_STAGE1_MUX1_MUX5 0x00003F00 -+#define BF_PXP_WFE_A_STAGE1_MUX1_MUX5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX1_MUX5) -+#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD3) -+#define BP_PXP_WFE_A_STAGE1_MUX1_MUX4 0 -+#define BM_PXP_WFE_A_STAGE1_MUX1_MUX4 0x0000003F -+#define BF_PXP_WFE_A_STAGE1_MUX1_MUX4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX1_MUX4) -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__INC 0x0 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__DEC 0x1 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__ADD 0x2 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__MINUS 0x3 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__AND 0x4 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__OR 0x5 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__XOR 0x6 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTLEFT 0x7 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTRIGHT 0x8 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_AND 0x9 -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_OR 0xa -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_CMP 0xb -+#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__NOP 0xc -+ -+#define HW_PXP_WFE_A_STAGE1_MUX2 (0x00001730) -+#define HW_PXP_WFE_A_STAGE1_MUX2_SET (0x00001734) -+#define HW_PXP_WFE_A_STAGE1_MUX2_CLR (0x00001738) -+#define HW_PXP_WFE_A_STAGE1_MUX2_TOG (0x0000173c) -+ -+#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD0) -+#define BP_PXP_WFE_A_STAGE1_MUX2_MUX11 24 -+#define BM_PXP_WFE_A_STAGE1_MUX2_MUX11 0x3F000000 -+#define BF_PXP_WFE_A_STAGE1_MUX2_MUX11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX2_MUX11) -+#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD1) -+#define BP_PXP_WFE_A_STAGE1_MUX2_MUX10 16 -+#define BM_PXP_WFE_A_STAGE1_MUX2_MUX10 0x003F0000 -+#define BF_PXP_WFE_A_STAGE1_MUX2_MUX10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX2_MUX10) -+#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD2) -+#define BP_PXP_WFE_A_STAGE1_MUX2_MUX9 8 -+#define BM_PXP_WFE_A_STAGE1_MUX2_MUX9 0x00003F00 -+#define BF_PXP_WFE_A_STAGE1_MUX2_MUX9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX2_MUX9) -+#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD3) -+#define BP_PXP_WFE_A_STAGE1_MUX2_MUX8 0 -+#define BM_PXP_WFE_A_STAGE1_MUX2_MUX8 0x0000003F -+#define BF_PXP_WFE_A_STAGE1_MUX2_MUX8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX2_MUX8) -+ -+#define HW_PXP_WFE_A_STAGE1_MUX3 (0x00001740) -+#define HW_PXP_WFE_A_STAGE1_MUX3_SET (0x00001744) -+#define HW_PXP_WFE_A_STAGE1_MUX3_CLR (0x00001748) -+#define HW_PXP_WFE_A_STAGE1_MUX3_TOG (0x0000174c) -+ -+#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD0) -+#define BP_PXP_WFE_A_STAGE1_MUX3_MUX15 24 -+#define BM_PXP_WFE_A_STAGE1_MUX3_MUX15 0x3F000000 -+#define BF_PXP_WFE_A_STAGE1_MUX3_MUX15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX3_MUX15) -+#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD1) -+#define BP_PXP_WFE_A_STAGE1_MUX3_MUX14 16 -+#define BM_PXP_WFE_A_STAGE1_MUX3_MUX14 0x003F0000 -+#define BF_PXP_WFE_A_STAGE1_MUX3_MUX14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX3_MUX14) -+#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD2) -+#define BP_PXP_WFE_A_STAGE1_MUX3_MUX13 8 -+#define BM_PXP_WFE_A_STAGE1_MUX3_MUX13 0x00003F00 -+#define BF_PXP_WFE_A_STAGE1_MUX3_MUX13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX3_MUX13) -+#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD3) -+#define BP_PXP_WFE_A_STAGE1_MUX3_MUX12 0 -+#define BM_PXP_WFE_A_STAGE1_MUX3_MUX12 0x0000003F -+#define BF_PXP_WFE_A_STAGE1_MUX3_MUX12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX3_MUX12) -+ -+#define HW_PXP_WFE_A_STAGE1_MUX4 (0x00001750) -+#define HW_PXP_WFE_A_STAGE1_MUX4_SET (0x00001754) -+#define HW_PXP_WFE_A_STAGE1_MUX4_CLR (0x00001758) -+#define HW_PXP_WFE_A_STAGE1_MUX4_TOG (0x0000175c) -+ -+#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD0 24 -+#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD0 0xFF000000 -+#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD0(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD0) -+#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD1 16 -+#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD1 0x00FF0000 -+#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD1(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD1) -+#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD2) -+#define BP_PXP_WFE_A_STAGE1_MUX4_MUX17 8 -+#define BM_PXP_WFE_A_STAGE1_MUX4_MUX17 0x00003F00 -+#define BF_PXP_WFE_A_STAGE1_MUX4_MUX17(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX4_MUX17) -+#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD3) -+#define BP_PXP_WFE_A_STAGE1_MUX4_MUX16 0 -+#define BM_PXP_WFE_A_STAGE1_MUX4_MUX16 0x0000003F -+#define BF_PXP_WFE_A_STAGE1_MUX4_MUX16(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX4_MUX16) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX0 (0x00001760) -+#define HW_PXP_WFE_A_STAGE2_MUX0_SET (0x00001764) -+#define HW_PXP_WFE_A_STAGE2_MUX0_CLR (0x00001768) -+#define HW_PXP_WFE_A_STAGE2_MUX0_TOG (0x0000176c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX0_MUX3 24 -+#define BM_PXP_WFE_A_STAGE2_MUX0_MUX3 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX0_MUX3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX0_MUX3) -+#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX0_MUX2 16 -+#define BM_PXP_WFE_A_STAGE2_MUX0_MUX2 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX0_MUX2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX0_MUX2) -+#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX0_MUX1 8 -+#define BM_PXP_WFE_A_STAGE2_MUX0_MUX1 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX0_MUX1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX0_MUX1) -+#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX0_MUX0 0 -+#define BM_PXP_WFE_A_STAGE2_MUX0_MUX0 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX0_MUX0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX0_MUX0) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX1 (0x00001770) -+#define HW_PXP_WFE_A_STAGE2_MUX1_SET (0x00001774) -+#define HW_PXP_WFE_A_STAGE2_MUX1_CLR (0x00001778) -+#define HW_PXP_WFE_A_STAGE2_MUX1_TOG (0x0000177c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX1_MUX7 24 -+#define BM_PXP_WFE_A_STAGE2_MUX1_MUX7 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX1_MUX7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX1_MUX7) -+#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX1_MUX6 16 -+#define BM_PXP_WFE_A_STAGE2_MUX1_MUX6 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX1_MUX6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX1_MUX6) -+#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX1_MUX5 8 -+#define BM_PXP_WFE_A_STAGE2_MUX1_MUX5 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX1_MUX5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX1_MUX5) -+#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX1_MUX4 0 -+#define BM_PXP_WFE_A_STAGE2_MUX1_MUX4 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX1_MUX4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX1_MUX4) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX2 (0x00001780) -+#define HW_PXP_WFE_A_STAGE2_MUX2_SET (0x00001784) -+#define HW_PXP_WFE_A_STAGE2_MUX2_CLR (0x00001788) -+#define HW_PXP_WFE_A_STAGE2_MUX2_TOG (0x0000178c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX2_MUX11 24 -+#define BM_PXP_WFE_A_STAGE2_MUX2_MUX11 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX2_MUX11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX2_MUX11) -+#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX2_MUX10 16 -+#define BM_PXP_WFE_A_STAGE2_MUX2_MUX10 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX2_MUX10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX2_MUX10) -+#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX2_MUX9 8 -+#define BM_PXP_WFE_A_STAGE2_MUX2_MUX9 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX2_MUX9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX2_MUX9) -+#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX2_MUX8 0 -+#define BM_PXP_WFE_A_STAGE2_MUX2_MUX8 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX2_MUX8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX2_MUX8) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX3 (0x00001790) -+#define HW_PXP_WFE_A_STAGE2_MUX3_SET (0x00001794) -+#define HW_PXP_WFE_A_STAGE2_MUX3_CLR (0x00001798) -+#define HW_PXP_WFE_A_STAGE2_MUX3_TOG (0x0000179c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX3_MUX15 24 -+#define BM_PXP_WFE_A_STAGE2_MUX3_MUX15 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX3_MUX15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX3_MUX15) -+#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX3_MUX14 16 -+#define BM_PXP_WFE_A_STAGE2_MUX3_MUX14 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX3_MUX14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX3_MUX14) -+#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX3_MUX13 8 -+#define BM_PXP_WFE_A_STAGE2_MUX3_MUX13 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX3_MUX13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX3_MUX13) -+#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX3_MUX12 0 -+#define BM_PXP_WFE_A_STAGE2_MUX3_MUX12 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX3_MUX12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX3_MUX12) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX4 (0x000017a0) -+#define HW_PXP_WFE_A_STAGE2_MUX4_SET (0x000017a4) -+#define HW_PXP_WFE_A_STAGE2_MUX4_CLR (0x000017a8) -+#define HW_PXP_WFE_A_STAGE2_MUX4_TOG (0x000017ac) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX4_MUX19 24 -+#define BM_PXP_WFE_A_STAGE2_MUX4_MUX19 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX4_MUX19(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX4_MUX19) -+#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX4_MUX18 16 -+#define BM_PXP_WFE_A_STAGE2_MUX4_MUX18 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX4_MUX18(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX4_MUX18) -+#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX4_MUX17 8 -+#define BM_PXP_WFE_A_STAGE2_MUX4_MUX17 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX4_MUX17(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX4_MUX17) -+#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX4_MUX16 0 -+#define BM_PXP_WFE_A_STAGE2_MUX4_MUX16 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX4_MUX16(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX4_MUX16) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX5 (0x000017b0) -+#define HW_PXP_WFE_A_STAGE2_MUX5_SET (0x000017b4) -+#define HW_PXP_WFE_A_STAGE2_MUX5_CLR (0x000017b8) -+#define HW_PXP_WFE_A_STAGE2_MUX5_TOG (0x000017bc) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX5_MUX23 24 -+#define BM_PXP_WFE_A_STAGE2_MUX5_MUX23 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX5_MUX23(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX5_MUX23) -+#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX5_MUX22 16 -+#define BM_PXP_WFE_A_STAGE2_MUX5_MUX22 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX5_MUX22(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX5_MUX22) -+#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX5_MUX21 8 -+#define BM_PXP_WFE_A_STAGE2_MUX5_MUX21 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX5_MUX21(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX5_MUX21) -+#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX5_MUX20 0 -+#define BM_PXP_WFE_A_STAGE2_MUX5_MUX20 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX5_MUX20(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX5_MUX20) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX6 (0x000017c0) -+#define HW_PXP_WFE_A_STAGE2_MUX6_SET (0x000017c4) -+#define HW_PXP_WFE_A_STAGE2_MUX6_CLR (0x000017c8) -+#define HW_PXP_WFE_A_STAGE2_MUX6_TOG (0x000017cc) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX6_MUX27 24 -+#define BM_PXP_WFE_A_STAGE2_MUX6_MUX27 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX6_MUX27(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX6_MUX27) -+#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX6_MUX26 16 -+#define BM_PXP_WFE_A_STAGE2_MUX6_MUX26 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX6_MUX26(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX6_MUX26) -+#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX6_MUX25 8 -+#define BM_PXP_WFE_A_STAGE2_MUX6_MUX25 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX6_MUX25(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX6_MUX25) -+#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX6_MUX24 0 -+#define BM_PXP_WFE_A_STAGE2_MUX6_MUX24 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX6_MUX24(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX6_MUX24) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX7 (0x000017d0) -+#define HW_PXP_WFE_A_STAGE2_MUX7_SET (0x000017d4) -+#define HW_PXP_WFE_A_STAGE2_MUX7_CLR (0x000017d8) -+#define HW_PXP_WFE_A_STAGE2_MUX7_TOG (0x000017dc) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX7_MUX31 24 -+#define BM_PXP_WFE_A_STAGE2_MUX7_MUX31 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX7_MUX31(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX7_MUX31) -+#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX7_MUX30 16 -+#define BM_PXP_WFE_A_STAGE2_MUX7_MUX30 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX7_MUX30(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX7_MUX30) -+#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX7_MUX29 8 -+#define BM_PXP_WFE_A_STAGE2_MUX7_MUX29 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX7_MUX29(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX7_MUX29) -+#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX7_MUX28 0 -+#define BM_PXP_WFE_A_STAGE2_MUX7_MUX28 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX7_MUX28(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX7_MUX28) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX8 (0x000017e0) -+#define HW_PXP_WFE_A_STAGE2_MUX8_SET (0x000017e4) -+#define HW_PXP_WFE_A_STAGE2_MUX8_CLR (0x000017e8) -+#define HW_PXP_WFE_A_STAGE2_MUX8_TOG (0x000017ec) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX8_MUX35 24 -+#define BM_PXP_WFE_A_STAGE2_MUX8_MUX35 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX8_MUX35(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX8_MUX35) -+#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX8_MUX34 16 -+#define BM_PXP_WFE_A_STAGE2_MUX8_MUX34 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX8_MUX34(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX8_MUX34) -+#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX8_MUX33 8 -+#define BM_PXP_WFE_A_STAGE2_MUX8_MUX33 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX8_MUX33(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX8_MUX33) -+#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX8_MUX32 0 -+#define BM_PXP_WFE_A_STAGE2_MUX8_MUX32 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX8_MUX32(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX8_MUX32) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX9 (0x000017f0) -+#define HW_PXP_WFE_A_STAGE2_MUX9_SET (0x000017f4) -+#define HW_PXP_WFE_A_STAGE2_MUX9_CLR (0x000017f8) -+#define HW_PXP_WFE_A_STAGE2_MUX9_TOG (0x000017fc) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX9_MUX39 24 -+#define BM_PXP_WFE_A_STAGE2_MUX9_MUX39 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX9_MUX39(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX9_MUX39) -+#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX9_MUX38 16 -+#define BM_PXP_WFE_A_STAGE2_MUX9_MUX38 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX9_MUX38(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX9_MUX38) -+#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX9_MUX37 8 -+#define BM_PXP_WFE_A_STAGE2_MUX9_MUX37 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX9_MUX37(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX9_MUX37) -+#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX9_MUX36 0 -+#define BM_PXP_WFE_A_STAGE2_MUX9_MUX36 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX9_MUX36(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX9_MUX36) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX10 (0x00001800) -+#define HW_PXP_WFE_A_STAGE2_MUX10_SET (0x00001804) -+#define HW_PXP_WFE_A_STAGE2_MUX10_CLR (0x00001808) -+#define HW_PXP_WFE_A_STAGE2_MUX10_TOG (0x0000180c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX10_MUX43 24 -+#define BM_PXP_WFE_A_STAGE2_MUX10_MUX43 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX10_MUX43(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX10_MUX43) -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__INC 0x0 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__DEC 0x1 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__ADD 0x2 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__MINUS 0x3 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__AND 0x4 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__OR 0x5 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__XOR 0x6 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTLEFT 0x7 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTRIGHT 0x8 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_AND 0x9 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_OR 0xa -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_CMP 0xb -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__NOP 0xc -+#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX10_MUX42 16 -+#define BM_PXP_WFE_A_STAGE2_MUX10_MUX42 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX10_MUX42(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX10_MUX42) -+#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX10_MUX41 8 -+#define BM_PXP_WFE_A_STAGE2_MUX10_MUX41 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX10_MUX41(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX10_MUX41) -+#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX10_MUX40 0 -+#define BM_PXP_WFE_A_STAGE2_MUX10_MUX40 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX10_MUX40(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX10_MUX40) -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__INC 0x0 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__DEC 0x1 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__ADD 0x2 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__MINUS 0x3 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__AND 0x4 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__OR 0x5 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__XOR 0x6 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_AND 0x9 -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_OR 0xa -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_CMP 0xb -+#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__NOP 0xc -+ -+#define HW_PXP_WFE_A_STAGE2_MUX11 (0x00001810) -+#define HW_PXP_WFE_A_STAGE2_MUX11_SET (0x00001814) -+#define HW_PXP_WFE_A_STAGE2_MUX11_CLR (0x00001818) -+#define HW_PXP_WFE_A_STAGE2_MUX11_TOG (0x0000181c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX11_MUX47 24 -+#define BM_PXP_WFE_A_STAGE2_MUX11_MUX47 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_MUX11_MUX47(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX11_MUX47) -+#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_MUX11_MUX46 16 -+#define BM_PXP_WFE_A_STAGE2_MUX11_MUX46 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_MUX11_MUX46(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX11_MUX46) -+#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_MUX11_MUX45 8 -+#define BM_PXP_WFE_A_STAGE2_MUX11_MUX45 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX11_MUX45(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX11_MUX45) -+#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX11_MUX44 0 -+#define BM_PXP_WFE_A_STAGE2_MUX11_MUX44 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX11_MUX44(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX11_MUX44) -+ -+#define HW_PXP_WFE_A_STAGE2_MUX12 (0x00001820) -+#define HW_PXP_WFE_A_STAGE2_MUX12_SET (0x00001824) -+#define HW_PXP_WFE_A_STAGE2_MUX12_CLR (0x00001828) -+#define HW_PXP_WFE_A_STAGE2_MUX12_TOG (0x0000182c) -+ -+#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD0 14 -+#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD0 0xFFFFC000 -+#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD0(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_MUX12_MUX49 8 -+#define BM_PXP_WFE_A_STAGE2_MUX12_MUX49 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_MUX12_MUX49(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX12_MUX49) -+#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_MUX12_MUX48 0 -+#define BM_PXP_WFE_A_STAGE2_MUX12_MUX48 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_MUX12_MUX48(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX12_MUX48) -+ -+#define HW_PXP_WFE_A_STAGE3_MUX0 (0x00001830) -+#define HW_PXP_WFE_A_STAGE3_MUX0_SET (0x00001834) -+#define HW_PXP_WFE_A_STAGE3_MUX0_CLR (0x00001838) -+#define HW_PXP_WFE_A_STAGE3_MUX0_TOG (0x0000183c) -+ -+#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD0) -+#define BP_PXP_WFE_A_STAGE3_MUX0_MUX3 24 -+#define BM_PXP_WFE_A_STAGE3_MUX0_MUX3 0x3F000000 -+#define BF_PXP_WFE_A_STAGE3_MUX0_MUX3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX0_MUX3) -+#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD1) -+#define BP_PXP_WFE_A_STAGE3_MUX0_MUX2 16 -+#define BM_PXP_WFE_A_STAGE3_MUX0_MUX2 0x003F0000 -+#define BF_PXP_WFE_A_STAGE3_MUX0_MUX2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX0_MUX2) -+#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD2) -+#define BP_PXP_WFE_A_STAGE3_MUX0_MUX1 8 -+#define BM_PXP_WFE_A_STAGE3_MUX0_MUX1 0x00003F00 -+#define BF_PXP_WFE_A_STAGE3_MUX0_MUX1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX0_MUX1) -+#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD3) -+#define BP_PXP_WFE_A_STAGE3_MUX0_MUX0 0 -+#define BM_PXP_WFE_A_STAGE3_MUX0_MUX0 0x0000003F -+#define BF_PXP_WFE_A_STAGE3_MUX0_MUX0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX0_MUX0) -+ -+#define HW_PXP_WFE_A_STAGE3_MUX1 (0x00001840) -+#define HW_PXP_WFE_A_STAGE3_MUX1_SET (0x00001844) -+#define HW_PXP_WFE_A_STAGE3_MUX1_CLR (0x00001848) -+#define HW_PXP_WFE_A_STAGE3_MUX1_TOG (0x0000184c) -+ -+#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD0) -+#define BP_PXP_WFE_A_STAGE3_MUX1_MUX7 24 -+#define BM_PXP_WFE_A_STAGE3_MUX1_MUX7 0x3F000000 -+#define BF_PXP_WFE_A_STAGE3_MUX1_MUX7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX1_MUX7) -+#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD1) -+#define BP_PXP_WFE_A_STAGE3_MUX1_MUX6 16 -+#define BM_PXP_WFE_A_STAGE3_MUX1_MUX6 0x003F0000 -+#define BF_PXP_WFE_A_STAGE3_MUX1_MUX6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX1_MUX6) -+#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD2) -+#define BP_PXP_WFE_A_STAGE3_MUX1_MUX5 8 -+#define BM_PXP_WFE_A_STAGE3_MUX1_MUX5 0x00003F00 -+#define BF_PXP_WFE_A_STAGE3_MUX1_MUX5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX1_MUX5) -+#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD3) -+#define BP_PXP_WFE_A_STAGE3_MUX1_MUX4 0 -+#define BM_PXP_WFE_A_STAGE3_MUX1_MUX4 0x0000003F -+#define BF_PXP_WFE_A_STAGE3_MUX1_MUX4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX1_MUX4) -+ -+#define HW_PXP_WFE_A_STAGE3_MUX2 (0x00001850) -+#define HW_PXP_WFE_A_STAGE3_MUX2_SET (0x00001854) -+#define HW_PXP_WFE_A_STAGE3_MUX2_CLR (0x00001858) -+#define HW_PXP_WFE_A_STAGE3_MUX2_TOG (0x0000185c) -+ -+#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD0) -+#define BP_PXP_WFE_A_STAGE3_MUX2_MUX11 24 -+#define BM_PXP_WFE_A_STAGE3_MUX2_MUX11 0x3F000000 -+#define BF_PXP_WFE_A_STAGE3_MUX2_MUX11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX2_MUX11) -+#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD1) -+#define BP_PXP_WFE_A_STAGE3_MUX2_MUX10 16 -+#define BM_PXP_WFE_A_STAGE3_MUX2_MUX10 0x003F0000 -+#define BF_PXP_WFE_A_STAGE3_MUX2_MUX10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX2_MUX10) -+#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD2) -+#define BP_PXP_WFE_A_STAGE3_MUX2_MUX9 8 -+#define BM_PXP_WFE_A_STAGE3_MUX2_MUX9 0x00003F00 -+#define BF_PXP_WFE_A_STAGE3_MUX2_MUX9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX2_MUX9) -+#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD3) -+#define BP_PXP_WFE_A_STAGE3_MUX2_MUX8 0 -+#define BM_PXP_WFE_A_STAGE3_MUX2_MUX8 0x0000003F -+#define BF_PXP_WFE_A_STAGE3_MUX2_MUX8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX2_MUX8) -+ -+#define HW_PXP_WFE_A_STAGE3_MUX3 (0x00001860) -+#define HW_PXP_WFE_A_STAGE3_MUX3_SET (0x00001864) -+#define HW_PXP_WFE_A_STAGE3_MUX3_CLR (0x00001868) -+#define HW_PXP_WFE_A_STAGE3_MUX3_TOG (0x0000186c) -+ -+#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD0) -+#define BP_PXP_WFE_A_STAGE3_MUX3_MUX15 24 -+#define BM_PXP_WFE_A_STAGE3_MUX3_MUX15 0x3F000000 -+#define BF_PXP_WFE_A_STAGE3_MUX3_MUX15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX3_MUX15) -+#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD1) -+#define BP_PXP_WFE_A_STAGE3_MUX3_MUX14 16 -+#define BM_PXP_WFE_A_STAGE3_MUX3_MUX14 0x003F0000 -+#define BF_PXP_WFE_A_STAGE3_MUX3_MUX14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX3_MUX14) -+#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD2) -+#define BP_PXP_WFE_A_STAGE3_MUX3_MUX13 8 -+#define BM_PXP_WFE_A_STAGE3_MUX3_MUX13 0x00003F00 -+#define BF_PXP_WFE_A_STAGE3_MUX3_MUX13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX3_MUX13) -+#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD3) -+#define BP_PXP_WFE_A_STAGE3_MUX3_MUX12 0 -+#define BM_PXP_WFE_A_STAGE3_MUX3_MUX12 0x0000003F -+#define BF_PXP_WFE_A_STAGE3_MUX3_MUX12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX3_MUX12) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_0 (0x00001870) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_1 (0x00001880) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_2 (0x00001890) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_3 (0x000018a0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_4 (0x000018b0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_5 (0x000018c0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_6 (0x000018d0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT0_7 (0x000018e0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225) -+#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_0 (0x000018f0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_1 (0x00001900) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_2 (0x00001910) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_3 (0x00001920) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_4 (0x00001930) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_5 (0x00001940) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_6 (0x00001950) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT1_7 (0x00001960) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225) -+#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_0 (0x00001970) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_1 (0x00001980) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_2 (0x00001990) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_3 (0x000019a0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_4 (0x000019b0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_5 (0x000019c0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_6 (0x000019d0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT2_7 (0x000019e0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225) -+#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_0 (0x000019f0) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_1 (0x00001a00) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_2 (0x00001a10) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_3 (0x00001a20) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_4 (0x00001a30) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_5 (0x00001a40) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_6 (0x00001a50) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192) -+ -+#define HW_PXP_WFE_A_STG1_8X1_OUT3_7 (0x00001a60) -+ -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225) -+#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_0 (0x00001a70) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_1 (0x00001a80) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_2 (0x00001a90) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_3 (0x00001aa0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_4 (0x00001ab0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_5 (0x00001ac0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_6 (0x00001ad0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT0_7 (0x00001ae0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_0 (0x00001af0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_1 (0x00001b00) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_2 (0x00001b10) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_3 (0x00001b20) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_4 (0x00001b30) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_5 (0x00001b40) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_6 (0x00001b50) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT1_7 (0x00001b60) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_0 (0x00001b70) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_1 (0x00001b80) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_2 (0x00001b90) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_3 (0x00001ba0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_4 (0x00001bb0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_5 (0x00001bc0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_6 (0x00001bd0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT2_7 (0x00001be0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_0 (0x00001bf0) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_1 (0x00001c00) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_2 (0x00001c10) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_3 (0x00001c20) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_4 (0x00001c30) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_5 (0x00001c40) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_6 (0x00001c50) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24) -+ -+#define HW_PXP_WFE_A_STG2_5X6_OUT3_7 (0x00001c60) -+ -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 30 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 24 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 22 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 16 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 14 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 8 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 6 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0 -+#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28) -+ -+#define HW_PXP_WFE_A_STAGE2_5X6_MASKS_0 (0x00001c70) -+ -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 29 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 0xE0000000 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 24 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 21 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 0x00E00000 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 16 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 13 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 0x0000E000 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 8 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 5 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 0x000000E0 -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0 -+#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0x0000001F -+#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0) -+ -+#define HW_PXP_WFE_A_STAGE2_5X6_ADDR_0 (0x00001c80) -+ -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 30 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 24 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 22 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 16 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 14 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 8 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 6 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3) -+#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0 -+#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F -+#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0) -+ -+#define HW_PXP_WFE_A_STG2_5X1_OUT0 (0x00001c90) -+ -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1) -+#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X1_OUT1 (0x00001ca0) -+ -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1) -+#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X1_OUT2 (0x00001cb0) -+ -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1) -+#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X1_OUT3 (0x00001cc0) -+ -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1) -+#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0) -+ -+#define HW_PXP_WFE_A_STG2_5X1_MASKS (0x00001cd0) -+ -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 29 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 0xE0000000 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD3(v) \ -+ (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK3 24 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3 0x1F000000 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 21 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 0x00E00000 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD2(v) \ -+ (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK2 16 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2 0x001F0000 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 13 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 0x0000E000 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK1 8 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1 0x00001F00 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 5 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 0x000000E0 -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0) -+#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0 -+#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0x0000001F -+#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0) -+ -+#define HW_PXP_WFE_B_CTRL (0x00001d00) -+#define HW_PXP_WFE_B_CTRL_SET (0x00001d04) -+#define HW_PXP_WFE_B_CTRL_CLR (0x00001d08) -+#define HW_PXP_WFE_B_CTRL_TOG (0x00001d0c) -+ -+#define BM_PXP_WFE_B_CTRL_DONE 0x80000000 -+#define BF_PXP_WFE_B_CTRL_DONE(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_CTRL_DONE) -+#define BP_PXP_WFE_B_CTRL_RSVD0 3 -+#define BM_PXP_WFE_B_CTRL_RSVD0 0x7FFFFFF8 -+#define BF_PXP_WFE_B_CTRL_RSVD0(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_CTRL_RSVD0) -+#define BM_PXP_WFE_B_CTRL_SW_RESET 0x00000004 -+#define BF_PXP_WFE_B_CTRL_SW_RESET(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_CTRL_SW_RESET) -+#define BM_PXP_WFE_B_CTRL_RSVD1 0x00000002 -+#define BF_PXP_WFE_B_CTRL_RSVD1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_CTRL_RSVD1) -+#define BM_PXP_WFE_B_CTRL_ENABLE 0x00000001 -+#define BF_PXP_WFE_B_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_CTRL_ENABLE) -+#define BV_PXP_WFE_B_CTRL_ENABLE__0 0x0 -+#define BV_PXP_WFE_B_CTRL_ENABLE__1 0x1 -+ -+#define HW_PXP_WFE_B_DIMENSIONS (0x00001d10) -+ -+#define BP_PXP_WFE_B_DIMENSIONS_RSVD0 28 -+#define BM_PXP_WFE_B_DIMENSIONS_RSVD0 0xF0000000 -+#define BF_PXP_WFE_B_DIMENSIONS_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_DIMENSIONS_RSVD0) -+#define BP_PXP_WFE_B_DIMENSIONS_HEIGHT 16 -+#define BM_PXP_WFE_B_DIMENSIONS_HEIGHT 0x0FFF0000 -+#define BF_PXP_WFE_B_DIMENSIONS_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_DIMENSIONS_HEIGHT) -+#define BP_PXP_WFE_B_DIMENSIONS_RSVD1 12 -+#define BM_PXP_WFE_B_DIMENSIONS_RSVD1 0x0000F000 -+#define BF_PXP_WFE_B_DIMENSIONS_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_DIMENSIONS_RSVD1) -+#define BP_PXP_WFE_B_DIMENSIONS_WIDTH 0 -+#define BM_PXP_WFE_B_DIMENSIONS_WIDTH 0x00000FFF -+#define BF_PXP_WFE_B_DIMENSIONS_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_DIMENSIONS_WIDTH) -+ -+#define HW_PXP_WFE_B_OFFSET (0x00001d20) -+ -+#define BP_PXP_WFE_B_OFFSET_RSVD0 28 -+#define BM_PXP_WFE_B_OFFSET_RSVD0 0xF0000000 -+#define BF_PXP_WFE_B_OFFSET_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_OFFSET_RSVD0) -+#define BP_PXP_WFE_B_OFFSET_Y_OFFSET 16 -+#define BM_PXP_WFE_B_OFFSET_Y_OFFSET 0x0FFF0000 -+#define BF_PXP_WFE_B_OFFSET_Y_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_OFFSET_Y_OFFSET) -+#define BP_PXP_WFE_B_OFFSET_RSVD1 12 -+#define BM_PXP_WFE_B_OFFSET_RSVD1 0x0000F000 -+#define BF_PXP_WFE_B_OFFSET_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_OFFSET_RSVD1) -+#define BP_PXP_WFE_B_OFFSET_X_OFFSET 0 -+#define BM_PXP_WFE_B_OFFSET_X_OFFSET 0x00000FFF -+#define BF_PXP_WFE_B_OFFSET_X_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_OFFSET_X_OFFSET) -+ -+#define HW_PXP_WFE_B_SW_DATA_REGS (0x00001d30) -+ -+#define BP_PXP_WFE_B_SW_DATA_REGS_VAL3 24 -+#define BM_PXP_WFE_B_SW_DATA_REGS_VAL3 0xFF000000 -+#define BF_PXP_WFE_B_SW_DATA_REGS_VAL3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_SW_DATA_REGS_VAL3) -+#define BP_PXP_WFE_B_SW_DATA_REGS_VAL2 16 -+#define BM_PXP_WFE_B_SW_DATA_REGS_VAL2 0x00FF0000 -+#define BF_PXP_WFE_B_SW_DATA_REGS_VAL2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_SW_DATA_REGS_VAL2) -+#define BP_PXP_WFE_B_SW_DATA_REGS_VAL1 8 -+#define BM_PXP_WFE_B_SW_DATA_REGS_VAL1 0x0000FF00 -+#define BF_PXP_WFE_B_SW_DATA_REGS_VAL1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_SW_DATA_REGS_VAL1) -+#define BP_PXP_WFE_B_SW_DATA_REGS_VAL0 0 -+#define BM_PXP_WFE_B_SW_DATA_REGS_VAL0 0x000000FF -+#define BF_PXP_WFE_B_SW_DATA_REGS_VAL0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_SW_DATA_REGS_VAL0) -+ -+#define HW_PXP_WFE_B_SW_FLAG_REGS (0x00001d40) -+ -+#define BP_PXP_WFE_B_SW_FLAG_REGS_RSVD 4 -+#define BM_PXP_WFE_B_SW_FLAG_REGS_RSVD 0xFFFFFFF0 -+#define BF_PXP_WFE_B_SW_FLAG_REGS_RSVD(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_SW_FLAG_REGS_RSVD) -+#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL3 0x00000008 -+#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL3) -+#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL2 0x00000004 -+#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL2) -+#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL1 0x00000002 -+#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL1) -+#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL0 0x00000001 -+#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL0) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX0 (0x00001d50) -+#define HW_PXP_WFE_B_STAGE1_MUX0_SET (0x00001d54) -+#define HW_PXP_WFE_B_STAGE1_MUX0_CLR (0x00001d58) -+#define HW_PXP_WFE_B_STAGE1_MUX0_TOG (0x00001d5c) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX0_MUX3 24 -+#define BM_PXP_WFE_B_STAGE1_MUX0_MUX3 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX0_MUX3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX0_MUX3) -+#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX0_MUX2 16 -+#define BM_PXP_WFE_B_STAGE1_MUX0_MUX2 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX0_MUX2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX0_MUX2) -+#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX0_MUX1 8 -+#define BM_PXP_WFE_B_STAGE1_MUX0_MUX1 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX0_MUX1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX0_MUX1) -+#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX0_MUX0 0 -+#define BM_PXP_WFE_B_STAGE1_MUX0_MUX0 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX0_MUX0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX0_MUX0) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX1 (0x00001d60) -+#define HW_PXP_WFE_B_STAGE1_MUX1_SET (0x00001d64) -+#define HW_PXP_WFE_B_STAGE1_MUX1_CLR (0x00001d68) -+#define HW_PXP_WFE_B_STAGE1_MUX1_TOG (0x00001d6c) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX1_MUX7 24 -+#define BM_PXP_WFE_B_STAGE1_MUX1_MUX7 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX1_MUX7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX1_MUX7) -+#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX1_MUX6 16 -+#define BM_PXP_WFE_B_STAGE1_MUX1_MUX6 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX1_MUX6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX1_MUX6) -+#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX1_MUX5 8 -+#define BM_PXP_WFE_B_STAGE1_MUX1_MUX5 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX1_MUX5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX1_MUX5) -+#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX1_MUX4 0 -+#define BM_PXP_WFE_B_STAGE1_MUX1_MUX4 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX1_MUX4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX1_MUX4) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX2 (0x00001d70) -+#define HW_PXP_WFE_B_STAGE1_MUX2_SET (0x00001d74) -+#define HW_PXP_WFE_B_STAGE1_MUX2_CLR (0x00001d78) -+#define HW_PXP_WFE_B_STAGE1_MUX2_TOG (0x00001d7c) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX2_MUX11 24 -+#define BM_PXP_WFE_B_STAGE1_MUX2_MUX11 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX2_MUX11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX2_MUX11) -+#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX2_MUX10 16 -+#define BM_PXP_WFE_B_STAGE1_MUX2_MUX10 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX2_MUX10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX2_MUX10) -+#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX2_MUX9 8 -+#define BM_PXP_WFE_B_STAGE1_MUX2_MUX9 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX2_MUX9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX2_MUX9) -+#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX2_MUX8 0 -+#define BM_PXP_WFE_B_STAGE1_MUX2_MUX8 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX2_MUX8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX2_MUX8) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX3 (0x00001d80) -+#define HW_PXP_WFE_B_STAGE1_MUX3_SET (0x00001d84) -+#define HW_PXP_WFE_B_STAGE1_MUX3_CLR (0x00001d88) -+#define HW_PXP_WFE_B_STAGE1_MUX3_TOG (0x00001d8c) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX3_MUX15 24 -+#define BM_PXP_WFE_B_STAGE1_MUX3_MUX15 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX3_MUX15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX3_MUX15) -+#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX3_MUX14 16 -+#define BM_PXP_WFE_B_STAGE1_MUX3_MUX14 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX3_MUX14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX3_MUX14) -+#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX3_MUX13 8 -+#define BM_PXP_WFE_B_STAGE1_MUX3_MUX13 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX3_MUX13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX3_MUX13) -+#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX3_MUX12 0 -+#define BM_PXP_WFE_B_STAGE1_MUX3_MUX12 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX3_MUX12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX3_MUX12) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX4 (0x00001d90) -+#define HW_PXP_WFE_B_STAGE1_MUX4_SET (0x00001d94) -+#define HW_PXP_WFE_B_STAGE1_MUX4_CLR (0x00001d98) -+#define HW_PXP_WFE_B_STAGE1_MUX4_TOG (0x00001d9c) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX4_MUX19 24 -+#define BM_PXP_WFE_B_STAGE1_MUX4_MUX19 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX4_MUX19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX4_MUX19) -+#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX4_MUX18 16 -+#define BM_PXP_WFE_B_STAGE1_MUX4_MUX18 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX4_MUX18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX4_MUX18) -+#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX4_MUX17 8 -+#define BM_PXP_WFE_B_STAGE1_MUX4_MUX17 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX4_MUX17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX4_MUX17) -+#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX4_MUX16 0 -+#define BM_PXP_WFE_B_STAGE1_MUX4_MUX16 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX4_MUX16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX4_MUX16) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX5 (0x00001da0) -+#define HW_PXP_WFE_B_STAGE1_MUX5_SET (0x00001da4) -+#define HW_PXP_WFE_B_STAGE1_MUX5_CLR (0x00001da8) -+#define HW_PXP_WFE_B_STAGE1_MUX5_TOG (0x00001dac) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX5_MUX23 24 -+#define BM_PXP_WFE_B_STAGE1_MUX5_MUX23 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX5_MUX23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX5_MUX23) -+#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX5_MUX22 16 -+#define BM_PXP_WFE_B_STAGE1_MUX5_MUX22 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX5_MUX22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX5_MUX22) -+#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX5_MUX21 8 -+#define BM_PXP_WFE_B_STAGE1_MUX5_MUX21 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX5_MUX21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX5_MUX21) -+#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX5_MUX20 0 -+#define BM_PXP_WFE_B_STAGE1_MUX5_MUX20 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX5_MUX20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX5_MUX20) -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__INC 0x0 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__DEC 0x1 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__ADD 0x2 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__MINUS 0x3 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__AND 0x4 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__OR 0x5 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__XOR 0x6 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTLEFT 0x7 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTRIGHT 0x8 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_AND 0x9 -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_OR 0xa -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_CMP 0xb -+#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__NOP 0xc -+ -+#define HW_PXP_WFE_B_STAGE1_MUX6 (0x00001db0) -+#define HW_PXP_WFE_B_STAGE1_MUX6_SET (0x00001db4) -+#define HW_PXP_WFE_B_STAGE1_MUX6_CLR (0x00001db8) -+#define HW_PXP_WFE_B_STAGE1_MUX6_TOG (0x00001dbc) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX6_MUX27 24 -+#define BM_PXP_WFE_B_STAGE1_MUX6_MUX27 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX6_MUX27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX6_MUX27) -+#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX6_MUX26 16 -+#define BM_PXP_WFE_B_STAGE1_MUX6_MUX26 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX6_MUX26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX6_MUX26) -+#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX6_MUX25 8 -+#define BM_PXP_WFE_B_STAGE1_MUX6_MUX25 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX6_MUX25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX6_MUX25) -+#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX6_MUX24 0 -+#define BM_PXP_WFE_B_STAGE1_MUX6_MUX24 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX6_MUX24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX6_MUX24) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX7 (0x00001dc0) -+#define HW_PXP_WFE_B_STAGE1_MUX7_SET (0x00001dc4) -+#define HW_PXP_WFE_B_STAGE1_MUX7_CLR (0x00001dc8) -+#define HW_PXP_WFE_B_STAGE1_MUX7_TOG (0x00001dcc) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX7_MUX31 24 -+#define BM_PXP_WFE_B_STAGE1_MUX7_MUX31 0x3F000000 -+#define BF_PXP_WFE_B_STAGE1_MUX7_MUX31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX7_MUX31) -+#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD1) -+#define BP_PXP_WFE_B_STAGE1_MUX7_MUX30 16 -+#define BM_PXP_WFE_B_STAGE1_MUX7_MUX30 0x003F0000 -+#define BF_PXP_WFE_B_STAGE1_MUX7_MUX30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX7_MUX30) -+#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_MUX7_MUX29 8 -+#define BM_PXP_WFE_B_STAGE1_MUX7_MUX29 0x00003F00 -+#define BF_PXP_WFE_B_STAGE1_MUX7_MUX29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX7_MUX29) -+#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_MUX7_MUX28 0 -+#define BM_PXP_WFE_B_STAGE1_MUX7_MUX28 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX7_MUX28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX7_MUX28) -+ -+#define HW_PXP_WFE_B_STAGE1_MUX8 (0x00001dd0) -+#define HW_PXP_WFE_B_STAGE1_MUX8_SET (0x00001dd4) -+#define HW_PXP_WFE_B_STAGE1_MUX8_CLR (0x00001dd8) -+#define HW_PXP_WFE_B_STAGE1_MUX8_TOG (0x00001ddc) -+ -+#define BP_PXP_WFE_B_STAGE1_MUX8_RSVD0 6 -+#define BM_PXP_WFE_B_STAGE1_MUX8_RSVD0 0xFFFFFFC0 -+#define BF_PXP_WFE_B_STAGE1_MUX8_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX8_RSVD0) -+#define BP_PXP_WFE_B_STAGE1_MUX8_MUX32 0 -+#define BM_PXP_WFE_B_STAGE1_MUX8_MUX32 0x0000003F -+#define BF_PXP_WFE_B_STAGE1_MUX8_MUX32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX8_MUX32) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX0 (0x00001de0) -+#define HW_PXP_WFE_B_STAGE2_MUX0_SET (0x00001de4) -+#define HW_PXP_WFE_B_STAGE2_MUX0_CLR (0x00001de8) -+#define HW_PXP_WFE_B_STAGE2_MUX0_TOG (0x00001dec) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX0_MUX3 24 -+#define BM_PXP_WFE_B_STAGE2_MUX0_MUX3 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX0_MUX3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX0_MUX3) -+#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX0_MUX2 16 -+#define BM_PXP_WFE_B_STAGE2_MUX0_MUX2 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX0_MUX2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX0_MUX2) -+#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX0_MUX1 8 -+#define BM_PXP_WFE_B_STAGE2_MUX0_MUX1 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX0_MUX1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX0_MUX1) -+#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX0_MUX0 0 -+#define BM_PXP_WFE_B_STAGE2_MUX0_MUX0 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX0_MUX0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX0_MUX0) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX1 (0x00001df0) -+#define HW_PXP_WFE_B_STAGE2_MUX1_SET (0x00001df4) -+#define HW_PXP_WFE_B_STAGE2_MUX1_CLR (0x00001df8) -+#define HW_PXP_WFE_B_STAGE2_MUX1_TOG (0x00001dfc) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX1_MUX7 24 -+#define BM_PXP_WFE_B_STAGE2_MUX1_MUX7 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX1_MUX7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX1_MUX7) -+#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX1_MUX6 16 -+#define BM_PXP_WFE_B_STAGE2_MUX1_MUX6 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX1_MUX6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX1_MUX6) -+#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX1_MUX5 8 -+#define BM_PXP_WFE_B_STAGE2_MUX1_MUX5 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX1_MUX5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX1_MUX5) -+#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX1_MUX4 0 -+#define BM_PXP_WFE_B_STAGE2_MUX1_MUX4 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX1_MUX4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX1_MUX4) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX2 (0x00001e00) -+#define HW_PXP_WFE_B_STAGE2_MUX2_SET (0x00001e04) -+#define HW_PXP_WFE_B_STAGE2_MUX2_CLR (0x00001e08) -+#define HW_PXP_WFE_B_STAGE2_MUX2_TOG (0x00001e0c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX2_MUX11 24 -+#define BM_PXP_WFE_B_STAGE2_MUX2_MUX11 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX2_MUX11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX2_MUX11) -+#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX2_MUX10 16 -+#define BM_PXP_WFE_B_STAGE2_MUX2_MUX10 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX2_MUX10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX2_MUX10) -+#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX2_MUX9 8 -+#define BM_PXP_WFE_B_STAGE2_MUX2_MUX9 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX2_MUX9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX2_MUX9) -+#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX2_MUX8 0 -+#define BM_PXP_WFE_B_STAGE2_MUX2_MUX8 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX2_MUX8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX2_MUX8) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX3 (0x00001e10) -+#define HW_PXP_WFE_B_STAGE2_MUX3_SET (0x00001e14) -+#define HW_PXP_WFE_B_STAGE2_MUX3_CLR (0x00001e18) -+#define HW_PXP_WFE_B_STAGE2_MUX3_TOG (0x00001e1c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX3_MUX15 24 -+#define BM_PXP_WFE_B_STAGE2_MUX3_MUX15 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX3_MUX15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX3_MUX15) -+#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX3_MUX14 16 -+#define BM_PXP_WFE_B_STAGE2_MUX3_MUX14 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX3_MUX14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX3_MUX14) -+#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX3_MUX13 8 -+#define BM_PXP_WFE_B_STAGE2_MUX3_MUX13 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX3_MUX13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX3_MUX13) -+#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX3_MUX12 0 -+#define BM_PXP_WFE_B_STAGE2_MUX3_MUX12 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX3_MUX12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX3_MUX12) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX4 (0x00001e20) -+#define HW_PXP_WFE_B_STAGE2_MUX4_SET (0x00001e24) -+#define HW_PXP_WFE_B_STAGE2_MUX4_CLR (0x00001e28) -+#define HW_PXP_WFE_B_STAGE2_MUX4_TOG (0x00001e2c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX4_MUX19 24 -+#define BM_PXP_WFE_B_STAGE2_MUX4_MUX19 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX4_MUX19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX4_MUX19) -+#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX4_MUX18 16 -+#define BM_PXP_WFE_B_STAGE2_MUX4_MUX18 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX4_MUX18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX4_MUX18) -+#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX4_MUX17 8 -+#define BM_PXP_WFE_B_STAGE2_MUX4_MUX17 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX4_MUX17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX4_MUX17) -+#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX4_MUX16 0 -+#define BM_PXP_WFE_B_STAGE2_MUX4_MUX16 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX4_MUX16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX4_MUX16) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX5 (0x00001e30) -+#define HW_PXP_WFE_B_STAGE2_MUX5_SET (0x00001e34) -+#define HW_PXP_WFE_B_STAGE2_MUX5_CLR (0x00001e38) -+#define HW_PXP_WFE_B_STAGE2_MUX5_TOG (0x00001e3c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX5_MUX23 24 -+#define BM_PXP_WFE_B_STAGE2_MUX5_MUX23 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX5_MUX23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX5_MUX23) -+#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX5_MUX22 16 -+#define BM_PXP_WFE_B_STAGE2_MUX5_MUX22 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX5_MUX22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX5_MUX22) -+#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX5_MUX21 8 -+#define BM_PXP_WFE_B_STAGE2_MUX5_MUX21 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX5_MUX21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX5_MUX21) -+#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX5_MUX20 0 -+#define BM_PXP_WFE_B_STAGE2_MUX5_MUX20 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX5_MUX20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX5_MUX20) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX6 (0x00001e40) -+#define HW_PXP_WFE_B_STAGE2_MUX6_SET (0x00001e44) -+#define HW_PXP_WFE_B_STAGE2_MUX6_CLR (0x00001e48) -+#define HW_PXP_WFE_B_STAGE2_MUX6_TOG (0x00001e4c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX6_MUX27 24 -+#define BM_PXP_WFE_B_STAGE2_MUX6_MUX27 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX6_MUX27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX6_MUX27) -+#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX6_MUX26 16 -+#define BM_PXP_WFE_B_STAGE2_MUX6_MUX26 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX6_MUX26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX6_MUX26) -+#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX6_MUX25 8 -+#define BM_PXP_WFE_B_STAGE2_MUX6_MUX25 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX6_MUX25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX6_MUX25) -+#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX6_MUX24 0 -+#define BM_PXP_WFE_B_STAGE2_MUX6_MUX24 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX6_MUX24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX6_MUX24) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX7 (0x00001e50) -+#define HW_PXP_WFE_B_STAGE2_MUX7_SET (0x00001e54) -+#define HW_PXP_WFE_B_STAGE2_MUX7_CLR (0x00001e58) -+#define HW_PXP_WFE_B_STAGE2_MUX7_TOG (0x00001e5c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX7_MUX31 24 -+#define BM_PXP_WFE_B_STAGE2_MUX7_MUX31 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX7_MUX31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX7_MUX31) -+#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX7_MUX30 16 -+#define BM_PXP_WFE_B_STAGE2_MUX7_MUX30 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX7_MUX30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX7_MUX30) -+#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX7_MUX29 8 -+#define BM_PXP_WFE_B_STAGE2_MUX7_MUX29 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX7_MUX29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX7_MUX29) -+#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX7_MUX28 0 -+#define BM_PXP_WFE_B_STAGE2_MUX7_MUX28 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX7_MUX28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX7_MUX28) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX8 (0x00001e60) -+#define HW_PXP_WFE_B_STAGE2_MUX8_SET (0x00001e64) -+#define HW_PXP_WFE_B_STAGE2_MUX8_CLR (0x00001e68) -+#define HW_PXP_WFE_B_STAGE2_MUX8_TOG (0x00001e6c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX8_MUX35 24 -+#define BM_PXP_WFE_B_STAGE2_MUX8_MUX35 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX8_MUX35(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX8_MUX35) -+#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX8_MUX34 16 -+#define BM_PXP_WFE_B_STAGE2_MUX8_MUX34 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX8_MUX34(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX8_MUX34) -+#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX8_MUX33 8 -+#define BM_PXP_WFE_B_STAGE2_MUX8_MUX33 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX8_MUX33(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX8_MUX33) -+#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX8_MUX32 0 -+#define BM_PXP_WFE_B_STAGE2_MUX8_MUX32 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX8_MUX32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX8_MUX32) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX9 (0x00001e70) -+#define HW_PXP_WFE_B_STAGE2_MUX9_SET (0x00001e74) -+#define HW_PXP_WFE_B_STAGE2_MUX9_CLR (0x00001e78) -+#define HW_PXP_WFE_B_STAGE2_MUX9_TOG (0x00001e7c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX9_MUX39 24 -+#define BM_PXP_WFE_B_STAGE2_MUX9_MUX39 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX9_MUX39(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX9_MUX39) -+#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX9_MUX38 16 -+#define BM_PXP_WFE_B_STAGE2_MUX9_MUX38 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX9_MUX38(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX9_MUX38) -+#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX9_MUX37 8 -+#define BM_PXP_WFE_B_STAGE2_MUX9_MUX37 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX9_MUX37(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX9_MUX37) -+#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX9_MUX36 0 -+#define BM_PXP_WFE_B_STAGE2_MUX9_MUX36 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX9_MUX36(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX9_MUX36) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX10 (0x00001e80) -+#define HW_PXP_WFE_B_STAGE2_MUX10_SET (0x00001e84) -+#define HW_PXP_WFE_B_STAGE2_MUX10_CLR (0x00001e88) -+#define HW_PXP_WFE_B_STAGE2_MUX10_TOG (0x00001e8c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX10_MUX43 24 -+#define BM_PXP_WFE_B_STAGE2_MUX10_MUX43 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX10_MUX43(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX10_MUX43) -+#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX10_MUX42 16 -+#define BM_PXP_WFE_B_STAGE2_MUX10_MUX42 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX10_MUX42(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX10_MUX42) -+#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX10_MUX41 8 -+#define BM_PXP_WFE_B_STAGE2_MUX10_MUX41 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX10_MUX41(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX10_MUX41) -+#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX10_MUX40 0 -+#define BM_PXP_WFE_B_STAGE2_MUX10_MUX40 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX10_MUX40(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX10_MUX40) -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__INC 0x0 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__DEC 0x1 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__ADD 0x2 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__MINUS 0x3 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__AND 0x4 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__OR 0x5 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__XOR 0x6 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_AND 0x9 -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_OR 0xa -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_CMP 0xb -+#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__NOP 0xc -+ -+#define HW_PXP_WFE_B_STAGE2_MUX11 (0x00001e90) -+#define HW_PXP_WFE_B_STAGE2_MUX11_SET (0x00001e94) -+#define HW_PXP_WFE_B_STAGE2_MUX11_CLR (0x00001e98) -+#define HW_PXP_WFE_B_STAGE2_MUX11_TOG (0x00001e9c) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX11_MUX47 24 -+#define BM_PXP_WFE_B_STAGE2_MUX11_MUX47 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_MUX11_MUX47(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX11_MUX47) -+#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_MUX11_MUX46 16 -+#define BM_PXP_WFE_B_STAGE2_MUX11_MUX46 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_MUX11_MUX46(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX11_MUX46) -+#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_MUX11_MUX45 8 -+#define BM_PXP_WFE_B_STAGE2_MUX11_MUX45 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_MUX11_MUX45(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX11_MUX45) -+#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_MUX11_MUX44 0 -+#define BM_PXP_WFE_B_STAGE2_MUX11_MUX44 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX11_MUX44(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX11_MUX44) -+ -+#define HW_PXP_WFE_B_STAGE2_MUX12 (0x00001ea0) -+#define HW_PXP_WFE_B_STAGE2_MUX12_SET (0x00001ea4) -+#define HW_PXP_WFE_B_STAGE2_MUX12_CLR (0x00001ea8) -+#define HW_PXP_WFE_B_STAGE2_MUX12_TOG (0x00001eac) -+ -+#define BP_PXP_WFE_B_STAGE2_MUX12_RSVD0 6 -+#define BM_PXP_WFE_B_STAGE2_MUX12_RSVD0 0xFFFFFFC0 -+#define BF_PXP_WFE_B_STAGE2_MUX12_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX12_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_MUX12_MUX48 0 -+#define BM_PXP_WFE_B_STAGE2_MUX12_MUX48 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_MUX12_MUX48(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX12_MUX48) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX0 (0x00001eb0) -+#define HW_PXP_WFE_B_STAGE3_MUX0_SET (0x00001eb4) -+#define HW_PXP_WFE_B_STAGE3_MUX0_CLR (0x00001eb8) -+#define HW_PXP_WFE_B_STAGE3_MUX0_TOG (0x00001ebc) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX0_MUX3 24 -+#define BM_PXP_WFE_B_STAGE3_MUX0_MUX3 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX0_MUX3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX0_MUX3) -+#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX0_MUX2 16 -+#define BM_PXP_WFE_B_STAGE3_MUX0_MUX2 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX0_MUX2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX0_MUX2) -+#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX0_MUX1 8 -+#define BM_PXP_WFE_B_STAGE3_MUX0_MUX1 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX0_MUX1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX0_MUX1) -+#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX0_MUX0 0 -+#define BM_PXP_WFE_B_STAGE3_MUX0_MUX0 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX0_MUX0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX0_MUX0) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX1 (0x00001ec0) -+#define HW_PXP_WFE_B_STAGE3_MUX1_SET (0x00001ec4) -+#define HW_PXP_WFE_B_STAGE3_MUX1_CLR (0x00001ec8) -+#define HW_PXP_WFE_B_STAGE3_MUX1_TOG (0x00001ecc) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX1_MUX7 24 -+#define BM_PXP_WFE_B_STAGE3_MUX1_MUX7 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX1_MUX7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX1_MUX7) -+#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX1_MUX6 16 -+#define BM_PXP_WFE_B_STAGE3_MUX1_MUX6 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX1_MUX6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX1_MUX6) -+#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX1_MUX5 8 -+#define BM_PXP_WFE_B_STAGE3_MUX1_MUX5 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX1_MUX5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX1_MUX5) -+#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX1_MUX4 0 -+#define BM_PXP_WFE_B_STAGE3_MUX1_MUX4 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX1_MUX4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX1_MUX4) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX2 (0x00001ed0) -+#define HW_PXP_WFE_B_STAGE3_MUX2_SET (0x00001ed4) -+#define HW_PXP_WFE_B_STAGE3_MUX2_CLR (0x00001ed8) -+#define HW_PXP_WFE_B_STAGE3_MUX2_TOG (0x00001edc) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX2_MUX11 24 -+#define BM_PXP_WFE_B_STAGE3_MUX2_MUX11 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX2_MUX11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX2_MUX11) -+#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX2_MUX10 16 -+#define BM_PXP_WFE_B_STAGE3_MUX2_MUX10 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX2_MUX10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX2_MUX10) -+#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX2_MUX9 8 -+#define BM_PXP_WFE_B_STAGE3_MUX2_MUX9 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX2_MUX9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX2_MUX9) -+#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX2_MUX8 0 -+#define BM_PXP_WFE_B_STAGE3_MUX2_MUX8 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX2_MUX8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX2_MUX8) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX3 (0x00001ee0) -+#define HW_PXP_WFE_B_STAGE3_MUX3_SET (0x00001ee4) -+#define HW_PXP_WFE_B_STAGE3_MUX3_CLR (0x00001ee8) -+#define HW_PXP_WFE_B_STAGE3_MUX3_TOG (0x00001eec) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX3_MUX15 24 -+#define BM_PXP_WFE_B_STAGE3_MUX3_MUX15 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX3_MUX15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX3_MUX15) -+#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX3_MUX14 16 -+#define BM_PXP_WFE_B_STAGE3_MUX3_MUX14 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX3_MUX14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX3_MUX14) -+#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX3_MUX13 8 -+#define BM_PXP_WFE_B_STAGE3_MUX3_MUX13 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX3_MUX13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX3_MUX13) -+#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX3_MUX12 0 -+#define BM_PXP_WFE_B_STAGE3_MUX3_MUX12 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX3_MUX12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX3_MUX12) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX4 (0x00001ef0) -+#define HW_PXP_WFE_B_STAGE3_MUX4_SET (0x00001ef4) -+#define HW_PXP_WFE_B_STAGE3_MUX4_CLR (0x00001ef8) -+#define HW_PXP_WFE_B_STAGE3_MUX4_TOG (0x00001efc) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX4_MUX19 24 -+#define BM_PXP_WFE_B_STAGE3_MUX4_MUX19 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX4_MUX19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX4_MUX19) -+#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX4_MUX18 16 -+#define BM_PXP_WFE_B_STAGE3_MUX4_MUX18 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX4_MUX18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX4_MUX18) -+#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX4_MUX17 8 -+#define BM_PXP_WFE_B_STAGE3_MUX4_MUX17 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX4_MUX17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX4_MUX17) -+#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX4_MUX16 0 -+#define BM_PXP_WFE_B_STAGE3_MUX4_MUX16 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX4_MUX16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX4_MUX16) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX5 (0x00001f00) -+#define HW_PXP_WFE_B_STAGE3_MUX5_SET (0x00001f04) -+#define HW_PXP_WFE_B_STAGE3_MUX5_CLR (0x00001f08) -+#define HW_PXP_WFE_B_STAGE3_MUX5_TOG (0x00001f0c) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX5_MUX23 24 -+#define BM_PXP_WFE_B_STAGE3_MUX5_MUX23 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX5_MUX23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX5_MUX23) -+#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX5_MUX22 16 -+#define BM_PXP_WFE_B_STAGE3_MUX5_MUX22 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX5_MUX22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX5_MUX22) -+#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX5_MUX21 8 -+#define BM_PXP_WFE_B_STAGE3_MUX5_MUX21 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX5_MUX21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX5_MUX21) -+#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX5_MUX20 0 -+#define BM_PXP_WFE_B_STAGE3_MUX5_MUX20 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX5_MUX20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX5_MUX20) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX6 (0x00001f10) -+#define HW_PXP_WFE_B_STAGE3_MUX6_SET (0x00001f14) -+#define HW_PXP_WFE_B_STAGE3_MUX6_CLR (0x00001f18) -+#define HW_PXP_WFE_B_STAGE3_MUX6_TOG (0x00001f1c) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX6_MUX27 24 -+#define BM_PXP_WFE_B_STAGE3_MUX6_MUX27 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX6_MUX27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX6_MUX27) -+#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX6_MUX26 16 -+#define BM_PXP_WFE_B_STAGE3_MUX6_MUX26 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX6_MUX26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX6_MUX26) -+#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX6_MUX25 8 -+#define BM_PXP_WFE_B_STAGE3_MUX6_MUX25 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX6_MUX25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX6_MUX25) -+#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX6_MUX24 0 -+#define BM_PXP_WFE_B_STAGE3_MUX6_MUX24 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX6_MUX24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX6_MUX24) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX7 (0x00001f20) -+#define HW_PXP_WFE_B_STAGE3_MUX7_SET (0x00001f24) -+#define HW_PXP_WFE_B_STAGE3_MUX7_CLR (0x00001f28) -+#define HW_PXP_WFE_B_STAGE3_MUX7_TOG (0x00001f2c) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX7_MUX31 24 -+#define BM_PXP_WFE_B_STAGE3_MUX7_MUX31 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX7_MUX31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX7_MUX31) -+#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX7_MUX30 16 -+#define BM_PXP_WFE_B_STAGE3_MUX7_MUX30 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX7_MUX30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX7_MUX30) -+#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX7_MUX29 8 -+#define BM_PXP_WFE_B_STAGE3_MUX7_MUX29 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX7_MUX29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX7_MUX29) -+#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX7_MUX28 0 -+#define BM_PXP_WFE_B_STAGE3_MUX7_MUX28 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX7_MUX28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX7_MUX28) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX8 (0x00001f30) -+#define HW_PXP_WFE_B_STAGE3_MUX8_SET (0x00001f34) -+#define HW_PXP_WFE_B_STAGE3_MUX8_CLR (0x00001f38) -+#define HW_PXP_WFE_B_STAGE3_MUX8_TOG (0x00001f3c) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX8_MUX35 24 -+#define BM_PXP_WFE_B_STAGE3_MUX8_MUX35 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX8_MUX35(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX8_MUX35) -+#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX8_MUX34 16 -+#define BM_PXP_WFE_B_STAGE3_MUX8_MUX34 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX8_MUX34(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX8_MUX34) -+#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX8_MUX33 8 -+#define BM_PXP_WFE_B_STAGE3_MUX8_MUX33 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX8_MUX33(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX8_MUX33) -+#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX8_MUX32 0 -+#define BM_PXP_WFE_B_STAGE3_MUX8_MUX32 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX8_MUX32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX8_MUX32) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX9 (0x00001f40) -+#define HW_PXP_WFE_B_STAGE3_MUX9_SET (0x00001f44) -+#define HW_PXP_WFE_B_STAGE3_MUX9_CLR (0x00001f48) -+#define HW_PXP_WFE_B_STAGE3_MUX9_TOG (0x00001f4c) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX9_MUX39 24 -+#define BM_PXP_WFE_B_STAGE3_MUX9_MUX39 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX9_MUX39(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX9_MUX39) -+#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX9_MUX38 16 -+#define BM_PXP_WFE_B_STAGE3_MUX9_MUX38 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX9_MUX38(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX9_MUX38) -+#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX9_MUX37 8 -+#define BM_PXP_WFE_B_STAGE3_MUX9_MUX37 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX9_MUX37(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX9_MUX37) -+#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX9_MUX36 0 -+#define BM_PXP_WFE_B_STAGE3_MUX9_MUX36 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX9_MUX36(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX9_MUX36) -+ -+#define HW_PXP_WFE_B_STAGE3_MUX10 (0x00001f50) -+#define HW_PXP_WFE_B_STAGE3_MUX10_SET (0x00001f54) -+#define HW_PXP_WFE_B_STAGE3_MUX10_CLR (0x00001f58) -+#define HW_PXP_WFE_B_STAGE3_MUX10_TOG (0x00001f5c) -+ -+#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD0 30 -+#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD0) -+#define BP_PXP_WFE_B_STAGE3_MUX10_MUX43 24 -+#define BM_PXP_WFE_B_STAGE3_MUX10_MUX43 0x3F000000 -+#define BF_PXP_WFE_B_STAGE3_MUX10_MUX43(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX10_MUX43) -+#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD1 22 -+#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD1) -+#define BP_PXP_WFE_B_STAGE3_MUX10_MUX42 16 -+#define BM_PXP_WFE_B_STAGE3_MUX10_MUX42 0x003F0000 -+#define BF_PXP_WFE_B_STAGE3_MUX10_MUX42(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX10_MUX42) -+#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD2 14 -+#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD2) -+#define BP_PXP_WFE_B_STAGE3_MUX10_MUX41 8 -+#define BM_PXP_WFE_B_STAGE3_MUX10_MUX41 0x00003F00 -+#define BF_PXP_WFE_B_STAGE3_MUX10_MUX41(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX10_MUX41) -+#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD3 6 -+#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD3) -+#define BP_PXP_WFE_B_STAGE3_MUX10_MUX40 0 -+#define BM_PXP_WFE_B_STAGE3_MUX10_MUX40 0x0000003F -+#define BF_PXP_WFE_B_STAGE3_MUX10_MUX40(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX10_MUX40) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_0 (0x00001f60) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_1 (0x00001f70) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_2 (0x00001f80) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_3 (0x00001f90) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_4 (0x00001fa0) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_5 (0x00001fb0) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_6 (0x00001fc0) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT0_7 (0x00001fd0) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29) -+#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_0 (0x00001fe0) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_1 (0x00001ff0) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_2 (0x00002000) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_3 (0x00002010) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_4 (0x00002020) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_5 (0x00002030) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_6 (0x00002040) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24) -+ -+#define HW_PXP_WFE_B_STG1_5X8_OUT1_7 (0x00002050) -+ -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 24 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 0xFF000000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 16 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 0x00FF0000 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 8 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 0x0000FF00 -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29) -+#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0 -+#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0x000000FF -+#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28) -+ -+#define HW_PXP_WFE_B_STAGE1_5X8_MASKS_0 (0x00002060) -+ -+#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 13 -+#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 0xFFFFE000 -+#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2) -+#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 8 -+#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 0x00001F00 -+#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1) -+#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 5 -+#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 0x000000E0 -+#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3) -+#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0 -+#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0x0000001F -+#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0) -+ -+#define HW_PXP_WFE_B_STG1_5X1_OUT0 (0x00002070) -+ -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1) -+#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_5X1_MASKS (0x00002080) -+ -+#define BP_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 5 -+#define BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 0xFFFFFFE0 -+#define BF_PXP_WFE_B_STG1_5X1_MASKS_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0) -+#define BP_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0 -+#define BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0x0000001F -+#define BF_PXP_WFE_B_STG1_5X1_MASKS_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_0 (0x00002090) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_1 (0x000020a0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_2 (0x000020b0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_3 (0x000020c0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_4 (0x000020d0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_5 (0x000020e0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_6 (0x000020f0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT0_7 (0x00002100) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_0 (0x00002110) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_1 (0x00002120) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_2 (0x00002130) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_3 (0x00002140) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_4 (0x00002150) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_5 (0x00002160) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_6 (0x00002170) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT1_7 (0x00002180) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_0 (0x00002190) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_1 (0x000021a0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_2 (0x000021b0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_3 (0x000021c0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_4 (0x000021d0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_5 (0x000021e0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_6 (0x000021f0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT2_7 (0x00002200) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_0 (0x00002210) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_1 (0x00002220) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_2 (0x00002230) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_3 (0x00002240) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_4 (0x00002250) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_5 (0x00002260) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_6 (0x00002270) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT3_7 (0x00002280) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_0 (0x00002290) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_1 (0x000022a0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_2 (0x000022b0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_3 (0x000022c0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_4 (0x000022d0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_5 (0x000022e0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_6 (0x000022f0) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG1_8X1_OUT4_7 (0x00002300) -+ -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_0 (0x00002310) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_1 (0x00002320) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_2 (0x00002330) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_3 (0x00002340) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_4 (0x00002350) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_5 (0x00002360) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_6 (0x00002370) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT0_7 (0x00002380) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_0 (0x00002390) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_1 (0x000023a0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_2 (0x000023b0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_3 (0x000023c0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_4 (0x000023d0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_5 (0x000023e0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_6 (0x000023f0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT1_7 (0x00002400) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_0 (0x00002410) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_1 (0x00002420) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_2 (0x00002430) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_3 (0x00002440) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_4 (0x00002450) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_5 (0x00002460) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_6 (0x00002470) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT2_7 (0x00002480) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_0 (0x00002490) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_1 (0x000024a0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_2 (0x000024b0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_3 (0x000024c0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_4 (0x000024e0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_5 (0x000024f0) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_6 (0x00002500) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24) -+ -+#define HW_PXP_WFE_B_STG2_5X6_OUT3_7 (0x00002510) -+ -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 30 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 0xC0000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 24 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 22 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 0x00C00000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 16 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 14 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 0x0000C000 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 8 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 6 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 0x000000C0 -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0 -+#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F -+#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28) -+ -+#define HW_PXP_WFE_B_STAGE2_5X6_MASKS_0 (0x00002520) -+ -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 29 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 0xE0000000 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 24 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 21 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 0x00E00000 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 16 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 13 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 0x0000E000 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 8 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 5 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 0x000000E0 -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0 -+#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0x0000001F -+#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0) -+ -+#define HW_PXP_WFE_B_STAGE2_5X6_ADDR_0 (0x00002530) -+ -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 30 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 0xC0000000 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 24 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 22 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 0x00C00000 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 16 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 14 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 0x0000C000 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 8 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 6 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 0x000000C0 -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0) -+#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0 -+#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F -+#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0) -+ -+#define HW_PXP_WFE_B_STG2_5X1_OUT0 (0x00002540) -+ -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1) -+#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X1_OUT1 (0x00002550) -+ -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1) -+#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X1_OUT2 (0x00002560) -+ -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1) -+#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X1_OUT3 (0x00002570) -+ -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1) -+#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG2_5X1_MASKS (0x00002580) -+ -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 29 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 0xE0000000 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD3(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK3 24 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3 0x1F000000 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 21 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 0x00E00000 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD2(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK2 16 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2 0x001F0000 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 13 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 0x0000E000 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK1 8 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1 0x00001F00 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 5 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 0x000000E0 -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD0(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0) -+#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0 -+#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0x0000001F -+#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_0 (0x00002590) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_1 (0x000025a0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_2 (0x000025b0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_3 (0x000025c0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_4 (0x000025d0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_5 (0x000025e0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_6 (0x000025f0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT0_7 (0x00002600) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_0 (0x00002610) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_1 (0x00002620) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_2 (0x00002630) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_3 (0x00002640) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_4 (0x00002650) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_5 (0x00002660) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_6 (0x00002670) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT1_7 (0x00002680) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_0 (0x00002690) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_1 (0x000026a0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_2 (0x000026b0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_3 (0x000026c0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_4 (0x000026d0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_5 (0x000026e0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_6 (0x000026f0) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT2_7 (0x00002700) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_0 (0x00002710) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_1 (0x00002720) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_2 (0x00002730) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_3 (0x00002740) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_4 (0x00002750) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_5 (0x00002760) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_6 (0x00002770) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_OUT3_7 (0x00002780) -+ -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255 0x80000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(v) \ -+ (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254 0x40000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(v) \ -+ (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253 0x20000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(v) \ -+ (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252 0x10000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(v) \ -+ (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251 0x08000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(v) \ -+ (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250 0x04000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(v) \ -+ (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249 0x02000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(v) \ -+ (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248 0x01000000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247 0x00800000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(v) \ -+ (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246 0x00400000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(v) \ -+ (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245 0x00200000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(v) \ -+ (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244 0x00100000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(v) \ -+ (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243 0x00080000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(v) \ -+ (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242 0x00040000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(v) \ -+ (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241 0x00020000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(v) \ -+ (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240 0x00010000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239 0x00008000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(v) \ -+ (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238 0x00004000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(v) \ -+ (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237 0x00002000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(v) \ -+ (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236 0x00001000 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(v) \ -+ (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235 0x00000800 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(v) \ -+ (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234 0x00000400 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(v) \ -+ (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233 0x00000200 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(v) \ -+ (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232 0x00000100 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231 0x00000080 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(v) \ -+ (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230 0x00000040 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(v) \ -+ (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229 0x00000020 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(v) \ -+ (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228 0x00000010 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(v) \ -+ (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227 0x00000008 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(v) \ -+ (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226 0x00000004 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(v) \ -+ (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225 0x00000002 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(v) \ -+ (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225) -+#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224 0x00000001 -+#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224) -+ -+#define HW_PXP_WFE_B_STG3_F8X1_MASKS (0x00002790) -+ -+#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 24 -+#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 0xFF000000 -+#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK3(v) \ -+ (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3) -+#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 16 -+#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 0x00FF0000 -+#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK2(v) \ -+ (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2) -+#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 8 -+#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 0x0000FF00 -+#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK1(v) \ -+ (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1) -+#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0 -+#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0x000000FF -+#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK0(v) \ -+ (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0) -+ -+#define HW_PXP_ALU_A_CTRL (0x00002810) -+#define HW_PXP_ALU_A_CTRL_SET (0x00002814) -+#define HW_PXP_ALU_A_CTRL_CLR (0x00002818) -+#define HW_PXP_ALU_A_CTRL_TOG (0x0000281c) -+ -+#define BP_PXP_ALU_A_CTRL_RSVD0 29 -+#define BM_PXP_ALU_A_CTRL_RSVD0 0xE0000000 -+#define BF_PXP_ALU_A_CTRL_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_ALU_A_CTRL_RSVD0) -+#define BM_PXP_ALU_A_CTRL_DONE 0x10000000 -+#define BF_PXP_ALU_A_CTRL_DONE(v) \ -+ (((v) << 28) & BM_PXP_ALU_A_CTRL_DONE) -+#define BP_PXP_ALU_A_CTRL_RSVD1 21 -+#define BM_PXP_ALU_A_CTRL_RSVD1 0x0FE00000 -+#define BF_PXP_ALU_A_CTRL_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_ALU_A_CTRL_RSVD1) -+#define BM_PXP_ALU_A_CTRL_DONE_IRQ_EN 0x00100000 -+#define BF_PXP_ALU_A_CTRL_DONE_IRQ_EN(v) \ -+ (((v) << 20) & BM_PXP_ALU_A_CTRL_DONE_IRQ_EN) -+#define BP_PXP_ALU_A_CTRL_RSVD2 17 -+#define BM_PXP_ALU_A_CTRL_RSVD2 0x000E0000 -+#define BF_PXP_ALU_A_CTRL_RSVD2(v) \ -+ (((v) << 17) & BM_PXP_ALU_A_CTRL_RSVD2) -+#define BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG 0x00010000 -+#define BF_PXP_ALU_A_CTRL_DONE_IRQ_FLAG(v) \ -+ (((v) << 16) & BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG) -+#define BP_PXP_ALU_A_CTRL_RSVD3 13 -+#define BM_PXP_ALU_A_CTRL_RSVD3 0x0000E000 -+#define BF_PXP_ALU_A_CTRL_RSVD3(v) \ -+ (((v) << 13) & BM_PXP_ALU_A_CTRL_RSVD3) -+#define BM_PXP_ALU_A_CTRL_BYPASS 0x00001000 -+#define BF_PXP_ALU_A_CTRL_BYPASS(v) \ -+ (((v) << 12) & BM_PXP_ALU_A_CTRL_BYPASS) -+#define BV_PXP_ALU_A_CTRL_BYPASS__0 0x0 -+#define BV_PXP_ALU_A_CTRL_BYPASS__1 0x1 -+#define BP_PXP_ALU_A_CTRL_RSVD4 9 -+#define BM_PXP_ALU_A_CTRL_RSVD4 0x00000E00 -+#define BF_PXP_ALU_A_CTRL_RSVD4(v) \ -+ (((v) << 9) & BM_PXP_ALU_A_CTRL_RSVD4) -+#define BM_PXP_ALU_A_CTRL_SW_RESET 0x00000100 -+#define BF_PXP_ALU_A_CTRL_SW_RESET(v) \ -+ (((v) << 8) & BM_PXP_ALU_A_CTRL_SW_RESET) -+#define BP_PXP_ALU_A_CTRL_RSVD5 5 -+#define BM_PXP_ALU_A_CTRL_RSVD5 0x000000E0 -+#define BF_PXP_ALU_A_CTRL_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_ALU_A_CTRL_RSVD5) -+#define BM_PXP_ALU_A_CTRL_START 0x00000010 -+#define BF_PXP_ALU_A_CTRL_START(v) \ -+ (((v) << 4) & BM_PXP_ALU_A_CTRL_START) -+#define BP_PXP_ALU_A_CTRL_RSVD6 1 -+#define BM_PXP_ALU_A_CTRL_RSVD6 0x0000000E -+#define BF_PXP_ALU_A_CTRL_RSVD6(v) \ -+ (((v) << 1) & BM_PXP_ALU_A_CTRL_RSVD6) -+#define BM_PXP_ALU_A_CTRL_ENABLE 0x00000001 -+#define BF_PXP_ALU_A_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_ALU_A_CTRL_ENABLE) -+#define BV_PXP_ALU_A_CTRL_ENABLE__0 0x0 -+#define BV_PXP_ALU_A_CTRL_ENABLE__1 0x1 -+ -+#define HW_PXP_ALU_A_BUF_SIZE (0x00002820) -+ -+#define BP_PXP_ALU_A_BUF_SIZE_RSVD0 28 -+#define BM_PXP_ALU_A_BUF_SIZE_RSVD0 0xF0000000 -+#define BF_PXP_ALU_A_BUF_SIZE_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_ALU_A_BUF_SIZE_RSVD0) -+#define BP_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 16 -+#define BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 -+#define BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT) -+#define BP_PXP_ALU_A_BUF_SIZE_RSVD1 12 -+#define BM_PXP_ALU_A_BUF_SIZE_RSVD1 0x0000F000 -+#define BF_PXP_ALU_A_BUF_SIZE_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_ALU_A_BUF_SIZE_RSVD1) -+#define BP_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0 -+#define BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0x00000FFF -+#define BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH) -+ -+#define HW_PXP_ALU_A_INST_ENTRY (0x00002830) -+ -+#define BP_PXP_ALU_A_INST_ENTRY_RSVD0 16 -+#define BM_PXP_ALU_A_INST_ENTRY_RSVD0 0xFFFF0000 -+#define BF_PXP_ALU_A_INST_ENTRY_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_ALU_A_INST_ENTRY_RSVD0) -+#define BP_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0 -+#define BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0x0000FFFF -+#define BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(v) \ -+ (((v) << 0) & BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR) -+ -+#define HW_PXP_ALU_A_PARAM (0x00002840) -+ -+#define BP_PXP_ALU_A_PARAM_RSVD0 16 -+#define BM_PXP_ALU_A_PARAM_RSVD0 0xFFFF0000 -+#define BF_PXP_ALU_A_PARAM_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_ALU_A_PARAM_RSVD0) -+#define BP_PXP_ALU_A_PARAM_PARAM1 8 -+#define BM_PXP_ALU_A_PARAM_PARAM1 0x0000FF00 -+#define BF_PXP_ALU_A_PARAM_PARAM1(v) \ -+ (((v) << 8) & BM_PXP_ALU_A_PARAM_PARAM1) -+#define BP_PXP_ALU_A_PARAM_PARAM0 0 -+#define BM_PXP_ALU_A_PARAM_PARAM0 0x000000FF -+#define BF_PXP_ALU_A_PARAM_PARAM0(v) \ -+ (((v) << 0) & BM_PXP_ALU_A_PARAM_PARAM0) -+ -+#define HW_PXP_ALU_A_CONFIG (0x00002850) -+ -+#define BP_PXP_ALU_A_CONFIG_BUF_ADDR 0 -+#define BM_PXP_ALU_A_CONFIG_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_ALU_A_CONFIG_BUF_ADDR(v) (v) -+ -+#define HW_PXP_ALU_A_LUT_CONFIG (0x00002860) -+#define HW_PXP_ALU_A_LUT_CONFIG_SET (0x00002864) -+#define HW_PXP_ALU_A_LUT_CONFIG_CLR (0x00002868) -+#define HW_PXP_ALU_A_LUT_CONFIG_TOG (0x0000286c) -+ -+#define BP_PXP_ALU_A_LUT_CONFIG_RSVD0 6 -+#define BM_PXP_ALU_A_LUT_CONFIG_RSVD0 0xFFFFFFC0 -+#define BF_PXP_ALU_A_LUT_CONFIG_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_ALU_A_LUT_CONFIG_RSVD0) -+#define BP_PXP_ALU_A_LUT_CONFIG_MODE 4 -+#define BM_PXP_ALU_A_LUT_CONFIG_MODE 0x00000030 -+#define BF_PXP_ALU_A_LUT_CONFIG_MODE(v) \ -+ (((v) << 4) & BM_PXP_ALU_A_LUT_CONFIG_MODE) -+#define BV_PXP_ALU_A_LUT_CONFIG_MODE__0 0x0 -+#define BV_PXP_ALU_A_LUT_CONFIG_MODE__1 0x1 -+#define BV_PXP_ALU_A_LUT_CONFIG_MODE__2 0x2 -+#define BV_PXP_ALU_A_LUT_CONFIG_MODE__3 0x3 -+#define BP_PXP_ALU_A_LUT_CONFIG_RSVD1 1 -+#define BM_PXP_ALU_A_LUT_CONFIG_RSVD1 0x0000000E -+#define BF_PXP_ALU_A_LUT_CONFIG_RSVD1(v) \ -+ (((v) << 1) & BM_PXP_ALU_A_LUT_CONFIG_RSVD1) -+#define BM_PXP_ALU_A_LUT_CONFIG_EN 0x00000001 -+#define BF_PXP_ALU_A_LUT_CONFIG_EN(v) \ -+ (((v) << 0) & BM_PXP_ALU_A_LUT_CONFIG_EN) -+ -+#define HW_PXP_ALU_A_LUT_DATA0 (0x00002870) -+ -+#define BP_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0 -+#define BM_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF -+#define BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(v) (v) -+ -+#define HW_PXP_ALU_A_LUT_DATA1 (0x00002880) -+ -+#define BP_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0 -+#define BM_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF -+#define BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(v) (v) -+ -+#define HW_PXP_ALU_A_DBG (0x00002890) -+ -+#define BP_PXP_ALU_A_DBG_DEBUG_SEL 24 -+#define BM_PXP_ALU_A_DBG_DEBUG_SEL 0xFF000000 -+#define BF_PXP_ALU_A_DBG_DEBUG_SEL(v) \ -+ (((v) << 24) & BM_PXP_ALU_A_DBG_DEBUG_SEL) -+#define BP_PXP_ALU_A_DBG_DEBUG_VALUE 0 -+#define BM_PXP_ALU_A_DBG_DEBUG_VALUE 0x00FFFFFF -+#define BF_PXP_ALU_A_DBG_DEBUG_VALUE(v) \ -+ (((v) << 0) & BM_PXP_ALU_A_DBG_DEBUG_VALUE) -+ -+#define HW_PXP_ALU_B_CTRL (0x000028a0) -+#define HW_PXP_ALU_B_CTRL_SET (0x000028a4) -+#define HW_PXP_ALU_B_CTRL_CLR (0x000028a8) -+#define HW_PXP_ALU_B_CTRL_TOG (0x000028ac) -+ -+#define BP_PXP_ALU_B_CTRL_RSVD0 29 -+#define BM_PXP_ALU_B_CTRL_RSVD0 0xE0000000 -+#define BF_PXP_ALU_B_CTRL_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_ALU_B_CTRL_RSVD0) -+#define BM_PXP_ALU_B_CTRL_DONE 0x10000000 -+#define BF_PXP_ALU_B_CTRL_DONE(v) \ -+ (((v) << 28) & BM_PXP_ALU_B_CTRL_DONE) -+#define BP_PXP_ALU_B_CTRL_RSVD1 21 -+#define BM_PXP_ALU_B_CTRL_RSVD1 0x0FE00000 -+#define BF_PXP_ALU_B_CTRL_RSVD1(v) \ -+ (((v) << 21) & BM_PXP_ALU_B_CTRL_RSVD1) -+#define BM_PXP_ALU_B_CTRL_DONE_IRQ_EN 0x00100000 -+#define BF_PXP_ALU_B_CTRL_DONE_IRQ_EN(v) \ -+ (((v) << 20) & BM_PXP_ALU_B_CTRL_DONE_IRQ_EN) -+#define BP_PXP_ALU_B_CTRL_RSVD2 17 -+#define BM_PXP_ALU_B_CTRL_RSVD2 0x000E0000 -+#define BF_PXP_ALU_B_CTRL_RSVD2(v) \ -+ (((v) << 17) & BM_PXP_ALU_B_CTRL_RSVD2) -+#define BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG 0x00010000 -+#define BF_PXP_ALU_B_CTRL_DONE_IRQ_FLAG(v) \ -+ (((v) << 16) & BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG) -+#define BP_PXP_ALU_B_CTRL_RSVD3 13 -+#define BM_PXP_ALU_B_CTRL_RSVD3 0x0000E000 -+#define BF_PXP_ALU_B_CTRL_RSVD3(v) \ -+ (((v) << 13) & BM_PXP_ALU_B_CTRL_RSVD3) -+#define BM_PXP_ALU_B_CTRL_BYPASS 0x00001000 -+#define BF_PXP_ALU_B_CTRL_BYPASS(v) \ -+ (((v) << 12) & BM_PXP_ALU_B_CTRL_BYPASS) -+#define BV_PXP_ALU_B_CTRL_BYPASS__0 0x0 -+#define BV_PXP_ALU_B_CTRL_BYPASS__1 0x1 -+#define BP_PXP_ALU_B_CTRL_RSVD4 9 -+#define BM_PXP_ALU_B_CTRL_RSVD4 0x00000E00 -+#define BF_PXP_ALU_B_CTRL_RSVD4(v) \ -+ (((v) << 9) & BM_PXP_ALU_B_CTRL_RSVD4) -+#define BM_PXP_ALU_B_CTRL_SW_RESET 0x00000100 -+#define BF_PXP_ALU_B_CTRL_SW_RESET(v) \ -+ (((v) << 8) & BM_PXP_ALU_B_CTRL_SW_RESET) -+#define BP_PXP_ALU_B_CTRL_RSVD5 5 -+#define BM_PXP_ALU_B_CTRL_RSVD5 0x000000E0 -+#define BF_PXP_ALU_B_CTRL_RSVD5(v) \ -+ (((v) << 5) & BM_PXP_ALU_B_CTRL_RSVD5) -+#define BM_PXP_ALU_B_CTRL_START 0x00000010 -+#define BF_PXP_ALU_B_CTRL_START(v) \ -+ (((v) << 4) & BM_PXP_ALU_B_CTRL_START) -+#define BP_PXP_ALU_B_CTRL_RSVD6 1 -+#define BM_PXP_ALU_B_CTRL_RSVD6 0x0000000E -+#define BF_PXP_ALU_B_CTRL_RSVD6(v) \ -+ (((v) << 1) & BM_PXP_ALU_B_CTRL_RSVD6) -+#define BM_PXP_ALU_B_CTRL_ENABLE 0x00000001 -+#define BF_PXP_ALU_B_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_ALU_B_CTRL_ENABLE) -+#define BV_PXP_ALU_B_CTRL_ENABLE__0 0x0 -+#define BV_PXP_ALU_B_CTRL_ENABLE__1 0x1 -+ -+#define HW_PXP_ALU_B_BUF_SIZE (0x000028b0) -+ -+#define BP_PXP_ALU_B_BUF_SIZE_RSVD0 28 -+#define BM_PXP_ALU_B_BUF_SIZE_RSVD0 0xF0000000 -+#define BF_PXP_ALU_B_BUF_SIZE_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_ALU_B_BUF_SIZE_RSVD0) -+#define BP_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 16 -+#define BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 -+#define BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT) -+#define BP_PXP_ALU_B_BUF_SIZE_RSVD1 12 -+#define BM_PXP_ALU_B_BUF_SIZE_RSVD1 0x0000F000 -+#define BF_PXP_ALU_B_BUF_SIZE_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_ALU_B_BUF_SIZE_RSVD1) -+#define BP_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0 -+#define BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0x00000FFF -+#define BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH) -+ -+#define HW_PXP_ALU_B_INST_ENTRY (0x000028c0) -+ -+#define BP_PXP_ALU_B_INST_ENTRY_RSVD0 16 -+#define BM_PXP_ALU_B_INST_ENTRY_RSVD0 0xFFFF0000 -+#define BF_PXP_ALU_B_INST_ENTRY_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_ALU_B_INST_ENTRY_RSVD0) -+#define BP_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0 -+#define BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0x0000FFFF -+#define BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(v) \ -+ (((v) << 0) & BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR) -+ -+#define HW_PXP_ALU_B_PARAM (0x000028d0) -+ -+#define BP_PXP_ALU_B_PARAM_RSVD0 16 -+#define BM_PXP_ALU_B_PARAM_RSVD0 0xFFFF0000 -+#define BF_PXP_ALU_B_PARAM_RSVD0(v) \ -+ (((v) << 16) & BM_PXP_ALU_B_PARAM_RSVD0) -+#define BP_PXP_ALU_B_PARAM_PARAM1 8 -+#define BM_PXP_ALU_B_PARAM_PARAM1 0x0000FF00 -+#define BF_PXP_ALU_B_PARAM_PARAM1(v) \ -+ (((v) << 8) & BM_PXP_ALU_B_PARAM_PARAM1) -+#define BP_PXP_ALU_B_PARAM_PARAM0 0 -+#define BM_PXP_ALU_B_PARAM_PARAM0 0x000000FF -+#define BF_PXP_ALU_B_PARAM_PARAM0(v) \ -+ (((v) << 0) & BM_PXP_ALU_B_PARAM_PARAM0) -+ -+#define HW_PXP_ALU_B_CONFIG (0x000028e0) -+ -+#define BP_PXP_ALU_B_CONFIG_BUF_ADDR 0 -+#define BM_PXP_ALU_B_CONFIG_BUF_ADDR 0xFFFFFFFF -+#define BF_PXP_ALU_B_CONFIG_BUF_ADDR(v) (v) -+ -+#define HW_PXP_ALU_B_LUT_CONFIG (0x000028f0) -+#define HW_PXP_ALU_B_LUT_CONFIG_SET (0x000028f4) -+#define HW_PXP_ALU_B_LUT_CONFIG_CLR (0x000028f8) -+#define HW_PXP_ALU_B_LUT_CONFIG_TOG (0x000028fc) -+ -+#define BP_PXP_ALU_B_LUT_CONFIG_RSVD0 6 -+#define BM_PXP_ALU_B_LUT_CONFIG_RSVD0 0xFFFFFFC0 -+#define BF_PXP_ALU_B_LUT_CONFIG_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_ALU_B_LUT_CONFIG_RSVD0) -+#define BP_PXP_ALU_B_LUT_CONFIG_MODE 4 -+#define BM_PXP_ALU_B_LUT_CONFIG_MODE 0x00000030 -+#define BF_PXP_ALU_B_LUT_CONFIG_MODE(v) \ -+ (((v) << 4) & BM_PXP_ALU_B_LUT_CONFIG_MODE) -+#define BV_PXP_ALU_B_LUT_CONFIG_MODE__0 0x0 -+#define BV_PXP_ALU_B_LUT_CONFIG_MODE__1 0x1 -+#define BV_PXP_ALU_B_LUT_CONFIG_MODE__2 0x2 -+#define BV_PXP_ALU_B_LUT_CONFIG_MODE__3 0x3 -+#define BP_PXP_ALU_B_LUT_CONFIG_RSVD1 1 -+#define BM_PXP_ALU_B_LUT_CONFIG_RSVD1 0x0000000E -+#define BF_PXP_ALU_B_LUT_CONFIG_RSVD1(v) \ -+ (((v) << 1) & BM_PXP_ALU_B_LUT_CONFIG_RSVD1) -+#define BM_PXP_ALU_B_LUT_CONFIG_EN 0x00000001 -+#define BF_PXP_ALU_B_LUT_CONFIG_EN(v) \ -+ (((v) << 0) & BM_PXP_ALU_B_LUT_CONFIG_EN) -+ -+#define HW_PXP_ALU_B_LUT_DATA0 (0x00002900) -+ -+#define BP_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0 -+#define BM_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF -+#define BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(v) (v) -+ -+#define HW_PXP_ALU_B_LUT_DATA1 (0x00002910) -+ -+#define BP_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0 -+#define BM_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF -+#define BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(v) (v) -+ -+#define HW_PXP_ALU_B_DBG (0x00002920) -+ -+#define BP_PXP_ALU_B_DBG_DEBUG_SEL 24 -+#define BM_PXP_ALU_B_DBG_DEBUG_SEL 0xFF000000 -+#define BF_PXP_ALU_B_DBG_DEBUG_SEL(v) \ -+ (((v) << 24) & BM_PXP_ALU_B_DBG_DEBUG_SEL) -+#define BP_PXP_ALU_B_DBG_DEBUG_VALUE 0 -+#define BM_PXP_ALU_B_DBG_DEBUG_VALUE 0x00FFFFFF -+#define BF_PXP_ALU_B_DBG_DEBUG_VALUE(v) \ -+ (((v) << 0) & BM_PXP_ALU_B_DBG_DEBUG_VALUE) -+ -+#define HW_PXP_HIST_A_CTRL (0x00002a00) -+ -+#define BP_PXP_HIST_A_CTRL_RSVD4 27 -+#define BM_PXP_HIST_A_CTRL_RSVD4 0xF8000000 -+#define BF_PXP_HIST_A_CTRL_RSVD4(v) \ -+ (((v) << 27) & BM_PXP_HIST_A_CTRL_RSVD4) -+#define BP_PXP_HIST_A_CTRL_PIXEL_WIDTH 24 -+#define BM_PXP_HIST_A_CTRL_PIXEL_WIDTH 0x07000000 -+#define BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(v) \ -+ (((v) << 24) & BM_PXP_HIST_A_CTRL_PIXEL_WIDTH) -+#define BM_PXP_HIST_A_CTRL_RSVD3 0x00800000 -+#define BF_PXP_HIST_A_CTRL_RSVD3(v) \ -+ (((v) << 23) & BM_PXP_HIST_A_CTRL_RSVD3) -+#define BP_PXP_HIST_A_CTRL_PIXEL_OFFSET 16 -+#define BM_PXP_HIST_A_CTRL_PIXEL_OFFSET 0x007F0000 -+#define BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_HIST_A_CTRL_PIXEL_OFFSET) -+#define BP_PXP_HIST_A_CTRL_RSVD2 13 -+#define BM_PXP_HIST_A_CTRL_RSVD2 0x0000E000 -+#define BF_PXP_HIST_A_CTRL_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_HIST_A_CTRL_RSVD2) -+#define BP_PXP_HIST_A_CTRL_STATUS 8 -+#define BM_PXP_HIST_A_CTRL_STATUS 0x00001F00 -+#define BF_PXP_HIST_A_CTRL_STATUS(v) \ -+ (((v) << 8) & BM_PXP_HIST_A_CTRL_STATUS) -+#define BP_PXP_HIST_A_CTRL_RSVD1 5 -+#define BM_PXP_HIST_A_CTRL_RSVD1 0x000000E0 -+#define BF_PXP_HIST_A_CTRL_RSVD1(v) \ -+ (((v) << 5) & BM_PXP_HIST_A_CTRL_RSVD1) -+#define BM_PXP_HIST_A_CTRL_CLEAR 0x00000010 -+#define BF_PXP_HIST_A_CTRL_CLEAR(v) \ -+ (((v) << 4) & BM_PXP_HIST_A_CTRL_CLEAR) -+#define BP_PXP_HIST_A_CTRL_RSVD0 1 -+#define BM_PXP_HIST_A_CTRL_RSVD0 0x0000000E -+#define BF_PXP_HIST_A_CTRL_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_HIST_A_CTRL_RSVD0) -+#define BM_PXP_HIST_A_CTRL_ENABLE 0x00000001 -+#define BF_PXP_HIST_A_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_HIST_A_CTRL_ENABLE) -+ -+#define HW_PXP_HIST_A_MASK (0x00002a10) -+ -+#define BP_PXP_HIST_A_MASK_MASK_VALUE1 24 -+#define BM_PXP_HIST_A_MASK_MASK_VALUE1 0xFF000000 -+#define BF_PXP_HIST_A_MASK_MASK_VALUE1(v) \ -+ (((v) << 24) & BM_PXP_HIST_A_MASK_MASK_VALUE1) -+#define BP_PXP_HIST_A_MASK_MASK_VALUE0 16 -+#define BM_PXP_HIST_A_MASK_MASK_VALUE0 0x00FF0000 -+#define BF_PXP_HIST_A_MASK_MASK_VALUE0(v) \ -+ (((v) << 16) & BM_PXP_HIST_A_MASK_MASK_VALUE0) -+#define BP_PXP_HIST_A_MASK_MASK_WIDTH 13 -+#define BM_PXP_HIST_A_MASK_MASK_WIDTH 0x0000E000 -+#define BF_PXP_HIST_A_MASK_MASK_WIDTH(v) \ -+ (((v) << 13) & BM_PXP_HIST_A_MASK_MASK_WIDTH) -+#define BP_PXP_HIST_A_MASK_MASK_OFFSET 6 -+#define BM_PXP_HIST_A_MASK_MASK_OFFSET 0x00001FC0 -+#define BF_PXP_HIST_A_MASK_MASK_OFFSET(v) \ -+ (((v) << 6) & BM_PXP_HIST_A_MASK_MASK_OFFSET) -+#define BP_PXP_HIST_A_MASK_MASK_MODE 4 -+#define BM_PXP_HIST_A_MASK_MASK_MODE 0x00000030 -+#define BF_PXP_HIST_A_MASK_MASK_MODE(v) \ -+ (((v) << 4) & BM_PXP_HIST_A_MASK_MASK_MODE) -+#define BV_PXP_HIST_A_MASK_MASK_MODE__EQUAL 0x0 -+#define BV_PXP_HIST_A_MASK_MASK_MODE__NOT_EQUAL 0x1 -+#define BV_PXP_HIST_A_MASK_MASK_MODE__INSIDE 0x2 -+#define BV_PXP_HIST_A_MASK_MASK_MODE__OUTSIDE 0x3 -+#define BP_PXP_HIST_A_MASK_RSVD0 1 -+#define BM_PXP_HIST_A_MASK_RSVD0 0x0000000E -+#define BF_PXP_HIST_A_MASK_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_HIST_A_MASK_RSVD0) -+#define BM_PXP_HIST_A_MASK_MASK_EN 0x00000001 -+#define BF_PXP_HIST_A_MASK_MASK_EN(v) \ -+ (((v) << 0) & BM_PXP_HIST_A_MASK_MASK_EN) -+ -+#define HW_PXP_HIST_A_BUF_SIZE (0x00002a20) -+ -+#define BP_PXP_HIST_A_BUF_SIZE_RSVD0 28 -+#define BM_PXP_HIST_A_BUF_SIZE_RSVD0 0xF0000000 -+#define BF_PXP_HIST_A_BUF_SIZE_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_HIST_A_BUF_SIZE_RSVD0) -+#define BP_PXP_HIST_A_BUF_SIZE_HEIGHT 16 -+#define BM_PXP_HIST_A_BUF_SIZE_HEIGHT 0x0FFF0000 -+#define BF_PXP_HIST_A_BUF_SIZE_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_HIST_A_BUF_SIZE_HEIGHT) -+#define BP_PXP_HIST_A_BUF_SIZE_RSVD1 12 -+#define BM_PXP_HIST_A_BUF_SIZE_RSVD1 0x0000F000 -+#define BF_PXP_HIST_A_BUF_SIZE_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_HIST_A_BUF_SIZE_RSVD1) -+#define BP_PXP_HIST_A_BUF_SIZE_WIDTH 0 -+#define BM_PXP_HIST_A_BUF_SIZE_WIDTH 0x00000FFF -+#define BF_PXP_HIST_A_BUF_SIZE_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_HIST_A_BUF_SIZE_WIDTH) -+ -+#define HW_PXP_HIST_A_TOTAL_PIXEL (0x00002a30) -+ -+#define BP_PXP_HIST_A_TOTAL_PIXEL_RSVD0 24 -+#define BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0 0xFF000000 -+#define BF_PXP_HIST_A_TOTAL_PIXEL_RSVD0(v) \ -+ (((v) << 24) & BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0) -+#define BP_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0 -+#define BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF -+#define BF_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL) -+ -+#define HW_PXP_HIST_A_ACTIVE_AREA_X (0x00002a40) -+ -+#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 28 -+#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 0xF0000000 -+#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(v) \ -+ (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1) -+#define BP_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 16 -+#define BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 -+#define BF_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET) -+#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 12 -+#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 0x0000F000 -+#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(v) \ -+ (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0) -+#define BP_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0 -+#define BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF -+#define BF_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET) -+ -+#define HW_PXP_HIST_A_ACTIVE_AREA_Y (0x00002a50) -+ -+#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 28 -+#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 0xF0000000 -+#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(v) \ -+ (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1) -+#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 -+#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 -+#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET) -+#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 12 -+#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 0x0000F000 -+#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(v) \ -+ (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0) -+#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 -+#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF -+#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET) -+ -+#define HW_PXP_HIST_A_RAW_STAT0 (0x00002a60) -+ -+#define BP_PXP_HIST_A_RAW_STAT0_STAT0 0 -+#define BM_PXP_HIST_A_RAW_STAT0_STAT0 0xFFFFFFFF -+#define BF_PXP_HIST_A_RAW_STAT0_STAT0(v) (v) -+ -+#define HW_PXP_HIST_A_RAW_STAT1 (0x00002a70) -+ -+#define BP_PXP_HIST_A_RAW_STAT1_STAT1 0 -+#define BM_PXP_HIST_A_RAW_STAT1_STAT1 0xFFFFFFFF -+#define BF_PXP_HIST_A_RAW_STAT1_STAT1(v) (v) -+ -+#define HW_PXP_HIST_B_CTRL (0x00002a80) -+ -+#define BP_PXP_HIST_B_CTRL_RSVD4 27 -+#define BM_PXP_HIST_B_CTRL_RSVD4 0xF8000000 -+#define BF_PXP_HIST_B_CTRL_RSVD4(v) \ -+ (((v) << 27) & BM_PXP_HIST_B_CTRL_RSVD4) -+#define BP_PXP_HIST_B_CTRL_PIXEL_WIDTH 24 -+#define BM_PXP_HIST_B_CTRL_PIXEL_WIDTH 0x07000000 -+#define BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(v) \ -+ (((v) << 24) & BM_PXP_HIST_B_CTRL_PIXEL_WIDTH) -+#define BM_PXP_HIST_B_CTRL_RSVD3 0x00800000 -+#define BF_PXP_HIST_B_CTRL_RSVD3(v) \ -+ (((v) << 23) & BM_PXP_HIST_B_CTRL_RSVD3) -+#define BP_PXP_HIST_B_CTRL_PIXEL_OFFSET 16 -+#define BM_PXP_HIST_B_CTRL_PIXEL_OFFSET 0x007F0000 -+#define BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_HIST_B_CTRL_PIXEL_OFFSET) -+#define BP_PXP_HIST_B_CTRL_RSVD2 13 -+#define BM_PXP_HIST_B_CTRL_RSVD2 0x0000E000 -+#define BF_PXP_HIST_B_CTRL_RSVD2(v) \ -+ (((v) << 13) & BM_PXP_HIST_B_CTRL_RSVD2) -+#define BP_PXP_HIST_B_CTRL_STATUS 8 -+#define BM_PXP_HIST_B_CTRL_STATUS 0x00001F00 -+#define BF_PXP_HIST_B_CTRL_STATUS(v) \ -+ (((v) << 8) & BM_PXP_HIST_B_CTRL_STATUS) -+#define BP_PXP_HIST_B_CTRL_RSVD1 5 -+#define BM_PXP_HIST_B_CTRL_RSVD1 0x000000E0 -+#define BF_PXP_HIST_B_CTRL_RSVD1(v) \ -+ (((v) << 5) & BM_PXP_HIST_B_CTRL_RSVD1) -+#define BM_PXP_HIST_B_CTRL_CLEAR 0x00000010 -+#define BF_PXP_HIST_B_CTRL_CLEAR(v) \ -+ (((v) << 4) & BM_PXP_HIST_B_CTRL_CLEAR) -+#define BP_PXP_HIST_B_CTRL_RSVD0 1 -+#define BM_PXP_HIST_B_CTRL_RSVD0 0x0000000E -+#define BF_PXP_HIST_B_CTRL_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_HIST_B_CTRL_RSVD0) -+#define BM_PXP_HIST_B_CTRL_ENABLE 0x00000001 -+#define BF_PXP_HIST_B_CTRL_ENABLE(v) \ -+ (((v) << 0) & BM_PXP_HIST_B_CTRL_ENABLE) -+ -+#define HW_PXP_HIST_B_MASK (0x00002a90) -+ -+#define BP_PXP_HIST_B_MASK_MASK_VALUE1 24 -+#define BM_PXP_HIST_B_MASK_MASK_VALUE1 0xFF000000 -+#define BF_PXP_HIST_B_MASK_MASK_VALUE1(v) \ -+ (((v) << 24) & BM_PXP_HIST_B_MASK_MASK_VALUE1) -+#define BP_PXP_HIST_B_MASK_MASK_VALUE0 16 -+#define BM_PXP_HIST_B_MASK_MASK_VALUE0 0x00FF0000 -+#define BF_PXP_HIST_B_MASK_MASK_VALUE0(v) \ -+ (((v) << 16) & BM_PXP_HIST_B_MASK_MASK_VALUE0) -+#define BP_PXP_HIST_B_MASK_MASK_WIDTH 13 -+#define BM_PXP_HIST_B_MASK_MASK_WIDTH 0x0000E000 -+#define BF_PXP_HIST_B_MASK_MASK_WIDTH(v) \ -+ (((v) << 13) & BM_PXP_HIST_B_MASK_MASK_WIDTH) -+#define BP_PXP_HIST_B_MASK_MASK_OFFSET 6 -+#define BM_PXP_HIST_B_MASK_MASK_OFFSET 0x00001FC0 -+#define BF_PXP_HIST_B_MASK_MASK_OFFSET(v) \ -+ (((v) << 6) & BM_PXP_HIST_B_MASK_MASK_OFFSET) -+#define BP_PXP_HIST_B_MASK_MASK_MODE 4 -+#define BM_PXP_HIST_B_MASK_MASK_MODE 0x00000030 -+#define BF_PXP_HIST_B_MASK_MASK_MODE(v) \ -+ (((v) << 4) & BM_PXP_HIST_B_MASK_MASK_MODE) -+#define BV_PXP_HIST_B_MASK_MASK_MODE__EQUAL 0x0 -+#define BV_PXP_HIST_B_MASK_MASK_MODE__NOT_EQUAL 0x1 -+#define BV_PXP_HIST_B_MASK_MASK_MODE__INSIDE 0x2 -+#define BV_PXP_HIST_B_MASK_MASK_MODE__OUTSIDE 0x3 -+#define BP_PXP_HIST_B_MASK_RSVD0 1 -+#define BM_PXP_HIST_B_MASK_RSVD0 0x0000000E -+#define BF_PXP_HIST_B_MASK_RSVD0(v) \ -+ (((v) << 1) & BM_PXP_HIST_B_MASK_RSVD0) -+#define BM_PXP_HIST_B_MASK_MASK_EN 0x00000001 -+#define BF_PXP_HIST_B_MASK_MASK_EN(v) \ -+ (((v) << 0) & BM_PXP_HIST_B_MASK_MASK_EN) -+ -+#define HW_PXP_HIST_B_BUF_SIZE (0x00002aa0) -+ -+#define BP_PXP_HIST_B_BUF_SIZE_RSVD0 28 -+#define BM_PXP_HIST_B_BUF_SIZE_RSVD0 0xF0000000 -+#define BF_PXP_HIST_B_BUF_SIZE_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_HIST_B_BUF_SIZE_RSVD0) -+#define BP_PXP_HIST_B_BUF_SIZE_HEIGHT 16 -+#define BM_PXP_HIST_B_BUF_SIZE_HEIGHT 0x0FFF0000 -+#define BF_PXP_HIST_B_BUF_SIZE_HEIGHT(v) \ -+ (((v) << 16) & BM_PXP_HIST_B_BUF_SIZE_HEIGHT) -+#define BP_PXP_HIST_B_BUF_SIZE_RSVD1 12 -+#define BM_PXP_HIST_B_BUF_SIZE_RSVD1 0x0000F000 -+#define BF_PXP_HIST_B_BUF_SIZE_RSVD1(v) \ -+ (((v) << 12) & BM_PXP_HIST_B_BUF_SIZE_RSVD1) -+#define BP_PXP_HIST_B_BUF_SIZE_WIDTH 0 -+#define BM_PXP_HIST_B_BUF_SIZE_WIDTH 0x00000FFF -+#define BF_PXP_HIST_B_BUF_SIZE_WIDTH(v) \ -+ (((v) << 0) & BM_PXP_HIST_B_BUF_SIZE_WIDTH) -+ -+#define HW_PXP_HIST_B_TOTAL_PIXEL (0x00002ab0) -+ -+#define BP_PXP_HIST_B_TOTAL_PIXEL_RSVD0 24 -+#define BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0 0xFF000000 -+#define BF_PXP_HIST_B_TOTAL_PIXEL_RSVD0(v) \ -+ (((v) << 24) & BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0) -+#define BP_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0 -+#define BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF -+#define BF_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(v) \ -+ (((v) << 0) & BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL) -+ -+#define HW_PXP_HIST_B_ACTIVE_AREA_X (0x00002ac0) -+ -+#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 28 -+#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 0xF0000000 -+#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(v) \ -+ (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1) -+#define BP_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 16 -+#define BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 -+#define BF_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET) -+#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 12 -+#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 0x0000F000 -+#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(v) \ -+ (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0) -+#define BP_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0 -+#define BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF -+#define BF_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET) -+ -+#define HW_PXP_HIST_B_ACTIVE_AREA_Y (0x00002ad0) -+ -+#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 28 -+#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 0xF0000000 -+#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(v) \ -+ (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1) -+#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 -+#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 -+#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET) -+#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 12 -+#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 0x0000F000 -+#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(v) \ -+ (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0) -+#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 -+#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF -+#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET) -+ -+#define HW_PXP_HIST_B_RAW_STAT0 (0x00002ae0) -+ -+#define BP_PXP_HIST_B_RAW_STAT0_STAT0 0 -+#define BM_PXP_HIST_B_RAW_STAT0_STAT0 0xFFFFFFFF -+#define BF_PXP_HIST_B_RAW_STAT0_STAT0(v) (v) -+ -+#define HW_PXP_HIST_B_RAW_STAT1 (0x00002af0) -+ -+#define BP_PXP_HIST_B_RAW_STAT1_STAT1 0 -+#define BM_PXP_HIST_B_RAW_STAT1_STAT1 0xFFFFFFFF -+#define BF_PXP_HIST_B_RAW_STAT1_STAT1(v) (v) -+ -+#define HW_PXP_HIST2_PARAM (0x00002b00) -+ -+#define BP_PXP_HIST2_PARAM_RSVD 16 -+#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 -+#define BF_PXP_HIST2_PARAM_RSVD(v) \ -+ (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) -+#define BP_PXP_HIST2_PARAM_RSVD1 14 -+#define BM_PXP_HIST2_PARAM_RSVD1 0x0000C000 -+#define BF_PXP_HIST2_PARAM_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_HIST2_PARAM_RSVD1) -+#define BP_PXP_HIST2_PARAM_VALUE1 8 -+#define BM_PXP_HIST2_PARAM_VALUE1 0x00003F00 -+#define BF_PXP_HIST2_PARAM_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) -+#define BP_PXP_HIST2_PARAM_RSVD0 6 -+#define BM_PXP_HIST2_PARAM_RSVD0 0x000000C0 -+#define BF_PXP_HIST2_PARAM_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HIST2_PARAM_RSVD0) -+#define BP_PXP_HIST2_PARAM_VALUE0 0 -+#define BM_PXP_HIST2_PARAM_VALUE0 0x0000003F -+#define BF_PXP_HIST2_PARAM_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) -+ -+#define HW_PXP_HIST4_PARAM (0x00002b10) -+ -+#define BP_PXP_HIST4_PARAM_RSVD3 30 -+#define BM_PXP_HIST4_PARAM_RSVD3 0xC0000000 -+#define BF_PXP_HIST4_PARAM_RSVD3(v) \ -+ (((v) << 30) & BM_PXP_HIST4_PARAM_RSVD3) -+#define BP_PXP_HIST4_PARAM_VALUE3 24 -+#define BM_PXP_HIST4_PARAM_VALUE3 0x3F000000 -+#define BF_PXP_HIST4_PARAM_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) -+#define BP_PXP_HIST4_PARAM_RSVD2 22 -+#define BM_PXP_HIST4_PARAM_RSVD2 0x00C00000 -+#define BF_PXP_HIST4_PARAM_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_HIST4_PARAM_RSVD2) -+#define BP_PXP_HIST4_PARAM_VALUE2 16 -+#define BM_PXP_HIST4_PARAM_VALUE2 0x003F0000 -+#define BF_PXP_HIST4_PARAM_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) -+#define BP_PXP_HIST4_PARAM_RSVD1 14 -+#define BM_PXP_HIST4_PARAM_RSVD1 0x0000C000 -+#define BF_PXP_HIST4_PARAM_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_HIST4_PARAM_RSVD1) -+#define BP_PXP_HIST4_PARAM_VALUE1 8 -+#define BM_PXP_HIST4_PARAM_VALUE1 0x00003F00 -+#define BF_PXP_HIST4_PARAM_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) -+#define BP_PXP_HIST4_PARAM_RSVD0 6 -+#define BM_PXP_HIST4_PARAM_RSVD0 0x000000C0 -+#define BF_PXP_HIST4_PARAM_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HIST4_PARAM_RSVD0) -+#define BP_PXP_HIST4_PARAM_VALUE0 0 -+#define BM_PXP_HIST4_PARAM_VALUE0 0x0000003F -+#define BF_PXP_HIST4_PARAM_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) -+ -+#define HW_PXP_HIST8_PARAM0 (0x00002b20) -+ -+#define BP_PXP_HIST8_PARAM0_RSVD3 30 -+#define BM_PXP_HIST8_PARAM0_RSVD3 0xC0000000 -+#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ -+ (((v) << 30) & BM_PXP_HIST8_PARAM0_RSVD3) -+#define BP_PXP_HIST8_PARAM0_VALUE3 24 -+#define BM_PXP_HIST8_PARAM0_VALUE3 0x3F000000 -+#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) -+#define BP_PXP_HIST8_PARAM0_RSVD2 22 -+#define BM_PXP_HIST8_PARAM0_RSVD2 0x00C00000 -+#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_HIST8_PARAM0_RSVD2) -+#define BP_PXP_HIST8_PARAM0_VALUE2 16 -+#define BM_PXP_HIST8_PARAM0_VALUE2 0x003F0000 -+#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) -+#define BP_PXP_HIST8_PARAM0_RSVD1 14 -+#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000C000 -+#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_HIST8_PARAM0_RSVD1) -+#define BP_PXP_HIST8_PARAM0_VALUE1 8 -+#define BM_PXP_HIST8_PARAM0_VALUE1 0x00003F00 -+#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) -+#define BP_PXP_HIST8_PARAM0_RSVD0 6 -+#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000C0 -+#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HIST8_PARAM0_RSVD0) -+#define BP_PXP_HIST8_PARAM0_VALUE0 0 -+#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000003F -+#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) -+ -+#define HW_PXP_HIST8_PARAM1 (0x00002b30) -+ -+#define BP_PXP_HIST8_PARAM1_RSVD7 30 -+#define BM_PXP_HIST8_PARAM1_RSVD7 0xC0000000 -+#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ -+ (((v) << 30) & BM_PXP_HIST8_PARAM1_RSVD7) -+#define BP_PXP_HIST8_PARAM1_VALUE7 24 -+#define BM_PXP_HIST8_PARAM1_VALUE7 0x3F000000 -+#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ -+ (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) -+#define BP_PXP_HIST8_PARAM1_RSVD6 22 -+#define BM_PXP_HIST8_PARAM1_RSVD6 0x00C00000 -+#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ -+ (((v) << 22) & BM_PXP_HIST8_PARAM1_RSVD6) -+#define BP_PXP_HIST8_PARAM1_VALUE6 16 -+#define BM_PXP_HIST8_PARAM1_VALUE6 0x003F0000 -+#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ -+ (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) -+#define BP_PXP_HIST8_PARAM1_RSVD5 14 -+#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000C000 -+#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ -+ (((v) << 14) & BM_PXP_HIST8_PARAM1_RSVD5) -+#define BP_PXP_HIST8_PARAM1_VALUE5 8 -+#define BM_PXP_HIST8_PARAM1_VALUE5 0x00003F00 -+#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ -+ (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) -+#define BP_PXP_HIST8_PARAM1_RSVD4 6 -+#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000C0 -+#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ -+ (((v) << 6) & BM_PXP_HIST8_PARAM1_RSVD4) -+#define BP_PXP_HIST8_PARAM1_VALUE4 0 -+#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000003F -+#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ -+ (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) -+ -+#define HW_PXP_HIST16_PARAM0 (0x00002b40) -+ -+#define BP_PXP_HIST16_PARAM0_RSVD3 30 -+#define BM_PXP_HIST16_PARAM0_RSVD3 0xC0000000 -+#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ -+ (((v) << 30) & BM_PXP_HIST16_PARAM0_RSVD3) -+#define BP_PXP_HIST16_PARAM0_VALUE3 24 -+#define BM_PXP_HIST16_PARAM0_VALUE3 0x3F000000 -+#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) -+#define BP_PXP_HIST16_PARAM0_RSVD2 22 -+#define BM_PXP_HIST16_PARAM0_RSVD2 0x00C00000 -+#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_HIST16_PARAM0_RSVD2) -+#define BP_PXP_HIST16_PARAM0_VALUE2 16 -+#define BM_PXP_HIST16_PARAM0_VALUE2 0x003F0000 -+#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) -+#define BP_PXP_HIST16_PARAM0_RSVD1 14 -+#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000C000 -+#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_HIST16_PARAM0_RSVD1) -+#define BP_PXP_HIST16_PARAM0_VALUE1 8 -+#define BM_PXP_HIST16_PARAM0_VALUE1 0x00003F00 -+#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) -+#define BP_PXP_HIST16_PARAM0_RSVD0 6 -+#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000C0 -+#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HIST16_PARAM0_RSVD0) -+#define BP_PXP_HIST16_PARAM0_VALUE0 0 -+#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000003F -+#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) -+ -+#define HW_PXP_HIST16_PARAM1 (0x00002b50) -+ -+#define BP_PXP_HIST16_PARAM1_RSVD7 30 -+#define BM_PXP_HIST16_PARAM1_RSVD7 0xC0000000 -+#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ -+ (((v) << 30) & BM_PXP_HIST16_PARAM1_RSVD7) -+#define BP_PXP_HIST16_PARAM1_VALUE7 24 -+#define BM_PXP_HIST16_PARAM1_VALUE7 0x3F000000 -+#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) -+#define BP_PXP_HIST16_PARAM1_RSVD6 22 -+#define BM_PXP_HIST16_PARAM1_RSVD6 0x00C00000 -+#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ -+ (((v) << 22) & BM_PXP_HIST16_PARAM1_RSVD6) -+#define BP_PXP_HIST16_PARAM1_VALUE6 16 -+#define BM_PXP_HIST16_PARAM1_VALUE6 0x003F0000 -+#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) -+#define BP_PXP_HIST16_PARAM1_RSVD5 14 -+#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000C000 -+#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ -+ (((v) << 14) & BM_PXP_HIST16_PARAM1_RSVD5) -+#define BP_PXP_HIST16_PARAM1_VALUE5 8 -+#define BM_PXP_HIST16_PARAM1_VALUE5 0x00003F00 -+#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) -+#define BP_PXP_HIST16_PARAM1_RSVD4 6 -+#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000C0 -+#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ -+ (((v) << 6) & BM_PXP_HIST16_PARAM1_RSVD4) -+#define BP_PXP_HIST16_PARAM1_VALUE4 0 -+#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000003F -+#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) -+ -+#define HW_PXP_HIST16_PARAM2 (0x00002b60) -+ -+#define BP_PXP_HIST16_PARAM2_RSVD11 30 -+#define BM_PXP_HIST16_PARAM2_RSVD11 0xC0000000 -+#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ -+ (((v) << 30) & BM_PXP_HIST16_PARAM2_RSVD11) -+#define BP_PXP_HIST16_PARAM2_VALUE11 24 -+#define BM_PXP_HIST16_PARAM2_VALUE11 0x3F000000 -+#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) -+#define BP_PXP_HIST16_PARAM2_RSVD10 22 -+#define BM_PXP_HIST16_PARAM2_RSVD10 0x00C00000 -+#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ -+ (((v) << 22) & BM_PXP_HIST16_PARAM2_RSVD10) -+#define BP_PXP_HIST16_PARAM2_VALUE10 16 -+#define BM_PXP_HIST16_PARAM2_VALUE10 0x003F0000 -+#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) -+#define BP_PXP_HIST16_PARAM2_RSVD9 14 -+#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000C000 -+#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ -+ (((v) << 14) & BM_PXP_HIST16_PARAM2_RSVD9) -+#define BP_PXP_HIST16_PARAM2_VALUE9 8 -+#define BM_PXP_HIST16_PARAM2_VALUE9 0x00003F00 -+#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) -+#define BP_PXP_HIST16_PARAM2_RSVD8 6 -+#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000C0 -+#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ -+ (((v) << 6) & BM_PXP_HIST16_PARAM2_RSVD8) -+#define BP_PXP_HIST16_PARAM2_VALUE8 0 -+#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000003F -+#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) -+ -+#define HW_PXP_HIST16_PARAM3 (0x00002b70) -+ -+#define BP_PXP_HIST16_PARAM3_RSVD15 30 -+#define BM_PXP_HIST16_PARAM3_RSVD15 0xC0000000 -+#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ -+ (((v) << 30) & BM_PXP_HIST16_PARAM3_RSVD15) -+#define BP_PXP_HIST16_PARAM3_VALUE15 24 -+#define BM_PXP_HIST16_PARAM3_VALUE15 0x3F000000 -+#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ -+ (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) -+#define BP_PXP_HIST16_PARAM3_RSVD14 22 -+#define BM_PXP_HIST16_PARAM3_RSVD14 0x00C00000 -+#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ -+ (((v) << 22) & BM_PXP_HIST16_PARAM3_RSVD14) -+#define BP_PXP_HIST16_PARAM3_VALUE14 16 -+#define BM_PXP_HIST16_PARAM3_VALUE14 0x003F0000 -+#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ -+ (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) -+#define BP_PXP_HIST16_PARAM3_RSVD13 14 -+#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000C000 -+#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ -+ (((v) << 14) & BM_PXP_HIST16_PARAM3_RSVD13) -+#define BP_PXP_HIST16_PARAM3_VALUE13 8 -+#define BM_PXP_HIST16_PARAM3_VALUE13 0x00003F00 -+#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ -+ (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) -+#define BP_PXP_HIST16_PARAM3_RSVD12 6 -+#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000C0 -+#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ -+ (((v) << 6) & BM_PXP_HIST16_PARAM3_RSVD12) -+#define BP_PXP_HIST16_PARAM3_VALUE12 0 -+#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000003F -+#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ -+ (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) -+ -+#define HW_PXP_HIST32_PARAM0 (0x00002b80) -+ -+#define BP_PXP_HIST32_PARAM0_RSVD3 30 -+#define BM_PXP_HIST32_PARAM0_RSVD3 0xC0000000 -+#define BF_PXP_HIST32_PARAM0_RSVD3(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM0_RSVD3) -+#define BP_PXP_HIST32_PARAM0_VALUE3 24 -+#define BM_PXP_HIST32_PARAM0_VALUE3 0x3F000000 -+#define BF_PXP_HIST32_PARAM0_VALUE3(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM0_VALUE3) -+#define BP_PXP_HIST32_PARAM0_RSVD2 22 -+#define BM_PXP_HIST32_PARAM0_RSVD2 0x00C00000 -+#define BF_PXP_HIST32_PARAM0_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM0_RSVD2) -+#define BP_PXP_HIST32_PARAM0_VALUE2 16 -+#define BM_PXP_HIST32_PARAM0_VALUE2 0x003F0000 -+#define BF_PXP_HIST32_PARAM0_VALUE2(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM0_VALUE2) -+#define BP_PXP_HIST32_PARAM0_RSVD1 14 -+#define BM_PXP_HIST32_PARAM0_RSVD1 0x0000C000 -+#define BF_PXP_HIST32_PARAM0_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM0_RSVD1) -+#define BP_PXP_HIST32_PARAM0_VALUE1 8 -+#define BM_PXP_HIST32_PARAM0_VALUE1 0x00003F00 -+#define BF_PXP_HIST32_PARAM0_VALUE1(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM0_VALUE1) -+#define BP_PXP_HIST32_PARAM0_RSVD0 6 -+#define BM_PXP_HIST32_PARAM0_RSVD0 0x000000C0 -+#define BF_PXP_HIST32_PARAM0_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM0_RSVD0) -+#define BP_PXP_HIST32_PARAM0_VALUE0 0 -+#define BM_PXP_HIST32_PARAM0_VALUE0 0x0000003F -+#define BF_PXP_HIST32_PARAM0_VALUE0(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM0_VALUE0) -+ -+#define HW_PXP_HIST32_PARAM1 (0x00002b90) -+ -+#define BP_PXP_HIST32_PARAM1_RSVD7 30 -+#define BM_PXP_HIST32_PARAM1_RSVD7 0xC0000000 -+#define BF_PXP_HIST32_PARAM1_RSVD7(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM1_RSVD7) -+#define BP_PXP_HIST32_PARAM1_VALUE7 24 -+#define BM_PXP_HIST32_PARAM1_VALUE7 0x3F000000 -+#define BF_PXP_HIST32_PARAM1_VALUE7(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM1_VALUE7) -+#define BP_PXP_HIST32_PARAM1_RSVD6 22 -+#define BM_PXP_HIST32_PARAM1_RSVD6 0x00C00000 -+#define BF_PXP_HIST32_PARAM1_RSVD6(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM1_RSVD6) -+#define BP_PXP_HIST32_PARAM1_VALUE6 16 -+#define BM_PXP_HIST32_PARAM1_VALUE6 0x003F0000 -+#define BF_PXP_HIST32_PARAM1_VALUE6(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM1_VALUE6) -+#define BP_PXP_HIST32_PARAM1_RSVD5 14 -+#define BM_PXP_HIST32_PARAM1_RSVD5 0x0000C000 -+#define BF_PXP_HIST32_PARAM1_RSVD5(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM1_RSVD5) -+#define BP_PXP_HIST32_PARAM1_VALUE5 8 -+#define BM_PXP_HIST32_PARAM1_VALUE5 0x00003F00 -+#define BF_PXP_HIST32_PARAM1_VALUE5(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM1_VALUE5) -+#define BP_PXP_HIST32_PARAM1_RSVD4 6 -+#define BM_PXP_HIST32_PARAM1_RSVD4 0x000000C0 -+#define BF_PXP_HIST32_PARAM1_RSVD4(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM1_RSVD4) -+#define BP_PXP_HIST32_PARAM1_VALUE4 0 -+#define BM_PXP_HIST32_PARAM1_VALUE4 0x0000003F -+#define BF_PXP_HIST32_PARAM1_VALUE4(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM1_VALUE4) -+ -+#define HW_PXP_HIST32_PARAM2 (0x00002ba0) -+ -+#define BP_PXP_HIST32_PARAM2_RSVD11 30 -+#define BM_PXP_HIST32_PARAM2_RSVD11 0xC0000000 -+#define BF_PXP_HIST32_PARAM2_RSVD11(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM2_RSVD11) -+#define BP_PXP_HIST32_PARAM2_VALUE11 24 -+#define BM_PXP_HIST32_PARAM2_VALUE11 0x3F000000 -+#define BF_PXP_HIST32_PARAM2_VALUE11(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM2_VALUE11) -+#define BP_PXP_HIST32_PARAM2_RSVD10 22 -+#define BM_PXP_HIST32_PARAM2_RSVD10 0x00C00000 -+#define BF_PXP_HIST32_PARAM2_RSVD10(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM2_RSVD10) -+#define BP_PXP_HIST32_PARAM2_VALUE10 16 -+#define BM_PXP_HIST32_PARAM2_VALUE10 0x003F0000 -+#define BF_PXP_HIST32_PARAM2_VALUE10(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM2_VALUE10) -+#define BP_PXP_HIST32_PARAM2_RSVD9 14 -+#define BM_PXP_HIST32_PARAM2_RSVD9 0x0000C000 -+#define BF_PXP_HIST32_PARAM2_RSVD9(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM2_RSVD9) -+#define BP_PXP_HIST32_PARAM2_VALUE9 8 -+#define BM_PXP_HIST32_PARAM2_VALUE9 0x00003F00 -+#define BF_PXP_HIST32_PARAM2_VALUE9(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM2_VALUE9) -+#define BP_PXP_HIST32_PARAM2_RSVD8 6 -+#define BM_PXP_HIST32_PARAM2_RSVD8 0x000000C0 -+#define BF_PXP_HIST32_PARAM2_RSVD8(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM2_RSVD8) -+#define BP_PXP_HIST32_PARAM2_VALUE8 0 -+#define BM_PXP_HIST32_PARAM2_VALUE8 0x0000003F -+#define BF_PXP_HIST32_PARAM2_VALUE8(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM2_VALUE8) -+ -+#define HW_PXP_HIST32_PARAM3 (0x00002bb0) -+ -+#define BP_PXP_HIST32_PARAM3_RSVD15 30 -+#define BM_PXP_HIST32_PARAM3_RSVD15 0xC0000000 -+#define BF_PXP_HIST32_PARAM3_RSVD15(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM3_RSVD15) -+#define BP_PXP_HIST32_PARAM3_VALUE15 24 -+#define BM_PXP_HIST32_PARAM3_VALUE15 0x3F000000 -+#define BF_PXP_HIST32_PARAM3_VALUE15(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM3_VALUE15) -+#define BP_PXP_HIST32_PARAM3_RSVD14 22 -+#define BM_PXP_HIST32_PARAM3_RSVD14 0x00C00000 -+#define BF_PXP_HIST32_PARAM3_RSVD14(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM3_RSVD14) -+#define BP_PXP_HIST32_PARAM3_VALUE14 16 -+#define BM_PXP_HIST32_PARAM3_VALUE14 0x003F0000 -+#define BF_PXP_HIST32_PARAM3_VALUE14(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM3_VALUE14) -+#define BP_PXP_HIST32_PARAM3_RSVD13 14 -+#define BM_PXP_HIST32_PARAM3_RSVD13 0x0000C000 -+#define BF_PXP_HIST32_PARAM3_RSVD13(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM3_RSVD13) -+#define BP_PXP_HIST32_PARAM3_VALUE13 8 -+#define BM_PXP_HIST32_PARAM3_VALUE13 0x00003F00 -+#define BF_PXP_HIST32_PARAM3_VALUE13(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM3_VALUE13) -+#define BP_PXP_HIST32_PARAM3_RSVD12 6 -+#define BM_PXP_HIST32_PARAM3_RSVD12 0x000000C0 -+#define BF_PXP_HIST32_PARAM3_RSVD12(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM3_RSVD12) -+#define BP_PXP_HIST32_PARAM3_VALUE12 0 -+#define BM_PXP_HIST32_PARAM3_VALUE12 0x0000003F -+#define BF_PXP_HIST32_PARAM3_VALUE12(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM3_VALUE12) -+ -+#define HW_PXP_HIST32_PARAM4 (0x00002bc0) -+ -+#define BP_PXP_HIST32_PARAM4_RSVD3 30 -+#define BM_PXP_HIST32_PARAM4_RSVD3 0xC0000000 -+#define BF_PXP_HIST32_PARAM4_RSVD3(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM4_RSVD3) -+#define BP_PXP_HIST32_PARAM4_VALUE19 24 -+#define BM_PXP_HIST32_PARAM4_VALUE19 0x3F000000 -+#define BF_PXP_HIST32_PARAM4_VALUE19(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM4_VALUE19) -+#define BP_PXP_HIST32_PARAM4_RSVD2 22 -+#define BM_PXP_HIST32_PARAM4_RSVD2 0x00C00000 -+#define BF_PXP_HIST32_PARAM4_RSVD2(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM4_RSVD2) -+#define BP_PXP_HIST32_PARAM4_VALUE18 16 -+#define BM_PXP_HIST32_PARAM4_VALUE18 0x003F0000 -+#define BF_PXP_HIST32_PARAM4_VALUE18(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM4_VALUE18) -+#define BP_PXP_HIST32_PARAM4_RSVD1 14 -+#define BM_PXP_HIST32_PARAM4_RSVD1 0x0000C000 -+#define BF_PXP_HIST32_PARAM4_RSVD1(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM4_RSVD1) -+#define BP_PXP_HIST32_PARAM4_VALUE17 8 -+#define BM_PXP_HIST32_PARAM4_VALUE17 0x00003F00 -+#define BF_PXP_HIST32_PARAM4_VALUE17(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM4_VALUE17) -+#define BP_PXP_HIST32_PARAM4_RSVD0 6 -+#define BM_PXP_HIST32_PARAM4_RSVD0 0x000000C0 -+#define BF_PXP_HIST32_PARAM4_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM4_RSVD0) -+#define BP_PXP_HIST32_PARAM4_VALUE16 0 -+#define BM_PXP_HIST32_PARAM4_VALUE16 0x0000003F -+#define BF_PXP_HIST32_PARAM4_VALUE16(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM4_VALUE16) -+ -+#define HW_PXP_HIST32_PARAM5 (0x00002bd0) -+ -+#define BP_PXP_HIST32_PARAM5_RSVD7 30 -+#define BM_PXP_HIST32_PARAM5_RSVD7 0xC0000000 -+#define BF_PXP_HIST32_PARAM5_RSVD7(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM5_RSVD7) -+#define BP_PXP_HIST32_PARAM5_VALUE23 24 -+#define BM_PXP_HIST32_PARAM5_VALUE23 0x3F000000 -+#define BF_PXP_HIST32_PARAM5_VALUE23(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM5_VALUE23) -+#define BP_PXP_HIST32_PARAM5_RSVD6 22 -+#define BM_PXP_HIST32_PARAM5_RSVD6 0x00C00000 -+#define BF_PXP_HIST32_PARAM5_RSVD6(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM5_RSVD6) -+#define BP_PXP_HIST32_PARAM5_VALUE22 16 -+#define BM_PXP_HIST32_PARAM5_VALUE22 0x003F0000 -+#define BF_PXP_HIST32_PARAM5_VALUE22(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM5_VALUE22) -+#define BP_PXP_HIST32_PARAM5_RSVD5 14 -+#define BM_PXP_HIST32_PARAM5_RSVD5 0x0000C000 -+#define BF_PXP_HIST32_PARAM5_RSVD5(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM5_RSVD5) -+#define BP_PXP_HIST32_PARAM5_VALUE21 8 -+#define BM_PXP_HIST32_PARAM5_VALUE21 0x00003F00 -+#define BF_PXP_HIST32_PARAM5_VALUE21(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM5_VALUE21) -+#define BP_PXP_HIST32_PARAM5_RSVD4 6 -+#define BM_PXP_HIST32_PARAM5_RSVD4 0x000000C0 -+#define BF_PXP_HIST32_PARAM5_RSVD4(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM5_RSVD4) -+#define BP_PXP_HIST32_PARAM5_VALUE20 0 -+#define BM_PXP_HIST32_PARAM5_VALUE20 0x0000003F -+#define BF_PXP_HIST32_PARAM5_VALUE20(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM5_VALUE20) -+ -+#define HW_PXP_HIST32_PARAM6 (0x00002be0) -+ -+#define BP_PXP_HIST32_PARAM6_RSVD11 30 -+#define BM_PXP_HIST32_PARAM6_RSVD11 0xC0000000 -+#define BF_PXP_HIST32_PARAM6_RSVD11(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM6_RSVD11) -+#define BP_PXP_HIST32_PARAM6_VALUE27 24 -+#define BM_PXP_HIST32_PARAM6_VALUE27 0x3F000000 -+#define BF_PXP_HIST32_PARAM6_VALUE27(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM6_VALUE27) -+#define BP_PXP_HIST32_PARAM6_RSVD10 22 -+#define BM_PXP_HIST32_PARAM6_RSVD10 0x00C00000 -+#define BF_PXP_HIST32_PARAM6_RSVD10(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM6_RSVD10) -+#define BP_PXP_HIST32_PARAM6_VALUE26 16 -+#define BM_PXP_HIST32_PARAM6_VALUE26 0x003F0000 -+#define BF_PXP_HIST32_PARAM6_VALUE26(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM6_VALUE26) -+#define BP_PXP_HIST32_PARAM6_RSVD9 14 -+#define BM_PXP_HIST32_PARAM6_RSVD9 0x0000C000 -+#define BF_PXP_HIST32_PARAM6_RSVD9(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM6_RSVD9) -+#define BP_PXP_HIST32_PARAM6_VALUE25 8 -+#define BM_PXP_HIST32_PARAM6_VALUE25 0x00003F00 -+#define BF_PXP_HIST32_PARAM6_VALUE25(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM6_VALUE25) -+#define BP_PXP_HIST32_PARAM6_RSVD8 6 -+#define BM_PXP_HIST32_PARAM6_RSVD8 0x000000C0 -+#define BF_PXP_HIST32_PARAM6_RSVD8(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM6_RSVD8) -+#define BP_PXP_HIST32_PARAM6_VALUE24 0 -+#define BM_PXP_HIST32_PARAM6_VALUE24 0x0000003F -+#define BF_PXP_HIST32_PARAM6_VALUE24(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM6_VALUE24) -+ -+#define HW_PXP_HIST32_PARAM7 (0x00002bf0) -+ -+#define BP_PXP_HIST32_PARAM7_RSVD15 30 -+#define BM_PXP_HIST32_PARAM7_RSVD15 0xC0000000 -+#define BF_PXP_HIST32_PARAM7_RSVD15(v) \ -+ (((v) << 30) & BM_PXP_HIST32_PARAM7_RSVD15) -+#define BP_PXP_HIST32_PARAM7_VALUE31 24 -+#define BM_PXP_HIST32_PARAM7_VALUE31 0x3F000000 -+#define BF_PXP_HIST32_PARAM7_VALUE31(v) \ -+ (((v) << 24) & BM_PXP_HIST32_PARAM7_VALUE31) -+#define BP_PXP_HIST32_PARAM7_RSVD14 22 -+#define BM_PXP_HIST32_PARAM7_RSVD14 0x00C00000 -+#define BF_PXP_HIST32_PARAM7_RSVD14(v) \ -+ (((v) << 22) & BM_PXP_HIST32_PARAM7_RSVD14) -+#define BP_PXP_HIST32_PARAM7_VALUE30 16 -+#define BM_PXP_HIST32_PARAM7_VALUE30 0x003F0000 -+#define BF_PXP_HIST32_PARAM7_VALUE30(v) \ -+ (((v) << 16) & BM_PXP_HIST32_PARAM7_VALUE30) -+#define BP_PXP_HIST32_PARAM7_RSVD13 14 -+#define BM_PXP_HIST32_PARAM7_RSVD13 0x0000C000 -+#define BF_PXP_HIST32_PARAM7_RSVD13(v) \ -+ (((v) << 14) & BM_PXP_HIST32_PARAM7_RSVD13) -+#define BP_PXP_HIST32_PARAM7_VALUE29 8 -+#define BM_PXP_HIST32_PARAM7_VALUE29 0x00003F00 -+#define BF_PXP_HIST32_PARAM7_VALUE29(v) \ -+ (((v) << 8) & BM_PXP_HIST32_PARAM7_VALUE29) -+#define BP_PXP_HIST32_PARAM7_RSVD2 6 -+#define BM_PXP_HIST32_PARAM7_RSVD2 0x000000C0 -+#define BF_PXP_HIST32_PARAM7_RSVD2(v) \ -+ (((v) << 6) & BM_PXP_HIST32_PARAM7_RSVD2) -+#define BP_PXP_HIST32_PARAM7_VALUE28 0 -+#define BM_PXP_HIST32_PARAM7_VALUE28 0x0000003F -+#define BF_PXP_HIST32_PARAM7_VALUE28(v) \ -+ (((v) << 0) & BM_PXP_HIST32_PARAM7_VALUE28) -+ -+#define HW_PXP_COMP_CTRL (0x00002c00) -+#define HW_PXP_COMP_CTRL_SET (0x00002c04) -+#define HW_PXP_COMP_CTRL_CLR (0x00002c08) -+#define HW_PXP_COMP_CTRL_TOG (0x00002c0c) -+ -+#define BP_PXP_COMP_CTRL_RSVD0 9 -+#define BM_PXP_COMP_CTRL_RSVD0 0xFFFFFE00 -+#define BF_PXP_COMP_CTRL_RSVD0(v) \ -+ (((v) << 9) & BM_PXP_COMP_CTRL_RSVD0) -+#define BM_PXP_COMP_CTRL_SW_RESET 0x00000100 -+#define BF_PXP_COMP_CTRL_SW_RESET(v) \ -+ (((v) << 8) & BM_PXP_COMP_CTRL_SW_RESET) -+#define BP_PXP_COMP_CTRL_RSVD1 1 -+#define BM_PXP_COMP_CTRL_RSVD1 0x000000FE -+#define BF_PXP_COMP_CTRL_RSVD1(v) \ -+ (((v) << 1) & BM_PXP_COMP_CTRL_RSVD1) -+#define BM_PXP_COMP_CTRL_START 0x00000001 -+#define BF_PXP_COMP_CTRL_START(v) \ -+ (((v) << 0) & BM_PXP_COMP_CTRL_START) -+ -+#define HW_PXP_COMP_FORMAT0 (0x00002c10) -+#define HW_PXP_COMP_FORMAT0_SET (0x00002c14) -+#define HW_PXP_COMP_FORMAT0_CLR (0x00002c18) -+#define HW_PXP_COMP_FORMAT0_TOG (0x00002c1c) -+ -+#define BP_PXP_COMP_FORMAT0_RSVD0 28 -+#define BM_PXP_COMP_FORMAT0_RSVD0 0xF0000000 -+#define BF_PXP_COMP_FORMAT0_RSVD0(v) \ -+ (((v) << 28) & BM_PXP_COMP_FORMAT0_RSVD0) -+#define BP_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 16 -+#define BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 0x0FFF0000 -+#define BF_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(v) \ -+ (((v) << 16) & BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B) -+#define BP_PXP_COMP_FORMAT0_RSVD1 10 -+#define BM_PXP_COMP_FORMAT0_RSVD1 0x0000FC00 -+#define BF_PXP_COMP_FORMAT0_RSVD1(v) \ -+ (((v) << 10) & BM_PXP_COMP_FORMAT0_RSVD1) -+#define BP_PXP_COMP_FORMAT0_MASK_INDEX 8 -+#define BM_PXP_COMP_FORMAT0_MASK_INDEX 0x00000300 -+#define BF_PXP_COMP_FORMAT0_MASK_INDEX(v) \ -+ (((v) << 8) & BM_PXP_COMP_FORMAT0_MASK_INDEX) -+#define BP_PXP_COMP_FORMAT0_RSVD2 6 -+#define BM_PXP_COMP_FORMAT0_RSVD2 0x000000C0 -+#define BF_PXP_COMP_FORMAT0_RSVD2(v) \ -+ (((v) << 6) & BM_PXP_COMP_FORMAT0_RSVD2) -+#define BP_PXP_COMP_FORMAT0_FIELD_NUM 4 -+#define BM_PXP_COMP_FORMAT0_FIELD_NUM 0x00000030 -+#define BF_PXP_COMP_FORMAT0_FIELD_NUM(v) \ -+ (((v) << 4) & BM_PXP_COMP_FORMAT0_FIELD_NUM) -+#define BP_PXP_COMP_FORMAT0_RSVD3 1 -+#define BM_PXP_COMP_FORMAT0_RSVD3 0x0000000E -+#define BF_PXP_COMP_FORMAT0_RSVD3(v) \ -+ (((v) << 1) & BM_PXP_COMP_FORMAT0_RSVD3) -+#define BM_PXP_COMP_FORMAT0_FLAG_32B 0x00000001 -+#define BF_PXP_COMP_FORMAT0_FLAG_32B(v) \ -+ (((v) << 0) & BM_PXP_COMP_FORMAT0_FLAG_32B) -+ -+#define HW_PXP_COMP_FORMAT1 (0x00002c20) -+ -+#define BP_PXP_COMP_FORMAT1_D_LEN 29 -+#define BM_PXP_COMP_FORMAT1_D_LEN 0xE0000000 -+#define BF_PXP_COMP_FORMAT1_D_LEN(v) \ -+ (((v) << 29) & BM_PXP_COMP_FORMAT1_D_LEN) -+#define BP_PXP_COMP_FORMAT1_D_OFFSET 24 -+#define BM_PXP_COMP_FORMAT1_D_OFFSET 0x1F000000 -+#define BF_PXP_COMP_FORMAT1_D_OFFSET(v) \ -+ (((v) << 24) & BM_PXP_COMP_FORMAT1_D_OFFSET) -+#define BP_PXP_COMP_FORMAT1_C_LEN 21 -+#define BM_PXP_COMP_FORMAT1_C_LEN 0x00E00000 -+#define BF_PXP_COMP_FORMAT1_C_LEN(v) \ -+ (((v) << 21) & BM_PXP_COMP_FORMAT1_C_LEN) -+#define BP_PXP_COMP_FORMAT1_C_OFFSET 16 -+#define BM_PXP_COMP_FORMAT1_C_OFFSET 0x001F0000 -+#define BF_PXP_COMP_FORMAT1_C_OFFSET(v) \ -+ (((v) << 16) & BM_PXP_COMP_FORMAT1_C_OFFSET) -+#define BP_PXP_COMP_FORMAT1_B_LEN 13 -+#define BM_PXP_COMP_FORMAT1_B_LEN 0x0000E000 -+#define BF_PXP_COMP_FORMAT1_B_LEN(v) \ -+ (((v) << 13) & BM_PXP_COMP_FORMAT1_B_LEN) -+#define BP_PXP_COMP_FORMAT1_B_OFFSET 8 -+#define BM_PXP_COMP_FORMAT1_B_OFFSET 0x00001F00 -+#define BF_PXP_COMP_FORMAT1_B_OFFSET(v) \ -+ (((v) << 8) & BM_PXP_COMP_FORMAT1_B_OFFSET) -+#define BP_PXP_COMP_FORMAT1_A_LEN 5 -+#define BM_PXP_COMP_FORMAT1_A_LEN 0x000000E0 -+#define BF_PXP_COMP_FORMAT1_A_LEN(v) \ -+ (((v) << 5) & BM_PXP_COMP_FORMAT1_A_LEN) -+#define BP_PXP_COMP_FORMAT1_A_OFFSET 0 -+#define BM_PXP_COMP_FORMAT1_A_OFFSET 0x0000001F -+#define BF_PXP_COMP_FORMAT1_A_OFFSET(v) \ -+ (((v) << 0) & BM_PXP_COMP_FORMAT1_A_OFFSET) -+ -+#define HW_PXP_COMP_FORMAT2 (0x00002c30) -+ -+#define BP_PXP_COMP_FORMAT2_RSVD 16 -+#define BM_PXP_COMP_FORMAT2_RSVD 0xFFFF0000 -+#define BF_PXP_COMP_FORMAT2_RSVD(v) \ -+ (((v) << 16) & BM_PXP_COMP_FORMAT2_RSVD) -+#define BP_PXP_COMP_FORMAT2_D_RUNLEN 12 -+#define BM_PXP_COMP_FORMAT2_D_RUNLEN 0x0000F000 -+#define BF_PXP_COMP_FORMAT2_D_RUNLEN(v) \ -+ (((v) << 12) & BM_PXP_COMP_FORMAT2_D_RUNLEN) -+#define BP_PXP_COMP_FORMAT2_C_RUNLEN 8 -+#define BM_PXP_COMP_FORMAT2_C_RUNLEN 0x00000F00 -+#define BF_PXP_COMP_FORMAT2_C_RUNLEN(v) \ -+ (((v) << 8) & BM_PXP_COMP_FORMAT2_C_RUNLEN) -+#define BP_PXP_COMP_FORMAT2_B_RUNLEN 4 -+#define BM_PXP_COMP_FORMAT2_B_RUNLEN 0x000000F0 -+#define BF_PXP_COMP_FORMAT2_B_RUNLEN(v) \ -+ (((v) << 4) & BM_PXP_COMP_FORMAT2_B_RUNLEN) -+#define BP_PXP_COMP_FORMAT2_A_RUNLEN 0 -+#define BM_PXP_COMP_FORMAT2_A_RUNLEN 0x0000000F -+#define BF_PXP_COMP_FORMAT2_A_RUNLEN(v) \ -+ (((v) << 0) & BM_PXP_COMP_FORMAT2_A_RUNLEN) -+ -+#define HW_PXP_COMP_MASK0 (0x00002c40) -+ -+#define BP_PXP_COMP_MASK0_VLD_MASK_LOW 0 -+#define BM_PXP_COMP_MASK0_VLD_MASK_LOW 0xFFFFFFFF -+#define BF_PXP_COMP_MASK0_VLD_MASK_LOW(v) (v) -+ -+#define HW_PXP_COMP_MASK1 (0x00002c50) -+ -+#define BP_PXP_COMP_MASK1_VLD_MASK_HIGH 0 -+#define BM_PXP_COMP_MASK1_VLD_MASK_HIGH 0xFFFFFFFF -+#define BF_PXP_COMP_MASK1_VLD_MASK_HIGH(v) (v) -+ -+#define HW_PXP_COMP_BUFFER_SIZE (0x00002c60) -+ -+#define BP_PXP_COMP_BUFFER_SIZE_RSVD0 29 -+#define BM_PXP_COMP_BUFFER_SIZE_RSVD0 0xE0000000 -+#define BF_PXP_COMP_BUFFER_SIZE_RSVD0(v) \ -+ (((v) << 29) & BM_PXP_COMP_BUFFER_SIZE_RSVD0) -+#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 16 -+#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 0x1FFF0000 -+#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(v) \ -+ (((v) << 16) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH) -+#define BP_PXP_COMP_BUFFER_SIZE_RSVD1 13 -+#define BM_PXP_COMP_BUFFER_SIZE_RSVD1 0x0000E000 -+#define BF_PXP_COMP_BUFFER_SIZE_RSVD1(v) \ -+ (((v) << 13) & BM_PXP_COMP_BUFFER_SIZE_RSVD1) -+#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0 -+#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0x00001FFF -+#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(v) \ -+ (((v) << 0) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH) -+ -+#define HW_PXP_COMP_SOURCE (0x00002c70) -+ -+#define BP_PXP_COMP_SOURCE_SOURCE_ADDR 0 -+#define BM_PXP_COMP_SOURCE_SOURCE_ADDR 0xFFFFFFFF -+#define BF_PXP_COMP_SOURCE_SOURCE_ADDR(v) (v) -+ -+#define HW_PXP_COMP_TARGET (0x00002c80) -+ -+#define BP_PXP_COMP_TARGET_TARGET_ADDR 0 -+#define BM_PXP_COMP_TARGET_TARGET_ADDR 0xFFFFFFFF -+#define BF_PXP_COMP_TARGET_TARGET_ADDR(v) (v) -+ -+#define HW_PXP_COMP_BUFFER_A (0x00002c90) -+ -+#define BP_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0 -+#define BM_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0xFFFFFFFF -+#define BF_PXP_COMP_BUFFER_A_A_SRAM_ADDR(v) (v) -+ -+#define HW_PXP_COMP_BUFFER_B (0x00002ca0) -+ -+#define BP_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0 -+#define BM_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0xFFFFFFFF -+#define BF_PXP_COMP_BUFFER_B_B_SRAM_ADDR(v) (v) -+ -+#define HW_PXP_COMP_BUFFER_C (0x00002cb0) -+ -+#define BP_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0 -+#define BM_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0xFFFFFFFF -+#define BF_PXP_COMP_BUFFER_C_C_SRAM_ADDR(v) (v) -+ -+#define HW_PXP_COMP_BUFFER_D (0x00002cc0) -+ -+#define BP_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0 -+#define BM_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0xFFFFFFFF -+#define BF_PXP_COMP_BUFFER_D_D_SRAM_ADDR(v) (v) -+ -+#define HW_PXP_COMP_DEBUG (0x00002cd0) -+ -+#define BP_PXP_COMP_DEBUG_DEBUG_VALUE 8 -+#define BM_PXP_COMP_DEBUG_DEBUG_VALUE 0xFFFFFF00 -+#define BF_PXP_COMP_DEBUG_DEBUG_VALUE(v) \ -+ (((v) << 8) & BM_PXP_COMP_DEBUG_DEBUG_VALUE) -+#define BP_PXP_COMP_DEBUG_DEBUG_SEL 0 -+#define BM_PXP_COMP_DEBUG_DEBUG_SEL 0x000000FF -+#define BF_PXP_COMP_DEBUG_DEBUG_SEL(v) \ -+ (((v) << 0) & BM_PXP_COMP_DEBUG_DEBUG_SEL) -+ -+#define HW_PXP_BUS_MUX (0x00002ce0) -+ -+#define BP_PXP_BUS_MUX_RSVD1 24 -+#define BM_PXP_BUS_MUX_RSVD1 0xFF000000 -+#define BF_PXP_BUS_MUX_RSVD1(v) \ -+ (((v) << 24) & BM_PXP_BUS_MUX_RSVD1) -+#define BP_PXP_BUS_MUX_WR_SEL 16 -+#define BM_PXP_BUS_MUX_WR_SEL 0x00FF0000 -+#define BF_PXP_BUS_MUX_WR_SEL(v) \ -+ (((v) << 16) & BM_PXP_BUS_MUX_WR_SEL) -+#define BP_PXP_BUS_MUX_RSVD0 8 -+#define BM_PXP_BUS_MUX_RSVD0 0x0000FF00 -+#define BF_PXP_BUS_MUX_RSVD0(v) \ -+ (((v) << 8) & BM_PXP_BUS_MUX_RSVD0) -+#define BP_PXP_BUS_MUX_RD_SEL 0 -+#define BM_PXP_BUS_MUX_RD_SEL 0x000000FF -+#define BF_PXP_BUS_MUX_RD_SEL(v) \ -+ (((v) << 0) & BM_PXP_BUS_MUX_RD_SEL) -+ -+#define HW_PXP_HANDSHAKE_READY_MUX0 (0x00002cf0) -+ -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK7 28 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK7 0xF0000000 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK7(v) \ -+ (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX0_HSK7) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK6 24 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK6 0x0F000000 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK6(v) \ -+ (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX0_HSK6) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK5 20 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK5 0x00F00000 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK5(v) \ -+ (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX0_HSK5) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK4 16 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK4 0x000F0000 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK4(v) \ -+ (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX0_HSK4) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK3 12 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK3 0x0000F000 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK3(v) \ -+ (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX0_HSK3) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK2 8 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK2 0x00000F00 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK2(v) \ -+ (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX0_HSK2) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK1 4 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK1 0x000000F0 -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK1(v) \ -+ (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX0_HSK1) -+#define BP_PXP_HANDSHAKE_READY_MUX0_HSK0 0 -+#define BM_PXP_HANDSHAKE_READY_MUX0_HSK0 0x0000000F -+#define BF_PXP_HANDSHAKE_READY_MUX0_HSK0(v) \ -+ (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX0_HSK0) -+ -+#define HW_PXP_HANDSHAKE_READY_MUX1 (0x00002d00) -+ -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK15 28 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK15 0xF0000000 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK15(v) \ -+ (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX1_HSK15) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK14 24 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK14 0x0F000000 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK14(v) \ -+ (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX1_HSK14) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK13 20 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK13 0x00F00000 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK13(v) \ -+ (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX1_HSK13) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK12 16 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK12 0x000F0000 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK12(v) \ -+ (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX1_HSK12) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK11 12 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK11 0x0000F000 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK11(v) \ -+ (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX1_HSK11) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK10 8 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK10 0x00000F00 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK10(v) \ -+ (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX1_HSK10) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK9 4 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK9 0x000000F0 -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK9(v) \ -+ (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX1_HSK9) -+#define BP_PXP_HANDSHAKE_READY_MUX1_HSK8 0 -+#define BM_PXP_HANDSHAKE_READY_MUX1_HSK8 0x0000000F -+#define BF_PXP_HANDSHAKE_READY_MUX1_HSK8(v) \ -+ (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX1_HSK8) -+ -+#define HW_PXP_HANDSHAKE_DONE_MUX0 (0x00002d10) -+ -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK7 28 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK7 0xF0000000 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK7(v) \ -+ (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK7) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK6 24 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK6 0x0F000000 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK6(v) \ -+ (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK6) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK5 20 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK5 0x00F00000 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK5(v) \ -+ (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK5) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK4 16 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK4 0x000F0000 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK4(v) \ -+ (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK4) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK3 12 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK3 0x0000F000 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK3(v) \ -+ (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK3) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK2 8 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK2 0x00000F00 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK2(v) \ -+ (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK2) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK1 4 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK1 0x000000F0 -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK1(v) \ -+ (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK1) -+#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK0 0 -+#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK0 0x0000000F -+#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK0(v) \ -+ (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK0) -+ -+#define HW_PXP_HANDSHAKE_DONE_MUX1 (0x00002d20) -+ -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK15 28 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK15 0xF0000000 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK15(v) \ -+ (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK15) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK14 24 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK14 0x0F000000 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK14(v) \ -+ (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK14) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK13 20 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK13 0x00F00000 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK13(v) \ -+ (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK13) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK12 16 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK12 0x000F0000 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK12(v) \ -+ (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK12) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK11 12 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK11 0x0000F000 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK11(v) \ -+ (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK11) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK10 8 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK10 0x00000F00 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK10(v) \ -+ (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK10) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK9 4 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK9 0x000000F0 -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK9(v) \ -+ (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK9) -+#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK8 0 -+#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK8 0x0000000F -+#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK8(v) \ -+ (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK8) -+ -+#define HW_PXP_HANDSHAKE_CPU_FETCH (0x00002d30) -+#define HW_PXP_HANDSHAKE_CPU_FETCH_SET (0x00002d34) -+#define HW_PXP_HANDSHAKE_CPU_FETCH_CLR (0x00002d38) -+#define HW_PXP_HANDSHAKE_CPU_FETCH_TOG (0x00002d3c) -+ -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN 0x80000000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN(v) \ -+ (((v) << 31) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN) -+#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD1 22 -+#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1 0x7FC00000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1) -+#define BP_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 20 -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 0x00300000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(v) \ -+ (((v) << 20) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES) -+#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_4 0x0 -+#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_8 0x1 -+#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_16 0x2 -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE 0x00080000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE(v) \ -+ (((v) << 19) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE 0x00040000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE(v) \ -+ (((v) << 18) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY 0x00020000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY(v) \ -+ (((v) << 17) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY 0x00010000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY(v) \ -+ (((v) << 16) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN 0x00008000 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN(v) \ -+ (((v) << 15) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN) -+#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD0 6 -+#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0 0x00007FC0 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0) -+#define BP_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 4 -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 0x00000030 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(v) \ -+ (((v) << 4) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES) -+#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_4 0x0 -+#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_8 0x1 -+#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_16 0x2 -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE 0x00000008 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE(v) \ -+ (((v) << 3) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE 0x00000004 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE(v) \ -+ (((v) << 2) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY 0x00000002 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY(v) \ -+ (((v) << 1) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY) -+#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY 0x00000001 -+#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY(v) \ -+ (((v) << 0) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY) -+ -+#define HW_PXP_HANDSHAKE_CPU_STORE (0x00002d40) -+#define HW_PXP_HANDSHAKE_CPU_STORE_SET (0x00002d44) -+#define HW_PXP_HANDSHAKE_CPU_STORE_CLR (0x00002d48) -+#define HW_PXP_HANDSHAKE_CPU_STORE_TOG (0x00002d4c) -+ -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN 0x80000000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN(v) \ -+ (((v) << 31) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN) -+#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD1 22 -+#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD1 0x7FC00000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD1(v) \ -+ (((v) << 22) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD1) -+#define BP_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 20 -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 0x00300000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(v) \ -+ (((v) << 20) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES) -+#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_4 0x0 -+#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_8 0x1 -+#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_16 0x2 -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE 0x00080000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE(v) \ -+ (((v) << 19) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE 0x00040000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE(v) \ -+ (((v) << 18) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY 0x00020000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY(v) \ -+ (((v) << 17) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY 0x00010000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY(v) \ -+ (((v) << 16) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN 0x00008000 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN(v) \ -+ (((v) << 15) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN) -+#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD0 6 -+#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD0 0x00007FC0 -+#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD0(v) \ -+ (((v) << 6) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD0) -+#define BP_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 4 -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 0x00000030 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(v) \ -+ (((v) << 4) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES) -+#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_4 0x0 -+#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_8 0x1 -+#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_16 0x2 -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE 0x00000008 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE(v) \ -+ (((v) << 3) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE 0x00000004 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE(v) \ -+ (((v) << 2) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY 0x00000002 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY(v) \ -+ (((v) << 1) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY) -+#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY 0x00000001 -+#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY(v) \ -+ (((v) << 0) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY) -+#endif /* __ARCH_ARM___PXP_H */ -diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile -index bc0d54f8e..6a2ef6330 100644 ---- a/drivers/firmware/arm_scmi/Makefile -+++ b/drivers/firmware/arm_scmi/Makefile -@@ -4,7 +4,7 @@ scmi-driver-y = driver.o notify.o - scmi-transport-y = shmem.o - scmi-transport-$(CONFIG_MAILBOX) += mailbox.o - scmi-transport-$(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) += smc.o --scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o system.o -+scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o - scmi-module-objs := $(scmi-bus-y) $(scmi-driver-y) $(scmi-protocols-y) \ - $(scmi-transport-y) - obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-module.o -diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h -index 34b7ae798..9c1f06759 100644 ---- a/drivers/firmware/arm_scmi/common.h -+++ b/drivers/firmware/arm_scmi/common.h -@@ -169,6 +169,7 @@ DECLARE_SCMI_REGISTER_UNREGISTER(perf); - DECLARE_SCMI_REGISTER_UNREGISTER(power); - DECLARE_SCMI_REGISTER_UNREGISTER(reset); - DECLARE_SCMI_REGISTER_UNREGISTER(sensors); -+DECLARE_SCMI_REGISTER_UNREGISTER(voltage); - DECLARE_SCMI_REGISTER_UNREGISTER(system); - - #define DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(id, name) \ -diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c -index 763223248..39f0d5f86 100644 ---- a/drivers/firmware/arm_scmi/driver.c -+++ b/drivers/firmware/arm_scmi/driver.c -@@ -751,8 +751,9 @@ static struct scmi_prot_devnames devnames[] = { - { SCMI_PROTOCOL_SYSTEM, { "syspower" },}, - { SCMI_PROTOCOL_PERF, { "cpufreq" },}, - { SCMI_PROTOCOL_CLOCK, { "clocks" },}, -- { SCMI_PROTOCOL_SENSOR, { "hwmon" },}, -+ { SCMI_PROTOCOL_SENSOR, { "hwmon", "iiodev" },}, - { SCMI_PROTOCOL_RESET, { "reset" },}, -+ { SCMI_PROTOCOL_VOLTAGE, { "regulator" },}, - }; - - static inline void -@@ -958,6 +959,7 @@ static int __init scmi_driver_init(void) - scmi_power_register(); - scmi_reset_register(); - scmi_sensors_register(); -+ scmi_voltage_register(); - scmi_system_register(); - - return platform_driver_register(&scmi_driver); -@@ -973,6 +975,7 @@ static void __exit scmi_driver_exit(void) - scmi_power_unregister(); - scmi_reset_unregister(); - scmi_sensors_unregister(); -+ scmi_voltage_unregister(); - scmi_system_unregister(); - - platform_driver_unregister(&scmi_driver); -diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c -index 82fb3babf..e374b1125 100644 ---- a/drivers/firmware/arm_scmi/perf.c -+++ b/drivers/firmware/arm_scmi/perf.c -@@ -750,6 +750,13 @@ static bool scmi_fast_switch_possible(const struct scmi_handle *handle, - return dom->fc_info && dom->fc_info->level_set_addr; - } - -+static bool scmi_power_scale_mw_get(const struct scmi_handle *handle) -+{ -+ struct scmi_perf_info *pi = handle->perf_priv; -+ -+ return pi->power_scale_mw; -+} -+ - static const struct scmi_perf_ops perf_ops = { - .limits_set = scmi_perf_limits_set, - .limits_get = scmi_perf_limits_get, -@@ -762,6 +769,7 @@ static const struct scmi_perf_ops perf_ops = { - .freq_get = scmi_dvfs_freq_get, - .est_power_get = scmi_dvfs_est_power_get, - .fast_switch_possible = scmi_fast_switch_possible, -+ .power_scale_mw_get = scmi_power_scale_mw_get, - }; - - static int scmi_perf_set_notify_enabled(const struct scmi_handle *handle, -diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c -index b4232d611..594d1669c 100644 ---- a/drivers/firmware/arm_scmi/sensors.c -+++ b/drivers/firmware/arm_scmi/sensors.c -@@ -7,16 +7,25 @@ - - #define pr_fmt(fmt) "SCMI Notifications SENSOR - " fmt - -+#include - #include - - #include "common.h" - #include "notify.h" - -+#define SCMI_MAX_NUM_SENSOR_AXIS 63 -+#define SCMIv2_SENSOR_PROTOCOL 0x10000 -+ - enum scmi_sensor_protocol_cmd { - SENSOR_DESCRIPTION_GET = 0x3, - SENSOR_TRIP_POINT_NOTIFY = 0x4, - SENSOR_TRIP_POINT_CONFIG = 0x5, - SENSOR_READING_GET = 0x6, -+ SENSOR_AXIS_DESCRIPTION_GET = 0x7, -+ SENSOR_LIST_UPDATE_INTERVALS = 0x8, -+ SENSOR_CONFIG_GET = 0x9, -+ SENSOR_CONFIG_SET = 0xA, -+ SENSOR_CONTINUOUS_UPDATE_NOTIFY = 0xB, - }; - - struct scmi_msg_resp_sensor_attributes { -@@ -28,29 +37,106 @@ struct scmi_msg_resp_sensor_attributes { - __le32 reg_size; - }; - -+/* v3 attributes_low macros */ -+#define SUPPORTS_UPDATE_NOTIFY(x) FIELD_GET(BIT(30), (x)) -+#define SENSOR_TSTAMP_EXP(x) FIELD_GET(GENMASK(14, 10), (x)) -+#define SUPPORTS_TIMESTAMP(x) FIELD_GET(BIT(9), (x)) -+#define SUPPORTS_EXTEND_ATTRS(x) FIELD_GET(BIT(8), (x)) -+ -+/* v2 attributes_high macros */ -+#define SENSOR_UPDATE_BASE(x) FIELD_GET(GENMASK(31, 27), (x)) -+#define SENSOR_UPDATE_SCALE(x) FIELD_GET(GENMASK(26, 22), (x)) -+ -+/* v3 attributes_high macros */ -+#define SENSOR_AXIS_NUMBER(x) FIELD_GET(GENMASK(21, 16), (x)) -+#define SUPPORTS_AXIS(x) FIELD_GET(BIT(8), (x)) -+ -+/* v3 resolution macros */ -+#define SENSOR_RES(x) FIELD_GET(GENMASK(26, 0), (x)) -+#define SENSOR_RES_EXP(x) FIELD_GET(GENMASK(31, 27), (x)) -+ -+struct scmi_msg_resp_attrs { -+ __le32 min_range_low; -+ __le32 min_range_high; -+ __le32 max_range_low; -+ __le32 max_range_high; -+}; -+ - struct scmi_msg_resp_sensor_description { - __le16 num_returned; - __le16 num_remaining; -- struct { -+ struct scmi_sensor_descriptor { - __le32 id; - __le32 attributes_low; --#define SUPPORTS_ASYNC_READ(x) ((x) & BIT(31)) --#define NUM_TRIP_POINTS(x) ((x) & 0xff) -+/* Common attributes_low macros */ -+#define SUPPORTS_ASYNC_READ(x) FIELD_GET(BIT(31), (x)) -+#define NUM_TRIP_POINTS(x) FIELD_GET(GENMASK(7, 0), (x)) - __le32 attributes_high; --#define SENSOR_TYPE(x) ((x) & 0xff) --#define SENSOR_SCALE(x) (((x) >> 11) & 0x1f) --#define SENSOR_SCALE_SIGN BIT(4) --#define SENSOR_SCALE_EXTEND GENMASK(7, 5) --#define SENSOR_UPDATE_SCALE(x) (((x) >> 22) & 0x1f) --#define SENSOR_UPDATE_BASE(x) (((x) >> 27) & 0x1f) -- u8 name[SCMI_MAX_STR_SIZE]; -- } desc[0]; -+/* Common attributes_high macros */ -+#define SENSOR_SCALE(x) FIELD_GET(GENMASK(15, 11), (x)) -+#define SENSOR_SCALE_SIGN BIT(4) -+#define SENSOR_SCALE_EXTEND GENMASK(31, 5) -+#define SENSOR_TYPE(x) FIELD_GET(GENMASK(7, 0), (x)) -+ u8 name[SCMI_MAX_STR_SIZE]; -+ /* only for version > 2.0 */ -+ __le32 power; -+ __le32 resolution; -+ struct scmi_msg_resp_attrs scalar_attrs; -+ } desc[]; - }; - --struct scmi_msg_sensor_trip_point_notify { -+/* Base scmi_sensor_descriptor size excluding extended attrs after name */ -+#define SCMI_MSG_RESP_SENS_DESCR_BASE_SZ 28 -+ -+/* Sign extend to a full s32 */ -+#define S32_EXT(v) \ -+ ({ \ -+ int __v = (v); \ -+ \ -+ if (__v & SENSOR_SCALE_SIGN) \ -+ __v |= SENSOR_SCALE_EXTEND; \ -+ __v; \ -+ }) -+ -+struct scmi_msg_sensor_axis_description_get { -+ __le32 id; -+ __le32 axis_desc_index; -+}; -+ -+struct scmi_msg_resp_sensor_axis_description { -+ __le32 num_axis_flags; -+#define NUM_AXIS_RETURNED(x) FIELD_GET(GENMASK(5, 0), (x)) -+#define NUM_AXIS_REMAINING(x) FIELD_GET(GENMASK(31, 26), (x)) -+ struct scmi_axis_descriptor { -+ __le32 id; -+ __le32 attributes_low; -+ __le32 attributes_high; -+ u8 name[SCMI_MAX_STR_SIZE]; -+ __le32 resolution; -+ struct scmi_msg_resp_attrs attrs; -+ } desc[]; -+}; -+ -+/* Base scmi_axis_descriptor size excluding extended attrs after name */ -+#define SCMI_MSG_RESP_AXIS_DESCR_BASE_SZ 28 -+ -+struct scmi_msg_sensor_list_update_intervals { -+ __le32 id; -+ __le32 index; -+}; -+ -+struct scmi_msg_resp_sensor_list_update_intervals { -+ __le32 num_intervals_flags; -+#define NUM_INTERVALS_RETURNED(x) FIELD_GET(GENMASK(11, 0), (x)) -+#define SEGMENTED_INTVL_FORMAT(x) FIELD_GET(BIT(12), (x)) -+#define NUM_INTERVALS_REMAINING(x) FIELD_GET(GENMASK(31, 16), (x)) -+ __le32 intervals[]; -+}; -+ -+struct scmi_msg_sensor_request_notify { - __le32 id; - __le32 event_control; --#define SENSOR_TP_NOTIFY_ALL BIT(0) -+#define SENSOR_NOTIFY_ALL BIT(0) - }; - - struct scmi_msg_set_sensor_trip_point { -@@ -66,18 +152,46 @@ struct scmi_msg_set_sensor_trip_point { - __le32 value_high; - }; - -+struct scmi_msg_sensor_config_set { -+ __le32 id; -+ __le32 sensor_config; -+}; -+ - struct scmi_msg_sensor_reading_get { - __le32 id; - __le32 flags; - #define SENSOR_READ_ASYNC BIT(0) - }; - -+struct scmi_resp_sensor_reading_complete { -+ __le32 id; -+ __le64 readings; -+}; -+ -+struct scmi_sensor_reading_resp { -+ __le32 sensor_value_low; -+ __le32 sensor_value_high; -+ __le32 timestamp_low; -+ __le32 timestamp_high; -+}; -+ -+struct scmi_resp_sensor_reading_complete_v3 { -+ __le32 id; -+ struct scmi_sensor_reading_resp readings[]; -+}; -+ - struct scmi_sensor_trip_notify_payld { - __le32 agent_id; - __le32 sensor_id; - __le32 trip_point_desc; - }; - -+struct scmi_sensor_update_notify_payld { -+ __le32 agent_id; -+ __le32 sensor_id; -+ struct scmi_sensor_reading_resp readings[]; -+}; -+ - struct sensors_info { - u32 version; - int num_sensors; -@@ -114,6 +228,194 @@ static int scmi_sensor_attributes_get(const struct scmi_handle *handle, - return ret; - } - -+static inline void scmi_parse_range_attrs(struct scmi_range_attrs *out, -+ struct scmi_msg_resp_attrs *in) -+{ -+ out->min_range = get_unaligned_le64((void *)&in->min_range_low); -+ out->max_range = get_unaligned_le64((void *)&in->max_range_low); -+} -+ -+static int scmi_sensor_update_intervals(const struct scmi_handle *handle, -+ struct scmi_sensor_info *s) -+{ -+ int ret, cnt; -+ u32 desc_index = 0; -+ u16 num_returned, num_remaining; -+ struct scmi_xfer *ti; -+ struct scmi_msg_resp_sensor_list_update_intervals *buf; -+ struct scmi_msg_sensor_list_update_intervals *msg; -+ -+ ret = scmi_xfer_get_init(handle, SENSOR_LIST_UPDATE_INTERVALS, -+ SCMI_PROTOCOL_SENSOR, sizeof(*msg), 0, &ti); -+ if (ret) -+ return ret; -+ -+ buf = ti->rx.buf; -+ do { -+ u32 flags; -+ -+ msg = ti->tx.buf; -+ /* Set the number of sensors to be skipped/already read */ -+ msg->id = cpu_to_le32(s->id); -+ msg->index = cpu_to_le32(desc_index); -+ -+ ret = scmi_do_xfer(handle, ti); -+ if (ret) -+ break; -+ -+ flags = le32_to_cpu(buf->num_intervals_flags); -+ num_returned = NUM_INTERVALS_RETURNED(flags); -+ num_remaining = NUM_INTERVALS_REMAINING(flags); -+ -+ /* -+ * Max intervals is not declared previously anywhere so we -+ * assume it's returned+remaining. -+ */ -+ if (!s->intervals.count) { -+ s->intervals.segmented = SEGMENTED_INTVL_FORMAT(flags); -+ s->intervals.count = num_returned + num_remaining; -+ /* segmented intervals are reported in one triplet */ -+ if (s->intervals.segmented && -+ (num_remaining || num_returned != 3)) { -+ dev_err(handle->dev, -+ "Sensor ID:%d advertises an invalid segmented interval (%d)\n", -+ s->id, s->intervals.count); -+ s->intervals.segmented = false; -+ s->intervals.count = 0; -+ ret = -EINVAL; -+ break; -+ } -+ /* Direct allocation when exceeding pre-allocated */ -+ if (s->intervals.count >= SCMI_MAX_PREALLOC_POOL) { -+ s->intervals.desc = -+ devm_kcalloc(handle->dev, -+ s->intervals.count, -+ sizeof(*s->intervals.desc), -+ GFP_KERNEL); -+ if (!s->intervals.desc) { -+ s->intervals.segmented = false; -+ s->intervals.count = 0; -+ ret = -ENOMEM; -+ break; -+ } -+ } -+ } else if (desc_index + num_returned > s->intervals.count) { -+ dev_err(handle->dev, -+ "No. of update intervals can't exceed %d\n", -+ s->intervals.count); -+ ret = -EINVAL; -+ break; -+ } -+ -+ for (cnt = 0; cnt < num_returned; cnt++) -+ s->intervals.desc[desc_index + cnt] = -+ le32_to_cpu(buf->intervals[cnt]); -+ -+ desc_index += num_returned; -+ -+ scmi_reset_rx_to_maxsz(handle, ti); -+ /* -+ * check for both returned and remaining to avoid infinite -+ * loop due to buggy firmware -+ */ -+ } while (num_returned && num_remaining); -+ -+ scmi_xfer_put(handle, ti); -+ return ret; -+} -+ -+static int scmi_sensor_axis_description(const struct scmi_handle *handle, -+ struct scmi_sensor_info *s) -+{ -+ int ret, cnt; -+ u32 desc_index = 0; -+ u16 num_returned, num_remaining; -+ struct scmi_xfer *te; -+ struct scmi_msg_resp_sensor_axis_description *buf; -+ struct scmi_msg_sensor_axis_description_get *msg; -+ -+ s->axis = devm_kcalloc(handle->dev, s->num_axis, -+ sizeof(*s->axis), GFP_KERNEL); -+ if (!s->axis) -+ return -ENOMEM; -+ -+ ret = scmi_xfer_get_init(handle, SENSOR_AXIS_DESCRIPTION_GET, -+ SCMI_PROTOCOL_SENSOR, sizeof(*msg), 0, &te); -+ if (ret) -+ return ret; -+ -+ buf = te->rx.buf; -+ do { -+ u32 flags; -+ struct scmi_axis_descriptor *adesc; -+ -+ msg = te->tx.buf; -+ /* Set the number of sensors to be skipped/already read */ -+ msg->id = cpu_to_le32(s->id); -+ msg->axis_desc_index = cpu_to_le32(desc_index); -+ -+ ret = scmi_do_xfer(handle, te); -+ if (ret) -+ break; -+ -+ flags = le32_to_cpu(buf->num_axis_flags); -+ num_returned = NUM_AXIS_RETURNED(flags); -+ num_remaining = NUM_AXIS_REMAINING(flags); -+ -+ if (desc_index + num_returned > s->num_axis) { -+ dev_err(handle->dev, "No. of axis can't exceed %d\n", -+ s->num_axis); -+ break; -+ } -+ -+ adesc = &buf->desc[0]; -+ for (cnt = 0; cnt < num_returned; cnt++) { -+ u32 attrh, attrl; -+ struct scmi_sensor_axis_info *a; -+ size_t dsize = SCMI_MSG_RESP_AXIS_DESCR_BASE_SZ; -+ -+ attrl = le32_to_cpu(adesc->attributes_low); -+ -+ a = &s->axis[desc_index + cnt]; -+ -+ a->id = le32_to_cpu(adesc->id); -+ a->extended_attrs = SUPPORTS_EXTEND_ATTRS(attrl); -+ -+ attrh = le32_to_cpu(adesc->attributes_high); -+ a->scale = S32_EXT(SENSOR_SCALE(attrh)); -+ a->type = SENSOR_TYPE(attrh); -+ strlcpy(a->name, adesc->name, SCMI_MAX_STR_SIZE); -+ -+ if (a->extended_attrs) { -+ unsigned int ares = -+ le32_to_cpu(adesc->resolution); -+ -+ a->resolution = SENSOR_RES(ares); -+ a->exponent = -+ S32_EXT(SENSOR_RES_EXP(ares)); -+ dsize += sizeof(adesc->resolution); -+ -+ scmi_parse_range_attrs(&a->attrs, -+ &adesc->attrs); -+ dsize += sizeof(adesc->attrs); -+ } -+ -+ adesc = (typeof(adesc))((u8 *)adesc + dsize); -+ } -+ -+ desc_index += num_returned; -+ -+ scmi_reset_rx_to_maxsz(handle, te); -+ /* -+ * check for both returned and remaining to avoid infinite -+ * loop due to buggy firmware -+ */ -+ } while (num_returned && num_remaining); -+ -+ scmi_xfer_put(handle, te); -+ return ret; -+} -+ - static int scmi_sensor_description_get(const struct scmi_handle *handle, - struct sensors_info *si) - { -@@ -131,9 +433,10 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, - buf = t->rx.buf; - - do { -+ struct scmi_sensor_descriptor *sdesc; -+ - /* Set the number of sensors to be skipped/already read */ - put_unaligned_le32(desc_index, t->tx.buf); -- - ret = scmi_do_xfer(handle, t); - if (ret) - break; -@@ -147,22 +450,97 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, - break; - } - -+ sdesc = &buf->desc[0]; - for (cnt = 0; cnt < num_returned; cnt++) { - u32 attrh, attrl; - struct scmi_sensor_info *s; -+ size_t dsize = SCMI_MSG_RESP_SENS_DESCR_BASE_SZ; - -- attrl = le32_to_cpu(buf->desc[cnt].attributes_low); -- attrh = le32_to_cpu(buf->desc[cnt].attributes_high); - s = &si->sensors[desc_index + cnt]; -- s->id = le32_to_cpu(buf->desc[cnt].id); -- s->type = SENSOR_TYPE(attrh); -- s->scale = SENSOR_SCALE(attrh); -- /* Sign extend to a full s8 */ -- if (s->scale & SENSOR_SCALE_SIGN) -- s->scale |= SENSOR_SCALE_EXTEND; -+ s->id = le32_to_cpu(sdesc->id); -+ -+ attrl = le32_to_cpu(sdesc->attributes_low); -+ /* common bitfields parsing */ - s->async = SUPPORTS_ASYNC_READ(attrl); - s->num_trip_points = NUM_TRIP_POINTS(attrl); -- strlcpy(s->name, buf->desc[cnt].name, SCMI_MAX_STR_SIZE); -+ /** -+ * only SCMIv3.0 specific bitfield below. -+ * Such bitfields are assumed to be zeroed on non -+ * relevant fw versions...assuming fw not buggy ! -+ */ -+ s->update = SUPPORTS_UPDATE_NOTIFY(attrl); -+ s->timestamped = SUPPORTS_TIMESTAMP(attrl); -+ if (s->timestamped) -+ s->tstamp_scale = -+ S32_EXT(SENSOR_TSTAMP_EXP(attrl)); -+ s->extended_scalar_attrs = -+ SUPPORTS_EXTEND_ATTRS(attrl); -+ -+ attrh = le32_to_cpu(sdesc->attributes_high); -+ /* common bitfields parsing */ -+ s->scale = S32_EXT(SENSOR_SCALE(attrh)); -+ s->type = SENSOR_TYPE(attrh); -+ /* Use pre-allocated pool wherever possible */ -+ s->intervals.desc = s->intervals.prealloc_pool; -+ if (si->version == SCMIv2_SENSOR_PROTOCOL) { -+ s->intervals.segmented = false; -+ s->intervals.count = 1; -+ /* -+ * Convert SCMIv2.0 update interval format to -+ * SCMIv3.0 to be used as the common exposed -+ * descriptor, accessible via common macros. -+ */ -+ s->intervals.desc[0] = -+ (SENSOR_UPDATE_BASE(attrh) << 5) | -+ SENSOR_UPDATE_SCALE(attrh); -+ } else { -+ /* -+ * From SCMIv3.0 update intervals are retrieved -+ * via a dedicated (optional) command. -+ * Since the command is optional, on error carry -+ * on without any update interval. -+ */ -+ if (scmi_sensor_update_intervals(handle, s)) -+ dev_dbg(handle->dev, -+ "Update Intervals not available for sensor ID:%d\n", -+ s->id); -+ } -+ /** -+ * only > SCMIv2.0 specific bitfield below. -+ * Such bitfields are assumed to be zeroed on non -+ * relevant fw versions...assuming fw not buggy ! -+ */ -+ s->num_axis = min_t(unsigned int, -+ SUPPORTS_AXIS(attrh) ? -+ SENSOR_AXIS_NUMBER(attrh) : 0, -+ SCMI_MAX_NUM_SENSOR_AXIS); -+ strlcpy(s->name, sdesc->name, SCMI_MAX_STR_SIZE); -+ -+ if (s->extended_scalar_attrs) { -+ s->sensor_power = le32_to_cpu(sdesc->power); -+ dsize += sizeof(sdesc->power); -+ /* Only for sensors reporting scalar values */ -+ if (s->num_axis == 0) { -+ unsigned int sres = -+ le32_to_cpu(sdesc->resolution); -+ -+ s->resolution = SENSOR_RES(sres); -+ s->exponent = -+ S32_EXT(SENSOR_RES_EXP(sres)); -+ dsize += sizeof(sdesc->resolution); -+ -+ scmi_parse_range_attrs(&s->scalar_attrs, -+ &sdesc->scalar_attrs); -+ dsize += sizeof(sdesc->scalar_attrs); -+ } -+ } -+ if (s->num_axis > 0) { -+ ret = scmi_sensor_axis_description(handle, s); -+ if (ret) -+ goto out; -+ } -+ -+ sdesc = (typeof(sdesc))((u8 *)sdesc + dsize); - } - - desc_index += num_returned; -@@ -174,19 +552,21 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, - */ - } while (num_returned && num_remaining); - -+out: - scmi_xfer_put(handle, t); - return ret; - } - --static int scmi_sensor_trip_point_notify(const struct scmi_handle *handle, -- u32 sensor_id, bool enable) -+static inline int -+scmi_sensor_request_notify(const struct scmi_handle *handle, u32 sensor_id, -+ u8 message_id, bool enable) - { - int ret; -- u32 evt_cntl = enable ? SENSOR_TP_NOTIFY_ALL : 0; -+ u32 evt_cntl = enable ? SENSOR_NOTIFY_ALL : 0; - struct scmi_xfer *t; -- struct scmi_msg_sensor_trip_point_notify *cfg; -+ struct scmi_msg_sensor_request_notify *cfg; - -- ret = scmi_xfer_get_init(handle, SENSOR_TRIP_POINT_NOTIFY, -+ ret = scmi_xfer_get_init(handle, message_id, - SCMI_PROTOCOL_SENSOR, sizeof(*cfg), 0, &t); - if (ret) - return ret; -@@ -201,6 +581,23 @@ static int scmi_sensor_trip_point_notify(const struct scmi_handle *handle, - return ret; - } - -+static int scmi_sensor_trip_point_notify(const struct scmi_handle *handle, -+ u32 sensor_id, bool enable) -+{ -+ return scmi_sensor_request_notify(handle, sensor_id, -+ SENSOR_TRIP_POINT_NOTIFY, -+ enable); -+} -+ -+static int -+scmi_sensor_continuous_update_notify(const struct scmi_handle *handle, -+ u32 sensor_id, bool enable) -+{ -+ return scmi_sensor_request_notify(handle, sensor_id, -+ SENSOR_CONTINUOUS_UPDATE_NOTIFY, -+ enable); -+} -+ - static int - scmi_sensor_trip_point_config(const struct scmi_handle *handle, u32 sensor_id, - u8 trip_id, u64 trip_value) -@@ -227,6 +624,75 @@ scmi_sensor_trip_point_config(const struct scmi_handle *handle, u32 sensor_id, - return ret; - } - -+static int scmi_sensor_config_get(const struct scmi_handle *handle, -+ u32 sensor_id, u32 *sensor_config) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ -+ ret = scmi_xfer_get_init(handle, SENSOR_CONFIG_GET, -+ SCMI_PROTOCOL_SENSOR, sizeof(__le32), -+ sizeof(__le32), &t); -+ if (ret) -+ return ret; -+ -+ put_unaligned_le32(cpu_to_le32(sensor_id), t->tx.buf); -+ ret = scmi_do_xfer(handle, t); -+ if (!ret) { -+ struct sensors_info *si = handle->sensor_priv; -+ struct scmi_sensor_info *s = si->sensors + sensor_id; -+ -+ *sensor_config = get_unaligned_le64(t->rx.buf); -+ s->sensor_config = *sensor_config; -+ } -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ -+static int scmi_sensor_config_set(const struct scmi_handle *handle, -+ u32 sensor_id, u32 sensor_config) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ struct scmi_msg_sensor_config_set *msg; -+ -+ ret = scmi_xfer_get_init(handle, SENSOR_CONFIG_SET, -+ SCMI_PROTOCOL_SENSOR, sizeof(*msg), 0, &t); -+ if (ret) -+ return ret; -+ -+ msg = t->tx.buf; -+ msg->id = cpu_to_le32(sensor_id); -+ msg->sensor_config = cpu_to_le32(sensor_config); -+ -+ ret = scmi_do_xfer(handle, t); -+ if (!ret) { -+ struct sensors_info *si = handle->sensor_priv; -+ struct scmi_sensor_info *s = si->sensors + sensor_id; -+ -+ s->sensor_config = sensor_config; -+ } -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ -+/** -+ * scmi_sensor_reading_get - Read scalar sensor value -+ * @handle: Platform handle -+ * @sensor_id: Sensor ID -+ * @value: The 64bit value sensor reading -+ * -+ * This function returns a single 64 bit reading value representing the sensor -+ * value; if the platform SCMI Protocol implementation and the sensor support -+ * multiple axis and timestamped-reads, this just returns the first axis while -+ * dropping the timestamp value. -+ * Use instead the @scmi_sensor_reading_get_timestamped to retrieve the array of -+ * timestamped multi-axis values. -+ * -+ * Return: 0 on Success -+ */ - static int scmi_sensor_reading_get(const struct scmi_handle *handle, - u32 sensor_id, u64 *value) - { -@@ -237,20 +703,24 @@ static int scmi_sensor_reading_get(const struct scmi_handle *handle, - struct scmi_sensor_info *s = si->sensors + sensor_id; - - ret = scmi_xfer_get_init(handle, SENSOR_READING_GET, -- SCMI_PROTOCOL_SENSOR, sizeof(*sensor), -- sizeof(u64), &t); -+ SCMI_PROTOCOL_SENSOR, sizeof(*sensor), 0, &t); - if (ret) - return ret; - - sensor = t->tx.buf; - sensor->id = cpu_to_le32(sensor_id); -- - if (s->async) { - sensor->flags = cpu_to_le32(SENSOR_READ_ASYNC); - ret = scmi_do_xfer_with_response(handle, t); -- if (!ret) -- *value = get_unaligned_le64((void *) -- ((__le32 *)t->rx.buf + 1)); -+ if (!ret) { -+ struct scmi_resp_sensor_reading_complete *resp; -+ -+ resp = t->rx.buf; -+ if (le32_to_cpu(resp->id) == sensor_id) -+ *value = get_unaligned_le64(&resp->readings); -+ else -+ ret = -EPROTO; -+ } - } else { - sensor->flags = cpu_to_le32(0); - ret = scmi_do_xfer(handle, t); -@@ -262,6 +732,84 @@ static int scmi_sensor_reading_get(const struct scmi_handle *handle, - return ret; - } - -+static inline void -+scmi_parse_sensor_readings(struct scmi_sensor_reading *out, -+ const struct scmi_sensor_reading_resp *in) -+{ -+ out->value = get_unaligned_le64((void *)&in->sensor_value_low); -+ out->timestamp = get_unaligned_le64((void *)&in->timestamp_low); -+} -+ -+/** -+ * scmi_sensor_reading_get_timestamped - Read multiple-axis timestamped values -+ * @handle: Platform handle -+ * @sensor_id: Sensor ID -+ * @count: The length of the provided @readings array -+ * @readings: An array of elements each representing a timestamped per-axis -+ * reading of type @struct scmi_sensor_reading. -+ * Returned readings are ordered as the @axis descriptors array -+ * included in @struct scmi_sensor_info and the max number of -+ * returned elements is min(@count, @num_axis); ideally the provided -+ * array should be of length @count equal to @num_axis. -+ * -+ * Return: 0 on Success -+ */ -+static int -+scmi_sensor_reading_get_timestamped(const struct scmi_handle *handle, -+ u32 sensor_id, u8 count, -+ struct scmi_sensor_reading *readings) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ struct scmi_msg_sensor_reading_get *sensor; -+ struct sensors_info *si = handle->sensor_priv; -+ struct scmi_sensor_info *s = si->sensors + sensor_id; -+ -+ if (!count || !readings || -+ (!s->num_axis && count > 1) || (s->num_axis && count > s->num_axis)) -+ return -EINVAL; -+ -+ ret = scmi_xfer_get_init(handle, SENSOR_READING_GET, -+ SCMI_PROTOCOL_SENSOR, sizeof(*sensor), 0, &t); -+ if (ret) -+ return ret; -+ -+ sensor = t->tx.buf; -+ sensor->id = cpu_to_le32(sensor_id); -+ if (s->async) { -+ sensor->flags = cpu_to_le32(SENSOR_READ_ASYNC); -+ ret = scmi_do_xfer_with_response(handle, t); -+ if (!ret) { -+ int i; -+ struct scmi_resp_sensor_reading_complete_v3 *resp; -+ -+ resp = t->rx.buf; -+ /* Retrieve only the number of requested axis anyway */ -+ if (le32_to_cpu(resp->id) == sensor_id) -+ for (i = 0; i < count; i++) -+ scmi_parse_sensor_readings(&readings[i], -+ &resp->readings[i]); -+ else -+ ret = -EPROTO; -+ } -+ } else { -+ sensor->flags = cpu_to_le32(0); -+ ret = scmi_do_xfer(handle, t); -+ if (!ret) { -+ int i; -+ struct scmi_sensor_reading_resp *resp_readings; -+ -+ resp_readings = t->rx.buf; -+ for (i = 0; i < count; i++) -+ scmi_parse_sensor_readings(&readings[i], -+ &resp_readings[i]); -+ } -+ } -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ - static const struct scmi_sensor_info * - scmi_sensor_info_get(const struct scmi_handle *handle, u32 sensor_id) - { -@@ -282,6 +830,9 @@ static const struct scmi_sensor_ops sensor_ops = { - .info_get = scmi_sensor_info_get, - .trip_point_config = scmi_sensor_trip_point_config, - .reading_get = scmi_sensor_reading_get, -+ .reading_get_timestamped = scmi_sensor_reading_get_timestamped, -+ .config_get = scmi_sensor_config_get, -+ .config_set = scmi_sensor_config_set, - }; - - static int scmi_sensor_set_notify_enabled(const struct scmi_handle *handle, -@@ -289,7 +840,19 @@ static int scmi_sensor_set_notify_enabled(const struct scmi_handle *handle, - { - int ret; - -- ret = scmi_sensor_trip_point_notify(handle, src_id, enable); -+ switch (evt_id) { -+ case SCMI_EVENT_SENSOR_TRIP_POINT_EVENT: -+ ret = scmi_sensor_trip_point_notify(handle, src_id, enable); -+ break; -+ case SCMI_EVENT_SENSOR_UPDATE: -+ ret = scmi_sensor_continuous_update_notify(handle, src_id, -+ enable); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ - if (ret) - pr_debug("FAIL_ENABLED - evt[%X] dom[%d] - ret:%d\n", - evt_id, src_id, ret); -@@ -302,20 +865,59 @@ static void *scmi_sensor_fill_custom_report(const struct scmi_handle *handle, - const void *payld, size_t payld_sz, - void *report, u32 *src_id) - { -- const struct scmi_sensor_trip_notify_payld *p = payld; -- struct scmi_sensor_trip_point_report *r = report; -+ void *rep = NULL; -+ -+ switch (evt_id) { -+ case SCMI_EVENT_SENSOR_TRIP_POINT_EVENT: -+ { -+ const struct scmi_sensor_trip_notify_payld *p = payld; -+ struct scmi_sensor_trip_point_report *r = report; - -- if (evt_id != SCMI_EVENT_SENSOR_TRIP_POINT_EVENT || -- sizeof(*p) != payld_sz) -- return NULL; -+ if (sizeof(*p) != payld_sz) -+ break; - -- r->timestamp = timestamp; -- r->agent_id = le32_to_cpu(p->agent_id); -- r->sensor_id = le32_to_cpu(p->sensor_id); -- r->trip_point_desc = le32_to_cpu(p->trip_point_desc); -- *src_id = r->sensor_id; -+ r->timestamp = timestamp; -+ r->agent_id = le32_to_cpu(p->agent_id); -+ r->sensor_id = le32_to_cpu(p->sensor_id); -+ r->trip_point_desc = le32_to_cpu(p->trip_point_desc); -+ *src_id = r->sensor_id; -+ rep = r; -+ break; -+ } -+ case SCMI_EVENT_SENSOR_UPDATE: -+ { -+ int i; -+ struct scmi_sensor_info *s; -+ const struct scmi_sensor_update_notify_payld *p = payld; -+ struct scmi_sensor_update_report *r = report; -+ struct sensors_info *sinfo = handle->sensor_priv; -+ -+ /* payld_sz is variable for this event */ -+ r->sensor_id = le32_to_cpu(p->sensor_id); -+ if (r->sensor_id >= sinfo->num_sensors) -+ break; -+ r->timestamp = timestamp; -+ r->agent_id = le32_to_cpu(p->agent_id); -+ s = &sinfo->sensors[r->sensor_id]; -+ /* -+ * The generated report r (@struct scmi_sensor_update_report) -+ * was pre-allocated to contain up to SCMI_MAX_NUM_SENSOR_AXIS -+ * readings: here it is filled with the effective @num_axis -+ * readings defined for this sensor or 1 for scalar sensors. -+ */ -+ r->readings_count = s->num_axis ?: 1; -+ for (i = 0; i < r->readings_count; i++) -+ scmi_parse_sensor_readings(&r->readings[i], -+ &p->readings[i]); -+ *src_id = r->sensor_id; -+ rep = r; -+ break; -+ } -+ default: -+ break; -+ } - -- return r; -+ return rep; - } - - static const struct scmi_event sensor_events[] = { -@@ -324,6 +926,16 @@ static const struct scmi_event sensor_events[] = { - .max_payld_sz = sizeof(struct scmi_sensor_trip_notify_payld), - .max_report_sz = sizeof(struct scmi_sensor_trip_point_report), - }, -+ { -+ .id = SCMI_EVENT_SENSOR_UPDATE, -+ .max_payld_sz = -+ sizeof(struct scmi_sensor_update_notify_payld) + -+ SCMI_MAX_NUM_SENSOR_AXIS * -+ sizeof(struct scmi_sensor_reading_resp), -+ .max_report_sz = sizeof(struct scmi_sensor_update_report) + -+ SCMI_MAX_NUM_SENSOR_AXIS * -+ sizeof(struct scmi_sensor_reading), -+ }, - }; - - static const struct scmi_event_ops sensor_event_ops = { -@@ -334,6 +946,7 @@ static const struct scmi_event_ops sensor_event_ops = { - static int scmi_sensors_protocol_init(struct scmi_handle *handle) - { - u32 version; -+ int ret; - struct sensors_info *sinfo; - - scmi_version_get(handle, SCMI_PROTOCOL_SENSOR, &version); -@@ -344,15 +957,19 @@ static int scmi_sensors_protocol_init(struct scmi_handle *handle) - sinfo = devm_kzalloc(handle->dev, sizeof(*sinfo), GFP_KERNEL); - if (!sinfo) - return -ENOMEM; -+ sinfo->version = version; - -- scmi_sensor_attributes_get(handle, sinfo); -- -+ ret = scmi_sensor_attributes_get(handle, sinfo); -+ if (ret) -+ return ret; - sinfo->sensors = devm_kcalloc(handle->dev, sinfo->num_sensors, - sizeof(*sinfo->sensors), GFP_KERNEL); - if (!sinfo->sensors) - return -ENOMEM; - -- scmi_sensor_description_get(handle, sinfo); -+ ret = scmi_sensor_description_get(handle, sinfo); -+ if (ret) -+ return ret; - - scmi_register_protocol_events(handle, - SCMI_PROTOCOL_SENSOR, SCMI_PROTO_QUEUE_SZ, -@@ -360,9 +977,8 @@ static int scmi_sensors_protocol_init(struct scmi_handle *handle) - ARRAY_SIZE(sensor_events), - sinfo->num_sensors); - -- sinfo->version = version; -- handle->sensor_ops = &sensor_ops; - handle->sensor_priv = sinfo; -+ handle->sensor_ops = &sensor_ops; - - return 0; - } -diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c -index 82a82a5dc..fcbe2677f 100644 ---- a/drivers/firmware/arm_scmi/smc.c -+++ b/drivers/firmware/arm_scmi/smc.c -@@ -9,9 +9,11 @@ - #include - #include - #include -+#include - #include - #include - #include -+#include - #include - - #include "common.h" -@@ -23,6 +25,8 @@ - * @shmem: Transmit/Receive shared memory area - * @shmem_lock: Lock to protect access to Tx/Rx shared memory area - * @func_id: smc/hvc call function id -+ * @irq: Optional; employed when platforms indicates msg completion by intr. -+ * @tx_complete: Optional, employed only when irq is valid. - */ - - struct scmi_smc { -@@ -30,8 +34,19 @@ struct scmi_smc { - struct scmi_shared_mem __iomem *shmem; - struct mutex shmem_lock; - u32 func_id; -+ int irq; -+ struct completion tx_complete; - }; - -+static irqreturn_t smc_msg_done_isr(int irq, void *data) -+{ -+ struct scmi_smc *scmi_info = data; -+ -+ complete(&scmi_info->tx_complete); -+ -+ return IRQ_HANDLED; -+} -+ - static bool smc_chan_available(struct device *dev, int idx) - { - struct device_node *np = of_parse_phandle(dev->of_node, "shmem", 0); -@@ -51,7 +66,7 @@ static int smc_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, - struct resource res; - struct device_node *np; - u32 func_id; -- int ret; -+ int ret, irq; - - if (!tx) - return -ENODEV; -@@ -79,6 +94,24 @@ static int smc_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, - if (ret < 0) - return ret; - -+ /* -+ * If there is an interrupt named "a2p", then the service and -+ * completion of a message is signaled by an interrupt rather than by -+ * the return of the SMC call. -+ */ -+ irq = of_irq_get_byname(cdev->of_node, "a2p"); -+ if (irq > 0) { -+ ret = devm_request_irq(dev, irq, smc_msg_done_isr, -+ IRQF_NO_SUSPEND, -+ dev_name(dev), scmi_info); -+ if (ret) { -+ dev_err(dev, "failed to setup SCMI smc irq\n"); -+ return ret; -+ } -+ init_completion(&scmi_info->tx_complete); -+ scmi_info->irq = irq; -+ } -+ - scmi_info->func_id = func_id; - scmi_info->cinfo = cinfo; - mutex_init(&scmi_info->shmem_lock); -@@ -110,7 +143,14 @@ static int smc_send_message(struct scmi_chan_info *cinfo, - - shmem_tx_prepare(scmi_info->shmem, xfer); - -+ if (scmi_info->irq) -+ reinit_completion(&scmi_info->tx_complete); -+ - arm_smccc_1_1_invoke(scmi_info->func_id, 0, 0, 0, 0, 0, 0, 0, &res); -+ -+ if (scmi_info->irq) -+ wait_for_completion(&scmi_info->tx_complete); -+ - scmi_rx_callback(scmi_info->cinfo, shmem_read_header(scmi_info->shmem)); - - mutex_unlock(&scmi_info->shmem_lock); -diff --git a/drivers/firmware/arm_scmi/voltage.c b/drivers/firmware/arm_scmi/voltage.c -new file mode 100644 -index 000000000..e794e4349 ---- /dev/null -+++ b/drivers/firmware/arm_scmi/voltage.c -@@ -0,0 +1,380 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * System Control and Management Interface (SCMI) Voltage Protocol -+ * -+ * Copyright (C) 2020 ARM Ltd. -+ */ -+ -+#include -+ -+#include "common.h" -+ -+#define VOLTAGE_DOMS_NUM_MASK GENMASK(15, 0) -+#define REMAINING_LEVELS_MASK GENMASK(31, 16) -+#define RETURNED_LEVELS_MASK GENMASK(11, 0) -+ -+enum scmi_voltage_protocol_cmd { -+ VOLTAGE_DOMAIN_ATTRIBUTES = 0x3, -+ VOLTAGE_DESCRIBE_LEVELS = 0x4, -+ VOLTAGE_CONFIG_SET = 0x5, -+ VOLTAGE_CONFIG_GET = 0x6, -+ VOLTAGE_LEVEL_SET = 0x7, -+ VOLTAGE_LEVEL_GET = 0x8, -+}; -+ -+#define NUM_VOLTAGE_DOMAINS(x) ((u16)(FIELD_GET(VOLTAGE_DOMS_NUM_MASK, (x)))) -+ -+struct scmi_msg_resp_domain_attributes { -+ __le32 attr; -+ u8 name[SCMI_MAX_STR_SIZE]; -+}; -+ -+struct scmi_msg_cmd_describe_levels { -+ __le32 domain_id; -+ __le32 level_index; -+}; -+ -+struct scmi_msg_resp_describe_levels { -+ __le32 flags; -+#define NUM_REMAINING_LEVELS(f) ((u16)(FIELD_GET(REMAINING_LEVELS_MASK, (f)))) -+#define NUM_RETURNED_LEVELS(f) ((u16)(FIELD_GET(RETURNED_LEVELS_MASK, (f)))) -+#define SUPPORTS_SEGMENTED_LEVELS(f) ((f) & BIT(12)) -+ __le32 voltage[]; -+}; -+ -+struct scmi_msg_cmd_config_set { -+ __le32 domain_id; -+ __le32 config; -+}; -+ -+struct scmi_msg_cmd_level_set { -+ __le32 domain_id; -+ __le32 flags; -+ __le32 voltage_level; -+}; -+ -+struct voltage_info { -+ unsigned int version; -+ unsigned int num_domains; -+ struct scmi_voltage_info *domains; -+}; -+ -+static int scmi_protocol_attributes_get(const struct scmi_handle *handle, -+ struct voltage_info *vinfo) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ -+ ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES, -+ SCMI_PROTOCOL_VOLTAGE, 0, sizeof(__le32), &t); -+ if (ret) -+ return ret; -+ -+ ret = scmi_do_xfer(handle, t); -+ if (!ret) -+ vinfo->num_domains = -+ NUM_VOLTAGE_DOMAINS(get_unaligned_le32(t->rx.buf)); -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ -+static int scmi_init_voltage_levels(struct device *dev, -+ struct scmi_voltage_info *v, -+ u32 num_returned, u32 num_remaining, -+ bool segmented) -+{ -+ u32 num_levels; -+ -+ num_levels = num_returned + num_remaining; -+ /* -+ * segmented levels entries are represented by a single triplet -+ * returned all in one go. -+ */ -+ if (!num_levels || -+ (segmented && (num_remaining || num_returned != 3))) { -+ dev_err(dev, -+ "Invalid level descriptor(%d/%d/%d) for voltage dom %d\n", -+ num_levels, num_returned, num_remaining, v->id); -+ return -EINVAL; -+ } -+ -+ v->levels_uv = devm_kcalloc(dev, num_levels, sizeof(u32), GFP_KERNEL); -+ if (!v->levels_uv) -+ return -ENOMEM; -+ -+ v->num_levels = num_levels; -+ v->segmented = segmented; -+ -+ return 0; -+} -+ -+static int scmi_voltage_descriptors_get(const struct scmi_handle *handle, -+ struct voltage_info *vinfo) -+{ -+ int ret, dom; -+ struct scmi_xfer *td, *tl; -+ struct device *dev = handle->dev; -+ struct scmi_msg_resp_domain_attributes *resp_dom; -+ struct scmi_msg_resp_describe_levels *resp_levels; -+ -+ ret = scmi_xfer_get_init(handle, VOLTAGE_DOMAIN_ATTRIBUTES, -+ SCMI_PROTOCOL_VOLTAGE, sizeof(__le32), -+ sizeof(*resp_dom), &td); -+ if (ret) -+ return ret; -+ resp_dom = td->rx.buf; -+ -+ ret = scmi_xfer_get_init(handle, VOLTAGE_DESCRIBE_LEVELS, -+ SCMI_PROTOCOL_VOLTAGE, sizeof(__le64), 0, &tl); -+ if (ret) -+ goto outd; -+ resp_levels = tl->rx.buf; -+ -+ for (dom = 0; dom < vinfo->num_domains; dom++) { -+ u32 desc_index = 0; -+ u16 num_returned = 0, num_remaining = 0; -+ struct scmi_msg_cmd_describe_levels *cmd; -+ struct scmi_voltage_info *v; -+ -+ /* Retrieve domain attributes at first ... */ -+ put_unaligned_le32(dom, td->tx.buf); -+ ret = scmi_do_xfer(handle, td); -+ /* Skip domain on comms error */ -+ if (ret) -+ continue; -+ -+ v = vinfo->domains + dom; -+ v->id = dom; -+ v->attributes = le32_to_cpu(resp_dom->attr); -+ strlcpy(v->name, resp_dom->name, SCMI_MAX_STR_SIZE); -+ -+ cmd = tl->tx.buf; -+ /* ...then retrieve domain levels descriptions */ -+ do { -+ u32 flags; -+ int cnt; -+ -+ cmd->domain_id = cpu_to_le32(v->id); -+ cmd->level_index = desc_index; -+ ret = scmi_do_xfer(handle, tl); -+ if (ret) -+ break; -+ -+ flags = le32_to_cpu(resp_levels->flags); -+ num_returned = NUM_RETURNED_LEVELS(flags); -+ num_remaining = NUM_REMAINING_LEVELS(flags); -+ -+ /* Allocate space for num_levels if not already done */ -+ if (!v->num_levels) { -+ ret = scmi_init_voltage_levels(dev, v, -+ num_returned, -+ num_remaining, -+ SUPPORTS_SEGMENTED_LEVELS(flags)); -+ if (ret) -+ break; -+ } -+ -+ if (desc_index + num_returned > v->num_levels) { -+ dev_err(handle->dev, -+ "No. of voltage levels can't exceed %d\n", -+ v->num_levels); -+ ret = -EINVAL; -+ break; -+ } -+ -+ for (cnt = 0; cnt < num_returned; cnt++) { -+ s32 val; -+ -+ val = -+ (s32)le32_to_cpu(resp_levels->voltage[cnt]); -+ v->levels_uv[desc_index + cnt] = val; -+ if (val < 0) -+ v->negative_volts_allowed = true; -+ } -+ -+ desc_index += num_returned; -+ -+ scmi_reset_rx_to_maxsz(handle, tl); -+ /* check both to avoid infinite loop due to buggy fw */ -+ } while (num_returned && num_remaining); -+ -+ if (ret) { -+ v->num_levels = 0; -+ devm_kfree(dev, v->levels_uv); -+ } -+ -+ scmi_reset_rx_to_maxsz(handle, td); -+ } -+ -+ scmi_xfer_put(handle, tl); -+outd: -+ scmi_xfer_put(handle, td); -+ -+ return ret; -+} -+ -+static int __scmi_voltage_get_u32(const struct scmi_handle *handle, -+ u8 cmd_id, u32 domain_id, u32 *value) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ struct voltage_info *vinfo = handle->voltage_priv; -+ -+ if (domain_id >= vinfo->num_domains) -+ return -EINVAL; -+ -+ ret = scmi_xfer_get_init(handle, cmd_id, -+ SCMI_PROTOCOL_VOLTAGE, -+ sizeof(__le32), 0, &t); -+ if (ret) -+ return ret; -+ -+ put_unaligned_le32(domain_id, t->tx.buf); -+ ret = scmi_do_xfer(handle, t); -+ if (!ret) -+ *value = get_unaligned_le32(t->rx.buf); -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ -+static int scmi_voltage_config_set(const struct scmi_handle *handle, -+ u32 domain_id, u32 config) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ struct voltage_info *vinfo = handle->voltage_priv; -+ struct scmi_msg_cmd_config_set *cmd; -+ -+ if (domain_id >= vinfo->num_domains) -+ return -EINVAL; -+ -+ ret = scmi_xfer_get_init(handle, VOLTAGE_CONFIG_SET, -+ SCMI_PROTOCOL_VOLTAGE, -+ sizeof(*cmd), 0, &t); -+ if (ret) -+ return ret; -+ -+ cmd = t->tx.buf; -+ cmd->domain_id = cpu_to_le32(domain_id); -+ cmd->config = cpu_to_le32(config & GENMASK(3, 0)); -+ -+ ret = scmi_do_xfer(handle, t); -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ -+static int scmi_voltage_config_get(const struct scmi_handle *handle, -+ u32 domain_id, u32 *config) -+{ -+ return __scmi_voltage_get_u32(handle, VOLTAGE_CONFIG_GET, -+ domain_id, config); -+} -+ -+static int scmi_voltage_level_set(const struct scmi_handle *handle, -+ u32 domain_id, u32 flags, s32 volt_uV) -+{ -+ int ret; -+ struct scmi_xfer *t; -+ struct voltage_info *vinfo = handle->voltage_priv; -+ struct scmi_msg_cmd_level_set *cmd; -+ -+ if (domain_id >= vinfo->num_domains) -+ return -EINVAL; -+ -+ ret = scmi_xfer_get_init(handle, VOLTAGE_LEVEL_SET, -+ SCMI_PROTOCOL_VOLTAGE, -+ sizeof(*cmd), 0, &t); -+ if (ret) -+ return ret; -+ -+ cmd = t->tx.buf; -+ cmd->domain_id = cpu_to_le32(domain_id); -+ cmd->flags = cpu_to_le32(flags); -+ cmd->voltage_level = cpu_to_le32(volt_uV); -+ -+ ret = scmi_do_xfer(handle, t); -+ -+ scmi_xfer_put(handle, t); -+ return ret; -+} -+ -+static int scmi_voltage_level_get(const struct scmi_handle *handle, -+ u32 domain_id, s32 *volt_uV) -+{ -+ return __scmi_voltage_get_u32(handle, VOLTAGE_LEVEL_GET, -+ domain_id, (u32 *)volt_uV); -+} -+ -+static const struct scmi_voltage_info * __must_check -+scmi_voltage_info_get(const struct scmi_handle *handle, u32 domain_id) -+{ -+ struct voltage_info *vinfo = handle->voltage_priv; -+ -+ if (domain_id >= vinfo->num_domains || -+ !vinfo->domains[domain_id].num_levels) -+ return NULL; -+ -+ return vinfo->domains + domain_id; -+} -+ -+static int scmi_voltage_domains_num_get(const struct scmi_handle *handle) -+{ -+ struct voltage_info *vinfo = handle->voltage_priv; -+ -+ return vinfo->num_domains; -+} -+ -+static struct scmi_voltage_ops voltage_ops = { -+ .num_domains_get = scmi_voltage_domains_num_get, -+ .info_get = scmi_voltage_info_get, -+ .config_set = scmi_voltage_config_set, -+ .config_get = scmi_voltage_config_get, -+ .level_set = scmi_voltage_level_set, -+ .level_get = scmi_voltage_level_get, -+}; -+ -+static int scmi_voltage_protocol_init(struct scmi_handle *handle) -+{ -+ int ret; -+ u32 version; -+ struct voltage_info *vinfo; -+ -+ ret = scmi_version_get(handle, SCMI_PROTOCOL_VOLTAGE, &version); -+ if (ret) -+ return ret; -+ -+ dev_dbg(handle->dev, "Voltage Version %d.%d\n", -+ PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); -+ -+ vinfo = devm_kzalloc(handle->dev, sizeof(*vinfo), GFP_KERNEL); -+ if (!vinfo) -+ return -ENOMEM; -+ vinfo->version = version; -+ -+ ret = scmi_protocol_attributes_get(handle, vinfo); -+ if (ret) -+ return ret; -+ -+ if (vinfo->num_domains) { -+ vinfo->domains = devm_kcalloc(handle->dev, vinfo->num_domains, -+ sizeof(*vinfo->domains), -+ GFP_KERNEL); -+ if (!vinfo->domains) -+ return -ENOMEM; -+ ret = scmi_voltage_descriptors_get(handle, vinfo); -+ if (ret) -+ return ret; -+ } else { -+ dev_warn(handle->dev, "No Voltage domains found.\n"); -+ } -+ -+ handle->voltage_ops = &voltage_ops; -+ handle->voltage_priv = vinfo; -+ -+ return 0; -+} -+ -+DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(SCMI_PROTOCOL_VOLTAGE, voltage) -diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile -index b76acbade..f23e2b0f3 100644 ---- a/drivers/firmware/imx/Makefile -+++ b/drivers/firmware/imx/Makefile -@@ -1,4 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_IMX_DSP) += imx-dsp.o --obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o -+obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o seco.o - obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o -diff --git a/drivers/firmware/imx/imx-dsp.c b/drivers/firmware/imx/imx-dsp.c -index 4265e9dbe..a6c06d747 100644 ---- a/drivers/firmware/imx/imx-dsp.c -+++ b/drivers/firmware/imx/imx-dsp.c -@@ -60,22 +60,40 @@ static void imx_dsp_handle_rx(struct mbox_client *c, void *msg) - } - } - --static int imx_dsp_probe(struct platform_device *pdev) -+struct mbox_chan *imx_dsp_request_channel(struct imx_dsp_ipc *dsp_ipc, int idx) - { -- struct device *dev = &pdev->dev; -- struct imx_dsp_ipc *dsp_ipc; -+ struct imx_dsp_chan *dsp_chan; -+ -+ if (idx >= DSP_MU_CHAN_NUM) -+ return ERR_PTR(-EINVAL); -+ -+ dsp_chan = &dsp_ipc->chans[idx]; -+ dsp_chan->ch = mbox_request_channel_byname(&dsp_chan->cl, dsp_chan->name); -+ return dsp_chan->ch; -+} -+EXPORT_SYMBOL(imx_dsp_request_channel); -+ -+void imx_dsp_free_channel(struct imx_dsp_ipc *dsp_ipc, int idx) -+{ -+ struct imx_dsp_chan *dsp_chan; -+ -+ if (idx >= DSP_MU_CHAN_NUM) -+ return; -+ -+ dsp_chan = &dsp_ipc->chans[idx]; -+ mbox_free_channel(dsp_chan->ch); -+} -+EXPORT_SYMBOL(imx_dsp_free_channel); -+ -+static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc) -+{ -+ struct device *dev = dsp_ipc->dev; - struct imx_dsp_chan *dsp_chan; - struct mbox_client *cl; - char *chan_name; - int ret; - int i, j; - -- device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); -- -- dsp_ipc = devm_kzalloc(dev, sizeof(*dsp_ipc), GFP_KERNEL); -- if (!dsp_ipc) -- return -ENOMEM; -- - for (i = 0; i < DSP_MU_CHAN_NUM; i++) { - if (i < 2) - chan_name = kasprintf(GFP_KERNEL, "txdb%d", i); -@@ -86,6 +104,7 @@ static int imx_dsp_probe(struct platform_device *pdev) - return -ENOMEM; - - dsp_chan = &dsp_ipc->chans[i]; -+ dsp_chan->name = chan_name; - cl = &dsp_chan->cl; - cl->dev = dev; - cl->tx_block = false; -@@ -104,27 +123,43 @@ static int imx_dsp_probe(struct platform_device *pdev) - } - - dev_dbg(dev, "request mbox chan %s\n", chan_name); -- /* chan_name is not used anymore by framework */ -- kfree(chan_name); - } - -- dsp_ipc->dev = dev; -- -- dev_set_drvdata(dev, dsp_ipc); -- -- dev_info(dev, "NXP i.MX DSP IPC initialized\n"); -- - return 0; - out: -- kfree(chan_name); - for (j = 0; j < i; j++) { - dsp_chan = &dsp_ipc->chans[j]; - mbox_free_channel(dsp_chan->ch); -+ kfree(dsp_chan->name); - } - - return ret; - } - -+static int imx_dsp_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct imx_dsp_ipc *dsp_ipc; -+ int ret; -+ -+ device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); -+ -+ dsp_ipc = devm_kzalloc(dev, sizeof(*dsp_ipc), GFP_KERNEL); -+ if (!dsp_ipc) -+ return -ENOMEM; -+ -+ dsp_ipc->dev = dev; -+ dev_set_drvdata(dev, dsp_ipc); -+ -+ ret = imx_dsp_setup_channels(dsp_ipc); -+ if (ret < 0) -+ return ret; -+ -+ dev_info(dev, "NXP i.MX DSP IPC initialized\n"); -+ -+ return 0; -+} -+ - static int imx_dsp_remove(struct platform_device *pdev) - { - struct imx_dsp_chan *dsp_chan; -@@ -136,6 +171,7 @@ static int imx_dsp_remove(struct platform_device *pdev) - for (i = 0; i < DSP_MU_CHAN_NUM; i++) { - dsp_chan = &dsp_ipc->chans[i]; - mbox_free_channel(dsp_chan->ch); -+ kfree(dsp_chan->name); - } - - return 0; -diff --git a/drivers/firmware/imx/imx-scu-irq.c b/drivers/firmware/imx/imx-scu-irq.c -index d9dcc2094..cc081a6a1 100644 ---- a/drivers/firmware/imx/imx-scu-irq.c -+++ b/drivers/firmware/imx/imx-scu-irq.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * Copyright 2019 NXP -+ * Copyright 2019-2020 NXP - * - * Implementation of the SCU IRQ functions using MU. - * -@@ -14,7 +14,7 @@ - - #define IMX_SC_IRQ_FUNC_ENABLE 1 - #define IMX_SC_IRQ_FUNC_STATUS 2 --#define IMX_SC_IRQ_NUM_GROUP 4 -+#define IMX_SC_IRQ_NUM_GROUP 7 - - static u32 mu_resource_id; - -@@ -42,53 +42,42 @@ struct imx_sc_msg_irq_enable { - - static struct imx_sc_ipc *imx_sc_irq_ipc_handle; - static struct work_struct imx_sc_irq_work; --static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); -+static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); - - int imx_scu_irq_register_notifier(struct notifier_block *nb) - { -- return atomic_notifier_chain_register( -+ return blocking_notifier_chain_register( - &imx_scu_irq_notifier_chain, nb); - } - EXPORT_SYMBOL(imx_scu_irq_register_notifier); - - int imx_scu_irq_unregister_notifier(struct notifier_block *nb) - { -- return atomic_notifier_chain_unregister( -+ return blocking_notifier_chain_unregister( - &imx_scu_irq_notifier_chain, nb); - } - EXPORT_SYMBOL(imx_scu_irq_unregister_notifier); - - static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group) - { -- return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain, -+ return blocking_notifier_call_chain(&imx_scu_irq_notifier_chain, - status, (void *)group); - } - - static void imx_scu_irq_work_handler(struct work_struct *work) - { -- struct imx_sc_msg_irq_get_status msg; -- struct imx_sc_rpc_msg *hdr = &msg.hdr; - u32 irq_status; - int ret; - u8 i; - - for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { -- hdr->ver = IMX_SC_RPC_VERSION; -- hdr->svc = IMX_SC_RPC_SVC_IRQ; -- hdr->func = IMX_SC_IRQ_FUNC_STATUS; -- hdr->size = 2; -- -- msg.data.req.resource = mu_resource_id; -- msg.data.req.group = i; -- -- ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); -+ ret = imx_scu_irq_get_status(i, &irq_status); - if (ret) { - pr_err("get irq group %d status failed, ret %d\n", - i, ret); - return; - } - -- irq_status = msg.data.resp.status; - if (!irq_status) - continue; - -@@ -97,6 +86,31 @@ static void imx_scu_irq_work_handler(struct work_struct *work) - } - } - -+int imx_scu_irq_get_status(u8 group, u32 *irq_status) -+{ -+ struct imx_sc_msg_irq_get_status msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_IRQ; -+ hdr->func = IMX_SC_IRQ_FUNC_STATUS; -+ hdr->size = 2; -+ -+ msg.data.req.resource = mu_resource_id; -+ msg.data.req.group = group; -+ -+ ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); -+ if (ret) -+ return ret; -+ -+ if (irq_status) -+ *irq_status = msg.data.resp.status; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_scu_irq_get_status); -+ - int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) - { - struct imx_sc_msg_irq_enable msg; -diff --git a/drivers/firmware/imx/imx-scu-soc.c b/drivers/firmware/imx/imx-scu-soc.c -index 2f32353de..c8d14315d 100644 ---- a/drivers/firmware/imx/imx-scu-soc.c -+++ b/drivers/firmware/imx/imx-scu-soc.c -@@ -12,6 +12,8 @@ - - static struct imx_sc_ipc *imx_sc_soc_ipc_handle; - -+extern bool TKT340553_SW_WORKAROUND; -+ - struct imx_sc_msg_misc_get_soc_id { - struct imx_sc_rpc_msg hdr; - union { -@@ -35,18 +37,15 @@ static int imx_scu_soc_uid(u64 *soc_uid) - { - struct imx_sc_msg_misc_get_soc_uid msg; - struct imx_sc_rpc_msg *hdr = &msg.hdr; -- int ret; -+ -+ memset(&msg, 0, sizeof(msg)); - - hdr->ver = IMX_SC_RPC_VERSION; - hdr->svc = IMX_SC_RPC_SVC_MISC; - hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID; - hdr->size = 1; - -- ret = imx_scu_call_rpc(imx_sc_soc_ipc_handle, &msg, true); -- if (ret) { -- pr_err("%s: get soc uid failed, ret %d\n", __func__, ret); -- return ret; -- } -+ imx_scu_call_rpc(imx_sc_soc_ipc_handle, &msg, true); - - *soc_uid = msg.uid_high; - *soc_uid <<= 32; -@@ -113,9 +112,13 @@ int imx_scu_soc_init(struct device *dev) - - /* format soc_id value passed from SCU firmware */ - val = id & 0x1f; -- soc_dev_attr->soc_id = devm_kasprintf(dev, GFP_KERNEL, "0x%x", val); -- if (!soc_dev_attr->soc_id) -- return -ENOMEM; -+ if (of_machine_is_compatible("fsl,imx8qm")) { -+ soc_dev_attr->soc_id = "i.MX8QM"; -+ TKT340553_SW_WORKAROUND = true; -+ } else if (of_machine_is_compatible("fsl,imx8qxp")) -+ soc_dev_attr->soc_id = "i.MX8QXP"; -+ else if (of_machine_is_compatible("fsl,imx8dxl")) -+ soc_dev_attr->soc_id = "i.MX8DXL"; - - /* format revision value passed from SCU firmware */ - val = (id >> 5) & 0xf; -diff --git a/drivers/firmware/imx/imx-scu.c b/drivers/firmware/imx/imx-scu.c -index dca79cacc..fd6de5771 100644 ---- a/drivers/firmware/imx/imx-scu.c -+++ b/drivers/firmware/imx/imx-scu.c -@@ -7,6 +7,7 @@ - * - */ - -+#include - #include - #include - #include -@@ -19,8 +20,11 @@ - #include - #include - -+#include -+ -+#define FSL_HVC_SC 0xC6000000 - #define SCU_MU_CHAN_NUM 8 --#define MAX_RX_TIMEOUT (msecs_to_jiffies(30)) -+#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) - - struct imx_sc_chan { - struct imx_sc_ipc *sc_ipc; -@@ -204,6 +208,7 @@ int imx_scu_call_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp) - { - uint8_t saved_svc, saved_func; - struct imx_sc_rpc_msg *hdr; -+ struct arm_smccc_res res; - int ret; - - if (WARN_ON(!sc_ipc || !msg)) -@@ -218,33 +223,45 @@ int imx_scu_call_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp) - saved_func = ((struct imx_sc_rpc_msg *)msg)->func; - } - sc_ipc->count = 0; -- ret = imx_scu_ipc_write(sc_ipc, msg); -- if (ret < 0) { -- dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); -- goto out; -- } -- -- if (have_resp) { -- if (!wait_for_completion_timeout(&sc_ipc->done, -- MAX_RX_TIMEOUT)) { -- dev_err(sc_ipc->dev, "RPC send msg timeout\n"); -- mutex_unlock(&sc_ipc->lock); -- return -ETIMEDOUT; -+ sc_ipc->rx_size = 0; -+ if (xen_initial_domain()) { -+ arm_smccc_hvc(FSL_HVC_SC, (uint64_t)msg, !have_resp, 0, 0, 0, -+ 0, 0, &res); -+ if (res.a0) -+ printk("Error FSL_HVC_SC %ld\n", res.a0); -+ -+ ret = res.a0; -+ -+ } else { -+ ret = imx_scu_ipc_write(sc_ipc, msg); -+ if (ret < 0) { -+ dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); -+ goto out; - } - -- /* response status is stored in hdr->func field */ -- hdr = msg; -- ret = hdr->func; -- /* -- * Some special SCU firmware APIs do NOT have return value -- * in hdr->func, but they do have response data, those special -- * APIs are defined as void function in SCU firmware, so they -- * should be treated as return success always. -- */ -- if ((saved_svc == IMX_SC_RPC_SVC_MISC) && -- (saved_func == IMX_SC_MISC_FUNC_UNIQUE_ID || -- saved_func == IMX_SC_MISC_FUNC_GET_BUTTON_STATUS)) -- ret = 0; -+ if (have_resp) { -+ if (!wait_for_completion_timeout(&sc_ipc->done, -+ MAX_RX_TIMEOUT)) { -+ dev_err(sc_ipc->dev, "RPC send msg timeout\n"); -+ mutex_unlock(&sc_ipc->lock); -+ return -ETIMEDOUT; -+ } -+ -+ /* response status is stored in hdr->func field */ -+ hdr = msg; -+ ret = hdr->func; -+ -+ /* -+ * Some special SCU firmware APIs do NOT have return value -+ * in hdr->func, but they do have response data, those special -+ * APIs are defined as void function in SCU firmware, so they -+ * should be treated as return success always. -+ */ -+ if ((saved_svc == IMX_SC_RPC_SVC_MISC) && -+ (saved_func == IMX_SC_MISC_FUNC_UNIQUE_ID || -+ saved_func == IMX_SC_MISC_FUNC_GET_BUTTON_STATUS)) -+ ret = 0; -+ } - } - - out: -@@ -354,7 +371,12 @@ static struct platform_driver imx_scu_driver = { - }, - .probe = imx_scu_probe, - }; --builtin_platform_driver(imx_scu_driver); -+ -+static int __init imx_scu_driver_init(void) -+{ -+ return platform_driver_register(&imx_scu_driver); -+} -+subsys_initcall_sync(imx_scu_driver_init); - - MODULE_AUTHOR("Dong Aisheng "); - MODULE_DESCRIPTION("IMX SCU firmware protocol driver"); -diff --git a/drivers/firmware/imx/misc.c b/drivers/firmware/imx/misc.c -index d073cb3ce..01878451d 100644 ---- a/drivers/firmware/imx/misc.c -+++ b/drivers/firmware/imx/misc.c -@@ -18,6 +18,13 @@ struct imx_sc_msg_req_misc_set_ctrl { - u16 resource; - } __packed __aligned(4); - -+ -+struct imx_sc_msg_req_misc_set_dma_group { -+ struct imx_sc_rpc_msg hdr; -+ u16 resource; -+ u8 val; -+} __packed __aligned(4); -+ - struct imx_sc_msg_req_cpu_start { - struct imx_sc_rpc_msg hdr; - u32 address_hi; -@@ -67,6 +74,24 @@ int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource, - } - EXPORT_SYMBOL(imx_sc_misc_set_control); - -+int imx_sc_misc_set_dma_group(struct imx_sc_ipc *ipc, u32 resource, -+ u32 val) -+{ -+ struct imx_sc_msg_req_misc_set_dma_group msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = (uint8_t)IMX_SC_RPC_SVC_MISC; -+ hdr->func = (uint8_t)IMX_SC_MISC_FUNC_SET_DMA_GROUP; -+ hdr->size = 2; -+ -+ msg.val = val; -+ msg.resource = resource; -+ -+ return imx_scu_call_rpc(ipc, &msg, true); -+} -+EXPORT_SYMBOL(imx_sc_misc_set_dma_group); -+ - /* - * This function gets a miscellaneous control value. - * -diff --git a/drivers/firmware/imx/rm.c b/drivers/firmware/imx/rm.c -index a12db6ff3..6dd4db386 100644 ---- a/drivers/firmware/imx/rm.c -+++ b/drivers/firmware/imx/rm.c -@@ -13,6 +13,11 @@ struct imx_sc_msg_rm_rsrc_owned { - u16 resource; - } __packed __aligned(4); - -+struct imx_sc_msg_rm_pt { -+ struct imx_sc_rpc_msg hdr; -+ u8 val; -+} __packed __aligned(4); -+ - /* - * This function check @resource is owned by current partition or not - * -@@ -43,3 +48,160 @@ bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource) - return hdr->func; - } - EXPORT_SYMBOL(imx_sc_rm_is_resource_owned); -+ -+/* -+ * This function returns the current partition number -+ * -+ * @param[in] ipc IPC handle -+ * @param[out] pt holding the partition number -+ * -+ * @return Returns 0 for success and < 0 for errors. -+ */ -+int imx_sc_rm_get_partition(struct imx_sc_ipc *ipc, u8 *pt) -+{ -+ struct imx_sc_msg_rm_pt msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_RM; -+ hdr->func = IMX_SC_RM_FUNC_GET_PARTITION; -+ hdr->size = 1; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret) -+ return ret; -+ -+ if (pt != NULL) -+ *pt = msg.val; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_rm_get_partition); -+ -+struct imx_sc_msg_rm_find_memreg { -+ struct imx_sc_rpc_msg hdr; -+ union { -+ struct { -+ u32 add_start_hi; -+ u32 add_start_lo; -+ u32 add_end_hi; -+ u32 add_end_lo; -+ } req; -+ struct { -+ u8 val; -+ } resp; -+ } data; -+} __packed __aligned(4); -+ -+int imx_sc_rm_find_memreg(struct imx_sc_ipc *ipc, u8 *mr, u64 addr_start, -+ u64 addr_end) -+{ -+ struct imx_sc_msg_rm_find_memreg msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_RM; -+ hdr->func = IMX_SC_RM_FUNC_FIND_MEMREG; -+ hdr->size = 5; -+ -+ msg.data.req.add_start_hi = addr_start >> 32; -+ msg.data.req.add_start_lo = addr_start; -+ msg.data.req.add_end_hi = addr_end >> 32; -+ msg.data.req.add_end_lo = addr_end; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret) -+ return ret; -+ -+ if (mr) -+ *mr = msg.data.resp.val; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_rm_find_memreg); -+ -+struct imx_sc_msg_rm_get_resource_owner { -+ struct imx_sc_rpc_msg hdr; -+ union { -+ struct { -+ u16 resource; -+ } req; -+ struct { -+ u8 val; -+ } resp; -+ } data; -+} __packed __aligned(4); -+ -+int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt) -+{ -+ struct imx_sc_msg_rm_get_resource_owner msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_RM; -+ hdr->func = IMX_SC_RM_FUNC_GET_RESOURCE_OWNER; -+ hdr->size = 2; -+ -+ msg.data.req.resource = resource; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret) -+ return ret; -+ -+ if (pt) -+ *pt = msg.data.resp.val; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_rm_get_resource_owner); -+ -+struct imx_sc_msg_set_memreg_permissions { -+ struct imx_sc_rpc_msg hdr; -+ u8 mr; -+ u8 pt; -+ u8 perm; -+} __packed __aligned(4); -+ -+int imx_sc_rm_set_memreg_permissions(struct imx_sc_ipc *ipc, u8 mr, -+ u8 pt, u8 perm) -+{ -+ struct imx_sc_msg_set_memreg_permissions msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_RM; -+ hdr->func = IMX_SC_RM_FUNC_SET_MEMREG_PERMISSIONS; -+ hdr->size = 2; -+ -+ msg.mr = mr; -+ msg.pt = pt; -+ msg.perm = perm; -+ -+ return imx_scu_call_rpc(ipc, &msg, true); -+} -+EXPORT_SYMBOL(imx_sc_rm_set_memreg_permissions); -+ -+int imx_sc_rm_get_did(struct imx_sc_ipc *ipc, u8 *did) -+{ -+ struct imx_sc_rpc_msg msg; -+ struct imx_sc_rpc_msg *hdr = &msg; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_RM; -+ hdr->func = IMX_SC_RM_FUNC_GET_DID; -+ hdr->size = 1; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret < 0) -+ return ret; -+ -+ if (did) -+ *did = msg.func; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_rm_get_did); -diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c -old mode 100644 -new mode 100755 -index 946eea292..2328a9ed6 ---- a/drivers/firmware/imx/scu-pd.c -+++ b/drivers/firmware/imx/scu-pd.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* - * Copyright (C) 2016 Freescale Semiconductor, Inc. -- * Copyright 2017-2018 NXP -+ * Copyright 2017-2018,2020 NXP - * Dong Aisheng - * - * Implementation of the SCU based Power Domains -@@ -44,10 +44,13 @@ - * - */ - -+#include - #include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -56,6 +59,17 @@ - #include - #include - #include -+#include -+ -+#define IMX_WU_MAX_IRQS (((IMX_SC_R_LAST + 31) / 32 ) * 32 ) -+ -+#define IMX_SIP_WAKEUP_SRC 0xc2000009 -+#define IMX_SIP_WAKEUP_SRC_SCU 0x1 -+#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 -+ -+static u32 wu[IMX_WU_MAX_IRQS]; -+static int wu_num; -+static void __iomem *gic_dist_base; - - /* SCU Power Mode Protocol definition */ - struct imx_sc_msg_req_set_resource_power_mode { -@@ -86,6 +100,8 @@ struct imx_sc_pd_soc { - u8 num_ranges; - }; - -+int imx_con_rsrc; -+ - static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { - /* LSIO SS */ - { "pwm", IMX_SC_R_PWM_0, 8, true, 0 }, -@@ -99,24 +115,29 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { - /* CONN SS */ - { "usb", IMX_SC_R_USB_0, 2, true, 0 }, - { "usb0phy", IMX_SC_R_USB_0_PHY, 1, false, 0 }, -+ { "usb1phy", IMX_SC_R_USB_1_PHY, 1, false, 0}, - { "usb2", IMX_SC_R_USB_2, 1, false, 0 }, - { "usb2phy", IMX_SC_R_USB_2_PHY, 1, false, 0 }, - { "sdhc", IMX_SC_R_SDHC_0, 3, true, 0 }, - { "enet", IMX_SC_R_ENET_0, 2, true, 0 }, - { "nand", IMX_SC_R_NAND, 1, false, 0 }, -- { "mlb", IMX_SC_R_MLB_0, 1, true, 0 }, - - /* AUDIO SS */ - { "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 }, - { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 }, - { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 }, - { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 }, -- { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 }, -+ { "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 }, -+ { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, -+ { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, - { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, -- { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, -+ { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, -+ { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 }, -+ { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, - { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, - { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, - { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 }, -+ { "esai1", IMX_SC_R_ESAI_1, 1, false, 0 }, - { "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 }, - { "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 }, - { "sai", IMX_SC_R_SAI_0, 3, true, 0 }, -@@ -133,11 +154,13 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { - /* DMA SS */ - { "can", IMX_SC_R_CAN_0, 3, true, 0 }, - { "ftm", IMX_SC_R_FTM_0, 2, true, 0 }, -- { "lpi2c", IMX_SC_R_I2C_0, 4, true, 0 }, -+ { "lpi2c", IMX_SC_R_I2C_0, 5, true, 0 }, - { "adc", IMX_SC_R_ADC_0, 1, true, 0 }, - { "lcd", IMX_SC_R_LCD_0, 1, true, 0 }, -+ { "lcd-pll", IMX_SC_R_ELCDIF_PLL, 1, true, 0 }, - { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 }, -- { "lpuart", IMX_SC_R_UART_0, 4, true, 0 }, -+ { "lpuart", IMX_SC_R_UART_0, 5, true, 0 }, -+ { "sim", IMX_SC_R_EMVSIM_0, 2, true, 0 }, - { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 }, - { "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 }, - -@@ -146,13 +169,22 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { - { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, - { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, - { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, -+ { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, -+ { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, -+ { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, -+ { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, - - /* GPU SS */ - { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 }, -+ { "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 }, -+ - - /* HSIO SS */ -+ { "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 }, -+ { "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 }, - { "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 }, - { "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 }, -+ { "sata-0", IMX_SC_R_SATA_0, 1, false, 0 }, - { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 }, - - /* MIPI SS */ -@@ -160,12 +192,27 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { - { "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, false, 0 }, - { "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, true, 0 }, - -+ { "mipi1", IMX_SC_R_MIPI_1, 1, 0 }, -+ { "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, 0 }, -+ { "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, 1 }, -+ - /* LVDS SS */ - { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, -+ { "lvds0-i2c0", IMX_SC_R_LVDS_0_I2C_0, 1, false, 0 }, -+ { "lvds0-pwm0", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 }, -+ -+ { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, -+ { "lvds1-i2c0", IMX_SC_R_LVDS_1_I2C_0, 1, false, 0 }, -+ { "lvds1-pwm0", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, - - /* DC SS */ - { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, - { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 }, -+ { "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 }, -+ -+ { "dc1", IMX_SC_R_DC_1, 1, false, 0 }, -+ { "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 }, -+ { "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 }, - - /* CM40 SS */ - { "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 }, -@@ -180,6 +227,53 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { - { "cm41-pid", IMX_SC_R_M4_1_PID0, 5, true, 0}, - { "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0}, - { "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0}, -+ -+ /* SECO SS */ -+ { "seco_mu", IMX_SC_R_SECO_MU_2, 3, true, 2}, -+ -+ /* V2X SS */ -+ { "v2x_mu", IMX_SC_R_V2X_MU_0, 2, true, 0}, -+ { "v2x_mu", IMX_SC_R_V2X_MU_2, 1, true, 2}, -+ { "v2x_mu", IMX_SC_R_V2X_MU_3, 2, true, 3}, -+ -+ /* DB SS */ -+ { "perf", IMX_SC_R_PERF, 1, false, 0}, -+ -+ /* IMAGE SS */ -+ { "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 }, -+ { "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 }, -+ { "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 }, -+ { "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 }, -+ { "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 }, -+ { "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 }, -+ { "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 }, -+ { "img-parallel", IMX_SC_R_PI_0, 1, false, 0 }, -+ { "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 }, -+ { "img-parallel-pwm0", IMX_SC_R_PI_0_PWM_0, 2, true, 0 }, -+ { "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 }, -+ { "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 }, -+ { "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 }, -+ { "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 }, -+ { "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 }, -+ -+ /* HDMI TX SS */ -+ { "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0}, -+ { "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0}, -+ { "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0}, -+ { "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0}, -+ { "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0}, -+ -+ /* HDMI RX SS */ -+ { "hdmi-rx", IMX_SC_R_HDMI_RX, 1, false, 0}, -+ { "hdmi-rx-pwm", IMX_SC_R_HDMI_RX_PWM_0, 1, false, 0}, -+ { "hdmi-rx-i2c0", IMX_SC_R_HDMI_RX_I2C_0, 1, false, 0}, -+ { "hdmi-rx-bypass", IMX_SC_R_HDMI_RX_BYPASS, 1, false, 0}, -+ -+ /* SECURITY SS */ -+ { "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2}, -+ -+ /* BOARD SS */ -+ { "board", IMX_SC_R_BOARD_R0, 8, true, 0}, - }; - - static const struct imx_sc_pd_soc imx8qxp_scu_pd = { -@@ -195,6 +289,73 @@ to_imx_sc_pd(struct generic_pm_domain *genpd) - return container_of(genpd, struct imx_sc_pm_domain, pd); - } - -+static int imx_pm_domains_suspend(void) -+{ -+ struct arm_smccc_res res; -+ u32 offset; -+ int i; -+ -+ for (i = 0; i < wu_num; i++) { -+ offset = GICD_ISENABLER + ((wu[i] + 32) / 32) * 4; -+ if (BIT(wu[i] % 32) & readl_relaxed(gic_dist_base + offset)) { -+ arm_smccc_smc(IMX_SIP_WAKEUP_SRC, -+ IMX_SIP_WAKEUP_SRC_IRQSTEER, -+ 0, 0, 0, 0, 0, 0, &res); -+ return 0; -+ } -+ } -+ -+ arm_smccc_smc(IMX_SIP_WAKEUP_SRC, -+ IMX_SIP_WAKEUP_SRC_SCU, -+ 0, 0, 0, 0, 0, 0, &res); -+ -+ return 0; -+} -+ -+struct syscore_ops imx_pm_domains_syscore_ops = { -+ .suspend = imx_pm_domains_suspend, -+}; -+ -+static void imx_sc_pd_enable_irqsteer_wakeup(struct device_node *np) -+{ -+ struct device_node *gic_node; -+ unsigned int i; -+ -+ wu_num = of_property_count_u32_elems(np, "wakeup-irq"); -+ if (wu_num <= 0) { -+ pr_warn("no irqsteer wakeup source supported!\n"); -+ return; -+ } -+ -+ gic_node = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); -+ WARN_ON(!gic_node); -+ -+ gic_dist_base = of_iomap(gic_node, 0); -+ WARN_ON(!gic_dist_base); -+ -+ for (i = 0; i < wu_num; i++) -+ WARN_ON(of_property_read_u32_index(np, "wakeup-irq", i, &wu[i])); -+ -+ register_syscore_ops(&imx_pm_domains_syscore_ops); -+} -+ -+static void imx_sc_pd_get_console_rsrc(void) -+{ -+ struct of_phandle_args specs; -+ int ret; -+ -+ if (!of_stdout) -+ return; -+ -+ ret = of_parse_phandle_with_args(of_stdout, "power-domains", -+ "#power-domain-cells", -+ 0, &specs); -+ if (ret) -+ return; -+ -+ imx_con_rsrc = specs.args[0]; -+} -+ - static int imx_sc_pd_power(struct generic_pm_domain *domain, bool power_on) - { - struct imx_sc_msg_req_set_resource_power_mode msg; -@@ -210,7 +371,12 @@ static int imx_sc_pd_power(struct generic_pm_domain *domain, bool power_on) - hdr->size = 2; - - msg.resource = pd->rsrc; -- msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : IMX_SC_PM_PW_MODE_LP; -+ msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : pd->pd.state_idx ? -+ IMX_SC_PM_PW_MODE_OFF : IMX_SC_PM_PW_MODE_LP; -+ -+ /* keep uart console power on for no_console_suspend */ -+ if (imx_con_rsrc == pd->rsrc && !console_suspend_enabled && !power_on) -+ return 0; - - ret = imx_scu_call_rpc(pm_ipc_handle, &msg, true); - if (ret) -@@ -255,6 +421,8 @@ imx_scu_add_pm_domain(struct device *dev, int idx, - const struct imx_sc_pd_range *pd_ranges) - { - struct imx_sc_pm_domain *sc_pd; -+ struct genpd_power_state *states; -+ bool is_off = true; - int ret; - - if (!imx_sc_rm_is_resource_owned(pm_ipc_handle, pd_ranges->rsrc + idx)) -@@ -264,9 +432,23 @@ imx_scu_add_pm_domain(struct device *dev, int idx, - if (!sc_pd) - return ERR_PTR(-ENOMEM); - -+ states = devm_kcalloc(dev, 2, sizeof(*states), GFP_KERNEL); -+ if (!states) { -+ devm_kfree(dev, sc_pd); -+ return ERR_PTR(-ENOMEM); -+ } -+ - sc_pd->rsrc = pd_ranges->rsrc + idx; - sc_pd->pd.power_off = imx_sc_pd_power_off; - sc_pd->pd.power_on = imx_sc_pd_power_on; -+ sc_pd->pd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; -+ states[0].power_off_latency_ns = 25000; -+ states[0].power_on_latency_ns = 25000; -+ states[1].power_off_latency_ns = 2500000; -+ states[1].power_on_latency_ns = 2500000; -+ -+ sc_pd->pd.states = states; -+ sc_pd->pd.state_count = 2; - - if (pd_ranges->postfix) - snprintf(sc_pd->name, sizeof(sc_pd->name), -@@ -276,20 +458,26 @@ imx_scu_add_pm_domain(struct device *dev, int idx, - "%s", pd_ranges->name); - - sc_pd->pd.name = sc_pd->name; -+ if (imx_con_rsrc == sc_pd->rsrc) { -+ sc_pd->pd.flags |= GENPD_FLAG_RPM_ALWAYS_ON; -+ is_off = false; -+ } - - if (sc_pd->rsrc >= IMX_SC_R_LAST) { - dev_warn(dev, "invalid pd %s rsrc id %d found", - sc_pd->name, sc_pd->rsrc); - - devm_kfree(dev, sc_pd); -+ devm_kfree(dev, states); - return NULL; - } - -- ret = pm_genpd_init(&sc_pd->pd, NULL, true); -+ ret = pm_genpd_init(&sc_pd->pd, NULL, is_off); - if (ret) { - dev_warn(dev, "failed to init pd %s rsrc id %d", - sc_pd->name, sc_pd->rsrc); - devm_kfree(dev, sc_pd); -+ devm_kfree(dev, states); - return NULL; - } - -@@ -351,6 +539,9 @@ static int imx_sc_pd_probe(struct platform_device *pdev) - if (!pd_soc) - return -ENODEV; - -+ imx_sc_pd_get_console_rsrc(); -+ imx_sc_pd_enable_irqsteer_wakeup(pdev->dev.of_node); -+ - return imx_scu_init_pm_domains(&pdev->dev, pd_soc); - } - -@@ -367,7 +558,12 @@ static struct platform_driver imx_sc_pd_driver = { - }, - .probe = imx_sc_pd_probe, - }; --builtin_platform_driver(imx_sc_pd_driver); -+ -+static int __init imx_sc_pd_driver_init(void) -+{ -+ return platform_driver_register(&imx_sc_pd_driver); -+} -+subsys_initcall(imx_sc_pd_driver_init); - - MODULE_AUTHOR("Dong Aisheng "); - MODULE_DESCRIPTION("IMX SCU Power Domain driver"); -diff --git a/drivers/firmware/imx/seco.c b/drivers/firmware/imx/seco.c -new file mode 100644 -index 000000000..18232c700 ---- /dev/null -+++ b/drivers/firmware/imx/seco.c -@@ -0,0 +1,249 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2020 NXP -+ * -+ * File containing client-side RPC functions for the SECO service. These -+ * function are ported to clients that communicate to the SC. -+ */ -+ -+#include -+ -+struct imx_sc_msg_seco_get_build_id { -+ struct imx_sc_rpc_msg hdr; -+ u32 version; -+ u32 commit; -+} __packed __aligned(4); -+ -+int imx_sc_seco_build_info(struct imx_sc_ipc *ipc, uint32_t *version, -+ uint32_t *commit) -+{ -+ struct imx_sc_msg_seco_get_build_id msg = {0}; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_SECO; -+ hdr->func = IMX_SC_SECO_FUNC_BUILD_INFO; -+ hdr->size = 1; -+ -+ imx_scu_call_rpc(ipc, &msg, true); -+ -+ if (version) -+ *version = msg.version; -+ if (commit) -+ *commit = msg.commit; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_seco_build_info); -+ -+struct imx_sc_msg_seco_sab_msg { -+ struct imx_sc_rpc_msg hdr; -+ u32 smsg_addr_hi; -+ u32 smsg_addr_lo; -+} __packed __aligned(4); -+ -+int imx_sc_seco_sab_msg(struct imx_sc_ipc *ipc, u64 smsg_addr) -+{ -+ struct imx_sc_msg_seco_sab_msg msg; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = IMX_SC_RPC_SVC_SECO; -+ hdr->func = IMX_SC_SECO_FUNC_SAB_MSG; -+ hdr->size = 3; -+ -+ msg.smsg_addr_hi = smsg_addr >> 32; -+ msg.smsg_addr_lo = smsg_addr; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ return ret; -+} -+EXPORT_SYMBOL(imx_sc_seco_sab_msg); -+ -+int imx_sc_seco_secvio_enable(struct imx_sc_ipc *ipc) -+{ -+ struct imx_sc_rpc_msg msg; -+ struct imx_sc_rpc_msg *hdr = &msg; -+ int ret; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; -+ hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_ENABLE; -+ hdr->size = 1; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_seco_secvio_enable); -+ -+struct imx_sc_msg_req_seco_config { -+ struct imx_sc_rpc_msg hdr; -+ u32 data0; -+ u32 data1; -+ u32 data2; -+ u32 data3; -+ u32 data4; -+ u8 id; -+ u8 access; -+ u8 size; -+} __packed __aligned(4); -+ -+struct imx_sc_msg_resp_seco_config { -+ struct imx_sc_rpc_msg hdr; -+ u32 data0; -+ u32 data1; -+ u32 data2; -+ u32 data3; -+ u32 data4; -+} __packed __aligned(4); -+ -+int imx_sc_seco_secvio_config(struct imx_sc_ipc *ipc, u8 id, u8 access, -+ u32 *data0, u32 *data1, u32 *data2, u32 *data3, -+ u32 *data4, u8 size) -+{ -+ struct imx_sc_msg_req_seco_config msg; -+ struct imx_sc_msg_resp_seco_config *resp; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ if (!ipc) -+ return -EINVAL; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; -+ hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_CONFIG; -+ hdr->size = 7; -+ -+ /* Check the pointers on data are valid and set it if doing a write */ -+ switch (size) { -+ case 5: -+ if (data4) { -+ if (access) -+ msg.data4 = *data4; -+ } else { -+ return -EINVAL; -+ } -+ fallthrough; -+ case 4: -+ if (data3) { -+ if (access) -+ msg.data3 = *data3; -+ } else { -+ return -EINVAL; -+ } -+ fallthrough; -+ case 3: -+ if (data2) { -+ if (access) -+ msg.data2 = *data2; -+ } else { -+ return -EINVAL; -+ } -+ fallthrough; -+ case 2: -+ if (data1) { -+ if (access) -+ msg.data1 = *data1; -+ } else { -+ return -EINVAL; -+ } -+ fallthrough; -+ case 1: -+ if (data0) { -+ if (access) -+ msg.data0 = *data0; -+ } else { -+ return -EINVAL; -+ } -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ msg.id = id; -+ msg.access = access; -+ msg.size = size; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret) -+ return ret; -+ -+ resp = (struct imx_sc_msg_resp_seco_config *)&msg; -+ -+ /* Pointers already checked so we just copy the data if reading */ -+ if (!access) -+ switch (size) { -+ case 5: -+ *data4 = resp->data4; -+ fallthrough; -+ case 4: -+ *data3 = resp->data3; -+ fallthrough; -+ case 3: -+ *data2 = resp->data2; -+ fallthrough; -+ case 2: -+ *data1 = resp->data1; -+ fallthrough; -+ case 1: -+ *data0 = resp->data0; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_seco_secvio_config); -+ -+struct imx_sc_msg_req_seco_dgo_config { -+ struct imx_sc_rpc_msg hdr; -+ u32 data; -+ u8 id; -+ u8 access; -+} __packed __aligned(4); -+ -+struct imx_sc_msg_resp_seco_dgo_config { -+ struct imx_sc_rpc_msg hdr; -+ u32 data; -+} __packed __aligned(4); -+ -+int imx_sc_seco_secvio_dgo_config(struct imx_sc_ipc *ipc, u8 id, u8 access, -+ u32 *data) -+{ -+ struct imx_sc_msg_req_seco_dgo_config msg; -+ struct imx_sc_msg_resp_seco_dgo_config *resp; -+ struct imx_sc_rpc_msg *hdr = &msg.hdr; -+ int ret; -+ -+ if (!ipc) -+ return -EINVAL; -+ -+ hdr->ver = IMX_SC_RPC_VERSION; -+ hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; -+ hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_DGO_CONFIG; -+ hdr->size = 3; -+ -+ if (access) { -+ if (data) -+ msg.data = *data; -+ else -+ return -EINVAL; -+ } -+ -+ msg.access = access; -+ msg.id = id; -+ -+ ret = imx_scu_call_rpc(ipc, &msg, true); -+ if (ret) -+ return ret; -+ -+ resp = (struct imx_sc_msg_resp_seco_dgo_config *)&msg; -+ -+ if (!access && data) -+ *data = resp->data; -+ -+ return 0; -+} -+EXPORT_SYMBOL(imx_sc_seco_secvio_dgo_config); -diff --git a/drivers/gpio/gpio-max732x.c b/drivers/gpio/gpio-max732x.c -index 238cbe926..4af7ea075 100644 ---- a/drivers/gpio/gpio-max732x.c -+++ b/drivers/gpio/gpio-max732x.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - - /* -@@ -76,6 +77,12 @@ - - #define INT_CAPS(x) (((uint64_t)(x)) << 32) - -+enum { -+ OUTPUT_MASK, -+ OUTPUT_VAL, -+ OUTPUT_NUM, -+}; -+ - enum { - MAX7319, - MAX7320, -@@ -622,6 +629,8 @@ static int max732x_probe(struct i2c_client *client, - struct i2c_client *c; - uint16_t addr_a, addr_b; - int ret, nr_port; -+ u16 out_set[OUTPUT_NUM]; -+ unsigned long mask, val; - - pdata = dev_get_platdata(&client->dev); - node = client->dev.of_node; -@@ -639,6 +648,10 @@ static int max732x_probe(struct i2c_client *client, - return -ENOMEM; - chip->client = client; - -+ ret = device_reset(&client->dev); -+ if (ret == -EPROBE_DEFER) -+ return ret; -+ - nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base); - chip->gpio_chip.parent = &client->dev; - -@@ -711,6 +724,15 @@ static int max732x_probe(struct i2c_client *client, - } - - i2c_set_clientdata(client, chip); -+ -+ /* set the output IO default voltage */ -+ if (!of_property_read_u16_array(node, "out-default", out_set, -+ ARRAY_SIZE(out_set))) { -+ mask = out_set[OUTPUT_MASK] & chip->dir_output; -+ val = out_set[OUTPUT_VAL]; -+ max732x_gpio_set_multiple(&chip->gpio_chip, &mask, &val); -+ } -+ - return 0; - } - -diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c -index d60d55207..4982e90d8 100644 ---- a/drivers/gpio/gpio-mpc8xxx.c -+++ b/drivers/gpio/gpio-mpc8xxx.c -@@ -426,9 +426,20 @@ static int mpc8xxx_remove(struct platform_device *pdev) - return 0; - } - -+static void mpc8xxx_shutdown(struct platform_device *pdev) -+{ -+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); -+ -+ if (mpc8xxx_gc->irq) { -+ irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); -+ irq_domain_remove(mpc8xxx_gc->irq); -+ } -+} -+ - static struct platform_driver mpc8xxx_plat_driver = { - .probe = mpc8xxx_probe, - .remove = mpc8xxx_remove, -+ .shutdown = mpc8xxx_shutdown, - .driver = { - .name = "gpio-mpc8xxx", - .of_match_table = mpc8xxx_gpio_ids, -diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c -index a78167b2c..33d3a0bfe 100644 ---- a/drivers/gpio/gpio-pca953x.c -+++ b/drivers/gpio/gpio-pca953x.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -981,14 +982,19 @@ static int pca953x_probe(struct i2c_client *client, - - chip->client = client; - -- reg = devm_regulator_get(&client->dev, "vcc"); -- if (IS_ERR(reg)) -- return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n"); -+ reg = devm_regulator_get_optional(&client->dev, "vcc"); -+ if (IS_ERR(reg)) { -+ if (PTR_ERR(reg) != -ENODEV) -+ return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n"); -+ reg = NULL; -+ } - -- ret = regulator_enable(reg); -- if (ret) { -- dev_err(&client->dev, "reg en err: %d\n", ret); -- return ret; -+ if (reg) { -+ ret = regulator_enable(reg); -+ if (ret) { -+ dev_err(&client->dev, "reg en err: %d\n", ret); -+ return ret; -+ } - } - chip->regulator = reg; - -@@ -1046,6 +1052,10 @@ static int pca953x_probe(struct i2c_client *client, - lockdep_set_subclass(&chip->i2c_lock, - i2c_adapter_depth(client->adapter)); - -+ ret = device_reset(&client->dev); -+ if (ret == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ - /* initialize cached registers from their original values. - * we can't share this chip with another i2c master. - */ -@@ -1078,7 +1088,8 @@ static int pca953x_probe(struct i2c_client *client, - return 0; - - err_exit: -- regulator_disable(chip->regulator); -+ if (chip->regulator) -+ regulator_disable(chip->regulator); - return ret; - } - -@@ -1097,7 +1108,8 @@ static int pca953x_remove(struct i2c_client *client) - ret = 0; - } - -- regulator_disable(chip->regulator); -+ if (chip->regulator) -+ regulator_disable(chip->regulator); - - return ret; - } -@@ -1158,7 +1170,8 @@ static int pca953x_suspend(struct device *dev) - if (atomic_read(&chip->wakeup_path)) - device_set_wakeup_path(dev); - else -- regulator_disable(chip->regulator); -+ if (chip->regulator) -+ regulator_disable(chip->regulator); - - return 0; - } -@@ -1168,15 +1181,20 @@ static int pca953x_resume(struct device *dev) - struct pca953x_chip *chip = dev_get_drvdata(dev); - int ret; - -+ regcache_cache_only(chip->regmap, false); -+ - if (!atomic_read(&chip->wakeup_path)) { -- ret = regulator_enable(chip->regulator); -- if (ret) { -- dev_err(dev, "Failed to enable regulator: %d\n", ret); -+ if (chip->regulator) { -+ ret = regulator_enable(chip->regulator); -+ if (ret) { -+ dev_err(dev, "Failed to enable regulator: %d\n", ret); -+ return 0; -+ } -+ } else { - return 0; - } - } - -- regcache_cache_only(chip->regmap, false); - regcache_mark_dirty(chip->regmap); - ret = pca953x_regcache_sync(dev); - if (ret) -diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile -index 835c88318..b8a7b5c5a 100644 ---- a/drivers/gpu/Makefile -+++ b/drivers/gpu/Makefile -@@ -3,6 +3,6 @@ - # taken to initialize them in the correct order. Link order is the only way - # to ensure this currently. - obj-$(CONFIG_TEGRA_HOST1X) += host1x/ -+obj-y += imx/ - obj-y += drm/ vga/ --obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/ - obj-$(CONFIG_TRACE_GPU_MEM) += trace/ -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index 81569009f..4fc2edb57 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -18,7 +18,7 @@ drm-y := drm_auth.o drm_cache.o \ - drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \ - drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \ - drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o \ -- drm_managed.o drm_vblank_work.o -+ drm_managed.o drm_vblank_work.o drm_notify.o - - drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o drm_dma.o drm_scatter.o drm_lock.o - drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o -diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig -index ef8c230e0..6955282c8 100644 ---- a/drivers/gpu/drm/bridge/cadence/Kconfig -+++ b/drivers/gpu/drm/bridge/cadence/Kconfig -@@ -22,3 +22,8 @@ config DRM_CDNS_MHDP8546_J721E - initializes the J721E Display Port and sets up the - clock and data muxes. - endif -+ -+config DRM_CDNS_HDMI_CEC -+ tristate "Cadence MHDP HDMI CEC driver" -+ select CEC_CORE -+ select CEC_NOTIFIER -diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile -index 8f647991b..75bd7561b 100644 ---- a/drivers/gpu/drm/bridge/cadence/Makefile -+++ b/drivers/gpu/drm/bridge/cadence/Makefile -@@ -2,3 +2,7 @@ - obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o - cdns-mhdp8546-y := cdns-mhdp8546-core.o - cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o -+ -+cdns_mhdp_drmcore-y := cdns-mhdp-common.o cdns-mhdp-dp.o cdns-mhdp-hdmi.o -+ -+cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI_CEC) += cdns-mhdp-cec.o -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c -new file mode 100644 -index 000000000..aaabc25a9 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c -@@ -0,0 +1,1323 @@ -+/* -+ * Cadence HDMI/DP HDCP driver -+ * -+ * Copyright 2021 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+#include -+#include -+#include -+#include -+ -+#include "cdns-mhdp-hdcp.h" -+ -+/* Default will be to use KM unless it has been explicitly */ -+#ifndef HDCP_USE_KMKEY -+ #define HDCP_USE_KMKEY 1 -+#endif -+ -+#define CDNS_HDCP_ACTIVATE (0x1 << 2) -+ -+#define IMX_FW_TIMEOUT_MS (64 * 1000) -+#define IMX_HDCP_PAIRING_FIRMWARE "imx/hdcp-pairing.bin" -+ -+#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT 0 -+#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT 1 -+#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT 2 -+#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT 3 -+#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT 4 -+#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT 5 -+ -+#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT 0 -+#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT 1 -+#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT 2 -+ -+/* HDCP TX ports working mode (HDCP 2.2 or 1.4) */ -+enum { -+ HDCP_TX_2, /* lock only with HDCP2 */ -+ HDCP_TX_1, /* lock only with HDCP1 */ -+ HDCP_TX_BOTH, /* lock on HDCP2 or 1 depend on other side */ -+}; -+ -+/* HDCP TX ports stream type (relevant if receiver is repeater) */ -+enum { -+ HDCP_CONTENT_TYPE_0, /* May be transmitted by -+ The HDCP Repeater to all HDCP Devices. */ -+ HDCP_CONTENT_TYPE_1, /* Must not be transmitted by the HDCP Repeater to -+ HDCP 1.x-compliant Devices and HDCP 2.0-compliant Repeaters */ -+}; -+ -+/* different error types for HDCP_TX_STATUS_CHANGE */ -+enum { -+ HDCP_TRAN_ERR_NO_ERROR, -+ HDCP_TRAN_ERR_HPD_IS_DOWN, -+ HDCP_TRAN_ERR_SRM_FAILURE, -+ HDCP_TRAN_ERR_SIGNATURE_VERIFICATION, -+ HDCP_TRAN_ERR_H_TAG_DIFF_H, -+ HDCP_TRAN_ERR_V_TAG_DIFF_V, -+ HDCP_TRAN_ERR_LOCALITY_CHECK, -+ HDCP_TRAN_ERR_DDC, -+ HDCP_TRAN_ERR_REAUTH_REQ, -+ HDCP_TRAN_ERR_TOPOLOGY, -+ HDCP_TRAN_ERR_HDCP_RSVD1, -+ HDCP_TRAN_ERR_HDMI_CAPABILITY, -+ HDCP_TRAN_ERR_RI, -+ HDCP_TRAN_ERR_WATCHDOG_EXPIRED, -+}; -+ -+static char const *g_last_error[16] = { -+ "No Error", -+ "HPD is down", -+ "SRM failure", -+ "Signature verification error", -+ "h tag != h", -+ "V tag diff v", -+ "Locality check", -+ "DDC error", -+ "REAUTH_REQ", -+ "Topology error", -+ "Verify receiver ID list failed", -+ "HDCP_RSVD1 was not 0,0,0", -+ "HDMI capability or mode", -+ "RI result was different than expected", -+ "WatchDog expired", -+ "Repeater integrity failed" -+}; -+ -+#define HDCP_MAX_RECEIVERS 32 -+#define HDCP_RECEIVER_ID_SIZE_BYTES 5 -+#define HPD_EVENT 1 -+#define HDCP_STATUS_SIZE 0x5 -+#define HDCP_PORT_STS_AUTH 0x1 -+#define HDCP_PORT_STS_REPEATER 0x2 -+#define HDCP_PORT_STS_TYPE_MASK 0xc -+#define HDCP_PORT_STS_TYPE_SHIFT 0x2 -+#define HDCP_PORT_STS_AUTH_STREAM_ID_SHIFT 0x4 -+#define HDCP_PORT_STS_AUTH_STREAM_ID_MASK 0x10 -+#define HDCP_PORT_STS_LAST_ERR_SHIFT 0x5 -+#define HDCP_PORT_STS_LAST_ERR_MASK (0x0F << 5) -+#define GET_HDCP_PORT_STS_LAST_ERR(__sts__) \ -+ (((__sts__) & HDCP_PORT_STS_LAST_ERR_MASK) >> \ -+ HDCP_PORT_STS_LAST_ERR_SHIFT) -+#define HDCP_PORT_STS_1_1_FEATURES 0x200 -+ -+#define HDCP_CONFIG_NONE ((u8) 0) -+#define HDCP_CONFIG_1_4 ((u8) 1) /* use HDCP 1.4 only */ -+#define HDCP_CONFIG_2_2 ((u8) 2) /* use HDCP 2.2 only */ -+ -+/* Default timeout to use for wait4event in milliseconds */ -+#define HDCP_EVENT_TO_DEF 800 -+/* Timeout value to use for repeater receiver ID check, spec says 3s */ -+#define HDCP_EVENT_TO_RPT 3500 -+ -+static int cdns_hdcp_check_link(struct cdns_mhdp_device *mhdp); -+ -+static void print_port_status(u16 sts) -+{ -+ char const *rx_type[4] = { "Unknown", "HDCP 1", "HDCP 2", "Unknown" }; -+ -+ DRM_DEBUG_KMS("INFO: HDCP Port Status: 0x%04x\n", sts); -+ DRM_DEBUG_KMS(" Authenticated: %d\n", sts & HDCP_PORT_STS_AUTH); -+ DRM_DEBUG_KMS(" Receiver is repeater: %d\n", sts & HDCP_PORT_STS_REPEATER); -+ DRM_DEBUG_KMS(" RX Type: %s\n", -+ rx_type[(sts & HDCP_PORT_STS_TYPE_MASK) >> HDCP_PORT_STS_TYPE_SHIFT]); -+ DRM_DEBUG_KMS(" AuthStreamId: %d\n", sts & HDCP_PORT_STS_AUTH_STREAM_ID_MASK); -+ DRM_DEBUG_KMS(" Last Error: %s\n", -+ g_last_error[(sts & HDCP_PORT_STS_LAST_ERR_MASK) >> HDCP_PORT_STS_LAST_ERR_SHIFT]); -+ DRM_DEBUG_KMS(" Enable 1.1 Features: %d\n", sts & HDCP_PORT_STS_1_1_FEATURES); -+} -+ -+static void print_events(u8 events) -+{ -+ if (events & HDMI_TX_HPD_EVENT) -+ DRM_INFO("INFO: HDMI_TX_HPD_EVENT\n"); -+ if (events & HDCPTX_STATUS_EVENT) -+ DRM_INFO("INFO: HDCPTX_STATUS_EVENT\n"); -+ if (events & HDCPTX_IS_KM_STORED_EVENT) -+ DRM_INFO("INFO: HDCPTX_IS_KM_STORED_EVENT\n"); -+ if (events & HDCPTX_STORE_KM_EVENT) -+ DRM_INFO("INFO: HDCPTX_STORE_KM_EVENT\n"); -+ if (events & HDCPTX_IS_RECEIVER_ID_VALID_EVENT) -+ DRM_INFO("INFO: HDCPTX_IS_RECEIVER_ID_VALID_EVENT\n"); -+} -+ -+static u8 wait4event(struct cdns_mhdp_device *mhdp, u8 *events, -+ u32 event_to_wait, u32 timeout_ms) -+{ -+ u8 reg_events; -+ u8 returned_events; -+ u8 event_mask = event_to_wait | HDCPTX_STATUS_EVENT; -+ unsigned timeout; -+ -+ timeout = timeout_ms; -+ do { -+ if (timeout == 0) -+ goto timeout_err; -+ timeout--; -+ udelay(1000); -+ reg_events = cdns_mhdp_get_event(mhdp); -+ *events |= reg_events; -+ } while (((event_mask & *events) == 0) && (event_to_wait > HDMI_TX_HPD_EVENT)); -+ -+ returned_events = *events & event_mask; -+ if (*events != returned_events) { -+ u32 unexpected_events = ~event_mask & *events; -+ -+ DRM_INFO("INFO: %s() all 0x%08x expected 0x%08x unexpected 0x%08x", -+ __func__, *events, returned_events, unexpected_events); -+ DRM_INFO("INFO: %s() All events:\n", __func__); -+ print_events(*events); -+ -+ DRM_INFO("INFO: %s() expected events:\n", __func__); -+ print_events(returned_events); -+ -+ DRM_INFO("INFO: %s() unexpected events:\n", __func__); -+ print_events(unexpected_events); -+ } else -+ print_events(*events); -+ -+ *events &= ~event_mask; -+ -+ return returned_events; -+ -+timeout_err: -+ DRM_INFO("INFO: %s() Timed out with events:\n", __func__); -+ print_events(event_to_wait); -+ return 0; -+} -+ -+static u16 cdns_hdcp_get_status(struct cdns_mhdp_device *mhdp) -+{ -+ u8 hdcp_status[HDCP_STATUS_SIZE]; -+ u16 hdcp_port_status; -+ -+ cdns_mhdp_hdcp_tx_status_req(mhdp, hdcp_status, HDCP_STATUS_SIZE); -+ hdcp_port_status = (hdcp_status[0] << 8) | hdcp_status[1]; -+ -+ return hdcp_port_status; -+} -+ -+static inline u8 check_event(u8 events, u8 tested) -+{ -+ if ((events & tested) == 0) -+ return 0; -+ return 1; -+} -+ -+/* Prints status. Returns error code (0 = no error) */ -+static u8 cdns_hdcp_handle_status(u16 status) -+{ -+ print_port_status(status); -+ if (status & HDCP_PORT_STS_LAST_ERR_MASK) -+ DRM_ERROR("ERROR: HDCP error was set to %s\n", -+ g_last_error[((status & HDCP_PORT_STS_LAST_ERR_MASK) -+ >> HDCP_PORT_STS_LAST_ERR_SHIFT)]); -+ return GET_HDCP_PORT_STS_LAST_ERR(status); -+} -+ -+static int cdns_hdcp_set_config(struct cdns_mhdp_device *mhdp, u8 hdcp_config) -+{ -+ u8 bus_config, retEvents; -+ u16 hdcp_port_status; -+ int ret; -+ -+ /* Clearing out existing events */ -+ wait4event(mhdp, &mhdp->hdcp.events, HDMI_TX_HPD_EVENT, HDCP_EVENT_TO_DEF); -+ mhdp->hdcp.events = 0; -+ -+ if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { -+ DRM_DEBUG_KMS("INFO: Switching HDCP Commands to SAPB.\n"); -+ bus_config = (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_BIT); -+ ret = cdns_mhdp_apb_conf(mhdp, bus_config); -+ if (ret) { -+ DRM_ERROR("Failed to set APB configuration.\n"); -+ if (ret & (1 << GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT))/* 1 - locked */ -+ DRM_ERROR("Failed to switch HDCP to SAPB Mailbox\n"); -+ return -1; -+ } -+ DRM_DEBUG_KMS("INFO: HDCP switched to SAPB\n"); -+ } -+ -+ /* HDCP 2.2(and/or 1.4) | activate | km-key | 0 */ -+ hdcp_config |= CDNS_HDCP_ACTIVATE | (HDCP_USE_KMKEY << 4) | (HDCP_CONTENT_TYPE_0 << 3); -+ -+ DRM_DEBUG_KMS("INFO: Enabling HDCP...\n"); -+ ret = cdns_mhdp_hdcp_tx_config(mhdp, hdcp_config); -+ if (ret < 0) -+ DRM_DEBUG_KMS("cdns_mhdp_hdcp_tx_config failed\n"); -+ -+ /* Wait until HDCP_TX_STATUS EVENT appears */ -+ DRM_DEBUG_KMS("INFO: wait4event -> HDCPTX_STATUS_EVENT\n"); -+ retEvents = wait4event(mhdp, &mhdp->hdcp.events, HDCPTX_STATUS_EVENT, HDCP_EVENT_TO_DEF); -+ -+ /* Set TX STATUS REQUEST */ -+ DRM_DEBUG_KMS("INFO: Getting port status\n"); -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ if (cdns_hdcp_handle_status(hdcp_port_status) != 0) -+ return -1; -+ -+ return 0; -+} -+ -+static int cdns_hdcp_auth_check(struct cdns_mhdp_device *mhdp) -+{ -+ u16 hdcp_port_status; -+ int ret; -+ -+ DRM_DEBUG_KMS("INFO: wait4event -> HDCPTX_STATUS_EVENT\n"); -+ mhdp->hdcp.events = wait4event(mhdp, &mhdp->hdcp.events, HDCPTX_STATUS_EVENT, HDCP_EVENT_TO_DEF+HDCP_EVENT_TO_DEF); -+ if (mhdp->hdcp.events == 0) -+ return -1; -+ -+ DRM_DEBUG_KMS("HDCP: HDCPTX_STATUS_EVENT\n"); -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ ret = cdns_hdcp_handle_status(hdcp_port_status); -+ if (ret != 0) { -+ if (ret == HDCP_TRAN_ERR_REAUTH_REQ) { -+ DRM_ERROR("HDCP_TRAN_ERR_REAUTH_REQ-->one more try!\n"); -+ return 1; -+ } else -+ return -1; -+ } -+ -+ if (hdcp_port_status & HDCP_PORT_STS_AUTH) { -+ DRM_INFO("Authentication completed successfully!\n"); -+ /* Dump hdmi and phy register */ -+ mhdp->hdcp.state = HDCP_STATE_AUTHENTICATED; -+ return 0; -+ } -+ -+ DRM_WARN("Authentication failed\n"); -+ mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; -+ return -1; -+} -+ -+inline void cdns_hdcp_swap_id(u8 *in, u8 *out) -+{ -+ int i; -+ -+ for (i = 0; i < HDCP_RECEIVER_ID_SIZE_BYTES; i++) -+ out[HDCP_RECEIVER_ID_SIZE_BYTES - (i + 1)] = in[i]; -+} -+ -+inline void cdns_hdcp_swap_list(u8 *list_in, u8 *list_out, int num_ids) -+{ -+ int i; -+ -+ for (i = 0; i < num_ids; i++) -+ cdns_hdcp_swap_id(&list_in[i * HDCP_RECEIVER_ID_SIZE_BYTES], -+ &list_out[i * HDCP_RECEIVER_ID_SIZE_BYTES]); -+} -+ -+static int cdns_hdcp_check_receviers(struct cdns_mhdp_device *mhdp) -+{ -+ u8 ret_events; -+ u8 hdcp_num_rec, i; -+ u8 hdcp_rec_id[HDCP_MAX_RECEIVERS][HDCP_RECEIVER_ID_SIZE_BYTES]; -+ u8 hdcp_rec_id_temp[HDCP_MAX_RECEIVERS][HDCP_RECEIVER_ID_SIZE_BYTES]; -+ u16 hdcp_port_status = 0; -+ int ret; -+ -+ DRM_INFO("INFO: Waiting for Receiver ID valid event\n"); -+ ret_events = 0; -+ do { -+ u8 events = 0; -+ u8 hdcp_last_error = 0; -+ events = check_event(ret_events, -+ HDCPTX_IS_RECEIVER_ID_VALID_EVENT); -+ DRM_DEBUG_KMS("INFO: Waiting HDCPTX_IS_RECEIVER_ID_VALID_EVENT\n"); -+ ret_events = wait4event(mhdp, &mhdp->hdcp.events, -+ HDCPTX_IS_RECEIVER_ID_VALID_EVENT, -+ (mhdp->hdcp.sink_is_repeater ? -+ HDCP_EVENT_TO_RPT : HDCP_EVENT_TO_DEF)); -+ if (ret_events == 0) { -+ /* time out occurred, return error */ -+ DRM_ERROR("HDCP error did not get receiver IDs\n"); -+ return -1; -+ } -+ if (check_event(ret_events, HDCPTX_STATUS_EVENT) != 0) { -+ /* There was a status update, could be due to HPD -+ going down or some other error, check if an error -+ was set, if so exit. -+ */ -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ hdcp_last_error = GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status); -+ if (cdns_hdcp_handle_status(hdcp_port_status)) { -+ DRM_ERROR("HDCP error no: %u\n", hdcp_last_error); -+ return -1; -+ } else { -+ /* No error logged, keep going. -+ * If this somehow happened at same time, then need to -+ * put the HDCPTX_STATUS_EVENT back into the global -+ * events pool and checked later. */ -+ mhdp->hdcp.events |= HDCPTX_STATUS_EVENT; -+ -+ /* Special condition when connected to HDCP 1.4 repeater -+ * with no downstream devices attached, then will not -+ * get receiver ID list but instead will reach -+ * authenticated state. */ -+ if ((mhdp->hdcp.hdcp_version == HDCP_TX_1) && (mhdp->hdcp.sink_is_repeater == 1) && -+ ((hdcp_port_status & HDCP_PORT_STS_AUTH) == HDCP_PORT_STS_AUTH)) { -+ DRM_INFO("Connected to HDCP 1.4 repeater with no downstream devices!\n"); -+ return 0; -+ } -+ -+ msleep(20); -+ } -+ } -+ } while (check_event(ret_events, -+ HDCPTX_IS_RECEIVER_ID_VALID_EVENT) == 0); -+ -+ DRM_INFO("INFO: Requesting Receivers ID's\n"); -+ -+ hdcp_num_rec = 0; -+ memset(&hdcp_rec_id, 0, sizeof(hdcp_rec_id)); -+ -+ ret = cdns_mhdp_hdcp_tx_is_receiver_id_valid(mhdp, (u8 *)hdcp_rec_id, &hdcp_num_rec); -+ if (ret) { -+ DRM_DEV_ERROR(mhdp->dev, "Failed to hdcp tx receiver ID.\n"); -+ return -1; -+ } -+ -+ if (hdcp_num_rec == 0) { -+ DRM_DEBUG_KMS("WARN: Failed to get receiver list\n"); -+ /* Unknown problem, return error */ -+ return -1; -+ } -+ -+ DRM_INFO("INFO: Number of Receivers: %d\n", hdcp_num_rec); -+ -+ for (i = 0; i < hdcp_num_rec; ++i) { -+ DRM_INFO("\tReveiver ID%2d: %.2X%.2X%.2X%.2X%.2X\n", -+ i, -+ hdcp_rec_id[i][0], -+ hdcp_rec_id[i][1], -+ hdcp_rec_id[i][2], -+ hdcp_rec_id[i][3], -+ hdcp_rec_id[i][4] -+ ); -+ } -+ -+ /* swap ids byte order */ -+ cdns_hdcp_swap_list(&hdcp_rec_id[0][0], -+ &hdcp_rec_id_temp[0][0], hdcp_num_rec); -+ -+ /* Check Receiver ID's against revocation list in SRM */ -+ if (drm_hdcp_check_ksvs_revoked(mhdp->drm_dev, (u8 *)hdcp_rec_id_temp, hdcp_num_rec)) { -+ mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; -+ DRM_ERROR("INFO: Receiver check fails\n"); -+ return -1; -+ } -+ -+ ret = cdns_mhdp_hdcp_tx_respond_receiver_id_valid(mhdp, 1); -+ DRM_INFO("INFO: Responding with Receiver ID's OK!, ret=%d\n", ret); -+ return ret; -+} -+ -+#ifdef STORE_PAIRING -+static int cdns_hdcp_get_stored_pairing(struct cdns_mhdp_device *mhdp) -+{ -+ int ret = 0; -+ unsigned long timeout = jiffies + msecs_to_jiffies(IMX_FW_TIMEOUT_MS); -+ unsigned long sleep = 1000; -+ const struct firmware *fw; -+ -+ DRM_DEBUG_KMS("%s()\n", __func__); -+ -+ while (time_before(jiffies, timeout)) { -+ ret = request_firmware(&fw, cdns_hdcp_PAIRING_FIRMWARE, mhdp->dev); -+ if (ret == -ENOENT) { -+ msleep(sleep); -+ sleep *= 2; -+ continue; -+ } else if (ret) { -+ DRM_DEV_INFO(mhdp->dev, "HDCP pairing data not found\n"); -+ goto out; -+ } -+ -+ mhdp->hdcp.num_paired = fw->size / -+ sizeof(struct hdcp_trans_pairing_data); -+ if (mhdp->hdcp.num_paired > MAX_STORED_KM) { -+ /* todo: handle dropping */ -+ mhdp->hdcp.num_paired = MAX_STORED_KM; -+ DRM_DEV_INFO(mhdp->dev, -+ "too many paired receivers - dropping older entries\n"); -+ } -+ memcpy(&mhdp->hdcp.pairing[0], fw->data, -+ sizeof(struct hdcp_trans_pairing_data) * mhdp->hdcp.num_paired); -+ release_firmware(fw); -+ goto out; -+ } -+ -+ DRM_DEV_ERROR(mhdp->dev, "Timed out trying to load firmware\n"); -+ ret = -ETIMEDOUT; -+ out: -+ return ret; -+} -+#endif -+ -+static int cdns_hdcp_find_km_store(struct cdns_mhdp_device *mhdp, -+ u8 receiver[HDCP_PAIRING_R_ID]) -+{ -+ int i; -+ -+ DRM_DEBUG_KMS("%s()\n", __func__); -+ for (i = 0; i < mhdp->hdcp.num_paired; i++) { -+ if (memcmp(receiver, mhdp->hdcp.pairing[i].receiver_id, -+ HDCP_PAIRING_R_ID) == 0) { -+ DRM_INFO("HDCP: found receiver id: 0x%x%x%x%x%x\n", -+ receiver[0], receiver[1], receiver[2], receiver[3], receiver[4]); -+ return i; -+ } -+ } -+ DRM_INFO("HDCP: receiver id: 0x%x%x%x%x%x not stored\n", -+ receiver[0], receiver[1], receiver[2], receiver[3], receiver[4]); -+ return -1; -+} -+ -+static int cdns_hdcp_store_km(struct cdns_mhdp_device *mhdp, -+ struct hdcp_trans_pairing_data *pairing, -+ int stored_km_index) -+{ -+ int i, temp_index; -+ struct hdcp_trans_pairing_data temp_pairing; -+ -+ DRM_DEBUG_KMS("%s()\n", __func__); -+ -+ if (stored_km_index < 0) { -+ /* drop one entry if array is full */ -+ if (mhdp->hdcp.num_paired == MAX_STORED_KM) -+ mhdp->hdcp.num_paired--; -+ -+ temp_index = mhdp->hdcp.num_paired; -+ mhdp->hdcp.num_paired++; -+ if (!pairing) { -+ DRM_ERROR("NULL HDCP pairing data!\n"); -+ return -1; -+ } else -+ /* save the new stored km */ -+ temp_pairing = *pairing; -+ } else { -+ /* save the current stored km */ -+ temp_index = stored_km_index; -+ temp_pairing = mhdp->hdcp.pairing[stored_km_index]; -+ } -+ -+ /* move entries one slot to the end */ -+ for (i = temp_index; i > 0; i--) -+ mhdp->hdcp.pairing[i] = mhdp->hdcp.pairing[i - 1]; -+ -+ /* save the current/new entry at the beginning */ -+ mhdp->hdcp.pairing[0] = temp_pairing; -+ -+ return 0; -+} -+ -+static inline int cdns_hdcp_auth_22(struct cdns_mhdp_device *mhdp) -+{ -+ int km_idx = -1; -+ u8 retEvents; -+ u16 hdcp_port_status; -+ u8 resp[HDCP_STATUS_SIZE]; -+ struct hdcp_trans_pairing_data pairing; -+ int ret; -+ -+ DRM_DEBUG_KMS("HDCP: Start 2.2 Authentication\n"); -+ mhdp->hdcp.sink_is_repeater = 0; -+ -+ /* Wait until HDCP2_TX_IS_KM_STORED EVENT appears */ -+ retEvents = 0; -+ DRM_DEBUG_KMS("INFO: Wait until HDCP2_TX_IS_KM_STORED EVENT appears\n"); -+ while (check_event(retEvents, HDCPTX_IS_KM_STORED_EVENT) == 0) { -+ DRM_DEBUG_KMS("INFO: Waiting FOR _IS_KM_STORED EVENT\n"); -+ retEvents = wait4event(mhdp, &mhdp->hdcp.events, -+ HDCPTX_IS_KM_STORED_EVENT, HDCP_EVENT_TO_DEF); -+ if (retEvents == 0) -+ /* time out occurred, return error */ -+ return -1; -+ if (check_event(retEvents, HDCPTX_STATUS_EVENT) != 0) { -+ /* There was a status update, could be due to HPD -+ going down or some other error, check if an error -+ was set, if so exit. -+ */ -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ if (cdns_hdcp_handle_status(hdcp_port_status) != 0) -+ return -1; -+ } -+ } -+ -+ DRM_DEBUG_KMS("HDCP: HDCPTX_IS_KM_STORED_EVENT\n"); -+ -+ /* Set HDCP2 TX KM STORED REQUEST */ -+ ret = cdns_mhdp_hdcp2_tx_is_km_stored_req(mhdp, resp, HDCP_STATUS_SIZE); -+ if (ret) { -+ DRM_DEV_ERROR(mhdp->dev, "Failed to hdcp2 tx km stored.\n"); -+ return -1; -+ } -+ -+ DRM_DEBUG_KMS("HDCP: CDN_API_HDCP2_TX_IS_KM_STORED_REQ_blocking\n"); -+ DRM_DEBUG_KMS("HDCP: Receiver ID: 0x%x%x%x%x%x\n", -+ resp[0], resp[1], resp[2], resp[3], resp[4]); -+ -+ km_idx = cdns_hdcp_find_km_store(mhdp, resp); -+ -+ /* Check if KM is stored */ -+ if (km_idx >= 0) { -+ DRM_DEBUG_KMS("INFO: KM is stored\n"); -+ /* Set HDCP2 TX RESPOND KM with stored KM */ -+ ret = cdns_mhdp_hdcp2_tx_respond_km(mhdp, (u8 *)&mhdp->hdcp.pairing[km_idx], -+ sizeof(struct hdcp_trans_pairing_data)); -+ -+ DRM_DEBUG_KMS("HDCP: CDN_API_HDCP2_TX_RESPOND_KM_blocking, ret=%d\n", ret); -+ } else { /* KM is not stored */ -+ /* Set HDCP2 TX RESPOND KM with empty data */ -+ ret = cdns_mhdp_hdcp2_tx_respond_km(mhdp, NULL, 0); -+ DRM_DEBUG_KMS("INFO: KM is not stored ret=%d\n", ret); -+ } -+ -+ if (cdns_hdcp_check_receviers(mhdp)) -+ return -1; -+ -+ /* Check if KM is not stored */ -+ if (km_idx < 0) { -+ int loop_cnt = 0; -+ -+ /* Wait until HDCP2_TX_STORE_KM EVENT appears */ -+ retEvents = 0; -+ DRM_DEBUG_KMS("INFO: wait4event -> HDCPTX_STORE_KM_EVENT\n"); -+ while (check_event(retEvents, HDCPTX_STORE_KM_EVENT) == 0) { -+ retEvents = wait4event(mhdp, &mhdp->hdcp.events, -+ HDCPTX_STORE_KM_EVENT, HDCP_EVENT_TO_DEF); -+ if (check_event(retEvents, HDCPTX_STATUS_EVENT) -+ != 0) { -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ if (cdns_hdcp_handle_status(hdcp_port_status) -+ != 0) -+ return -1; -+ } -+ if (loop_cnt > 2) { -+ DRM_ERROR("Did not get event HDCPTX_STORE_KM_EVENT in time\n"); -+ return -1; -+ } else -+ loop_cnt++; -+ } -+ DRM_DEBUG_KMS("HDCP: HDCPTX_STORE_KM_EVENT\n"); -+ -+ /* Set HDCP2_TX_STORE_KM REQUEST */ -+ ret = cdns_mhdp_hdcp2_tx_store_km(mhdp, (u8 *)&pairing, sizeof(struct hdcp_trans_pairing_data)); -+ DRM_DEBUG_KMS("HDCP: CDN_API_HDCP2_TX_STORE_KM_REQ_blocking ret=%d\n", ret); -+ cdns_hdcp_store_km(mhdp, &pairing, km_idx); -+ } else -+ cdns_hdcp_store_km(mhdp, NULL, km_idx); -+ -+ /* Check if device was a repeater */ -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ -+ /* Exit if there was any errors logged at this point... */ -+ if (GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status) > 0) { -+ cdns_hdcp_handle_status(hdcp_port_status); -+ return -1; -+ } -+ -+ if (hdcp_port_status & HDCP_PORT_STS_REPEATER) -+ mhdp->hdcp.sink_is_repeater = 1; -+ -+ /* If sink was a repeater, we will be getting additional IDs to validate... -+ * Note that this one may take some time since spec allows up to 3s... */ -+ if (mhdp->hdcp.sink_is_repeater) -+ if (cdns_hdcp_check_receviers(mhdp)) -+ return -1; -+ -+ /* Slight delay to allow firmware to finish setting up authenticated state */ -+ msleep(300); -+ -+ DRM_INFO("Finished cdns_hdcp_auth_22\n"); -+ return 0; -+} -+ -+static inline int cdns_hdcp_auth_14(struct cdns_mhdp_device *mhdp) -+{ -+ u16 hdcp_port_status; -+ int ret = 0; -+ -+ DRM_DEBUG_KMS("HDCP: Starting 1.4 Authentication\n"); -+ mhdp->hdcp.sink_is_repeater = 0; -+ -+ ret = cdns_hdcp_check_receviers(mhdp); -+ if (ret) -+ return -1; -+ -+ /* Check if device was a repeater */ -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ -+ /* Exit if there was any errors logged at this point... */ -+ if (GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status) > 0) { -+ cdns_hdcp_handle_status(hdcp_port_status); -+ return -1; -+ } -+ -+ if (hdcp_port_status & HDCP_PORT_STS_REPEATER) { -+ DRM_INFO("Connected to a repeater\n"); -+ mhdp->hdcp.sink_is_repeater = 1; -+ } else -+ DRM_INFO("Connected to a normal sink\n"); -+ -+ /* If sink was a repeater, we will be getting additional IDs to validate... -+ * Note that this one may take some time since spec allows up to 3s... */ -+ if (mhdp->hdcp.sink_is_repeater) -+ ret = cdns_hdcp_check_receviers(mhdp); -+ -+ /* Slight delay to allow firmware to finish setting up authenticated state */ -+ msleep(300); -+ -+ return ret; -+} -+ -+static int cdns_hdcp_auth(struct cdns_mhdp_device *mhdp, u8 hdcp_config) -+{ -+ int ret = 0; -+ -+ DRM_DEBUG_KMS("HDCP: Start Authentication\n"); -+ -+ if (mhdp->hdcp.reauth_in_progress == 0) { -+ ret = cdns_hdcp_set_config(mhdp, hdcp_config); -+ if (ret) { -+ DRM_ERROR("cdns_hdcp_set_config failed\n"); -+ return -1; -+ } -+ } -+ -+ mhdp->hdcp.reauth_in_progress = 0; -+ mhdp->hdcp.sink_is_repeater = 0; -+ mhdp->hdcp.hdcp_version = hdcp_config; -+ -+ do { -+ if (mhdp->hdcp.cancel == 1) { -+ DRM_ERROR("mhdp->hdcp.cancel is TRUE\n"); -+ return -ECANCELED; -+ } -+ -+ if (hdcp_config == HDCP_TX_1) -+ ret = cdns_hdcp_auth_14(mhdp); -+ else -+ ret = cdns_hdcp_auth_22(mhdp); -+ if (ret) { -+ u16 hdcp_port_status; -+ DRM_ERROR("cdns_hdcp_auth_%s failed\n", -+ (hdcp_config == HDCP_TX_1) ? "14" : "22"); -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ cdns_hdcp_handle_status(hdcp_port_status); -+ return -1; -+ } -+ -+ ret = cdns_hdcp_auth_check(mhdp); -+ } while (ret == 1); -+ -+ return ret; -+} -+ -+static int _cdns_hdcp_disable(struct cdns_mhdp_device *mhdp) -+{ -+ int ret = 0; -+ u8 hdcp_cfg = (HDCP_USE_KMKEY << 4); -+ -+ DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n", -+ mhdp->connector.base.name, mhdp->connector.base.base.id); -+ DRM_DEBUG_KMS("INFO: Disabling HDCP...\n"); -+ -+ ret = cdns_mhdp_hdcp_tx_config(mhdp, hdcp_cfg); -+ if (ret < 0) -+ DRM_DEBUG_KMS("cdns_mhdp_hdcp_tx_config failed\n"); -+ -+ DRM_DEBUG_KMS("HDCP is disabled\n"); -+ -+ mhdp->hdcp.events = 0; -+ -+ return ret; -+} -+ -+static int _cdns_hdcp_enable(struct cdns_mhdp_device *mhdp) -+{ -+ int i, ret = 0, tries = 9; -+ u8 hpd_sts; -+ -+ hpd_sts = cdns_mhdp_read_hpd(mhdp); -+ if (hpd_sts == 0) { -+ dev_info(mhdp->dev, "%s HDP detected low, set state to DISABLING\n", __func__); -+ mhdp->hdcp.state = HDCP_STATE_DISABLING; -+ return -1; -+ } -+ -+ DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n", -+ mhdp->connector.base.name, mhdp->connector.base.base.id); -+ -+ mhdp->hdcp.events = 0; -+ -+ /* Incase of authentication failures, HDCP spec expects reauth. */ -+ /* TBD should this actually try 2.2 n times then 1.4? */ -+ for (i = 0; i < tries; i++) { -+ if (mhdp->hdcp.config & HDCP_CONFIG_2_2) { -+ ret = cdns_hdcp_auth(mhdp, HDCP_TX_2); -+ if (ret == 0) -+ return 0; -+ else if (ret == -ECANCELED) -+ return ret; -+ _cdns_hdcp_disable(mhdp); -+ } -+ } -+ -+ for (i = 0; i < tries; i++) { -+ if (mhdp->hdcp.config & HDCP_CONFIG_1_4) { -+ ret = cdns_hdcp_auth(mhdp, HDCP_TX_1); -+ if (ret == 0) -+ return 0; -+ else if (ret == -ECANCELED) -+ return ret; -+ _cdns_hdcp_disable(mhdp); -+ } -+ DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret); -+ } -+ -+ DRM_ERROR("HDCP authentication failed (%d tries/%d)\n", tries, ret); -+ return ret; -+} -+ -+static void cdns_hdcp_check_work(struct work_struct *work) -+{ -+ struct cdns_mhdp_hdcp *hdcp = container_of(work, -+ struct cdns_mhdp_hdcp, check_work.work); -+ struct cdns_mhdp_device *mhdp = container_of(hdcp, -+ struct cdns_mhdp_device, hdcp); -+ -+ /* todo: maybe we don't need to always schedule */ -+ cdns_hdcp_check_link(mhdp); -+ schedule_delayed_work(&hdcp->check_work, 50); -+} -+ -+static void cdns_hdcp_prop_work(struct work_struct *work) -+{ -+ struct cdns_mhdp_hdcp *hdcp = container_of(work, -+ struct cdns_mhdp_hdcp, prop_work); -+ struct cdns_mhdp_device *mhdp = container_of(hdcp, -+ struct cdns_mhdp_device, hdcp); -+ -+ struct drm_device *dev = mhdp->drm_dev; -+ struct drm_connector_state *state; -+ -+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); -+ mutex_lock(&mhdp->hdcp.mutex); -+ -+ /* -+ * This worker is only used to flip between ENABLED/DESIRED. Either of -+ * those to UNDESIRED is handled by core. If hdcp_value == UNDESIRED, -+ * we're running just after hdcp has been disabled, so just exit -+ */ -+ if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { -+ state = mhdp->connector.base.state; -+ state->content_protection = mhdp->hdcp.value; -+ } -+ -+ mutex_unlock(&mhdp->hdcp.mutex); -+ drm_modeset_unlock(&dev->mode_config.connection_mutex); -+} -+ -+static void show_hdcp_supported(struct cdns_mhdp_device *mhdp) -+{ -+ if ((mhdp->hdcp.config & (HDCP_CONFIG_1_4 | HDCP_CONFIG_2_2)) == -+ (HDCP_CONFIG_1_4 | HDCP_CONFIG_2_2)) -+ DRM_INFO("Both HDCP 1.4 and 2 2 are enabled\n"); -+ else if (mhdp->hdcp.config & HDCP_CONFIG_1_4) -+ DRM_INFO("Only HDCP 1.4 is enabled\n"); -+ else if (mhdp->hdcp.config & HDCP_CONFIG_2_2) -+ DRM_INFO("Only HDCP 2.2 is enabled\n"); -+ else -+ DRM_INFO("HDCP is disabled\n"); -+} -+ -+static ssize_t HDCPTX_do_reauth_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count); -+static struct device_attribute HDCPTX_do_reauth = __ATTR_WO(HDCPTX_do_reauth); -+ -+static ssize_t HDCPTX_do_reauth_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int ret; -+ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); -+ -+ ret = cdns_mhdp_hdcp_tx_reauth(mhdp, 1); -+ if (ret < 0) { -+ dev_err(dev, "%s cdns_mhdp_hdcp_tx_reauth failed\n", __func__); -+ return -1; -+ } -+ -+ return count; -+} -+ -+static ssize_t HDCPTX_Version_show(struct device *dev, -+ struct device_attribute *attr, char *buf); -+static ssize_t HDCPTX_Version_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count); -+static struct device_attribute HDCPTX_Version = __ATTR_RW(HDCPTX_Version); -+ -+static ssize_t HDCPTX_Version_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); -+ int value, ret; -+ -+ ret = kstrtoint(buf, 10, &value); -+ if (ret != 0) -+ return -EINVAL; -+ -+ if (value == 2) -+ mhdp->hdcp.config = 2; -+ else if (value == 1) -+ mhdp->hdcp.config = 1; -+ else if (value == 3) -+ mhdp->hdcp.config = 3; -+ else -+ mhdp->hdcp.config = 0; -+ -+ return count; -+} -+ -+ssize_t HDCPTX_Version_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); -+ -+ return sprintf(buf, "%d\n", mhdp->hdcp.config); -+} -+ -+static ssize_t HDCPTX_Status_show(struct device *dev, -+ struct device_attribute *attr, char *buf); -+static ssize_t HDCPTX_Status_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count); -+static struct device_attribute HDCPTX_Status = __ATTR_RW(HDCPTX_Status); -+ -+ssize_t HDCPTX_Status_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); -+ -+ switch (mhdp->hdcp.state) { -+ case HDCP_STATE_NO_AKSV: -+ return sprintf(buf, "%d :HDCP_STATE_NO_AKSV\n", mhdp->hdcp.state); -+ case HDCP_STATE_INACTIVE: -+ return sprintf(buf, "%d :HDCP_STATE_INACTIVE\n", mhdp->hdcp.state); -+ case HDCP_STATE_ENABLING: -+ return sprintf(buf, "%d :HDCP_STATE_ENABLING\n", mhdp->hdcp.state); -+ case HDCP_STATE_AUTHENTICATING: -+ return sprintf(buf, "%d :HDCP_STATE_AUTHENTICATING\n", mhdp->hdcp.state); -+ case HDCP_STATE_AUTHENTICATED: -+ return sprintf(buf, "%d :HDCP_STATE_AUTHENTICATED\n", mhdp->hdcp.state); -+ case HDCP_STATE_DISABLING: -+ return sprintf(buf, "%d :HDCP_STATE_DISABLING\n", mhdp->hdcp.state); -+ case HDCP_STATE_AUTH_FAILED: -+ return sprintf(buf, "%d :HDCP_STATE_AUTH_FAILED\n", mhdp->hdcp.state); -+ default: -+ return sprintf(buf, "%d :HDCP_STATE don't exist\n", mhdp->hdcp.state); -+ } -+} -+ -+ssize_t HDCPTX_Status_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); -+ int value, ret; -+ -+ if (count == 2) { -+ ret = kstrtoint(buf, 10, &value); -+ if (ret != 0) -+ return -EINVAL; -+ -+ if ((value >= HDCP_STATE_NO_AKSV) && (value <= HDCP_STATE_AUTH_FAILED)) { -+ mhdp->hdcp.state = value; -+ return count; -+ } -+ dev_err(dev, "%s &hdp->state invalid\n", __func__); -+ return -1; -+ } -+ -+ dev_info(dev, "%s &hdp->state desired %s count=%d\n ", __func__, buf, (int)count); -+ -+ if (strncmp(buf, "HDCP_STATE_NO_AKSV", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_NO_AKSV; -+ else if (strncmp(buf, "HDCP_STATE_INACTIVE", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_INACTIVE; -+ else if (strncmp(buf, "HDCP_STATE_ENABLING", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_ENABLING; -+ else if (strncmp(buf, "HDCP_STATE_AUTHENTICATING", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_AUTHENTICATING; -+ else if (strncmp(buf, "HDCP_STATE_AUTHENTICATED", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_AUTHENTICATED; -+ else if (strncmp(buf, "HDCP_STATE_DISABLING", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_DISABLING; -+ else if (strncmp(buf, "HDCP_STATE_AUTH_FAILED", count - 1) == 0) -+ mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; -+ else -+ dev_err(dev, "%s &hdp->state invalid\n", __func__); -+ return -1; -+} -+ -+void cnds_hdcp_create_device_files(struct cdns_mhdp_device *mhdp) -+{ -+ -+ if (device_create_file(mhdp->dev, &HDCPTX_do_reauth)) { -+ DRM_ERROR("Unable to create HDCPTX_do_reauth sysfs\n"); -+ device_remove_file(mhdp->dev, &HDCPTX_do_reauth); -+ } -+ -+ if (device_create_file(mhdp->dev, &HDCPTX_Version)) { -+ DRM_ERROR("Unable to create HDCPTX_Version sysfs\n"); -+ device_remove_file(mhdp->dev, &HDCPTX_Version); -+ } -+ -+ if (device_create_file(mhdp->dev, &HDCPTX_Status)) { -+ DRM_ERROR(KERN_ERR "Unable to create HDCPTX_Status sysfs\n"); -+ device_remove_file(mhdp->dev, &HDCPTX_Status); -+ } -+} -+EXPORT_SYMBOL(cnds_hdcp_create_device_files); -+ -+#ifdef DEBUG -+void cdns_hdcp_show_pairing(struct cdns_mhdp_device *mhdp, struct hdcp_trans_pairing_data *p) -+{ -+ char s[80]; -+ int i, k; -+ -+ DRM_INFO("Reveiver ID: %.2X%.2X%.2X%.2X%.2X\n", -+ p->receiver_id[0], -+ p->receiver_id[1], -+ p->receiver_id[2], -+ p->receiver_id[3], -+ p->receiver_id[4]); -+ for (k = 0, i = 0; k < 16; k++) -+ i += snprintf(&s[i], sizeof(s), "%02x", p->m[k]); -+ -+ DRM_INFO("\tm: %s\n", s); -+ -+ for (k = 0, i = 0; k < 16; k++) -+ i += snprintf(&s[i], sizeof(s), "%02x", p->km[k]); -+ -+ DRM_INFO("\tkm: %s\n", s); -+ -+ for (k = 0, i = 0; k < 16; k++) -+ i += snprintf(&s[i], sizeof(s), "%02x", p->ekh[k]); -+ -+ DRM_INFO("\tekh: %s\n", s); -+} -+#endif -+ -+void cdns_hdcp_dump_pairing(struct seq_file *s, void *data) -+{ -+ struct cdns_mhdp_device *mhdp = data; -+#ifdef DEBUG -+ int i; -+ for (i = 0; i < mhdp->hdcp.num_paired; i++) -+ cdns_hdcp_show_pairing(mhdp, &mhdp->hdcp.pairing[i]); -+#endif -+ seq_write(s, &mhdp->hdcp.pairing[0], -+ mhdp->hdcp.num_paired * sizeof(struct hdcp_trans_pairing_data)); -+} -+ -+static int cdns_hdcp_pairing_show(struct seq_file *s, void *data) -+{ -+ cdns_hdcp_dump_pairing(s, s->private); -+ return 0; -+} -+ -+static int cdns_hdcp_dump_pairing_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, cdns_hdcp_pairing_show, inode->i_private); -+} -+ -+static const struct file_operations cdns_hdcp_dump_fops = { -+ .open = cdns_hdcp_dump_pairing_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static void cdns_hdcp_debugfs_init(struct cdns_mhdp_device *mhdp) -+{ -+ struct dentry *d, *root; -+ -+ root = debugfs_create_dir("imx-hdcp", NULL); -+ if (IS_ERR(root) || !root) -+ goto err; -+ -+ d = debugfs_create_file("dump_pairing", 0444, root, mhdp, -+ &cdns_hdcp_dump_fops); -+ if (!d) -+ goto err; -+ return; -+ -+err: -+ dev_err(mhdp->dev, "Unable to create debugfs entries\n"); -+} -+ -+int cdns_hdcp_init(struct cdns_mhdp_device *mhdp, struct device_node *of_node) -+{ -+ const char *compat; -+ u32 temp; -+ int ret; -+ -+ ret = of_property_read_string(of_node, "compatible", &compat); -+ if (ret) { -+ DRM_ERROR("Failed to compatible dts string\n"); -+ return ret; -+ } -+ -+ if (!(strstr(compat, "hdmi") || strstr(compat, "dp"))) -+ return -EPERM; -+ -+ ret = of_property_read_u32(of_node, "hdcp-config", &temp); -+ if (ret) { -+ /* using highest level by default */ -+ mhdp->hdcp.config = HDCP_CONFIG_2_2; -+ DRM_INFO("Failed to get HDCP config - using HDCP 2.2 only\n"); -+ } else { -+ mhdp->hdcp.config = temp; -+ show_hdcp_supported(mhdp); -+ } -+ -+ cdns_hdcp_debugfs_init(mhdp); -+ -+#ifdef USE_DEBUG_KEYS /* reserve for hdcp test key */ -+ { -+ u8 hdcp_cfg; -+ hdcp_cfg = HDCP_TX_2 | (HDCP_USE_KMKEY << 4) | (HDCP_CONTENT_TYPE_0 << 3); -+ imx_hdmi_load_test_keys(mhdp, &hdcp_cfg); -+ } -+#endif -+ -+ mhdp->hdcp.state = HDCP_STATE_INACTIVE; -+ -+ mutex_init(&mhdp->hdcp.mutex); -+ INIT_DELAYED_WORK(&mhdp->hdcp.check_work, cdns_hdcp_check_work); -+ INIT_WORK(&mhdp->hdcp.prop_work, cdns_hdcp_prop_work); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(cdns_hdcp_init); -+ -+int cdns_hdcp_enable(struct cdns_mhdp_device *mhdp) -+{ -+ int ret = 0; -+ -+ mhdp->hdcp.reauth_in_progress = 0; -+ -+#ifdef STORE_PAIRING -+ cdns_hdcp_get_stored_pairing(mhdp); -+#endif -+ msleep(500); -+ -+ mutex_lock(&mhdp->hdcp.mutex); -+ -+ mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; -+ mhdp->hdcp.state = HDCP_STATE_ENABLING; -+ mhdp->hdcp.cancel = 0; -+ -+ schedule_work(&mhdp->hdcp.prop_work); -+ schedule_delayed_work(&mhdp->hdcp.check_work, 50); -+ -+ mutex_unlock(&mhdp->hdcp.mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_hdcp_enable); -+ -+int cdns_hdcp_disable(struct cdns_mhdp_device *mhdp) -+{ -+ int ret = 0; -+ -+ cancel_delayed_work_sync(&mhdp->hdcp.check_work); -+ -+ mutex_lock(&mhdp->hdcp.mutex); -+ if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { -+ mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; -+ mhdp->hdcp.state = HDCP_STATE_DISABLING; -+ mhdp->hdcp.cancel = 1; -+ schedule_work(&mhdp->hdcp.prop_work); -+ } -+ -+ mutex_unlock(&mhdp->hdcp.mutex); -+ -+ /* Make sure HDCP_STATE_DISABLING state is handled */ -+ cdns_hdcp_check_link(mhdp); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_hdcp_disable); -+ -+void cdns_hdcp_atomic_check(struct drm_connector *connector, -+ struct drm_connector_state *old_state, -+ struct drm_connector_state *new_state) -+{ -+ u64 old_cp = old_state->content_protection; -+ u64 new_cp = new_state->content_protection; -+ struct drm_crtc_state *crtc_state; -+ -+ if (!new_state->crtc) { -+ /* -+ * If the connector is being disabled with CP enabled, mark it -+ * desired so it's re-enabled when the connector is brought back -+ */ -+ if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) -+ new_state->content_protection = -+ DRM_MODE_CONTENT_PROTECTION_DESIRED; -+ return; -+ } -+ -+ /* -+ * Nothing to do if the state didn't change, or HDCP was activated since -+ * the last commit -+ */ -+ if (old_cp == new_cp || -+ (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && -+ new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) -+ return; -+ -+ crtc_state = drm_atomic_get_new_crtc_state(new_state->state, new_state->crtc); -+ crtc_state->mode_changed = true; -+} -+EXPORT_SYMBOL_GPL(cdns_hdcp_atomic_check); -+ -+static int cdns_hdcp_check_link(struct cdns_mhdp_device *mhdp) -+{ -+ u16 hdcp_port_status = 0; -+ u8 hdcp_last_error = 0; -+ u8 hpd_sts; -+ int ret = 0; -+ -+ mhdp->hdcp.reauth_in_progress = 0; -+ mutex_lock(&mhdp->lock); -+ -+ if (mhdp->hdcp.state == HDCP_STATE_INACTIVE) -+ goto out; -+ -+ if (mhdp->hdcp.state == HDCP_STATE_DISABLING) { -+ _cdns_hdcp_disable(mhdp); -+ mhdp->hdcp.state = HDCP_STATE_INACTIVE; -+ goto out; -+ } -+ -+ if ((mhdp->hdcp.state == HDCP_STATE_AUTHENTICATED) || -+ (mhdp->hdcp.state == HDCP_STATE_AUTHENTICATING) || -+ (mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING) || -+ (mhdp->hdcp.state == HDCP_STATE_ENABLING)) { -+ -+ /* In active states, check the HPD signal. Because of the IRQ -+ * debounce delay, the state might not reflect the disconnection. -+ * The FW could already have detected the HDP down and reported error */ -+ hpd_sts = cdns_mhdp_read_hpd(mhdp); -+ if (hpd_sts == 0) { -+ mhdp->hdcp.state = HDCP_STATE_DISABLING; -+ goto out; -+ } -+ } -+ -+/* TODO items: -+ Need to make sure that any requests from the firmware are actually -+ processed so want to remove this first jump to 'out', i.e. process -+ reauthentication requests, cleanup errors and repeater receiver id -+ checks. -+*/ -+ if (mhdp->hdcp.state == HDCP_STATE_AUTHENTICATED) { -+ /* get port status */ -+ hdcp_port_status = cdns_hdcp_get_status(mhdp); -+ hdcp_last_error = GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status); -+ if (hdcp_last_error == HDCP_TRAN_ERR_REAUTH_REQ) { -+ DRM_INFO("Sink requesting re-authentication\n"); -+ mhdp->hdcp.state = HDCP_STATE_REAUTHENTICATING; -+ } else if (hdcp_last_error) { -+ DRM_ERROR("HDCP error no: %u\n", hdcp_last_error); -+ -+ if (mhdp->hdcp.value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) -+ goto out; -+ if (hdcp_port_status & HDCP_PORT_STS_AUTH) { -+ if (mhdp->hdcp.value != -+ DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { -+ mhdp->hdcp.value = -+ DRM_MODE_CONTENT_PROTECTION_ENABLED; -+ schedule_work(&mhdp->hdcp.prop_work); -+ goto out; -+ } -+ } -+ -+ mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; -+ -+ } else if (mhdp->hdcp.sink_is_repeater) { -+ u8 new_events; -+ /* Check events... and process if HDCPTX_IS_RECEIVER_ID_VALID_EVENT. */ -+ new_events = cdns_mhdp_get_event(mhdp); -+ mhdp->hdcp.events |= new_events; -+ if (check_event(mhdp->hdcp.events, HDCPTX_IS_RECEIVER_ID_VALID_EVENT)) { -+ DRM_INFO("Sink repeater updating receiver ID list...\n"); -+ if (cdns_hdcp_check_receviers(mhdp)) -+ mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; -+ } -+ } -+ } -+ -+ if (mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING) { -+ /* For now just deal with HDCP2.2 */ -+ if (mhdp->hdcp.hdcp_version == HDCP_TX_2) -+ mhdp->hdcp.reauth_in_progress = 1; -+ else -+ mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; -+ } -+ -+ if (mhdp->hdcp.state == HDCP_STATE_ENABLING) { -+ mhdp->hdcp.state = HDCP_STATE_AUTHENTICATING; -+ ret = _cdns_hdcp_enable(mhdp); -+ if (ret == -ECANCELED) -+ goto out; -+ else if (ret) { -+ DRM_ERROR("Failed to enable hdcp (%d)\n", ret); -+ mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; -+ schedule_work(&mhdp->hdcp.prop_work); -+ goto out; -+ } -+ } -+ -+ if ((mhdp->hdcp.state == HDCP_STATE_AUTH_FAILED) || -+ (mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING)) { -+ -+ print_port_status(hdcp_port_status); -+ if (mhdp->hdcp.state == HDCP_STATE_AUTH_FAILED) { -+ DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication 0x%2x\n", -+ mhdp->connector.base.name, mhdp->connector.base.base.id, hdcp_port_status); -+ ret = _cdns_hdcp_disable(mhdp); -+ if (ret) { -+ DRM_ERROR("Failed to disable hdcp (%d)\n", ret); -+ mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; -+ schedule_work(&mhdp->hdcp.prop_work); -+ goto out; -+ } -+ } else -+ DRM_DEBUG_KMS("[%s:%d] HDCP attempt reauthentication 0x%2x\n", -+ mhdp->connector.base.name, mhdp->connector.base.base.id, hdcp_port_status); -+ -+ ret = _cdns_hdcp_enable(mhdp); -+ if (ret == -ECANCELED) -+ goto out; -+ else if (ret) { -+ DRM_ERROR("Failed to enable hdcp (%d)\n", ret); -+ mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; -+ schedule_work(&mhdp->hdcp.prop_work); -+ goto out; -+ } -+ } -+ -+out: -+ mutex_unlock(&mhdp->lock); -+ -+ return ret; -+} -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h b/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h -new file mode 100644 -index 000000000..9de875925 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h -@@ -0,0 +1,23 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2021 NXP Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+ -+#ifndef CDNS_HDCP_COMMON_H -+#define CDNS_HDCP_COMMON_H -+ -+int cdns_hdcp_init(struct cdns_mhdp_device *mhdp, struct device_node *of_node); -+int cdns_hdcp_enable(struct cdns_mhdp_device *mhdp); -+int cdns_hdcp_disable(struct cdns_mhdp_device *mhdp); -+void cdns_hdcp_atomic_check(struct drm_connector *connector, -+ struct drm_connector_state *old_state, -+ struct drm_connector_state *new_state); -+void cnds_hdcp_create_device_files(struct cdns_mhdp_device *mhdp); -+ -+#endif /* CDNS_HDCP_COMMON_H */ -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c -new file mode 100644 -index 000000000..18ae36cd3 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c -@@ -0,0 +1,365 @@ -+/* -+ * Copyright 2019-2020 NXP -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+#define CEC_NAME "cdns-mhdp-cec" -+ -+#define REG_ADDR_OFF 4 -+ -+/* regsiter define */ -+#define TX_MSG_HEADER 0x33800 -+#define TX_MSG_LENGTH 0x33840 -+#define TX_MSG_CMD 0x33844 -+#define RX_MSG_CMD 0x33850 -+#define RX_CLEAR_BUF 0x33854 -+#define LOGICAL_ADDRESS_LA0 0x33858 -+ -+#define CLK_DIV_MSB 0x3386c -+#define CLK_DIV_LSB 0x33870 -+#define RX_MSG_DATA1 0x33900 -+#define RX_MSG_LENGTH 0x33940 -+#define RX_MSG_STATUS 0x33944 -+#define NUM_OF_MSG_RX_BUF 0x33948 -+#define TX_MSG_STATUS 0x3394c -+#define DB_L_TIMER 0x33980 -+ -+/** -+ * CEC Transceiver operation. -+ */ -+enum { -+ CEC_TX_STOP, -+ CEC_TX_TRANSMIT, -+ CEC_TX_ABORT, -+ CEC_TX_ABORT_AND_TRANSMIT -+}; -+ -+/** -+ * CEC Transceiver status. -+ */ -+enum { -+ CEC_STS_IDLE, -+ CEC_STS_BUSY, -+ CEC_STS_SUCCESS, -+ CEC_STS_ERROR -+}; -+ -+/** -+ * CEC Receiver operation. -+ */ -+enum { -+ CEC_RX_STOP, -+ CEC_RX_READ, -+ CEC_RX_DISABLE, -+ CEC_RX_ABORT_AND_CLR_FIFO -+}; -+/** -+ * Maximum number of Messages in the RX Buffers. -+ */ -+#define CEC_MAX_RX_MSGS 2 -+ -+static u32 mhdp_cec_read(struct cdns_mhdp_cec *cec, u32 offset) -+{ -+ u32 val; -+ -+ mutex_lock(cec->iolock); -+ -+ if (cec->bus_type == BUS_TYPE_LOW4K_HDMI_RX) { -+ /* Remap address to low 4K HDMI RX */ -+ writel(offset >> 12, cec->regs_sec + 4); -+ val = readl((offset & 0xfff) + cec->regs_base); -+ } else if (cec->bus_type == BUS_TYPE_LOW4K_APB) { -+ /* Remap address to low 4K memory */ -+ writel(offset >> 12, cec->regs_sec + 8); -+ val = readl((offset & 0xfff) + cec->regs_base); -+ } else -+ val = readl(cec->regs_base + offset); -+ -+ mutex_unlock(cec->iolock); -+ -+ return val; -+} -+ -+static void mhdp_cec_write(struct cdns_mhdp_cec *cec, u32 offset, u32 val) -+{ -+ mutex_lock(cec->iolock); -+ -+ if (cec->bus_type == BUS_TYPE_LOW4K_HDMI_RX) { -+ /* Remap address to low 4K SAPB bus */ -+ writel(offset >> 12, cec->regs_sec + 4); -+ writel(val, (offset & 0xfff) + cec->regs_base); -+ } else if (cec->bus_type == BUS_TYPE_LOW4K_APB) { -+ /* Remap address to low 4K memory */ -+ writel(offset >> 12, cec->regs_sec + 8); -+ writel(val, (offset & 0xfff) + cec->regs_base); -+ } else if (cec->bus_type == BUS_TYPE_NORMAL_SAPB) -+ writel(val, cec->regs_sec + offset); -+ else -+ writel(val, cec->regs_base + offset); -+ -+ mutex_unlock(cec->iolock); -+} -+ -+static u32 mhdp_get_fw_clk(struct cdns_mhdp_cec *cec) -+{ -+ return mhdp_cec_read(cec, SW_CLK_H); -+} -+ -+static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec) -+{ -+ mhdp_cec_write(cec, RX_CLEAR_BUF, 1); -+ mhdp_cec_write(cec, RX_CLEAR_BUF, 0); -+} -+ -+static void mhdp_cec_set_divider(struct cdns_mhdp_cec *cec) -+{ -+ u32 clk_div; -+ -+ /* Set clock divider */ -+ clk_div = mhdp_get_fw_clk(cec) * 10; -+ -+ mhdp_cec_write(cec, CLK_DIV_MSB, -+ (clk_div >> 8) & 0xFF); -+ mhdp_cec_write(cec, CLK_DIV_LSB, clk_div & 0xFF); -+} -+ -+static u32 mhdp_cec_read_message(struct cdns_mhdp_cec *cec) -+{ -+ struct cec_msg *msg = &cec->msg; -+ int len; -+ int i; -+ -+ mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_READ); -+ -+ len = mhdp_cec_read(cec, RX_MSG_LENGTH); -+ msg->len = len + 1; -+ dev_dbg(cec->dev, "RX MSG len =%d\n", len); -+ -+ /* Read RX MSG bytes */ -+ for (i = 0; i < msg->len; ++i) { -+ msg->msg[i] = (u8) mhdp_cec_read(cec, RX_MSG_DATA1 + (i * REG_ADDR_OFF)); -+ dev_dbg(cec->dev, "RX MSG[%d]=0x%x\n", i, msg->msg[i]); -+ } -+ -+ mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_STOP); -+ -+ return true; -+} -+ -+static u32 mhdp_cec_write_message(struct cdns_mhdp_cec *cec, struct cec_msg *msg) -+{ -+ u8 i; -+ -+ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); -+ -+ if (msg->len > CEC_MAX_MSG_SIZE) { -+ dev_err(cec->dev, "Invalid MSG size!\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < msg->len; ++i) -+ printk("msg[%d]=0x%x\n",i, msg->msg[i]); -+ -+ /* Write Message to register */ -+ for (i = 0; i < msg->len; ++i) { -+ mhdp_cec_write(cec, TX_MSG_HEADER + (i * REG_ADDR_OFF), -+ msg->msg[i]); -+ } -+ /* Write Message Length (payload + opcode) */ -+ mhdp_cec_write(cec, TX_MSG_LENGTH, msg->len - 1); -+ -+ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_TRANSMIT); -+ -+ return true; -+} -+ -+static int mhdp_cec_set_logical_addr(struct cdns_mhdp_cec *cec, u32 la) -+{ -+ u8 la_reg; -+ u8 i; -+ -+ if (la == CEC_LOG_ADDR_INVALID) { -+ /* invalid all LA address */ -+ for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) -+ mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), 0); -+ return 0; -+ } -+ -+ /* In fact cdns mhdp cec could support max 5 La address */ -+ for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) { -+ la_reg = mhdp_cec_read(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF)); -+ /* Check LA already used */ -+ if (la_reg & 0x10) -+ continue; -+ -+ if ((la_reg & 0xF) == la) { -+ dev_warn(cec->dev, "Warning. LA already in use.\n"); -+ return 0; -+ } -+ -+ la = (la & 0xF) | (1 << 4); -+ -+ mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), la); -+ return 0; -+ } -+ -+ dev_warn(cec->dev, "All LA in use\n"); -+ -+ return -ENXIO; -+} -+ -+static int mhdp_cec_poll_worker(void *_cec) -+{ -+ struct cdns_mhdp_cec *cec = (struct cdns_mhdp_cec *)_cec; -+ int num_rx_msgs, i; -+ int sts; -+ -+ set_freezable(); -+ -+ for (;;) { -+ if (kthread_freezable_should_stop(NULL)) -+ break; -+ -+ /* Check TX State */ -+ sts = mhdp_cec_read(cec, TX_MSG_STATUS); -+ switch (sts) { -+ case CEC_STS_SUCCESS: -+ cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, -+ 0); -+ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); -+ break; -+ case CEC_STS_ERROR: -+ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); -+ cec_transmit_done(cec->adap, -+ CEC_TX_STATUS_MAX_RETRIES | -+ CEC_TX_STATUS_NACK, 0, 1, 0, 0); -+ break; -+ case CEC_STS_BUSY: -+ default: -+ break; -+ } -+ -+ /* Check RX State */ -+ sts = mhdp_cec_read(cec, RX_MSG_STATUS); -+ num_rx_msgs = mhdp_cec_read(cec, NUM_OF_MSG_RX_BUF); -+ switch (sts) { -+ case CEC_STS_SUCCESS: -+ if (num_rx_msgs == 0xf) -+ num_rx_msgs = CEC_MAX_RX_MSGS; -+ -+ if (num_rx_msgs > CEC_MAX_RX_MSGS) { -+ dev_err(cec->dev, "Error rx msg num %d\n", -+ num_rx_msgs); -+ mhdp_cec_clear_rx_buffer(cec); -+ break; -+ } -+ -+ /* Rx FIFO Depth 2 RX MSG */ -+ for (i = 0; i < num_rx_msgs; i++) { -+ mhdp_cec_read_message(cec); -+ cec->msg.rx_status = CEC_RX_STATUS_OK; -+ cec_received_msg(cec->adap, &cec->msg); -+ } -+ break; -+ default: -+ break; -+ } -+ -+ if (!kthread_should_stop()) -+ schedule_timeout_idle(20); -+ } -+ -+ return 0; -+} -+ -+static int mhdp_cec_adap_enable(struct cec_adapter *adap, bool enable) -+{ -+ struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); -+ -+ if (enable) { -+ mhdp_cec_write(cec, DB_L_TIMER, 0x10); -+ mhdp_cec_set_divider(cec); -+ } else -+ mhdp_cec_set_divider(cec); -+ -+ return 0; -+} -+ -+static int mhdp_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) -+{ -+ struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); -+ -+ return mhdp_cec_set_logical_addr(cec, addr); -+} -+ -+static int mhdp_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, -+ u32 signal_free_time, struct cec_msg *msg) -+{ -+ struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); -+ -+ mhdp_cec_write_message(cec, msg); -+ -+ return 0; -+} -+ -+static const struct cec_adap_ops cdns_mhdp_cec_adap_ops = { -+ .adap_enable = mhdp_cec_adap_enable, -+ .adap_log_addr = mhdp_cec_adap_log_addr, -+ .adap_transmit = mhdp_cec_adap_transmit, -+}; -+ -+int cdns_mhdp_register_cec_driver(struct cdns_mhdp_cec *cec) -+{ -+ int ret; -+ -+ cec->adap = cec_allocate_adapter(&cdns_mhdp_cec_adap_ops, cec, -+ CEC_NAME, -+ CEC_CAP_PHYS_ADDR | CEC_CAP_LOG_ADDRS | -+ CEC_CAP_TRANSMIT | CEC_CAP_PASSTHROUGH -+ | CEC_CAP_RC, CEC_MAX_LOG_ADDRS); -+ ret = PTR_ERR_OR_ZERO(cec->adap); -+ if (ret) -+ return ret; -+ ret = cec_register_adapter(cec->adap, cec->dev); -+ if (ret) { -+ cec_delete_adapter(cec->adap); -+ return ret; -+ } -+ -+ cec->cec_worker = kthread_create(mhdp_cec_poll_worker, cec, "cdns-mhdp-cec"); -+ if (IS_ERR(cec->cec_worker)) -+ dev_err(cec->dev, "failed create hdp cec thread\n"); -+ -+ wake_up_process(cec->cec_worker); -+ -+ dev_dbg(cec->dev, "CEC successfuly probed\n"); -+ return 0; -+} -+ -+int cdns_mhdp_unregister_cec_driver(struct cdns_mhdp_cec *cec) -+{ -+ if (cec->cec_worker) { -+ kthread_stop(cec->cec_worker); -+ cec->cec_worker = NULL; -+ } -+ cec_unregister_adapter(cec->adap); -+ return 0; -+} -+ -+MODULE_AUTHOR("Sandor.Yu@NXP.com"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("NXP CDNS MHDP HDMI CEC driver"); -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c -new file mode 100644 -index 000000000..447e9f188 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c -@@ -0,0 +1,853 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd -+ * Author: Chris Zhong -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "cdns-mhdp.h" -+ -+#define CDNS_DP_SPDIF_CLK 200000000 -+#define FW_ALIVE_TIMEOUT_US 1000000 -+u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset) -+{ -+ u32 val; -+ -+ mutex_lock(&mhdp->iolock); -+ -+ if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { -+ /* Remap address to low 4K SAPB bus */ -+ writel(offset >> 12, mhdp->regs_sec + 0xc); -+ val = readl((offset & 0xfff) + mhdp->regs_base); -+ } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { -+ /* Remap address to low 4K memory */ -+ writel(offset >> 12, mhdp->regs_sec + 8); -+ val = readl((offset & 0xfff) + mhdp->regs_base); -+ } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) -+ val = readl(mhdp->regs_sec + offset); -+ else -+ val = readl(mhdp->regs_base + offset); -+ -+ mutex_unlock(&mhdp->iolock); -+ -+ return val; -+} -+EXPORT_SYMBOL(cdns_mhdp_bus_read); -+ -+void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset) -+{ -+ mutex_lock(&mhdp->iolock); -+ -+ if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { -+ /* Remap address to low 4K SAPB bus */ -+ writel(offset >> 12, mhdp->regs_sec + 0xc); -+ writel(val, (offset & 0xfff) + mhdp->regs_base); -+ } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { -+ /* Remap address to low 4K memory */ -+ writel(offset >> 12, mhdp->regs_sec + 8); -+ writel(val, (offset & 0xfff) + mhdp->regs_base); -+ } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) -+ writel(val, mhdp->regs_sec + offset); -+ else -+ writel(val, mhdp->regs_base + offset); -+ -+ mutex_unlock(&mhdp->iolock); -+} -+EXPORT_SYMBOL(cdns_mhdp_bus_write); -+ -+void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk) -+{ -+ cdns_mhdp_bus_write(clk / 1000000, mhdp, SW_CLK_H); -+} -+EXPORT_SYMBOL(cdns_mhdp_set_fw_clk); -+ -+void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp) -+{ -+ u32 val; -+ -+ val = DPTX_FRMR_DATA_CLK_RSTN_EN | -+ DPTX_FRMR_DATA_CLK_EN | -+ DPTX_PHY_DATA_RSTN_EN | -+ DPTX_PHY_DATA_CLK_EN | -+ DPTX_PHY_CHAR_RSTN_EN | -+ DPTX_PHY_CHAR_CLK_EN | -+ SOURCE_AUX_SYS_CLK_RSTN_EN | -+ SOURCE_AUX_SYS_CLK_EN | -+ DPTX_SYS_CLK_RSTN_EN | -+ DPTX_SYS_CLK_EN | -+ CFG_DPTX_VIF_CLK_RSTN_EN | -+ CFG_DPTX_VIF_CLK_EN; -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_DPTX_CAR); -+ -+ val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_PHY_CAR); -+ -+ val = SOURCE_PKT_SYS_RSTN_EN | -+ SOURCE_PKT_SYS_CLK_EN | -+ SOURCE_PKT_DATA_RSTN_EN | -+ SOURCE_PKT_DATA_CLK_EN; -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_PKT_CAR); -+ -+ val = SPDIF_CDR_CLK_RSTN_EN | -+ SPDIF_CDR_CLK_EN | -+ SOURCE_AIF_SYS_RSTN_EN | -+ SOURCE_AIF_SYS_CLK_EN | -+ SOURCE_AIF_CLK_RSTN_EN | -+ SOURCE_AIF_CLK_EN; -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_AIF_CAR); -+ -+ val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | -+ SOURCE_CIPHER_SYS_CLK_EN | -+ SOURCE_CIPHER_CHAR_CLK_RSTN_EN | -+ SOURCE_CIPHER_CHAR_CLK_EN; -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_CIPHER_CAR); -+ -+ val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | -+ SOURCE_CRYPTO_SYS_CLK_EN; -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_CRYPTO_CAR); -+ -+ /* enable Mailbox and PIF interrupt */ -+ cdns_mhdp_bus_write(0, mhdp, APB_INT_MASK); -+} -+EXPORT_SYMBOL(cdns_mhdp_clock_reset); -+ -+bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp) -+{ -+ u32 alive, newalive; -+ u8 retries_left = 50; -+ -+ alive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); -+ -+ while (retries_left--) { -+ msleep(1); -+ -+ newalive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); -+ if (alive == newalive) -+ continue; -+ return true; -+ } -+ return false; -+} -+EXPORT_SYMBOL(cdns_mhdp_check_alive); -+ -+int mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) -+{ -+ int val, ret; -+ -+ ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_EMPTY_ADDR, -+ val, !val, MAILBOX_RETRY_US, -+ MAILBOX_TIMEOUT_US); -+ if (ret < 0) -+ return ret; -+ -+ return cdns_mhdp_bus_read(mhdp, MAILBOX0_RD_DATA) & 0xff; -+} -+ -+static int mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val) -+{ -+ int ret, full; -+ -+ ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_FULL_ADDR, -+ full, !full, MAILBOX_RETRY_US, -+ MAILBOX_TIMEOUT_US); -+ if (ret < 0) -+ return ret; -+ -+ cdns_mhdp_bus_write(val, mhdp, MAILBOX0_WR_DATA); -+ -+ return 0; -+} -+ -+int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, -+ u8 module_id, u8 opcode, -+ u16 req_size) -+{ -+ u32 mbox_size, i; -+ u8 header[4]; -+ int ret; -+ -+ /* read the header of the message */ -+ for (i = 0; i < 4; i++) { -+ ret = mhdp_mailbox_read(mhdp); -+ if (ret < 0) -+ return ret; -+ -+ header[i] = ret; -+ } -+ -+ mbox_size = get_unaligned_be16(header + 2); -+ -+ if (opcode != header[0] || module_id != header[1] || -+ req_size != mbox_size) { -+ DRM_DEV_ERROR(mhdp->dev, -+ "Hmmm spurious mailbox data maybe, cleaning out...%d:%d:%d vs %d:%d:%d\n", -+ module_id, opcode, req_size, header[1], -+ header[0], mbox_size); -+ /* -+ * If the message in mailbox is not what we want, we need to -+ * clear the mailbox by reading its contents. -+ */ -+ for (i = 0; i < mbox_size; i++) -+ if (mhdp_mailbox_read(mhdp) < 0) -+ break; -+ -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(cdns_mhdp_mailbox_validate_receive); -+ -+int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, -+ u8 *buff, u16 buff_size) -+{ -+ u32 i; -+ int ret; -+ -+ for (i = 0; i < buff_size; i++) { -+ ret = mhdp_mailbox_read(mhdp); -+ if (ret < 0) -+ return ret; -+ -+ buff[i] = ret; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(cdns_mhdp_mailbox_read_receive); -+ -+int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, -+ u8 opcode, u16 size, u8 *message) -+{ -+ u8 header[4]; -+ int ret, i; -+ -+ header[0] = opcode; -+ header[1] = module_id; -+ put_unaligned_be16(size, header + 2); -+ -+ for (i = 0; i < 4; i++) { -+ ret = mhdp_mailbox_write(mhdp, header[i]); -+ if (ret) -+ return ret; -+ } -+ -+ for (i = 0; i < size; i++) { -+ ret = mhdp_mailbox_write(mhdp, message[i]); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(cdns_mhdp_mailbox_send); -+ -+int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) -+{ -+ u8 msg[4], resp[8]; -+ u32 val; -+ int ret; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ if (addr == 0) { -+ ret = -EINVAL; -+ goto err_reg_read; -+ } -+ -+ put_unaligned_be32(addr, msg); -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, -+ GENERAL_READ_REGISTER, -+ sizeof(msg), msg); -+ if (ret) -+ goto err_reg_read; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, -+ GENERAL_READ_REGISTER, -+ sizeof(resp)); -+ if (ret) -+ goto err_reg_read; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, resp, sizeof(resp)); -+ if (ret) -+ goto err_reg_read; -+ -+ /* Returned address value should be the same as requested */ -+ if (memcmp(msg, resp, sizeof(msg))) { -+ ret = -EINVAL; -+ goto err_reg_read; -+ } -+ -+ val = get_unaligned_be32(resp + 4); -+ -+ mutex_unlock(&mhdp->api_lock); -+ return val; -+err_reg_read: -+ mutex_unlock(&mhdp->api_lock); -+ DRM_DEV_ERROR(mhdp->dev, "Failed to read register.\n"); -+ -+mutex_unlock(&mhdp->api_lock); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_reg_read); -+ -+int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) -+{ -+ int ret; -+ u8 msg[8]; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ put_unaligned_be32(addr, msg); -+ put_unaligned_be32(val, msg + 4); -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, -+ GENERAL_WRITE_REGISTER, -+ sizeof(msg), msg); -+ mutex_unlock(&mhdp->api_lock); -+return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_reg_write); -+ -+int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, -+ u8 start_bit, u8 bits_no, u32 val) -+{ -+ int ret; -+ u8 field[8]; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ put_unaligned_be16(addr, field); -+ field[2] = start_bit; -+ field[3] = bits_no; -+ put_unaligned_be32(val, field + 4); -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_WRITE_FIELD, sizeof(field), field); -+ mutex_unlock(&mhdp->api_lock); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_reg_write_bit); -+ -+int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, -+ u32 i_size, const u32 *d_mem, u32 d_size) -+{ -+ u32 reg; -+ int i, ret; -+ -+ /* reset ucpu before load firmware*/ -+ cdns_mhdp_bus_write(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET, -+ mhdp, APB_CTRL); -+ -+ for (i = 0; i < i_size; i += 4) -+ cdns_mhdp_bus_write(*i_mem++, mhdp, ADDR_IMEM + i); -+ -+ for (i = 0; i < d_size; i += 4) -+ cdns_mhdp_bus_write(*d_mem++, mhdp, ADDR_DMEM + i); -+ -+ /* un-reset ucpu */ -+ cdns_mhdp_bus_write(0, mhdp, APB_CTRL); -+ -+ /* check the keep alive register to make sure fw working */ -+ ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, KEEP_ALIVE, -+ reg, reg, 2000, FW_ALIVE_TIMEOUT_US); -+ if (ret < 0) { -+ DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n", -+ reg); -+ return -EINVAL; -+ } -+ -+ reg = cdns_mhdp_bus_read(mhdp, VER_L) & 0xff; -+ mhdp->fw_version = reg; -+ reg = cdns_mhdp_bus_read(mhdp, VER_H) & 0xff; -+ mhdp->fw_version |= reg << 8; -+ reg = cdns_mhdp_bus_read(mhdp, VER_LIB_L_ADDR) & 0xff; -+ mhdp->fw_version |= reg << 16; -+ reg = cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) & 0xff; -+ mhdp->fw_version |= reg << 24; -+ -+ DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version); -+ -+ return 0; -+} -+EXPORT_SYMBOL(cdns_mhdp_load_firmware); -+ -+int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable) -+{ -+ u8 msg[5]; -+ int ret, i; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ msg[0] = GENERAL_MAIN_CONTROL; -+ msg[1] = MB_MODULE_ID_GENERAL; -+ msg[2] = 0; -+ msg[3] = 1; -+ msg[4] = enable ? FW_ACTIVE : FW_STANDBY; -+ -+ for (i = 0; i < sizeof(msg); i++) { -+ ret = mhdp_mailbox_write(mhdp, msg[i]); -+ if (ret) -+ goto err_set_firmware_active; -+ } -+ -+ /* read the firmware state */ -+ for (i = 0; i < sizeof(msg); i++) { -+ ret = mhdp_mailbox_read(mhdp); -+ if (ret < 0) -+ goto err_set_firmware_active; -+ -+ msg[i] = ret; -+ } -+ -+ ret = 0; -+ -+err_set_firmware_active: -+ if (ret < 0) -+ DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n"); -+ mutex_unlock(&mhdp->api_lock); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_set_firmware_active); -+ -+int cdns_mhdp_apb_conf(struct cdns_mhdp_device *mhdp, u8 sel) -+{ -+ u8 status; -+ int ret; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_BUS_SETTINGS, -+ sizeof(sel), &sel); -+ if (ret) -+ goto err_apb_conf; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, -+ GENERAL_BUS_SETTINGS, sizeof(status)); -+ if (ret) -+ goto err_apb_conf; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); -+ if (ret) -+ goto err_apb_conf; -+ -+ mutex_unlock(&mhdp->api_lock); -+ -+ return status; -+ -+err_apb_conf: -+ DRM_ERROR("apb conf failed: %d\n", ret); -+mutex_unlock(&mhdp->api_lock); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_apb_conf); -+ -+int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp) -+{ -+ u8 msg[8]; -+ int ret, lane; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate); -+ msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN; -+ if (mhdp->dp.link_training_type == DP_TX_FULL_LINK_TRAINING) { -+ msg[2] = (VOLTAGE_LEVEL_3 & 0x3) | (mhdp->dp.force_vswing & 0x1) << 4; -+ msg[3] = (PRE_EMPHASIS_LEVEL_2 & 0x3) | (mhdp->dp.force_preemphasis & 0x1) << 4; -+ } else { -+ msg[2] = 0; -+ msg[3] = 0; -+ for (lane = 0; lane < mhdp->dp.num_lanes; lane++) { -+ msg[2] |= (mhdp->dp.vswing[lane] & 0x3) << (2 * lane); -+ msg[3] |= (mhdp->dp.preemphasis[lane] & 0x3) << (2 * lane); -+ } -+ } -+ msg[4] = PTS1 | PTS2 | PTS3 | PTS4; -+ msg[5] = mhdp->dp.link_training_type; -+ msg[6] = mhdp->lane_mapping; -+ msg[7] = ENHANCED; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_SET_HOST_CAPABILITIES, -+ sizeof(msg), msg); -+ if (ret) -+ goto err_set_host_cap; -+ -+/* TODO Sandor */ -+// ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL, -+// AUX_HOST_INVERT); -+ -+err_set_host_cap: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret); -+ mutex_unlock(&mhdp->api_lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_set_host_cap); -+ -+int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp) -+{ -+ u8 msg[5]; -+ int ret; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ memset(msg, 0, sizeof(msg)); -+ -+ msg[0] = MHDP_EVENT_ENABLE_HPD | MHDP_EVENT_ENABLE_TRAINING; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_ENABLE_EVENT, sizeof(msg), msg); -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret); -+ -+ mutex_unlock(&mhdp->api_lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_event_config); -+ -+u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp) -+{ -+ return cdns_mhdp_bus_read(mhdp, SW_EVENTS0); -+} -+EXPORT_SYMBOL(cdns_mhdp_get_event); -+ -+int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp) -+{ -+ u8 status; -+ int ret; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, -+ 0, NULL); -+ if (ret) -+ goto err_get_hpd; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, -+ GENERAL_GET_HPD_STATE, sizeof(status)); -+ if (ret) -+ goto err_get_hpd; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); -+ if (ret) -+ goto err_get_hpd; -+ -+ mutex_unlock(&mhdp->api_lock); -+ -+ return status; -+ -+err_get_hpd: -+ DRM_ERROR("read hpd failed: %d\n", ret); -+ mutex_unlock(&mhdp->api_lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_read_hpd); -+ -+int cdns_mhdp_get_edid_block(void *data, u8 *edid, -+ unsigned int block, size_t length) -+{ -+ struct cdns_mhdp_device *mhdp = data; -+ u8 msg[2], reg[2], i; -+ int ret; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ for (i = 0; i < 4; i++) { -+ msg[0] = block / 2; -+ msg[1] = block % 2; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_GET_EDID, sizeof(msg), msg); -+ if (ret) -+ continue; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, -+ MB_MODULE_ID_DP_TX, -+ DPTX_GET_EDID, -+ sizeof(reg) + length); -+ if (ret) -+ continue; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ continue; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); -+ if (ret) -+ continue; -+ -+ if (reg[0] == length && reg[1] == block / 2) -+ break; -+ } -+ -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n", -+ block, ret); -+ -+ mutex_unlock(&mhdp->api_lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_get_edid_block); -+ -+int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active) -+{ -+ u8 msg; -+ int ret; -+ -+ mutex_lock(&mhdp->api_lock); -+ -+ msg = !!active; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_SET_VIDEO, sizeof(msg), &msg); -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret); -+ -+ mutex_unlock(&mhdp->api_lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_set_video_status); -+ -+static int mhdp_get_msa_misc(struct video_info *video, -+ struct drm_display_mode *mode) -+{ -+ u32 msa_misc; -+ u8 val[2] = {0}; -+ -+ switch (video->color_fmt) { -+ case PXL_RGB: -+ case Y_ONLY: -+ val[0] = 0; -+ break; -+ /* set YUV default color space conversion to BT601 */ -+ case YCBCR_4_4_4: -+ val[0] = 6 + BT_601 * 8; -+ break; -+ case YCBCR_4_2_2: -+ val[0] = 5 + BT_601 * 8; -+ break; -+ case YCBCR_4_2_0: -+ val[0] = 5; -+ break; -+ } -+ -+ switch (video->color_depth) { -+ case 6: -+ val[1] = 0; -+ break; -+ case 8: -+ val[1] = 1; -+ break; -+ case 10: -+ val[1] = 2; -+ break; -+ case 12: -+ val[1] = 3; -+ break; -+ case 16: -+ val[1] = 4; -+ break; -+ } -+ -+ msa_misc = 2 * val[0] + 32 * val[1] + -+ ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); -+ -+ return msa_misc; -+} -+ -+int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp) -+{ -+ struct video_info *video = &mhdp->video_info; -+ struct drm_display_mode *mode = &mhdp->mode; -+ u64 symbol; -+ u32 val, link_rate, rem; -+ u8 bit_per_pix, tu_size_reg = TU_SIZE; -+ int ret; -+ -+ bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? -+ (video->color_depth * 2) : (video->color_depth * 3); -+ -+ link_rate = mhdp->dp.rate / 1000; -+ -+ ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); -+ if (ret) -+ goto err_config_video; -+ -+ ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0); -+ if (ret) -+ goto err_config_video; -+ -+ /* -+ * get a best tu_size and valid symbol: -+ * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 -+ * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) -+ * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set -+ * TU += 2 and repeat 2nd step. -+ */ -+ do { -+ tu_size_reg += 2; -+ symbol = (u64) tu_size_reg * mode->clock * bit_per_pix; -+ do_div(symbol, mhdp->dp.num_lanes * link_rate * 8); -+ rem = do_div(symbol, 1000); -+ if (tu_size_reg > 64) { -+ ret = -EINVAL; -+ DRM_DEV_ERROR(mhdp->dev, -+ "tu error, clk:%d, lanes:%d, rate:%d\n", -+ mode->clock, mhdp->dp.num_lanes, -+ link_rate); -+ goto err_config_video; -+ } -+ } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || -+ (rem > 850) || (rem < 100)); -+ -+ val = symbol + (tu_size_reg << 8); -+ val |= TU_CNT_RST_EN; -+ ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val); -+ if (ret) -+ goto err_config_video; -+ -+ /* set the FIFO Buffer size */ -+ val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; -+ val /= (mhdp->dp.num_lanes * link_rate); -+ val = div_u64(8 * (symbol + 1), bit_per_pix) - val; -+ val += 2; -+ ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val); -+ -+ switch (video->color_depth) { -+ case 6: -+ val = BCS_6; -+ break; -+ case 8: -+ val = BCS_8; -+ break; -+ case 10: -+ val = BCS_10; -+ break; -+ case 12: -+ val = BCS_12; -+ break; -+ case 16: -+ val = BCS_16; -+ break; -+ } -+ -+ val += video->color_fmt << 8; -+ ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; -+ val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; -+ ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = (mode->hsync_start - mode->hdisplay) << 16; -+ val |= mode->htotal - mode->hsync_end; -+ ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->hdisplay * bit_per_pix / 8; -+ ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); -+ ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->hsync_end - mode->hsync_start; -+ val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); -+ ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->vtotal; -+ val |= (mode->vtotal - mode->vsync_start) << 16; -+ ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->vsync_end - mode->vsync_start; -+ val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); -+ ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mhdp_get_msa_misc(video, mode); -+ ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val); -+ if (ret) -+ goto err_config_video; -+ -+ ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->hsync_end - mode->hsync_start; -+ val |= mode->hdisplay << 16; -+ ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->vdisplay; -+ val |= (mode->vtotal - mode->vsync_start) << 16; -+ ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val); -+ if (ret) -+ goto err_config_video; -+ -+ val = mode->vtotal; -+ ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val); -+ if (ret) -+ goto err_config_video; -+ -+ ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0); -+ -+err_config_video: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_config_video); -+ -+int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) -+{ -+ return cdns_mhdp_reg_write(mhdp, ADDR_PHY_AFE + (addr << 2), val); -+} -+EXPORT_SYMBOL(cdns_phy_reg_write); -+ -+u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) -+{ -+ return cdns_mhdp_reg_read(mhdp, ADDR_PHY_AFE + (addr << 2)); -+} -+EXPORT_SYMBOL(cdns_phy_reg_read); -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c -new file mode 100644 -index 000000000..299e533d6 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c -@@ -0,0 +1,278 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+ -+#include -+#include -+#include -+#include -+ -+#define LINK_TRAINING_TIMEOUT_MS 500 -+#define LINK_TRAINING_RETRY_MS 20 -+ -+int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, -+ u32 addr, u8 *data, u16 len) -+{ -+ u8 msg[5], reg[5]; -+ int ret; -+ -+ put_unaligned_be16(len, msg); -+ put_unaligned_be24(addr, msg + 2); -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_READ_DPCD, sizeof(msg), msg); -+ if (ret) -+ goto err_dpcd_read; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_READ_DPCD, -+ sizeof(reg) + len); -+ if (ret) -+ goto err_dpcd_read; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ goto err_dpcd_read; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); -+ -+err_dpcd_read: -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_dpcd_read); -+ -+int cdns_mhdp_i2c_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data, -+ u16 len, u8 mot, u16 *respLength) -+{ -+ u8 msg[5], reg[3]; -+ int ret; -+ -+ put_unaligned_be16(len, msg); -+ msg[2] = addr; -+ msg[3] = mot; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_I2C_READ, sizeof(msg), msg); -+ if (ret) -+ goto err_i2c_read; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_I2C_READ, -+ sizeof(reg) + len); -+ if (ret) -+ goto err_i2c_read; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ goto err_i2c_read; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); -+ *respLength = (reg[0] << 8u) + reg[1]; -+ -+err_i2c_read: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "i2c read failed: %d\n", ret); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_i2c_read); -+ -+int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) -+{ -+ u8 msg[6], reg[5]; -+ int ret; -+ -+ put_unaligned_be16(1, msg); -+ put_unaligned_be24(addr, msg + 2); -+ msg[5] = value; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_WRITE_DPCD, sizeof(msg), msg); -+ if (ret) -+ goto err_dpcd_write; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_WRITE_DPCD, sizeof(reg)); -+ if (ret) -+ goto err_dpcd_write; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ goto err_dpcd_write; -+ -+ if (addr != get_unaligned_be24(reg + 2)) -+ ret = -EINVAL; -+ -+err_dpcd_write: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_dpcd_write); -+ -+int cdns_mhdp_i2c_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 *value, -+ u8 mot, u16 len, u16 *respLength) -+{ -+ u8 msg[4+DP_AUX_MAX_PAYLOAD_BYTES], reg[3]; -+ int ret; -+ -+ put_unaligned_be16(len, msg); -+ msg[2] = addr; -+ msg[3] = mot; -+ memcpy(&msg[4], value, len); -+ -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_I2C_WRITE, sizeof(msg), msg); -+ if (ret) -+ goto err_i2c_write; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_I2C_WRITE, sizeof(reg)); -+ if (ret) -+ goto err_i2c_write; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ goto err_i2c_write; -+ -+ if (addr != reg[2]) -+ ret = -EINVAL; -+ -+ *respLength = (reg[0]<<8u) + reg[1]; -+ -+err_i2c_write: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "i2c write failed: %d\n", ret); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_i2c_write); -+ -+ -+int cdns_mhdp_get_last_i2c_status(struct cdns_mhdp_device *mhdp, u8 *resp) -+{ -+ u8 status[1]; -+ int ret; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_GET_LAST_I2C_STATUS, 0, NULL); -+ if (ret) -+ goto err_get_i2c_status; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_GET_LAST_I2C_STATUS, -+ sizeof(status)); -+ if (ret) -+ goto err_get_i2c_status; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); -+ if (ret) -+ goto err_get_i2c_status; -+ -+ *resp = status[0]; -+ -+err_get_i2c_status: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "get i2c status failed: %d\n", -+ ret); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_get_last_i2c_status); -+ -+static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp) -+{ -+ unsigned long timeout; -+ u8 msg, event[2]; -+ int ret; -+ -+ msg = LINK_TRAINING_RUN; -+ -+ /* start training */ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_TRAINING_CONTROL, sizeof(msg), &msg); -+ if (ret) -+ goto err_training_start; -+ -+ timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS); -+ while (time_before(jiffies, timeout)) { -+ msleep(LINK_TRAINING_RETRY_MS); -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_READ_EVENT, 0, NULL); -+ if (ret) -+ goto err_training_start; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, -+ MB_MODULE_ID_DP_TX, -+ DPTX_READ_EVENT, -+ sizeof(event)); -+ if (ret) -+ goto err_training_start; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, event, -+ sizeof(event)); -+ if (ret) -+ goto err_training_start; -+ -+ if (event[1] & CLK_RECOVERY_FAILED) -+ DRM_DEV_ERROR(mhdp->dev, "clock recovery failed\n"); -+ else if (event[1] & EQ_PHASE_FINISHED) -+ return 0; -+ } -+ -+ ret = -ETIMEDOUT; -+ -+err_training_start: -+ DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret); -+ return ret; -+} -+ -+static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp) -+{ -+ u8 status[13]; -+ int ret; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_READ_LINK_STAT, 0, NULL); -+ if (ret) -+ goto err_get_training_status; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, -+ DPTX_READ_LINK_STAT, -+ sizeof(status)); -+ if (ret) -+ goto err_get_training_status; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); -+ if (ret) -+ goto err_get_training_status; -+ -+ mhdp->dp.rate = drm_dp_bw_code_to_link_rate(status[0]); -+ mhdp->dp.num_lanes = status[1]; -+ -+err_get_training_status: -+ if (ret) -+ DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n", -+ ret); -+ return ret; -+} -+ -+int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp) -+{ -+ int ret; -+ -+ ret = cdns_mhdp_training_start(mhdp); -+ if (ret) { -+ DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = cdns_mhdp_get_training_status(mhdp); -+ if (ret) { -+ DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n", -+ ret); -+ return ret; -+ } -+ -+ DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.rate, -+ mhdp->dp.num_lanes); -+ return ret; -+} -+EXPORT_SYMBOL(cdns_mhdp_train_link); -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c -new file mode 100644 -index 000000000..47c853781 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c -@@ -0,0 +1,332 @@ -+/* -+ * Copyright 2019-2021 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, -+ u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type) -+{ -+ u32 *packet32, len32; -+ u32 val, i; -+ -+ /* invalidate entry */ -+ val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id); -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); -+ cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); -+ -+ /* flush fifo 1 */ -+ cdns_mhdp_bus_write(F_FIFO1_FLUSH(1), mhdp, SOURCE_PIF_FIFO1_FLUSH); -+ -+ /* write packet into memory */ -+ packet32 = (u32 *)packet; -+ len32 = packet_len / 4; -+ for (i = 0; i < len32; i++) -+ cdns_mhdp_bus_write(F_DATA_WR(packet32[i]), mhdp, SOURCE_PIF_DATA_WR); -+ -+ /* write entry id */ -+ cdns_mhdp_bus_write(F_WR_ADDR(entry_id), mhdp, SOURCE_PIF_WR_ADDR); -+ -+ /* write request */ -+ cdns_mhdp_bus_write(F_HOST_WR(1), mhdp, SOURCE_PIF_WR_REQ); -+ -+ /* update entry */ -+ val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) | -+ F_PACKET_TYPE(packet_type) | F_PKT_ALLOC_ADDRESS(entry_id); -+ cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); -+ -+ cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); -+} -+ -+int cdns_hdmi_get_edid_block(void *data, u8 *edid, -+ u32 block, size_t length) -+{ -+ struct cdns_mhdp_device *mhdp = data; -+ u8 msg[2], reg[5], i; -+ int ret; -+ -+ for (i = 0; i < 4; i++) { -+ msg[0] = block / 2; -+ msg[1] = block % 2; -+ -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, -+ sizeof(msg), msg); -+ if (ret) -+ continue; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, -+ HDMI_TX_EDID, sizeof(reg) + length); -+ if (ret) -+ continue; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ continue; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); -+ if (ret) -+ continue; -+ -+ if ((reg[3] << 8 | reg[4]) == length) -+ break; -+ } -+ -+ if (ret) -+ DRM_ERROR("get block[%d] edid failed: %d\n", block, ret); -+ return ret; -+} -+ -+int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data) -+{ -+ u8 msg[4], reg[6]; -+ int ret; -+ -+ msg[0] = 0x54; -+ msg[1] = addr; -+ msg[2] = 0; -+ msg[3] = 1; -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, -+ sizeof(msg), msg); -+ if (ret) -+ goto err_scdc_read; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, -+ HDMI_TX_READ, sizeof(reg)); -+ if (ret) -+ goto err_scdc_read; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ goto err_scdc_read; -+ -+ *data = reg[5]; -+ -+err_scdc_read: -+ if (ret) -+ DRM_ERROR("scdc read failed: %d\n", ret); -+ return ret; -+} -+ -+int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value) -+{ -+ u8 msg[5], reg[5]; -+ int ret; -+ -+ msg[0] = 0x54; -+ msg[1] = addr; -+ msg[2] = 0; -+ msg[3] = 1; -+ msg[4] = value; -+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, -+ sizeof(msg), msg); -+ if (ret) -+ goto err_scdc_write; -+ -+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, -+ HDMI_TX_WRITE, sizeof(reg)); -+ if (ret) -+ goto err_scdc_write; -+ -+ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); -+ if (ret) -+ goto err_scdc_write; -+ -+ if (reg[0] != 0) -+ ret = -EINVAL; -+ -+err_scdc_write: -+ if (ret) -+ DRM_ERROR("scdc write failed: %d\n", ret); -+ return ret; -+} -+ -+int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, -+ int protocol, -+ u32 char_rate) -+{ -+ u32 reg0; -+ u32 reg1; -+ u32 val; -+ int ret; -+ -+ /* Set PHY to HDMI data */ -+ ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1)); -+ if (ret < 0) -+ return ret; -+ -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD, -+ F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0)); -+ if (ret < 0) -+ return ret; -+ -+ /* open CARS */ -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3); -+ if (ret < 0) -+ return ret; -+ -+ reg0 = reg1 = 0x7c1f; -+ if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) { -+ reg0 = 0; -+ reg1 = 0xFFFFF; -+ } -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0); -+ if (ret < 0) -+ return ret; -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1); -+ if (ret < 0) -+ return ret; -+ -+ /* set hdmi mode and preemble mode data enable */ -+ val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) | F_DATA_EN(1) | -+ F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF) | F_CLEAR_AVMUTE(1); -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); -+ -+ return ret; -+} -+ -+int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, -+ struct drm_display_mode *mode, -+ struct video_info *video_info) -+{ -+ int ret; -+ u32 val; -+ u32 vsync_lines = mode->vsync_end - mode->vsync_start; -+ u32 eof_lines = mode->vsync_start - mode->vdisplay; -+ u32 sof_lines = mode->vtotal - mode->vsync_end; -+ u32 hblank = mode->htotal - mode->hdisplay; -+ u32 hactive = mode->hdisplay; -+ u32 vblank = mode->vtotal - mode->vdisplay; -+ u32 vactive = mode->vdisplay; -+ u32 hfront = mode->hsync_start - mode->hdisplay; -+ u32 hback = mode->htotal - mode->hsync_end; -+ u32 vfront = eof_lines; -+ u32 hsync = hblank - hfront - hback; -+ u32 vsync = vsync_lines; -+ u32 vback = sof_lines; -+ u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) + -+ ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2); -+ -+ ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive << 16) + hblank); -+ if (ret < 0) -+ return ret; -+ -+ ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive << 16) + vblank); -+ if (ret < 0) -+ return ret; -+ -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront); -+ if (ret < 0) -+ return ret; -+ -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync); -+ if (ret < 0) -+ return ret; -+ -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback); -+ if (ret < 0) -+ return ret; -+ -+ ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity); -+ if (ret < 0) -+ return ret; -+ -+ /* Reset Data Enable */ -+ val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); -+ val &= ~F_DATA_EN(1); -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); -+ if (ret < 0) -+ return ret; -+ -+ /* Set bpc */ -+ val &= ~F_VIF_DATA_WIDTH(3); -+ switch (video_info->color_depth) { -+ case 10: -+ val |= F_VIF_DATA_WIDTH(1); -+ break; -+ case 12: -+ val |= F_VIF_DATA_WIDTH(2); -+ break; -+ case 16: -+ val |= F_VIF_DATA_WIDTH(3); -+ break; -+ case 8: -+ default: -+ val |= F_VIF_DATA_WIDTH(0); -+ break; -+ } -+ -+ /* select color encoding */ -+ val &= ~F_HDMI_ENCODING(3); -+ switch (video_info->color_fmt) { -+ case YCBCR_4_4_4: -+ val |= F_HDMI_ENCODING(2); -+ break; -+ case YCBCR_4_2_2: -+ val |= F_HDMI_ENCODING(1); -+ break; -+ case YCBCR_4_2_0: -+ val |= F_HDMI_ENCODING(3); -+ break; -+ case PXL_RGB: -+ default: -+ val |= F_HDMI_ENCODING(0); -+ break; -+ } -+ -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); -+ if (ret < 0) -+ return ret; -+ -+ /* set data enable */ -+ val |= F_DATA_EN(1); -+ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); -+ -+ return ret; -+} -+ -+int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp) -+{ -+ u32 val; -+ -+ val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); -+ val &= ~F_GCP_EN(1); -+ -+ return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); -+} -+ -+int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp) -+{ -+ u32 val; -+ -+ val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); -+ val |= F_GCP_EN(1); -+ -+ return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); -+} -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h -new file mode 100644 -index 000000000..8ad99eb8f ---- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h -@@ -0,0 +1,232 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence MHDP DP MST bridge driver. -+ * -+ * Copyright: 2018 Cadence Design Systems, Inc. -+ * -+ * Author: Quentin Schulz -+ */ -+ -+ -+#ifndef CDNS_MHDP_H -+#define CDNS_MHDP_H -+ -+#include -+ -+#define CDNS_APB_CFG 0x00000 -+#define CDNS_APB_CTRL (CDNS_APB_CFG + 0x00) -+#define CDNS_MAILBOX_FULL (CDNS_APB_CFG + 0x08) -+#define CDNS_MAILBOX_EMPTY (CDNS_APB_CFG + 0x0c) -+#define CDNS_MAILBOX_TX_DATA (CDNS_APB_CFG + 0x10) -+#define CDNS_MAILBOX_RX_DATA (CDNS_APB_CFG + 0x14) -+#define CDNS_KEEP_ALIVE (CDNS_APB_CFG + 0x18) -+#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0) -+ -+#define CDNS_MB_INT_MASK (CDNS_APB_CFG + 0x34) -+ -+#define CDNS_SW_CLK_L (CDNS_APB_CFG + 0x3c) -+#define CDNS_SW_CLK_H (CDNS_APB_CFG + 0x40) -+#define CDNS_SW_EVENT0 (CDNS_APB_CFG + 0x44) -+#define CDNS_DPTX_HPD BIT(0) -+ -+#define CDNS_SW_EVENT1 (CDNS_APB_CFG + 0x48) -+#define CDNS_SW_EVENT2 (CDNS_APB_CFG + 0x4c) -+#define CDNS_SW_EVENT3 (CDNS_APB_CFG + 0x50) -+ -+#define CDNS_APB_INT_MASK (CDNS_APB_CFG + 0x6C) -+#define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0) -+#define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1) -+ -+#define CDNS_DPTX_CAR (CDNS_APB_CFG + 0x904) -+#define CDNS_VIF_CLK_EN BIT(0) -+#define CDNS_VIF_CLK_RSTN BIT(1) -+ -+#define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + (s * 0x20)) -+#define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \ -+ 0x00) -+#define CDNS_IP_DTCT_WIN GENMASK(11, 0) -+#define CDNS_IP_DET_INTERLACE_FORMAT BIT(12) -+#define CDNS_IP_BYPASS_V_INTERFACE BIT(13) -+ -+#define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \ -+ 0x10) -+#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1) -+#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2) -+ -+#define CDNS_DPTX_PHY_CONFIG 0x02000 -+#define CDNS_PHY_TRAINING_EN BIT(0) -+#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1) -+#define CDNS_PHY_SCRAMBLER_BYPASS BIT(5) -+#define CDNS_PHY_ENCODER_BYPASS BIT(6) -+#define CDNS_PHY_SKEW_BYPASS BIT(7) -+#define CDNS_PHY_TRAINING_AUTO BIT(8) -+#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9) -+#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12) -+#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15) -+#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18) -+#define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \ -+ CDNS_PHY_LANE2_SKEW(2) | \ -+ CDNS_PHY_LANE3_SKEW(3)) -+#define CDNS_PHY_10BIT_EN BIT(21) -+ -+#define CDNS_DPTX_FRAMER 0x02200 -+#define CDNS_DP_FRAMER_GLOBAL_CONFIG (CDNS_DPTX_FRAMER + 0x00) -+#define CDNS_DP_NUM_LANES(x) (x - 1) -+#define CDNS_DP_MST_EN BIT(2) -+#define CDNS_DP_FRAMER_EN BIT(3) -+#define CDNS_DP_RATE_GOVERNOR_EN BIT(4) -+#define CDNS_DP_NO_VIDEO_MODE BIT(5) -+#define CDNS_DP_DISABLE_PHY_RST BIT(6) -+#define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7) -+ -+#define CDNS_DP_SW_RESET (CDNS_DPTX_FRAMER + 0x04) -+#define CDNS_DP_FRAMER_TU (CDNS_DPTX_FRAMER + 0x08) -+#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8) -+#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0)) -+#define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15) -+ -+#define CDNS_DPTX_STREAM(s) (0x03000 + s * 0x80) -+#define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00) -+#define CDNS_DP_MSAH0_H_TOTAL(x) (x) -+#define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16) -+ -+#define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04) -+#define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x) -+#define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15) -+#define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16) -+ -+#define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08) -+#define CDNS_DP_MSAV0_V_TOTAL(x) (x) -+#define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16) -+ -+#define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c) -+#define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x) -+#define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15) -+#define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16) -+ -+#define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10) -+#define CDNS_DP_STREAM_CONFIGs(s) (CDNS_DPTX_STREAM(s) + 0x14) -+#define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c) -+#define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8) -+ -+#define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30) -+#define CDNS_DP_H_HSYNC_WIDTH(x) (x) -+#define CDNS_DP_H_H_TOTAL(x) ((x) << 16) -+ -+#define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34) -+#define CDNS_DP_V0_VHEIGHT(x) (x) -+#define CDNS_DP_V0_VSTART(x) ((x) << 16) -+ -+#define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38) -+#define CDNS_DP_V1_VTOTAL(x) (x) -+#define CDNS_DP_V1_VTOTAL_EVEN BIT(16) -+ -+#define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c) -+#define CDNS_DP_FRAMER_6_BPC BIT(0) -+#define CDNS_DP_FRAMER_8_BPC BIT(1) -+#define CDNS_DP_FRAMER_10_BPC BIT(2) -+#define CDNS_DP_FRAMER_12_BPC BIT(3) -+#define CDNS_DP_FRAMER_16_BPC BIT(4) -+#define CDNS_DP_FRAMER_PXL_FORMAT 0x8 -+#define CDNS_DP_FRAMER_RGB BIT(0) -+#define CDNS_DP_FRAMER_YCBCR444 BIT(1) -+#define CDNS_DP_FRAMER_YCBCR422 BIT(2) -+#define CDNS_DP_FRAMER_YCBCR420 BIT(3) -+#define CDNS_DP_FRAMER_Y_ONLY BIT(4) -+ -+#define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x10) -+#define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0) -+#define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1) -+#define CDNS_DP_FRAMER_INTERLACE BIT(2) -+ -+#define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64) -+#define CDNS_DP_ACTIVE_LINE_THRESH(x) (x) -+ -+#define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68) -+#define CDNS_DP_VB_ID_INTERLACED BIT(2) -+#define CDNS_DP_VB_ID_COMPRESSED BIT(6) -+ -+#define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78) -+#define CDNS_DP_BACK_PORCH(x) (x) -+#define CDNS_DP_FRONT_PORCH(x) ((x) << 16) -+ -+#define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c) -+#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16 -+ -+#define CDNS_DP_MST_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14) -+#define CDNS_DP_MST_STRM_CFG_STREAM_EN BIT(0) -+#define CDNS_DP_MST_STRM_CFG_NO_VIDEO BIT(1) -+ -+#define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44) -+#define CDNS_DP_S_ALLOC_START_SLOT(x) (x) -+#define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8) -+ -+#define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48) -+#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x) -+#define CDNS_DP_RG_TARG_AV_SLOTS_X(x) (x << 4) -+#define CDNS_DP_RG_ENABLE BIT(10) -+ -+#define CDNS_DP_MTPH_CONTROL 0x2264 -+#define CDNS_DP_MTPH_ECF_EN BIT(0) -+#define CDNS_DP_MTPH_ACT_EN BIT(1) -+#define CDNS_DP_MTPH_LVP_EN BIT(2) -+ -+#define CDNS_DP_MTPH_STATUS 0x226C -+#define CDNS_DP_MTPH_ACT_STATUS BIT(0) -+ -+#define CDNS_DPTX_GLOBAL 0x02300 -+#define CDNS_DP_LANE_EN (CDNS_DPTX_GLOBAL + 0x00) -+#define CDNS_DP_LANE_EN_LANES(x) GENMASK(x - 1, 0) -+#define CDNS_DP_ENHNCD (CDNS_DPTX_GLOBAL + 0x04) -+ -+ -+#define to_mhdp_connector(x) container_of(x, struct cdns_mhdp_connector, base) -+#define to_mhdp_bridge(x) container_of(x, struct cdns_mhdp_bridge, base) -+#define mgr_to_mhdp(x) container_of(x, struct cdns_mhdp_device, mst_mgr) -+ -+#define CDNS_MHDP_MAX_STREAMS 4 -+ -+#define MAILBOX_RETRY_US 1000 -+#define MAILBOX_TIMEOUT_US 5000000 -+ -+#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \ -+({ \ -+ u64 __timeout_us = (timeout_us); \ -+ unsigned long __sleep_us = (sleep_us); \ -+ ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \ -+ might_sleep_if((__sleep_us) != 0); \ -+ for (;;) { \ -+ (val) = op(addr, offset); \ -+ if (cond) \ -+ break; \ -+ if (__timeout_us && \ -+ ktime_compare(ktime_get(), __timeout) > 0) { \ -+ (val) = op(addr, offset); \ -+ break; \ -+ } \ -+ if (__sleep_us) \ -+ usleep_range((__sleep_us >> 2) + 1, __sleep_us); \ -+ } \ -+ (cond) ? 0 : -ETIMEDOUT; \ -+}) -+ -+enum pixel_format { -+ PIXEL_FORMAT_RGB = 1, -+ PIXEL_FORMAT_YCBCR_444 = 2, -+ PIXEL_FORMAT_YCBCR_422 = 4, -+ PIXEL_FORMAT_YCBCR_420 = 8, -+ PIXEL_FORMAT_Y_ONLY = 16, -+}; -+ -+ -+int cdns_mhdp_mst_init(struct cdns_mhdp_device *mhdp); -+void cdns_mhdp_mst_deinit(struct cdns_mhdp_device *mhdp); -+bool cdns_mhdp_mst_probe(struct cdns_mhdp_device *mhdp); -+enum pixel_format cdns_mhdp_get_pxlfmt(u32 color_formats); -+u32 cdns_mhdp_get_bpp(u32 bpc, u32 color_formats); -+void cdns_mhdp_configure_video(struct drm_bridge *bridge); -+void cdns_mhdp_mst_enable(struct drm_bridge *bridge); -+void cdns_mhdp_mst_disable(struct drm_bridge *bridge); -+void cdns_mhdp_enable(struct drm_bridge *bridge); -+ -+#endif -diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c -index 6cac2e58c..6b1c5104b 100644 ---- a/drivers/gpu/drm/bridge/nwl-dsi.c -+++ b/drivers/gpu/drm/bridge/nwl-dsi.c -@@ -8,7 +8,9 @@ - - #include - #include -+#include - #include -+#include - #include - #include - #include -@@ -21,6 +23,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -28,6 +31,8 @@ - #include - #include - -+#include -+ - #include