diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
deleted file mode 100644
index f318db1..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_DAC_H
-#define STM32F4xx_HAL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-#if defined(DAC)
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
- HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
-
-} HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC handle Structure definition
- */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-typedef struct __DAC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-{
- DAC_TypeDef *Instance; /*!< Register base address */
-
- __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
-
- HAL_LockTypeDef Lock; /*!< DAC locking object */
-
- DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
-
- __IO uint32_t ErrorCode; /*!< DAC Error code */
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
-#if defined(DAC_CHANNEL2_SUPPORT)
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
-#endif /* DAC_CHANNEL2_SUPPORT */
-
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-} DAC_HandleTypeDef;
-
-/**
- * @brief DAC Configuration regular Channel structure definition
- */
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-
-} DAC_ChannelConfTypeDef;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL DAC Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
- HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
- HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
- HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
-#if defined(DAC_CHANNEL2_SUPPORT)
- HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
- HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
- HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
- HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
-#endif /* DAC_CHANNEL2_SUPPORT */
- HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
- HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
- HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
-} HAL_DAC_CallbackIDTypeDef;
-
-/**
- * @brief HAL DAC Callback pointer definition
- */
-typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_Error_Code DAC Error Code
- * @{
- */
-#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
-#endif /* DAC_CHANNEL2_SUPPORT */
-#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
-#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
- * @{
- */
-#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer DAC output buffer
- * @{
- */
-#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
- * @{
- */
-#define DAC_CHANNEL_1 0x00000000U
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_CHANNEL_2 0x00000010U
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignment DAC data alignment
- * @{
- */
-#define DAC_ALIGN_12B_R 0x00000000U
-#define DAC_ALIGN_12B_L 0x00000004U
-#define DAC_ALIGN_8B_R 0x00000008U
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition DAC flags definition
- * @{
- */
-#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_IT_definition DAC IT definition
- * @{
- */
-#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @brief Reset DAC handle state.
- * @param __HANDLE__ specifies the DAC handle.
- * @retval None
- */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/** @brief Enable the DAC channel.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __DAC_Channel__ specifies the DAC channel
- * @retval None
- */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
- ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Disable the DAC channel.
- * @param __HANDLE__ specifies the DAC handle
- * @param __DAC_Channel__ specifies the DAC channel.
- * @retval None
- */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
- ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Set DHR12R1 alignment.
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/** @brief Set DHR12R2 alignment.
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/** @brief Set DHR12RD alignment.
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt.
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt.
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief Check whether the specified DAC interrupt source is enabled or not.
- * @param __HANDLE__ DAC handle
- * @param __INTERRUPT__ DAC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
- & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the DAC flag to get.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the DAC's flag.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the DAC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
- * @{
- */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-#else
-#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-
-/**
- * @}
- */
-
-/* Include DAC HAL Extended module */
-#include "stm32f4xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/* DAC callback registering/unregistering */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
- pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Functions DAC Private Functions
- * @{
- */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F4xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
deleted file mode 100644
index cb4ba1e..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_dac_ex.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_DAC_EX_H
-#define STM32F4xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-#if defined(DAC)
-
-/** @addtogroup DACEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL State structures definition
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
- * @{
- */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
- * @{
- */
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-#endif
-HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-#endif
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DACEx_Private_Functions
- * @{
- */
-#if defined(DAC_CHANNEL2_SUPPORT)
-/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
-/* are called by HAL_DAC_Start_DMA */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F4xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
deleted file mode 100644
index f50ea7c..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
+++ /dev/null
@@ -1,688 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_ltdc.h
- * @author MCD Application Team
- * @brief Header file of LTDC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_LTDC_H
-#define STM32F4xx_HAL_LTDC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-#if defined (LTDC)
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup LTDC LTDC
- * @brief LTDC HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Types LTDC Exported Types
- * @{
- */
-#define MAX_LAYER 2U
-
-/**
- * @brief LTDC color structure definition
- */
-typedef struct
-{
- uint8_t Blue; /*!< Configures the blue value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Green; /*!< Configures the green value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Red; /*!< Configures the red value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Reserved; /*!< Reserved 0xFF */
-} LTDC_ColorTypeDef;
-
-/**
- * @brief LTDC Init structure definition
- */
-typedef struct
-{
- uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
- This parameter can be one value of @ref LTDC_HS_POLARITY */
-
- uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
- This parameter can be one value of @ref LTDC_VS_POLARITY */
-
- uint32_t DEPolarity; /*!< configures the data enable polarity.
- This parameter can be one of value of @ref LTDC_DE_POLARITY */
-
- uint32_t PCPolarity; /*!< configures the pixel clock polarity.
- This parameter can be one of value of @ref LTDC_PC_POLARITY */
-
- uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
- uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
- uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
- This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
-
- uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
- This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
-
- uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
-
- uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
-
- uint32_t TotalWidth; /*!< configures the total width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
-
- uint32_t TotalHeigh; /*!< configures the total height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
-
- LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
-} LTDC_InitTypeDef;
-
-/**
- * @brief LTDC Layer structure definition
- */
-typedef struct
-{
- uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
- uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
- uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
- uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
-
- uint32_t PixelFormat; /*!< Specifies the pixel format.
- This parameter can be one of value of @ref LTDC_Pixelformat */
-
- uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Alpha0; /*!< Configures the default alpha value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t BlendingFactor1; /*!< Select the blending factor 1.
- This parameter can be one of value of @ref LTDC_BlendingFactor1 */
-
- uint32_t BlendingFactor2; /*!< Select the blending factor 2.
- This parameter can be one of value of @ref LTDC_BlendingFactor2 */
-
- uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
-
- uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
-
- uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
- LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
-} LTDC_LayerCfgTypeDef;
-
-/**
- * @brief HAL LTDC State structures definition
- */
-typedef enum
-{
- HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
- HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
- HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
- HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
- HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
-} HAL_LTDC_StateTypeDef;
-
-/**
- * @brief LTDC handle Structure definition
- */
-#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-typedef struct __LTDC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
-{
- LTDC_TypeDef *Instance; /*!< LTDC Register base address */
-
- LTDC_InitTypeDef Init; /*!< LTDC parameters */
-
- LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
-
- HAL_LockTypeDef Lock; /*!< LTDC Lock */
-
- __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
-
- __IO uint32_t ErrorCode; /*!< LTDC Error code */
-
-#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
- void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
- void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
- void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
-
- void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
- void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
-
-#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
-
-
-} LTDC_HandleTypeDef;
-
-#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL LTDC Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
- HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
-
- HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
- HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
- HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
-
-} HAL_LTDC_CallbackIDTypeDef;
-
-/**
- * @brief HAL LTDC Callback pointer definition
- */
-typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */
-
-#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
- * @{
- */
-
-/** @defgroup LTDC_Error_Code LTDC Error Code
- * @{
- */
-#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
-#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
-#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
-#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
-#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
-#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Layer LTDC Layer
- * @{
- */
-#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
-#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
-/**
- * @}
- */
-
-/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
- * @{
- */
-#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
-#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
- * @{
- */
-#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
-#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
- * @{
- */
-#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
-#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
- * @{
- */
-#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
-#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_SYNC LTDC SYNC
- * @{
- */
-#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */
-#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
- * @{
- */
-#define LTDC_COLOR 0x000000FFU /*!< Color mask */
-/**
- * @}
- */
-
-/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
- * @{
- */
-#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
-#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
-/**
- * @}
- */
-
-/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
- * @{
- */
-#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
-#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
-/**
- * @}
- */
-
-/** @defgroup LTDC_Pixelformat LTDC Pixel format
- * @{
- */
-#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Alpha LTDC Alpha
- * @{
- */
-#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */
-/**
- * @}
- */
-
-/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
- * @{
- */
-#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */
-#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
-
-#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
-#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Interrupts LTDC Interrupts
- * @{
- */
-#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */
-#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */
-#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */
-#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Flags LTDC Flags
- * @{
- */
-#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */
-#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */
-#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */
-#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Reload_Type LTDC Reload Type
- * @{
- */
-#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
-#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
- * @{
- */
-
-/** @brief Reset LTDC handle state.
- * @param __HANDLE__ LTDC handle
- * @retval None
- */
-#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
-#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the LTDC.
- * @param __HANDLE__ LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
-
-/**
- * @brief Disable the LTDC.
- * @param __HANDLE__ LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
-
-/**
- * @brief Enable the LTDC Layer.
- * @param __HANDLE__ LTDC handle
- * @param __LAYER__ Specify the layer to be enabled.
- * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval None.
- */
-#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
-
-/**
- * @brief Disable the LTDC Layer.
- * @param __HANDLE__ LTDC handle
- * @param __LAYER__ Specify the layer to be disabled.
- * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval None.
- */
-#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
-
-/**
- * @brief Reload immediately all LTDC Layers.
- * @param __HANDLE__ LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
-
-/**
- * @brief Reload during vertical blanking period all LTDC Layers.
- * @param __HANDLE__ LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
-
-/* Interrupt & Flag management */
-/**
- * @brief Get the LTDC pending flags.
- * @param __HANDLE__ LTDC handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg LTDC_FLAG_LI: Line Interrupt flag
- * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
- * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
-
-/**
- * @brief Clears the LTDC pending flags.
- * @param __HANDLE__ LTDC handle
- * @param __FLAG__ Specify the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg LTDC_FLAG_LI: Line Interrupt flag
- * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
- * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
- * @retval None
- */
-#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
- * @brief Enables the specified LTDC interrupts.
- * @param __HANDLE__ LTDC handle
- * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg LTDC_IT_LI: Line Interrupt flag
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_IT_TE: Transfer Error interrupt flag
- * @arg LTDC_IT_RR: Register Reload Interrupt Flag
- * @retval None
- */
-#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified LTDC interrupts.
- * @param __HANDLE__ LTDC handle
- * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg LTDC_IT_LI: Line Interrupt flag
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_IT_TE: Transfer Error interrupt flag
- * @arg LTDC_IT_RR: Register Reload Interrupt Flag
- * @retval None
- */
-#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified LTDC interrupt has occurred or not.
- * @param __HANDLE__ LTDC handle
- * @param __INTERRUPT__ Specify the LTDC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg LTDC_IT_LI: Line Interrupt flag
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_IT_TE: Transfer Error interrupt flag
- * @arg LTDC_IT_RR: Register Reload Interrupt Flag
- * @retval The state of INTERRUPT (SET or RESET).
- */
-#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
-/**
- * @}
- */
-
-/* Include LTDC HAL Extension module */
-#include "stm32f4xx_hal_ltdc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup LTDC_Exported_Functions
- * @{
- */
-/** @addtogroup LTDC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
-HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup LTDC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
-/**
- * @}
- */
-
-/** @addtogroup LTDC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
-HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
-HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
-HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-
-/**
- * @}
- */
-
-/** @addtogroup LTDC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
-uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup LTDC_Private_Macros LTDC Private Macros
- * @{
- */
-#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
-#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
-#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
-#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
-#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
-#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
-#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
-#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
-#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
-#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
- ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
-#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
- ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
-#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
-#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
-#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
-#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
-#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
-#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
-#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
-#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
-#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Functions LTDC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* LTDC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F4xx_HAL_LTDC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
deleted file mode 100644
index c2a6534..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_ltdc_ex.h
- * @author MCD Application Team
- * @brief Header file of LTDC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_LTDC_EX_H
-#define STM32F4xx_HAL_LTDC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-#if defined (LTDC) && defined (DSI)
-
-#include "stm32f4xx_hal_dsi.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup LTDCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup LTDCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup LTDCEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
-HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* LTDC && DSI */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F4xx_HAL_LTDC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
deleted file mode 100644
index 25a2198..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h
+++ /dev/null
@@ -1,745 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_mmc.h
- * @author MCD Application Team
- * @brief Header file of MMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_MMC_H
-#define STM32F4xx_HAL_MMC_H
-
-#if defined(SDIO)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup MMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_Types MMC Exported Types
- * @{
- */
-
-/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
- HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
- HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
- HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
- HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
- HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
- HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
-}HAL_MMC_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
- * @{
- */
-typedef uint32_t HAL_MMC_CardStateTypeDef;
-
-#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
-#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
-#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
-#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
-#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
-#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
-#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
-#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
-#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
- * @{
- */
-#define MMC_InitTypeDef SDIO_InitTypeDef
-#define MMC_TypeDef SDIO_TypeDef
-
-/**
- * @brief MMC Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
-}HAL_MMC_CardInfoTypeDef;
-
-/**
- * @brief MMC handle Structure definition
- */
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-typedef struct __MMC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
-{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
-
- MMC_InitTypeDef Init; /*!< MMC required parameters */
-
- HAL_LockTypeDef Lock; /*!< MMC locking object */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< MMC Tx Transfer size */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< MMC Rx Transfer size */
-
- __IO uint32_t Context; /*!< MMC transfer context */
-
- __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
-
- __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
-
- DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
-
- HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
- uint32_t CSD[4U]; /*!< MMC card specific data table */
-
- uint32_t CID[4U]; /*!< MMC card identification number table */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
-
- void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
-#endif
-}MMC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGroup; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-
-}HAL_MMC_CardCSDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_MMC_CardCIDTypeDef;
-/**
- * @}
- */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
- HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
- HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
- HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
-
- HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
- HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
-}HAL_MMC_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
- * @{
- */
-typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-#endif
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Constants Exported Constants
- * @{
- */
-
-#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
- * @{
- */
-#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
- * @{
- */
-#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
- * @{
- */
-/**
- * @brief
- */
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
-#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
- * @{
- */
-#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
-#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_macros MMC Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset MMC handle state.
- * @param __HANDLE__ : MMC handle.
- * @retval None
- */
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
-#endif
-
-/**
- * @brief Enable the MMC device.
- * @retval None
- */
-#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the MMC device.
- * @retval None
- */
-#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval The new state of MMC FLAG (SET or RESET).
- */
-#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the MMC's pending flags.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval None
- */
-#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval The new state of MMC IT (SET or RESET).
- */
-#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Functions MMC Exported Functions
- * @{
- */
-
-/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/* MMC callback registering/unregistering */
-HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
-#endif
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
- * @{
- */
-HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup MMC_Private_Types MMC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup MMC_Private_Defines MMC Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Variables MMC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Constants MMC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup MMC_Private_Macros MMC Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Functions MMC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SDIO */
-
-#endif /* STM32F4xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h
deleted file mode 100644
index b1bef3f..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_nand.h
- * @author MCD Application Team
- * @brief Header file of NAND HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_NAND_H
-#define __STM32F4xx_HAL_NAND_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
- #include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
- #include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
- STM32F479xx */
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NAND
- * @{
- */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-
-/* Exported typedef ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Types NAND Exported Types
- * @{
- */
-
-/**
- * @brief HAL NAND State structures definition
- */
-typedef enum
-{
- HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-}HAL_NAND_StateTypeDef;
-
-/**
- * @brief NAND Memory electronic signature Structure definition
- */
-typedef struct
-{
- /*State = HAL_NAND_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
-
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* IO operation functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
- * @{
- */
-#define NAND_DEVICE1 0x70000000U
-#define NAND_DEVICE2 0x80000000U
-#define NAND_WRITE_TIMEOUT 0x01000000U
-
-#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS 0x00000100U
-#define NAND_INVALID_ADDRESS 0x00000200U
-#define NAND_TIMEOUT_ERROR 0x00000400U
-#define NAND_BUSY 0x00000000U
-#define NAND_ERROR 0x00000001U
-#define NAND_READY 0x00000040U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Macros NAND Private Macros
- * @{
- */
-
-/**
- * @brief NAND memory address computation.
- * @param __ADDRESS__ NAND memory address.
- * @param __HANDLE__ NAND handle.
- * @retval NAND Raw address value
- */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
-
-/**
- * @brief NAND memory Column address computation.
- * @param __HANDLE__ NAND handle.
- * @retval NAND Raw address value
- */
-#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
-
-/**
- * @brief NAND memory address cycling.
- * @param __ADDRESS__ NAND memory address.
- * @retval NAND address cycling value.
- */
-#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
-
-/**
- * @brief NAND memory Columns cycling.
- * @param __ADDRESS__ NAND memory address.
- * @retval NAND Column address cycling value.
- */
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
-
-/**
- * @}
- */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F446xx || STM32F469xx || STM32F479xx */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
deleted file mode 100644
index 2d2956e..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
+++ /dev/null
@@ -1,753 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_qspi.h
- * @author MCD Application Team
- * @brief Header file of QSPI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_QSPI_H
-#define STM32F4xx_HAL_QSPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-#if defined(QUADSPI)
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup QSPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Types QSPI Exported Types
- * @{
- */
-
-/**
- * @brief QSPI Init structure definition
- */
-typedef struct
-{
- uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
- This parameter can be a number between 0 and 255 */
- uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
- This parameter can be a value between 1 and 32 */
- uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
- take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
- This parameter can be a value of @ref QSPI_SampleShifting */
- uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
- required to address the flash memory. The flash capacity can be up to 4GB
- (addressed using 32 bits) in indirect mode, but the addressable space in
- memory-mapped mode is limited to 256MB
- This parameter can be a number between 0 and 31 */
- uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
- of clock cycles which the chip select must remain high between commands.
- This parameter can be a value of @ref QSPI_ChipSelectHighTime */
- uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
- This parameter can be a value of @ref QSPI_ClockMode */
- uint32_t FlashID; /* Specifies the Flash which will be used,
- This parameter can be a value of @ref QSPI_Flash_Select */
- uint32_t DualFlash; /* Specifies the Dual Flash Mode State
- This parameter can be a value of @ref QSPI_DualFlash_Mode */
-}QSPI_InitTypeDef;
-
-/**
- * @brief HAL QSPI State structures definition
- */
-typedef enum
-{
- HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
- HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
- HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
- HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
- HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
- HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
- HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
- HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
- HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
-}HAL_QSPI_StateTypeDef;
-
-/**
- * @brief QSPI Handle Structure definition
- */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-typedef struct __QSPI_HandleTypeDef
-#else
-typedef struct
-#endif
-{
- QUADSPI_TypeDef *Instance; /* QSPI registers base address */
- QSPI_InitTypeDef Init; /* QSPI communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
- __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
- __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
- __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
- __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
- DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
- __IO HAL_LockTypeDef Lock; /* Locking object */
- __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
- __IO uint32_t ErrorCode; /* QSPI Error code */
- uint32_t Timeout; /* Timeout for the QSPI memory access */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
- void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
-
- void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
- void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
-#endif
-}QSPI_HandleTypeDef;
-
-/**
- * @brief QSPI Command structure definition
- */
-typedef struct
-{
- uint32_t Instruction; /* Specifies the Instruction to be sent
- This parameter can be a value (8-bit) between 0x00 and 0xFF */
- uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
- uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
- uint32_t AddressSize; /* Specifies the Address Size
- This parameter can be a value of @ref QSPI_AddressSize */
- uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
- This parameter can be a value of @ref QSPI_AlternateBytesSize */
- uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
- This parameter can be a number between 0 and 31 */
- uint32_t InstructionMode; /* Specifies the Instruction Mode
- This parameter can be a value of @ref QSPI_InstructionMode */
- uint32_t AddressMode; /* Specifies the Address Mode
- This parameter can be a value of @ref QSPI_AddressMode */
- uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
- This parameter can be a value of @ref QSPI_AlternateBytesMode */
- uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
- This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
- This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
- until end of memory)*/
- uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
- This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
- output by one half of system clock in DDR mode.
- This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
- uint32_t SIOOMode; /* Specifies the send instruction only once mode
- This parameter can be a value of @ref QSPI_SIOOMode */
-}QSPI_CommandTypeDef;
-
-/**
- * @brief QSPI Auto Polling mode configuration structure definition
- */
-typedef struct
-{
- uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFF */
- uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
- This parameter can be any value between 1 and 4 */
- uint32_t MatchMode; /* Specifies the method used for determining a match.
- This parameter can be a value of @ref QSPI_MatchMode */
- uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
- This parameter can be a value of @ref QSPI_AutomaticStop */
-}QSPI_AutoPollingTypeDef;
-
-/**
- * @brief QSPI Memory Mapped mode configuration structure definition
- */
-typedef struct
-{
- uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFF */
- uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
- This parameter can be a value of @ref QSPI_TimeOutActivation */
-}QSPI_MemoryMappedTypeDef;
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL QSPI Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
- HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
- HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
- HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
- HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
- HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
- HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
- HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
- HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
- HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
-
- HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
- HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
-}HAL_QSPI_CallbackIDTypeDef;
-
-/**
- * @brief HAL QSPI Callback pointer definition
- */
-typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
-#endif
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
- * @{
- */
-
-/** @defgroup QSPI_ErrorCode QSPI Error Code
- * @{
- */
-#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
-#endif
-/**
- * @}
- */
-
-/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
- * @{
- */
-#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!State = HAL_QSPI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
-#endif
-
-/** @brief Enable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @retval None
- */
-#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief Disable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @retval None
- */
-#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief Enable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Timeout interrupt
- * @arg QSPI_IT_SM: QSPI Status match interrupt
- * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
- * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
- * @arg QSPI_IT_TE: QSPI Transfer error interrupt
- * @retval None
- */
-#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-
-/** @brief Disable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Timeout interrupt
- * @arg QSPI_IT_SM: QSPI Status match interrupt
- * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
- * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
- * @arg QSPI_IT_TE: QSPI Transfer error interrupt
- * @retval None
- */
-#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief Check whether the specified QSPI interrupt source is enabled or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Timeout interrupt
- * @arg QSPI_IT_SM: QSPI Status match interrupt
- * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
- * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
- * @arg QSPI_IT_TE: QSPI Transfer error interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Check whether the selected QSPI flag is set or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI flag to check.
- * This parameter can be one of the following values:
- * @arg QSPI_FLAG_BUSY: QSPI Busy flag
- * @arg QSPI_FLAG_TO: QSPI Timeout flag
- * @arg QSPI_FLAG_SM: QSPI Status match flag
- * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
- * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
- * @arg QSPI_FLAG_TE: QSPI Transfer error flag
- * @retval None
- */
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
-
-/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
- * This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: QSPI Timeout flag
- * @arg QSPI_FLAG_SM: QSPI Status match flag
- * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
- * @arg QSPI_FLAG_TE: QSPI Transfer error flag
- * @retval None
- */
-#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup QSPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup QSPI_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
-/**
- * @}
- */
-
-/** @addtogroup QSPI_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-/* QSPI IRQ handler method */
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-
-/* QSPI status flag polling mode */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
-
-/* QSPI memory-mapped mode */
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-
-/* Callback functions in non-blocking modes ***********************************/
-void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI status flag polling mode */
-void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI memory-mapped mode */
-void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-/* QSPI callback registering/unregistering */
-HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
-#endif
-/**
- * @}
- */
-
-/** @addtogroup QSPI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
-uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
- * @{
- */
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
-
-#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
-
-#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
- ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-
-#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
- ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
- ((FLASH_ID) == QSPI_FLASH_ID_2))
-
-#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
- ((MODE) == QSPI_DUALFLASH_DISABLE))
-
-#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
-
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-
-#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
-
-#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
- ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
- ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
- ((MODE) == QSPI_INSTRUCTION_4_LINES))
-
-#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
- ((MODE) == QSPI_ADDRESS_1_LINE) || \
- ((MODE) == QSPI_ADDRESS_2_LINES) || \
- ((MODE) == QSPI_ADDRESS_4_LINES))
-
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-
-#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
- ((MODE) == QSPI_DATA_1_LINE) || \
- ((MODE) == QSPI_DATA_2_LINES) || \
- ((MODE) == QSPI_DATA_4_LINES))
-
-#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
- ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-
-#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
- ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
-
-#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
- ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-
-#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
-
-#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
- ((MODE) == QSPI_MATCH_MODE_OR))
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
- ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
-
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
- ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
-
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
-/**
-* @}
-*/
-/* End of private macros -----------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F4xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
deleted file mode 100644
index 8048f25..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
+++ /dev/null
@@ -1,897 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_sai.h
- * @author MCD Application Team
- * @brief Header file of SAI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SAI_H
-#define __STM32F4xx_HAL_SAI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
- defined(STM32F423xx)
-
-/** @addtogroup SAI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SAI_Exported_Types SAI Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
- HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
- HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
- HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
- HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
- HAL_SAI_STATE_TIMEOUT = 0x03U, /*!< SAI timeout state */
- HAL_SAI_STATE_ERROR = 0x04U /*!< SAI error state */
-} HAL_SAI_StateTypeDef;
-
-/**
- * @brief SAI Callback prototype
- */
-typedef void (*SAIcallback)(void);
-
-/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
- * @brief SAI Init Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
- This parameter can be a value of @ref SAI_Block_Mode */
-
- uint32_t Synchro; /*!< Specifies SAI Block synchronization
- This parameter can be a value of @ref SAI_Block_Synchronization */
-
- uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
- for BlockA and BlockB
- This parameter can be a value of @ref SAI_Block_SyncExt
- @note: If both audio blocks of same SAI are used, this parameter has
- to be set to the same value for each audio block */
-
- uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
- This parameter can be a value of @ref SAI_Block_Output_Drive
- @note this value has to be set before enabling the audio block
- but after the audio block configuration. */
-
- uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
- This parameter can be a value of @ref SAI_Block_NoDivider
- @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
- should be aligned to a number equal to a power of 2, from 8 to 256.
- If bit NODIV in the SAI_xCR1 register is set, the frame length can
- take any of the values without constraint since the input clock of
- the audio block should be equal to the bit clock.
- There is no MCLK_x clock which can be output. */
-
- uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
- This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
-
- uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
- This parameter is not used for STM32F446xx devices. */
-
- uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
- This parameter can be a value of @ref SAI_Audio_Frequency */
-
- uint32_t Mckdiv; /*!< Specifies the master clock divider.
- This parameter must be a number between Min_Data = 0 and Max_Data = 15.
- @note This parameter is used only if AudioFrequency is set to
- SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
-
- uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
- This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
-
- uint32_t CompandingMode; /*!< Specifies the companding mode type.
- This parameter can be a value of @ref SAI_Block_Companding_Mode */
-
- uint32_t TriState; /*!< Specifies the companding mode type.
- This parameter can be a value of @ref SAI_TRIState_Management */
-
- /* This part of the structure is automatically filled if your are using the high level intialisation
- function HAL_SAI_InitProtocol */
-
- uint32_t Protocol; /*!< Specifies the SAI Block protocol.
- This parameter can be a value of @ref SAI_Block_Protocol */
-
- uint32_t DataSize; /*!< Specifies the SAI Block data size.
- This parameter can be a value of @ref SAI_Block_Data_Size */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
-
- uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
- This parameter can be a value of @ref SAI_Block_Clock_Strobing */
-} SAI_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
- * @brief SAI Frame Init structure definition
- * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
- * @{
- */
-typedef struct
-{
- uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
- This parameter must be a number between Min_Data = 8 and Max_Data = 256.
- @note If master clock MCLK_x pin is declared as an output, the frame length
- should be aligned to a number equal to power of 2 in order to keep
- in an audio frame, an integer number of MCLK pulses by bit Clock. */
-
- uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
- This Parameter specifies the length in number of bit clock (SCK + 1)
- of the active level of FS signal in audio frame.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
-
- uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
- This parameter can be a value of @ref SAI_Block_FS_Definition */
-
- uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
- This parameter can be a value of @ref SAI_Block_FS_Polarity */
-
- uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
- This parameter can be a value of @ref SAI_Block_FS_Offset */
-} SAI_FrameInitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
- * @brief SAI Block Slot Init Structure definition
- * @note For SPDIF protocol, these parameters are not used (set by hardware).
- * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
- * @{
- */
-typedef struct
-{
- uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
- This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
-
- uint32_t SlotSize; /*!< Specifies the Slot Size.
- This parameter can be a value of @ref SAI_Block_Slot_Size */
-
- uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
- This parameter can be a value of @ref SAI_Block_Slot_Active */
-} SAI_SlotInitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
- * @brief SAI handle Structure definition
- * @{
- */
-typedef struct __SAI_HandleTypeDef
-{
- SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
-
- SAI_InitTypeDef Init; /*!< SAI communication parameters */
-
- SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
-
- SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
-
- uint16_t XferSize; /*!< SAI transfer size */
-
- uint16_t XferCount; /*!< SAI transfer counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
-
- SAIcallback mutecallback;/*!< SAI mute callback */
-
- void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
-
- HAL_LockTypeDef Lock; /*!< SAI locking object */
-
- __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
-
- __IO uint32_t ErrorCode; /*!< SAI Error code */
-
-#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
- void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
- void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
- void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
- void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
- void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
- void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
- void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
-#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
-} SAI_HandleTypeDef;
-/**
- * @}
- */
-
-#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
-/**
- * @brief SAI callback ID enumeration definition
- */
-typedef enum
-{
- HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
- HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
- HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
- HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
- HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
- HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
- HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
-} HAL_SAI_CallbackIDTypeDef;
-
-/**
- * @brief SAI callback pointer definition
- */
-typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
-#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SAI_Exported_Constants SAI Exported Constants
- * @{
- */
-
-/** @defgroup SAI_Error_Code SAI Error Code
- * @{
- */
-#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
-#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
-#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
-#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
-#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
-#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
-#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
-#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
-#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
-#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_SyncExt SAI External synchronisation
- * @{
- */
-#define SAI_SYNCEXT_DISABLE 0U
-#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
-#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
-/**
- * @}
- */
-
-/** @defgroup SAI_Protocol SAI Supported protocol
- * @{
- */
-#define SAI_I2S_STANDARD 0U
-#define SAI_I2S_MSBJUSTIFIED 1U
-#define SAI_I2S_LSBJUSTIFIED 2U
-#define SAI_PCM_LONG 3U
-#define SAI_PCM_SHORT 4U
-/**
- * @}
- */
-
-/** @defgroup SAI_Protocol_DataSize SAI protocol data size
- * @{
- */
-#define SAI_PROTOCOL_DATASIZE_16BIT 0U
-#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
-#define SAI_PROTOCOL_DATASIZE_24BIT 2U
-#define SAI_PROTOCOL_DATASIZE_32BIT 3U
-/**
- * @}
- */
-
-/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
- * @{
- */
-#define SAI_AUDIO_FREQUENCY_192K 192000U
-#define SAI_AUDIO_FREQUENCY_96K 96000U
-#define SAI_AUDIO_FREQUENCY_48K 48000U
-#define SAI_AUDIO_FREQUENCY_44K 44100U
-#define SAI_AUDIO_FREQUENCY_32K 32000U
-#define SAI_AUDIO_FREQUENCY_22K 22050U
-#define SAI_AUDIO_FREQUENCY_16K 16000U
-#define SAI_AUDIO_FREQUENCY_11K 11025U
-#define SAI_AUDIO_FREQUENCY_8K 8000U
-#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mode SAI Block Mode
- * @{
- */
-#define SAI_MODEMASTER_TX 0x00000000U
-#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
-#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
-#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Protocol SAI Block Protocol
- * @{
- */
-#define SAI_FREE_PROTOCOL 0x00000000U
-#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
-#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Data_Size SAI Block Data Size
- * @{
- */
-#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
-#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
-#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
-#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
- * @{
- */
-#define SAI_FIRSTBIT_MSB 0x00000000U
-#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
- * @{
- */
-#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
-#define SAI_CLOCKSTROBING_RISINGEDGE 1U
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
- * @{
- */
-#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
-#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
-#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
-#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
-#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
- * @{
- */
-#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
-#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
- * @{
- */
-#define SAI_FS_STARTFRAME 0x00000000U
-#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
- * @{
- */
-#define SAI_FS_ACTIVE_LOW 0x00000000U
-#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
- * @{
- */
-#define SAI_FS_FIRSTBIT 0x00000000U
-#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
- * @{
- */
-#define SAI_SLOTSIZE_DATASIZE 0x00000000U
-#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
-#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
- * @{
- */
-#define SAI_SLOT_NOTACTIVE 0x00000000U
-#define SAI_SLOTACTIVE_0 0x00000001U
-#define SAI_SLOTACTIVE_1 0x00000002U
-#define SAI_SLOTACTIVE_2 0x00000004U
-#define SAI_SLOTACTIVE_3 0x00000008U
-#define SAI_SLOTACTIVE_4 0x00000010U
-#define SAI_SLOTACTIVE_5 0x00000020U
-#define SAI_SLOTACTIVE_6 0x00000040U
-#define SAI_SLOTACTIVE_7 0x00000080U
-#define SAI_SLOTACTIVE_8 0x00000100U
-#define SAI_SLOTACTIVE_9 0x00000200U
-#define SAI_SLOTACTIVE_10 0x00000400U
-#define SAI_SLOTACTIVE_11 0x00000800U
-#define SAI_SLOTACTIVE_12 0x00001000U
-#define SAI_SLOTACTIVE_13 0x00002000U
-#define SAI_SLOTACTIVE_14 0x00004000U
-#define SAI_SLOTACTIVE_15 0x00008000U
-#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
-/**
- * @}
- */
-
-/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
- * @{
- */
-#define SAI_STEREOMODE 0x00000000U
-#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
-/**
- * @}
- */
-
-/** @defgroup SAI_TRIState_Management SAI TRIState Management
- * @{
- */
-#define SAI_OUTPUT_NOTRELEASED 0x00000000U
-#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
- * @{
- */
-#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
-#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
-#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
- * @{
- */
-#define SAI_NOCOMPANDING 0x00000000U
-#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
-#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
-#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
-#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
- * @{
- */
-#define SAI_ZERO_VALUE 0x00000000U
-#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
- * @{
- */
-#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
-#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
-#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
-#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
-#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
-#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
-#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
- * @{
- */
-#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
-#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
-#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
-#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
-#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
-#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
-#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
- * @{
- */
-#define SAI_FIFOSTATUS_EMPTY 0x00000000U
-#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
-#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
-#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
-#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
-#define SAI_FIFOSTATUS_FULL 0x00050000U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SAI_Exported_Macros SAI Exported Macros
- * @brief macros to handle interrupts and specific configurations
- * @{
- */
-
-/** @brief Reset SAI handle state
- * @param __HANDLE__ specifies the SAI Handle.
- * @retval None
- */
-#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
-#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
-#else
-#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
-#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
-
-/** @brief Enable or disable the specified SAI interrupts.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
- * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
- * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
- * @arg SAI_IT_FREQ: FIFO request interrupt enable
- * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
- * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
- * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
- * @retval None
- */
-#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
-#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
-
-/** @brief Check if the specified SAI interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the SAI Handle.
- * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
- * @param __INTERRUPT__ specifies the SAI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
- * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
- * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
- * @arg SAI_IT_FREQ: FIFO request interrupt enable
- * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
- * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
- * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SAI flag is set or not.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
- * @arg SAI_FLAG_MUTEDET: Mute detection flag.
- * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
- * @arg SAI_FLAG_FREQ: FIFO request flag.
- * @arg SAI_FLAG_CNRDY: Codec not ready flag.
- * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
- * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified SAI pending flag.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
- * @arg SAI_FLAG_MUTEDET: Clear Mute detection
- * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
- * @arg SAI_FLAG_FREQ: Clear FIFO request
- * @arg SAI_FLAG_CNRDY: Clear Codec not ready
- * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
- * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
- * @retval None
- */
-#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
-
-/** @brief Enable SAI
- * @param __HANDLE__ specifies the SAI Handle.
- * @retval None
- */
-#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
-
-/** @brief Disable SAI
- * @param __HANDLE__ specifies the SAI Handle.
- * @retval None
- */
-#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
-
-/**
- * @}
- */
-
-/* Include HAL SAI Extension module */
-#include "stm32f4xx_hal_sai_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SAI_Exported_Functions
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-/** @addtogroup SAI_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
-HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
-void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
-void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
-
-#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
-/* SAI callbacks register/unregister functions ********************************/
-HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
- HAL_SAI_CallbackIDTypeDef CallbackID,
- pSAI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
- HAL_SAI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* I/O operation functions *****************************************************/
-/** @addtogroup SAI_Exported_Functions_Group2
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
-
-/* Abort function */
-HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
-
-/* Mute management */
-HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
-HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
-HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
-
-/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
-void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
-/**
- * @}
- */
-
-/** @addtogroup SAI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
-uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup SAI_Private_Macros
- * @{
- */
-#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
- ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
- ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
-
-#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
- ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
- ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
- ((PROTOCOL) == SAI_PCM_LONG) ||\
- ((PROTOCOL) == SAI_PCM_SHORT))
-
-#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
- ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
- ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
- ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
-
-#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
-
-#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
- ((MODE) == SAI_MODEMASTER_RX) || \
- ((MODE) == SAI_MODESLAVE_TX) || \
- ((MODE) == SAI_MODESLAVE_RX))
-
-#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
- ((PROTOCOL) == SAI_AC97_PROTOCOL) || \
- ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
-
-#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
- ((DATASIZE) == SAI_DATASIZE_10) || \
- ((DATASIZE) == SAI_DATASIZE_16) || \
- ((DATASIZE) == SAI_DATASIZE_20) || \
- ((DATASIZE) == SAI_DATASIZE_24) || \
- ((DATASIZE) == SAI_DATASIZE_32))
-
-#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
- ((BIT) == SAI_FIRSTBIT_LSB))
-
-#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
- ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
-
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
- ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
-
-#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
- ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
-
-#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
- ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
-
-#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
-
-#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
- ((VALUE) == SAI_LAST_SENT_VALUE))
-
-#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
- ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
- ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
- ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
- ((MODE) == SAI_ALAW_2CPL_COMPANDING))
-
-#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
-
-#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
- ((STATE) == SAI_OUTPUT_RELEASED))
-
-#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
- ((MODE) == SAI_STEREOMODE))
-
-#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
-
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
-
-#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
- ((SIZE) == SAI_SLOTSIZE_16B) || \
- ((SIZE) == SAI_SLOTSIZE_32B))
-
-#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
-
-#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
- ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
-
-#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
- ((POLARITY) == SAI_FS_ACTIVE_HIGH))
-
-#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
- ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
-
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
-
-#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
-
-#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SAI_Private_Functions SAI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_SAI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
deleted file mode 100644
index 8f30bd6..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_sai_ex.h
- * @author MCD Application Team
- * @brief Header file of SAI Extension HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SAI_EX_H
-#define __STM32F4xx_HAL_SAI_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SAIEx
- * @{
- */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
- defined(STM32F423xx)
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SAI_Clock_Source SAI Clock Source
- * @{
- */
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define SAI_CLKSOURCE_PLLI2S 0x00000000U
-#define SAI_CLKSOURCE_EXT 0x00100000U
-#define SAI_CLKSOURCE_PLLR 0x00200000U
-#define SAI_CLKSOURCE_HS 0x00300000U
-#else
-#define SAI_CLKSOURCE_PLLSAI 0x00000000U
-#define SAI_CLKSOURCE_PLLI2S 0x00100000U
-#define SAI_CLKSOURCE_EXT 0x00200000U
-#define SAI_CLKSOURCE_NA 0x00400000U /*!< No applicable for STM32F446xx */
-#endif
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SAIEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup SAIEx_Exported_Functions_Group1
- * @{
- */
-
-/* Extended features functions ************************************************/
-void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
-uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
- ((SOURCE) == SAI_CLKSOURCE_EXT)||\
- ((SOURCE) == SAI_CLKSOURCE_PLLR)||\
- ((SOURCE) == SAI_CLKSOURCE_HS))
-#else
-#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
- ((SOURCE) == SAI_CLKSOURCE_EXT)||\
- ((SOURCE) == SAI_CLKSOURCE_PLLI2S)||\
- ((SOURCE) == SAI_CLKSOURCE_NA))
-#endif
-/* Private functions ---------------------------------------------------------*/
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_SAI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c
deleted file mode 100644
index 0780502..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c
+++ /dev/null
@@ -1,1342 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_dac.c
- * @author MCD Application Team
- * @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Digital to Analog Converter (DAC) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- *
- @verbatim
- ==============================================================================
- ##### DAC Peripheral features #####
- ==============================================================================
- [..]
- *** DAC Channels ***
- ====================
- [..]
- STM32F4 devices integrate two 12-bit Digital Analog Converters
-
- The 2 converters (i.e. channel1 & channel2)
- can be used independently or simultaneously (dual mode):
- (#) DAC channel1 with DAC_OUT1 (PA4) as output
- (#) DAC channel2 with DAC_OUT2 (PA5) as output
-
- *** DAC Triggers ***
- ====================
- [..]
- Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
- and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
- [..]
- Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
- The used pin (GPIOx_PIN_9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
- (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-
- (#) Software using DAC_TRIGGER_SOFTWARE
-
- *** DAC Buffer mode feature ***
- ===============================
- [..]
- Each DAC channel integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
- [..]
- (@) Refer to the device datasheet for more details about output
- impedance value with and without output buffer.
-
- *** DAC wave generation feature ***
- ===================================
- [..]
- Both DAC channels can be used to generate
- (#) Noise wave
- (#) Triangle wave
-
- *** DAC data format ***
- =======================
- [..]
- The DAC data format can be:
- (#) 8-bit right alignment using DAC_ALIGN_8B_R
- (#) 12-bit left alignment using DAC_ALIGN_12B_L
- (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
- *** DAC data value to voltage correspondence ***
- ================================================
- [..]
- The analog output voltage on each DAC channel pin is determined
- by the following equation:
- [..]
- DAC_OUTx = VREF+ * DOR / 4095
- (+) with DOR is the Data Output Register
- [..]
- VREF+ is the input voltage reference (refer to the device datasheet)
- [..]
- e.g. To set DAC_OUT1 to 0.7V, use
- (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
- *** DMA requests ***
- =====================
- [..]
- A DMA request can be generated when an external trigger (but not a software trigger)
- occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
- DMA1 requests are mapped as following:
- (#) DAC channel1 mapped on DMA1 Stream5 channel7 which must be
- already configured
- (#) DAC channel2 mapped on DMA1 Stream6 channel7 which must be
- already configured
-
- [..]
- (@) For Dual mode and specific signal (Triangle and noise) generation please
- refer to Extended Features Driver description
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) DAC APB clock must be enabled to get write access to DAC
- registers using HAL_DAC_Init()
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
- (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
- (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
-
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
- (+) Stop the DAC peripheral using HAL_DAC_Stop()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
- First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
- (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
- (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
- HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
- (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
- *** Callback registration ***
- =============================================
- [..]
- The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- Use Functions HAL_DAC_RegisterCallback() to register a user callback,
- it allows to register following callbacks:
- (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
- (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
- (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
- (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
- (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
- (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
- (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
- (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
- (+) MspInitCallback : DAC MspInit.
- (+) MspDeInitCallback : DAC MspdeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
- Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
- (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
- (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
- (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
- (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
- (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
- (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
- (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
- (+) MspInitCallback : DAC MspInit.
- (+) MspDeInitCallback : DAC MspdeInit.
- (+) All Callbacks
- This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
- By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
- Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
- and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in READY state only.
- Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
- in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
- during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
- or HAL_DAC_Init function.
-
- When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
-
- *** DAC HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DAC HAL driver.
-
- (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
- (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
- (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
- (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-
- [..]
- (@) You can refer to the DAC HAL driver header file for more useful macros
-
-@endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(DAC)
-
-/** @defgroup DAC DAC
- * @brief DAC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
- * @{
- */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DAC.
- (+) De-initialize the DAC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct and initialize the associated handle.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
-{
- /* Check DAC handle */
- if (hdac == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- if (hdac->State == HAL_DAC_STATE_RESET)
- {
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- /* Init the DAC Callback settings */
- hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
- hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
- hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
- hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-#if defined(DAC_CHANNEL2_SUPPORT)
- hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
- hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
- hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
- hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-#endif /* DAC_CHANNEL2_SUPPORT */
- if (hdac->MspInitCallback == NULL)
- {
- hdac->MspInitCallback = HAL_DAC_MspInit;
- }
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
- /* Allocate lock resource and initialize it */
- hdac->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- /* Init the low level hardware */
- hdac->MspInitCallback(hdac);
-#else
- /* Init the low level hardware */
- HAL_DAC_MspInit(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
- }
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitialize the DAC peripheral registers to their default reset values.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
-{
- /* Check DAC handle */
- if (hdac == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- if (hdac->MspDeInitCallback == NULL)
- {
- hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
- }
- /* DeInit the low level hardware */
- hdac->MspDeInitCallback(hdac);
-#else
- /* DeInit the low level hardware */
- HAL_DAC_MspDeInit(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the DAC MSP.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the DAC MSP.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- if (Channel == DAC_CHANNEL_1)
- {
- /* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
- {
- /* Enable the selected DAC software conversion */
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
- }
- }
-#if defined(DAC_CHANNEL2_SUPPORT)
- else
- {
- /* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
- {
- /* Enable the selected DAC software conversion*/
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
- }
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disables DAC and stop conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to DAC peripheral
- * @param Alignment Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- if (Channel == DAC_CHANNEL_1)
- {
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Enable the selected DAC channel1 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Case of use of channel 1 */
- switch (Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
- break;
- default:
- break;
- }
- }
-#if defined(DAC_CHANNEL2_SUPPORT)
- else
- {
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
- /* Enable the selected DAC channel2 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Case of use of channel 2 */
- switch (Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
- break;
- default:
- break;
- }
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
-
- /* Enable the DMA Stream */
- if (Channel == DAC_CHANNEL_1)
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
- /* Enable the DMA Stream */
- status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
- }
-#if defined(DAC_CHANNEL2_SUPPORT)
- else
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-
- /* Enable the DMA Stream */
- status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdac);
-
- if (status == HAL_OK)
- {
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
- }
- else
- {
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Disables DAC and stop conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the selected DAC channel DMA request */
- hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Disable the DMA Stream */
-
- /* Channel1 is used */
- if (Channel == DAC_CHANNEL_1)
- {
- /* Disable the DMA Stream */
- (void)HAL_DMA_Abort(hdac->DMA_Handle1);
-
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
- }
-#if defined(DAC_CHANNEL2_SUPPORT)
- else /* Channel2 is used for */
- {
- /* Disable the DMA Stream */
- (void)HAL_DMA_Abort(hdac->DMA_Handle2);
-
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handles DAC interrupt request
- * This function uses the interruption of DMA
- * underrun.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
-{
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
- {
- /* Check underrun flag of DAC channel 1 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to channel1 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Error callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->DMAUnderrunCallbackCh1(hdac);
-#else
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
- }
- }
-
-#if defined(DAC_CHANNEL2_SUPPORT)
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
- {
- /* Check underrun flag of DAC channel 2 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to channel2 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
-
- /* Disable the selected DAC channel2 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Error callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->DMAUnderrunCallbackCh2(hdac);
-#else
- HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
- }
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Alignment Specifies the data alignment.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data Data to be loaded in the selected data holding register.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
- __IO uint32_t tmp = 0UL;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)hdac->Instance;
- if (Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
- }
-#if defined(DAC_CHANNEL2_SUPPORT)
- else
- {
- tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
-
- /* Set the DAC channel selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Conversion complete callback in non-blocking mode for Channel1
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel1.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA underrun DAC callback for channel1.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
- uint32_t result = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- if (Channel == DAC_CHANNEL_1)
- {
- result = hdac->Instance->DOR1;
- }
-#if defined(DAC_CHANNEL2_SUPPORT)
- else
- {
- result = hdac->Instance->DOR2;
- }
-#endif /* DAC_CHANNEL2_SUPPORT */
- /* Returns the DAC channel data output register value */
- return result;
-}
-
-/**
- * @brief Configures the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig DAC configuration structure.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
-{
- uint32_t tmpreg1;
- uint32_t tmpreg2;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Get the DAC CR value */
- tmpreg1 = hdac->Instance->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
- /* Configure for the selected DAC channel: buffer output, trigger */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
- /* Write to DAC CR */
- hdac->Instance->CR = tmpreg1;
- /* Disable wave generation */
- CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DAC state.
- (+) Check the DAC Errors.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the DAC handle state
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL state
- */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
-{
- /* Return DAC handle state */
- return hdac->State;
-}
-
-
-/**
- * @brief Return the DAC error code
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval DAC Error Code
- */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
- return hdac->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User DAC Callback
- * To be used instead of the weak (surcharged) predefined callback
- * @param hdac DAC handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
- * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
- * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
- * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
- * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
- * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
- * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
- * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
- *
- * @param pCallback pointer to the Callback function
- * @retval status
- */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
- pDAC_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- if (hdac->State == HAL_DAC_STATE_READY)
- {
- switch (CallbackID)
- {
- case HAL_DAC_CH1_COMPLETE_CB_ID :
- hdac->ConvCpltCallbackCh1 = pCallback;
- break;
- case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
- hdac->ConvHalfCpltCallbackCh1 = pCallback;
- break;
- case HAL_DAC_CH1_ERROR_ID :
- hdac->ErrorCallbackCh1 = pCallback;
- break;
- case HAL_DAC_CH1_UNDERRUN_CB_ID :
- hdac->DMAUnderrunCallbackCh1 = pCallback;
- break;
-#if defined(DAC_CHANNEL2_SUPPORT)
- case HAL_DAC_CH2_COMPLETE_CB_ID :
- hdac->ConvCpltCallbackCh2 = pCallback;
- break;
- case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
- hdac->ConvHalfCpltCallbackCh2 = pCallback;
- break;
- case HAL_DAC_CH2_ERROR_ID :
- hdac->ErrorCallbackCh2 = pCallback;
- break;
- case HAL_DAC_CH2_UNDERRUN_CB_ID :
- hdac->DMAUnderrunCallbackCh2 = pCallback;
- break;
-#endif /* DAC_CHANNEL2_SUPPORT */
- case HAL_DAC_MSPINIT_CB_ID :
- hdac->MspInitCallback = pCallback;
- break;
- case HAL_DAC_MSPDEINIT_CB_ID :
- hdac->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (hdac->State == HAL_DAC_STATE_RESET)
- {
- switch (CallbackID)
- {
- case HAL_DAC_MSPINIT_CB_ID :
- hdac->MspInitCallback = pCallback;
- break;
- case HAL_DAC_MSPDEINIT_CB_ID :
- hdac->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdac);
- return status;
-}
-
-/**
- * @brief Unregister a User DAC Callback
- * DAC Callback is redirected to the weak (surcharged) predefined callback
- * @param hdac DAC handle
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
- * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
- * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
- * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
- * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
- * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
- * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
- * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
- * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
- * @retval status
- */
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- if (hdac->State == HAL_DAC_STATE_READY)
- {
- switch (CallbackID)
- {
- case HAL_DAC_CH1_COMPLETE_CB_ID :
- hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
- break;
- case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
- hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
- break;
- case HAL_DAC_CH1_ERROR_ID :
- hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
- break;
- case HAL_DAC_CH1_UNDERRUN_CB_ID :
- hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
- break;
-#if defined(DAC_CHANNEL2_SUPPORT)
- case HAL_DAC_CH2_COMPLETE_CB_ID :
- hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
- break;
- case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
- hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
- break;
- case HAL_DAC_CH2_ERROR_ID :
- hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
- break;
- case HAL_DAC_CH2_UNDERRUN_CB_ID :
- hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
- break;
-#endif /* DAC_CHANNEL2_SUPPORT */
- case HAL_DAC_MSPINIT_CB_ID :
- hdac->MspInitCallback = HAL_DAC_MspInit;
- break;
- case HAL_DAC_MSPDEINIT_CB_ID :
- hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
- break;
- case HAL_DAC_ALL_CB_ID :
- hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
- hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
- hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
- hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-#if defined(DAC_CHANNEL2_SUPPORT)
- hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
- hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
- hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
- hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-#endif /* DAC_CHANNEL2_SUPPORT */
- hdac->MspInitCallback = HAL_DAC_MspInit;
- hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (hdac->State == HAL_DAC_STATE_RESET)
- {
- switch (CallbackID)
- {
- case HAL_DAC_MSPINIT_CB_ID :
- hdac->MspInitCallback = HAL_DAC_MspInit;
- break;
- case HAL_DAC_MSPDEINIT_CB_ID :
- hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdac);
- return status;
-}
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA conversion complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->ConvCpltCallbackCh1(hdac);
-#else
- HAL_DAC_ConvCpltCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
- hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->ConvHalfCpltCallbackCh1(hdac);
-#else
- HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->ErrorCallbackCh1(hdac);
-#else
- HAL_DAC_ErrorCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
- hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c
deleted file mode 100644
index 0e10b09..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_dac_ex.c
- * @author MCD Application Team
- * @brief Extended DAC HAL module driver.
- * This file provides firmware functions to manage the extended
- * functionalities of the DAC peripheral.
- *
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- *** Dual mode IO operation ***
- ==============================
- [..]
- (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
- Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
- HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
- Channel 1 and Channel 2.
-
- *** Signal generation operation ***
- ===================================
- [..]
- (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
- (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-#if defined(DAC)
-
-/** @defgroup DACEx DACEx
- * @brief DAC Extended HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
- * @{
- */
-
-/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### Extended features functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
- (+) Get result of dual mode conversion.
-
-@endverbatim
- * @{
- */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Enables DAC and starts conversion of both channels.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
-{
- uint32_t tmp_swtrig = 0UL;
-
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
- __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
-
- /* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
- {
- tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
- }
- if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
- {
- tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
- }
- /* Enable the selected DAC software conversion*/
- SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disables DAC and stop conversion of both channels.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
-{
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
- __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @brief Enable or disable the selected DAC channel wave generation.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Amplitude Select max triangle amplitude.
- * This parameter can be one of the following values:
- * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
- * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
- * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
- * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
- * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
- * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
- * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
- * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
- * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
- * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
- * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
- * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the triangle wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
- (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable or disable the selected DAC channel wave generation.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
- * This parameter can be one of the following values:
- * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the noise wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
- (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Set the specified data holding register value for dual DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Alignment Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * DAC_ALIGN_8B_R: 8bit right data alignment selected
- * DAC_ALIGN_12B_L: 12bit left data alignment selected
- * DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
- * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
- uint32_t data;
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (Alignment == DAC_ALIGN_8B_R)
- {
- data = ((uint32_t)Data2 << 8U) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16U) | Data1;
- }
-
- tmp = (uint32_t)hdac->Instance;
- tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Conversion complete callback in non-blocking mode for Channel2.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel2.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA underrun DAC callback for Channel2.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
- */
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-
-/**
- * @}
- */
-
-/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
- * @{
- */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Return the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
-{
- uint32_t tmp = 0UL;
-
- tmp |= hdac->Instance->DOR1;
-
- tmp |= hdac->Instance->DOR2 << 16UL;
-
- /* Returns the DAC channel data output register value */
- return tmp;
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx private functions
- * @brief Extended private functions
- * @{
- */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief DMA conversion complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->ConvCpltCallbackCh2(hdac);
-#else
- HAL_DACEx_ConvCpltCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
- hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->ConvHalfCpltCallbackCh2(hdac);
-#else
- HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA error callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- hdac->ErrorCallbackCh2(hdac);
-#else
- HAL_DACEx_ErrorCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
- hdac->State = HAL_DAC_STATE_READY;
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c
deleted file mode 100644
index 9848dd0..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c
+++ /dev/null
@@ -1,2095 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_i2s.c
- * @author MCD Application Team
- * @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Integrated Interchip Sound (I2S) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The I2S HAL driver can be used as follow:
-
- (#) Declare a I2S_HandleTypeDef handle structure.
- (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
- (##) Enable the SPIx interface clock.
- (##) I2S pins configuration:
- (+++) Enable the clock for the I2S GPIOs.
- (+++) Configure these I2S pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
- and HAL_I2S_Receive_IT() APIs).
- (+++) Configure the I2Sx interrupt priority.
- (+++) Enable the NVIC I2S IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
- and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream/Channel.
- (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Stream/Channel.
-
- (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
- using HAL_I2S_Init() function.
-
- -@- The specific I2S interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
- -@- Make sure that either:
- (+@) I2S PLL clock is configured or
- (+@) External clock source is configured after setting correctly
- the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
-
- (#) Three mode of operations are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
- In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
- HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
- In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
- inside DR register and avoid using DeInit/Init process for the next transfer.
-
- *** I2S HAL driver macros list ***
- ===================================
- [..]
- Below the list of most used macros in I2S HAL driver.
-
- (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
- (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
- (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
- (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
-
- [..]
- (@) You can refer to the I2S HAL driver header file for more useful macros
-
- *** I2S HAL driver macros list ***
- ===================================
- [..]
- Callback registration:
-
- (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
- allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
-
- Function HAL_I2S_RegisterCallback() allows to register following callbacks:
- (++) TxCpltCallback : I2S Tx Completed callback
- (++) RxCpltCallback : I2S Rx Completed callback
- (++) TxRxCpltCallback : I2S TxRx Completed callback
- (++) TxHalfCpltCallback : I2S Tx Half Completed callback
- (++) RxHalfCpltCallback : I2S Rx Half Completed callback
- (++) ErrorCallback : I2S Error callback
- (++) MspInitCallback : I2S Msp Init callback
- (++) MspDeInitCallback : I2S Msp DeInit callback
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
-
- (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
- weak function.
- HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (++) TxCpltCallback : I2S Tx Completed callback
- (++) RxCpltCallback : I2S Rx Completed callback
- (++) TxRxCpltCallback : I2S TxRx Completed callback
- (++) TxHalfCpltCallback : I2S Tx Half Completed callback
- (++) RxHalfCpltCallback : I2S Rx Half Completed callback
- (++) ErrorCallback : I2S Error callback
- (++) MspInitCallback : I2S Msp Init callback
- (++) MspDeInitCallback : I2S Msp DeInit callback
-
- [..]
- By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
- all callbacks are set to the corresponding weak functions:
- examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
- these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
- [..]
- Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
- Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- Then, the user first registers the MspInit/MspDeInit user callbacks
- using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
- or HAL_I2S_Init() function.
-
- [..]
- When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2S I2S
- * @brief I2S HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
- uint32_t Timeout);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the I2Sx peripheral in simplex mode:
-
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2S_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Standard
- (++) Data Format
- (++) MCLK Output
- (++) Audio frequency
- (++) Polarity
- (++) Full duplex mode
-
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx peripheral.
- @endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2S according to the specified parameters
- * in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
- uint32_t i2sdiv;
- uint32_t i2sodd;
- uint32_t packetlength;
- uint32_t tmp;
- uint32_t i2sclk;
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- uint16_t tmpreg;
-#endif
-
- /* Check the I2S handle allocation */
- if (hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
- assert_param(IS_I2S_MODE(hi2s->Init.Mode));
- assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
- assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
- assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
- assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
-
- if (hi2s->State == HAL_I2S_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2s->Lock = HAL_UNLOCKED;
-
- /* Initialize Default I2S IrqHandler ISR */
- hi2s->IrqHandlerISR = I2S_IRQHandler;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- /* Init the I2S Callback settings */
- hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
-
- if (hi2s->MspInitCallback == NULL)
- {
- hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
- }
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- hi2s->MspInitCallback(hi2s);
-#else
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2S_MspInit(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
- hi2s->Instance->I2SPR = 0x0002U;
-
- /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
- /* If the requested audio frequency is not the default, compute the prescaler */
- if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
- {
- /* Check the frame length (For the Prescaler computing) ********************/
- if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
- {
- /* Packet length is 16 bits */
- packetlength = 16U;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 32U;
- }
-
- /* I2S standard */
- if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
- {
- /* In I2S standard packet length is multiplied by 2 */
- packetlength = packetlength * 2U;
- }
-
- /* Get the source clock value **********************************************/
-#if defined(I2S_APB1_APB2_FEATURE)
- if (IS_I2S_APB1_INSTANCE(hi2s->Instance))
- {
- i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1);
- }
- else
- {
- i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2);
- }
-#else
- i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
-#endif /* I2S_APB1_APB2_FEATURE */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
- {
- tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
- }
- else
- {
- tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
- }
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint32_t)(tmp & (uint32_t)1U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint32_t)(i2sodd << 8U);
- }
- else
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
- return HAL_ERROR;
- }
-
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
-
- /* Write to SPIx I2SPR register the computed value */
- hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- /* And configure the I2S with the I2S_InitStruct values */
- MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
- SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
- (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
- hi2s->Init.Standard | hi2s->Init.DataFormat | \
- hi2s->Init.CPOL));
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
- if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
- {
- /* Write to SPIx I2SCFGR */
- SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
- }
-#endif /* SPI_I2SCFGR_ASTRTEN */
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-
- /* Configure the I2S extended if the full duplex mode is enabled */
- assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
-
- if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
- hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler;
-
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
- I2SxEXT(hi2s->Instance)->I2SPR = 2U;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- tmp = I2S_MODE_SLAVE_RX;
- }
- else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */
- {
- tmp = I2S_MODE_SLAVE_TX;
- }
-
- /* Configure the I2S Slave with the I2S Master parameter values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
- (uint16_t)tmp | \
- (uint16_t)hi2s->Init.Standard | \
- (uint16_t)hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL);
-
- /* Write to SPIx I2SCFGR */
- WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the I2S peripheral
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Check the I2S handle allocation */
- if (hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* Disable the I2S Peripheral Clock */
- __HAL_I2S_DISABLE(hi2s);
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- if (hi2s->MspDeInitCallback == NULL)
- {
- hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- hi2s->MspDeInitCallback(hi2s);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_I2S_MspDeInit(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief I2S MSP Init
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S MSP DeInit
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspDeInit could be implemented in the user file
- */
-}
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
- * @brief Register a User I2S Callback
- * To be used instead of the weak predefined callback
- * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for the specified I2S.
- * @param CallbackID ID of the callback to be registered
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
- pI2S_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- /* Update the error code */
- hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hi2s);
-
- if (HAL_I2S_STATE_READY == hi2s->State)
- {
- switch (CallbackID)
- {
- case HAL_I2S_TX_COMPLETE_CB_ID :
- hi2s->TxCpltCallback = pCallback;
- break;
-
- case HAL_I2S_RX_COMPLETE_CB_ID :
- hi2s->RxCpltCallback = pCallback;
- break;
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- case HAL_I2S_TX_RX_COMPLETE_CB_ID :
- hi2s->TxRxCpltCallback = pCallback;
- break;
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
- hi2s->TxHalfCpltCallback = pCallback;
- break;
-
- case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
- hi2s->RxHalfCpltCallback = pCallback;
- break;
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
- hi2s->TxRxHalfCpltCallback = pCallback;
- break;
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- case HAL_I2S_ERROR_CB_ID :
- hi2s->ErrorCallback = pCallback;
- break;
-
- case HAL_I2S_MSPINIT_CB_ID :
- hi2s->MspInitCallback = pCallback;
- break;
-
- case HAL_I2S_MSPDEINIT_CB_ID :
- hi2s->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (HAL_I2S_STATE_RESET == hi2s->State)
- {
- switch (CallbackID)
- {
- case HAL_I2S_MSPINIT_CB_ID :
- hi2s->MspInitCallback = pCallback;
- break;
-
- case HAL_I2S_MSPDEINIT_CB_ID :
- hi2s->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
- return status;
-}
-
-/**
- * @brief Unregister an I2S Callback
- * I2S callback is redirected to the weak predefined callback
- * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for the specified I2S.
- * @param CallbackID ID of the callback to be unregistered
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hi2s);
-
- if (HAL_I2S_STATE_READY == hi2s->State)
- {
- switch (CallbackID)
- {
- case HAL_I2S_TX_COMPLETE_CB_ID :
- hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
- break;
-
- case HAL_I2S_RX_COMPLETE_CB_ID :
- hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
- break;
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- case HAL_I2S_TX_RX_COMPLETE_CB_ID :
- hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
- break;
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
- hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- break;
-
- case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
- hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- break;
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
- hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
- break;
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- case HAL_I2S_ERROR_CB_ID :
- hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_I2S_MSPINIT_CB_ID :
- hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_I2S_MSPDEINIT_CB_ID :
- hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (HAL_I2S_STATE_RESET == hi2s->State)
- {
- switch (CallbackID)
- {
- case HAL_I2S_MSPINIT_CB_ID :
- hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_I2S_MSPDEINIT_CB_ID :
- hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
- return status;
-}
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2S_Transmit()
- (++) HAL_I2S_Receive()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2S_Transmit_IT()
- (++) HAL_I2S_Receive_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2S_Transmit_DMA()
- (++) HAL_I2S_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2S_TxCpltCallback()
- (++) HAL_I2S_RxCpltCallback()
- (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 24-bit or 32-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tmpreg_cfgr;
-
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set state and reset error code */
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pTxBuffPtr = pData;
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR;
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- while (hi2s->TxXferCount > 0U)
- {
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr++;
- hi2s->TxXferCount--;
-
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- /* Check if an underrun occurs */
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Clear underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- }
- }
-
- /* Check if Slave mode is selected */
- if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
- || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
- {
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 24-bit or 32-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tmpreg_cfgr;
-
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set state and reset error code */
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pRxBuffPtr = pData;
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if Master Receiver mode is selected */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Receive data */
- while (hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
- hi2s->pRxBuffPtr++;
- hi2s->RxXferCount--;
-
- /* Check if an overrun occurs */
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- }
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return HAL_OK;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 24-bit or 32-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t tmpreg_cfgr;
-
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set state and reset error code */
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pTxBuffPtr = pData;
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- __HAL_UNLOCK(hi2s);
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 24-bit or 32-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
- * between Master and Slave otherwise the I2S interrupt should be optimized.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t tmpreg_cfgr;
-
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set state and reset error code */
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pRxBuffPtr = pData;
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Enable RXNE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- __HAL_UNLOCK(hi2s);
- return HAL_OK;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to the Transmit data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 24-bit or 32-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t tmpreg_cfgr;
-
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set state and reset error code */
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pTxBuffPtr = pData;
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Set the I2S Tx DMA Half transfer complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
- /* Set the I2S Tx DMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
- /* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
- (uint32_t)hi2s->pTxBuffPtr,
- (uint32_t)&hi2s->Instance->DR,
- hi2s->TxXferSize))
- {
- /* Update SPI error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- hi2s->State = HAL_I2S_STATE_READY;
-
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if the I2S Tx request is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- }
-
- __HAL_UNLOCK(hi2s);
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 24-bit or 32-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t tmpreg_cfgr;
-
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set state and reset error code */
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pRxBuffPtr = pData;
-
- tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
- /* Check if Master Receiver mode is selected */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
- hi2s->RxXferSize))
- {
- /* Update SPI error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- hi2s->State = HAL_I2S_STATE_READY;
-
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if the I2S Rx request is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- }
-
- __HAL_UNLOCK(hi2s);
- return HAL_OK;
-}
-
-/**
- * @brief Pauses the audio DMA Stream/Channel playing from the Media.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Disable the I2S DMA Tx request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- }
- else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Disable the I2S DMA Rx request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- }
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Pause the audio file playing by disabling the I2S DMA request */
- CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- else
- {
- /* nothing to do */
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio DMA Stream/Channel playing from the Media.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Enable the I2S DMA Tx request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- }
- else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Enable the I2S DMA Rx request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- }
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Pause the audio file playing by disabling the I2S DMA request */
- SET_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- SET_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-
- /* If the I2Sext peripheral is still not enabled, enable it */
- if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
- {
- /* Enable I2Sext peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
- }
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- else
- {
- /* nothing to do */
- }
-
- /* If the I2S peripheral is still not enabled, enable it */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the audio DMA Stream/Channel playing from the Media.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- uint32_t tickstart;
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- HAL_StatusTypeDef errorcode = HAL_OK;
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
- when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
- */
-
- if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- /* Abort the I2S DMA tx Stream/Channel */
- if (hi2s->hdmatx != NULL)
- {
- /* Disable the I2S DMA tx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
- {
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
-
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- hi2s->State = HAL_I2S_STATE_READY;
- errorcode = HAL_ERROR;
- }
-
- /* Wait until BSY flag is Reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- hi2s->State = HAL_I2S_STATE_READY;
- errorcode = HAL_ERROR;
- }
-
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Clear UDR flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Disable the I2S Tx DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-
- if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Abort the I2S DMA rx Stream/Channel */
- if (hi2s->hdmarx != NULL)
- {
- /* Disable the I2S DMA rx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
- {
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
-
- /* Disable I2Sext peripheral */
- __HAL_I2SEXT_DISABLE(hi2s);
-
- /* Clear OVR flag */
- __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
-
- /* Disable the I2SxEXT DMA request */
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
-
- if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Read DR to Flush RX Data */
- READ_REG(I2SxEXT(hi2s->Instance)->DR);
- }
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- }
-
- else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
- {
- /* Abort the I2S DMA rx Stream/Channel */
- if (hi2s->hdmarx != NULL)
- {
- /* Disable the I2S DMA rx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
- {
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-
- if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Abort the I2S DMA tx Stream/Channel */
- if (hi2s->hdmatx != NULL)
- {
- /* Disable the I2S DMA tx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
- {
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
-
- tickstart = HAL_GetTick();
-
- /* Wait until TXE flag is set */
- while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_TXE) != SET)
- {
- if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
- errorcode = HAL_ERROR;
- }
- }
-
- /* Wait until BSY flag is Reset */
- while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_BSY) != RESET)
- {
- if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
- errorcode = HAL_ERROR;
- }
- }
-
- /* Disable I2Sext peripheral */
- __HAL_I2SEXT_DISABLE(hi2s);
-
- /* Clear UDR flag */
- __HAL_I2SEXT_CLEAR_UDRFLAG(hi2s);
-
- /* Disable the I2SxEXT DMA request */
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Clear OVR flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Disable the I2S Rx DMA request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
- if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Read DR to Flush RX Data */
- READ_REG((hi2s->Instance)->DR);
- }
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- return errorcode;
-}
-
-/**
- * @brief This function handles I2S interrupt request.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- /* Call the IrqHandler ISR set during HAL_I2S_INIT */
- hi2s->IrqHandlerISR(hi2s);
-}
-
-/**
- * @brief Tx Transfer Half completed callbacks
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer half completed callbacks
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S error callbacks
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2S state
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL state
- */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->State;
-}
-
-/**
- * @brief Return the I2S error code
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval I2S Error Code
- */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-/**
- * @brief DMA I2S transmit process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
- /* if DMA is configured in DMA_NORMAL Mode */
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- /* Disable Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
- hi2s->TxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
- }
- /* Call user Tx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxCpltCallback(hi2s);
-#else
- HAL_I2S_TxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA I2S transmit process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user Tx half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxHalfCpltCallback(hi2s);
-#else
- HAL_I2S_TxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA I2S receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
- /* if DMA is configured in DMA_NORMAL Mode */
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- /* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- hi2s->RxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
- }
- /* Call user Rx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->RxCpltCallback(hi2s);
-#else
- HAL_I2S_RxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA I2S receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user Rx half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->RxHalfCpltCallback(hi2s);
-#else
- HAL_I2S_RxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr++;
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call user Tx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxCpltCallback(hi2s);
-#else
- HAL_I2S_TxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
- /* Receive data */
- (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
- hi2s->pRxBuffPtr++;
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call user Rx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->RxCpltCallback(hi2s);
-#else
- HAL_I2S_RxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief This function handles I2S interrupt request.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- __IO uint32_t i2ssr = hi2s->Instance->SR;
-
- if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* I2S in mode Receiver ------------------------------------------------*/
- if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- I2S_Receive_IT(hi2s);
- }
-
- /* I2S Overrun error interrupt occurred -------------------------------------*/
- if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-
- if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* I2S in mode Transmitter -----------------------------------------------*/
- if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- I2S_Transmit_IT(hi2s);
- }
-
- /* I2S Underrun error interrupt occurred --------------------------------*/
- if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Clear Underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until flag is set to status*/
- while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c
deleted file mode 100644
index 97e3fd6..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c
+++ /dev/null
@@ -1,1138 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_i2s_ex.c
- * @author MCD Application Team
- * @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of I2S extension peripheral:
- * + Extension features Functions
- *
- @verbatim
- ==============================================================================
- ##### I2S Extension features #####
- ==============================================================================
- [..]
- (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
- data simultaneously using two data lines. Each SPI peripheral has an extended block
- called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
- (#) The extension block is not a full SPI IP, it is used only as I2S slave to
- implement full duplex mode. The extension block uses the same clock sources
- as its master.
-
- (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
-
- [..]
- (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
- I2Sx can be I2S2 or I2S3.
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
- (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
- (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) __HAL_I2SEXT_FLUSH_RX_DR: In Full-Duplex Slave mode, if HAL_I2S_DMAStop is used to stop the
- communication, an error HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
- In this case __HAL_I2SEXT_FLUSH_RX_DR macro must be used to flush the remaining data
- inside I2Sx and I2Sx_ext DR registers and avoid using DeInit/Init process for the next transfer.
- @endverbatim
-
- Additional Figure: The Extended block uses the same clock sources as its master.
-
- +-----------------------+
- I2Sx_SCK | |
- ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
- +--|-->| |
- | | +-----------------------+
- | |
- I2S_WS | |
- ------>| |
- | | +-----------------------+
- | +-->| |
- | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
- +----->| |
- +-----------------------+
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-/** @defgroup I2SEx I2SEx
- * @brief I2S Extended HAL module driver
- * @{
- */
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-
-/* Private typedef -----------------------------------------------------------*/
-/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
- * @{
- */
-typedef enum
-{
- I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
- I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */
-} I2S_UseTypeDef;
-/**
- * @}
- */
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
- * @{
- */
-static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
-static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
-static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
-static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
-static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
-static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
- uint32_t Flag,
- uint32_t State,
- uint32_t Timeout,
- I2S_UseTypeDef i2sUsed);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup I2SEx I2SEx
- * @{
- */
-
-/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
- * @{
- */
-
-/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
- * @brief I2SEx IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions#####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2SEx_TransmitReceive()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2SEx_TransmitReceive_IT()
- (++) HAL_I2SEx_FullDuplex_IRQHandler()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2SEx_TransmitReceive_DMA()
-
- (#) A set of Transfer Complete Callback are provided in non Blocking mode:
- (++) HAL_I2SEx_TxRxCpltCallback()
-@endverbatim
- * @{
- */
-/**
- * @brief Full-Duplex Transmit/Receive data in blocking mode.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
- uint16_t *pTxData,
- uint16_t *pRxData,
- uint16_t Size,
- uint32_t Timeout)
-{
- uint32_t tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set state and reset error code */
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
- {
- /* Prepare the First Data before enabling the I2S */
- hi2s->Instance->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2Sx peripheral */
- __HAL_I2S_ENABLE(hi2s);
-
- /* Check if Master Receiver mode is selected */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
- }
-
- while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
- {
- if (hi2s->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
- }
- /* Write Data on DR register */
- hi2s->Instance->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Check if an underrun occurs */
- if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
- {
- /* Clear Underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- }
- }
- if (hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
- }
- /* Read Data from DR register */
- (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
- hi2s->RxXferCount--;
-
- /* Check if an overrun occurs */
- if (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- }
- }
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- /* Prepare the First Data before enabling the I2S */
- I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral before the I2Sext*/
- __HAL_I2S_ENABLE(hi2s);
-
- /* Check if Master Receiver mode is selected */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
- {
- if (hi2s->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
- }
- /* Write Data on DR register */
- I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Check if an underrun occurs */
- if ((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
- {
- /* Clear Underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- }
- }
- if (hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
- {
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- errorcode = HAL_ERROR;
- goto error;
- }
- /* Read Data from DR register */
- (*pRxData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
-
- /* Check if an overrun occurs */
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- }
- }
- }
- }
-
- if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error :
- hi2s->State = HAL_I2S_STATE_READY;
- __HAL_UNLOCK(hi2s);
- return errorcode;
-}
-
-/**
- * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
- uint16_t *pTxData,
- uint16_t *pRxData,
- uint16_t Size)
-{
- uint32_t tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
-
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
- /* Set the function for IT treatment */
- if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- /* Enable I2Sext RXNE and ERR interrupts */
- __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Enable I2Sx TXE and ERR interrupts */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Transmit First data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- }
- }
- else /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- {
- /* Enable I2Sext TXE and ERR interrupts */
- __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Enable I2Sext RXNE and ERR interrupts */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Transmit First data */
- I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable I2Sext TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- }
- }
-
- /* Enable I2Sext peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
-
-error :
- __HAL_UNLOCK(hi2s);
- return errorcode;
-}
-
-/**
- * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
- uint16_t *pTxData,
- uint16_t *pRxData,
- uint16_t Size)
-{
- uint32_t *tmp = NULL;
- uint32_t tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
-
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
-
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
-
- /* Set the I2S Rx DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
-
- /* Set the I2S Tx DMA Half transfer complete callback as NULL */
- hi2s->hdmatx->XferHalfCpltCallback = NULL;
-
- /* Set the I2S Tx DMA transfer complete callback as NULL */
- hi2s->hdmatx->XferCpltCallback = NULL;
-
- /* Set the I2S Tx DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
-
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
- {
- /* Enable the Rx DMA Stream */
- tmp = (uint32_t *)&pRxData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
-
- /* Enable Rx DMA Request */
- SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
-
- /* Enable the Tx DMA Stream */
- tmp = (uint32_t *)&pTxData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral after the I2Sext */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
- else
- {
- /* Check if Master Receiver mode is selected */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
- /* Enable the Tx DMA Stream */
- tmp = (uint32_t *)&pTxData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
-
- /* Enable Tx DMA Request */
- SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
-
- /* Enable the Rx DMA Stream */
- tmp = (uint32_t *)&pRxData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
-
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
- /* Enable I2S peripheral before the I2Sext */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
-
-error :
- __HAL_UNLOCK(hi2s);
- return errorcode;
-}
-
-/**
- * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
- * @param hi2s I2S handle
- * @retval HAL status
- */
-void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- __IO uint32_t i2ssr = hi2s->Instance->SR;
- __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
- __IO uint32_t i2scr2 = hi2s->Instance->CR2;
- __IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2;
-
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- /* I2S in mode Transmitter -------------------------------------------------*/
- if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
- I2SEx_TxISR_I2S(hi2s);
- }
-
- /* I2Sext in mode Receiver -----------------------------------------------*/
- if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
- I2SEx_RxISR_I2SExt(hi2s);
- }
-
- /* I2Sext Overrun error interrupt occurred --------------------------------*/
- if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
-
- /* I2S Underrun error interrupt occurred ----------------------------------*/
- if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Disable RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Clear underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- /* I2Sext in mode Transmitter ----------------------------------------------*/
- if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
- I2SEx_TxISR_I2SExt(hi2s);
- }
-
- /* I2S in mode Receiver --------------------------------------------------*/
- if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
- I2SEx_RxISR_I2S(hi2s);
- }
-
- /* I2S Overrun error interrupt occurred -------------------------------------*/
- if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Disable TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
-
- /* I2Sext Underrun error interrupt occurred -------------------------------*/
- if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @brief Tx and Rx Transfer half completed callback
- * @param hi2s I2S handle
- * @retval None
- */
-__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callback
- * @param hi2s I2S handle
- * @retval None
- */
-__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
- * @{
- */
-
-/**
- * @brief DMA I2S transmit receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Call user TxRx Half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxRxHalfCpltCallback(hi2s);
-#else
- HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA I2S transmit receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* If DMA is configured in DMA_NORMAL mode */
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
- ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- /* Disable Tx & Rx DMA Requests */
- {
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- }
- else
- {
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
- }
-
- hi2s->RxXferCount = 0U;
- hi2s->TxXferCount = 0U;
-
- hi2s->State = HAL_I2S_STATE_READY;
- }
-
- /* Call user TxRx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxRxCpltCallback(hi2s);
-#else
- HAL_I2SEx_TxRxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma DMA handle
- * @retval None
- */
-static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->ErrorCallback(hi2s);
-#else
- HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief I2S Full-Duplex IT handler transmit function
- * @param hi2s I2S handle
- * @retval None
- */
-static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s)
-{
- /* Write Data on DR register */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if (hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call user TxRx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxRxCpltCallback(hi2s);
-#else
- HAL_I2SEx_TxRxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @brief I2SExt Full-Duplex IT handler transmit function
- * @param hi2s I2S handle
- * @retval None
- */
-static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s)
-{
- /* Write Data on DR register */
- I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable I2Sext TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if (hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call user TxRx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxRxCpltCallback(hi2s);
-#else
- HAL_I2SEx_TxRxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @brief I2S Full-Duplex IT handler receive function
- * @param hi2s I2S handle
- * @retval None
- */
-static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s)
-{
- /* Read Data from DR register */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- if (hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call user TxRx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxRxCpltCallback(hi2s);
-#else
- HAL_I2SEx_TxRxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @brief I2SExt Full-Duplex IT handler receive function
- * @param hi2s I2S handle
- * @retval None
- */
-static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
-{
- /* Read Data from DR register */
- (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- /* Disable I2Sext RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- if (hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call user TxRx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- hi2s->TxRxCpltCallback(hi2s);
-#else
- HAL_I2SEx_TxRxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s I2S handle
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
- * @param i2sUsed I2S instance reference
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
- uint32_t Flag,
- uint32_t State,
- uint32_t Timeout,
- I2S_UseTypeDef i2sUsed)
-{
- uint32_t tickstart = HAL_GetTick();
-
- if (i2sUsed == I2S_USE_I2S)
- {
- /* Wait until flag is reset */
- while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else /* i2sUsed == I2S_USE_I2SEXT */
- {
- /* Wait until flag is reset */
- while (((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/**
- * @}
- */
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c
deleted file mode 100644
index 31c8799..0000000
--- a/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c
+++ /dev/null
@@ -1,2903 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_qspi.c
- * @author MCD Application Team
- * @brief QSPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the QuadSPI interface (QSPI).
- * + Initialization and de-initialization functions
- * + Indirect functional mode management
- * + Memory-mapped functional mode management
- * + Auto-polling functional mode management
- * + Interrupts and flags management
- * + DMA channel configuration for indirect functional mode
- * + Errors management and abort functionality
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- *** Initialization ***
- ======================
- [..]
- (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
- (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
- (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
- (++) If interrupt mode is used, enable and configure QuadSPI global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
- with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
- link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
- DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (#) Configure the flash size, the clock prescaler, the fifo threshold, the
- clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
-
- *** Indirect functional mode ***
- ================================
- [..]
- (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
- functions :
- (++) Instruction phase : the mode used and if present the instruction opcode.
- (++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
- bytes values.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used and if present the number of bytes.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
- if activated.
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (#) If no data is required for the command, it is sent directly to the memory :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
- (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
- HAL_QSPI_Transmit_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
- HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
- HAL_QSPI_Receive_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
- HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-
- *** Auto-polling functional mode ***
- ====================================
- [..]
- (#) Configure the command sequence and the auto-polling functional mode using the
- HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
- (++) Instruction phase : the mode used and if present the instruction opcode.
- (++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
- bytes values.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
- if activated.
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
- the polling interval and the automatic stop activation.
- (#) After the configuration :
- (++) In polling mode, the output of the function is done when the status match is reached. The
- automatic stop is activated to avoid an infinite loop.
- (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
-
- *** Memory-mapped functional mode ***
- =====================================
- [..]
- (#) Configure the command sequence and the memory-mapped functional mode using the
- HAL_QSPI_MemoryMapped() functions :
- (++) Instruction phase : the mode used and if present the instruction opcode.
- (++) Address phase : the mode used and the size.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
- bytes values.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
- if activated.
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (++) The timeout activation and the timeout period.
- (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
- the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
-
- *** Errors management and abort functionality ***
- =================================================
- [..]
- (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
- flushes the fifo :
- (++) In polling mode, the output of the function is done when the transfer
- complete bit is set and the busy bit cleared.
- (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
- the transfer complete bit is set.
-
- *** Control functions ***
- =========================
- [..]
- (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
- (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
- (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
- (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
- (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
-
- *** Callback registration ***
- =============================================
- [..]
- The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
- it allows to register following callbacks:
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) FifoThresholdCallback : callback when the fifo threshold is reached.
- (+) CmdCpltCallback : callback when a command without data is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
- (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
- (+) StatusMatchCallback : callback when a status match occurs.
- (+) TimeOutCallback : callback when the timeout perioed expires.
- (+) MspInitCallback : QSPI MspInit.
- (+) MspDeInitCallback : QSPI MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
- Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) FifoThresholdCallback : callback when the fifo threshold is reached.
- (+) CmdCpltCallback : callback when a command without data is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
- (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
- (+) StatusMatchCallback : callback when a status match occurs.
- (+) TimeOutCallback : callback when the timeout perioed expires.
- (+) MspInitCallback : QSPI MspInit.
- (+) MspDeInitCallback : QSPI MspDeInit.
- This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
- By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
- Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
- and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in READY state only.
- Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
- in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
- during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
- or HAL_QSPI_Init function.
-
- When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
-
- *** Workarounds linked to Silicon Limitation ***
- ====================================================
- [..]
- (#) Workarounds Implemented inside HAL Driver
- (++) Extra data written in the FIFO at the end of a read transfer
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-#if defined(QUADSPI)
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup QSPI QSPI
- * @brief QSPI HAL module driver
- * @{
- */
-#ifdef HAL_QSPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-
-/* Private define ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Constants QSPI Private Constants
- * @{
- */
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!Instance));
- assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
- assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
- assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
- assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
- assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
- assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
- assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
-
- if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
- {
- assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
- }
-
- if(hqspi->State == HAL_QSPI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hqspi->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
- hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
- hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
- hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
- hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
- hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
- hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
- hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
- hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
- hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
- hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
-
- if(hqspi->MspInitCallback == NULL)
- {
- hqspi->MspInitCallback = HAL_QSPI_MspInit;
- }
-
- /* Init the low level hardware */
- hqspi->MspInitCallback(hqspi);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_QSPI_MspInit(hqspi);
-#endif
-
- /* Configure the default timeout for the QSPI memory access */
- HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
- }
-
- /* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
- if(status == HAL_OK)
- {
- /* Configure QSPI Clock Prescaler and Sample Shift */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
- ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
- hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
-
- /* Configure QSPI Flash Size, CS High Time and Clock Mode */
- MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
- ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
- hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
-
- /* Enable the QSPI peripheral */
- __HAL_QSPI_ENABLE(hqspi);
-
- /* Set QSPI error code to none */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Initialize the QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief De-Initialize the QSPI peripheral.
- * @param hqspi : QSPI handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
-{
- /* Check the QSPI handle allocation */
- if(hqspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Disable the QSPI Peripheral Clock */
- __HAL_QSPI_DISABLE(hqspi);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- if(hqspi->MspDeInitCallback == NULL)
- {
- hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
- }
-
- /* DeInit the low level hardware */
- hqspi->MspDeInitCallback(hqspi);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_QSPI_MspDeInit(hqspi);
-#endif
-
- /* Set QSPI error code to none */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Initialize the QSPI state */
- hqspi->State = HAL_QSPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the QSPI MSP.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the QSPI MSP.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
- * @brief QSPI Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to :
- (+) Handle the interrupts.
- (+) Handle the command sequence.
- (+) Transmit data in blocking, interrupt or DMA mode.
- (+) Receive data in blocking, interrupt or DMA mode.
- (+) Manage the auto-polling functional mode.
- (+) Manage the memory-mapped functional mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle QSPI interrupt request.
- * @param hqspi : QSPI handle
- * @retval None
- */
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
-{
- __IO uint32_t *data_reg;
- uint32_t flag = READ_REG(hqspi->Instance->SR);
- uint32_t itsource = READ_REG(hqspi->Instance->CR);
-
- /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
- if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
- {
- data_reg = &hqspi->Instance->DR;
-
- if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
- {
- /* Transmission process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
- {
- if (hqspi->TxXferCount > 0U)
- {
- /* Fill the FIFO until the threshold is reached */
- *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
- hqspi->pTxBuffPtr++;
- hqspi->TxXferCount--;
- }
- else
- {
- /* No more data available for the transfer */
- /* Disable the QSPI FIFO Threshold Interrupt */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
- break;
- }
- }
- }
- else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
- {
- /* Receiving Process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
- {
- if (hqspi->RxXferCount > 0U)
- {
- /* Read the FIFO until the threshold is reached */
- *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
- hqspi->pRxBuffPtr++;
- hqspi->RxXferCount--;
- }
- else
- {
- /* All data have been received for the transfer */
- /* Disable the QSPI FIFO Threshold Interrupt */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
- break;
- }
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- /* FIFO Threshold callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->FifoThresholdCallback(hqspi);
-#else
- HAL_QSPI_FifoThresholdCallback(hqspi);
-#endif
- }
-
- /* QSPI Transfer Complete interrupt occurred -------------------------------*/
- else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
-
- /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
- /* Transfer complete callback */
- if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
- {
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Disable the DMA channel */
- __HAL_DMA_DISABLE(hqspi->hdma);
- }
-
- /* Clear Busy bit */
- HAL_QSPI_Abort_IT(hqspi);
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* TX Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->TxCpltCallback(hqspi);
-#else
- HAL_QSPI_TxCpltCallback(hqspi);
-#endif
- }
- else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
- {
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Disable the DMA channel */
- __HAL_DMA_DISABLE(hqspi->hdma);
- }
- else
- {
- data_reg = &hqspi->Instance->DR;
- while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
- {
- if (hqspi->RxXferCount > 0U)
- {
- /* Read the last data received in the FIFO until it is empty */
- *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
- hqspi->pRxBuffPtr++;
- hqspi->RxXferCount--;
- }
- else
- {
- /* All data have been received for the transfer */
- break;
- }
- }
- }
-
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */
- HAL_QSPI_Abort_IT(hqspi);
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* RX Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->RxCpltCallback(hqspi);
-#else
- HAL_QSPI_RxCpltCallback(hqspi);
-#endif
- }
- else if(hqspi->State == HAL_QSPI_STATE_BUSY)
- {
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Command Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->CmdCpltCallback(hqspi);
-#else
- HAL_QSPI_CmdCpltCallback(hqspi);
-#endif
- }
- else if(hqspi->State == HAL_QSPI_STATE_ABORT)
- {
- /* Reset functional mode configuration to indirect write mode by default */
- CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
- {
- /* Abort called by the user */
-
- /* Abort Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->AbortCpltCallback(hqspi);
-#else
- HAL_QSPI_AbortCpltCallback(hqspi);
-#endif
- }
- else
- {
- /* Abort due to an error (eg : DMA error) */
-
- /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->ErrorCallback(hqspi);
-#else
- HAL_QSPI_ErrorCallback(hqspi);
-#endif
- }
- }
- else
- {
- /* Nothing to do */
- }
- }
-
- /* QSPI Status Match interrupt occurred ------------------------------------*/
- else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
-
- /* Check if the automatic poll mode stop is activated */
- if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
- {
- /* Disable the QSPI Transfer Error and Status Match Interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
-
- /* Status match callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->StatusMatchCallback(hqspi);
-#else
- HAL_QSPI_StatusMatchCallback(hqspi);
-#endif
- }
-
- /* QSPI Transfer Error interrupt occurred ----------------------------------*/
- else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
-
- /* Disable all the QSPI Interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
- /* Set error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Disable the DMA channel */
- hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
- if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
- {
- /* Set error code to DMA */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->ErrorCallback(hqspi);
-#else
- HAL_QSPI_ErrorCallback(hqspi);
-#endif
- }
- }
- else
- {
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->ErrorCallback(hqspi);
-#else
- HAL_QSPI_ErrorCallback(hqspi);
-#endif
- }
- }
-
- /* QSPI Timeout interrupt occurred -----------------------------------------*/
- else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
-
- /* Timeout callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->TimeOutCallback(hqspi);
-#else
- HAL_QSPI_TimeOutCallback(hqspi);
-#endif
- }
-
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief Set the command configuration.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param Timeout : Timeout duration
- * @note This function is used only in Indirect Read or Write Modes
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
-{
- HAL_StatusTypeDef status;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Call the configuration function */
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- if (cmd->DataMode == QSPI_DATA_NONE)
- {
- /* When there is no data phase, the transfer start as soon as the configuration is done
- so wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
- else
- {
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Set the command configuration in interrupt mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @note This function is used only in Indirect Read or Write Modes
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
-{
- HAL_StatusTypeDef status;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- if (cmd->DataMode == QSPI_DATA_NONE)
- {
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
- }
-
- /* Call the configuration function */
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- if (cmd->DataMode == QSPI_DATA_NONE)
- {
- /* When there is no data phase, the transfer start as soon as the configuration is done
- so activate TC and TE interrupts */
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI Transfer Error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
- }
- else
- {
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @param Timeout : Timeout duration
- * @note This function is used only in Indirect Write Mode
-
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = HAL_GetTick();
- __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- while(hqspi->TxXferCount > 0U)
- {
- /* Wait until FT flag is set to send data */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
-
- if (status != HAL_OK)
- {
- break;
- }
-
- *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
- hqspi->pTxBuffPtr++;
- hqspi->TxXferCount--;
- }
-
- if (status == HAL_OK)
- {
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Clear Transfer Complete bit */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Clear Busy bit */
- status = HAL_QSPI_Abort(hqspi);
- }
- }
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- return status;
-}
-
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @param Timeout : Timeout duration
- * @note This function is used only in Indirect Read Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = HAL_GetTick();
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
- __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pRxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- while(hqspi->RxXferCount > 0U)
- {
- /* Wait until FT or TC flag is set to read received data */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
-
- if (status != HAL_OK)
- {
- break;
- }
-
- *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
- hqspi->pRxBuffPtr++;
- hqspi->RxXferCount--;
- }
-
- if (status == HAL_OK)
- {
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Clear Transfer Complete bit */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */
- status = HAL_QSPI_Abort(hqspi);
- }
- }
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- return status;
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode with interrupt.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @note This function is used only in Indirect Write Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pTxBuffPtr = pData;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
- /* Configure QSPI: CCR register with functional as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @note This function is used only in Indirect Read Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pRxBuffPtr = pData;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode with DMA.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @note This function is used only in Indirect Write Mode
- * @note If DMA peripheral access is configured as halfword, the number
- * of data and the fifo threshold should be aligned on halfword
- * @note If DMA peripheral access is configured as word, the number
- * of data and the fifo threshold should be aligned on word
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Clear the error code */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Configure counters of the handle */
- if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
- {
- hqspi->TxXferCount = data_size;
- }
- else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
- {
- if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
- {
- /* The number of data or the fifo threshold is not aligned on halfword
- => no transfer possible with DMA peripheral access configured as halfword */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- else
- {
- hqspi->TxXferCount = (data_size >> 1U);
- }
- }
- else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
- {
- if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
- {
- /* The number of data or the fifo threshold is not aligned on word
- => no transfer possible with DMA peripheral access configured as word */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- else
- {
- hqspi->TxXferCount = (data_size >> 2U);
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- if (status == HAL_OK)
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
- /* Configure size and pointer of the handle */
- hqspi->TxXferSize = hqspi->TxXferCount;
- hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional mode as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
-
- /* Set the QSPI DMA Half transfer complete callback */
- hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-
- /* Clear the DMA abort callback */
- hqspi->hdma->XferAbortCallback = NULL;
-
-#if defined (QSPI1_V2_1L)
- /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
- AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
- Change the following configuration of DMA peripheral
- - Enable peripheral increment
- - Disable memory increment
- - Set DMA direction as peripheral to memory mode */
-
- /* Enable peripheral increment mode of the DMA */
- hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
-
- /* Disable memory increment mode of the DMA */
- hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
-
- /* Update peripheral/memory increment mode bits */
- MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
-
- /* Configure the direction of the DMA */
- hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-#else
- /* Configure the direction of the DMA */
- hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
-#endif /* QSPI1_V2_1L */
-
- /* Update direction mode bit */
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
- /* Enable the QSPI transmit DMA Channel */
- if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer.
- * @note This function is used only in Indirect Read Mode
- * @note If DMA peripheral access is configured as halfword, the number
- * of data and the fifo threshold should be aligned on halfword
- * @note If DMA peripheral access is configured as word, the number
- * of data and the fifo threshold should be aligned on word
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
- uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Clear the error code */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Configure counters of the handle */
- if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
- {
- hqspi->RxXferCount = data_size;
- }
- else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
- {
- if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
- {
- /* The number of data or the fifo threshold is not aligned on halfword
- => no transfer possible with DMA peripheral access configured as halfword */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- else
- {
- hqspi->RxXferCount = (data_size >> 1U);
- }
- }
- else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
- {
- if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
- {
- /* The number of data or the fifo threshold is not aligned on word
- => no transfer possible with DMA peripheral access configured as word */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- else
- {
- hqspi->RxXferCount = (data_size >> 2U);
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- if (status == HAL_OK)
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
- /* Configure size and pointer of the handle */
- hqspi->RxXferSize = hqspi->RxXferCount;
- hqspi->pRxBuffPtr = pData;
-
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
-
- /* Set the QSPI DMA Half transfer complete callback */
- hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-
- /* Clear the DMA abort callback */
- hqspi->hdma->XferAbortCallback = NULL;
-
-#if defined (QSPI1_V2_1L)
- /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
- AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
- Change the following configuration of DMA peripheral
- - Enable peripheral increment
- - Disable memory increment
- - Set DMA direction as memory to peripheral mode
- - 4 Extra words (32-bits) are added for read operation to guarantee
- the last data is transferred from DMA FIFO to RAM memory */
-
- /* Enable peripheral increment of the DMA */
- hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
-
- /* Disable memory increment of the DMA */
- hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
-
- /* Update peripheral/memory increment mode bits */
- MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
-
- /* Configure the direction of the DMA */
- hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
-
- /* 4 Extra words (32-bits) are needed for read operation to guarantee
- the last data is transferred from DMA FIFO to RAM memory */
- WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
-
- /* Update direction mode bit */
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- /* Enable the DMA Channel */
- if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
- {
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
- }
- else
- {
- status = HAL_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-#else
- /* Configure the direction of the DMA */
- hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-
- /* Update direction mode bit */
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
- /* Enable the DMA Channel */
- if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK)
- {
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-#endif /* QSPI1_V2_1L */
- }
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the polling configuration information.
- * @param Timeout : Timeout duration
- * @note This function is used only in Automatic Polling Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
-{
- HAL_StatusTypeDef status;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- assert_param(IS_QSPI_INTERVAL(cfg->Interval));
- assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
- assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Configure QSPI: PSMAR register with the status match value */
- WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
- /* Configure QSPI: PSMKR register with the status mask value */
- WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
- /* Configure QSPI: PIR register with the interval value */
- WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
- /* Configure QSPI: CR register with Match mode and Automatic stop enabled
- (otherwise there will be an infinite loop in blocking mode) */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
- (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
- /* Call the configuration function */
- cmd->NbData = cfg->StatusBytesSize;
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
- /* Wait until SM flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the polling configuration information.
- * @note This function is used only in Automatic Polling Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
-{
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- assert_param(IS_QSPI_INTERVAL(cfg->Interval));
- assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
- assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
- assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- /* Configure QSPI: PSMAR register with the status match value */
- WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
- /* Configure QSPI: PSMKR register with the status mask value */
- WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
- /* Configure QSPI: PIR register with the interval value */
- WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
- /* Configure QSPI: CR register with Match mode and Automatic stop mode */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
- (cfg->MatchMode | cfg->AutomaticStop));
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
- /* Call the configuration function */
- cmd->NbData = cfg->StatusBytesSize;
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI Transfer Error and status match Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Configure the Memory Mapped mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the memory mapped configuration information.
- * @note This function is used only in Memory mapped Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
-{
- HAL_StatusTypeDef status;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- /* Configure QSPI: CR register with timeout counter enable */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
-
- if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
- {
- assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
-
- /* Configure QSPI: LPTR register with the low-power timeout value */
- WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
-
- /* Enable the QSPI TimeOut Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
- }
-
- /* Call the configuration function */
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Transfer Error callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Abort completed callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_AbortCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Command completed callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_CmdCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FIFO Threshold callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Status Match callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_StatusMatchCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timeout callback.
- * @param hqspi : QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_TimeOutCallback could be implemented in the user file
- */
-}
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User QSPI Callback
- * To be used instead of the weak (surcharged) predefined callback
- * @param hqspi : QSPI handle
- * @param CallbackId : ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
- * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
- * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
- * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
- * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
- * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
- * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
- * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
- * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
- * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
- * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
- * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
- * @param pCallback : pointer to the Callback function
- * @retval status
- */
-HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(pCallback == NULL)
- {
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- switch (CallbackId)
- {
- case HAL_QSPI_ERROR_CB_ID :
- hqspi->ErrorCallback = pCallback;
- break;
- case HAL_QSPI_ABORT_CB_ID :
- hqspi->AbortCpltCallback = pCallback;
- break;
- case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
- hqspi->FifoThresholdCallback = pCallback;
- break;
- case HAL_QSPI_CMD_CPLT_CB_ID :
- hqspi->CmdCpltCallback = pCallback;
- break;
- case HAL_QSPI_RX_CPLT_CB_ID :
- hqspi->RxCpltCallback = pCallback;
- break;
- case HAL_QSPI_TX_CPLT_CB_ID :
- hqspi->TxCpltCallback = pCallback;
- break;
- case HAL_QSPI_RX_HALF_CPLT_CB_ID :
- hqspi->RxHalfCpltCallback = pCallback;
- break;
- case HAL_QSPI_TX_HALF_CPLT_CB_ID :
- hqspi->TxHalfCpltCallback = pCallback;
- break;
- case HAL_QSPI_STATUS_MATCH_CB_ID :
- hqspi->StatusMatchCallback = pCallback;
- break;
- case HAL_QSPI_TIMEOUT_CB_ID :
- hqspi->TimeOutCallback = pCallback;
- break;
- case HAL_QSPI_MSP_INIT_CB_ID :
- hqspi->MspInitCallback = pCallback;
- break;
- case HAL_QSPI_MSP_DEINIT_CB_ID :
- hqspi->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (hqspi->State == HAL_QSPI_STATE_RESET)
- {
- switch (CallbackId)
- {
- case HAL_QSPI_MSP_INIT_CB_ID :
- hqspi->MspInitCallback = pCallback;
- break;
- case HAL_QSPI_MSP_DEINIT_CB_ID :
- hqspi->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
- return status;
-}
-
-/**
- * @brief Unregister a User QSPI Callback
- * QSPI Callback is redirected to the weak (surcharged) predefined callback
- * @param hqspi : QSPI handle
- * @param CallbackId : ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
- * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
- * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
- * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
- * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
- * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
- * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
- * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
- * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
- * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
- * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
- * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
- * @retval status
- */
-HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- switch (CallbackId)
- {
- case HAL_QSPI_ERROR_CB_ID :
- hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
- break;
- case HAL_QSPI_ABORT_CB_ID :
- hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
- break;
- case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
- hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
- break;
- case HAL_QSPI_CMD_CPLT_CB_ID :
- hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
- break;
- case HAL_QSPI_RX_CPLT_CB_ID :
- hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
- break;
- case HAL_QSPI_TX_CPLT_CB_ID :
- hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
- break;
- case HAL_QSPI_RX_HALF_CPLT_CB_ID :
- hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
- break;
- case HAL_QSPI_TX_HALF_CPLT_CB_ID :
- hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
- break;
- case HAL_QSPI_STATUS_MATCH_CB_ID :
- hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
- break;
- case HAL_QSPI_TIMEOUT_CB_ID :
- hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
- break;
- case HAL_QSPI_MSP_INIT_CB_ID :
- hqspi->MspInitCallback = HAL_QSPI_MspInit;
- break;
- case HAL_QSPI_MSP_DEINIT_CB_ID :
- hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
- break;
- default :
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (hqspi->State == HAL_QSPI_STATE_RESET)
- {
- switch (CallbackId)
- {
- case HAL_QSPI_MSP_INIT_CB_ID :
- hqspi->MspInitCallback = HAL_QSPI_MspInit;
- break;
- case HAL_QSPI_MSP_DEINIT_CB_ID :
- hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
- break;
- default :
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
- return status;
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
- * @brief QSPI control and State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control and State functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to :
- (+) Check in run-time the state of the driver.
- (+) Check the error code set during last operation.
- (+) Abort any operation.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the QSPI handle state.
- * @param hqspi : QSPI handle
- * @retval HAL state
- */
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
-{
- /* Return QSPI handle state */
- return hqspi->State;
-}
-
-/**
-* @brief Return the QSPI error code.
-* @param hqspi : QSPI handle
-* @retval QSPI Error Code
-*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
-{
- return hqspi->ErrorCode;
-}
-
-/**
-* @brief Abort the current transmission.
-* @param hqspi : QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check if the state is in one of the busy states */
- if (((uint32_t)hqspi->State & 0x2U) != 0U)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort DMA channel */
- status = HAL_DMA_Abort(hqspi->hdma);
- if(status != HAL_OK)
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- }
- }
-
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Wait until BUSY flag is reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
- }
-
- if (status == HAL_OK)
- {
- /* Reset functional mode configuration to indirect write mode by default */
- CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
-
- return status;
-}
-
-/**
-* @brief Abort the current transmission (non-blocking function)
-* @param hqspi : QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check if the state is in one of the busy states */
- if (((uint32_t)hqspi->State & 0x2U) != 0U)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_ABORT;
-
- /* Disable all interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort DMA channel */
- hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
- if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
- {
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Abort Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->AbortCpltCallback(hqspi);
-#else
- HAL_QSPI_AbortCpltCallback(hqspi);
-#endif
- }
- }
- else
- {
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Enable the QSPI Transfer Complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
- }
- }
- return status;
-}
-
-/** @brief Set QSPI timeout.
- * @param hqspi : QSPI handle.
- * @param Timeout : Timeout for the QSPI memory access.
- * @retval None
- */
-void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
-{
- hqspi->Timeout = Timeout;
-}
-
-/** @brief Set QSPI Fifo threshold.
- * @param hqspi : QSPI handle.
- * @param Threshold : Threshold of the Fifo (value between 1 and 16).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Synchronize init structure with new FIFO threshold value */
- hqspi->Init.FifoThreshold = Threshold;
-
- /* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/** @brief Get QSPI Fifo threshold.
- * @param hqspi : QSPI handle.
- * @retval Fifo threshold (value between 1 and 16)
- */
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
-{
- return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
-}
-
-/** @brief Set FlashID.
- * @param hqspi : QSPI handle.
- * @param FlashID : Index of the flash memory to be accessed.
- * This parameter can be a value of @ref QSPI_Flash_Select.
- * @note The FlashID is ignored when dual flash mode is enabled.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameter */
- assert_param(IS_QSPI_FLASH_ID(FlashID));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Synchronize init structure with new FlashID value */
- hqspi->Init.FlashID = FlashID;
-
- /* Configure QSPI FlashID */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup QSPI_Private_Functions QSPI Private Functions
- * @{
- */
-
-/**
- * @brief DMA QSPI receive process complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
- hqspi->RxXferCount = 0U;
-
- /* Enable the QSPI transfer complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-}
-
-/**
- * @brief DMA QSPI transmit process complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
- hqspi->TxXferCount = 0U;
-
- /* Enable the QSPI transfer complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-}
-
-/**
- * @brief DMA QSPI receive process half complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->RxHalfCpltCallback(hqspi);
-#else
- HAL_QSPI_RxHalfCpltCallback(hqspi);
-#endif
-}
-
-/**
- * @brief DMA QSPI transmit process half complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->TxHalfCpltCallback(hqspi);
-#else
- HAL_QSPI_TxHalfCpltCallback(hqspi);
-#endif
-}
-
-/**
- * @brief DMA QSPI communication error callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
-
- /* if DMA error is FIFO error ignore it */
- if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
- {
- hqspi->RxXferCount = 0U;
- hqspi->TxXferCount = 0U;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort the QSPI */
- (void)HAL_QSPI_Abort_IT(hqspi);
-
- }
-}
-
-/**
- * @brief DMA QSPI abort complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
-{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
-
- hqspi->RxXferCount = 0U;
- hqspi->TxXferCount = 0U;
-
- if(hqspi->State == HAL_QSPI_STATE_ABORT)
- {
- /* DMA Abort called by QSPI abort */
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Enable the QSPI Transfer Complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
- }
- else
- {
- /* DMA Abort called due to a transfer error interrupt */
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
- hqspi->ErrorCallback(hqspi);
-#else
- HAL_QSPI_ErrorCallback(hqspi);
-#endif
- }
-}
-
-/**
- * @brief Wait for a flag state until timeout.
- * @param hqspi : QSPI handle
- * @param Flag : Flag checked
- * @param State : Value of the flag expected
- * @param Tickstart : Tick start value
- * @param Timeout : Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
- FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is in expected state */
- while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- {
- hqspi->State = HAL_QSPI_STATE_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Wait for a flag state until timeout using CPU cycle.
- * @param hqspi : QSPI handle
- * @param Flag : Flag checked
- * @param State : Value of the flag expected
- * @param Timeout : Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
-{
- __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U);
- do
- {
- if (count-- == 0U)
- {
- hqspi->State = HAL_QSPI_STATE_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the communication registers.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param FunctionalMode : functional mode to configured
- * This parameter can be one of the following values:
- * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
- * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
- * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
- * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
- * @retval None
- */
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
-{
- assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
-
- if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
- {
- /* Configure QSPI: DLR register with the number of data to read or write */
- WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
- }
-
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- /* Configure QSPI: ABR register with alternate bytes value */
- WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with instruction, address and alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
- cmd->Instruction | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with instruction and alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode |
- cmd->Instruction | FunctionalMode));
- }
- }
- else
- {
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with instruction and address ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with only instruction ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateByteMode | cmd->AddressMode |
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));
- }
- }
- }
- else
- {
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- /* Configure QSPI: ABR register with alternate bytes value */
- WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with address and alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode |
- cmd->InstructionMode | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with only alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
- }
- }
- else
- {
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with only address ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateByteMode | cmd->AddressSize |
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with only data phase ----*/
- if (cmd->DataMode != QSPI_DATA_NONE)
- {
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
- cmd->AlternateByteMode | cmd->AddressMode |
- cmd->InstructionMode | FunctionalMode));
- }
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_QSPI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(QUADSPI) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/