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fix:Format modification

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Signed-off-by: guodongqi <guodongqi2@huawei.com>
This commit is contained in:
guodongqi 2022-04-08 10:20:38 +08:00
parent a070af67ab
commit c9561b058f
13 changed files with 130 additions and 150 deletions
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2
sample/platform/uart/dev/hello_uart_dev.c
View File

@ -12,7 +12,7 @@
#include "hdf_log.h"
#define HDF_LOG_TAG hello_uart
#define INFO_SIZE 16
#define INFO_SIZE 16
int main(void)
{

2
sample/platform/uart/dispatch/hello_uart_dispatch.c
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@ -12,7 +12,7 @@
#include "uart_if.h"
#define HDF_LOG_TAG hello_uart_dispatch
#define UART_PORT 5
#define UART_PORT 5
int main(void)
{

2
sample/platform/uart/dispatch/uart_if.c
View File

@ -7,9 +7,9 @@
*/
#include "uart_if.h"
#include "hdf_io_service_if.h"
#include "hdf_log.h"
#include "osal_mem.h"
#include "hdf_io_service_if.h"
#define HDF_LOG_TAG uart_if

6
sample/platform/uart/dispatch/uart_if.h
View File

@ -12,11 +12,9 @@
#include <stdint.h>
#define UART_DEV_SERVICE_NAME_PREFIX "HDF_PLATFORM_UART_%d"
#define MAX_DEV_NAME_SIZE 32
#define MAX_DEV_NAME_SIZE 32
enum {
UART_WRITE = 1
};
enum { UART_WRITE = 1 };
struct DevHandle {
void *object;

3
sample/platform/uart/include/buf_fifo.h
View File

@ -9,8 +9,8 @@
#ifndef BUF_FIFO_H
#define BUF_FIFO_H
#include <stdint.h>
#include <stdbool.h>
#include <stdint.h>
struct BufferFifo {
volatile uint32_t readPosition;
@ -32,4 +32,3 @@ static inline bool IsPowerOfTwo(int num)
bool BufferFifoInit(struct BufferFifo *fifo, uint8_t *buf, uint16_t bufSize);
#endif // BUF_FIFO_H

2
sample/platform/uart/include/uart_dev_sample.h
View File

@ -18,7 +18,7 @@ extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define UART_IOC_MAGIC 'u'
#define UART_IOC_MAGIC 'u'
/* baudrate config */
#define UART_CFG_BAUDRATE _IO(UART_IOC_MAGIC, 1)

4
sample/platform/uart/include/uart_dispatch_sample.h
View File

@ -11,9 +11,7 @@
#include "uart_pl011_sample.h"
enum {
UART_WRITE = 1
};
enum { UART_WRITE = 1 };
int32_t SampleDispatch(struct HdfDeviceIoClient *client, int cmdId, struct HdfSBuf *data, struct HdfSBuf *reply);

218
sample/platform/uart/include/uart_pl011_sample.h
View File

@ -19,36 +19,36 @@ extern "C" {
#endif
struct UartRegisterMap {
volatile uint32_t dr; /* Offset: 0x000 TYPE: (RW) Data register */
volatile uint32_t dr; /* Offset: 0x000 TYPE: (RW) Data register */
union {
volatile uint32_t rsr; /* Offset: 0x004 TYPE: (RO) Receive status register */
volatile uint32_t ecr; /* Offset: 0x004 TYPE: (WO) Error clear register */
volatile uint32_t rsr; /* Offset: 0x004 TYPE: (RO) Receive status register */
volatile uint32_t ecr; /* Offset: 0x004 TYPE: (WO) Error clear register */
};
volatile uint32_t reserved0[4]; /* Offset: 0x008-0x014 Reserved */
volatile uint32_t fr; /* Offset: 0x018 TYPE: (RO) Flag register */
volatile uint32_t reserved1; /* Offset: 0x01C Reserved */
volatile uint32_t ilpr; /* Offset: 0x020 TYPE: (RW) IrDA low-power counter register */
volatile uint32_t ibrd; /* Offset: 0x024 TYPE: (RW) Integer baud rate register */
volatile uint32_t fbrd; /* Offset: 0x028 TYPE: (RW) Fractional baud rate register */
volatile uint32_t lcr; /* Offset: 0x02C TYPE: (RW) Line control register */
volatile uint32_t cr; /* Offset: 0x030 TYPE: (RW) Control register */
volatile uint32_t ifls; /* Offset: 0x034 TYPE: (RW) Interrupt FIFO level select register */
volatile uint32_t imsc; /* Offset: 0x038 TYPE: (RW) Interrupt mask set/clear register */
volatile uint32_t ris; /* Offset: 0x03C TYPE: (RO) Raw interrupt status register */
volatile uint32_t mis; /* Offset: 0x040 TYPE: (RO) Masked interrupt status register */
volatile uint32_t icr; /* Offset: 0x044 TYPE: (WO) Interrupt clear register */
volatile uint32_t dmacr; /* Offset: 0x048 TYPE: (RW) DMA control register */
volatile uint32_t reserved0[4]; /* Offset: 0x008-0x014 Reserved */
volatile uint32_t fr; /* Offset: 0x018 TYPE: (RO) Flag register */
volatile uint32_t reserved1; /* Offset: 0x01C Reserved */
volatile uint32_t ilpr; /* Offset: 0x020 TYPE: (RW) IrDA low-power counter register */
volatile uint32_t ibrd; /* Offset: 0x024 TYPE: (RW) Integer baud rate register */
volatile uint32_t fbrd; /* Offset: 0x028 TYPE: (RW) Fractional baud rate register */
volatile uint32_t lcr; /* Offset: 0x02C TYPE: (RW) Line control register */
volatile uint32_t cr; /* Offset: 0x030 TYPE: (RW) Control register */
volatile uint32_t ifls; /* Offset: 0x034 TYPE: (RW) Interrupt FIFO level select register */
volatile uint32_t imsc; /* Offset: 0x038 TYPE: (RW) Interrupt mask set/clear register */
volatile uint32_t ris; /* Offset: 0x03C TYPE: (RO) Raw interrupt status register */
volatile uint32_t mis; /* Offset: 0x040 TYPE: (RO) Masked interrupt status register */
volatile uint32_t icr; /* Offset: 0x044 TYPE: (WO) Interrupt clear register */
volatile uint32_t dmacr; /* Offset: 0x048 TYPE: (RW) DMA control register */
};
struct UartResource {
uint32_t num; /* UART port num */
uint32_t base; /* UART PL011 base address */
uint32_t irqNum; /* UART PL011 IRQ num */
uint32_t baudrate; /* Default baudrate */
uint32_t wlen; /* Default word length */
uint32_t parity; /* Default parity */
uint32_t stopBit; /* Default stop bits */
uint32_t uartClk; /* UART clock */
uint32_t num; /* UART port num */
uint32_t base; /* UART PL011 base address */
uint32_t irqNum; /* UART PL011 IRQ num */
uint32_t baudrate; /* Default baudrate */
uint32_t wlen; /* Default word length */
uint32_t parity; /* Default parity */
uint32_t stopBit; /* Default stop bits */
uint32_t uartClk; /* UART clock */
unsigned long physBase;
};
@ -60,126 +60,115 @@ enum UartDeviceState {
struct UartDevice {
struct IDeviceIoService ioService;
struct UartResource resource;
enum UartDeviceState state; /* UART State */
uint32_t uartClk; /* UART clock */
uint32_t baudrate; /* Baudrate */
enum UartDeviceState state; /* UART State */
uint32_t uartClk; /* UART clock */
uint32_t baudrate; /* Baudrate */
struct BufferFifo rxFifo;
};
/* Receive Status Register/Error Clear Register data */
#define UART_PL011_RSR_FRAMING_ERROR_MASK (1 << 0x0u) /* Framing error bit mask */
#define UART_PL011_RSR_PARITY_ERROR_MASK (1 << 0x1u) /* Parity error bit mask */
#define UART_PL011_RSR_BREAK_ERROR_MASK (1 << 0x2u) /* Break error bit mask */
#define UART_PL011_RSR_OVERRUN_ERROR_MASK (1 << 0x3u) /* Overrun error bit mask */
#define UART_PL011_RSR_FRAMING_ERROR_MASK (1 << 0x0u) /* Framing error bit mask */
#define UART_PL011_RSR_PARITY_ERROR_MASK (1 << 0x1u) /* Parity error bit mask */
#define UART_PL011_RSR_BREAK_ERROR_MASK (1 << 0x2u) /* Break error bit mask */
#define UART_PL011_RSR_OVERRUN_ERROR_MASK (1 << 0x3u) /* Overrun error bit mask */
/* Receive Status Register Error Mask */
#define UART_PL011_RSR_RX_ERROR_MASK ( \
UART_PL011_RSR_FRAMING_ERROR_MASK \
| UART_PL011_RSR_PARITY_ERROR_MASK \
| UART_PL011_RSR_BREAK_ERROR_MASK \
| UART_PL011_RSR_OVERRUN_ERROR_MASK)
#define UART_PL011_RSR_RX_ERROR_MASK \
(UART_PL011_RSR_FRAMING_ERROR_MASK | UART_PL011_RSR_PARITY_ERROR_MASK | UART_PL011_RSR_BREAK_ERROR_MASK | \
UART_PL011_RSR_OVERRUN_ERROR_MASK)
#define UART_PL011_FR_CTS_MASK (1 << 0x0u) /* Clear to send bit mask */
#define UART_PL011_FR_DSR_MASK (1 << 0x1u) /* Data set ready bit mask */
#define UART_PL011_FR_DCD_MASK (1 << 0x2u) /* Data carrier detect bit mask */
#define UART_PL011_FR_BUSY_MASK (1 << 0x3u) /* UART busy bit mask */
#define UART_PL011_FR_RX_FIFO_EMPTY_MASK (1 << 0x4u) /* Receive FIFO empty bit mask */
#define UART_PL011_FR_TX_FIFO_FULL_MASK (1 << 0x5u) /* Transmit FIFO full bit mask */
#define UART_PL011_FR_RX_FIFO_FULL_MASK (1 << 0x6u) /* Receive FIFO full bit mask */
#define UART_PL011_FR_TX_FIFO_EMPTY_MASK (1 << 0x7u) /* Transmit FIFO empty. bit mask */
#define UART_PL011_FR_RI_MASK (1 << 0x8u) /* Ring indicator bit mask */
#define UART_PL011_FR_CTS_MASK (1 << 0x0u) /* Clear to send bit mask */
#define UART_PL011_FR_DSR_MASK (1 << 0x1u) /* Data set ready bit mask */
#define UART_PL011_FR_DCD_MASK (1 << 0x2u) /* Data carrier detect bit mask */
#define UART_PL011_FR_BUSY_MASK (1 << 0x3u) /* UART busy bit mask */
#define UART_PL011_FR_RX_FIFO_EMPTY_MASK (1 << 0x4u) /* Receive FIFO empty bit mask */
#define UART_PL011_FR_TX_FIFO_FULL_MASK (1 << 0x5u) /* Transmit FIFO full bit mask */
#define UART_PL011_FR_RX_FIFO_FULL_MASK (1 << 0x6u) /* Receive FIFO full bit mask */
#define UART_PL011_FR_TX_FIFO_EMPTY_MASK (1 << 0x7u) /* Transmit FIFO empty. bit mask */
#define UART_PL011_FR_RI_MASK (1 << 0x8u) /* Ring indicator bit mask */
/* PL011 Line Control Register Data bits */
#define UART_PL011_LCR_H_BRK_MASK (1 << 0x0u) /* Send Break bit mask */
#define UART_PL011_LCR_H_PEN_MASK (1 << 0x1u) /* Parity enable bit mask */
#define UART_PL011_LCR_H_EPS_MASK (1 << 0x2u) /* Even parity select bit mask . */
#define UART_PL011_LCR_H_FEN_MASK (1 << 0x4u) /* Enable FIFOs bit mask */
#define UART_PL011_LCR_H_SPS_MASK (1 << 0x7u) /* Stick parity select bit mask */
#define UART_PL011_LCR_H_BRK_MASK (1 << 0x0u) /* Send Break bit mask */
#define UART_PL011_LCR_H_PEN_MASK (1 << 0x1u) /* Parity enable bit mask */
#define UART_PL011_LCR_H_EPS_MASK (1 << 0x2u) /* Even parity select bit mask . */
#define UART_PL011_LCR_H_FEN_MASK (1 << 0x4u) /* Enable FIFOs bit mask */
#define UART_PL011_LCR_H_SPS_MASK (1 << 0x7u) /* Stick parity select bit mask */
#define UART_PL011_LCR_H_WLEN_BIT_OFFSET 0x5u /* Word length bit offset */
#define UART_PL011_LCR_H_WLEN_MASK ( \
0x3u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_LCR_H_WLEN_BIT_OFFSET 0x5u /* Word length bit offset */
#define UART_PL011_LCR_H_WLEN_MASK (0x3u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_5BITS (0x0u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_6BITS (0x1u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_7BITS (0x2u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_8BITS (0x3u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_5BITS (0x0u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_6BITS (0x1u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_7BITS (0x2u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_WLEN_8BITS (0x3u << UART_PL011_LCR_H_WLEN_BIT_OFFSET)
#define UART_PL011_NONE_PARITY_CHECKED 0
#define UART_PL011_NONE_PARITY_CHECKED 0
#define UART_PL011_LCR_H_STP2_BIT_OFFSET 0x3u /* Two stop bits select */
#define UART_PL011_LCR_H_STP2_BIT_OFFSET 0x3u /* Two stop bits select */
#define UART_PL011_STOPBIT_1 (0x0u << UART_PL011_LCR_H_STP2_BIT_OFFSET)
#define UART_PL011_STOPBIT_2 (0x1u << UART_PL011_LCR_H_STP2_BIT_OFFSET)
#define UART_PL011_STOPBIT_1 (0x0u << UART_PL011_LCR_H_STP2_BIT_OFFSET)
#define UART_PL011_STOPBIT_2 (0x1u << UART_PL011_LCR_H_STP2_BIT_OFFSET)
#define UART_PL011_LCR_H_PARITY_MASK ( \
UART_PL011_LCR_H_PEN_MASK \
| UART_PL011_LCR_H_EPS_MASK \
| UART_PL011_LCR_H_SPS_MASK)
#define UART_PL011_LCR_H_PARITY_MASK (UART_PL011_LCR_H_PEN_MASK | UART_PL011_LCR_H_EPS_MASK | UART_PL011_LCR_H_SPS_MASK)
#define UART_PL011_LCR_H_STOPBIT_MASK (0x1u << UART_PL011_LCR_H_STP2_BIT_OFFSET)
#define UART_PL011_LCR_H_STOPBIT_MASK (0x1u << UART_PL011_LCR_H_STP2_BIT_OFFSET)
#define UART_PL011_DATA_FORMAT_MASK ( \
UART_PL011_LCR_H_PARITY_MASK \
| UART_PL011_LCR_H_STOPBIT_MASK \
| UART_PL011_LCR_H_WLEN_MASK)
#define UART_PL011_DATA_FORMAT_MASK \
(UART_PL011_LCR_H_PARITY_MASK | UART_PL011_LCR_H_STOPBIT_MASK | UART_PL011_LCR_H_WLEN_MASK)
/* Control Register */
#define UART_PL011_CR_UARTEN_MASK (0x1u << 0x0u) /* Uart enable bit mask */
#define UART_PL011_CR_SIREN_MASK (0x1u << 0x1u) /* Sir enable bit mask */
#define UART_PL011_CR_SIRLP_MASK (0x1u << 0x2u) /* SIR low-power IrDA mode bit mask */
#define UART_PL011_CR_LBE_MASK (0x1u << 0x7u) /* Loopback enable bit mask */
#define UART_PL011_CR_TXE_MASK (0x1u << 0x8u) /* Transmit enable bit mask */
#define UART_PL011_CR_RXE_MASK (0x1u << 0x9u) /* Receive enable bit mask */
#define UART_PL011_CR_DTR_MASK (0x1u << 0xAu) /* Data transmit ready.bit mask */
#define UART_PL011_CR_RTS_MASK (0x1u << 0xBu) /* Request to send bit mask */
#define UART_PL011_CR_OUT1_MASK (0x1u << 0xCu) /* Out1 bit field mask */
#define UART_PL011_CR_OUT2_MASK (0x1u << 0xDu) /* Out2 bit field mask */
#define UART_PL011_CR_RTSE_MASK (0x1u << 0xEu) /* RTS hardware flow control enable bit mask */
#define UART_PL011_CR_CTSE_MASK (0x1u << 0xFu) /* CTS hardware flow control enable bit mask */
#define UART_PL011_CR_UARTEN_MASK (0x1u << 0x0u) /* Uart enable bit mask */
#define UART_PL011_CR_SIREN_MASK (0x1u << 0x1u) /* Sir enable bit mask */
#define UART_PL011_CR_SIRLP_MASK (0x1u << 0x2u) /* SIR low-power IrDA mode bit mask */
#define UART_PL011_CR_LBE_MASK (0x1u << 0x7u) /* Loopback enable bit mask */
#define UART_PL011_CR_TXE_MASK (0x1u << 0x8u) /* Transmit enable bit mask */
#define UART_PL011_CR_RXE_MASK (0x1u << 0x9u) /* Receive enable bit mask */
#define UART_PL011_CR_DTR_MASK (0x1u << 0xAu) /* Data transmit ready.bit mask */
#define UART_PL011_CR_RTS_MASK (0x1u << 0xBu) /* Request to send bit mask */
#define UART_PL011_CR_OUT1_MASK (0x1u << 0xCu) /* Out1 bit field mask */
#define UART_PL011_CR_OUT2_MASK (0x1u << 0xDu) /* Out2 bit field mask */
#define UART_PL011_CR_RTSE_MASK (0x1u << 0xEu) /* RTS hardware flow control enable bit mask */
#define UART_PL011_CR_CTSE_MASK (0x1u << 0xFu) /* CTS hardware flow control enable bit mask */
/* Interrupt FIFO Level Select Register Transmit bit offset */
#define UART_PL011_IFLS_TX_BIT_OFFSET 0x0u
#define UART_PL011_IFLS_TX_BIT_OFFSET 0x0u
/* Interrupt FIFO Level Select Register Receive bit offset */
#define UART_PL011_IFLS_RX_BIT_OFFSET 0x3u
#define UART_PL011_IFLS_RX_BIT_OFFSET 0x3u
#define UART_PL011_RX_FIFO_LVL_1_8 (0x0u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_1_4 (0x1u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_1_2 (0x2u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_3_4 (0x3u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_7_8 (0x4u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_1_8 (0x0u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_1_4 (0x1u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_1_2 (0x2u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_3_4 (0x3u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_RX_FIFO_LVL_7_8 (0x4u << UART_PL011_IFLS_RX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_1_8 (0x0u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_1_4 (0x1u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_1_2 (0x2u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_3_4 (0x3u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_7_8 (0x4u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_1_8 (0x0u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_1_4 (0x1u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_1_2 (0x2u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_3_4 (0x3u << UART_PL011_IFLS_TX_BIT_OFFSET)
#define UART_PL011_TX_FIFO_LVL_7_8 (0x4u << UART_PL011_IFLS_TX_BIT_OFFSET)
/* Default register values of UART PL011 */
#define UART_PL011_DEFAULT_DATA_REG_VALUE (0x0u)
#define UART_PL011_DEFAULT_ECR_VALUE (0xFFu)
#define UART_PL011_DEFAULT_ILPR_VALUE (0x0u)
#define UART_PL011_DEFAULT_IBRD_REG_VALUE (0x0u)
#define UART_PL011_DEFAULT_FBRD_REG_VALUE (0x0u)
#define UART_PL011_DEFAULT_DATA_REG_VALUE (0x0u)
#define UART_PL011_DEFAULT_ECR_VALUE (0xFFu)
#define UART_PL011_DEFAULT_ILPR_VALUE (0x0u)
#define UART_PL011_DEFAULT_IBRD_REG_VALUE (0x0u)
#define UART_PL011_DEFAULT_FBRD_REG_VALUE (0x0u)
/* Clear UARTLCR */
#define UART_PL011_DEFAULT_LCR_H_VALUE (0x0u)
#define UART_PL011_DEFAULT_CTRL_REG_VALUE (0x0300u)
#define UART_PL011_DEFAULT_LCR_H_VALUE (0x0u)
#define UART_PL011_DEFAULT_CTRL_REG_VALUE (0x0300u)
#define UART_PL011_DEFAULT_IFLS_REG_VALUE ( \
UART_PL011_RX_FIFO_LVL_1_2 \
| UART_PL011_TX_FIFO_LVL_7_8)
#define UART_PL011_DEFAULT_IFLS_REG_VALUE (UART_PL011_RX_FIFO_LVL_1_2 | UART_PL011_TX_FIFO_LVL_7_8)
/* Clear interrupt mask */
#define UART_PL011_DEFAULT_IMSC_REG_VALUE (0x0u)
#define UART_PL011_DEFAULT_IMSC_REG_VALUE (0x0u)
/* Clear interrupt */
#define UART_PL011_DEFAULT_ICR_VALUE (0x7FFu)
#define UART_PL011_DEFAULT_DMACR_VALUE (0x0u)
#define UART_PL011_DEFAULT_ICR_VALUE (0x7FFu)
#define UART_PL011_DEFAULT_DMACR_VALUE (0x0u)
#define FREQ_IRLPBAUD16_MIN (1420000u) /* 1.42 MHz */
#define FREQ_IRLPBAUD16_MAX (2120000u) /* 2.12 MHz */
#define SAMPLING_FACTOR (16u)
#define UART_PL011_FBRD_WIDTH (6u)
#define FREQ_IRLPBAUD16_MIN (1420000u) /* 1.42 MHz */
#define FREQ_IRLPBAUD16_MAX (2120000u) /* 2.12 MHz */
#define SAMPLING_FACTOR (16u)
#define UART_PL011_FBRD_WIDTH (6u)
/**
* \brief ARM UART PL011 error enumeration types
@ -220,7 +209,7 @@ void UartPl011SetLcrBits(struct UartRegisterMap *regMap, uint32_t bits);
static inline void UartPl011Write(struct UartRegisterMap *regMap, uint8_t byte)
{
while (UartPl011IsBusy(regMap)) { }
while (UartPl011IsBusy(regMap)) {}
regMap->dr = byte;
}
@ -239,4 +228,3 @@ static inline void UartPl011EnableFifo(struct UartRegisterMap *regMap)
}
#endif
#endif /* UART_PL011_SAMPLE_H */

2
sample/platform/uart/src/buf_fifo.c
View File

@ -10,7 +10,7 @@
bool BufferFifoInit(struct BufferFifo *fifo, uint8_t *fifoBuffer, uint16_t fifoSize)
{
if (fifoBuffer == NULL) {
if (fifoBuffer == NULL || fifo == NULL) {
return false;
}
if (!IsPowerOfTwo(fifoSize)) {

19
sample/platform/uart/src/uart_dev_sample.c
View File

@ -8,13 +8,13 @@
#include "uart_dev_sample.h"
#include "fs/fs.h"
#include "securec.h"
#include "user_copy.h"
#include "hdf_log.h"
#include "osal_mem.h"
#include "securec.h"
#include "uart_pl011_sample.h"
#include "user_copy.h"
#define HDF_LOG_TAG uart_dev_sample
#define HDF_LOG_TAG uart_dev_sample
#define HDF_UART_FS_MODE 0660
static int32_t UartSampleDevOpen(struct file *filep)
@ -33,6 +33,7 @@ static int32_t UartSampleDevOpen(struct file *filep)
HDF_LOGI("%s: open uart%d success", __func__, host->num);
return HDF_SUCCESS;
}
static int32_t UartSampleRelease(struct file *filep)
{
struct UartHost *host = NULL;
@ -122,7 +123,7 @@ static int32_t UartSampleDevIoctl(struct file *filep, int32_t cmd, unsigned long
if (host->priv == NULL) {
return HDF_ERR_INVALID_PARAM;
}
ret = HDF_FAILURE;
switch (cmd) {
case UART_CFG_BAUDRATE:
@ -137,11 +138,11 @@ static int32_t UartSampleDevIoctl(struct file *filep, int32_t cmd, unsigned long
}
const struct file_operations_vfs g_uartSampleDevFops = {
.open = UartSampleDevOpen,
.close = UartSampleRelease,
.read = UartSampleRead,
.write = UartSampleWrite,
.ioctl = UartSampleDevIoctl,
.open = UartSampleDevOpen,
.close = UartSampleRelease,
.read = UartSampleRead,
.write = UartSampleWrite,
.ioctl = UartSampleDevIoctl,
};
#define MAX_DEV_NAME_SIZE 32

4
sample/platform/uart/src/uart_pl011_sample.c
View File

@ -54,8 +54,7 @@ UartPl011Error UartPl011SetBaudrate(struct UartRegisterMap *regMap, uint32_t clk
return UART_PL011_ERR_NONE;
}
void UartPl011SetDataFormat(
struct UartRegisterMap *regMap, uint32_t wordLen, uint32_t parity, uint32_t stopBits)
void UartPl011SetDataFormat(struct UartRegisterMap *regMap, uint32_t wordLen, uint32_t parity, uint32_t stopBits)
{
bool uartEnabled = UartPl011IsEnabled(regMap);
uint32_t lcr = regMap->lcr & (~UART_PL011_DATA_FORMAT_MASK);
@ -87,4 +86,3 @@ void UartPl011ResetRegisters(struct UartRegisterMap *regMap)
regMap->icr = UART_PL011_DEFAULT_ICR_VALUE;
regMap->dmacr = UART_PL011_DEFAULT_DMACR_VALUE;
}

9
sample/platform/uart/src/uart_sample.c
View File

@ -6,8 +6,8 @@
* See the LICENSE file in the root of this repository for complete details.
*/
#include "device_resource_if.h"
#include "buf_fifo.h"
#include "device_resource_if.h"
#include "hdf_device_desc.h"
#include "hdf_log.h"
#include "hisoc/uart.h"
@ -18,7 +18,7 @@
#include "uart_dispatch_sample.h"
#include "uart_pl011_sample.h"
#define HDF_LOG_TAG uart_sample
#define HDF_LOG_TAG uart_sample
#define UART_RX_FIFO_SIZE 128
static uint8_t g_fifoBuffer[UART_RX_FIFO_SIZE] = {0};
@ -180,8 +180,7 @@ static int InitUartDevice(struct UartDevice *device)
return HDF_SUCCESS;
}
static uint32_t GetUartDeviceResource(
struct UartDevice *device, const struct DeviceResourceNode *resourceNode)
static uint32_t GetUartDeviceResource(struct UartDevice *device, const struct DeviceResourceNode *resourceNode)
{
struct UartResource *resource = &device->resource;
struct DeviceResourceIface *dri = NULL;
@ -259,7 +258,7 @@ static void DeinitUartDevice(struct UartDevice *device)
{
struct UartRegisterMap *regMap = (struct UartRegisterMap *)device->resource.physBase;
/* wait for uart enter idle. */
while (UartPl011IsBusy(regMap)) { }
while (UartPl011IsBusy(regMap)) {}
UartPl011ResetRegisters(regMap);
uart_clk_cfg(0, false);
OsalIoUnmap((void *)device->resource.physBase);

7
tools/hc-gen/src/startup_cfg_gen.cpp
View File

@ -214,11 +214,10 @@ void StartupCfgGen::GetHostCaps(const std::shared_ptr<AstObject> &capsTerm, Host
void StartupCfgGen::GetHostLoadMode(const std::shared_ptr<AstObject> &hostInfo, HostInfo &hostData)
{
uint32_t preload;
std::shared_ptr<AstObject> devInfo = nullptr;
std::shared_ptr<AstObject> current = nullptr;
std::shared_ptr<AstObject> devNodeInfo = nullptr;
devInfo = hostInfo->Child();
std::shared_ptr<AstObject> devInfo = hostInfo->Child();
while (devInfo != nullptr) {
if (!devInfo->IsNode()) {
devInfo = devInfo->Next();
@ -271,13 +270,13 @@ bool StartupCfgGen::GetHostInfo()
hostData.hostUID = serviceName;
object = hostInfo->Lookup("uid", PARSEROP_CONFTERM);
if (object != nullptr && object->Child()->StringValue() != "") {
if (object != nullptr && !object->Child()->StringValue().empty()) {
hostData.hostUID = object->Child()->StringValue();
}
hostData.hostGID = serviceName;
object = hostInfo->Lookup("gid", PARSEROP_CONFTERM);
if (object != nullptr && object->Child()->StringValue() != "") {
if (object != nullptr && !object->Child()->StringValue().empty()) {
hostData.hostGID = object->Child()->StringValue();
}
object = hostInfo->Lookup("caps", PARSEROP_CONFTERM);