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https://gitee.com/openharmony/kernel_linux
synced 2024-12-14 02:12:17 +00:00
[ALSA] Remove snd_vx_delay() function
Replace snd_vx_delay() with appropriate delay/sleep functions. Signed-off-by: Takashi Iwai <tiwai@suse.de>
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c8eb6ba16a
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@ -274,8 +274,6 @@ static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
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#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
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#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
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void snd_vx_delay(vx_core_t *chip, int msec);
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static inline void vx_reset_dsp(vx_core_t *chip)
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{
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snd_assert(chip->ops->reset_dsp, return);
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@ -40,18 +40,6 @@ MODULE_DESCRIPTION("Common routines for Digigram VX drivers");
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MODULE_LICENSE("GPL");
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/*
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* snd_vx_delay - delay for the specified time
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* @xmsec: the time to delay in msec
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*/
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void snd_vx_delay(vx_core_t *chip, int xmsec)
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{
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if (! in_interrupt() && xmsec >= 1000 / HZ)
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msleep(xmsec);
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else
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mdelay(xmsec);
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}
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/*
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* vx_check_reg_bit - wait for the specified bit is set/reset on a register
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* @reg: register to check
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@ -76,7 +64,7 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time)
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do {
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if ((snd_vx_inb(chip, reg) & mask) == bit)
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return 0;
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//snd_vx_delay(chip, 10);
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//msleep(10);
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} while (time_after_eq(end_time, jiffies));
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snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg));
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return -EIO;
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@ -664,7 +652,7 @@ int snd_vx_dsp_boot(vx_core_t *chip, const struct firmware *boot)
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if ((err = snd_vx_load_boot_image(chip, boot)) < 0)
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return err;
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snd_vx_delay(chip, 10);
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msleep(10);
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return 0;
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}
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@ -704,7 +692,7 @@ int snd_vx_dsp_load(vx_core_t *chip, const struct firmware *dsp)
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}
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snd_printdd(KERN_DEBUG "checksum = 0x%08x\n", csum);
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snd_vx_delay(chip, 200);
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msleep(200);
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if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
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return err;
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@ -831,7 +819,6 @@ EXPORT_SYMBOL(snd_vx_create);
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EXPORT_SYMBOL(snd_vx_setup_firmware);
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EXPORT_SYMBOL(snd_vx_free_firmware);
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EXPORT_SYMBOL(snd_vx_irq_handler);
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EXPORT_SYMBOL(snd_vx_delay);
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EXPORT_SYMBOL(snd_vx_dsp_boot);
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EXPORT_SYMBOL(snd_vx_dsp_load);
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EXPORT_SYMBOL(snd_vx_load_boot_image);
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@ -154,7 +154,7 @@ static void vx2_reset_dsp(vx_core_t *_chip)
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/* set the reset dsp bit to 0 */
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vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
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snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME);
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mdelay(XX_DSP_RESET_WAIT_TIME);
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chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
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/* set the reset dsp bit to 1 */
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@ -362,10 +362,10 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
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/* XILINX reset (wait at least 1 milisecond between reset on and off). */
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
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vx_inl(chip, CNTRL);
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snd_vx_delay(chip, 10);
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msleep(10);
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
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vx_inl(chip, CNTRL);
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snd_vx_delay(chip, 10);
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msleep(10);
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if (chip->type == VX_TYPE_BOARD)
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port = VX_CNTRL;
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@ -381,7 +381,7 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
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}
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put_xilinx_data(chip, port, 4, 0xff); /* end signature */
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snd_vx_delay(chip, 200);
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msleep(200);
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/* test after loading (is buggy with VX222) */
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if (chip->type != VX_TYPE_BOARD) {
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@ -720,17 +720,17 @@ static void vx2_reset_codec(vx_core_t *_chip)
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/* Set the reset CODEC bit to 0. */
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vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
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vx_inl(chip, CDSP);
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snd_vx_delay(_chip, 10);
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msleep(10);
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/* Set the reset CODEC bit to 1. */
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chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
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vx_outl(chip, CDSP, chip->regCDSP);
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vx_inl(chip, CDSP);
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if (_chip->type == VX_TYPE_BOARD) {
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snd_vx_delay(_chip, 1);
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msleep(1);
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return;
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}
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snd_vx_delay(_chip, 5); /* additionnel wait time for AKM's */
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msleep(5); /* additionnel wait time for AKM's */
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vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
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@ -96,7 +96,7 @@ static int vx_check_magic(vx_core_t *chip)
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c = vx_inb(chip, CDSP);
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if (c == CDSP_MAGIC)
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return 0;
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snd_vx_delay(chip, 10);
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msleep(10);
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} while (time_after_eq(end_time, jiffies));
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snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
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return -EIO;
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@ -134,12 +134,12 @@ static void vxp_reset_codec(vx_core_t *_chip)
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/* Set the reset CODEC bit to 1. */
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vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
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vx_inb(chip, CDSP);
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snd_vx_delay(_chip, 10);
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msleep(10);
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/* Set the reset CODEC bit to 0. */
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chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
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vx_outb(chip, CDSP, chip->regCDSP);
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vx_inb(chip, CDSP);
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snd_vx_delay(_chip, 1);
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msleep(1);
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}
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/*
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@ -207,7 +207,7 @@ static int vxp_load_xilinx_binary(vx_core_t *_chip, const struct firmware *fw)
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vx_outb(chip, ICR, ICR_HF0);
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/* TEMPO 250ms : wait until Xilinx is downloaded */
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snd_vx_delay(_chip, 300);
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msleep(300);
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/* test magical word */
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if (vx_check_magic(_chip) < 0)
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@ -221,7 +221,7 @@ static int vxp_load_xilinx_binary(vx_core_t *_chip, const struct firmware *fw)
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chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
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vx_outb(chip, DIALOG, chip->regDIALOG);
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vx_inb(chip, DIALOG);
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snd_vx_delay(_chip, 10);
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msleep(10);
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chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
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vx_outb(chip, DIALOG, chip->regDIALOG);
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vx_inb(chip, DIALOG);
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