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[POWERPC] Add arch/powerpc driver for UIC, PPC4xx interrupt controller
This patch adds a driver to arch/powerpc/sysdev for the UIC, the on-chip interrupt controller from IBM/AMCC 4xx chips. It uses the new irq host mapping infrastructure. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson
Paul Mackerras
parent
f65573314e
commit
e58923ed14
@ -21,6 +21,7 @@ obj-$(CONFIG_PM) += timer.o
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ifeq ($(CONFIG_PPC_MERGE),y)
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obj-$(CONFIG_PPC_I8259) += i8259.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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obj-$(CONFIG_4xx) += uic.o
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endif
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# Temporary hack until we have migrated to asm-powerpc
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342
arch/powerpc/sysdev/uic.c
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342
arch/powerpc/sysdev/uic.c
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@ -0,0 +1,342 @@
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/*
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* arch/powerpc/sysdev/uic.c
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*
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* IBM PowerPC 4xx Universal Interrupt Controller
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*
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* Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/sysdev.h>
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#include <linux/device.h>
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#include <linux/bootmem.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/dcr.h>
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#define NR_UIC_INTS 32
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#define UIC_SR 0x0
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#define UIC_ER 0x2
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#define UIC_CR 0x3
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#define UIC_PR 0x4
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#define UIC_TR 0x5
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#define UIC_MSR 0x6
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#define UIC_VR 0x7
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#define UIC_VCR 0x8
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#define uic_irq_to_hw(virq) (irq_map[virq].hwirq)
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struct uic *primary_uic;
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struct uic {
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int index;
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int dcrbase;
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spinlock_t lock;
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/* The remapper for this UIC */
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struct irq_host *irqhost;
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/* For secondary UICs, the cascade interrupt's irqaction */
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struct irqaction cascade;
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/* The device node of the interrupt controller */
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struct device_node *of_node;
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};
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static void uic_unmask_irq(unsigned int virq)
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{
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struct uic *uic = get_irq_chip_data(virq);
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unsigned int src = uic_irq_to_hw(virq);
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unsigned long flags;
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u32 er;
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spin_lock_irqsave(&uic->lock, flags);
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er = mfdcr(uic->dcrbase + UIC_ER);
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er |= 1 << (31 - src);
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mtdcr(uic->dcrbase + UIC_ER, er);
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spin_unlock_irqrestore(&uic->lock, flags);
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}
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static void uic_mask_irq(unsigned int virq)
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{
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struct uic *uic = get_irq_chip_data(virq);
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unsigned int src = uic_irq_to_hw(virq);
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unsigned long flags;
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u32 er;
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spin_lock_irqsave(&uic->lock, flags);
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er = mfdcr(uic->dcrbase + UIC_ER);
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er &= ~(1 << (31 - src));
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mtdcr(uic->dcrbase + UIC_ER, er);
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spin_unlock_irqrestore(&uic->lock, flags);
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}
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static void uic_ack_irq(unsigned int virq)
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{
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struct uic *uic = get_irq_chip_data(virq);
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unsigned int src = uic_irq_to_hw(virq);
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unsigned long flags;
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spin_lock_irqsave(&uic->lock, flags);
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mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
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spin_unlock_irqrestore(&uic->lock, flags);
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}
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static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
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{
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struct uic *uic = get_irq_chip_data(virq);
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unsigned int src = uic_irq_to_hw(virq);
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struct irq_desc *desc = get_irq_desc(virq);
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unsigned long flags;
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int trigger, polarity;
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u32 tr, pr, mask;
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switch (flow_type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_NONE:
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uic_mask_irq(virq);
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return 0;
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case IRQ_TYPE_EDGE_RISING:
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trigger = 1; polarity = 1;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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trigger = 1; polarity = 0;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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trigger = 0; polarity = 1;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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trigger = 0; polarity = 0;
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break;
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default:
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return -EINVAL;
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}
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mask = ~(1 << (31 - src));
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spin_lock_irqsave(&uic->lock, flags);
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tr = mfdcr(uic->dcrbase + UIC_TR);
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pr = mfdcr(uic->dcrbase + UIC_PR);
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tr = (tr & mask) | (trigger << (31-src));
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pr = (pr & mask) | (polarity << (31-src));
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mtdcr(uic->dcrbase + UIC_PR, pr);
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mtdcr(uic->dcrbase + UIC_TR, tr);
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desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
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desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
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if (trigger)
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desc->status |= IRQ_LEVEL;
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spin_unlock_irqrestore(&uic->lock, flags);
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return 0;
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}
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static struct irq_chip uic_irq_chip = {
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.typename = " UIC ",
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.unmask = uic_unmask_irq,
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.mask = uic_mask_irq,
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/* .mask_ack = uic_mask_irq_and_ack, */
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.ack = uic_ack_irq,
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.set_type = uic_set_irq_type,
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};
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static int uic_host_match(struct irq_host *h, struct device_node *node)
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{
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struct uic *uic = h->host_data;
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return uic->of_node == node;
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}
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static int uic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct uic *uic = h->host_data;
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set_irq_chip_data(virq, uic);
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/* Despite the name, handle_level_irq() works for both level
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* and edge irqs on UIC. FIXME: check this is correct */
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set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
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/* Set default irq type */
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set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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/* UIC intspecs must have 2 cells */
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BUG_ON(intsize != 2);
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*out_hwirq = intspec[0];
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*out_type = intspec[1];
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return 0;
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}
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static struct irq_host_ops uic_host_ops = {
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.match = uic_host_match,
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.map = uic_host_map,
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.xlate = uic_host_xlate,
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};
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irqreturn_t uic_cascade(int virq, void *data)
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{
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struct uic *uic = data;
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u32 msr;
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int src;
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int subvirq;
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msr = mfdcr(uic->dcrbase + UIC_MSR);
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src = 32 - ffs(msr);
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subvirq = irq_linear_revmap(uic->irqhost, src);
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generic_handle_irq(subvirq);
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return IRQ_HANDLED;
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}
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static struct uic * __init uic_init_one(struct device_node *node)
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{
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struct uic *uic;
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const u32 *indexp, *dcrreg;
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int len;
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BUG_ON(! device_is_compatible(node, "ibm,uic"));
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uic = alloc_bootmem(sizeof(*uic));
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if (! uic)
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return NULL; /* FIXME: panic? */
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memset(uic, 0, sizeof(*uic));
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spin_lock_init(&uic->lock);
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uic->of_node = of_node_get(node);
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indexp = get_property(node, "cell-index", &len);
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if (!indexp || (len != sizeof(u32))) {
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printk(KERN_ERR "uic: Device node %s has missing or invalid "
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"cell-index property\n", node->full_name);
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return NULL;
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}
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uic->index = *indexp;
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dcrreg = get_property(node, "dcr-reg", &len);
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if (!dcrreg || (len != 2*sizeof(u32))) {
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printk(KERN_ERR "uic: Device node %s has missing or invalid "
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"dcr-reg property\n", node->full_name);
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return NULL;
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}
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uic->dcrbase = *dcrreg;
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uic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_UIC_INTS,
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&uic_host_ops, -1);
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if (! uic->irqhost) {
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of_node_put(node);
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return NULL; /* FIXME: panic? */
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}
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uic->irqhost->host_data = uic;
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/* Start with all interrupts disabled, level and non-critical */
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mtdcr(uic->dcrbase + UIC_ER, 0);
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mtdcr(uic->dcrbase + UIC_CR, 0);
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mtdcr(uic->dcrbase + UIC_TR, 0);
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/* Clear any pending interrupts, in case the firmware left some */
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mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
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printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
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NR_UIC_INTS, uic->dcrbase);
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return uic;
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}
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void __init uic_init_tree(void)
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{
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struct device_node *np;
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struct uic *uic;
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const u32 *interrupts;
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/* First locate and initialize the top-level UIC */
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np = of_find_compatible_node(NULL, NULL, "ibm,uic");
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while (np) {
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interrupts = get_property(np, "interrupts", NULL);
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if (! interrupts)
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break;
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np = of_find_compatible_node(np, NULL, "ibm,uic");
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}
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BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
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* top-level interrupt controller */
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primary_uic = uic_init_one(np);
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if (! primary_uic)
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panic("Unable to initialize primary UIC %s\n", np->full_name);
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irq_set_default_host(primary_uic->irqhost);
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of_node_put(np);
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/* The scan again for cascaded UICs */
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np = of_find_compatible_node(NULL, NULL, "ibm,uic");
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while (np) {
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interrupts = get_property(np, "interrupts", NULL);
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if (interrupts) {
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/* Secondary UIC */
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int cascade_virq;
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int ret;
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uic = uic_init_one(np);
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if (! uic)
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panic("Unable to initialize a secondary UIC %s\n",
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np->full_name);
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cascade_virq = irq_of_parse_and_map(np, 0);
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uic->cascade.handler = uic_cascade;
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uic->cascade.name = "UIC cascade";
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uic->cascade.dev_id = uic;
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ret = setup_irq(cascade_virq, &uic->cascade);
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if (ret)
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printk(KERN_ERR "Failed to setup_irq(%d) for "
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"UIC%d cascade\n", cascade_virq,
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uic->index);
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/* FIXME: setup critical cascade?? */
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}
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np = of_find_compatible_node(np, NULL, "ibm,uic");
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}
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}
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int uic_get_irq(void)
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{
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u32 msr;
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int src;
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BUG_ON(! primary_uic);
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msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
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src = 32 - ffs(msr);
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return irq_linear_revmap(primary_uic->irqhost, src);
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}
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23
include/asm-powerpc/uic.h
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23
include/asm-powerpc/uic.h
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@ -0,0 +1,23 @@
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/*
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* include/asm-powerpc/uic.h
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*
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* IBM PPC4xx UIC external definitions and structure.
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*
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* Maintainer: David Gibson <dwg@au1.ibm.com>
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* Copyright 2007 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_POWERPC_UIC_H
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#define _ASM_POWERPC_UIC_H
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#ifdef __KERNEL__
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extern void __init uic_init_tree(void);
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extern unsigned int uic_get_irq(void);
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_UIC_H */
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