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c81611c4e9
On ARM we want these to be the same size on 32- and 64-bit. This is an ABI change on ARM. X86 does not change. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Cc: Jan Beulich <JBeulich@suse.com> Cc: Keir (Xen.org) <keir@xen.org> Cc: Tim Deegan <tim@xen.org> Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Cc: linux-arm-kernel@lists.infradead.org Cc: xen-devel@lists.xen.org Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
41 lines
899 B
C
41 lines
899 B
C
#ifndef _ASM_ARM_XEN_EVENTS_H
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#define _ASM_ARM_XEN_EVENTS_H
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#include <asm/ptrace.h>
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enum ipi_vector {
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XEN_PLACEHOLDER_VECTOR,
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/* Xen IPIs go here */
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XEN_NR_IPIS,
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};
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static inline int xen_irqs_disabled(struct pt_regs *regs)
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{
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return raw_irqs_disabled_flags(regs->ARM_cpsr);
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}
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/*
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* We cannot use xchg because it does not support 8-byte
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* values. However it is safe to use {ldr,dtd}exd directly because all
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* platforms which Xen can run on support those instructions.
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*/
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static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val)
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{
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xen_ulong_t oldval;
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unsigned int tmp;
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wmb();
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asm volatile("@ xchg_xen_ulong\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" strexd %1, %2, %H2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (oldval), "=&r" (tmp)
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: "r" (val), "r" (ptr)
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: "memory", "cc");
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return oldval;
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}
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#endif /* _ASM_ARM_XEN_EVENTS_H */
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