Thierry Reding 0f1bc12e9e clk: tegra: Allow PLLE training to succeed ...

Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2013-04-01 11:44:38 -07:00

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mmp

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mvebu

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mxs

arm-soc: soc-specific updates

2013-02-21 15:27:22 -08:00

socfpga

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spear

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tegra

clk: tegra: Allow PLLE training to succeed

2013-04-01 11:44:38 -07:00

ux500

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versatile

arm-soc: driver specific changes

2013-02-21 15:12:18 -08:00

x86

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clk-bcm2835.c

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clk-devres.c

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clk-divider.c

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clk-fixed-factor.c

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clk-fixed-rate.c

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clk-gate.c

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clk-highbank.c

ACPI and power management updates for 3.9-rc1

2013-02-20 11:26:56 -08:00

clk-ls1x.c

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clk-max77686.c

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clk-mux.c

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clk-nomadik.c

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clk-prima2.c

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clk-twl6040.c

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clk-u300.c

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clk-vt8500.c

clk: vt8500: Fix "fix device clock divisor calculations"

2013-03-14 22:34:26 +01:00

clk-wm831x.c

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clk-zynq.c

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clk.c

hlist: drop the node parameter from iterators

2013-02-27 19:10:24 -08:00

clkdev.c

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Kconfig

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Makefile

arm-soc: soc-specific updates

2013-02-21 15:27:22 -08:00