mirror of
https://github.com/openharmony/kernel_linux_common_modules.git
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Haryslee
173 lines
4.0 KiB
C
173 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2023 Huawei Device Co., Ltd.
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*/
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#ifndef __ASM_POINTER_AUTH_CONTEXT_H
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#define __ASM_POINTER_AUTH_CONTEXT_H
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#include <asm/asm-offsets.h>
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#include <asm/sysreg.h>
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/* Compute and store hash value of cpu context. */
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.macro sign_thread_context_common, tmp1=x0, tmp2=x1, tmp3=x2
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pacga \tmp2, \tmp1, \tmp2
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pacga \tmp2, \tmp3, \tmp2
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str \tmp2, [\tmp1, CPU_CONTEXT_PAC_HASH]
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.endm
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/* Compute and auth hash value of cpu context. */
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.macro auth_thread_context_common, tmp1=x0, tmp2=x1, tmp3=x2
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pacga \tmp2, \tmp1, \tmp2
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pacga \tmp2, \tmp3, \tmp2
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ldr \tmp3, [\tmp1, CPU_CONTEXT_PAC_HASH]
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cmp \tmp2, \tmp3
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b.ne .Lthread_context_pac_panic\@
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b .Lauth_thread_context_done\@
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.Lthread_context_pac_panic\@:
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adrp x0, .Lthread_context_pac_str
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add x0, x0, :lo12:.Lthread_context_pac_str
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bl panic
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.Lauth_thread_context_done\@:
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.endm
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/* Compute and store hash value of the regs. */
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.macro sign_exception_context_common, tmp1=x0, tmp2=x1, tmp3=x2, tmp4=x3, tmp5=x4, tmp6=x5, tmp7=x6
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pacga \tmp2, \tmp1, \tmp2
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pacga \tmp2, \tmp3, \tmp2
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pacga \tmp2, \tmp4, \tmp2
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pacga \tmp2, \tmp5, \tmp2
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pacga \tmp2, \tmp6, \tmp2
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pacga \tmp2, \tmp7, \tmp2
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str \tmp2, [\tmp1, S_PAC_HASH]
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.endm
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/* Compute and auth hash value of the regs. */
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.macro auth_exception_context_common, tmp1=x0, tmp2=x1, tmp3=x2, tmp4=x3, tmp5=x4, tmp6=x5, tmp7=x6
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pacga \tmp2, \tmp1, \tmp2
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pacga \tmp2, \tmp3, \tmp2
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pacga \tmp2, \tmp4, \tmp2
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pacga \tmp2, \tmp5, \tmp2
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pacga \tmp2, \tmp6, \tmp2
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pacga \tmp2, \tmp7, \tmp2
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ldr \tmp3, [\tmp1, S_PAC_HASH]
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cmp \tmp2, \tmp3
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b.ne .Lpt_regs_pac_panic\@
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b .Lauth_exception_context_done\@
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.Lpt_regs_pac_panic\@:
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adrp x0, .Lpt_regs_pac_panic_str
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add x0, x0, :lo12:.Lpt_regs_pac_panic_str
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bl panic
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.Lauth_exception_context_done\@:
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.endm
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.Lpt_regs_pac_panic_str:
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.asciz "Failed to match pac hash of exception context!\n"
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.align 2
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.Lthread_context_pac_str:
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.asciz "Failed to match pac hash of cpu context!\n"
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.align 2
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.macro pac_cpu_context sign_or_auth
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.if \sign_or_auth == 0
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/* x0: base of curr task */
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mov x2, x0
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.else
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/* x1: base of next task */
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mov x2, x1
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.endif
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add x2, x2, #THREAD_CPU_CONTEXT
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/* sign sp, lr of cpu context. */
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mov x3, lr
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mov x4, x9
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.if \sign_or_auth == 0
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sign_thread_context_common x2, x3, x4
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.else
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auth_thread_context_common x2, x3, x4
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.endif
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.endm
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.macro sign_cpu_context sign=0
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pac_cpu_context \sign
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.endm
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.macro auth_cpu_context auth=1
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pac_cpu_context \auth
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.endm
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.macro prepare_compat_pt_regs, sign_or_auth
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/* base of pt_regs */
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mov x23, sp
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mov x24, #0
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mov x25, #0
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/* sign lr, sp, pc, pstate of compat task */
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mov x26, x14
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mov x27, x13
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mrs x20, elr_el1
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.if \sign_or_auth == 0
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mrs x21, spsr_el1
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.else
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mov x21, x22
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.endif
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.endm
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.macro prepare_pt_regs, el, sign_or_auth
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/* base of pt_regs */
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mov x23, sp
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/* sign x16, x17, lr, sp, pc, pstate of task */
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mov x24, x16
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mov x25, x17
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.if \sign_or_auth == 0
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mov x26, lr
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.else
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ldr x26, [x23, #S_LR]
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.endif
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.if \el == 0
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mrs x27, sp_el0
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.else
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add x27, x23, #S_FRAME_SIZE
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.endif
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mrs x20, elr_el1
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.if \sign_or_auth == 0
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mrs x21, spsr_el1
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.else
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mov x21, x22
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.endif
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.endm
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.macro pac_pt_regs, el, sign_or_auth
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.if \el == 0
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/* Test the task is in the mode of 32-bit or 64-bit */
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mrs x23, spsr_el1
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mov x24, #(PSR_MODE32_BIT | PSR_MODE_MASK)
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mov x25, #(PSR_MODE32_BIT | PSR_MODE_EL0t)
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and x23, x23, x24
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sub x23, x23, x25
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cbnz x23, .Lis_not_compat_task\@
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/* Task in 32-bit mode */
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prepare_compat_pt_regs \sign_or_auth
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b .Lpac_handle\@
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.endif
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/* Task in 64-bit mode */
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.Lis_not_compat_task\@:
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prepare_pt_regs \el, \sign_or_auth
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/* Call the sign or auth function. */
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.Lpac_handle\@:
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.if \sign_or_auth == 0
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sign_exception_context_common x23, x24, x25, x26, x27, x20, x21
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.else
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auth_exception_context_common x23, x24, x25, x26, x27, x20, x21
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.endif
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.endm
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.macro sign_pt_regs, el, sign=0
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pac_pt_regs \el, \sign
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.endm
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.macro auth_pt_regs, el, auth=1
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pac_pt_regs \el, \auth
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.endm
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#endif /* __ASM_POINTER_AUTH_CONTEXT_H */
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