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https://gitee.com/openharmony/third_party_benchmark
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ecc1685340
@ -86,15 +86,15 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
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// This returns a time-base, which is not always precisely a cycle-count.
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#if defined(__powerpc64__) || defined(__ppc64__)
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int64_t tb;
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asm volatile("mfspr %0, 268" : "=r" (tb));
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asm volatile("mfspr %0, 268" : "=r"(tb));
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return tb;
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#else
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uint32_t tbl, tbu0, tbu1;
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asm volatile(
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"mftbu %0\n"
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"mftbl %1\n"
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"mftbu %2"
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: "=r"(tbu0), "=r"(tbl), "=r"(tbu1));
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"mftbu %0\n"
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"mftbl %1\n"
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"mftbu %2"
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: "=r"(tbu0), "=r"(tbl), "=r"(tbu1));
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tbl &= -static_cast<int32_t>(tbu0 == tbu1);
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// high 32 bits in tbu1; low 32 bits in tbl (tbu0 is no longer needed)
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return (static_cast<uint64_t>(tbu1) << 32) | tbl;
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@ -179,14 +179,14 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
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// This asm also includes the PowerPC overflow handling strategy, as above.
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// Implemented in assembly because Clang insisted on branching.
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asm volatile(
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"rdcycleh %0\n"
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"rdcycle %1\n"
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"rdcycleh %2\n"
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"sub %0, %0, %2\n"
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"seqz %0, %0\n"
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"sub %0, zero, %0\n"
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"and %1, %1, %0\n"
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: "=r"(cycles_hi0), "=r"(cycles_lo), "=r"(cycles_hi1));
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"rdcycleh %0\n"
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"rdcycle %1\n"
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"rdcycleh %2\n"
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"sub %0, %0, %2\n"
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"seqz %0, %0\n"
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"sub %0, zero, %0\n"
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"and %1, %1, %0\n"
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: "=r"(cycles_hi0), "=r"(cycles_lo), "=r"(cycles_hi1));
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return (static_cast<uint64_t>(cycles_hi1) << 32) | cycles_lo;
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#else
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uint64_t cycles;
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