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https://github.com/openharmony/third_party_elfutils.git
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lizhenlin
91 lines
3.7 KiB
C
91 lines
3.7 KiB
C
/* x86 linux perf_events register handling, pieces common to x86-64 and i386.
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Copyright (C) 2025 Red Hat, Inc.
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This file is part of elfutils.
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This file is free software; you can redistribute it and/or modify
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it under the terms of either
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* the GNU Lesser General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at
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your option) any later version
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or
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* the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at
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your option) any later version
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or both in parallel, as here.
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elfutils is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received copies of the GNU General Public License and
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the GNU Lesser General Public License along with this program. If
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not, see <http://www.gnu.org/licenses/>. */
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static bool
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x86_set_initial_registers_sample (const Dwarf_Word *regs, uint32_t n_regs,
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uint64_t regs_mask, uint32_t abi,
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Dwarf_Word *dwarf_regs, int expected_regs)
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{
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#if (!defined __i386__ && !defined __x86_64__) || !defined(__linux__)
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return false;
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#else /* __i386__ || __x86_64__ */
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/* The following facts are needed to translate x86 registers correctly:
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- perf register order seen in linux arch/x86/include/uapi/asm/perf_regs.h
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The registers array is built in the same order as the enum!
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(See the code in tools/perf/util/intel-pt.c intel_pt_add_gp_regs().)
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- EBL PERF_FRAME_REGS_MASK specifies all registers except segment and
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flags. However, regs_mask might be a different set of registers.
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Again, regs_mask bits are in asm/perf_regs.h enum order.
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- dwarf register order seen in elfutils backends/{x86_64,i386}_initreg.c
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(matching pt_regs struct in linux arch/x86/include/asm/ptrace.h)
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and it's a fairly different register order!
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For comparison, you can study codereview.qt-project.org/gitweb?p=qt-creator/perfparser.git;a=blob;f=app/perfregisterinfo.cpp;hb=HEAD
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and follow the code which uses those tables of magic numbers.
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But it's better to follow original sources of truth for this. */
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bool is_abi32 = (abi == PERF_SAMPLE_REGS_ABI_32);
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/* Locations of dwarf_regs in the perf_event_x86_regs enum order,
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not the regs[i] array (which will include a subset of the regs): */
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static const int regs_i386[] = {0, 2, 3, 1, 7/*sp*/, 6, 4, 5, 8/*ip*/};
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static const int regs_x86_64[] = {0, 3, 2, 1, 4, 5, 6, 7/*sp*/,
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16/*r8 after flags+segment*/, 17, 18, 19, 20, 21, 22, 23,
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8/*ip*/};
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const int *dwarf_to_perf = is_abi32 ? regs_i386 : regs_x86_64;
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/* Locations of perf_regs in the regs[] array, according to regs_mask: */
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int perf_to_regs[PERF_REG_X86_64_MAX];
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uint64_t expected_mask = is_abi32 ? PERF_FRAME_REGISTERS_I386 : PERF_FRAME_REGISTERS_X86_64;
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int j, k; uint64_t bit;
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/* TODO: Is it worth caching this perf_to_regs computation as long
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as regs_mask is kept the same across repeated calls? */
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for (j = 0, k = 0, bit = 1; k < PERF_REG_X86_64_MAX; k++, bit <<= 1)
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{
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if ((bit & expected_mask) && (bit & regs_mask)) {
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if (n_regs <= (uint32_t)j)
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return false; /* regs_mask count doesn't match n_regs */
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perf_to_regs[k] = j;
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j++;
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} else {
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perf_to_regs[k] = -1;
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}
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}
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for (int i = 0; i < expected_regs; i++)
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{
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k = dwarf_to_perf[i];
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j = perf_to_regs[k];
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if (j < 0) continue;
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if (n_regs <= (uint32_t)j) continue;
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dwarf_regs[i] = regs[j];
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}
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return true;
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#endif /* __i386__ || __x86_64__ */
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}
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