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https://gitee.com/openharmony/third_party_ffmpeg
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x86: use new schema for ASM macros
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Vitor Sessak
Michael Niedermayer
parent
65212e3ed9
commit
2fd5e70869
@ -27,15 +27,15 @@ av_cold void ff_fft_init_mmx(FFTContext *s)
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int has_vectors = av_get_cpu_flags();
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if (has_vectors & AV_CPU_FLAG_3DNOW && HAVE_AMD3DNOW) {
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/* 3DNow! for K6-2/3 */
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s->imdct_calc = ff_imdct_calc_3dn;
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s->imdct_half = ff_imdct_half_3dn;
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s->fft_calc = ff_fft_calc_3dn;
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s->imdct_calc = ff_imdct_calc_3dnow;
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s->imdct_half = ff_imdct_half_3dnow;
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s->fft_calc = ff_fft_calc_3dnow;
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}
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if (has_vectors & AV_CPU_FLAG_3DNOWEXT && HAVE_AMD3DNOWEXT) {
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/* 3DNowEx for K7 */
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s->imdct_calc = ff_imdct_calc_3dn2;
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s->imdct_half = ff_imdct_half_3dn2;
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s->fft_calc = ff_fft_calc_3dn2;
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s->imdct_calc = ff_imdct_calc_3dnow2;
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s->imdct_half = ff_imdct_half_3dnow2;
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s->fft_calc = ff_fft_calc_3dnow2;
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}
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if (has_vectors & AV_CPU_FLAG_SSE && HAVE_SSE) {
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/* SSE for P3/P4/K8 */
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@ -24,13 +24,13 @@
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void ff_fft_permute_sse(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_avx(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_sse(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dn(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dn2(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dnow(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dnow2(FFTContext *s, FFTComplex *z);
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void ff_imdct_calc_3dn(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dn(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_3dn2(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dn2(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_3dnow(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dnow(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_3dnow2(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dnow2(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_sse(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_sse(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_avx(FFTContext *s, FFTSample *output, const FFTSample *input);
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@ -30,30 +30,30 @@ DECLARE_ALIGNED(8, static const unsigned int, m1m1)[2] = { 1U<<31, 1U<<31 };
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"movq "#s","#d"\n"\
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"psrlq $32,"#d"\n"\
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"punpckldq "#s","#d"\n"
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#define ff_fft_calc_3dn2 ff_fft_calc_3dn
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#define ff_fft_dispatch_3dn2 ff_fft_dispatch_3dn
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#define ff_fft_dispatch_interleave_3dn2 ff_fft_dispatch_interleave_3dn
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#define ff_imdct_calc_3dn2 ff_imdct_calc_3dn
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#define ff_imdct_half_3dn2 ff_imdct_half_3dn
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#define ff_fft_calc_3dnow2 ff_fft_calc_3dnow
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#define ff_fft_dispatch_3dnow2 ff_fft_dispatch_3dnow
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#define ff_fft_dispatch_interleave_3dnow2 ff_fft_dispatch_interleave_3dnow
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#define ff_imdct_calc_3dnow2 ff_imdct_calc_3dnow
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#define ff_imdct_half_3dnow2 ff_imdct_half_3dnow
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#else
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#define PSWAPD(s,d) "pswapd "#s","#d"\n"
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#endif
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void ff_fft_dispatch_3dn2(FFTComplex *z, int nbits);
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void ff_fft_dispatch_interleave_3dn2(FFTComplex *z, int nbits);
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void ff_fft_dispatch_3dnow2(FFTComplex *z, int nbits);
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void ff_fft_dispatch_interleave_3dnow2(FFTComplex *z, int nbits);
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void ff_fft_calc_3dn2(FFTContext *s, FFTComplex *z)
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void ff_fft_calc_3dnow2(FFTContext *s, FFTComplex *z)
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{
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int n = 1<<s->nbits;
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int i;
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ff_fft_dispatch_interleave_3dn2(z, s->nbits);
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ff_fft_dispatch_interleave_3dnow2(z, s->nbits);
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__asm__ volatile("femms");
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if(n <= 8)
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for(i=0; i<n; i+=2)
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FFSWAP(FFTSample, z[i].im, z[i+1].re);
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}
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void ff_imdct_half_3dn2(FFTContext *s, FFTSample *output, const FFTSample *input)
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void ff_imdct_half_3dnow2(FFTContext *s, FFTSample *output, const FFTSample *input)
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{
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x86_reg j, k;
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long n = s->mdct_size;
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@ -101,7 +101,7 @@ void ff_imdct_half_3dn2(FFTContext *s, FFTSample *output, const FFTSample *input
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);
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}
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ff_fft_dispatch_3dn2(z, s->nbits);
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ff_fft_dispatch_3dnow2(z, s->nbits);
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#define CMUL(j,mm0,mm1)\
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"movq (%2,"#j",2), %%mm6 \n"\
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@ -144,13 +144,13 @@ void ff_imdct_half_3dn2(FFTContext *s, FFTSample *output, const FFTSample *input
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__asm__ volatile("femms");
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}
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void ff_imdct_calc_3dn2(FFTContext *s, FFTSample *output, const FFTSample *input)
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void ff_imdct_calc_3dnow2(FFTContext *s, FFTSample *output, const FFTSample *input)
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{
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x86_reg j, k;
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long n = s->mdct_size;
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long n4 = n >> 2;
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ff_imdct_half_3dn2(s, output+n4, input);
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ff_imdct_half_3dnow2(s, output+n4, input);
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j = -n;
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k = n-8;
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@ -297,7 +297,7 @@ IF%1 mova Z(1), m5
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%define Z2(x) [r0+mmsize*x]
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%define ZH(x) [r0+mmsize*x+mmsize/2]
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INIT_YMM
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INIT_YMM avx
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%if HAVE_AVX
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align 16
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@ -391,7 +391,7 @@ fft32_interleave_avx:
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%endif
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INIT_XMM
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INIT_XMM sse
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%define movdqa movaps
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align 16
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@ -440,11 +440,9 @@ fft16_sse:
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ret
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INIT_MMX
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%macro FFT48_3DN 1
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%macro FFT48_3DN 0
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align 16
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fft4%1:
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fft4_ %+ cpuname:
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T2_3DN m0, m1, Z(0), Z(1)
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mova m2, Z(2)
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mova m3, Z(3)
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@ -458,7 +456,7 @@ fft4%1:
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ret
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align 16
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fft8%1:
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fft8_ %+ cpuname:
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T2_3DN m0, m1, Z(0), Z(1)
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mova m2, Z(2)
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mova m3, Z(3)
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@ -496,7 +494,8 @@ fft8%1:
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ret
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%endmacro
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FFT48_3DN _3dn2
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INIT_MMX 3dnow2
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FFT48_3DN
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%macro pswapd 2
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%ifidn %1, %2
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@ -509,7 +508,8 @@ FFT48_3DN _3dn2
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%endif
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%endmacro
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FFT48_3DN _3dn
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INIT_MMX 3dnow
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FFT48_3DN
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%define Z(x) [zq + o1q*(x&6) + mmsize*(x&1)]
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@ -533,7 +533,7 @@ DEFINE_ARGS z, w, n, o1, o3
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rep ret
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%endmacro
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INIT_YMM
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INIT_YMM avx
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%if HAVE_AVX
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%macro INTERL_AVX 5
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@ -551,7 +551,7 @@ DECL_PASS pass_avx, PASS_BIG 1
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DECL_PASS pass_interleave_avx, PASS_BIG 0
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%endif
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INIT_XMM
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INIT_XMM sse
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%macro INTERL_SSE 5
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mova %3, %2
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@ -566,16 +566,16 @@ INIT_XMM
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DECL_PASS pass_sse, PASS_BIG 1
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DECL_PASS pass_interleave_sse, PASS_BIG 0
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INIT_MMX
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INIT_MMX 3dnow
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%define mulps pfmul
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%define addps pfadd
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%define subps pfsub
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%define unpcklps punpckldq
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%define unpckhps punpckhdq
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DECL_PASS pass_3dn, PASS_SMALL 1, [wq], [wq+o1q]
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DECL_PASS pass_interleave_3dn, PASS_BIG 0
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%define pass_3dn2 pass_3dn
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%define pass_interleave_3dn2 pass_interleave_3dn
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DECL_PASS pass_3dnow, PASS_SMALL 1, [wq], [wq+o1q]
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DECL_PASS pass_interleave_3dnow, PASS_BIG 0
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%define pass_3dnow2 pass_3dnow
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%define pass_interleave_3dnow2 pass_interleave_3dnow
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%ifdef PIC
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%define SECTION_REL - $$
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@ -593,67 +593,70 @@ DECL_PASS pass_interleave_3dn, PASS_BIG 0
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call r2
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%endmacro ; FFT_DISPATCH
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%macro DECL_FFT 2-3 ; nbits, cpu, suffix
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%xdefine list_of_fft fft4%2 SECTION_REL, fft8%2 SECTION_REL
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%macro DECL_FFT 1-2 ; nbits, cpu, suffix
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%xdefine cpusuffix _ %+ cpuname
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%xdefine fullsuffix %2_ %+ cpuname
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%xdefine list_of_fft fft4 %+ cpusuffix SECTION_REL, fft8 %+ cpusuffix SECTION_REL
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%if %1>=5
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%xdefine list_of_fft list_of_fft, fft16%2 SECTION_REL
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%xdefine list_of_fft list_of_fft, fft16 %+ cpusuffix SECTION_REL
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%endif
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%if %1>=6
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%xdefine list_of_fft list_of_fft, fft32%3%2 SECTION_REL
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%xdefine list_of_fft list_of_fft, fft32 %+ fullsuffix SECTION_REL
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%endif
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%assign n 1<<%1
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%rep 17-%1
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%assign n2 n/2
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%assign n4 n/4
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%xdefine list_of_fft list_of_fft, fft %+ n %+ %3%2 SECTION_REL
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%xdefine list_of_fft list_of_fft, fft %+ n %+ fullsuffix SECTION_REL
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align 16
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fft %+ n %+ %3%2:
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call fft %+ n2 %+ %2
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fft %+ n %+ fullsuffix:
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call fft %+ n2 %+ cpusuffix
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add r0, n*4 - (n&(-2<<%1))
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call fft %+ n4 %+ %2
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call fft %+ n4 %+ cpusuffix
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add r0, n*2 - (n2&(-2<<%1))
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call fft %+ n4 %+ %2
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call fft %+ n4 %+ cpusuffix
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sub r0, n*6 + (n2&(-2<<%1))
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lea r1, [cos_ %+ n]
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mov r2d, n4/2
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jmp pass%3%2
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jmp pass %+ fullsuffix
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%assign n n*2
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%endrep
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%undef n
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align 8
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dispatch_tab%3%2: pointer list_of_fft
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dispatch_tab %+ fullsuffix: pointer list_of_fft
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section .text
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; On x86_32, this function does the register saving and restoring for all of fft.
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; The others pass args in registers and don't spill anything.
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cglobal fft_dispatch%3%2, 2,5,8, z, nbits
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FFT_DISPATCH %3%2, nbits
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%ifidn %2, _avx
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cglobal fft_dispatch%2, 2,5,8, z, nbits
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FFT_DISPATCH fullsuffix, nbits
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%if mmsize == 32
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vzeroupper
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%endif
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RET
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%endmacro ; DECL_FFT
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%if HAVE_AVX
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INIT_YMM
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DECL_FFT 6, _avx
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DECL_FFT 6, _avx, _interleave
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INIT_YMM avx
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DECL_FFT 6
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DECL_FFT 6, _interleave
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%endif
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INIT_XMM
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DECL_FFT 5, _sse
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DECL_FFT 5, _sse, _interleave
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INIT_MMX
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DECL_FFT 4, _3dn
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DECL_FFT 4, _3dn, _interleave
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DECL_FFT 4, _3dn2
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DECL_FFT 4, _3dn2, _interleave
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INIT_XMM sse
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DECL_FFT 5
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DECL_FFT 5, _interleave
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INIT_MMX 3dnow
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DECL_FFT 4
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DECL_FFT 4, _interleave
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INIT_MMX 3dnow2
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DECL_FFT 4
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DECL_FFT 4, _interleave
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INIT_XMM
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INIT_XMM sse
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%undef mulps
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%undef addps
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%undef subps
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@ -749,8 +752,8 @@ INIT_XMM
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jl .post
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%endmacro
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%macro DECL_IMDCT 2
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cglobal imdct_half%1, 3,12,8; FFTContext *s, FFTSample *output, const FFTSample *input
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%macro DECL_IMDCT 1
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cglobal imdct_half, 3,12,8; FFTContext *s, FFTSample *output, const FFTSample *input
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%if ARCH_X86_64
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%define rrevtab r7
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%define rtcos r8
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@ -822,7 +825,7 @@ cglobal imdct_half%1, 3,12,8; FFTContext *s, FFTSample *output, const FFTSample
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mov r0, r1
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mov r1d, [r5+FFTContext.nbits]
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FFT_DISPATCH %1, r1
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FFT_DISPATCH _ %+ cpuname, r1
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mov r0d, [r5+FFTContext.mdctsize]
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add r6, r0
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@ -836,20 +839,20 @@ cglobal imdct_half%1, 3,12,8; FFTContext *s, FFTSample *output, const FFTSample
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neg r0
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mov r1, -mmsize
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sub r1, r0
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%2 r0, r1, r6, rtcos, rtsin
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%1 r0, r1, r6, rtcos, rtsin
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%if ARCH_X86_64 == 0
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add esp, 12
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%endif
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%ifidn avx_enabled, 1
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%if mmsize == 32
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vzeroupper
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%endif
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RET
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%endmacro
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DECL_IMDCT _sse, POSROTATESHUF
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DECL_IMDCT POSROTATESHUF
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INIT_YMM
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INIT_YMM avx
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%if HAVE_AVX
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DECL_IMDCT _avx, POSROTATESHUF_AVX
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DECL_IMDCT POSROTATESHUF_AVX
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%endif
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