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vp9: add 10bpp simd (mmxext/ssse3) for idct_idct_4x4.
This commit is contained in:
Ronald S. Bultje
parent
1c3be32533
commit
6b579cf547
@ -85,6 +85,8 @@ DECLARE_ALIGNED(32, const ymm_reg, ff_pd_16) = { 0x0000001000000010ULL, 0x000
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0x0000001000000010ULL, 0x0000001000000010ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pd_32) = { 0x0000002000000020ULL, 0x0000002000000020ULL,
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0x0000002000000020ULL, 0x0000002000000020ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pd_8192) = { 0x0000200000002000ULL, 0x0000200000002000ULL,
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0x0000200000002000ULL, 0x0000200000002000ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pd_65535)= { 0x0000ffff0000ffffULL, 0x0000ffff0000ffffULL,
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0x0000ffff0000ffffULL, 0x0000ffff0000ffffULL };
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@ -65,6 +65,7 @@ extern const xmm_reg ff_ps_neg;
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extern const ymm_reg ff_pd_1;
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extern const ymm_reg ff_pd_16;
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extern const ymm_reg ff_pd_32;
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extern const ymm_reg ff_pd_8192;
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extern const ymm_reg ff_pd_65535;
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# if ARCH_X86_64
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@ -125,6 +125,10 @@ lpf_mix2_wrappers_set(BPC, avx);
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decl_ipred_fns(tm, BPC, mmxext, sse2);
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decl_itxfm_func(iwht, iwht, 4, BPC, mmxext);
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#if BPC == 10
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decl_itxfm_func(idct, idct, 4, BPC, mmxext);
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decl_itxfm_func(idct, idct, 4, BPC, ssse3);
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#endif
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#endif /* HAVE_YASM */
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av_cold void INIT_FUNC(VP9DSPContext *dsp, int bitexact)
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@ -170,6 +174,9 @@ av_cold void INIT_FUNC(VP9DSPContext *dsp, int bitexact)
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init_ipred_func(tm, TM_VP8, 4, BPC, mmxext);
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if (!bitexact) {
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init_itx_func_one(4 /* lossless */, iwht, iwht, 4, BPC, mmxext);
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#if BPC == 10
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init_itx_func(TX_4X4, DCT_DCT, idct, idct, 4, 10, mmxext);
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#endif
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}
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}
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@ -182,6 +189,11 @@ av_cold void INIT_FUNC(VP9DSPContext *dsp, int bitexact)
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if (EXTERNAL_SSSE3(cpu_flags)) {
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init_lpf_funcs(BPC, ssse3);
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#if BPC == 10
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if (!bitexact) {
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init_itx_func(TX_4X4, DCT_DCT, idct, idct, 4, 10, ssse3);
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}
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#endif
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}
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if (EXTERNAL_AVX(cpu_flags)) {
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@ -71,8 +71,6 @@ pw_13377x2: times 8 dw 13377*2
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pw_m13377_13377: times 4 dw -13377, 13377
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pw_13377_0: times 4 dw 13377, 0
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pd_8192: times 4 dd 8192
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cextern pw_8
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cextern pw_16
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cextern pw_32
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@ -80,38 +78,10 @@ cextern pw_512
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cextern pw_1024
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cextern pw_2048
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cextern pw_m1
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cextern pd_8192
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SECTION .text
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; (a*x + b*y + round) >> shift
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%macro VP9_MULSUB_2W_2X 5 ; dst1, dst2/src, round, coefs1, coefs2
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pmaddwd m%1, m%2, %4
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pmaddwd m%2, %5
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paddd m%1, %3
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paddd m%2, %3
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psrad m%1, 14
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psrad m%2, 14
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%endmacro
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%macro VP9_MULSUB_2W_4X 7 ; dst1, dst2, coef1, coef2, rnd, tmp1/src, tmp2
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VP9_MULSUB_2W_2X %7, %6, %5, [pw_m%3_%4], [pw_%4_%3]
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VP9_MULSUB_2W_2X %1, %2, %5, [pw_m%3_%4], [pw_%4_%3]
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packssdw m%1, m%7
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packssdw m%2, m%6
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%endmacro
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%macro VP9_UNPACK_MULSUB_2W_4X 7-9 ; dst1, dst2, (src1, src2,) coef1, coef2, rnd, tmp1, tmp2
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%if %0 == 7
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punpckhwd m%6, m%2, m%1
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punpcklwd m%2, m%1
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VP9_MULSUB_2W_4X %1, %2, %3, %4, %5, %6, %7
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%else
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punpckhwd m%8, m%4, m%3
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punpcklwd m%2, m%4, m%3
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VP9_MULSUB_2W_4X %1, %2, %5, %6, %7, %8, %9
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%endif
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%endmacro
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%macro VP9_UNPACK_MULSUB_2D_4X 6 ; dst1 [src1], dst2 [src2], dst3, dst4, mul1, mul2
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punpckhwd m%4, m%2, m%1
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punpcklwd m%2, m%1
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@ -191,24 +161,6 @@ cglobal vp9_iwht_iwht_4x4_add, 3, 3, 0, dst, stride, block, eob
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; void vp9_idct_idct_4x4_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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;-------------------------------------------------------------------------------------------
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%macro VP9_IDCT4_1D_FINALIZE 0
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SUMSUB_BA w, 3, 2, 4 ; m3=t3+t0, m2=-t3+t0
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SUMSUB_BA w, 1, 0, 4 ; m1=t2+t1, m0=-t2+t1
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SWAP 0, 3, 2 ; 3102 -> 0123
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%endmacro
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%macro VP9_IDCT4_1D 0
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%if cpuflag(ssse3)
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SUMSUB_BA w, 2, 0, 4 ; m2=IN(0)+IN(2) m0=IN(0)-IN(2)
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pmulhrsw m2, m6 ; m2=t0
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pmulhrsw m0, m6 ; m0=t1
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%else ; <= sse2
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VP9_UNPACK_MULSUB_2W_4X 0, 2, 11585, 11585, m7, 4, 5 ; m0=t1, m1=t0
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%endif
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VP9_UNPACK_MULSUB_2W_4X 1, 3, 15137, 6270, m7, 4, 5 ; m1=t2, m3=t3
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VP9_IDCT4_1D_FINALIZE
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%endmacro
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; 2x2 top left corner
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%macro VP9_IDCT4_2x2_1D 0
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pmulhrsw m0, m5 ; m0=t1
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@ -25,8 +25,18 @@
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SECTION_RODATA
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cextern pw_8
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cextern pw_1023
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cextern pw_2048
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cextern pw_4095
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cextern pd_8192
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; FIXME these should probably be shared between 8bpp and 10/12bpp
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pw_m11585_11585: times 4 dw -11585, 11585
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pw_11585_11585: times 8 dw 11585
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pw_m15137_6270: times 4 dw -15137, 6270
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pw_6270_15137: times 4 dw 6270, 15137
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pw_11585x2: times 8 dw 11585*2
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SECTION .text
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@ -118,3 +128,89 @@ INIT_MMX mmxext
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IWHT4_FN 10, 1023
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INIT_MMX mmxext
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IWHT4_FN 12, 4095
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; 4x4 coefficients are 5+depth+sign bits, so for 10bpp, everything still fits
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; in 15+1 words without additional effort, since the coefficients are 15bpp.
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%macro IDCT4_10_FN 0
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cglobal vp9_idct_idct_4x4_add_10, 4, 4, 8, dst, stride, block, eob
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cmp eobd, 1
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jg .idctfull
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; dc-only
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%if cpuflag(ssse3)
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movd m0, [blockq]
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mova m5, [pw_11585x2]
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pmulhrsw m0, m5
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pmulhrsw m0, m5
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%else
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DEFINE_ARGS dst, stride, block, coef
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mov coefd, dword [blockq]
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imul coefd, 11585
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add coefd, 8192
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sar coefd, 14
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imul coefd, 11585
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add coefd, (8 << 14) + 8192
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sar coefd, 14 + 4
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movd m0, coefd
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%endif
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pshufw m0, m0, 0
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pxor m4, m4
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mova m5, [pw_1023]
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movh [blockq], m4
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%if cpuflag(ssse3)
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pmulhrsw m0, [pw_2048] ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
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%endif
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VP9_STORE_2X 0, 0, 6, 7, 4, 5
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lea dstq, [dstq+2*strideq]
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VP9_STORE_2X 0, 0, 6, 7, 4, 5
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RET
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.idctfull:
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mova m0, [blockq+0*16+0]
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mova m1, [blockq+1*16+0]
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packssdw m0, [blockq+0*16+8]
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packssdw m1, [blockq+1*16+8]
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mova m2, [blockq+2*16+0]
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mova m3, [blockq+3*16+0]
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packssdw m2, [blockq+2*16+8]
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packssdw m3, [blockq+3*16+8]
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%if cpuflag(ssse3)
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mova m6, [pw_11585x2]
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%endif
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mova m7, [pd_8192] ; rounding
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VP9_IDCT4_1D
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TRANSPOSE4x4W 0, 1, 2, 3, 4
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VP9_IDCT4_1D
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pxor m4, m4
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ZERO_BLOCK blockq, 16, 4, m4
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%if cpuflag(ssse3)
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mova m5, [pw_2048]
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pmulhrsw m0, m5
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pmulhrsw m1, m5
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pmulhrsw m2, m5
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pmulhrsw m3, m5
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%else
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mova m5, [pw_8]
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paddw m0, m5
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paddw m1, m5
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paddw m2, m5
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paddw m3, m5
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psraw m0, 4
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psraw m1, 4
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psraw m2, 4
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psraw m3, 4
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%endif
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mova m5, [pw_1023]
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VP9_STORE_2X 0, 1, 6, 7, 4, 5
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lea dstq, [dstq+2*strideq]
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VP9_STORE_2X 2, 3, 6, 7, 4, 5
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RET
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%endmacro
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INIT_MMX mmxext
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IDCT4_10_FN
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INIT_MMX ssse3
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IDCT4_10_FN
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@ -35,3 +35,50 @@
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paddw m3, m2
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SWAP 3, 2, 1
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%endmacro
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; (a*x + b*y + round) >> shift
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%macro VP9_MULSUB_2W_2X 5 ; dst1, dst2/src, round, coefs1, coefs2
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pmaddwd m%1, m%2, %4
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pmaddwd m%2, %5
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paddd m%1, %3
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paddd m%2, %3
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psrad m%1, 14
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psrad m%2, 14
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%endmacro
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%macro VP9_MULSUB_2W_4X 7 ; dst1, dst2, coef1, coef2, rnd, tmp1/src, tmp2
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VP9_MULSUB_2W_2X %7, %6, %5, [pw_m%3_%4], [pw_%4_%3]
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VP9_MULSUB_2W_2X %1, %2, %5, [pw_m%3_%4], [pw_%4_%3]
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packssdw m%1, m%7
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packssdw m%2, m%6
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%endmacro
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%macro VP9_UNPACK_MULSUB_2W_4X 7-9 ; dst1, dst2, (src1, src2,) coef1, coef2, rnd, tmp1, tmp2
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%if %0 == 7
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punpckhwd m%6, m%2, m%1
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punpcklwd m%2, m%1
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VP9_MULSUB_2W_4X %1, %2, %3, %4, %5, %6, %7
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%else
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punpckhwd m%8, m%4, m%3
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punpcklwd m%2, m%4, m%3
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VP9_MULSUB_2W_4X %1, %2, %5, %6, %7, %8, %9
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%endif
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%endmacro
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%macro VP9_IDCT4_1D_FINALIZE 0
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SUMSUB_BA w, 3, 2, 4 ; m3=t3+t0, m2=-t3+t0
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SUMSUB_BA w, 1, 0, 4 ; m1=t2+t1, m0=-t2+t1
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SWAP 0, 3, 2 ; 3102 -> 0123
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%endmacro
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%macro VP9_IDCT4_1D 0
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%if cpuflag(ssse3)
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SUMSUB_BA w, 2, 0, 4 ; m2=IN(0)+IN(2) m0=IN(0)-IN(2)
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pmulhrsw m2, m6 ; m2=t0
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pmulhrsw m0, m6 ; m0=t1
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%else ; <= sse2
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VP9_UNPACK_MULSUB_2W_4X 0, 2, 11585, 11585, m7, 4, 5 ; m0=t1, m1=t0
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%endif
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VP9_UNPACK_MULSUB_2W_4X 1, 3, 15137, 6270, m7, 4, 5 ; m1=t2, m3=t3
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VP9_IDCT4_1D_FINALIZE
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%endmacro
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