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5e826fd65e
All our ARM asm preserves alignment so setting this attribute in a common location is simpler. This removes numerous warnings when linking with armcc. Signed-off-by: Mans Rullgard <mans@mansr.com>
194 lines
7.0 KiB
ArmAsm
194 lines
7.0 KiB
ArmAsm
/*
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* Copyright (c) 2011 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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.macro prerot dst, rt
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lsr r3, r6, #2 @ n4
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add \rt, r4, r6, lsr #1 @ revtab + n4
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add r9, r3, r3, lsl #1 @ n3
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add r8, r7, r6 @ tcos + n4
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add r3, r2, r6, lsr #1 @ in + n4
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add r9, r2, r9, lsl #1 @ in + n3
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sub r8, r8, #16
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sub r10, r3, #16
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sub r11, r9, #16
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mov r12, #-16
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1:
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vld2.16 {d0,d1}, [r9, :128]!
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vld2.16 {d2,d3}, [r11,:128], r12
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vld2.16 {d4,d5}, [r3, :128]!
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vld2.16 {d6,d7}, [r10,:128], r12
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vld2.16 {d16,d17},[r7, :128]! @ cos, sin
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vld2.16 {d18,d19},[r8, :128], r12
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vrev64.16 q1, q1
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vrev64.16 q3, q3
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vrev64.16 q9, q9
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vneg.s16 d0, d0
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vneg.s16 d2, d2
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vneg.s16 d16, d16
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vneg.s16 d18, d18
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vhsub.s16 d0, d0, d3 @ re
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vhsub.s16 d4, d7, d4 @ im
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vhsub.s16 d6, d6, d5
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vhsub.s16 d2, d2, d1
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vmull.s16 q10, d0, d16
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vmlsl.s16 q10, d4, d17
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vmull.s16 q11, d0, d17
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vmlal.s16 q11, d4, d16
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vmull.s16 q12, d6, d18
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vmlsl.s16 q12, d2, d19
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vmull.s16 q13, d6, d19
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vmlal.s16 q13, d2, d18
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vshrn.s32 d0, q10, #15
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vshrn.s32 d1, q11, #15
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vshrn.s32 d2, q12, #15
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vshrn.s32 d3, q13, #15
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vzip.16 d0, d1
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vzip.16 d2, d3
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ldrh lr, [r4], #2
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ldrh r2, [\rt, #-2]!
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add lr, \dst, lr, lsl #2
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add r2, \dst, r2, lsl #2
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vst1.32 {d0[0]}, [lr,:32]
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vst1.32 {d2[0]}, [r2,:32]
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ldrh lr, [r4], #2
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ldrh r2, [\rt, #-2]!
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add lr, \dst, lr, lsl #2
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add r2, \dst, r2, lsl #2
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vst1.32 {d0[1]}, [lr,:32]
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vst1.32 {d2[1]}, [r2,:32]
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ldrh lr, [r4], #2
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ldrh r2, [\rt, #-2]!
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add lr, \dst, lr, lsl #2
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add r2, \dst, r2, lsl #2
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vst1.32 {d1[0]}, [lr,:32]
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vst1.32 {d3[0]}, [r2,:32]
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ldrh lr, [r4], #2
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ldrh r2, [\rt, #-2]!
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add lr, \dst, lr, lsl #2
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add r2, \dst, r2, lsl #2
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vst1.32 {d1[1]}, [lr,:32]
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vst1.32 {d3[1]}, [r2,:32]
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subs r6, r6, #32
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bgt 1b
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.endm
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function ff_mdct_fixed_calc_neon, export=1
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push {r1,r4-r11,lr}
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ldr r4, [r0, #8] @ revtab
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ldr r6, [r0, #16] @ mdct_size; n
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ldr r7, [r0, #24] @ tcos
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prerot r1, r5
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mov r4, r0
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bl X(ff_fft_fixed_calc_neon)
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pop {r5}
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mov r12, #-16
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ldr r6, [r4, #16] @ mdct_size; n
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ldr r7, [r4, #24] @ tcos
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add r5, r5, r6, lsr #1
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add r7, r7, r6, lsr #1
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sub r1, r5, #16
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sub r2, r7, #16
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1:
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vld2.16 {d4,d5}, [r7,:128]!
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vld2.16 {d6,d7}, [r2,:128], r12
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vld2.16 {d0,d1}, [r5,:128]
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vld2.16 {d2,d3}, [r1,:128]
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vrev64.16 q3, q3
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vrev64.16 q1, q1
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vneg.s16 q3, q3
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vneg.s16 q2, q2
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vmull.s16 q11, d2, d6
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vmlal.s16 q11, d3, d7
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vmull.s16 q8, d0, d5
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vmlsl.s16 q8, d1, d4
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vmull.s16 q9, d0, d4
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vmlal.s16 q9, d1, d5
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vmull.s16 q10, d2, d7
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vmlsl.s16 q10, d3, d6
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vshrn.s32 d0, q11, #15
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vshrn.s32 d1, q8, #15
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vshrn.s32 d2, q9, #15
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vshrn.s32 d3, q10, #15
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vrev64.16 q0, q0
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vst2.16 {d2,d3}, [r5,:128]!
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vst2.16 {d0,d1}, [r1,:128], r12
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subs r6, r6, #32
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bgt 1b
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pop {r4-r11,pc}
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endfunc
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function ff_mdct_fixed_calcw_neon, export=1
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push {r1,r4-r11,lr}
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ldrd r4, r5, [r0, #8] @ revtab, tmp_buf
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ldr r6, [r0, #16] @ mdct_size; n
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ldr r7, [r0, #24] @ tcos
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prerot r5, r1
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mov r4, r0
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mov r1, r5
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bl X(ff_fft_fixed_calc_neon)
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pop {r7}
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mov r12, #-16
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ldr r6, [r4, #16] @ mdct_size; n
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ldr r9, [r4, #24] @ tcos
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add r5, r5, r6, lsr #1
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add r7, r7, r6
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add r9, r9, r6, lsr #1
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sub r3, r5, #16
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sub r1, r7, #16
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sub r2, r9, #16
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1:
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vld2.16 {d4,d5}, [r9,:128]!
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vld2.16 {d6,d7}, [r2,:128], r12
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vld2.16 {d0,d1}, [r5,:128]!
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vld2.16 {d2,d3}, [r3,:128], r12
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vrev64.16 q3, q3
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vrev64.16 q1, q1
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vneg.s16 q3, q3
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vneg.s16 q2, q2
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vmull.s16 q8, d2, d6
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vmlal.s16 q8, d3, d7
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vmull.s16 q9, d0, d5
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vmlsl.s16 q9, d1, d4
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vmull.s16 q10, d0, d4
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vmlal.s16 q10, d1, d5
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vmull.s16 q11, d2, d7
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vmlsl.s16 q11, d3, d6
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vrev64.32 q8, q8
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vrev64.32 q9, q9
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vst2.32 {q10,q11},[r7,:128]!
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vst2.32 {d16,d18},[r1,:128], r12
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vst2.32 {d17,d19},[r1,:128], r12
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subs r6, r6, #32
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bgt 1b
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pop {r4-r11,pc}
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endfunc
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