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i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).

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This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Plamena Manolova 2016-12-06 21:37:01 +02:00 committed by Lionel Landwerlin
parent 8481386892
commit 0ff74a8990
6 changed files with 15 additions and 4 deletions
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2
docs/features.txt
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@ -287,7 +287,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_ARB_indirect_parameters DONE (nvc0, radeonsi)
GL_ARB_parallel_shader_compile not started, but Chia-I Wu did some related work in 2014
GL_ARB_pipeline_statistics_query DONE (i965, nvc0, radeonsi, softpipe, swr)
GL_ARB_post_depth_coverage not started
GL_ARB_post_depth_coverage DONE (i965)
GL_ARB_robustness_isolation not started
GL_ARB_sample_locations not started
GL_ARB_seamless_cubemap_per_texture DONE (i965, nvc0, radeonsi, r600, softpipe, swr)

1
docs/relnotes/13.1.0.html
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@ -44,6 +44,7 @@ Note: some of the new features are only available with certain drivers.
</p>
<ul>
<li>GL_ARB_post_depth_coverage on i965/gen9+</li>
<li>GL_NV_image_formats on any driver supporting GL_ARB_shader_image_load_store (i965, nvc0, radeonsi, softpipe)</li>
</ul>

1
src/mesa/drivers/dri/i965/brw_compiler.h
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@ -397,6 +397,7 @@ struct brw_wm_prog_data {
bool computed_stencil;
bool early_fragment_tests;
bool post_depth_coverage;
bool dispatch_8;
bool dispatch_16;
bool dual_src_blend;

1
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -6454,6 +6454,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
shader->info->outputs_read);
prog_data->early_fragment_tests = shader->info->fs.early_fragment_tests;
prog_data->post_depth_coverage = shader->info->fs.post_depth_coverage;
prog_data->barycentric_interp_modes =
brw_compute_barycentric_interp_modes(compiler->devinfo, shader);

13
src/mesa/drivers/dri/i965/gen8_ps_state.c
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@ -53,10 +53,17 @@ gen8_upload_ps_extra(struct brw_context *brw,
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
if (prog_data->uses_sample_mask) {
if (brw->gen >= 9)
dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
else
if (brw->gen >= 9) {
if (prog_data->post_depth_coverage) {
dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
}
else {
dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
}
}
else {
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
}
}
if (prog_data->uses_omask)

1
src/mesa/drivers/dri/i965/intel_extensions.c
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@ -415,6 +415,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.KHR_texture_compression_astc_ldr = true;
ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
ctx->Extensions.MESA_shader_framebuffer_fetch = true;
ctx->Extensions.ARB_post_depth_coverage = true;
}
if (ctx->API == API_OPENGL_CORE)