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vc4: Switch to using the libdrm-provided vc4_drm.h.
The required version is set to .69 for the getparam ioctl that will be used in the next commit.
This commit is contained in:
Eric Anholt
parent
3d8c29ed32
commit
16985eb308
@ -75,6 +75,7 @@ LIBDRM_INTEL_REQUIRED=2.4.61
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LIBDRM_NVVIEUX_REQUIRED=2.4.66
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LIBDRM_NOUVEAU_REQUIRED=2.4.66
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LIBDRM_FREEDRENO_REQUIRED=2.4.67
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LIBDRM_VC4_REQUIRED=2.4.69
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DRI2PROTO_REQUIRED=2.6
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DRI3PROTO_REQUIRED=1.0
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PRESENTPROTO_REQUIRED=1.0
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@ -2467,6 +2468,7 @@ if test -n "$with_gallium_drivers"; then
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;;
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xvc4)
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HAVE_GALLIUM_VC4=yes
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PKG_CHECK_MODULES([VC4], [libdrm_vc4 >= $LIBDRM_VC4_REQUIRED])
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gallium_require_drm "vc4"
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gallium_require_drm_loader
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@ -29,6 +29,7 @@ endif
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AM_CFLAGS = \
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-I$(top_builddir)/src/compiler/nir \
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$(LIBDRM_CFLAGS) \
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$(VC4_CFLAGS) \
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$(GALLIUM_DRIVER_CFLAGS) \
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$(SIM_CFLAGS) \
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$()
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@ -36,5 +37,5 @@ AM_CFLAGS = \
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noinst_LTLIBRARIES = libvc4.la
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libvc4_la_SOURCES = $(C_SOURCES)
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libvc4_la_LIBADD = $(SIM_LIB)
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libvc4_la_LIBADD = $(SIM_LIB) $(VC4_LIBS)
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libvc4_la_LDFLAGS = $(SIM_LDFLAGS)
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@ -1,279 +0,0 @@
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/*
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* Copyright © 2014-2015 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef _UAPI_VC4_DRM_H_
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#define _UAPI_VC4_DRM_H_
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#include <drm.h>
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#define DRM_VC4_SUBMIT_CL 0x00
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#define DRM_VC4_WAIT_SEQNO 0x01
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#define DRM_VC4_WAIT_BO 0x02
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#define DRM_VC4_CREATE_BO 0x03
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#define DRM_VC4_MMAP_BO 0x04
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#define DRM_VC4_CREATE_SHADER_BO 0x05
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#define DRM_VC4_GET_HANG_STATE 0x06
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#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
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#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
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#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
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#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
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#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
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#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
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#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
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struct drm_vc4_submit_rcl_surface {
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uint32_t hindex; /* Handle index, or ~0 if not present. */
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uint32_t offset; /* Offset to start of buffer. */
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/*
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* Bits for either render config (color_write) or load/store packet.
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* Bits should all be 0 for MSAA load/stores.
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*/
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uint16_t bits;
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#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
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uint16_t flags;
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};
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/**
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* struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
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* engine.
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*
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* Drivers typically use GPU BOs to store batchbuffers / command lists and
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* their associated state. However, because the VC4 lacks an MMU, we have to
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* do validation of memory accesses by the GPU commands. If we were to store
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* our commands in BOs, we'd need to do uncached readback from them to do the
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* validation process, which is too expensive. Instead, userspace accumulates
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* commands and associated state in plain memory, then the kernel copies the
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* data to its own address space, and then validates and stores it in a GPU
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* BO.
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*/
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struct drm_vc4_submit_cl {
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/* Pointer to the binner command list.
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*
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* This is the first set of commands executed, which runs the
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* coordinate shader to determine where primitives land on the screen,
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* then writes out the state updates and draw calls necessary per tile
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* to the tile allocation BO.
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*/
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uint64_t bin_cl;
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/* Pointer to the shader records.
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*
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* Shader records are the structures read by the hardware that contain
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* pointers to uniforms, shaders, and vertex attributes. The
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* reference to the shader record has enough information to determine
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* how many pointers are necessary (fixed number for shaders/uniforms,
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* and an attribute count), so those BO indices into bo_handles are
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* just stored as uint32_ts before each shader record passed in.
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*/
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uint64_t shader_rec;
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/* Pointer to uniform data and texture handles for the textures
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* referenced by the shader.
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*
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* For each shader state record, there is a set of uniform data in the
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* order referenced by the record (FS, VS, then CS). Each set of
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* uniform data has a uint32_t index into bo_handles per texture
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* sample operation, in the order the QPU_W_TMUn_S writes appear in
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* the program. Following the texture BO handle indices is the actual
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* uniform data.
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*
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* The individual uniform state blocks don't have sizes passed in,
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* because the kernel has to determine the sizes anyway during shader
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* code validation.
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*/
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uint64_t uniforms;
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uint64_t bo_handles;
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/* Size in bytes of the binner command list. */
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uint32_t bin_cl_size;
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/* Size in bytes of the set of shader records. */
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uint32_t shader_rec_size;
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/* Number of shader records.
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*
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* This could just be computed from the contents of shader_records and
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* the address bits of references to them from the bin CL, but it
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* keeps the kernel from having to resize some allocations it makes.
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*/
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uint32_t shader_rec_count;
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/* Size in bytes of the uniform state. */
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uint32_t uniforms_size;
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/* Number of BO handles passed in (size is that times 4). */
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uint32_t bo_handle_count;
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/* RCL setup: */
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uint16_t width;
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uint16_t height;
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uint8_t min_x_tile;
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uint8_t min_y_tile;
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uint8_t max_x_tile;
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uint8_t max_y_tile;
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struct drm_vc4_submit_rcl_surface color_read;
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struct drm_vc4_submit_rcl_surface color_write;
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struct drm_vc4_submit_rcl_surface zs_read;
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struct drm_vc4_submit_rcl_surface zs_write;
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struct drm_vc4_submit_rcl_surface msaa_color_write;
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struct drm_vc4_submit_rcl_surface msaa_zs_write;
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uint32_t clear_color[2];
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uint32_t clear_z;
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uint8_t clear_s;
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uint32_t pad:24;
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#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
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uint32_t flags;
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/* Returned value of the seqno of this render job (for the
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* wait ioctl).
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*/
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uint64_t seqno;
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};
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/**
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* struct drm_vc4_wait_seqno - ioctl argument for waiting for
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* DRM_VC4_SUBMIT_CL completion using its returned seqno.
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*
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* timeout_ns is the timeout in nanoseconds, where "0" means "don't
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* block, just return the status."
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*/
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struct drm_vc4_wait_seqno {
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uint64_t seqno;
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uint64_t timeout_ns;
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};
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/**
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* struct drm_vc4_wait_bo - ioctl argument for waiting for
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* completion of the last DRM_VC4_SUBMIT_CL on a BO.
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*
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* This is useful for cases where multiple processes might be
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* rendering to a BO and you want to wait for all rendering to be
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* completed.
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*/
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struct drm_vc4_wait_bo {
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uint32_t handle;
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uint32_t pad;
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uint64_t timeout_ns;
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};
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/**
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* struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
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*
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* There are currently no values for the flags argument, but it may be
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* used in a future extension.
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*/
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struct drm_vc4_create_bo {
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uint32_t size;
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uint32_t flags;
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/** Returned GEM handle for the BO. */
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uint32_t handle;
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uint32_t pad;
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};
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/**
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* struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
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* shader BOs.
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*
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* Since allowing a shader to be overwritten while it's also being
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* executed from would allow privlege escalation, shaders must be
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* created using this ioctl, and they can't be mmapped later.
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*/
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struct drm_vc4_create_shader_bo {
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/* Size of the data argument. */
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uint32_t size;
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/* Flags, currently must be 0. */
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uint32_t flags;
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/* Pointer to the data. */
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uint64_t data;
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/** Returned GEM handle for the BO. */
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uint32_t handle;
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/* Pad, must be 0. */
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uint32_t pad;
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};
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/**
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* struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
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*
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* This doesn't actually perform an mmap. Instead, it returns the
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* offset you need to use in an mmap on the DRM device node. This
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* means that tools like valgrind end up knowing about the mapped
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* memory.
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*
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* There are currently no values for the flags argument, but it may be
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* used in a future extension.
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*/
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struct drm_vc4_mmap_bo {
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/** Handle for the object being mapped. */
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uint32_t handle;
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uint32_t flags;
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/** offset into the drm node to use for subsequent mmap call. */
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uint64_t offset;
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};
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struct drm_vc4_get_hang_state_bo {
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uint32_t handle;
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uint32_t paddr;
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uint32_t size;
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uint32_t pad;
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};
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/**
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* struct drm_vc4_hang_state - ioctl argument for collecting state
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* from a GPU hang for analysis.
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*/
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struct drm_vc4_get_hang_state {
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/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
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uint64_t bo;
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/**
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* On input, the size of the bo array. Output is the number
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* of bos to be returned.
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*/
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uint32_t bo_count;
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uint32_t start_bin, start_render;
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uint32_t ct0ca, ct0ea;
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uint32_t ct1ca, ct1ea;
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uint32_t ct0cs, ct1cs;
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uint32_t ct0ra0, ct1ra0;
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uint32_t bpca, bpcs;
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uint32_t bpoa, bpos;
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uint32_t vpmbase;
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uint32_t dbge;
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uint32_t fdbgo;
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uint32_t fdbgb;
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uint32_t fdbgr;
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uint32_t fdbgs;
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uint32_t errstat;
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/* Pad that we may save more registers into in the future. */
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uint32_t pad[16];
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};
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#endif /* _UAPI_VC4_DRM_H_ */
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