openharmony/third_party_mesa3d
1
0
Fork 0
mirror of https://gitee.com/openharmony/third_party_mesa3d synced 2024-11-24 16:00:56 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

i965: Remove check for hiz on earlier gens than SNB

Browse Source 
Only caller, brw_workaround_depthstencil_alignment(), returns
early for gen6+.

While at it, reduce scope for brw_get_depthstencil_tile_masks() as
well.

Reviewed-by: Samuel Iglesias Gons\341lvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen 2016-12-28 17:49:56 +02:00
parent 26a9e039fd
commit 19412abb3f
2 changed files with 2 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -1246,12 +1246,6 @@ brw_meta_resolve_color(struct brw_context *brw,
/*======================================================================
* brw_misc_state.c
*/
void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
uint32_t depth_level,
uint32_t depth_layer,
struct intel_mipmap_tree *stencil_mt,
uint32_t *out_tile_mask_x,
uint32_t *out_tile_mask_y);
void brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask);

18
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@ -165,7 +165,7 @@ brw_depthbuffer_format(struct brw_context *brw)
* packet. If the 3 buffers don't agree on the drawing offset ANDed with this
* mask, then we're in trouble.
*/
void
static void
brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
uint32_t depth_level,
uint32_t depth_layer,
@ -179,21 +179,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
depth_mt->cpp,
&tile_mask_x, &tile_mask_y);
if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
intel_get_tile_masks(depth_mt->hiz_buf->mt->tiling,
depth_mt->hiz_buf->mt->tr_mode,
depth_mt->hiz_buf->mt->cpp,
&hiz_tile_mask_x,
&hiz_tile_mask_y);
/* Each HiZ row represents 2 rows of pixels */
hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;
tile_mask_x |= hiz_tile_mask_x;
tile_mask_y |= hiz_tile_mask_y;
}
assert(!intel_miptree_level_has_hiz(depth_mt, depth_level));
}
if (stencil_mt) {