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intel: Remove Gen10-specific device entries

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The enables removal of gen_device_info::is_cannonlake.

v2: Remove GEN10_FEATURES and GEN10_HW_INFO macros.  Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>
This commit is contained in:
Ian Romanick 2020-10-07 10:28:47 -07:00
parent b0e3af4fb8
commit 19aaafd4a6
3 changed files with 0 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
include/pci_ids/i965_pci_ids.h
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@ -229,19 +229,6 @@ CHIPSET(0x9BCC, cfl_gt2, "CML GT2", "Intel(R) UHD Graphics")
CHIPSET(0x9BE6, cfl_gt2, "CML GT2", "Intel(R) UHD Graphics P630")
CHIPSET(0x9BF6, cfl_gt2, "CML GT2", "Intel(R) UHD Graphics P630")
CHIPSET(0x5A49, cnl_gt0_5, "CNL GT0.5", "Intel(R) HD Graphics")
CHIPSET(0x5A4A, cnl_gt0_5, "CNL GT0.5", "Intel(R) HD Graphics")
CHIPSET(0x5A41, cnl_gt1, "CNL GT1", "Intel(R) HD Graphics")
CHIPSET(0x5A42, cnl_gt1, "CNL GT1", "Intel(R) HD Graphics")
CHIPSET(0x5A44, cnl_gt1, "CNL GT1", "Intel(R) HD Graphics")
CHIPSET(0x5A59, cnl_gt1_5, "CNL GT1.5", "Intel(R) HD Graphics")
CHIPSET(0x5A5A, cnl_gt1_5, "CNL GT1.5", "Intel(R) HD Graphics")
CHIPSET(0x5A5C, cnl_gt1_5, "CNL GT1.5", "Intel(R) HD Graphics")
CHIPSET(0x5A50, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
CHIPSET(0x5A51, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
CHIPSET(0x5A52, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
CHIPSET(0x5A54, cnl_gt2, "CNL GT2", "Intel(R) HD Graphics")
CHIPSET(0x8A50, icl_gt2, "ICL GT2", "Intel(R) HD Graphics")
CHIPSET(0x8A51, icl_gt2, "ICL GT2", "Intel(R) Iris(R) Plus Graphics")
CHIPSET(0x8A52, icl_gt2, "ICL GT2", "Intel(R) Iris(R) Plus Graphics")

61
src/intel/dev/gen_device_info.c
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@ -57,7 +57,6 @@ static const struct {
{ "cfl", 0x3E9B },
{ "whl", 0x3EA1 },
{ "cml", 0x9b41 },
{ "cnl", 0x5a52 },
{ "icl", 0x8a52 },
{ "ehl", 0x4500 },
{ "jsl", 0x4E71 },
@ -790,68 +789,8 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = {
.simulator_id = 24,
};
#define GEN10_HW_INFO \
.gen = 10, \
.num_thread_per_eu = 7, \
.max_vs_threads = 728, \
.max_gs_threads = 432, \
.max_tcs_threads = 432, \
.max_tes_threads = 624, \
.max_cs_threads = 56, \
.timestamp_frequency = 19200000, \
.urb = { \
.min_entries = { \
[MESA_SHADER_VERTEX] = 64, \
[MESA_SHADER_TESS_EVAL] = 34, \
}, \
.max_entries = { \
[MESA_SHADER_VERTEX] = 3936, \
[MESA_SHADER_TESS_CTRL] = 896, \
[MESA_SHADER_TESS_EVAL] = 2064, \
[MESA_SHADER_GEOMETRY] = 832, \
}, \
}
#define subslices(args...) { args, }
#define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
GEN10_HW_INFO, \
.has_sample_with_hiz = true, \
.gt = _gt, \
.num_slices = _slices, \
.num_subslices = _subslices, \
.num_eu_per_subslice = 8, \
.l3_banks = _l3
static const struct gen_device_info gen_device_info_cnl_gt0_5 = {
/* GT0.5 */
GEN10_FEATURES(1, 1, subslices(2), 2),
.is_cannonlake = true,
.simulator_id = 15,
};
static const struct gen_device_info gen_device_info_cnl_gt1 = {
/* GT1 */
GEN10_FEATURES(1, 1, subslices(3), 3),
.is_cannonlake = true,
.simulator_id = 15,
};
static const struct gen_device_info gen_device_info_cnl_gt1_5 = {
/* GT 1.5 */
GEN10_FEATURES(1, 2, subslices(2, 2), 6),
.is_cannonlake = true,
.simulator_id = 15,
};
static const struct gen_device_info gen_device_info_cnl_gt2 = {
/* GT2 */
GEN10_FEATURES(2, 2, subslices(3, 2), 6),
.is_cannonlake = true,
.simulator_id = 15,
};
#define GEN11_HW_INFO \
.gen = 11, \
.has_pln = false, \

1
src/intel/dev/gen_device_info.h
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@ -61,7 +61,6 @@ struct gen_device_info
bool is_kabylake;
bool is_geminilake;
bool is_coffeelake;
bool is_cannonlake;
bool is_elkhartlake;
bool is_dg1;