mirror of
https://gitee.com/openharmony/third_party_mesa3d
synced 2024-11-24 16:00:56 +00:00
r300: Fix saturate mode handling in radeon_program_alu
This commit is contained in:
Nicolai Haehnle
parent
cf0ae102db
commit
2d766923c4
@ -39,24 +39,26 @@
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static struct prog_instruction *emit1(struct gl_program* p,
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gl_inst_opcode Opcode, struct prog_dst_register DstReg,
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gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg,
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struct prog_src_register SrcReg)
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{
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struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
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fpi->Opcode = Opcode;
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fpi->SaturateMode = Saturate;
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fpi->DstReg = DstReg;
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fpi->SrcReg[0] = SrcReg;
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return fpi;
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}
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static struct prog_instruction *emit2(struct gl_program* p,
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gl_inst_opcode Opcode, struct prog_dst_register DstReg,
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gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg,
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struct prog_src_register SrcReg0, struct prog_src_register SrcReg1)
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{
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struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
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fpi->Opcode = Opcode;
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fpi->SaturateMode = Saturate;
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fpi->DstReg = DstReg;
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fpi->SrcReg[0] = SrcReg0;
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fpi->SrcReg[1] = SrcReg1;
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@ -64,13 +66,14 @@ static struct prog_instruction *emit2(struct gl_program* p,
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}
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static struct prog_instruction *emit3(struct gl_program* p,
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gl_inst_opcode Opcode, struct prog_dst_register DstReg,
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gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg,
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struct prog_src_register SrcReg0, struct prog_src_register SrcReg1,
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struct prog_src_register SrcReg2)
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{
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struct prog_instruction *fpi = radeonAppendInstructions(p, 1);
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fpi->Opcode = Opcode;
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fpi->SaturateMode = Saturate;
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fpi->DstReg = DstReg;
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fpi->SrcReg[0] = SrcReg0;
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fpi->SrcReg[1] = SrcReg1;
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@ -188,7 +191,7 @@ static void transform_ABS(struct radeon_transform_context* t,
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src.Abs = 1;
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src.NegateBase = 0;
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src.NegateAbs = 0;
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emit1(t->Program, OPCODE_MOV, inst->DstReg, src);
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emit1(t->Program, OPCODE_MOV, inst->SaturateMode, inst->DstReg, src);
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}
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static void transform_DPH(struct radeon_transform_context* t,
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@ -198,7 +201,7 @@ static void transform_DPH(struct radeon_transform_context* t,
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if (src0.NegateAbs) {
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if (src0.Abs) {
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int tempreg = radeonFindFreeTemporary(t);
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emit1(t->Program, OPCODE_MOV, dstreg(PROGRAM_TEMPORARY, tempreg), src0);
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emit1(t->Program, OPCODE_MOV, 0, dstreg(PROGRAM_TEMPORARY, tempreg), src0);
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src0 = srcreg(src0.File, src0.Index);
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} else {
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src0.NegateAbs = 0;
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@ -207,7 +210,7 @@ static void transform_DPH(struct radeon_transform_context* t,
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}
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set_swizzle(&src0, 3, SWIZZLE_ONE);
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set_negate_base(&src0, 3, 0);
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emit2(t->Program, OPCODE_DP4, inst->DstReg, src0, inst->SrcReg[1]);
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emit2(t->Program, OPCODE_DP4, inst->SaturateMode, inst->DstReg, src0, inst->SrcReg[1]);
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}
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/**
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@ -217,7 +220,7 @@ static void transform_DPH(struct radeon_transform_context* t,
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static void transform_DST(struct radeon_transform_context* t,
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struct prog_instruction* inst)
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{
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emit2(t->Program, OPCODE_MUL, inst->DstReg,
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emit2(t->Program, OPCODE_MUL, inst->SaturateMode, inst->DstReg,
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swizzle(inst->SrcReg[0], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE),
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swizzle(inst->SrcReg[1], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_ONE, SWIZZLE_W));
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}
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@ -226,8 +229,9 @@ static void transform_FLR(struct radeon_transform_context* t,
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struct prog_instruction* inst)
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{
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int tempreg = radeonFindFreeTemporary(t);
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emit1(t->Program, OPCODE_FRC, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]);
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emit2(t->Program, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
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emit1(t->Program, OPCODE_FRC, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]);
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emit2(t->Program, OPCODE_ADD, inst->SaturateMode, inst->DstReg,
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inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
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}
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/**
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@ -279,42 +283,42 @@ static void transform_LIT(struct radeon_transform_context* t,
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// tmp.x = max(0.0, Src.x);
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// tmp.y = max(0.0, Src.y);
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// tmp.w = clamp(Src.z, -128+eps, 128-eps);
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emit2(t->Program, OPCODE_MAX,
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emit2(t->Program, OPCODE_MAX, 0,
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dstregtmpmask(temp, WRITEMASK_XYW),
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inst->SrcReg[0],
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swizzle(srcreg(PROGRAM_CONSTANT, constant),
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SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, constant_swizzle&3));
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emit2(t->Program, OPCODE_MIN,
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emit2(t->Program, OPCODE_MIN, 0,
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dstregtmpmask(temp, WRITEMASK_Z),
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swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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negate(srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle)));
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// tmp.w = Pow(tmp.y, tmp.w)
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emit1(t->Program, OPCODE_LG2,
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emit1(t->Program, OPCODE_LG2, 0,
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dstregtmpmask(temp, WRITEMASK_W),
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swizzle(srctemp, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
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emit2(t->Program, OPCODE_MUL,
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emit2(t->Program, OPCODE_MUL, 0,
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dstregtmpmask(temp, WRITEMASK_W),
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swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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swizzle(srctemp, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z));
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emit1(t->Program, OPCODE_EX2,
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emit1(t->Program, OPCODE_EX2, 0,
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dstregtmpmask(temp, WRITEMASK_W),
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swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
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// tmp.z = (tmp.x > 0) ? tmp.w : 0.0
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emit3(t->Program, OPCODE_CMP,
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emit3(t->Program, OPCODE_CMP, inst->SaturateMode,
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dstregtmpmask(temp, WRITEMASK_Z),
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negate(swizzle(srctemp, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
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swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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builtin_zero);
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// tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0
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emit1(t->Program, OPCODE_MOV,
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emit1(t->Program, OPCODE_MOV, inst->SaturateMode,
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dstregtmpmask(temp, WRITEMASK_XYW),
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swizzle(srctemp, SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE));
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if (needTemporary)
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emit1(t->Program, OPCODE_MOV, inst->DstReg, srctemp);
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emit1(t->Program, OPCODE_MOV, 0, inst->DstReg, srctemp);
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}
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static void transform_LRP(struct radeon_transform_context* t,
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@ -322,10 +326,10 @@ static void transform_LRP(struct radeon_transform_context* t,
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{
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int tempreg = radeonFindFreeTemporary(t);
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emit2(t->Program, OPCODE_ADD,
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emit2(t->Program, OPCODE_ADD, 0,
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dstreg(PROGRAM_TEMPORARY, tempreg),
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inst->SrcReg[1], negate(inst->SrcReg[2]));
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emit3(t->Program, OPCODE_MAD,
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emit3(t->Program, OPCODE_MAD, inst->SaturateMode,
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inst->DstReg,
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inst->SrcReg[0], srcreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[2]);
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}
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@ -339,15 +343,15 @@ static void transform_POW(struct radeon_transform_context* t,
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tempdst.WriteMask = WRITEMASK_W;
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tempsrc.Swizzle = SWIZZLE_WWWW;
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emit1(t->Program, OPCODE_LG2, tempdst, scalar(inst->SrcReg[0]));
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emit2(t->Program, OPCODE_MUL, tempdst, tempsrc, scalar(inst->SrcReg[1]));
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emit1(t->Program, OPCODE_EX2, inst->DstReg, tempsrc);
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emit1(t->Program, OPCODE_LG2, 0, tempdst, scalar(inst->SrcReg[0]));
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emit2(t->Program, OPCODE_MUL, 0, tempdst, tempsrc, scalar(inst->SrcReg[1]));
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emit1(t->Program, OPCODE_EX2, inst->SaturateMode, inst->DstReg, tempsrc);
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}
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static void transform_RSQ(struct radeon_transform_context* t,
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struct prog_instruction* inst)
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{
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emit1(t->Program, OPCODE_RSQ, inst->DstReg, absolute(inst->SrcReg[0]));
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emit1(t->Program, OPCODE_RSQ, inst->SaturateMode, inst->DstReg, absolute(inst->SrcReg[0]));
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}
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static void transform_SGE(struct radeon_transform_context* t,
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@ -355,8 +359,9 @@ static void transform_SGE(struct radeon_transform_context* t,
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{
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int tempreg = radeonFindFreeTemporary(t);
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emit2(t->Program, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
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emit3(t->Program, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_zero, builtin_one);
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emit2(t->Program, OPCODE_ADD, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
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emit3(t->Program, OPCODE_CMP, inst->SaturateMode, inst->DstReg,
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srcreg(PROGRAM_TEMPORARY, tempreg), builtin_zero, builtin_one);
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}
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static void transform_SLT(struct radeon_transform_context* t,
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@ -364,20 +369,21 @@ static void transform_SLT(struct radeon_transform_context* t,
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{
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int tempreg = radeonFindFreeTemporary(t);
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emit2(t->Program, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
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emit3(t->Program, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_one, builtin_zero);
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emit2(t->Program, OPCODE_ADD, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1]));
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emit3(t->Program, OPCODE_CMP, inst->SaturateMode, inst->DstReg,
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srcreg(PROGRAM_TEMPORARY, tempreg), builtin_one, builtin_zero);
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}
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static void transform_SUB(struct radeon_transform_context* t,
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struct prog_instruction* inst)
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{
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emit2(t->Program, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(inst->SrcReg[1]));
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emit2(t->Program, OPCODE_ADD, inst->SaturateMode, inst->DstReg, inst->SrcReg[0], negate(inst->SrcReg[1]));
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}
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static void transform_SWZ(struct radeon_transform_context* t,
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struct prog_instruction* inst)
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{
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emit1(t->Program, OPCODE_MOV, inst->DstReg, inst->SrcReg[0]);
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emit1(t->Program, OPCODE_MOV, inst->SaturateMode, inst->DstReg, inst->SrcReg[0]);
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}
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static void transform_XPD(struct radeon_transform_context* t,
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@ -385,10 +391,10 @@ static void transform_XPD(struct radeon_transform_context* t,
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{
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int tempreg = radeonFindFreeTemporary(t);
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emit2(t->Program, OPCODE_MUL, dstreg(PROGRAM_TEMPORARY, tempreg),
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emit2(t->Program, OPCODE_MUL, 0, dstreg(PROGRAM_TEMPORARY, tempreg),
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swizzle(inst->SrcReg[0], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W),
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swizzle(inst->SrcReg[1], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W));
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emit3(t->Program, OPCODE_MAD, inst->DstReg,
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emit3(t->Program, OPCODE_MAD, inst->SaturateMode, inst->DstReg,
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swizzle(inst->SrcReg[0], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W),
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swizzle(inst->SrcReg[1], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W),
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negate(srcreg(PROGRAM_TEMPORARY, tempreg)));
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@ -471,18 +477,18 @@ static void sin_approx(struct radeon_transform_context* t,
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{
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GLuint tempreg = radeonFindFreeTemporary(t);
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emit2(t->Program, OPCODE_MUL, dstregtmpmask(tempreg, WRITEMASK_XY),
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emit2(t->Program, OPCODE_MUL, 0, dstregtmpmask(tempreg, WRITEMASK_XY),
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swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
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srcreg(PROGRAM_CONSTANT, constants[0]));
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emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_X),
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emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_X),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
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absolute(swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
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emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_Y),
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emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_Y),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
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absolute(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)),
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negate(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)));
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emit3(t->Program, OPCODE_MAD, dst,
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emit3(t->Program, OPCODE_MAD, 0, dst,
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
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@ -511,13 +517,13 @@ GLboolean radeonTransformTrigSimple(struct radeon_transform_context* t,
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// MAD tmp.x, src, 1/(2*PI), 0.75
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// FRC tmp.x, tmp.x
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// MAD tmp.z, tmp.x, 2*PI, -PI
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emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
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emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W),
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swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X));
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emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_W),
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emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(tempreg, WRITEMASK_W),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
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emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
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emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
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@ -526,13 +532,13 @@ GLboolean radeonTransformTrigSimple(struct radeon_transform_context* t,
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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constants);
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} else if (inst->Opcode == OPCODE_SIN) {
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emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
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emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W),
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swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y));
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emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_W),
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emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(tempreg, WRITEMASK_W),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W));
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emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_W),
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emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W),
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swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
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negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
|
||||
@ -541,13 +547,13 @@ GLboolean radeonTransformTrigSimple(struct radeon_transform_context* t,
|
||||
swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
|
||||
constants);
|
||||
} else {
|
||||
emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_XY),
|
||||
emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_XY),
|
||||
swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
|
||||
swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z),
|
||||
swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W));
|
||||
emit1(t->Program, OPCODE_FRC, dstregtmpmask(tempreg, WRITEMASK_XY),
|
||||
emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(tempreg, WRITEMASK_XY),
|
||||
srcreg(PROGRAM_TEMPORARY, tempreg));
|
||||
emit3(t->Program, OPCODE_MAD, dstregtmpmask(tempreg, WRITEMASK_XY),
|
||||
emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_XY),
|
||||
srcreg(PROGRAM_TEMPORARY, tempreg),
|
||||
swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W),
|
||||
negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)));
|
||||
@ -594,26 +600,30 @@ GLboolean radeonTransformTrigScale(struct radeon_transform_context* t,
|
||||
temp = radeonFindFreeTemporary(t);
|
||||
constant = _mesa_add_unnamed_constant(t->Program->Parameters, RCP_2PI, 1, &constant_swizzle);
|
||||
|
||||
emit2(t->Program, OPCODE_MUL, dstregtmpmask(temp, WRITEMASK_W),
|
||||
emit2(t->Program, OPCODE_MUL, 0, dstregtmpmask(temp, WRITEMASK_W),
|
||||
swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
|
||||
srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle));
|
||||
emit1(t->Program, OPCODE_FRC, dstregtmpmask(temp, WRITEMASK_W),
|
||||
emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(temp, WRITEMASK_W),
|
||||
srcreg(PROGRAM_TEMPORARY, temp));
|
||||
|
||||
if (inst->Opcode == OPCODE_COS) {
|
||||
emit1(t->Program, OPCODE_COS, inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
emit1(t->Program, OPCODE_COS, inst->SaturateMode, inst->DstReg,
|
||||
srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
} else if (inst->Opcode == OPCODE_SIN) {
|
||||
emit1(t->Program, OPCODE_SIN, inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
emit1(t->Program, OPCODE_SIN, inst->SaturateMode,
|
||||
inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
} else if (inst->Opcode == OPCODE_SCS) {
|
||||
struct prog_dst_register moddst = inst->DstReg;
|
||||
|
||||
if (inst->DstReg.WriteMask & WRITEMASK_X) {
|
||||
moddst.WriteMask = WRITEMASK_X;
|
||||
emit1(t->Program, OPCODE_COS, moddst, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
emit1(t->Program, OPCODE_COS, inst->SaturateMode, moddst,
|
||||
srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
}
|
||||
if (inst->DstReg.WriteMask & WRITEMASK_Y) {
|
||||
moddst.WriteMask = WRITEMASK_Y;
|
||||
emit1(t->Program, OPCODE_SIN, moddst, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
emit1(t->Program, OPCODE_SIN, inst->SaturateMode, moddst,
|
||||
srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user