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aco/isel: Fix i64/u64->float32 conversion for large inputs

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Previously, inputs such as 0x100000000 would have their upper 32-bits
ignored despite being representable by 32-bit floats.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9597>
This commit is contained in:
Tony Wasserka 2021-03-15 12:26:51 +01:00 committed by Marge Bot
parent 436922c84a
commit 3a2b055726
1 changed files with 33 additions and 6 deletions
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39
src/amd/compiler/aco_instruction_selection.cpp
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@ -2444,9 +2444,25 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
case nir_op_i2f32: {
assert(dst.size() == 1);
Temp src = get_alu_src(ctx, instr->src[0]);
if (instr->src[0].src.ssa->bit_size <= 16)
src = convert_int(ctx, bld, src, instr->src[0].src.ssa->bit_size, 32, true);
bld.vop1(aco_opcode::v_cvt_f32_i32, Definition(dst), src);
const unsigned input_size = instr->src[0].src.ssa->bit_size;
if (input_size <= 32) {
if (input_size <= 16) {
/* Sign-extend to 32-bits */
src = convert_int(ctx, bld, src, input_size, 32, true);
}
bld.vop1(aco_opcode::v_cvt_f32_i32, Definition(dst), src);
} else {
assert(input_size == 64);
RegClass rc = RegClass(src.type(), 1);
Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
upper = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), lower, upper);
bld.vop1(aco_opcode::v_cvt_f32_f64, Definition(dst), upper);
}
break;
}
case nir_op_i2f64: {
@ -2496,12 +2512,23 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
case nir_op_u2f32: {
assert(dst.size() == 1);
Temp src = get_alu_src(ctx, instr->src[0]);
if (instr->src[0].src.ssa->bit_size == 8) {
const unsigned input_size = instr->src[0].src.ssa->bit_size;
if (input_size == 8) {
bld.vop1(aco_opcode::v_cvt_f32_ubyte0, Definition(dst), src);
} else {
if (instr->src[0].src.ssa->bit_size == 16)
} else if (input_size <= 32) {
if (input_size == 16)
src = convert_int(ctx, bld, src, instr->src[0].src.ssa->bit_size, 32, true);
bld.vop1(aco_opcode::v_cvt_f32_u32, Definition(dst), src);
} else {
assert(input_size == 64);
RegClass rc = RegClass(src.type(), 1);
Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
upper = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), lower, upper);
bld.vop1(aco_opcode::v_cvt_f32_f64, Definition(dst), upper);
}
break;
}