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https://gitee.com/openharmony/third_party_mesa3d
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drm-uapi: Update headers from drm-next
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Jason Ekstrand
parent
ae8365a9eb
commit
3cd26d981b
@ -10,9 +10,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
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The last update was done at the following kernel commit :
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commit 6d61e70ccc21606ffb8a0a03bd3aba24f659502b
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Merge: 338ffbf7cb5e c0bc126f97fb
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commit 7846b12fe0b5feab5446d892f41b5140c1419109
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Merge: 7ebdb0d d78acfe
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Author: Dave Airlie <airlied@redhat.com>
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Date: Tue Jun 27 07:24:49 2017 +1000
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Date: Tue Aug 29 10:38:14 2017 +1000
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Backmerge tag 'v4.12-rc7' into drm-next
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Merge branch 'drm-vmwgfx-next' of git://people.freedesktop.org/~syeh/repos_linux into drm-next
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@ -694,6 +694,7 @@ struct drm_prime_handle {
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struct drm_syncobj_create {
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__u32 handle;
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#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
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__u32 flags;
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};
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@ -712,6 +713,24 @@ struct drm_syncobj_handle {
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__u32 pad;
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};
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
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struct drm_syncobj_wait {
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__u64 handles;
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/* absolute timeout */
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__s64 timeout_nsec;
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__u32 count_handles;
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__u32 flags;
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__u32 first_signaled; /* only valid when not waiting all */
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__u32 pad;
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};
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struct drm_syncobj_array {
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__u64 handles;
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__u32 count_handles;
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__u32 pad;
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};
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#if defined(__cplusplus)
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}
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#endif
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@ -834,6 +853,9 @@ extern "C" {
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#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
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#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
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#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
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#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
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#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
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#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
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/**
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* Device specific ioctls should only be in their respective headers
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@ -712,6 +712,56 @@ struct drm_mode_atomic {
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__u64 user_data;
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};
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struct drm_format_modifier_blob {
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#define FORMAT_BLOB_CURRENT 1
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/* Version of this blob format */
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__u32 version;
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/* Flags */
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__u32 flags;
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/* Number of fourcc formats supported */
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__u32 count_formats;
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/* Where in this blob the formats exist (in bytes) */
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__u32 formats_offset;
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/* Number of drm_format_modifiers */
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__u32 count_modifiers;
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/* Where in this blob the modifiers exist (in bytes) */
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__u32 modifiers_offset;
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/* __u32 formats[] */
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/* struct drm_format_modifier modifiers[] */
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};
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struct drm_format_modifier {
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/* Bitmask of formats in get_plane format list this info applies to. The
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* offset allows a sliding window of which 64 formats (bits).
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*
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* Some examples:
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* In today's world with < 65 formats, and formats 0, and 2 are
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* supported
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* 0x0000000000000005
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* ^-offset = 0, formats = 5
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*
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* If the number formats grew to 128, and formats 98-102 are
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* supported with the modifier:
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*
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* 0x0000003c00000000 0000000000000000
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* ^
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* |__offset = 64, formats = 0x3c00000000
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*
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*/
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__u64 formats;
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__u32 offset;
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__u32 pad;
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/* The modifier that applies to the >get_plane format list bitmask. */
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__u64 modifier;
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};
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/**
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* Create a new 'blob' data property, copying length bytes from data pointer,
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* and returning new blob ID.
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@ -260,6 +260,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
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#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
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#define DRM_I915_PERF_OPEN 0x36
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#define DRM_I915_PERF_ADD_CONFIG 0x37
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#define DRM_I915_PERF_REMOVE_CONFIG 0x38
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@ -315,6 +317,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
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#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
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#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
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#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
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#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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* on the security mechanisms provided by hardware.
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@ -819,7 +823,7 @@ struct drm_i915_gem_exec_object2 {
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struct drm_i915_gem_exec_fence {
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/**
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* User's handle for a dma-fence to wait on or signal.
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* User's handle for a drm_syncobj to wait on or signal.
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*/
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__u32 handle;
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@ -842,10 +846,11 @@ struct drm_i915_gem_execbuffer2 {
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__u32 DR1;
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__u32 DR4;
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__u32 num_cliprects;
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/** This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
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* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
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* struct drm_i915_gem_exec_fence *fences.
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*/
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/**
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* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
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* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
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* struct drm_i915_gem_exec_fence *fences.
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*/
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__u64 cliprects_ptr;
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#define I915_EXEC_RING_MASK (7<<0)
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#define I915_EXEC_DEFAULT (0<<0)
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@ -1493,6 +1498,22 @@ enum drm_i915_perf_record_type {
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DRM_I915_PERF_RECORD_MAX /* non-ABI */
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};
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/**
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* Structure to upload perf dynamic configuration into the kernel.
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*/
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struct drm_i915_perf_oa_config {
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/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
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char uuid[36];
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__u32 n_mux_regs;
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__u32 n_boolean_regs;
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__u32 n_flex_regs;
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__u64 mux_regs_ptr;
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__u64 boolean_regs_ptr;
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__u64 flex_regs_ptr;
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};
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#if defined(__cplusplus)
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}
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#endif
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@ -40,6 +40,7 @@ extern "C" {
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#define DRM_VC4_GET_PARAM 0x07
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#define DRM_VC4_SET_TILING 0x08
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#define DRM_VC4_GET_TILING 0x09
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#define DRM_VC4_LABEL_BO 0x0a
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#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
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#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
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@ -51,6 +52,7 @@ extern "C" {
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#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
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#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
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#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
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#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
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struct drm_vc4_submit_rcl_surface {
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__u32 hindex; /* Handle index, or ~0 if not present. */
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@ -153,6 +155,16 @@ struct drm_vc4_submit_cl {
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__u32 pad:24;
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#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
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/* By default, the kernel gets to choose the order that the tiles are
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* rendered in. If this is set, then the tiles will be rendered in a
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* raster order, with the right-to-left vs left-to-right and
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* top-to-bottom vs bottom-to-top dictated by
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* VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
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* blits to be implemented using the 3D engine.
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*/
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#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
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#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
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#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
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__u32 flags;
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/* Returned value of the seqno of this render job (for the
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@ -292,6 +304,7 @@ struct drm_vc4_get_hang_state {
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#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
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#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
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#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
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#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
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struct drm_vc4_get_param {
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__u32 param;
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@ -311,6 +324,15 @@ struct drm_vc4_set_tiling {
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__u64 modifier;
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};
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/**
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* struct drm_vc4_label_bo - Attach a name to a BO for debug purposes.
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*/
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struct drm_vc4_label_bo {
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__u32 handle;
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__u32 len;
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__u64 name;
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};
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#if defined(__cplusplus)
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}
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#endif
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