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zink: make zink_gfx_pipeline_state::vertices_per_patch a bitfield
this is clamped to MAX_PATCH_VERTICES Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12586>
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7b3dfea6c1
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4a5dfabb12
@ -1122,7 +1122,7 @@ void main()
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struct zink_shader *
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zink_shader_tcs_create(struct zink_context *ctx, struct zink_shader *vs)
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{
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unsigned vertices_per_patch = ctx->gfx_pipeline_state.vertices_per_patch;
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unsigned vertices_per_patch = ctx->gfx_pipeline_state.vertices_per_patch + 1;
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struct zink_shader *ret = CALLOC_STRUCT(zink_shader);
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ret->programs = _mesa_pointer_set_create(NULL);
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simple_mtx_init(&ret->lock, mtx_plain);
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@ -438,7 +438,8 @@ zink_draw_vbo(struct pipe_context *pctx,
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ctx->buffer_rebind_counter = screen->buffer_rebind_counter;
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zink_rebind_all_buffers(ctx);
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}
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if (ctx->gfx_pipeline_state.vertices_per_patch != ctx->gfx_pipeline_state.patch_vertices)
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uint8_t vertices_per_patch = ctx->gfx_pipeline_state.patch_vertices ? ctx->gfx_pipeline_state.patch_vertices - 1 : 0;
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if (ctx->gfx_pipeline_state.vertices_per_patch != vertices_per_patch)
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ctx->gfx_pipeline_state.dirty = true;
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bool drawid_broken = ctx->drawid_broken;
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ctx->drawid_broken = false;
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@ -448,7 +449,7 @@ zink_draw_vbo(struct pipe_context *pctx,
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(HAS_MULTIDRAW && num_draws > 1 && !dinfo->increment_draw_id));
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if (drawid_broken != ctx->drawid_broken)
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ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_VERTEX);
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ctx->gfx_pipeline_state.vertices_per_patch = ctx->gfx_pipeline_state.patch_vertices;
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ctx->gfx_pipeline_state.vertices_per_patch = vertices_per_patch;
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if (ctx->rast_state->base.point_quad_rasterization && mode_changed) {
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if (ctx->gfx_prim_mode == PIPE_PRIM_POINTS || mode == PIPE_PRIM_POINTS)
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ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_FRAGMENT);
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@ -239,7 +239,7 @@ zink_create_gfx_pipeline(struct zink_screen *screen,
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VkPipelineTessellationDomainOriginStateCreateInfo tdci = {0};
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if (prog->shaders[PIPE_SHADER_TESS_CTRL] && prog->shaders[PIPE_SHADER_TESS_EVAL]) {
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tci.sType = VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO;
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tci.patchControlPoints = state->vertices_per_patch;
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tci.patchControlPoints = state->vertices_per_patch + 1;
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pci.pTessellationState = &tci;
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tci.pNext = &tdci;
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tdci.sType = VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO;
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@ -40,8 +40,8 @@ struct zink_vertex_elements_state;
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struct zink_gfx_pipeline_state {
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uint32_t rast_state : ZINK_RAST_HW_STATE_SIZE; //zink_rasterizer_hw_state
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uint32_t vertices_per_patch:5;
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uint32_t rast_samples:7;
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uint32_t vertices_per_patch;
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uint32_t void_alpha_attachments:PIPE_MAX_COLOR_BUFS;
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VkSampleMask sample_mask;
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@ -161,7 +161,7 @@ shader_key_tcs_gen(struct zink_context *ctx, struct zink_shader *zs,
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struct zink_tcs_key *tcs_key = &key->key.tcs;
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key->size = sizeof(struct zink_tcs_key);
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tcs_key->vertices_per_patch = ctx->gfx_pipeline_state.vertices_per_patch;
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tcs_key->vertices_per_patch = ctx->gfx_pipeline_state.vertices_per_patch + 1;
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tcs_key->vs_outputs_written = shaders[PIPE_SHADER_VERTEX]->nir->info.outputs_written;
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}
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