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intel/tools: Add unit tests for assembler
v1: Pass executable object from meson to test(Dylan Baker) v2: Ignore generated output files from git status(Matt Turner) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
This commit is contained in:
Sagar Ghuge
Matt Turner
parent
1fb5ce0a11
commit
4e828bb48a
1
.gitignore
vendored
1
.gitignore
vendored
@ -1,3 +1,4 @@
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*.pyc
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*.pyo
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*.out
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build
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@ -154,3 +154,21 @@ i965_asm = executable(
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c_args : [c_vis_args, no_override_init_args],
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install : true
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)
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asm_testcases = [
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['brw', 'tests/gen4'],
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['g4x', 'tests/gen4.5'],
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['ilk', 'tests/gen5'],
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['snb', 'tests/gen6'],
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['ivb', 'tests/gen7'],
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['hsw', 'tests/gen7.5'],
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['bdw', 'tests/gen8'],
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['skl', 'tests/gen9'],
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]
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test_runner = find_program('tests/run-test.sh')
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foreach testcase : asm_testcases
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test('i965_asm : ' + testcase[1], test_runner,
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args : [i965_asm, testcase[1], testcase[0]],
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env : ['srcdir=' + meson.current_source_dir()])
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endforeach
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49
src/intel/tools/tests/gen4.5/add.asm
Normal file
49
src/intel/tools/tests/gen4.5/add.asm
Normal file
@ -0,0 +1,49 @@
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add(16) g10<1>UW g1.4<2,4,0>UW 0x10101010V { align1 };
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add(8) g6<1>F g10<8,8,1>UW -g1<0,1,0>F { align1 };
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add(8) g8<1>F g10.8<8,8,1>UW -g1<0,1,0>F { align1 sechalf };
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add(16) g4<1>F g18<8,8,1>F g6<8,8,1>F { align1 compr };
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add(1) m14.4<1>D g8.4<0,1,0>D 16D { align1 nomask };
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add(8) g5<1>.xD g2<4>.xD 64D { align16 };
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add(8) g4<1>.xD g5<4>.xD g4<4>.xD { align16 };
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add(8) g3<1>F g3<4>F g5<4>F { align16 };
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add(16) g24<1>F g20<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
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add(16) g14<1>D g14<8,8,1>D 1D { align1 compr };
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add(8) m5<1>.xyzF g10<4>.xyzzF g8<4>.xyzzF { align16 NoDDClr };
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add.le.f0.0(16) g6<1>F g8<8,8,1>F g4<8,8,1>F { align1 compr };
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add(16) m3<1>F g4<8,8,1>F g12<8,8,1>F { align1 compr4 };
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add(8) a0<1>UW g4<16,8,2>UW 0x0040UW { align1 };
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add(8) a0<1>UW g5<16,8,2>UW 0x0040UW { align1 sechalf };
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add(8) g3<1>.xyF g2<4>.xyyyF 0x3f800000F /* 1F */ { align16 };
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add(16) m4<1>F -g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr4 };
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add(16) m2<1>D g6<8,8,1>D g8.3<0,1,0>D { align1 compr };
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add(16) m14<1>D g4<8,8,1>D 12D { align1 compr };
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add.sat(16) g6<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 compr };
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add(8) g37<1>UW g1.4<2,4,0>UW 0x10101010V { align1 };
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add(8) g38<1>D g2<0,1,0>D 1D { align1 };
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add(8) m5<1>.xF g3<4>.xF 0x3f000000F /* 0.5F */ { align16 };
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add(16) g4<1>D g2<0,1,0>D -g2.2<0,1,0>D { align1 compr };
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add.sat(8) m5<1>F g7<4>F g8<4>F { align16 };
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add(8) g31<1>.xyzF g28<4>.xyzzF 0x30300000VF /* [0F, 0F, 1F, 1F]VF */ { align16 };
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add.sat(8) m5<1>.xyzF g25<4>.xyzzF g26<4>.xyzzF { align16 NoDDClr };
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add.ge.f0.0(8) g8<1>.xF -g8<4>.xF 0x3f800000F /* 1F */ { align16 };
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add(16) g4.1<2>UW g4.1<16,8,2>UW g6<16,8,2>UW { align1 compr };
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add.ge.f0.0(16) g4<1>F -g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
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add(8) g4<1>.xyF g4<4>.xyyyF 0xbf800000F /* -1F */ { align16 NoDDClr };
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add(8) m5<1>.xyzF g4<4>.xyzzF g2<0>.xyzzF { align16 };
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add.sat(16) m6<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 compr4 };
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add(8) m5<1>.zwF g8<4>.xxxyF g9<4>.xxxyF { align16 NoDDChk };
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add(8) g4<1>.xUD g4<4>.xUD 0x00000040UD { align16 };
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add.sat(8) m5<1>.yF g1<0>.zF 0x3f000000F /* 0.5F */ { align16 };
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add(16) m14<1>UD g4<8,8,1>UD 0x00000110UD { align1 compr };
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add(8) g5<1>F -g9<4>.xyxyF g9<4>.zwzwF { align16 sechalf };
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add.sat(8) m5<1>.yF g6<4>.xF g7<4>.xF { align16 NoDDClr,NoDDChk };
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add.sat(8) m5<1>.wF g6<4>.xF g7<4>.xF { align16 NoDDChk };
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add.ge.f0.0(16) g16<1>F g18<8,8,1>F g10<8,8,1>F { align1 compr };
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add.sat(8) m5<1>.yF -g1<0>.xF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
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add.sat(8) m5<1>.zF g3<4>.yF 0x40000000F /* 2F */ { align16 NoDDClr,NoDDChk };
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add.sat(8) m5<1>.wF g3<4>.yF 0xc0000000F /* -2F */ { align16 NoDDChk };
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add(8) m5<1>F g3<4>F 0x2020a038VF /* [1.5F, -0.5F, 0.5F, 0.5F]VF */ { align16 };
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add(8) g5<1>.zF g4<4>.xF 0xbf800000F /* -1F */ { align16 NoDDClr,NoDDChk };
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add(8) m5<1>.xyF g12<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
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add(8) m5<1>.wF -g3<4>.xF 0x3f800000F /* 1F */ { align16 NoDDClr,NoDDChk };
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add(8) g5<1>.xyF g3<0>.xyyyF g4<4>.xyyyF { align16 NoDDClr };
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49
src/intel/tools/tests/gen4.5/add.expected
Normal file
49
src/intel/tools/tests/gen4.5/add.expected
Normal file
@ -0,0 +1,49 @@
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40 00 80 00 29 6d 40 21 28 00 48 00 10 10 10 10
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40 00 60 00 3d 75 c0 20 40 01 8d 00 20 40 00 00
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40 10 60 00 3d 75 00 21 50 01 8d 00 20 40 00 00
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40 20 80 00 bd 77 80 20 40 02 8d 00 c0 00 8d 00
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40 02 00 00 a6 1c d0 21 10 01 00 00 10 00 00 00
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40 01 60 00 a5 1c a1 20 40 00 60 00 40 00 00 00
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40 01 60 00 a5 14 81 20 a0 00 60 00 80 00 60 00
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40 01 60 00 bd 77 6f 20 64 00 6e 00 a4 00 6e 00
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40 20 80 00 bd 7f 00 23 80 02 8d 00 00 00 80 3f
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40 20 80 00 a5 1c c0 21 c0 01 8d 00 01 00 00 00
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40 05 60 00 be 77 a7 20 44 01 6a 00 04 01 6a 00
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40 20 80 06 bd 77 c0 20 00 01 8d 00 80 00 8d 00
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40 20 80 00 be 77 60 30 80 00 8d 00 80 01 8d 00
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40 00 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00
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40 10 60 00 28 2d 00 22 a0 00 ae 00 40 00 40 00
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40 01 60 00 bd 7f 63 20 44 00 65 00 00 00 80 3f
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40 20 80 00 be 7f 80 30 c0 40 8d 00 00 00 80 3f
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40 20 80 00 a6 14 40 20 c0 00 8d 00 0c 01 00 00
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40 20 80 00 a6 1c c0 21 80 00 8d 00 0c 00 00 00
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40 20 80 80 bd 77 c0 20 80 00 8d 00 44 00 00 00
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40 00 60 00 29 6d a0 24 28 00 48 00 10 10 10 10
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40 00 60 00 a5 1c c0 24 40 00 00 00 01 00 00 00
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40 01 60 00 be 7f a1 20 60 00 60 00 00 00 00 3f
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40 20 80 00 a5 14 80 20 40 00 00 00 48 40 00 00
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40 01 60 80 be 77 af 20 e4 00 6e 00 04 01 6e 00
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40 01 60 00 bd 5f e7 23 84 03 6a 00 00 00 30 30
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40 05 60 80 be 77 a7 20 24 03 6a 00 44 03 6a 00
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40 01 60 04 bd 7f 01 21 00 41 60 00 00 00 80 3f
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40 20 80 00 29 25 82 40 82 00 ae 00 c0 00 ae 00
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40 20 80 04 bd 7f 80 20 c0 40 8d 00 00 00 80 3f
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40 05 60 00 bd 7f 83 20 84 00 65 00 00 00 80 bf
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40 01 60 00 be 77 a7 20 84 00 6a 00 44 00 0a 00
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40 20 80 80 be 77 c0 30 40 00 00 00 50 00 00 00
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40 09 60 00 be 77 ac 20 00 01 64 00 20 01 64 00
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40 01 60 00 21 0c 81 20 80 00 60 00 40 00 00 00
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40 01 60 80 be 7f a2 20 2a 00 0a 00 00 00 00 3f
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40 20 80 00 22 0c c0 21 80 00 8d 00 10 01 00 00
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40 11 60 00 bd 77 af 20 24 41 64 00 2e 01 6e 00
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40 0d 60 80 be 77 a2 20 c0 00 60 00 e0 00 60 00
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40 09 60 80 be 77 a8 20 c0 00 60 00 e0 00 60 00
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40 20 80 04 bd 77 00 22 40 02 8d 00 40 01 8d 00
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40 05 60 80 be 7f a2 20 20 40 00 00 00 00 00 3f
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40 0d 60 80 be 7f a4 20 65 00 65 00 00 00 00 40
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40 09 60 80 be 7f a8 20 65 00 65 00 00 00 00 c0
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40 01 60 00 be 5f af 20 64 00 6e 00 38 a0 20 20
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40 0d 60 00 bd 7f a4 20 80 00 60 00 00 00 80 bf
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40 05 60 00 be 7f a3 20 84 01 65 00 00 00 00 3f
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40 0d 60 00 be 7f a8 20 60 40 60 00 00 00 80 3f
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40 05 60 00 bd 77 a3 20 64 00 05 00 84 00 65 00
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17
src/intel/tools/tests/gen4.5/and.asm
Normal file
17
src/intel/tools/tests/gen4.5/and.asm
Normal file
@ -0,0 +1,17 @@
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and(8) g9<1>.wUD g9<4>.wUD 524032D { align16 };
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and(16) g4<1>D g6<8,8,1>D 1D { align1 compr };
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and(8) g10<1>.xD g10<4>.xD 1D { align16 };
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and(16) g6<1>UD g10<8,8,1>UD g8<8,8,1>UD { align1 compr };
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and.nz.f0.0(16) null<1>D g6<8,8,1>UD 1D { align1 compr };
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and(16) g4<1>D g8<8,8,1>UD 1D { align1 compr };
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and(8) g2<1>D g2<8,8,1>UD 1D { align1 };
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and.nz.f0.0(8) null<1>.xD g9<4>.xUD 1D { align16 };
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and(16) g12<1>UD g2.4<0,1,0>UD 0x80000000UD { align1 compr };
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and.nz.f0.0(16) g110<1>D g6<8,8,1>D 1D { align1 compr };
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and(1) g10<1>UD f0<0,1,0>UW 0x0000000fUD { align1 nomask };
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and(8) g17<1>.xUD g1<0>.xUD 0x80000000UD { align16 };
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and.nz.f0.0(16) g6<1>D g4<8,8,1>UD 1D { align1 compr };
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and(8) g5<1>.xUD g1<0>.xUD g1<0>.yUD { align16 };
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and(8) g8<1>.xD g7<4>.xUD 1D { align16 };
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and.nz.f0.0(8) g6<1>.xD g6<4>.xD 1D { align16 };
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and.nz.f0.0(1) null<1>UD g1.6<0,1,0>UD 0x04000000UD { align1 };
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17
src/intel/tools/tests/gen4.5/and.expected
Normal file
17
src/intel/tools/tests/gen4.5/and.expected
Normal file
@ -0,0 +1,17 @@
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05 01 60 00 21 1c 28 21 2f 01 6f 00 00 ff 07 00
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05 20 80 00 a5 1c 80 20 c0 00 8d 00 01 00 00 00
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05 01 60 00 a5 1c 41 21 40 01 60 00 01 00 00 00
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05 20 80 00 21 04 c0 20 40 01 8d 00 00 01 8d 00
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05 20 80 02 24 1c 00 20 c0 00 8d 00 01 00 00 00
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05 20 80 00 25 1c 80 20 00 01 8d 00 01 00 00 00
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05 00 60 00 25 1c 40 20 40 00 8d 00 01 00 00 00
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05 01 60 02 24 1c 01 20 20 01 60 00 01 00 00 00
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05 20 80 00 21 0c 80 21 50 00 00 00 00 00 00 80
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05 20 80 02 a5 1c c0 2d c0 00 8d 00 01 00 00 00
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05 02 00 00 01 0d 40 21 00 06 00 00 0f 00 00 00
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05 01 60 00 21 0c 21 22 20 00 00 00 00 00 00 80
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05 20 80 02 25 1c c0 20 80 00 8d 00 01 00 00 00
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05 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00
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05 01 60 00 25 1c 01 21 e0 00 60 00 01 00 00 00
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05 01 60 02 a5 1c c1 20 c0 00 60 00 01 00 00 00
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05 00 00 02 20 0c 00 20 38 00 00 00 00 00 00 04
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5
src/intel/tools/tests/gen4.5/asr.asm
Normal file
5
src/intel/tools/tests/gen4.5/asr.asm
Normal file
@ -0,0 +1,5 @@
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asr(16) g4<1>D -g1.6<0,1,0>D 31D { align1 compr };
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asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr };
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asr(8) g4<1>D g5<4>D g4<4>UD { align16 };
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asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 };
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asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr };
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5
src/intel/tools/tests/gen4.5/asr.expected
Normal file
5
src/intel/tools/tests/gen4.5/asr.expected
Normal file
@ -0,0 +1,5 @@
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0c 20 80 00 a5 1c 80 20 38 40 00 00 1f 00 00 00
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0c 20 80 02 a4 1c 00 20 38 40 00 00 1f 00 00 00
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0c 01 60 00 a5 04 8f 20 a4 00 6e 00 84 00 6e 00
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0c 01 60 00 a5 0c 61 21 a0 00 60 00 02 00 00 00
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0c 20 80 00 a5 0c 40 21 c0 00 8d 00 02 00 00 00
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5
src/intel/tools/tests/gen4.5/break.asm
Normal file
5
src/intel/tools/tests/gen4.5/break.asm
Normal file
@ -0,0 +1,5 @@
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(-f0.0) break(16) Jump: 10 Pop: 0 { align1 };
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break(16) Jump: 5 Pop: 1 { align1 };
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(+f0.0) break(16) Jump: 141 Pop: 0 { align1 };
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(+f0.0.x) break(8) Jump: 16 Pop: 0 { align16 };
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break(8) Jump: 6 Pop: 2 { align16 };
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5
src/intel/tools/tests/gen4.5/break.expected
Normal file
5
src/intel/tools/tests/gen4.5/break.expected
Normal file
@ -0,0 +1,5 @@
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28 00 91 00 00 1c 00 34 00 14 60 00 0a 00 00 00
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28 00 80 00 00 1c 00 34 00 14 60 00 05 00 01 00
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28 00 81 00 00 1c 00 34 00 14 60 00 8d 00 00 00
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28 01 62 00 00 1c 0f 34 04 14 6e 00 10 00 00 00
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28 01 60 00 00 1c 0f 34 04 14 6e 00 06 00 02 00
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80
src/intel/tools/tests/gen4.5/cmp.asm
Normal file
80
src/intel/tools/tests/gen4.5/cmp.asm
Normal file
@ -0,0 +1,80 @@
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cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16 };
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cmp.nz.f0.0(8) null<1>D g7<4>.xyzzD 0D { align16 };
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cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
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cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
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cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
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cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
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cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
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cmp.l.f0.0(8) g7<1>.xF g7<4>.xF 0x3189705fF /* 4e-09F */ { align16 };
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cmp.ge.f0.0(8) g6<1>.xF g2<0>.xF g6<4>.xF { align16 };
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cmp.z.f0.0(8) null<1>F g3<0>.zwwwF g3<0>.xyyyF { align16 };
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cmp.ge.f0.0(16) null<1>D g14<8,8,1>D 16D { align1 compr };
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cmp.l.f0.0(16) null<1>D g2<0,1,0>D 1D { align1 compr };
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cmp.z.f0.0(16) g8<1>F g32<8,8,1>F g2.3<0,1,0>F { align1 compr };
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cmp.ge.f0.0(16) null<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
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cmp.nz.f0.0(8) null<1>F g12<4>.xyyyF g1<0>.xyyyF { align16 };
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cmp.z.f0.0(8) null<1>D g6<4>D g2.4<0>D { align16 };
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cmp.z.f0.0(16) g6<1>D g2.1<0,1,0>D 39D { align1 compr };
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cmp.z.f0.0(16) g4<1>F g2.1<0,1,0>F 0x41000000F /* 8F */ { align1 compr };
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cmp.z.f0.0(8) g5<1>.xD g5<4>.xD g1<0>.zD { align16 };
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cmp.l.f0.0(8) g3<1>.xyF g1<0>.xyyyF g1<0>.zwwwF { align16 };
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cmp.z.f0.0(16) null<1>D g2<0,1,0>D 1D { align1 compr };
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cmp.z.f0.0(16) null<1>F g14<8,8,1>F g2.1<0,1,0>F { align1 compr };
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cmp.z.f0.0(8) g6<1>.xF g6<4>.xF g3<0>.yF { align16 };
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cmp.nz.f0.0(16) g4<1>F g6<8,8,1>F g2.2<0,1,0>F { align1 compr };
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cmp.ge.f0.0(16) null<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
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cmp.nz.f0.0(16) null<1>D g2<0,1,0>D 0D { align1 compr };
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cmp.nz.f0.0(8) g5<1>F g5<8,8,1>F g38<8,8,1>F { align1 };
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cmp.ge.f0.0(8) null<1>.xD g5<4>.xD 4D { align16 };
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cmp.nz.f0.0(16) null<1>F g2.4<0,1,0>F 0x0F /* 0F */ { align1 compr };
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cmp.z.f0.0(16) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 compr };
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cmp.ge.f0.0(16) g4<1>D g2<0,1,0>D 1D { align1 compr };
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cmp.nz.f0.0(16) g4<1>D g2.1<0,1,0>D 0D { align1 compr };
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cmp.z.f0.0(16) g8<1>D g6<8,8,1>D g2.5<0,1,0>D { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>F g4<8,8,1>F g2.5<0,1,0>F { align1 compr };
|
||||
cmp.l.f0.0(16) g6<1>D g3<0,1,0>D 1D { align1 compr };
|
||||
cmp.ge.f0.0(8) null<1>F g32<4>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.l.f0.0(8) null<1>F g23<4>.xF 0x43000000F /* 128F */ { align16 };
|
||||
cmp.le.f0.0(8) g32<1>.xF g32<4>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.ge.f0.0(16) g4<1>D g2.3<0,1,0>D g2<0,1,0>D { align1 compr };
|
||||
cmp.nz.f0.0(8) g3<1>.xD g1<0>.xD g1<0>.yD { align16 };
|
||||
cmp.nz.f0.0(8) g3<1>.xyzF g1<0>.xyzzF g1.4<0>.xyzzF { align16 };
|
||||
cmp.nz.f0.0(8) null<1>F g1<0>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.le.f0.0(8) g5<1>.xD g1<0>.xD 0D { align16 };
|
||||
cmp.l.f0.0(16) g4<1>D g2.1<0,1,0>D g2<0,1,0>D { align1 compr };
|
||||
cmp.ge.f0.0(8) g3<1>D g1<0>D g1.4<0>D { align16 };
|
||||
cmp.le.f0.0(16) null<1>F g4<8,8,1>F 0x3f000000F /* 0.5F */ { align1 compr };
|
||||
cmp.le.f0.0(16) g20<1>F g4<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 compr };
|
||||
cmp.z.f0.0(8) null<1>F g3<0>.xyzzF 0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 };
|
||||
cmp.nz.f0.0(8) null<1>D g1<0>.xyzzD g1.4<0>.xyzzD { align16 };
|
||||
cmp.ge.f0.0(8) null<1>.xD g5<4>.xD g3<0>.xD { align16 };
|
||||
cmp.nz.f0.0(16) g8<1>F g2.2<0,1,0>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.l.f0.0(8) null<1>F g1<0>F g3<4>F { align16 };
|
||||
cmp.g.f0.0(8) g7<1>.xF g2<4>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.g.f0.0(8) null<1>.xF g2<4>.yF 0x0F /* 0F */ { align16 };
|
||||
cmp.nz.f0.0(16) null<1>D g16<8,8,1>D g12<8,8,1>D { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.z.f0.0(8) null<1>.xD g1<0>.xD 1D { align16 };
|
||||
cmp.nz.f0.0(16) g6<1>D g4<8,8,1>D g2.2<0,1,0>D { align1 compr };
|
||||
cmp.g.f0.0(16) g16<1>F (abs)g8<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
cmp.l.f0.0(8) g5<1>.xD g1<0>.yD g1<0>.xD { align16 };
|
||||
cmp.ge.f0.0(8) g6<1>.xF g3<4>.xF 0x41f00000F /* 30F */ { align16 };
|
||||
cmp.g.f0.0(16) null<1>D g2.1<0,1,0>D 0D { align1 compr };
|
||||
cmp.ge.f0.0(16) null<1>D g4<8,8,1>D g2.1<0,1,0>D { align1 compr };
|
||||
cmp.le.f0.0(8) null<1>.xF g8<4>.xF 0x3f000000F /* 0.5F */ { align16 };
|
||||
cmp.ge.f0.0(8) null<1>.xF g22<4>.xF g10<4>.xF { align16 };
|
||||
cmp.z.f0.0(8) g9<1>.xF g1<0>.xF 0x40b79581F /* 5.737F */ { align16 };
|
||||
cmp.z.f0.0(16) null<1>D g6<8,8,1>D g2<0,1,0>D { align1 compr };
|
||||
cmp.nz.f0.0(16) null<1>F g4<8,8,1>F g8<8,8,1>F { align1 compr };
|
||||
(+f0.1) cmp.z.f0.1(16) null<1>D g6<8,8,1>D 0D { align1 compr };
|
||||
cmp.nz.f0.0(8) g11<1>.xD g4<4>.xD 10D { align16 };
|
||||
cmp.nz.f0.0(8) g3<1>F g3<4>F 0x0F /* 0F */ { align16 };
|
||||
cmp.le.f0.0(16) g4<1>D g2<0,1,0>D 0D { align1 compr };
|
||||
cmp.l.f0.0(8) null<1>.xD g6<4>.xD g5<4>.xD { align16 };
|
||||
cmp.ge.f0.0(8) g10<1>.xD g5<4>.xD 2D { align16 };
|
||||
cmp.g.f0.0(8) null<1>.xD g3<0>.zD 4D { align16 };
|
||||
cmp.g.f0.0(16) null<1>F g20<8,8,1>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>D g2<0,1,0>D g6<8,8,1>D { align1 compr };
|
||||
(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 };
|
||||
cmp.le.f0.0(8) g3<1>.xUD g1<0>.xUD 0x00000001UD { align16 };
|
||||
cmp.g.f0.0(8) g8<1>.xD g1<0>.xD 2D { align16 };
|
||||
80
src/intel/tools/tests/gen4.5/cmp.expected
Normal file
80
src/intel/tools/tests/gen4.5/cmp.expected
Normal file
@ -0,0 +1,80 @@
|
||||
10 01 60 02 bc 5f 0f 20 64 00 0a 00 64 6e 74 74
|
||||
10 01 60 02 a4 1c 0f 20 e4 00 6a 00 00 00 00 00
|
||||
10 20 80 04 bd 7f c0 20 80 00 8d 00 5f 70 89 31
|
||||
10 20 80 05 bd 7f 00 21 80 00 8d 00 5f 70 89 31
|
||||
10 20 80 05 bd 77 00 21 80 00 8d 00 c0 00 8d 00
|
||||
10 20 80 04 bd 77 40 21 80 00 8d 00 c0 00 8d 00
|
||||
10 01 60 01 a5 1c 41 21 80 00 00 00 00 00 00 00
|
||||
10 01 60 05 bd 7f e1 20 e0 00 60 00 5f 70 89 31
|
||||
10 01 60 04 bd 77 c1 20 40 00 00 00 c0 00 60 00
|
||||
10 01 60 01 bc 77 0f 20 6e 00 0f 00 64 00 05 00
|
||||
10 20 80 04 a4 1c 00 20 c0 01 8d 00 10 00 00 00
|
||||
10 20 80 05 a4 1c 00 20 40 00 00 00 01 00 00 00
|
||||
10 20 80 01 bd 77 00 21 00 04 8d 00 4c 00 00 00
|
||||
10 20 80 04 bc 7f 00 20 c0 00 8d 00 00 00 00 00
|
||||
10 01 60 02 bc 77 0f 20 84 01 65 00 24 00 05 00
|
||||
10 01 60 01 a4 14 0f 20 c4 00 6e 00 54 00 0e 00
|
||||
10 20 80 01 a5 1c c0 20 44 00 00 00 27 00 00 00
|
||||
10 20 80 01 bd 7f 80 20 44 00 00 00 00 00 00 41
|
||||
10 01 60 01 a5 14 a1 20 a0 00 60 00 2a 00 0a 00
|
||||
10 01 60 05 bd 77 63 20 24 00 05 00 2e 00 0f 00
|
||||
10 20 80 01 a4 1c 00 20 40 00 00 00 01 00 00 00
|
||||
10 20 80 01 bc 77 00 20 c0 01 8d 00 44 00 00 00
|
||||
10 01 60 01 bd 77 c1 20 c0 00 60 00 65 00 05 00
|
||||
10 20 80 02 bd 77 80 20 c0 00 8d 00 48 00 00 00
|
||||
10 20 80 04 bc 77 00 20 00 22 8d 00 00 21 8d 00
|
||||
10 20 80 02 a4 1c 00 20 40 00 00 00 00 00 00 00
|
||||
10 00 60 02 bd 77 a0 20 a0 00 8d 00 c0 04 8d 00
|
||||
10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00
|
||||
10 20 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00
|
||||
10 20 80 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
|
||||
10 20 80 04 a5 1c 80 20 40 00 00 00 01 00 00 00
|
||||
10 20 80 02 a5 1c 80 20 44 00 00 00 00 00 00 00
|
||||
10 20 80 01 a5 14 00 21 c0 00 8d 00 54 00 00 00
|
||||
10 20 80 05 bc 77 00 20 80 00 8d 00 54 00 00 00
|
||||
10 20 80 05 a5 1c c0 20 60 00 00 00 01 00 00 00
|
||||
10 01 60 04 bc 7f 0f 20 00 04 60 00 00 00 00 00
|
||||
10 01 60 05 bc 7f 0f 20 e0 02 60 00 00 00 00 43
|
||||
10 01 60 06 bd 7f 01 24 00 04 60 00 00 00 00 00
|
||||
10 20 80 04 a5 14 80 20 4c 00 00 00 40 00 00 00
|
||||
10 01 60 02 a5 14 61 20 20 00 00 00 25 00 05 00
|
||||
10 01 60 02 bd 77 67 20 24 00 0a 00 34 00 0a 00
|
||||
10 01 60 02 bc 7f 0f 20 20 00 00 00 00 00 00 00
|
||||
10 01 60 06 a5 1c a1 20 20 00 00 00 00 00 00 00
|
||||
10 20 80 05 a5 14 80 20 44 00 00 00 40 00 00 00
|
||||
10 01 60 04 a5 14 6f 20 24 00 0e 00 34 00 0e 00
|
||||
10 20 80 06 bc 7f 00 20 80 00 8d 00 00 00 00 3f
|
||||
10 20 80 06 bd 7f 80 22 80 00 8d 00 9a 3f 1c 46
|
||||
10 01 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e
|
||||
10 01 60 02 a4 14 0f 20 24 00 0a 00 34 00 0a 00
|
||||
10 01 60 04 a4 14 01 20 a0 00 60 00 60 00 00 00
|
||||
10 20 80 02 bd 7f 00 21 48 00 00 00 00 00 00 00
|
||||
10 01 60 05 bc 77 0f 20 24 00 0e 00 64 00 6e 00
|
||||
10 01 60 03 bd 7f e1 20 40 00 60 00 00 00 00 00
|
||||
10 01 60 03 bc 7f 01 20 45 00 65 00 00 00 00 00
|
||||
10 20 80 02 a4 14 00 20 00 02 8d 00 80 01 8d 00
|
||||
10 20 80 05 bc 7f 00 20 40 00 00 00 00 00 00 00
|
||||
10 01 60 01 a4 1c 01 20 20 00 00 00 01 00 00 00
|
||||
10 20 80 02 a5 14 c0 20 80 00 8d 00 48 00 00 00
|
||||
10 20 80 03 bd 7f 00 22 00 21 8d 00 00 00 80 3f
|
||||
10 01 60 05 a5 14 a1 20 25 00 05 00 20 00 00 00
|
||||
10 01 60 04 bd 7f c1 20 60 00 60 00 00 00 f0 41
|
||||
10 20 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00
|
||||
10 20 80 04 a4 14 00 20 80 00 8d 00 44 00 00 00
|
||||
10 01 60 06 bc 7f 01 20 00 01 60 00 00 00 00 3f
|
||||
10 01 60 04 bc 77 01 20 c0 02 60 00 40 01 60 00
|
||||
10 01 60 01 bd 7f 21 21 20 00 00 00 81 95 b7 40
|
||||
10 20 80 01 a4 14 00 20 c0 00 8d 00 40 00 00 00
|
||||
10 20 80 02 bc 77 00 20 80 00 8d 00 00 01 8d 00
|
||||
10 20 81 01 a4 1c 00 20 c0 00 8d 02 00 00 00 00
|
||||
10 01 60 02 a5 1c 61 21 80 00 60 00 0a 00 00 00
|
||||
10 01 60 02 bd 7f 6f 20 64 00 6e 00 00 00 00 00
|
||||
10 20 80 06 a5 1c 80 20 40 00 00 00 00 00 00 00
|
||||
10 01 60 05 a4 14 01 20 c0 00 60 00 a0 00 60 00
|
||||
10 01 60 04 a5 1c 41 21 a0 00 60 00 02 00 00 00
|
||||
10 01 60 03 a4 1c 01 20 6a 00 0a 00 04 00 00 00
|
||||
10 20 80 03 bc 7f 00 20 80 02 8d 00 00 00 00 00
|
||||
10 20 80 05 a4 14 00 20 40 00 00 00 c0 00 8d 00
|
||||
10 00 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00
|
||||
10 01 60 06 21 0c 61 20 20 00 00 00 01 00 00 00
|
||||
10 01 60 03 a5 1c 01 21 20 00 00 00 02 00 00 00
|
||||
2
src/intel/tools/tests/gen4.5/cont.asm
Normal file
2
src/intel/tools/tests/gen4.5/cont.asm
Normal file
@ -0,0 +1,2 @@
|
||||
cont(16) Jump: 4 Pop: 1 { align1 };
|
||||
cont(8) Jump: 4 Pop: 1 { align16 };
|
||||
2
src/intel/tools/tests/gen4.5/cont.expected
Normal file
2
src/intel/tools/tests/gen4.5/cont.expected
Normal file
@ -0,0 +1,2 @@
|
||||
29 00 80 00 00 1c 00 34 00 14 60 00 04 00 01 00
|
||||
29 01 60 00 00 1c 0f 34 04 14 6e 00 04 00 01 00
|
||||
2
src/intel/tools/tests/gen4.5/do.asm
Normal file
2
src/intel/tools/tests/gen4.5/do.asm
Normal file
@ -0,0 +1,2 @@
|
||||
do(16) { align1 };
|
||||
do(8) { align16 };
|
||||
2
src/intel/tools/tests/gen4.5/do.expected
Normal file
2
src/intel/tools/tests/gen4.5/do.expected
Normal file
@ -0,0 +1,2 @@
|
||||
26 00 80 00 9c 73 00 20 00 00 8d 00 00 00 8d 00
|
||||
26 01 60 00 9c 73 0f 20 04 00 6e 00 04 00 6e 00
|
||||
7
src/intel/tools/tests/gen4.5/dp2.asm
Normal file
7
src/intel/tools/tests/gen4.5/dp2.asm
Normal file
@ -0,0 +1,7 @@
|
||||
dp2(8) g7<1>.xF g7<4>.xyyyF g7<4>.xyyyF { align16 };
|
||||
dp2(8) m5<1>.xF g1<0>.yF g1<0>.yF { align16 };
|
||||
dp2(8) m5<1>.yzF g1<0>.xF g1<0>.zwwwF { align16 NoDDClr };
|
||||
dp2(8) m5<1>.wF g1<0>.ywwwF g1<0>.wyyyF { align16 NoDDChk };
|
||||
dp2(8) g4<1>.yF g1<0>.xyyyF g1.4<0>.xyyyF { align16 NoDDClr };
|
||||
dp2(8) g4<1>.zF g1<0>.xyyyF g1.4<0>.zwwwF { align16 NoDDClr,NoDDChk };
|
||||
dp2(8) g4<1>.wF g1<0>.xyyyF g2<0>.xyyyF { align16 NoDDChk };
|
||||
7
src/intel/tools/tests/gen4.5/dp2.expected
Normal file
7
src/intel/tools/tests/gen4.5/dp2.expected
Normal file
@ -0,0 +1,7 @@
|
||||
57 01 60 00 bd 77 e1 20 e4 00 65 00 e4 00 65 00
|
||||
57 01 60 00 be 77 a1 20 25 00 05 00 25 00 05 00
|
||||
57 05 60 00 be 77 a6 20 20 00 00 00 2e 00 0f 00
|
||||
57 09 60 00 be 77 a8 20 2d 00 0f 00 27 00 05 00
|
||||
57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00
|
||||
57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00
|
||||
57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00
|
||||
9
src/intel/tools/tests/gen4.5/dp3.asm
Normal file
9
src/intel/tools/tests/gen4.5/dp3.asm
Normal file
@ -0,0 +1,9 @@
|
||||
dp3(8) g5<1>.xF g5<4>.xyzzF g5<4>.xyzzF { align16 };
|
||||
dp3(8) m5<1>.xF g3<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr };
|
||||
dp3(8) m5<1>.yF g3.4<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr,NoDDChk };
|
||||
dp3(8) g19<1>.xF g3<0>.xyzzF g3.4<0>.xyzzF { align16 NoDDClr };
|
||||
dp3(8) g19<1>.yF g3<0>.xyzzF g4<0>.xyzzF { align16 NoDDClr,NoDDChk };
|
||||
dp3(8) g19<1>.zF g3<0>.xyzzF g4.4<0>.xyzzF { align16 NoDDChk };
|
||||
dp3(8) m5<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
|
||||
dp3.le.f0.0(8) g18<1>.xF g17<4>.xyzzF g3.4<0>.xyzzF { align16 };
|
||||
dp3.sat(8) g4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
|
||||
9
src/intel/tools/tests/gen4.5/dp3.expected
Normal file
9
src/intel/tools/tests/gen4.5/dp3.expected
Normal file
@ -0,0 +1,9 @@
|
||||
56 01 60 00 bd 77 a1 20 a4 00 6a 00 a4 00 6a 00
|
||||
56 05 60 00 be 77 a1 20 64 00 0a 00 c4 00 6a 00
|
||||
56 0d 60 00 be 77 a2 20 74 00 0a 00 c4 00 6a 00
|
||||
56 05 60 00 bd 77 61 22 64 00 0a 00 74 00 0a 00
|
||||
56 0d 60 00 bd 77 62 22 64 00 0a 00 84 00 0a 00
|
||||
56 09 60 00 bd 77 64 22 64 00 0a 00 94 00 0a 00
|
||||
56 01 60 00 be 77 a1 20 84 00 6a 00 a4 00 6a 00
|
||||
56 01 60 06 bd 77 41 22 24 02 6a 00 74 00 0a 00
|
||||
56 01 60 80 bd 77 81 20 84 00 6a 00 a4 00 6a 00
|
||||
5
src/intel/tools/tests/gen4.5/dp4.asm
Normal file
5
src/intel/tools/tests/gen4.5/dp4.asm
Normal file
@ -0,0 +1,5 @@
|
||||
dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 };
|
||||
dp4(8) g4<1>.xF g5<4>F g1<0>F { align16 NoDDClr };
|
||||
dp4(8) g4<1>.yF g5<4>F g1.4<0>F { align16 NoDDClr,NoDDChk };
|
||||
dp4(8) g4<1>.wF g5<4>F g2.4<0>F { align16 NoDDChk };
|
||||
dp4(8) m5<1>.xF g4<4>F g5<4>F { align16 };
|
||||
5
src/intel/tools/tests/gen4.5/dp4.expected
Normal file
5
src/intel/tools/tests/gen4.5/dp4.expected
Normal file
@ -0,0 +1,5 @@
|
||||
54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00
|
||||
54 05 60 00 bd 77 81 20 a4 00 6e 00 24 00 0e 00
|
||||
54 0d 60 00 bd 77 82 20 a4 00 6e 00 34 00 0e 00
|
||||
54 09 60 00 bd 77 88 20 a4 00 6e 00 54 00 0e 00
|
||||
54 01 60 00 be 77 a1 20 84 00 6e 00 a4 00 6e 00
|
||||
5
src/intel/tools/tests/gen4.5/dph.asm
Normal file
5
src/intel/tools/tests/gen4.5/dph.asm
Normal file
@ -0,0 +1,5 @@
|
||||
dph(8) m5<1>.xF g4<4>.xyzxF g5<4>F { align16 };
|
||||
dph.sat(8) m5<1>F g1<0>.xyzxF g3<4>F { align16 };
|
||||
dph(8) g5<1>.xF g4<4>.xyzxF g1<0>F { align16 NoDDClr };
|
||||
dph(8) g5<1>.yF g4<4>.xyzxF g1.4<0>F { align16 NoDDClr,NoDDChk };
|
||||
dph(8) g6<1>.wF g5<4>.xyzxF g2.4<0>F { align16 NoDDChk };
|
||||
5
src/intel/tools/tests/gen4.5/dph.expected
Normal file
5
src/intel/tools/tests/gen4.5/dph.expected
Normal file
@ -0,0 +1,5 @@
|
||||
55 01 60 00 be 77 a1 20 84 00 62 00 a4 00 6e 00
|
||||
55 01 60 80 be 77 af 20 24 00 02 00 64 00 6e 00
|
||||
55 05 60 00 bd 77 a1 20 84 00 62 00 24 00 0e 00
|
||||
55 0d 60 00 bd 77 a2 20 84 00 62 00 34 00 0e 00
|
||||
55 09 60 00 bd 77 c8 20 a4 00 62 00 54 00 0e 00
|
||||
2
src/intel/tools/tests/gen4.5/else.asm
Normal file
2
src/intel/tools/tests/gen4.5/else.asm
Normal file
@ -0,0 +1,2 @@
|
||||
else(16) Jump: 7 Pop: 1 { align1 switch };
|
||||
else(8) Jump: 3 Pop: 1 { align16 switch };
|
||||
2
src/intel/tools/tests/gen4.5/else.expected
Normal file
2
src/intel/tools/tests/gen4.5/else.expected
Normal file
@ -0,0 +1,2 @@
|
||||
24 80 80 00 00 1c 00 34 00 14 60 00 07 00 01 00
|
||||
24 81 60 00 00 1c 0f 34 04 14 6e 00 03 00 01 00
|
||||
2
src/intel/tools/tests/gen4.5/endif.asm
Normal file
2
src/intel/tools/tests/gen4.5/endif.asm
Normal file
@ -0,0 +1,2 @@
|
||||
endif(16) Pop: 1 { align1 switch };
|
||||
endif(8) Pop: 1 { align16 switch };
|
||||
2
src/intel/tools/tests/gen4.5/endif.expected
Normal file
2
src/intel/tools/tests/gen4.5/endif.expected
Normal file
@ -0,0 +1,2 @@
|
||||
25 80 80 00 84 1c 00 20 00 00 8d 00 00 00 01 00
|
||||
25 81 60 00 84 1c 0f 20 04 00 6e 00 00 00 01 00
|
||||
4
src/intel/tools/tests/gen4.5/frc.asm
Normal file
4
src/intel/tools/tests/gen4.5/frc.asm
Normal file
@ -0,0 +1,4 @@
|
||||
frc.sat(8) m5<1>F g3<4>F { align16 };
|
||||
frc(8) g7<1>.xF (abs)g1<0>.xF { align16 };
|
||||
frc(16) g4<1>F g2<0,1,0>F { align1 compr };
|
||||
frc(16) m3<1>F g10<8,8,1>F { align1 compr4 };
|
||||
4
src/intel/tools/tests/gen4.5/frc.expected
Normal file
4
src/intel/tools/tests/gen4.5/frc.expected
Normal file
@ -0,0 +1,4 @@
|
||||
43 01 60 80 be 03 af 20 64 00 6e 00 00 00 00 00
|
||||
43 01 60 00 bd 03 e1 20 20 20 00 00 00 00 00 00
|
||||
43 20 80 00 bd 03 80 20 40 00 00 00 00 00 00 00
|
||||
43 20 80 00 be 03 60 30 40 01 8d 00 00 00 00 00
|
||||
2
src/intel/tools/tests/gen4.5/if.asm
Normal file
2
src/intel/tools/tests/gen4.5/if.asm
Normal file
@ -0,0 +1,2 @@
|
||||
(+f0.0) if(16) Jump: 15 { align1 switch };
|
||||
(+f0.0.x) if(8) Jump: 7 { align16 switch };
|
||||
2
src/intel/tools/tests/gen4.5/if.expected
Normal file
2
src/intel/tools/tests/gen4.5/if.expected
Normal file
@ -0,0 +1,2 @@
|
||||
22 80 81 00 00 1c 00 34 00 14 60 00 0f 00 00 00
|
||||
22 81 62 00 00 1c 0f 34 04 14 6e 00 07 00 00 00
|
||||
3
src/intel/tools/tests/gen4.5/iff.asm
Normal file
3
src/intel/tools/tests/gen4.5/iff.asm
Normal file
@ -0,0 +1,3 @@
|
||||
(-f0.0) iff(16) Jump: 5 { align1 switch };
|
||||
(+f0.0.x) iff(8) Jump: 11 { align16 switch };
|
||||
(+f0.0) iff(16) Jump: 7 { align1 switch };
|
||||
3
src/intel/tools/tests/gen4.5/iff.expected
Normal file
3
src/intel/tools/tests/gen4.5/iff.expected
Normal file
@ -0,0 +1,3 @@
|
||||
23 80 91 00 00 1c 00 34 00 14 60 00 05 00 00 00
|
||||
23 81 62 00 00 1c 0f 34 04 14 6e 00 0b 00 00 00
|
||||
23 80 81 00 00 1c 00 34 00 14 60 00 07 00 00 00
|
||||
1
src/intel/tools/tests/gen4.5/jmpi.asm
Normal file
1
src/intel/tools/tests/gen4.5/jmpi.asm
Normal file
@ -0,0 +1 @@
|
||||
(+f0.0) jmpi(1) 0x00000002UD { align1 nomask };
|
||||
1
src/intel/tools/tests/gen4.5/jmpi.expected
Normal file
1
src/intel/tools/tests/gen4.5/jmpi.expected
Normal file
@ -0,0 +1 @@
|
||||
20 02 01 00 00 0c 00 34 00 14 00 00 02 00 00 00
|
||||
1
src/intel/tools/tests/gen4.5/mach.asm
Normal file
1
src/intel/tools/tests/gen4.5/mach.asm
Normal file
@ -0,0 +1 @@
|
||||
mach(8) null<1>D g1<0>.xD g1<0>.yD { align16 };
|
||||
1
src/intel/tools/tests/gen4.5/mach.expected
Normal file
1
src/intel/tools/tests/gen4.5/mach.expected
Normal file
@ -0,0 +1 @@
|
||||
49 01 60 00 a4 14 0f 20 20 00 00 00 25 00 05 00
|
||||
102
src/intel/tools/tests/gen4.5/mov.asm
Normal file
102
src/intel/tools/tests/gen4.5/mov.asm
Normal file
@ -0,0 +1,102 @@
|
||||
mov(8) m2<1>UD g1<8,8,1>UD { align1 nomask };
|
||||
mov(8) g9<1>.xyzUD 0x00000000UD { align16 };
|
||||
mov.sat(8) m5<1>F g4<4>F { align16 };
|
||||
mov(8) m4<1>F g6<4>F { align16 };
|
||||
mov(8) m2<1>UD g9<4>UD { align16 };
|
||||
mov(16) g6<1>D 1065353216D { align1 compr };
|
||||
mov.nz.f0.0(16) null<1>D g2<0,1,0>D { align1 compr };
|
||||
mov(16) m3<1>F 0x0F /* 0F */ { align1 compr4 };
|
||||
mov(16) m4<1>F g4<8,8,1>F { align1 compr4 };
|
||||
mov(8) m2<1>UD 0x00000000UD { align16 };
|
||||
mov(8) g8<1>F 0x30003000VF /* [0F, 1F, 0F, 1F]VF */ { align16 };
|
||||
mov(8) g7<1>.xD 0D { align16 };
|
||||
(+f0.0.any4h) mov(8) g7<1>.xD -1D { align16 };
|
||||
mov(16) m3<1>F g4<8,8,1>D { align1 compr4 };
|
||||
mov(1) m14<1>D 0D { align1 nomask };
|
||||
mov(8) m15<1>D g3<0>D { align16 };
|
||||
mov(1) m14<1>D g8<0,1,0>D { align1 nomask };
|
||||
mov(16) g12<1>F g4<8,8,1>UW { align1 compr };
|
||||
mov(16) g4<1>D g12<8,8,1>F { align1 compr };
|
||||
mov(16) g12<1>F g4<8,8,1>D { align1 compr };
|
||||
mov(8) m15<1>D g2<4>.xUD { align16 };
|
||||
mov(8) g7<1>.xD g4<0>.yD { align16 };
|
||||
mov(8) g7<1>.xD g10<4>.xD { align16 NoDDClr };
|
||||
mov(8) g7<1>.yD g4<0>.yD { align16 NoDDChk };
|
||||
mov(16) m2<1>UD 0x00000000UD { align1 compr };
|
||||
mov(16) m6<1>D g9.3<0,1,0>D { align1 compr };
|
||||
mov(16) m8<1>UD 0D { align1 compr };
|
||||
mov(16) m2<1>D g4<8,8,1>F { align1 compr };
|
||||
mov(8) m5<1>.xF g3<4>.xD { align16 NoDDClr };
|
||||
mov(8) m5<1>.yzwD 0D { align16 NoDDChk };
|
||||
mov.sat(16) m3<1>F g2<0,1,0>F { align1 compr4 };
|
||||
mov(8) m6<1>F 0x50484030VF /* [1F, 2F, 3F, 4F]VF */ { align16 };
|
||||
mov(8) m3<1>F 0x42fc6666F /* 126.2F */ { align1 };
|
||||
mov(8) m3<1>F 0x42fc6666F /* 126.2F */ { align1 sechalf };
|
||||
mov(8) m5<1>.wD g8<4>.wD { align16 NoDDChk };
|
||||
mov(8) g6<1>.xD g6<4>.xF { align16 };
|
||||
mov(8) m3<1>F g[a0]<VxH,1,0>F { align1 };
|
||||
mov(8) m7<1>F g[a0]<VxH,1,0>F { align1 sechalf };
|
||||
mov(8) g20<1>.yD -1070881309D { align16 NoDDClr };
|
||||
mov(8) g20<1>.zD 1091044167D { align16 NoDDChk };
|
||||
mov(8) g28<1>.zD -1102236248D { align16 NoDDClr,NoDDChk };
|
||||
mov(8) g5<1>.xD acc0<4>D { align16 };
|
||||
mov(8) m13<1>.wD 1107296256D { align16 NoDDClr };
|
||||
mov(8) g11<1>.yzwD 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 };
|
||||
mov(8) m13<1>.xyzF 0x7f7e7dVF /* [29F, 30F, 31F, 0F]VF */ { align16 NoDDChk };
|
||||
mov(16) m3<1>UD g4<8,8,1>UD { align1 compr4 };
|
||||
mov(8) m6<1>.xF 0x0F /* 0F */ { align16 };
|
||||
(+f0.0.all4h) mov(8) g3<1>.xD -1D { align16 };
|
||||
mov(8) g3<1>F g2<0,1,0>D { align1 };
|
||||
mov(8) m3<1>F g2<8,8,1>D { align1 };
|
||||
mov(8) m5<1>.yF g3<4>.xD { align16 NoDDClr,NoDDChk };
|
||||
mov(8) m5<1>.wF g3<4>.xD { align16 NoDDChk };
|
||||
mov(8) g3<1>.xF g3<4>.xD { align16 NoDDClr };
|
||||
mov(8) g3<1>.yF g4<4>.xD { align16 NoDDClr,NoDDChk };
|
||||
mov(8) g3<1>.wF g4<4>.xD { align16 NoDDChk };
|
||||
mov(8) g8<1>UD g2<4>UD { align16 };
|
||||
mov(8) g7<1>.xF g3<0>.xD { align16 };
|
||||
mov(8) g6<1>.xF -g5<4>.yF { align16 NoDDClr };
|
||||
mov.nz.f0.0(16) g4<1>F -(abs)g2<0,1,0>F { align1 compr };
|
||||
(+f0.0) mov(16) g4<1>F 0xbf800000F /* -1F */ { align1 compr };
|
||||
mov(16) g24<1>D g42<8,8,1>D { align1 compr };
|
||||
mov(8) g8<1>F g[a0]<VxH,1,0>F { align1 };
|
||||
mov(8) g9<1>F g[a0]<VxH,1,0>F { align1 sechalf };
|
||||
mov(8) g3<1>.xyzF 0x0F /* 0F */ { align16 };
|
||||
mov(16) m2<1>UD g28<8,8,1>UW { align1 compr };
|
||||
mov(8) m3<1>D g2<0,1,0>D { align1 };
|
||||
mov(8) m3<1>D g2<0,1,0>D { align1 sechalf };
|
||||
mov(1) m14.2<1>UD 0x00000000UD { align1 nomask };
|
||||
mov(8) g5<1>.zD g1.4<0>.xD { align16 NoDDClr,NoDDChk };
|
||||
mov.sat(8) m5<1>.wF g20<4>.wF { align16 NoDDChk };
|
||||
mov(8) g26<1>.xyzUD 0x00000000UD { align16 NoDDClr };
|
||||
mov(8) m9<1>.xyD g4<0>.yzzzD { align16 NoDDClr };
|
||||
mov(8) m5<1>F g3<4>D { align16 };
|
||||
mov(8) m3<1>F g4<8,8,1>F { align1 nomask };
|
||||
mov.sat(8) m5<1>.zF 0x3eaaaaabF /* 0.333333F */ { align16 };
|
||||
mov.sat(8) m5<1>.wF 0x3dcccccdF /* 0.1F */ { align16 NoDDClr };
|
||||
mov(8) m5<1>.zD g3<4>.zD { align16 NoDDClr,NoDDChk };
|
||||
mov(8) m13<1>.yD 1107820544D { align16 NoDDClr,NoDDChk };
|
||||
mov.sat(8) m5<1>.wF 0x3f800000F /* 1F */ { align16 NoDDChk };
|
||||
mov.sat(8) m5<1>F g3<4>D { align16 };
|
||||
mov.sat(8) m5<1>.zF 0x3f666660F /* 0.9F */ { align16 NoDDClr,NoDDChk };
|
||||
mov(16) g10<1>F g2<0,1,0>F { align1 compr };
|
||||
mov(16) g10<1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
mov(8) m15<1>D 0D { align16 };
|
||||
mov.sat(16) g4<1>F g2<0,1,0>F { align1 compr };
|
||||
mov(8) g2<1>.xyzF g2<4>.wF { align16 };
|
||||
mov(8) g5<1>.xyzF 0x7f7e7dVF /* [29F, 30F, 31F, 0F]VF */ { align16 NoDDChk };
|
||||
mov.sat(8) m5<1>.xF g4<4>.xF { align16 NoDDClr };
|
||||
mov.sat(8) m5<1>.yzF g5<4>.xxyyF { align16 NoDDClr,NoDDChk };
|
||||
mov(1) f0.1<1>UW g0<0,1,0>UW { align1 nomask };
|
||||
mov(1) g0<1>UW f0.1<0,1,0>UW { align1 nomask };
|
||||
mov(8) m5<1>.zwF 0x30000000VF /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr };
|
||||
mov.sat(8) m5<1>.xF g5<4>.xD { align16 NoDDClr };
|
||||
mov.sat(8) m5<1>.yF g5<4>.xD { align16 NoDDClr,NoDDChk };
|
||||
mov.sat(8) m5<1>.wF g5<4>.xD { align16 NoDDChk };
|
||||
mov(8) g6<1>.yzD 0xf7c000VF /* [0F, -2F, -23F, 0F]VF */ { align16 NoDDChk };
|
||||
mov(8) m2<1>.xyzUD 0x00000000UD { align16 NoDDClr };
|
||||
mov(8) m2<1>.wUD g8<4>.xUD { align16 NoDDChk };
|
||||
mov(8) g5<1>F g3<4>UD { align16 };
|
||||
mov.nz.f0.0(8) null<1>.xD g8<4>.xD { align16 };
|
||||
mov.nz.f0.0(8) g8<1>F -(abs)g1<0>F { align16 };
|
||||
(+f0.0) mov(8) g8<1>F 0xbf800000F /* -1F */ { align16 };
|
||||
102
src/intel/tools/tests/gen4.5/mov.expected
Normal file
102
src/intel/tools/tests/gen4.5/mov.expected
Normal file
@ -0,0 +1,102 @@
|
||||
01 02 60 00 22 00 40 20 20 00 8d 00 00 00 00 00
|
||||
01 01 60 00 61 00 27 21 00 00 00 00 00 00 00 00
|
||||
01 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00
|
||||
01 01 60 00 be 03 8f 20 c4 00 6e 00 00 00 00 00
|
||||
01 01 60 00 22 00 4f 20 24 01 6e 00 00 00 00 00
|
||||
01 20 80 00 e5 10 c0 20 00 00 00 00 00 00 80 3f
|
||||
01 20 80 02 a4 00 00 20 40 00 00 00 00 00 00 00
|
||||
01 20 80 00 fe 73 60 30 00 00 00 00 00 00 00 00
|
||||
01 20 80 00 be 03 80 30 80 00 8d 00 00 00 00 00
|
||||
01 01 60 00 62 00 4f 20 00 00 00 00 00 00 00 00
|
||||
01 01 60 00 fd 52 0f 21 00 00 00 00 00 30 00 30
|
||||
01 01 60 00 e5 10 e1 20 00 00 00 00 00 00 00 00
|
||||
01 01 66 00 e5 10 e1 20 00 00 00 00 ff ff ff ff
|
||||
01 20 80 00 be 00 60 30 80 00 8d 00 00 00 00 00
|
||||
01 02 00 00 e6 10 c0 21 00 00 00 00 00 00 00 00
|
||||
01 01 60 00 a6 00 ef 21 64 00 0e 00 00 00 00 00
|
||||
01 02 00 00 a6 00 c0 21 00 01 00 00 00 00 00 00
|
||||
01 20 80 00 3d 01 80 21 80 00 8d 00 00 00 00 00
|
||||
01 20 80 00 a5 03 80 20 80 01 8d 00 00 00 00 00
|
||||
01 20 80 00 bd 00 80 21 80 00 8d 00 00 00 00 00
|
||||
01 01 60 00 26 00 ef 21 40 00 60 00 00 00 00 00
|
||||
01 01 60 00 a5 00 e1 20 85 00 05 00 00 00 00 00
|
||||
01 05 60 00 a5 00 e1 20 40 01 60 00 00 00 00 00
|
||||
01 09 60 00 a5 00 e2 20 85 00 05 00 00 00 00 00
|
||||
01 20 80 00 62 00 40 20 00 00 00 00 00 00 00 00
|
||||
01 20 80 00 a6 00 c0 20 2c 01 00 00 00 00 00 00
|
||||
01 20 80 00 e2 10 00 21 00 00 00 00 00 00 00 00
|
||||
01 20 80 00 a6 03 40 20 80 00 8d 00 00 00 00 00
|
||||
01 05 60 00 be 00 a1 20 60 00 60 00 00 00 00 00
|
||||
01 09 60 00 e6 10 ae 20 00 00 00 00 00 00 00 00
|
||||
01 20 80 80 be 03 60 30 40 00 00 00 00 00 00 00
|
||||
01 01 60 00 fe 52 cf 20 00 00 00 00 30 40 48 50
|
||||
01 00 60 00 fe 73 60 20 00 00 00 00 66 66 fc 42
|
||||
01 10 60 00 fe 73 60 20 00 00 00 00 66 66 fc 42
|
||||
01 09 60 00 a6 00 a8 20 0f 01 6f 00 00 00 00 00
|
||||
01 01 60 00 a5 03 c1 20 c0 00 60 00 00 00 00 00
|
||||
01 00 60 00 be 03 60 20 00 80 e0 01 00 00 00 00
|
||||
01 10 60 00 be 03 e0 20 00 80 e0 01 00 00 00 00
|
||||
01 05 60 00 e5 10 82 22 00 00 00 00 e3 a5 2b c0
|
||||
01 09 60 00 e5 10 84 22 00 00 00 00 47 03 08 41
|
||||
01 0d 60 00 e5 10 84 23 00 00 00 00 a8 35 4d be
|
||||
01 01 60 00 85 00 a1 20 04 04 6e 00 00 00 00 00
|
||||
01 05 60 00 e6 10 a8 21 00 00 00 00 00 00 00 42
|
||||
01 01 60 00 e5 52 6e 21 00 00 00 00 00 30 40 48
|
||||
01 09 60 00 fe 52 a7 21 00 00 00 00 7d 7e 7f 00
|
||||
01 20 80 00 22 00 60 30 80 00 8d 00 00 00 00 00
|
||||
01 01 60 00 fe 73 c1 20 00 00 00 00 00 00 00 00
|
||||
01 01 67 00 e5 10 61 20 00 00 00 00 ff ff ff ff
|
||||
01 00 60 00 bd 00 60 20 40 00 00 00 00 00 00 00
|
||||
01 00 60 00 be 00 60 20 40 00 8d 00 00 00 00 00
|
||||
01 0d 60 00 be 00 a2 20 60 00 60 00 00 00 00 00
|
||||
01 09 60 00 be 00 a8 20 60 00 60 00 00 00 00 00
|
||||
01 05 60 00 bd 00 61 20 60 00 60 00 00 00 00 00
|
||||
01 0d 60 00 bd 00 62 20 80 00 60 00 00 00 00 00
|
||||
01 09 60 00 bd 00 68 20 80 00 60 00 00 00 00 00
|
||||
01 01 60 00 21 00 0f 21 44 00 6e 00 00 00 00 00
|
||||
01 01 60 00 bd 00 e1 20 60 00 00 00 00 00 00 00
|
||||
01 05 60 00 bd 03 c1 20 a5 40 65 00 00 00 00 00
|
||||
01 20 80 02 bd 03 80 20 40 60 00 00 00 00 00 00
|
||||
01 20 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf
|
||||
01 20 80 00 a5 00 00 23 40 05 8d 00 00 00 00 00
|
||||
01 00 60 00 bd 03 00 21 00 80 e0 01 00 00 00 00
|
||||
01 10 60 00 bd 03 20 21 00 80 e0 01 00 00 00 00
|
||||
01 01 60 00 fd 73 67 20 00 00 00 00 00 00 00 00
|
||||
01 20 80 00 22 01 40 20 80 03 8d 00 00 00 00 00
|
||||
01 00 60 00 a6 00 60 20 40 00 00 00 00 00 00 00
|
||||
01 10 60 00 a6 00 60 20 40 00 00 00 00 00 00 00
|
||||
01 02 00 00 62 00 c8 21 00 00 00 00 00 00 00 00
|
||||
01 0d 60 00 a5 00 a4 20 30 00 00 00 00 00 00 00
|
||||
01 09 60 80 be 03 a8 20 8f 02 6f 00 00 00 00 00
|
||||
01 05 60 00 61 00 47 23 00 00 00 00 00 00 00 00
|
||||
01 05 60 00 a6 00 23 21 89 00 0a 00 00 00 00 00
|
||||
01 01 60 00 be 00 af 20 64 00 6e 00 00 00 00 00
|
||||
01 02 60 00 be 03 60 20 80 00 8d 00 00 00 00 00
|
||||
01 01 60 80 fe 73 a4 20 00 00 00 00 ab aa aa 3e
|
||||
01 05 60 80 fe 73 a8 20 00 00 00 00 cd cc cc 3d
|
||||
01 0d 60 00 a6 00 a4 20 6a 00 6a 00 00 00 00 00
|
||||
01 0d 60 00 e6 10 a2 21 00 00 00 00 00 00 08 42
|
||||
01 09 60 80 fe 73 a8 20 00 00 00 00 00 00 80 3f
|
||||
01 01 60 80 be 00 af 20 64 00 6e 00 00 00 00 00
|
||||
01 0d 60 80 fe 73 a4 20 00 00 00 00 60 66 66 3f
|
||||
01 20 80 00 bd 03 40 21 40 00 00 00 00 00 00 00
|
||||
01 20 80 00 fd 73 40 21 00 00 00 00 00 00 80 3f
|
||||
01 01 60 00 e6 10 ef 21 00 00 00 00 00 00 00 00
|
||||
01 20 80 80 bd 03 80 20 40 00 00 00 00 00 00 00
|
||||
01 01 60 00 bd 03 47 20 4f 00 6f 00 00 00 00 00
|
||||
01 09 60 00 fd 52 a7 20 00 00 00 00 7d 7e 7f 00
|
||||
01 05 60 80 be 03 a1 20 80 00 60 00 00 00 00 00
|
||||
01 0d 60 80 be 03 a6 20 a0 00 65 00 00 00 00 00
|
||||
01 02 00 00 28 01 02 26 00 00 00 00 00 00 00 00
|
||||
01 02 00 00 09 01 00 20 02 06 00 00 00 00 00 00
|
||||
01 05 60 00 fe 52 ac 20 00 00 00 00 00 00 00 30
|
||||
01 05 60 80 be 00 a1 20 a0 00 60 00 00 00 00 00
|
||||
01 0d 60 80 be 00 a2 20 a0 00 60 00 00 00 00 00
|
||||
01 09 60 80 be 00 a8 20 a0 00 60 00 00 00 00 00
|
||||
01 09 60 00 e5 52 c6 20 00 00 00 00 00 c0 f7 00
|
||||
01 05 60 00 62 00 47 20 00 00 00 00 00 00 00 00
|
||||
01 09 60 00 22 00 48 20 00 01 60 00 00 00 00 00
|
||||
01 01 60 00 3d 00 af 20 64 00 6e 00 00 00 00 00
|
||||
01 01 60 02 a4 00 01 20 00 01 60 00 00 00 00 00
|
||||
01 01 60 02 bd 03 0f 21 24 60 0e 00 00 00 00 00
|
||||
01 01 61 00 fd 73 0f 21 00 00 00 00 00 00 80 bf
|
||||
37
src/intel/tools/tests/gen4.5/mul.asm
Normal file
37
src/intel/tools/tests/gen4.5/mul.asm
Normal file
@ -0,0 +1,37 @@
|
||||
mul(16) m3<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr4 };
|
||||
mul(8) g8<1>.xyzF g6<4>.xyzzF g8<4>.wF { align16 };
|
||||
mul(8) g9<1>.wUD g7<4>.wF 0x45000000F /* 2048F */ { align16 };
|
||||
mul(16) g22<1>F g18<8,8,1>F g20<8,8,1>F { align1 compr };
|
||||
mul(8) g8<1>.xD g8<4>.xD g5<0>.xD { align16 };
|
||||
mul(8) g8<1>.xD g8<4>.xD 32D { align16 };
|
||||
mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
|
||||
mul(16) m3<1>F g6<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 compr4 };
|
||||
mul(8) m5<1>.xyF g3<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
|
||||
mul(8) g5<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 };
|
||||
mul.sat(16) m2<1>F g14<8,8,1>F g6<8,8,1>F { align1 compr };
|
||||
mul(8) acc0<1>D g1<0>.xD g1<0>.yD { align16 };
|
||||
mul(8) m5<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 };
|
||||
mul(16) g4<1>D g6<8,8,1>D g2<0,1,0>D { align1 compr };
|
||||
mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr };
|
||||
mul(8) g4<1>F g4<8,8,1>F g55<8,8,1>F { align1 };
|
||||
mul(8) g26<1>.wUD g29<4>.wF 0x45000000F /* 2048F */ { align16 NoDDChk };
|
||||
mul(8) g2<1>.xyzF g2<4>.wF 0x40404830VF /* [1F, 3F, 2F, 2F]VF */ { align16 };
|
||||
mul(16) g4<1>D g2<0,1,0>UW g2.2<0,1,0>D { align1 compr };
|
||||
mul.sat(8) g6<1>.xyzF g6<4>.xyzzF g7<4>.xF { align16 };
|
||||
mul.sat(8) m5<1>F g6<4>F 0x3b800000F /* 0.00390625F */ { align16 };
|
||||
mul.sat(8) m5<1>.xyzF g3<4>.xyzzF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
|
||||
mul.g.f0.0(16) null<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr };
|
||||
mul.l.f0.0(8) null<1>.xF g1<0>.zF g1<0>.yF { align16 };
|
||||
mul.l.f0.0(16) null<1>F g2.2<0,1,0>F g2.1<0,1,0>F { align1 compr };
|
||||
mul.l.f0.0(16) g14<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr };
|
||||
mul(8) m5<1>.xyF g3<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDChk };
|
||||
mul.nz.f0.0(16) g16<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr };
|
||||
mul.sat(8) m6<1>.xyzF g32<4>.xF g30<4>.xyzzF { align16 NoDDClr };
|
||||
mul.nz.f0.0(16) g6<1>F g4<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 compr };
|
||||
mul.sat(8) m5<1>.xyF g1<0>.wzzzF g3<4>.wzzzF { align16 };
|
||||
mul.sat(8) m5<1>F g4<4>F 0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 };
|
||||
mul(8) m5<1>F g3<4>F 0x20305454VF /* [5F, 5F, 1F, 0.5F]VF */ { align16 };
|
||||
mul(8) m6<1>.xyzF g12<4>.xyzzF g13<4>.xF { align16 NoDDClr };
|
||||
mul(8) m5<1>.xyzF g3<4>.xyzzF 0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr };
|
||||
mul(8) m5<1>.zF g3<4>.zF 0x3f000000F /* 0.5F */ { align16 NoDDClr,NoDDChk };
|
||||
mul(8) m5<1>F g3<4>F g1<0>.xF { align16 };
|
||||
37
src/intel/tools/tests/gen4.5/mul.expected
Normal file
37
src/intel/tools/tests/gen4.5/mul.expected
Normal file
@ -0,0 +1,37 @@
|
||||
41 20 80 00 be 77 60 30 40 01 8d 00 80 01 8d 00
|
||||
41 01 60 00 bd 77 07 21 c4 00 6a 00 0f 01 6f 00
|
||||
41 01 60 00 a1 7f 28 21 ef 00 6f 00 00 00 00 45
|
||||
41 20 80 00 bd 77 c0 22 40 02 8d 00 80 02 8d 00
|
||||
41 01 60 00 a5 14 01 21 00 01 60 00 a0 00 00 00
|
||||
41 01 60 00 a5 1c 01 21 00 01 60 00 20 00 00 00
|
||||
41 20 80 00 bd 7f c0 22 00 02 8d 00 00 00 80 41
|
||||
41 20 80 00 be 7f 60 30 c0 00 8d 00 00 00 80 3b
|
||||
41 05 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f
|
||||
41 01 60 00 bd 7f af 20 64 00 6e 00 00 00 80 37
|
||||
41 20 80 80 be 77 40 20 c0 01 8d 00 c0 00 8d 00
|
||||
41 01 60 00 a4 14 0f 24 20 00 00 00 25 00 05 00
|
||||
41 01 60 00 be 7f af 20 64 00 6e 00 00 00 00 3f
|
||||
41 20 80 00 a5 14 80 20 c0 00 8d 00 40 00 00 00
|
||||
41 20 80 80 bd 77 40 22 00 02 8d 00 c0 01 8d 00
|
||||
41 00 60 00 bd 77 80 20 80 00 8d 00 e0 06 8d 00
|
||||
41 09 60 00 a1 7f 48 23 af 03 6f 00 00 00 00 45
|
||||
41 01 60 00 bd 5f 47 20 4f 00 6f 00 30 48 40 40
|
||||
41 20 80 00 25 15 80 20 40 00 00 00 48 00 00 00
|
||||
41 01 60 80 bd 77 c7 20 c4 00 6a 00 e0 00 60 00
|
||||
41 01 60 80 be 7f af 20 c4 00 6e 00 00 00 80 3b
|
||||
41 05 60 80 be 7f a7 20 64 00 6a 00 00 00 00 3f
|
||||
41 20 80 03 bc 77 00 20 40 01 8d 00 80 01 8d 00
|
||||
41 01 60 05 bc 77 01 20 2a 00 0a 00 25 00 05 00
|
||||
41 20 80 05 bc 77 00 20 48 00 00 00 44 00 00 00
|
||||
41 20 80 05 bd 77 c0 21 40 01 8d 00 80 01 8d 00
|
||||
41 09 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f
|
||||
41 20 80 02 bd 77 00 22 40 01 8d 00 80 01 8d 00
|
||||
41 05 60 80 be 77 c7 20 00 04 60 00 c4 03 6a 00
|
||||
41 20 80 02 bd 7f c0 20 80 00 8d 00 00 80 80 3f
|
||||
41 01 60 80 be 77 a3 20 2b 00 0a 00 6b 00 6a 00
|
||||
41 01 60 80 be 5f af 20 84 00 6e 00 30 30 30 20
|
||||
41 01 60 00 be 5f af 20 64 00 6e 00 54 54 30 20
|
||||
41 05 60 00 be 77 c7 20 84 01 6a 00 a0 01 60 00
|
||||
41 05 60 00 be 5f a7 20 64 00 6a 00 20 20 30 30
|
||||
41 0d 60 00 be 7f a4 20 6a 00 6a 00 00 00 00 3f
|
||||
41 01 60 00 be 77 af 20 64 00 6e 00 20 00 00 00
|
||||
3
src/intel/tools/tests/gen4.5/not.asm
Normal file
3
src/intel/tools/tests/gen4.5/not.asm
Normal file
@ -0,0 +1,3 @@
|
||||
not(16) g6<1>D -g4<8,8,1>D { align1 compr };
|
||||
not(8) g2<1>D -g2<8,8,1>D { align1 };
|
||||
not(8) g5<1>.xD g5<4>.xD { align16 };
|
||||
3
src/intel/tools/tests/gen4.5/not.expected
Normal file
3
src/intel/tools/tests/gen4.5/not.expected
Normal file
@ -0,0 +1,3 @@
|
||||
04 20 80 00 a5 00 c0 20 80 40 8d 00 00 00 00 00
|
||||
04 00 60 00 a5 00 40 20 40 40 8d 00 00 00 00 00
|
||||
04 01 60 00 a5 00 a1 20 a0 00 60 00 00 00 00 00
|
||||
6
src/intel/tools/tests/gen4.5/or.asm
Normal file
6
src/intel/tools/tests/gen4.5/or.asm
Normal file
@ -0,0 +1,6 @@
|
||||
or(8) g13<1>.xUD g13<4>.xUD g14<4>.xUD { align16 };
|
||||
or(8) g3<1>UD g3<8,8,1>UD g5<8,8,1>UD { align1 };
|
||||
or(16) g12<1>UD g14<8,8,1>UD g20<8,8,1>UD { align1 compr };
|
||||
(+f0.0) or(16) g12<1>UD g12<8,8,1>UD 0x3f800000UD { align1 compr };
|
||||
or(8) m2<1>.wUD g10<4>.xUD g11<4>.xUD { align16 };
|
||||
(+f0.0) or(8) g17<1>.xUD g17<4>.xUD 0x3f800000UD { align16 };
|
||||
6
src/intel/tools/tests/gen4.5/or.expected
Normal file
6
src/intel/tools/tests/gen4.5/or.expected
Normal file
@ -0,0 +1,6 @@
|
||||
06 01 60 00 21 04 a1 21 a0 01 60 00 c0 01 60 00
|
||||
06 00 60 00 21 04 60 20 60 00 8d 00 a0 00 8d 00
|
||||
06 20 80 00 21 04 80 21 c0 01 8d 00 80 02 8d 00
|
||||
06 20 81 00 21 0c 80 21 80 01 8d 00 00 00 80 3f
|
||||
06 01 60 00 22 04 48 20 40 01 60 00 60 01 60 00
|
||||
06 01 61 00 21 0c 21 22 20 02 60 00 00 00 80 3f
|
||||
3
src/intel/tools/tests/gen4.5/pln.asm
Normal file
3
src/intel/tools/tests/gen4.5/pln.asm
Normal file
@ -0,0 +1,3 @@
|
||||
pln(16) g10<1>F g3.4<0,1,0>F g6<8,8,1>F { align1 compr };
|
||||
pln(8) g37<1>F g4.4<0,1,0>F g38<8,8,1>F { align1 };
|
||||
pln(16) m4<1>F g5.4<0,1,0>F g6<8,8,1>F { align1 compr4 };
|
||||
3
src/intel/tools/tests/gen4.5/pln.expected
Normal file
3
src/intel/tools/tests/gen4.5/pln.expected
Normal file
@ -0,0 +1,3 @@
|
||||
5a 20 80 00 bd 77 40 21 70 00 00 00 c0 00 8d 00
|
||||
5a 00 60 00 bd 77 a0 24 90 00 00 00 c0 04 8d 00
|
||||
5a 20 80 00 be 77 80 30 b0 00 00 00 c0 00 8d 00
|
||||
4
src/intel/tools/tests/gen4.5/rndd.asm
Normal file
4
src/intel/tools/tests/gen4.5/rndd.asm
Normal file
@ -0,0 +1,4 @@
|
||||
rndd(16) g16<1>F g24<8,8,1>F { align1 compr };
|
||||
rndd(8) g6<1>.xF g1<0>.xF { align16 };
|
||||
rndd(8) g6<1>.xF (abs)g1<0>.xF { align16 NoDDClr };
|
||||
rndd(8) g6<1>.yF g7<4>.xF { align16 NoDDClr,NoDDChk };
|
||||
4
src/intel/tools/tests/gen4.5/rndd.expected
Normal file
4
src/intel/tools/tests/gen4.5/rndd.expected
Normal file
@ -0,0 +1,4 @@
|
||||
45 20 80 00 bd 03 00 22 00 03 8d 00 00 00 00 00
|
||||
45 01 60 00 bd 03 c1 20 20 00 00 00 00 00 00 00
|
||||
45 05 60 00 bd 03 c1 20 20 20 00 00 00 00 00 00
|
||||
45 0d 60 00 bd 03 c2 20 e0 00 60 00 00 00 00 00
|
||||
31
src/intel/tools/tests/gen4.5/sel.asm
Normal file
31
src/intel/tools/tests/gen4.5/sel.asm
Normal file
@ -0,0 +1,31 @@
|
||||
(+f0.0.any4h) sel(8) g7<1>UD g9<4>UD g8<4>UD { align16 };
|
||||
(+f0.0) sel(8) g10<1>.xyUD g7<4>.xyyyUD g3<0>.zwwwUD { align16 };
|
||||
(+f0.0.all4h) sel(8) g6<1>UD g6<4>UD g7<4>UD { align16 };
|
||||
(+f0.0) sel(16) g6<1>UD g40<8,8,1>UD g46<8,8,1>UD { align1 compr };
|
||||
(+f0.0) sel(16) m3<1>UD g30<8,8,1>UD 0x3f800000UD { align1 compr4 };
|
||||
(+f0.0) sel(16) g10<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
|
||||
(-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
|
||||
(+f0.0.x) sel(8) g6<1>.xUD g6<4>.yUD 0x41a80000UD { align16 };
|
||||
(-f0.0.x) sel(8) g6<1>.xUD g6<4>.xUD 0x41b80000UD { align16 };
|
||||
(+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
|
||||
(+f0.0) sel(16) m3<1>UD g18<8,8,1>UD g24<8,8,1>UD { align1 compr4 };
|
||||
(+f0.0.x) sel(8) g10<1>.xUD g9<4>.yUD g9<4>.xUD { align16 };
|
||||
(+f0.0) sel(16) g28<1>UD g8<0,1,0>UD 0x00000000UD { align1 compr };
|
||||
(+f0.0) sel(8) g28<1>.yF g32<4>.xF 0x0F /* 0F */ { align16 };
|
||||
(-f0.0.z) sel(8) g28<1>.zUD g31<4>.xUD 0x00000000UD { align16 };
|
||||
(+f0.0) sel.sat(8) m5<1>F g1<0>F g3<4>F { align16 };
|
||||
(-f0.0) sel(16) g8<1>F (abs)g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
(-f0.0) sel(16) m3<1>UD g14<8,8,1>UD 0x3f00022fUD { align1 compr4 };
|
||||
(+f0.0) sel(16) m4<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr4 };
|
||||
(-f0.0.y) sel(8) g3<1>.yUD g4<4>.xUD 0x00000000UD { align16 };
|
||||
(+f0.0) sel(8) g5<1>UD g3<4>UD 0x00000000UD { align16 };
|
||||
(+f0.0.y) sel(8) g3<1>.yUD g1<0>.wUD g1<0>.zUD { align16 };
|
||||
(+f0.0) sel(8) g5<1>.xyF g1<0>.xyyyF g1<0>.zF { align16 };
|
||||
(+f0.0.x) sel(8) g5<1>.xF g1<0>.xF -g1<0>.xF { align16 };
|
||||
(-f0.0) sel(8) g5<1>.wUD g5<4>.wUD 0x3f800000UD { align16 };
|
||||
(-f0.0) sel(8) g4<1>.xyzF (abs)g4<4>.xyzzF 0x3f800000F /* 1F */ { align16 };
|
||||
(+f0.0.x) sel(8) g4<1>.xD -g4<4>.xD 0D { align16 };
|
||||
(+f0.0) sel(16) g4<1>D -g6<8,8,1>D -1D { align1 compr };
|
||||
(-f0.0.x) sel(8) g3<1>.xF (abs)g3<4>.xF 0x3f800000F /* 1F */ { align16 };
|
||||
(+f0.0) sel(16) m3<1>F g4<8,8,1>F 0x3f800000F /* 1F */ { align1 compr4 };
|
||||
(+f0.0) sel.sat(8) m5<1>F g6<4>F 0xbf800000F /* -1F */ { align16 };
|
||||
31
src/intel/tools/tests/gen4.5/sel.expected
Normal file
31
src/intel/tools/tests/gen4.5/sel.expected
Normal file
@ -0,0 +1,31 @@
|
||||
02 01 66 00 21 04 ef 20 24 01 6e 00 04 01 6e 00
|
||||
02 01 61 00 21 04 43 21 e4 00 65 00 6e 00 0f 00
|
||||
02 01 67 00 21 04 cf 20 c4 00 6e 00 e4 00 6e 00
|
||||
02 20 81 00 21 04 c0 20 00 05 8d 00 c0 05 8d 00
|
||||
02 20 81 00 22 0c 60 30 c0 03 8d 00 00 00 80 3f
|
||||
02 20 81 00 bd 7f 40 21 c0 00 8d 00 00 00 00 00
|
||||
02 20 91 00 21 0c 80 20 c0 00 8d 00 00 00 00 00
|
||||
02 01 62 00 21 0c c1 20 c5 00 65 00 00 00 a8 41
|
||||
02 01 72 00 21 0c c1 20 c0 00 60 00 00 00 b8 41
|
||||
02 20 81 00 bd 77 80 20 00 22 8d 00 00 21 8d 00
|
||||
02 20 81 00 22 04 60 30 40 02 8d 00 00 03 8d 00
|
||||
02 01 62 00 21 04 41 21 25 01 65 00 20 01 60 00
|
||||
02 20 81 00 21 0c 80 23 00 01 00 00 00 00 00 00
|
||||
02 01 61 00 bd 7f 82 23 00 04 60 00 00 00 00 00
|
||||
02 01 74 00 21 0c 84 23 e0 03 60 00 00 00 00 00
|
||||
02 01 61 80 be 77 af 20 24 00 0e 00 64 00 6e 00
|
||||
02 20 91 00 bd 7f 00 21 c0 20 8d 00 00 00 80 3f
|
||||
02 20 91 00 22 0c 60 30 c0 01 8d 00 2f 02 00 3f
|
||||
02 20 81 00 be 77 80 30 80 00 8d 00 c0 00 8d 00
|
||||
02 01 73 00 21 0c 62 20 80 00 60 00 00 00 00 00
|
||||
02 01 61 00 21 0c af 20 64 00 6e 00 00 00 00 00
|
||||
02 01 63 00 21 04 62 20 2f 00 0f 00 2a 00 0a 00
|
||||
02 01 61 00 bd 77 a3 20 24 00 05 00 2a 00 0a 00
|
||||
02 01 62 00 bd 77 a1 20 20 00 00 00 20 40 00 00
|
||||
02 01 71 00 21 0c a8 20 af 00 6f 00 00 00 80 3f
|
||||
02 01 71 00 bd 7f 87 20 84 20 6a 00 00 00 80 3f
|
||||
02 01 62 00 a5 1c 81 20 80 40 60 00 00 00 00 00
|
||||
02 20 81 00 a5 1c 80 20 c0 40 8d 00 ff ff ff ff
|
||||
02 01 72 00 bd 7f 61 20 60 20 60 00 00 00 80 3f
|
||||
02 20 81 00 be 7f 60 30 80 00 8d 00 00 00 80 3f
|
||||
02 01 61 80 be 7f af 20 c4 00 6e 00 00 00 80 bf
|
||||
222
src/intel/tools/tests/gen4.5/send.asm
Normal file
222
src/intel/tools/tests/gen4.5/send.asm
Normal file
@ -0,0 +1,222 @@
|
||||
send(16) 2 g12<1>F g10<8,8,1>F 0x01110001
|
||||
math MsgDesc: inv mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04800
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
|
||||
send(8) 1 g8<1>.wF g6<4>.wF 0x01110001
|
||||
math MsgDesc: inv mlen 1 rlen 1 { align16 };
|
||||
send(8) 1 null<1>F g0<4>F 0x8650c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x8640c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
|
||||
send(8) 13 g0<1>F g0<4>F 0x053190ff
|
||||
write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 };
|
||||
send(8) 14 g9<1>F g0<4>F 0x042150ff
|
||||
read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 };
|
||||
send(8) 1 null<1>F g0<4>F 0x8680c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02780001
|
||||
sampler MsgDesc: (1, 0, 0, ) mlen 7 rlen 8 { align1 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580001
|
||||
sampler MsgDesc: (1, 0, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(8) 14 g3<1>UD g0<4>F 0x04211000
|
||||
read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 1 { align16 };
|
||||
send(8) 1 g6<1>.xF g6<4>.xF 0x01110004
|
||||
math MsgDesc: sqrt mlen 1 rlen 1 { align16 };
|
||||
send(16) 1 g26<1>UW g0<8,8,1>UW 0x02382001
|
||||
sampler MsgDesc: (1, 0, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02983001
|
||||
sampler MsgDesc: (1, 0, 3, ) mlen 9 rlen 8 { align1 };
|
||||
send(8) 1 null<1>F g0<4>F 0x06d04400
|
||||
urb MsgDesc: 0 urb_write interleave used mlen 13 rlen 0 { align16 };
|
||||
send(8) 1 null<1>F g0<4>F 0x8650c460
|
||||
urb MsgDesc: 6 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x8660c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 6 rlen 0 { align16 EOT };
|
||||
send(8) 2 g6<1>F g4<8,8,1>F 0x0121000a
|
||||
math MsgDesc: pow mlen 2 rlen 1 { align1 };
|
||||
send(16) 1 g16<1>UW g0<8,8,1>UW 0x02380001
|
||||
sampler MsgDesc: (1, 0, 0, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 2 g6<1>F g4<8,8,1>F 0x01110007
|
||||
math MsgDesc: cos mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 13 g8<1>UW g0<8,8,1>F 0x02383001
|
||||
sampler MsgDesc: (1, 0, 3, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 2 g4<1>F g2.4<0,1,0>F 0x01110081
|
||||
math MsgDesc: inv scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02980001
|
||||
sampler MsgDesc: (1, 0, 0, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85e04800
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x8670c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 EOT };
|
||||
send(8) 1 null<1>UW g0<8,8,1>UW 0x85604c00
|
||||
write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x8680c460
|
||||
urb MsgDesc: 6 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
|
||||
send(8) 1 g5<1>.yF g6<4>.xF 0x01110006
|
||||
math MsgDesc: sin mlen 1 rlen 1 { align16 };
|
||||
send(8) 1 g7<1>.xD g1<0>.zD 0x0121001c
|
||||
math MsgDesc: intdiv signed mlen 2 rlen 1 { align16 };
|
||||
send(8) 1 null<1>F g0<4>F 0x8640c460
|
||||
urb MsgDesc: 6 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85c04800
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x86b0c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 EOT };
|
||||
send(16) 2 g6<1>F g4<8,8,1>F 0x01110003
|
||||
math MsgDesc: exp mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02983005
|
||||
sampler MsgDesc: (5, 0, 3, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 g12<1>UW g0<8,8,1>UW 0x02983006
|
||||
sampler MsgDesc: (6, 0, 3, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 g20<1>UW g0<8,8,1>UW 0x02983007
|
||||
sampler MsgDesc: (7, 0, 3, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 g28<1>UW g0<8,8,1>UW 0x02983008
|
||||
sampler MsgDesc: (8, 0, 3, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04000
|
||||
write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04001
|
||||
write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04002
|
||||
write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04803
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT };
|
||||
send(8) 2 g4<1>D g2.4<0,1,0>D 0x0121009c
|
||||
math MsgDesc: intdiv signed scalar mlen 2 rlen 1 { align1 };
|
||||
send(16) 14 g8<1>UW null<8,8,1>F 0x04120301
|
||||
read MsgDesc: OWord Block Read MsgCtrl = 0x3 Surface = 1 mlen 1 rlen 2 { align1 nomask };
|
||||
send(8) 1 g30<1>.xF (abs)g30<4>.xF 0x01110005
|
||||
math MsgDesc: rsq mlen 1 rlen 1 { align16 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02981001
|
||||
sampler MsgDesc: (1, 0, 1, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 2 g4<1>F g2<0,1,0>F 0x01110086
|
||||
math MsgDesc: sin scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 2 g6<1>F g2<0,1,0>F 0x01110087
|
||||
math MsgDesc: cos scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 2 g4<1>F g2.1<0,1,0>F 0x01110085
|
||||
math MsgDesc: rsq scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85f04800
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02982001
|
||||
sampler MsgDesc: (1, 0, 2, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580304
|
||||
sampler MsgDesc: (4, 3, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(8) 1 g5<1>.xF g1<0>.xF 0x01110002
|
||||
math MsgDesc: log mlen 1 rlen 1 { align16 };
|
||||
send(8) 1 g6<1>UW g0<8,8,1>UW 0x02640001
|
||||
sampler MsgDesc: (1, 0, 0, ) mlen 6 rlen 4 { align1 };
|
||||
send(8) 1 g10<1>UW g0<8,8,1>UW 0x02641001
|
||||
sampler MsgDesc: (1, 0, 1, ) mlen 6 rlen 4 { align1 };
|
||||
send(8) 2 g4<1>F g2<0,1,0>F 0x012100ca
|
||||
math MsgDesc: pow sat scalar mlen 2 rlen 1 { align1 };
|
||||
send(16) 1 g16<1>UW g0<8,8,1>UW 0x02982102
|
||||
sampler MsgDesc: (2, 1, 2, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04801
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x8690c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 EOT };
|
||||
send(8) 1 null<1>F g0<4>F 0x86c0c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 12 rlen 0 { align16 EOT };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04802
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 EOT };
|
||||
send(16) 1 g20<1>UW g0<8,8,1>UW 0x02580102
|
||||
sampler MsgDesc: (2, 1, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(8) 1 null<1>F g0<4>F 0x86a0c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 10 rlen 0 { align16 EOT };
|
||||
send(16) 2 g4<1>F g2<0,1,0>F 0x01110082
|
||||
math MsgDesc: log scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 1 g14<1>UW g0<8,8,1>UW 0x02382102
|
||||
sampler MsgDesc: (2, 1, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g26<1>UW g0<8,8,1>UW 0x02382203
|
||||
sampler MsgDesc: (3, 2, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g26<1>UW g0<8,8,1>UW 0x02580203
|
||||
sampler MsgDesc: (3, 2, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(16) 1 g34<1>UW g0<8,8,1>UW 0x02382304
|
||||
sampler MsgDesc: (4, 3, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g42<1>UW g0<8,8,1>UW 0x02382405
|
||||
sampler MsgDesc: (5, 4, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g42<1>UW g0<8,8,1>UW 0x02580405
|
||||
sampler MsgDesc: (5, 4, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(16) 1 g50<1>UW g0<8,8,1>UW 0x02382506
|
||||
sampler MsgDesc: (6, 5, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g50<1>UW g0<8,8,1>UW 0x02580506
|
||||
sampler MsgDesc: (6, 5, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(16) 1 g58<1>UW g0<8,8,1>UW 0x02382607
|
||||
sampler MsgDesc: (7, 6, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g58<1>UW g0<8,8,1>UW 0x02580607
|
||||
sampler MsgDesc: (7, 6, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(16) 1 g66<1>UW g0<8,8,1>UW 0x02382708
|
||||
sampler MsgDesc: (8, 7, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g66<1>UW g0<8,8,1>UW 0x02580708
|
||||
sampler MsgDesc: (8, 7, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(8) 1 null<1>F g0<4>F 0x86d0c400
|
||||
urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 EOT };
|
||||
send(8) 1 g10<1>UW g0<8,8,1>UW 0x02641102
|
||||
sampler MsgDesc: (2, 1, 1, ) mlen 6 rlen 4 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85b04800
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 11 rlen 0 { align1 EOT };
|
||||
send(8) 2 g3<1>F g0<4>F 0x02211505
|
||||
sampler MsgDesc: (5, 5, 1, ) mlen 2 rlen 1 { align16 };
|
||||
send(16) 2 g4<1>F g2<0,1,0>F 0x011100c4
|
||||
math MsgDesc: sqrt sat scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(16) 2 g4<1>F g2<0,1,0>F 0x011100c3
|
||||
math MsgDesc: exp sat scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(8) 2 g3<1>F g0<4>F 0x02211000
|
||||
sampler MsgDesc: (0, 0, 1, ) mlen 2 rlen 1 { align16 };
|
||||
send(16) 13 g24<1>UW g0<8,8,1>F 0x02383002
|
||||
sampler MsgDesc: (2, 0, 3, ) mlen 3 rlen 8 { align1 };
|
||||
send(8) 1 g3<1>F g1<0>F 0x01110044
|
||||
math MsgDesc: sqrt sat mlen 1 rlen 1 { align16 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02983002
|
||||
sampler MsgDesc: (2, 0, 3, ) mlen 9 rlen 8 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04003
|
||||
write MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04804
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 EOT };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04004
|
||||
write MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04805
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 EOT };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04005
|
||||
write MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04806
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 EOT };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x05a04006
|
||||
write MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 };
|
||||
send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04807
|
||||
write MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 EOT };
|
||||
send(8) 1 g8<1>UW g0<8,8,1>UW 0x02742001
|
||||
sampler MsgDesc: (1, 0, 2, ) mlen 7 rlen 4 { align1 };
|
||||
send(16) 1 g12<1>UW g0<8,8,1>UW 0x02780102
|
||||
sampler MsgDesc: (2, 1, 0, ) mlen 7 rlen 8 { align1 };
|
||||
send(8) 1 null<1>F g0<4>F 0x8620c460
|
||||
urb MsgDesc: 6 urb_write interleave used complete mlen 2 rlen 0 { align16 EOT };
|
||||
send(16) 2 g6<1>F g2<0,1,0>F 0x01110084
|
||||
math MsgDesc: sqrt scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(8) 1 g3<1>F g1<0>F 0x01110043
|
||||
math MsgDesc: exp sat mlen 1 rlen 1 { align16 };
|
||||
send(8) 2 g4<1>F g2<0,1,0>F 0x0121008a
|
||||
math MsgDesc: pow scalar mlen 2 rlen 1 { align1 };
|
||||
send(8) 1 g8<1>UW g0<8,8,1>UW 0x02640102
|
||||
sampler MsgDesc: (2, 1, 0, ) mlen 6 rlen 4 { align1 };
|
||||
send(16) 2 g4<1>F g2<0,1,0>F 0x01110083
|
||||
math MsgDesc: exp scalar mlen 1 rlen 1 { align1 compr };
|
||||
send(8) 1 g8<1>UW g0<8,8,1>UW 0x02a42001
|
||||
sampler MsgDesc: (1, 0, 2, ) mlen 10 rlen 4 { align1 };
|
||||
send(16) 1 g14<1>UW g0<8,8,1>UW 0x02580003
|
||||
sampler MsgDesc: (3, 0, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(16) 1 g22<1>UW g0<8,8,1>UW 0x02580004
|
||||
sampler MsgDesc: (4, 0, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580f10
|
||||
sampler MsgDesc: (16, 15, 0, ) mlen 5 rlen 8 { align1 };
|
||||
send(8) 2 g3<1>F g0<4>F 0x02211303
|
||||
sampler MsgDesc: (3, 3, 1, ) mlen 2 rlen 1 { align16 };
|
||||
send(8) 1 g3<1>F g1<0>F 0x0121004a
|
||||
math MsgDesc: pow sat mlen 2 rlen 1 { align16 };
|
||||
send(16) 1 g10<1>UW g0<8,8,1>UW 0x02382004
|
||||
sampler MsgDesc: (4, 0, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g10<1>UW g0<8,8,1>UW 0x02382003
|
||||
sampler MsgDesc: (3, 0, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g10<1>UW g0<8,8,1>UW 0x02382002
|
||||
sampler MsgDesc: (2, 0, 2, ) mlen 3 rlen 8 { align1 };
|
||||
send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580002
|
||||
sampler MsgDesc: (2, 0, 0, ) mlen 5 rlen 8 { align1 };
|
||||
111
src/intel/tools/tests/gen4.5/send.expected
Normal file
111
src/intel/tools/tests/gen4.5/send.expected
Normal file
@ -0,0 +1,111 @@
|
||||
31 20 80 02 bd 0f 80 21 40 01 8d 00 01 00 11 01
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 a0 85
|
||||
31 01 60 01 bd 0f 08 21 cf 00 6f 00 01 00 11 01
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 50 86
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 40 86
|
||||
31 01 60 0d bd 0f 0f 20 04 00 6e 00 ff 90 31 05
|
||||
31 01 60 0e bd 0f 2f 21 04 00 6e 00 ff 50 21 04
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 80 86
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 78 02
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 58 02
|
||||
31 01 60 0e a1 0f 6f 20 04 00 6e 00 00 10 21 04
|
||||
31 01 60 01 bd 0f c1 20 c0 00 60 00 04 00 11 01
|
||||
31 00 80 01 29 0d 40 23 00 00 8d 00 01 20 38 02
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 01 30 98 02
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 44 d0 06
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 50 86
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 60 86
|
||||
31 00 60 02 bd 0f c0 20 80 00 8d 00 0a 00 21 01
|
||||
31 00 80 01 29 0d 00 22 00 00 8d 00 01 00 38 02
|
||||
31 20 80 02 bd 0f c0 20 80 00 8d 00 07 00 11 01
|
||||
31 00 80 0d a9 0f 00 21 00 00 8d 00 01 30 38 02
|
||||
31 20 80 02 bd 0f 80 20 50 00 00 00 81 00 11 01
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 98 02
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 e0 85
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 70 86
|
||||
31 00 60 01 28 0d 00 20 00 00 8d 00 00 4c 60 85
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 80 86
|
||||
31 01 60 01 bd 0f a2 20 c0 00 60 00 06 00 11 01
|
||||
31 01 60 01 a5 0c e1 20 2a 00 0a 00 1c 00 21 01
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 40 86
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 c0 85
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 b0 86
|
||||
31 20 80 02 bd 0f c0 20 80 00 8d 00 03 00 11 01
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 05 30 98 02
|
||||
31 00 80 01 29 0d 80 21 00 00 8d 00 06 30 98 02
|
||||
31 00 80 01 29 0d 80 22 00 00 8d 00 07 30 98 02
|
||||
31 00 80 01 29 0d 80 23 00 00 8d 00 08 30 98 02
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 00 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 01 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 02 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 03 48 a0 85
|
||||
31 00 60 02 a5 0c 80 20 50 00 00 00 9c 00 21 01
|
||||
31 02 80 0e 89 0f 00 21 00 00 8d 00 01 03 12 04
|
||||
31 01 60 01 bd 0f c1 23 c0 23 60 00 05 00 11 01
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 01 10 98 02
|
||||
31 20 80 02 bd 0f 80 20 40 00 00 00 86 00 11 01
|
||||
31 20 80 02 bd 0f c0 20 40 00 00 00 87 00 11 01
|
||||
31 20 80 02 bd 0f 80 20 44 00 00 00 85 00 11 01
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 f0 85
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 01 20 98 02
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 04 03 58 02
|
||||
31 01 60 01 bd 0f a1 20 20 00 00 00 02 00 11 01
|
||||
31 00 60 01 29 0d c0 20 00 00 8d 00 01 00 64 02
|
||||
31 00 60 01 29 0d 40 21 00 00 8d 00 01 10 64 02
|
||||
31 00 60 02 bd 0f 80 20 40 00 00 00 ca 00 21 01
|
||||
31 00 80 01 29 0d 00 22 00 00 8d 00 02 21 98 02
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 01 48 a0 85
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 90 86
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 c0 86
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 02 48 a0 85
|
||||
31 00 80 01 29 0d 80 22 00 00 8d 00 02 01 58 02
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 a0 86
|
||||
31 20 80 02 bd 0f 80 20 40 00 00 00 82 00 11 01
|
||||
31 00 80 01 29 0d c0 21 00 00 8d 00 02 21 38 02
|
||||
31 00 80 01 29 0d 40 23 00 00 8d 00 03 22 38 02
|
||||
31 00 80 01 29 0d 40 23 00 00 8d 00 03 02 58 02
|
||||
31 00 80 01 29 0d 40 24 00 00 8d 00 04 23 38 02
|
||||
31 00 80 01 29 0d 40 25 00 00 8d 00 05 24 38 02
|
||||
31 00 80 01 29 0d 40 25 00 00 8d 00 05 04 58 02
|
||||
31 00 80 01 29 0d 40 26 00 00 8d 00 06 25 38 02
|
||||
31 00 80 01 29 0d 40 26 00 00 8d 00 06 05 58 02
|
||||
31 00 80 01 29 0d 40 27 00 00 8d 00 07 26 38 02
|
||||
31 00 80 01 29 0d 40 27 00 00 8d 00 07 06 58 02
|
||||
31 00 80 01 29 0d 40 28 00 00 8d 00 08 27 38 02
|
||||
31 00 80 01 29 0d 40 28 00 00 8d 00 08 07 58 02
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 d0 86
|
||||
31 00 60 01 29 0d 40 21 00 00 8d 00 02 11 64 02
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 b0 85
|
||||
31 01 60 02 bd 0f 6f 20 04 00 6e 00 05 15 21 02
|
||||
31 20 80 02 bd 0f 80 20 40 00 00 00 c4 00 11 01
|
||||
31 20 80 02 bd 0f 80 20 40 00 00 00 c3 00 11 01
|
||||
31 01 60 02 bd 0f 6f 20 04 00 6e 00 00 10 21 02
|
||||
31 00 80 0d a9 0f 00 23 00 00 8d 00 02 30 38 02
|
||||
31 01 60 01 bd 0f 6f 20 24 00 0e 00 44 00 11 01
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 02 30 98 02
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 03 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 04 48 a0 85
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 04 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 05 48 a0 85
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 05 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 06 48 a0 85
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 06 40 a0 05
|
||||
31 00 80 01 28 0d 00 20 00 00 8d 00 07 48 a0 85
|
||||
31 00 60 01 29 0d 00 21 00 00 8d 00 01 20 74 02
|
||||
31 00 80 01 29 0d 80 21 00 00 8d 00 02 01 78 02
|
||||
31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 20 86
|
||||
31 20 80 02 bd 0f c0 20 40 00 00 00 84 00 11 01
|
||||
31 01 60 01 bd 0f 6f 20 24 00 0e 00 43 00 11 01
|
||||
31 00 60 02 bd 0f 80 20 40 00 00 00 8a 00 21 01
|
||||
31 00 60 01 29 0d 00 21 00 00 8d 00 02 01 64 02
|
||||
31 20 80 02 bd 0f 80 20 40 00 00 00 83 00 11 01
|
||||
31 00 60 01 29 0d 00 21 00 00 8d 00 01 20 a4 02
|
||||
31 00 80 01 29 0d c0 21 00 00 8d 00 03 00 58 02
|
||||
31 00 80 01 29 0d c0 22 00 00 8d 00 04 00 58 02
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 10 0f 58 02
|
||||
31 01 60 02 bd 0f 6f 20 04 00 6e 00 03 13 21 02
|
||||
31 01 60 01 bd 0f 6f 20 24 00 0e 00 4a 00 21 01
|
||||
31 00 80 01 29 0d 40 21 00 00 8d 00 04 20 38 02
|
||||
31 00 80 01 29 0d 40 21 00 00 8d 00 03 20 38 02
|
||||
31 00 80 01 29 0d 40 21 00 00 8d 00 02 20 38 02
|
||||
31 00 80 01 29 0d 80 20 00 00 8d 00 02 00 58 02
|
||||
5
src/intel/tools/tests/gen4.5/shl.asm
Normal file
5
src/intel/tools/tests/gen4.5/shl.asm
Normal file
@ -0,0 +1,5 @@
|
||||
shl(8) g4<1>.xD g1<0>.yD 0x00000004UD { align16 };
|
||||
shl(16) g4<1>D g2.4<0,1,0>D 0x00000004UD { align1 compr };
|
||||
shl(16) m14<1>D g2<0,1,0>D 0x00000004UD { align1 compr };
|
||||
shl(8) g11<1>.xUD g11<4>.xUD 4D { align16 };
|
||||
shl(8) g5<1>D g3<4>D g4<4>UD { align16 };
|
||||
5
src/intel/tools/tests/gen4.5/shl.expected
Normal file
5
src/intel/tools/tests/gen4.5/shl.expected
Normal file
@ -0,0 +1,5 @@
|
||||
09 01 60 00 a5 0c 81 20 25 00 05 00 04 00 00 00
|
||||
09 20 80 00 a5 0c 80 20 50 00 00 00 04 00 00 00
|
||||
09 20 80 00 a6 0c c0 21 40 00 00 00 04 00 00 00
|
||||
09 01 60 00 21 1c 61 21 60 01 60 00 04 00 00 00
|
||||
09 01 60 00 a5 04 af 20 64 00 6e 00 84 00 6e 00
|
||||
1
src/intel/tools/tests/gen4.5/shr.asm
Normal file
1
src/intel/tools/tests/gen4.5/shr.asm
Normal file
@ -0,0 +1 @@
|
||||
shr(1) g10.4<1>UD g10.4<0,1,0>UD 0x00000004UD { align1 nomask };
|
||||
1
src/intel/tools/tests/gen4.5/shr.expected
Normal file
1
src/intel/tools/tests/gen4.5/shr.expected
Normal file
@ -0,0 +1 @@
|
||||
08 02 00 00 21 0c 50 21 50 01 00 00 04 00 00 00
|
||||
4
src/intel/tools/tests/gen4.5/while.asm
Normal file
4
src/intel/tools/tests/gen4.5/while.asm
Normal file
@ -0,0 +1,4 @@
|
||||
while(16) Jump: -10 { align1 };
|
||||
while(8) Jump: -16 { align16 };
|
||||
(-f0.0) while(16) Jump: -11 { align1 };
|
||||
(-f0.0.x) while(8) Jump: -11 { align16 };
|
||||
4
src/intel/tools/tests/gen4.5/while.expected
Normal file
4
src/intel/tools/tests/gen4.5/while.expected
Normal file
@ -0,0 +1,4 @@
|
||||
27 00 80 00 00 1c 00 34 00 14 60 00 f6 ff 00 00
|
||||
27 01 60 00 00 1c 0f 34 04 14 6e 00 f0 ff 00 00
|
||||
27 00 91 00 00 1c 00 34 00 14 60 00 f5 ff 00 00
|
||||
27 01 72 00 00 1c 0f 34 04 14 6e 00 f5 ff 00 00
|
||||
2
src/intel/tools/tests/gen4.5/xor.asm
Normal file
2
src/intel/tools/tests/gen4.5/xor.asm
Normal file
@ -0,0 +1,2 @@
|
||||
xor(16) g4<1>UD g2<0,1,0>UD g2.1<0,1,0>UD { align1 compr };
|
||||
xor(8) g5<1>.xUD g1<0>.xUD g1<0>.yUD { align16 };
|
||||
2
src/intel/tools/tests/gen4.5/xor.expected
Normal file
2
src/intel/tools/tests/gen4.5/xor.expected
Normal file
@ -0,0 +1,2 @@
|
||||
07 20 80 00 21 04 80 20 40 00 00 00 44 00 00 00
|
||||
07 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00
|
||||
48
src/intel/tools/tests/gen4/add.asm
Normal file
48
src/intel/tools/tests/gen4/add.asm
Normal file
@ -0,0 +1,48 @@
|
||||
add(16) g10<1>UW g1.4<2,4,0>UW 0x10101010V { align1 };
|
||||
add(16) g6<1>F g10<8,8,1>UW -g1<0,1,0>F { align1 compr };
|
||||
add(16) g4<1>F g18<8,8,1>F g6<8,8,1>F { align1 compr };
|
||||
add(1) m14.4<1>D g8.4<0,1,0>D 16D { align1 nomask };
|
||||
add(8) g5<1>.xD g2<4>.xD 64D { align16 };
|
||||
add(8) g4<1>.xD g5<4>.xD g4<4>.xD { align16 };
|
||||
add(8) g3<1>F g3<4>F g5<4>F { align16 };
|
||||
add(16) g24<1>F g20<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
add(16) g14<1>D g14<8,8,1>D 1D { align1 compr };
|
||||
add(8) m5<1>.xyzF g10<4>.xyzzF g8<4>.xyzzF { align16 NoDDClr };
|
||||
add.le.f0.0(16) g6<1>F g8<8,8,1>F g4<8,8,1>F { align1 compr };
|
||||
add(8) a0<1>UW g4<16,8,2>UW 0x0040UW { align1 };
|
||||
add(8) a0<1>UW g5<16,8,2>UW 0x0040UW { align1 sechalf };
|
||||
add(8) g3<1>.xyF g2<4>.xyyyF 0x3f800000F /* 1F */ { align16 };
|
||||
add(16) m2<1>D g6<8,8,1>D g8.3<0,1,0>D { align1 compr };
|
||||
add(16) m14<1>D g4<8,8,1>D 12D { align1 compr };
|
||||
add.sat(16) g6<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 compr };
|
||||
add(8) g37<1>UW g1.4<2,4,0>UW 0x10101010V { align1 };
|
||||
add(8) g37<1>F g37<8,8,1>UW -g1<0,1,0>F { align1 };
|
||||
add(8) g37<1>D g2<0,1,0>D 1D { align1 };
|
||||
add(8) m5<1>.xF g3<4>.xF 0x3f000000F /* 0.5F */ { align16 };
|
||||
add(16) g4<1>D g2<0,1,0>D -g2.2<0,1,0>D { align1 compr };
|
||||
add.sat(8) m5<1>F g7<4>F g8<4>F { align16 };
|
||||
add(8) g31<1>.xyzF g28<4>.xyzzF 0x30300000VF /* [0F, 0F, 1F, 1F]VF */ { align16 };
|
||||
add.sat(8) m5<1>.xyzF g25<4>.xyzzF g26<4>.xyzzF { align16 NoDDClr };
|
||||
add.ge.f0.0(8) g8<1>.xF -g8<4>.xF 0x3f800000F /* 1F */ { align16 };
|
||||
add(16) g4.1<2>UW g4.1<16,8,2>UW g6<16,8,2>UW { align1 compr };
|
||||
add.ge.f0.0(16) g4<1>F -g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
add(8) g4<1>.xyF g4<4>.xyyyF 0xbf800000F /* -1F */ { align16 NoDDClr };
|
||||
add(8) m5<1>.xyzF g4<4>.xyzzF g2<0>.xyzzF { align16 };
|
||||
add(16) m2<1>F -g16<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
add(8) m5<1>.zwF g8<4>.xxxyF g9<4>.xxxyF { align16 NoDDChk };
|
||||
add(8) g4<1>.xUD g4<4>.xUD 0x00000040UD { align16 };
|
||||
add.sat(8) m5<1>.yF g1<0>.zF 0x3f000000F /* 0.5F */ { align16 };
|
||||
add(16) m2<1>F g22<8,8,1>F g2<0,1,0>F { align1 compr };
|
||||
add(16) m14<1>UD g4<8,8,1>UD 0x00000110UD { align1 compr };
|
||||
add(8) g5<1>F -g9<4>.xyxyF g9<4>.zwzwF { align16 sechalf };
|
||||
add.sat(8) m5<1>.yF g6<4>.xF g7<4>.xF { align16 NoDDClr,NoDDChk };
|
||||
add.sat(8) m5<1>.wF g6<4>.xF g7<4>.xF { align16 NoDDChk };
|
||||
add.ge.f0.0(16) g16<1>F g18<8,8,1>F g10<8,8,1>F { align1 compr };
|
||||
add.sat(8) m5<1>.yF -g1<0>.xF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
|
||||
add.sat(8) m5<1>.zF g3<4>.yF 0x40000000F /* 2F */ { align16 NoDDClr,NoDDChk };
|
||||
add.sat(8) m5<1>.wF g3<4>.yF 0xc0000000F /* -2F */ { align16 NoDDChk };
|
||||
add(8) m5<1>F g3<4>F 0x2020a038VF /* [1.5F, -0.5F, 0.5F, 0.5F]VF */ { align16 };
|
||||
add(8) g5<1>.zF g4<4>.xF 0xbf800000F /* -1F */ { align16 NoDDClr,NoDDChk };
|
||||
add(8) m5<1>.xyF g12<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
|
||||
add(8) m5<1>.wF -g3<4>.xF 0x3f800000F /* 1F */ { align16 NoDDClr,NoDDChk };
|
||||
add(8) g5<1>.xyF g3<0>.xyyyF g4<4>.xyyyF { align16 NoDDClr };
|
||||
48
src/intel/tools/tests/gen4/add.expected
Normal file
48
src/intel/tools/tests/gen4/add.expected
Normal file
@ -0,0 +1,48 @@
|
||||
40 00 80 00 29 6d 40 21 28 00 48 00 10 10 10 10
|
||||
40 20 80 00 3d 75 c0 20 40 01 8d 00 20 40 00 00
|
||||
40 20 80 00 bd 77 80 20 40 02 8d 00 c0 00 8d 00
|
||||
40 02 00 00 a6 1c d0 21 10 01 00 00 10 00 00 00
|
||||
40 01 60 00 a5 1c a1 20 40 00 60 00 40 00 00 00
|
||||
40 01 60 00 a5 14 81 20 a0 00 60 00 80 00 60 00
|
||||
40 01 60 00 bd 77 6f 20 64 00 6e 00 a4 00 6e 00
|
||||
40 20 80 00 bd 7f 00 23 80 02 8d 00 00 00 80 3f
|
||||
40 20 80 00 a5 1c c0 21 c0 01 8d 00 01 00 00 00
|
||||
40 05 60 00 be 77 a7 20 44 01 6a 00 04 01 6a 00
|
||||
40 20 80 06 bd 77 c0 20 00 01 8d 00 80 00 8d 00
|
||||
40 00 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00
|
||||
40 10 60 00 28 2d 00 22 a0 00 ae 00 40 00 40 00
|
||||
40 01 60 00 bd 7f 63 20 44 00 65 00 00 00 80 3f
|
||||
40 20 80 00 a6 14 40 20 c0 00 8d 00 0c 01 00 00
|
||||
40 20 80 00 a6 1c c0 21 80 00 8d 00 0c 00 00 00
|
||||
40 20 80 80 bd 77 c0 20 80 00 8d 00 44 00 00 00
|
||||
40 00 60 00 29 6d a0 24 28 00 48 00 10 10 10 10
|
||||
40 00 60 00 3d 75 a0 24 a0 04 8d 00 20 40 00 00
|
||||
40 00 60 00 a5 1c a0 24 40 00 00 00 01 00 00 00
|
||||
40 01 60 00 be 7f a1 20 60 00 60 00 00 00 00 3f
|
||||
40 20 80 00 a5 14 80 20 40 00 00 00 48 40 00 00
|
||||
40 01 60 80 be 77 af 20 e4 00 6e 00 04 01 6e 00
|
||||
40 01 60 00 bd 5f e7 23 84 03 6a 00 00 00 30 30
|
||||
40 05 60 80 be 77 a7 20 24 03 6a 00 44 03 6a 00
|
||||
40 01 60 04 bd 7f 01 21 00 41 60 00 00 00 80 3f
|
||||
40 20 80 00 29 25 82 40 82 00 ae 00 c0 00 ae 00
|
||||
40 20 80 04 bd 7f 80 20 c0 40 8d 00 00 00 80 3f
|
||||
40 05 60 00 bd 7f 83 20 84 00 65 00 00 00 80 bf
|
||||
40 01 60 00 be 77 a7 20 84 00 6a 00 44 00 0a 00
|
||||
40 20 80 00 be 7f 40 20 00 42 8d 00 00 00 80 3f
|
||||
40 09 60 00 be 77 ac 20 00 01 64 00 20 01 64 00
|
||||
40 01 60 00 21 0c 81 20 80 00 60 00 40 00 00 00
|
||||
40 01 60 80 be 7f a2 20 2a 00 0a 00 00 00 00 3f
|
||||
40 20 80 00 be 77 40 20 c0 02 8d 00 40 00 00 00
|
||||
40 20 80 00 22 0c c0 21 80 00 8d 00 10 01 00 00
|
||||
40 11 60 00 bd 77 af 20 24 41 64 00 2e 01 6e 00
|
||||
40 0d 60 80 be 77 a2 20 c0 00 60 00 e0 00 60 00
|
||||
40 09 60 80 be 77 a8 20 c0 00 60 00 e0 00 60 00
|
||||
40 20 80 04 bd 77 00 22 40 02 8d 00 40 01 8d 00
|
||||
40 05 60 80 be 7f a2 20 20 40 00 00 00 00 00 3f
|
||||
40 0d 60 80 be 7f a4 20 65 00 65 00 00 00 00 40
|
||||
40 09 60 80 be 7f a8 20 65 00 65 00 00 00 00 c0
|
||||
40 01 60 00 be 5f af 20 64 00 6e 00 38 a0 20 20
|
||||
40 0d 60 00 bd 7f a4 20 80 00 60 00 00 00 80 bf
|
||||
40 05 60 00 be 7f a3 20 84 01 65 00 00 00 00 3f
|
||||
40 0d 60 00 be 7f a8 20 60 40 60 00 00 00 80 3f
|
||||
40 05 60 00 bd 77 a3 20 64 00 05 00 84 00 65 00
|
||||
17
src/intel/tools/tests/gen4/and.asm
Normal file
17
src/intel/tools/tests/gen4/and.asm
Normal file
@ -0,0 +1,17 @@
|
||||
and(8) g9<1>.wUD g9<4>.wUD 524032D { align16 };
|
||||
and(16) g4<1>D g6<8,8,1>D 1D { align1 compr };
|
||||
and(8) g10<1>.xD g10<4>.xD 1D { align16 };
|
||||
and(16) g6<1>UD g10<8,8,1>UD g8<8,8,1>UD { align1 compr };
|
||||
and.nz.f0.0(16) null<1>D g6<8,8,1>UD 1D { align1 compr };
|
||||
and(16) g4<1>D g8<8,8,1>UD 1D { align1 compr };
|
||||
and(8) g2<1>D g2<8,8,1>UD 1D { align1 };
|
||||
and.nz.f0.0(8) null<1>.xD g9<4>.xUD 1D { align16 };
|
||||
and(16) g12<1>UD g2.4<0,1,0>UD 0x80000000UD { align1 compr };
|
||||
and.nz.f0.0(16) g110<1>D g6<8,8,1>D 1D { align1 compr };
|
||||
and(8) g17<1>.xUD g1<0>.xUD 0x80000000UD { align16 };
|
||||
and.nz.f0.0(16) g6<1>D g4<8,8,1>UD 1D { align1 compr };
|
||||
and(1) g12<1>UD f0<0,1,0>UW 0x0000000fUD { align1 nomask };
|
||||
and(8) g5<1>.xUD g1<0>.xUD g1<0>.yUD { align16 };
|
||||
and(8) g8<1>.xD g7<4>.xUD 1D { align16 };
|
||||
and.nz.f0.0(8) g6<1>.xD g6<4>.xD 1D { align16 };
|
||||
and.nz.f0.0(1) null<1>UD g1.6<0,1,0>UD 0x04000000UD { align1 };
|
||||
17
src/intel/tools/tests/gen4/and.expected
Normal file
17
src/intel/tools/tests/gen4/and.expected
Normal file
@ -0,0 +1,17 @@
|
||||
05 01 60 00 21 1c 28 21 2f 01 6f 00 00 ff 07 00
|
||||
05 20 80 00 a5 1c 80 20 c0 00 8d 00 01 00 00 00
|
||||
05 01 60 00 a5 1c 41 21 40 01 60 00 01 00 00 00
|
||||
05 20 80 00 21 04 c0 20 40 01 8d 00 00 01 8d 00
|
||||
05 20 80 02 24 1c 00 20 c0 00 8d 00 01 00 00 00
|
||||
05 20 80 00 25 1c 80 20 00 01 8d 00 01 00 00 00
|
||||
05 00 60 00 25 1c 40 20 40 00 8d 00 01 00 00 00
|
||||
05 01 60 02 24 1c 01 20 20 01 60 00 01 00 00 00
|
||||
05 20 80 00 21 0c 80 21 50 00 00 00 00 00 00 80
|
||||
05 20 80 02 a5 1c c0 2d c0 00 8d 00 01 00 00 00
|
||||
05 01 60 00 21 0c 21 22 20 00 00 00 00 00 00 80
|
||||
05 20 80 02 25 1c c0 20 80 00 8d 00 01 00 00 00
|
||||
05 02 00 00 01 0d 80 21 00 06 00 00 0f 00 00 00
|
||||
05 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00
|
||||
05 01 60 00 25 1c 01 21 e0 00 60 00 01 00 00 00
|
||||
05 01 60 02 a5 1c c1 20 c0 00 60 00 01 00 00 00
|
||||
05 00 00 02 20 0c 00 20 38 00 00 00 00 00 00 04
|
||||
5
src/intel/tools/tests/gen4/asr.asm
Normal file
5
src/intel/tools/tests/gen4/asr.asm
Normal file
@ -0,0 +1,5 @@
|
||||
asr(16) g4<1>D -g1.6<0,1,0>D 31D { align1 compr };
|
||||
asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr };
|
||||
asr(8) g4<1>D g5<4>D g4<4>UD { align16 };
|
||||
asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 };
|
||||
asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr };
|
||||
5
src/intel/tools/tests/gen4/asr.expected
Normal file
5
src/intel/tools/tests/gen4/asr.expected
Normal file
@ -0,0 +1,5 @@
|
||||
0c 20 80 00 a5 1c 80 20 38 40 00 00 1f 00 00 00
|
||||
0c 20 80 02 a4 1c 00 20 38 40 00 00 1f 00 00 00
|
||||
0c 01 60 00 a5 04 8f 20 a4 00 6e 00 84 00 6e 00
|
||||
0c 01 60 00 a5 0c 61 21 a0 00 60 00 02 00 00 00
|
||||
0c 20 80 00 a5 0c 40 21 c0 00 8d 00 02 00 00 00
|
||||
5
src/intel/tools/tests/gen4/break.asm
Normal file
5
src/intel/tools/tests/gen4/break.asm
Normal file
@ -0,0 +1,5 @@
|
||||
(-f0.0) break(16) Jump: 10 Pop: 0 { align1 };
|
||||
break(16) Jump: 5 Pop: 1 { align1 };
|
||||
(+f0.0) break(16) Jump: 156 Pop: 0 { align1 };
|
||||
(+f0.0.x) break(8) Jump: 16 Pop: 0 { align16 };
|
||||
break(8) Jump: 6 Pop: 2 { align16 };
|
||||
5
src/intel/tools/tests/gen4/break.expected
Normal file
5
src/intel/tools/tests/gen4/break.expected
Normal file
@ -0,0 +1,5 @@
|
||||
28 00 91 00 00 1c 00 34 00 14 60 00 0a 00 00 00
|
||||
28 00 80 00 00 1c 00 34 00 14 60 00 05 00 01 00
|
||||
28 00 81 00 00 1c 00 34 00 14 60 00 9c 00 00 00
|
||||
28 01 62 00 00 1c 0f 34 04 14 6e 00 10 00 00 00
|
||||
28 01 60 00 00 1c 0f 34 04 14 6e 00 06 00 02 00
|
||||
80
src/intel/tools/tests/gen4/cmp.asm
Normal file
80
src/intel/tools/tests/gen4/cmp.asm
Normal file
@ -0,0 +1,80 @@
|
||||
cmp.l.f0.0(8) null<1>F g8<4>.wF 0x0F /* 0F */ { align16 };
|
||||
cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16 };
|
||||
cmp.nz.f0.0(8) null<1>D g7<4>.xyzzD 0D { align16 };
|
||||
cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
|
||||
cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
|
||||
cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
|
||||
cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
|
||||
cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
|
||||
cmp.l.f0.0(8) g7<1>.xF g7<4>.xF 0x3189705fF /* 4e-09F */ { align16 };
|
||||
cmp.ge.f0.0(8) g6<1>.xF g2<0>.xF g6<4>.xF { align16 };
|
||||
cmp.z.f0.0(8) null<1>F g3<0>.zwwwF g3<0>.xyyyF { align16 };
|
||||
cmp.ge.f0.0(16) null<1>D g14<8,8,1>D 16D { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>D g2<0,1,0>D 1D { align1 compr };
|
||||
cmp.z.f0.0(16) g8<1>F g32<8,8,1>F g2.3<0,1,0>F { align1 compr };
|
||||
cmp.ge.f0.0(16) null<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.nz.f0.0(8) null<1>F g12<4>.xyyyF g1<0>.xyyyF { align16 };
|
||||
cmp.z.f0.0(8) null<1>D g6<4>D g2.4<0>D { align16 };
|
||||
cmp.z.f0.0(16) g6<1>D g2.1<0,1,0>D 39D { align1 compr };
|
||||
cmp.ge.f0.0(8) null<1>F g5<4>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.le.f0.0(8) g5<1>.xF g5<4>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.z.f0.0(16) g4<1>F g2.1<0,1,0>F 0x41000000F /* 8F */ { align1 compr };
|
||||
cmp.z.f0.0(8) g5<1>.xD g5<4>.xD g1<0>.zD { align16 };
|
||||
cmp.l.f0.0(8) g3<1>.xyF g1<0>.xyyyF g1<0>.zwwwF { align16 };
|
||||
cmp.z.f0.0(16) null<1>D g2<0,1,0>D 1D { align1 compr };
|
||||
cmp.z.f0.0(16) null<1>F g14<8,8,1>F g2.1<0,1,0>F { align1 compr };
|
||||
cmp.z.f0.0(8) g6<1>.xF g6<4>.xF g3<0>.yF { align16 };
|
||||
cmp.nz.f0.0(16) g4<1>F g6<8,8,1>F g2.2<0,1,0>F { align1 compr };
|
||||
cmp.ge.f0.0(16) null<1>F (abs)g14<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
|
||||
cmp.nz.f0.0(8) g5<1>F g5<8,8,1>F g37<8,8,1>F { align1 };
|
||||
cmp.ge.f0.0(8) null<1>.xD g5<4>.xD 4D { align16 };
|
||||
cmp.nz.f0.0(16) null<1>F g2.4<0,1,0>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.z.f0.0(16) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
cmp.ge.f0.0(16) g4<1>D g2<0,1,0>D 1D { align1 compr };
|
||||
cmp.nz.f0.0(16) g4<1>D g2.1<0,1,0>D 0D { align1 compr };
|
||||
cmp.z.f0.0(16) g8<1>D g6<8,8,1>D g2.5<0,1,0>D { align1 compr };
|
||||
cmp.nz.f0.0(16) null<1>D g2<0,1,0>D 0D { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>F g4<8,8,1>F g2.5<0,1,0>F { align1 compr };
|
||||
cmp.l.f0.0(16) g6<1>D g3<0,1,0>D 1D { align1 compr };
|
||||
cmp.ge.f0.0(16) g4<1>D g2.3<0,1,0>D g2<0,1,0>D { align1 compr };
|
||||
cmp.nz.f0.0(8) g3<1>.xD g1<0>.xD g1<0>.yD { align16 };
|
||||
cmp.nz.f0.0(8) g3<1>.xyzF g1<0>.xyzzF g1.4<0>.xyzzF { align16 };
|
||||
cmp.nz.f0.0(8) null<1>F g1<0>.xF 0x0F /* 0F */ { align16 };
|
||||
cmp.le.f0.0(8) g5<1>.xD g1<0>.xD 0D { align16 };
|
||||
cmp.l.f0.0(16) g4<1>D g2.1<0,1,0>D g2<0,1,0>D { align1 compr };
|
||||
cmp.ge.f0.0(8) g3<1>D g1<0>D g1.4<0>D { align16 };
|
||||
cmp.le.f0.0(16) null<1>F g4<8,8,1>F 0x3f000000F /* 0.5F */ { align1 compr };
|
||||
cmp.le.f0.0(16) g20<1>F g4<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 compr };
|
||||
cmp.z.f0.0(8) null<1>F g3<0>.xyzzF 0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 };
|
||||
cmp.nz.f0.0(8) null<1>D g1<0>.xyzzD g1.4<0>.xyzzD { align16 };
|
||||
cmp.ge.f0.0(8) null<1>.xD g5<4>.xD g3<0>.xD { align16 };
|
||||
cmp.g.f0.0(8) g4<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 };
|
||||
cmp.nz.f0.0(16) g8<1>F g2.2<0,1,0>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.l.f0.0(8) null<1>F g1<0>F g3<4>F { align16 };
|
||||
cmp.g.f0.0(8) null<1>.xF g2<4>.yF 0x0F /* 0F */ { align16 };
|
||||
cmp.nz.f0.0(16) null<1>D g16<8,8,1>D g12<8,8,1>D { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.z.f0.0(8) null<1>.xD g1<0>.xD 1D { align16 };
|
||||
cmp.nz.f0.0(16) g6<1>D g4<8,8,1>D g2.2<0,1,0>D { align1 compr };
|
||||
cmp.g.f0.0(16) g16<1>F (abs)g8<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
|
||||
cmp.l.f0.0(8) g5<1>.xD g1<0>.yD g1<0>.xD { align16 };
|
||||
cmp.ge.f0.0(8) g6<1>.xF g3<4>.xF 0x41f00000F /* 30F */ { align16 };
|
||||
cmp.g.f0.0(16) null<1>D g2.1<0,1,0>D 0D { align1 compr };
|
||||
cmp.ge.f0.0(16) null<1>D g4<8,8,1>D g2.1<0,1,0>D { align1 compr };
|
||||
cmp.le.f0.0(8) null<1>.xF g8<4>.xF 0x3f000000F /* 0.5F */ { align16 };
|
||||
cmp.ge.f0.0(8) null<1>.xF g22<4>.xF g10<4>.xF { align16 };
|
||||
cmp.z.f0.0(8) g9<1>.xF g1<0>.xF 0x40b79581F /* 5.737F */ { align16 };
|
||||
cmp.z.f0.0(16) null<1>D g6<8,8,1>D g2<0,1,0>D { align1 compr };
|
||||
cmp.nz.f0.0(16) null<1>F g4<8,8,1>F g8<8,8,1>F { align1 compr };
|
||||
(+f0.1) cmp.z.f0.1(16) null<1>D g6<8,8,1>D 0D { align1 compr };
|
||||
cmp.nz.f0.0(8) g11<1>.xD g4<4>.xD 10D { align16 };
|
||||
cmp.nz.f0.0(8) g3<1>F g3<4>F 0x0F /* 0F */ { align16 };
|
||||
cmp.le.f0.0(16) g4<1>D g2<0,1,0>D 0D { align1 compr };
|
||||
cmp.l.f0.0(8) null<1>.xD g6<4>.xD g5<4>.xD { align16 };
|
||||
cmp.ge.f0.0(8) g10<1>.xD g5<4>.xD 2D { align16 };
|
||||
cmp.g.f0.0(8) null<1>.xD g3<0>.zD 4D { align16 };
|
||||
cmp.g.f0.0(16) null<1>F g20<8,8,1>F 0x0F /* 0F */ { align1 compr };
|
||||
cmp.l.f0.0(16) null<1>D g2<0,1,0>D g6<8,8,1>D { align1 compr };
|
||||
(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 };
|
||||
cmp.le.f0.0(8) g3<1>.xUD g1<0>.xUD 0x00000001UD { align16 };
|
||||
cmp.g.f0.0(8) g8<1>.xD g1<0>.xD 2D { align16 };
|
||||
80
src/intel/tools/tests/gen4/cmp.expected
Normal file
80
src/intel/tools/tests/gen4/cmp.expected
Normal file
@ -0,0 +1,80 @@
|
||||
10 01 60 05 bc 7f 0f 20 0f 01 6f 00 00 00 00 00
|
||||
10 01 60 02 bc 5f 0f 20 64 00 0a 00 64 6e 74 74
|
||||
10 01 60 02 a4 1c 0f 20 e4 00 6a 00 00 00 00 00
|
||||
10 20 80 04 bd 7f c0 20 80 00 8d 00 5f 70 89 31
|
||||
10 20 80 05 bd 7f 00 21 80 00 8d 00 5f 70 89 31
|
||||
10 20 80 05 bd 77 00 21 80 00 8d 00 c0 00 8d 00
|
||||
10 20 80 04 bd 77 40 21 80 00 8d 00 c0 00 8d 00
|
||||
10 01 60 01 a5 1c 41 21 80 00 00 00 00 00 00 00
|
||||
10 01 60 05 bd 7f e1 20 e0 00 60 00 5f 70 89 31
|
||||
10 01 60 04 bd 77 c1 20 40 00 00 00 c0 00 60 00
|
||||
10 01 60 01 bc 77 0f 20 6e 00 0f 00 64 00 05 00
|
||||
10 20 80 04 a4 1c 00 20 c0 01 8d 00 10 00 00 00
|
||||
10 20 80 05 a4 1c 00 20 40 00 00 00 01 00 00 00
|
||||
10 20 80 01 bd 77 00 21 00 04 8d 00 4c 00 00 00
|
||||
10 20 80 04 bc 7f 00 20 c0 00 8d 00 00 00 00 00
|
||||
10 01 60 02 bc 77 0f 20 84 01 65 00 24 00 05 00
|
||||
10 01 60 01 a4 14 0f 20 c4 00 6e 00 54 00 0e 00
|
||||
10 20 80 01 a5 1c c0 20 44 00 00 00 27 00 00 00
|
||||
10 01 60 04 bc 7f 0f 20 a0 00 60 00 00 00 00 00
|
||||
10 01 60 06 bd 7f a1 20 a0 00 60 00 00 00 00 00
|
||||
10 20 80 01 bd 7f 80 20 44 00 00 00 00 00 00 41
|
||||
10 01 60 01 a5 14 a1 20 a0 00 60 00 2a 00 0a 00
|
||||
10 01 60 05 bd 77 63 20 24 00 05 00 2e 00 0f 00
|
||||
10 20 80 01 a4 1c 00 20 40 00 00 00 01 00 00 00
|
||||
10 20 80 01 bc 77 00 20 c0 01 8d 00 44 00 00 00
|
||||
10 01 60 01 bd 77 c1 20 c0 00 60 00 65 00 05 00
|
||||
10 20 80 02 bd 77 80 20 c0 00 8d 00 48 00 00 00
|
||||
10 20 80 04 bc 77 00 20 c0 21 8d 00 00 21 8d 00
|
||||
10 00 60 02 bd 77 a0 20 a0 00 8d 00 a0 04 8d 00
|
||||
10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00
|
||||
10 20 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00
|
||||
10 20 80 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
|
||||
10 20 80 04 a5 1c 80 20 40 00 00 00 01 00 00 00
|
||||
10 20 80 02 a5 1c 80 20 44 00 00 00 00 00 00 00
|
||||
10 20 80 01 a5 14 00 21 c0 00 8d 00 54 00 00 00
|
||||
10 20 80 02 a4 1c 00 20 40 00 00 00 00 00 00 00
|
||||
10 20 80 05 bc 77 00 20 80 00 8d 00 54 00 00 00
|
||||
10 20 80 05 a5 1c c0 20 60 00 00 00 01 00 00 00
|
||||
10 20 80 04 a5 14 80 20 4c 00 00 00 40 00 00 00
|
||||
10 01 60 02 a5 14 61 20 20 00 00 00 25 00 05 00
|
||||
10 01 60 02 bd 77 67 20 24 00 0a 00 34 00 0a 00
|
||||
10 01 60 02 bc 7f 0f 20 20 00 00 00 00 00 00 00
|
||||
10 01 60 06 a5 1c a1 20 20 00 00 00 00 00 00 00
|
||||
10 20 80 05 a5 14 80 20 44 00 00 00 40 00 00 00
|
||||
10 01 60 04 a5 14 6f 20 24 00 0e 00 34 00 0e 00
|
||||
10 20 80 06 bc 7f 00 20 80 00 8d 00 00 00 00 3f
|
||||
10 20 80 06 bd 7f 80 22 80 00 8d 00 9a 3f 1c 46
|
||||
10 01 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e
|
||||
10 01 60 02 a4 14 0f 20 24 00 0a 00 34 00 0a 00
|
||||
10 01 60 04 a4 14 01 20 a0 00 60 00 60 00 00 00
|
||||
10 01 60 03 bd 7f 8f 20 64 00 6e 00 00 00 00 3f
|
||||
10 20 80 02 bd 7f 00 21 48 00 00 00 00 00 00 00
|
||||
10 01 60 05 bc 77 0f 20 24 00 0e 00 64 00 6e 00
|
||||
10 01 60 03 bc 7f 01 20 45 00 65 00 00 00 00 00
|
||||
10 20 80 02 a4 14 00 20 00 02 8d 00 80 01 8d 00
|
||||
10 20 80 05 bc 7f 00 20 40 00 00 00 00 00 00 00
|
||||
10 01 60 01 a4 1c 01 20 20 00 00 00 01 00 00 00
|
||||
10 20 80 02 a5 14 c0 20 80 00 8d 00 48 00 00 00
|
||||
10 20 80 03 bd 7f 00 22 00 21 8d 00 00 00 80 3f
|
||||
10 01 60 05 a5 14 a1 20 25 00 05 00 20 00 00 00
|
||||
10 01 60 04 bd 7f c1 20 60 00 60 00 00 00 f0 41
|
||||
10 20 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00
|
||||
10 20 80 04 a4 14 00 20 80 00 8d 00 44 00 00 00
|
||||
10 01 60 06 bc 7f 01 20 00 01 60 00 00 00 00 3f
|
||||
10 01 60 04 bc 77 01 20 c0 02 60 00 40 01 60 00
|
||||
10 01 60 01 bd 7f 21 21 20 00 00 00 81 95 b7 40
|
||||
10 20 80 01 a4 14 00 20 c0 00 8d 00 40 00 00 00
|
||||
10 20 80 02 bc 77 00 20 80 00 8d 00 00 01 8d 00
|
||||
10 20 81 01 a4 1c 00 20 c0 00 8d 02 00 00 00 00
|
||||
10 01 60 02 a5 1c 61 21 80 00 60 00 0a 00 00 00
|
||||
10 01 60 02 bd 7f 6f 20 64 00 6e 00 00 00 00 00
|
||||
10 20 80 06 a5 1c 80 20 40 00 00 00 00 00 00 00
|
||||
10 01 60 05 a4 14 01 20 c0 00 60 00 a0 00 60 00
|
||||
10 01 60 04 a5 1c 41 21 a0 00 60 00 02 00 00 00
|
||||
10 01 60 03 a4 1c 01 20 6a 00 0a 00 04 00 00 00
|
||||
10 20 80 03 bc 7f 00 20 80 02 8d 00 00 00 00 00
|
||||
10 20 80 05 a4 14 00 20 40 00 00 00 c0 00 8d 00
|
||||
10 00 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00
|
||||
10 01 60 06 21 0c 61 20 20 00 00 00 01 00 00 00
|
||||
10 01 60 03 a5 1c 01 21 20 00 00 00 02 00 00 00
|
||||
2
src/intel/tools/tests/gen4/cont.asm
Normal file
2
src/intel/tools/tests/gen4/cont.asm
Normal file
@ -0,0 +1,2 @@
|
||||
cont(16) Jump: 4 Pop: 1 { align1 };
|
||||
cont(8) Jump: 4 Pop: 1 { align16 };
|
||||
2
src/intel/tools/tests/gen4/cont.expected
Normal file
2
src/intel/tools/tests/gen4/cont.expected
Normal file
@ -0,0 +1,2 @@
|
||||
29 00 80 00 00 1c 00 34 00 14 60 00 04 00 01 00
|
||||
29 01 60 00 00 1c 0f 34 04 14 6e 00 04 00 01 00
|
||||
2
src/intel/tools/tests/gen4/do.asm
Normal file
2
src/intel/tools/tests/gen4/do.asm
Normal file
@ -0,0 +1,2 @@
|
||||
do(16) { align1 };
|
||||
do(8) { align16 };
|
||||
2
src/intel/tools/tests/gen4/do.expected
Normal file
2
src/intel/tools/tests/gen4/do.expected
Normal file
@ -0,0 +1,2 @@
|
||||
26 00 80 00 9c 73 00 20 00 00 8d 00 00 00 8d 00
|
||||
26 01 60 00 9c 73 0f 20 04 00 6e 00 04 00 6e 00
|
||||
7
src/intel/tools/tests/gen4/dp2.asm
Normal file
7
src/intel/tools/tests/gen4/dp2.asm
Normal file
@ -0,0 +1,7 @@
|
||||
dp2(8) g7<1>.xF g7<4>.xyyyF g7<4>.xyyyF { align16 };
|
||||
dp2(8) m5<1>.xF g1<0>.yF g1<0>.yF { align16 };
|
||||
dp2(8) m5<1>.yzF g1<0>.xF g1<0>.zwwwF { align16 NoDDClr };
|
||||
dp2(8) m5<1>.wF g1<0>.ywwwF g1<0>.wyyyF { align16 NoDDChk };
|
||||
dp2(8) g4<1>.yF g1<0>.xyyyF g1.4<0>.xyyyF { align16 NoDDClr };
|
||||
dp2(8) g4<1>.zF g1<0>.xyyyF g1.4<0>.zwwwF { align16 NoDDClr,NoDDChk };
|
||||
dp2(8) g4<1>.wF g1<0>.xyyyF g2<0>.xyyyF { align16 NoDDChk };
|
||||
7
src/intel/tools/tests/gen4/dp2.expected
Normal file
7
src/intel/tools/tests/gen4/dp2.expected
Normal file
@ -0,0 +1,7 @@
|
||||
57 01 60 00 bd 77 e1 20 e4 00 65 00 e4 00 65 00
|
||||
57 01 60 00 be 77 a1 20 25 00 05 00 25 00 05 00
|
||||
57 05 60 00 be 77 a6 20 20 00 00 00 2e 00 0f 00
|
||||
57 09 60 00 be 77 a8 20 2d 00 0f 00 27 00 05 00
|
||||
57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00
|
||||
57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00
|
||||
57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00
|
||||
10
src/intel/tools/tests/gen4/dp3.asm
Normal file
10
src/intel/tools/tests/gen4/dp3.asm
Normal file
@ -0,0 +1,10 @@
|
||||
dp3(8) g5<1>.xF g5<4>.xyzzF g5<4>.xyzzF { align16 };
|
||||
dp3(8) m5<1>.xF g3<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr };
|
||||
dp3(8) m5<1>.yF g3.4<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr,NoDDChk };
|
||||
dp3(8) g19<1>.xF g3<0>.xyzzF g3.4<0>.xyzzF { align16 NoDDClr };
|
||||
dp3(8) g19<1>.yF g3<0>.xyzzF g4<0>.xyzzF { align16 NoDDClr,NoDDChk };
|
||||
dp3(8) g19<1>.zF g3<0>.xyzzF g4.4<0>.xyzzF { align16 NoDDChk };
|
||||
dp3(8) m5<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
|
||||
dp3.le.f0.0(8) g18<1>.xF g17<4>.xyzzF g3.4<0>.xyzzF { align16 };
|
||||
dp3.sat(8) g4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
|
||||
dp3.sat(8) m5<1>F g3<4>.xyzzF g3<4>.xyzzF { align16 };
|
||||
10
src/intel/tools/tests/gen4/dp3.expected
Normal file
10
src/intel/tools/tests/gen4/dp3.expected
Normal file
@ -0,0 +1,10 @@
|
||||
56 01 60 00 bd 77 a1 20 a4 00 6a 00 a4 00 6a 00
|
||||
56 05 60 00 be 77 a1 20 64 00 0a 00 c4 00 6a 00
|
||||
56 0d 60 00 be 77 a2 20 74 00 0a 00 c4 00 6a 00
|
||||
56 05 60 00 bd 77 61 22 64 00 0a 00 74 00 0a 00
|
||||
56 0d 60 00 bd 77 62 22 64 00 0a 00 84 00 0a 00
|
||||
56 09 60 00 bd 77 64 22 64 00 0a 00 94 00 0a 00
|
||||
56 01 60 00 be 77 a1 20 84 00 6a 00 a4 00 6a 00
|
||||
56 01 60 06 bd 77 41 22 24 02 6a 00 74 00 0a 00
|
||||
56 01 60 80 bd 77 81 20 84 00 6a 00 a4 00 6a 00
|
||||
56 01 60 80 be 77 af 20 64 00 6a 00 64 00 6a 00
|
||||
6
src/intel/tools/tests/gen4/dp4.asm
Normal file
6
src/intel/tools/tests/gen4/dp4.asm
Normal file
@ -0,0 +1,6 @@
|
||||
dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 };
|
||||
dp4(8) g4<1>.xF g5<4>F g1<0>F { align16 NoDDClr };
|
||||
dp4(8) g4<1>.yF g5<4>F g1.4<0>F { align16 NoDDClr,NoDDChk };
|
||||
dp4(8) g4<1>.wF g5<4>F g2.4<0>F { align16 NoDDChk };
|
||||
dp4(8) m5<1>.xF g4<4>F g5<4>F { align16 };
|
||||
dp4.sat(8) m5<1>F g3<4>.xF g3<4>F { align16 };
|
||||
6
src/intel/tools/tests/gen4/dp4.expected
Normal file
6
src/intel/tools/tests/gen4/dp4.expected
Normal file
@ -0,0 +1,6 @@
|
||||
54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00
|
||||
54 05 60 00 bd 77 81 20 a4 00 6e 00 24 00 0e 00
|
||||
54 0d 60 00 bd 77 82 20 a4 00 6e 00 34 00 0e 00
|
||||
54 09 60 00 bd 77 88 20 a4 00 6e 00 54 00 0e 00
|
||||
54 01 60 00 be 77 a1 20 84 00 6e 00 a4 00 6e 00
|
||||
54 01 60 80 be 77 af 20 60 00 60 00 64 00 6e 00
|
||||
5
src/intel/tools/tests/gen4/dph.asm
Normal file
5
src/intel/tools/tests/gen4/dph.asm
Normal file
@ -0,0 +1,5 @@
|
||||
dph(8) m5<1>.xF g4<4>.xyzxF g5<4>F { align16 };
|
||||
dph.sat(8) m5<1>F g1<0>.xyzxF g3<4>F { align16 };
|
||||
dph(8) g5<1>.xF g4<4>.xyzxF g1<0>F { align16 NoDDClr };
|
||||
dph(8) g5<1>.yF g4<4>.xyzxF g1.4<0>F { align16 NoDDClr,NoDDChk };
|
||||
dph(8) g6<1>.wF g5<4>.xyzxF g2.4<0>F { align16 NoDDChk };
|
||||
5
src/intel/tools/tests/gen4/dph.expected
Normal file
5
src/intel/tools/tests/gen4/dph.expected
Normal file
@ -0,0 +1,5 @@
|
||||
55 01 60 00 be 77 a1 20 84 00 62 00 a4 00 6e 00
|
||||
55 01 60 80 be 77 af 20 24 00 02 00 64 00 6e 00
|
||||
55 05 60 00 bd 77 a1 20 84 00 62 00 24 00 0e 00
|
||||
55 0d 60 00 bd 77 a2 20 84 00 62 00 34 00 0e 00
|
||||
55 09 60 00 bd 77 c8 20 a4 00 62 00 54 00 0e 00
|
||||
2
src/intel/tools/tests/gen4/else.asm
Normal file
2
src/intel/tools/tests/gen4/else.asm
Normal file
@ -0,0 +1,2 @@
|
||||
else(16) Jump: 7 Pop: 1 { align1 switch };
|
||||
else(8) Jump: 3 Pop: 1 { align16 switch };
|
||||
2
src/intel/tools/tests/gen4/else.expected
Normal file
2
src/intel/tools/tests/gen4/else.expected
Normal file
@ -0,0 +1,2 @@
|
||||
24 80 80 00 00 1c 00 34 00 14 60 00 07 00 01 00
|
||||
24 81 60 00 00 1c 0f 34 04 14 6e 00 03 00 01 00
|
||||
2
src/intel/tools/tests/gen4/endif.asm
Normal file
2
src/intel/tools/tests/gen4/endif.asm
Normal file
@ -0,0 +1,2 @@
|
||||
endif(16) Pop: 1 { align1 switch };
|
||||
endif(8) Pop: 1 { align16 switch };
|
||||
2
src/intel/tools/tests/gen4/endif.expected
Normal file
2
src/intel/tools/tests/gen4/endif.expected
Normal file
@ -0,0 +1,2 @@
|
||||
25 80 80 00 84 1c 00 20 00 00 8d 00 00 00 01 00
|
||||
25 81 60 00 84 1c 0f 20 04 00 6e 00 00 00 01 00
|
||||
3
src/intel/tools/tests/gen4/frc.asm
Normal file
3
src/intel/tools/tests/gen4/frc.asm
Normal file
@ -0,0 +1,3 @@
|
||||
frc.sat(8) m5<1>F g3<4>F { align16 };
|
||||
frc(8) g7<1>.xF (abs)g1<0>.xF { align16 };
|
||||
frc(16) g4<1>F g2<0,1,0>F { align1 compr };
|
||||
3
src/intel/tools/tests/gen4/frc.expected
Normal file
3
src/intel/tools/tests/gen4/frc.expected
Normal file
@ -0,0 +1,3 @@
|
||||
43 01 60 80 be 03 af 20 64 00 6e 00 00 00 00 00
|
||||
43 01 60 00 bd 03 e1 20 20 20 00 00 00 00 00 00
|
||||
43 20 80 00 bd 03 80 20 40 00 00 00 00 00 00 00
|
||||
2
src/intel/tools/tests/gen4/if.asm
Normal file
2
src/intel/tools/tests/gen4/if.asm
Normal file
@ -0,0 +1,2 @@
|
||||
(+f0.0) if(16) Jump: 15 { align1 switch };
|
||||
(+f0.0.x) if(8) Jump: 7 { align16 switch };
|
||||
2
src/intel/tools/tests/gen4/if.expected
Normal file
2
src/intel/tools/tests/gen4/if.expected
Normal file
@ -0,0 +1,2 @@
|
||||
22 80 81 00 00 1c 00 34 00 14 60 00 0f 00 00 00
|
||||
22 81 62 00 00 1c 0f 34 04 14 6e 00 07 00 00 00
|
||||
3
src/intel/tools/tests/gen4/iff.asm
Normal file
3
src/intel/tools/tests/gen4/iff.asm
Normal file
@ -0,0 +1,3 @@
|
||||
(-f0.0) iff(16) Jump: 5 { align1 switch };
|
||||
(+f0.0.x) iff(8) Jump: 11 { align16 switch };
|
||||
(+f0.0) iff(16) Jump: 7 { align1 switch };
|
||||
3
src/intel/tools/tests/gen4/iff.expected
Normal file
3
src/intel/tools/tests/gen4/iff.expected
Normal file
@ -0,0 +1,3 @@
|
||||
23 80 91 00 00 1c 00 34 00 14 60 00 05 00 00 00
|
||||
23 81 62 00 00 1c 0f 34 04 14 6e 00 0b 00 00 00
|
||||
23 80 81 00 00 1c 00 34 00 14 60 00 07 00 00 00
|
||||
1
src/intel/tools/tests/gen4/jmpi.asm
Normal file
1
src/intel/tools/tests/gen4/jmpi.asm
Normal file
@ -0,0 +1 @@
|
||||
(+f0.0) jmpi(1) 0x00000002UD { align1 nomask };
|
||||
1
src/intel/tools/tests/gen4/jmpi.expected
Normal file
1
src/intel/tools/tests/gen4/jmpi.expected
Normal file
@ -0,0 +1 @@
|
||||
20 02 01 00 00 0c 00 34 00 14 00 00 02 00 00 00
|
||||
2
src/intel/tools/tests/gen4/line.asm
Normal file
2
src/intel/tools/tests/gen4/line.asm
Normal file
@ -0,0 +1,2 @@
|
||||
line(16) null<1>F g3.4<0,1,0>F g6<8,8,1>F { align1 compr };
|
||||
line(8) null<1>F g4.4<0,1,0>F g37<8,8,1>F { align1 };
|
||||
2
src/intel/tools/tests/gen4/line.expected
Normal file
2
src/intel/tools/tests/gen4/line.expected
Normal file
@ -0,0 +1,2 @@
|
||||
59 20 80 00 bc 77 00 20 70 00 00 00 c0 00 8d 00
|
||||
59 00 60 00 bc 77 00 20 90 00 00 00 a0 04 8d 00
|
||||
3
src/intel/tools/tests/gen4/mac.asm
Normal file
3
src/intel/tools/tests/gen4/mac.asm
Normal file
@ -0,0 +1,3 @@
|
||||
mac(16) g10<1>F g3.5<0,1,0>F g8<8,8,1>F { align1 compr };
|
||||
mac(8) g39<1>F g4.5<0,1,0>F g38<8,8,1>F { align1 };
|
||||
mac(16) m11<1>F g7.1<0,1,0>F g10<8,8,1>F { align1 compr };
|
||||
3
src/intel/tools/tests/gen4/mac.expected
Normal file
3
src/intel/tools/tests/gen4/mac.expected
Normal file
@ -0,0 +1,3 @@
|
||||
48 20 80 00 bd 77 40 21 74 00 00 00 00 01 8d 00
|
||||
48 00 60 00 bd 77 e0 24 94 00 00 00 c0 04 8d 00
|
||||
48 20 80 00 be 77 60 21 e4 00 00 00 40 01 8d 00
|
||||
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Reference in New Issue
Block a user