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iris: Use mi_builder in iris_load_indirect_location()

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For example, this allows us to take advantage of command-streamer
based register offsets in mi_builder.

Ref: 06cf838cbd ("intel/mi_builder: Support gen11 command-streamer based register offsets")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13652>
This commit is contained in:
Jordan Justen 2021-11-02 03:36:04 -07:00
parent 833c0394e0
commit 6ffdcc335e
1 changed files with 8 additions and 12 deletions
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20
src/gallium/drivers/iris/iris_state.c
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@ -6929,18 +6929,14 @@ iris_load_indirect_location(struct iris_context *ice,
struct iris_state_ref *grid_size = &ice->state.grid_size;
struct iris_bo *bo = iris_resource_bo(grid_size->res);
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMX;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 0);
}
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMY;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 4);
}
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = GPGPU_DISPATCHDIMZ;
lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 8);
}
struct mi_builder b;
mi_builder_init(&b, &batch->screen->devinfo, batch);
struct mi_value size_x = mi_mem32(ro_bo(bo, grid_size->offset + 0));
struct mi_value size_y = mi_mem32(ro_bo(bo, grid_size->offset + 4));
struct mi_value size_z = mi_mem32(ro_bo(bo, grid_size->offset + 8));
mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMX), size_x);
mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMY), size_y);
mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
}
#if GFX_VERx10 >= 125