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docs/isl: Improve the bit[6] swizzling section of the tiling chapter
Suggested-by: Luis Strano <luis.strano@intel.com> Acked-by: Luis Strano <luis.strano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
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@ -50,17 +50,24 @@ the tile in elements depends on the size of the element in bytes.
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Bit-6 Swizzling
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^^^^^^^^^^^^^^^
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On some hardware, there is an additional address swizzle that is applied on top
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of the tiling format. Whether or not swizzling is enabled depends on the memory
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configuration of the system. In general, systems with dual-channel RAM have
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swizzling enabled and single-channel do not. Supposedly, this swizzling allows
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for better balancing between the two memory channels and increases performance.
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Because it depends on the memory configuration which may change from one boot
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to the next, it requires a run-time check.
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On some older hardware, there is an additional address swizzle that is applied
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on top of the tiling format. This has been removed starting with Broadwell
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because, as it says in the Broadwell PRM Vol 5 "Tiling Algorithm" (p. 17):
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Address Swizzling for Tiled-Surfaces is no longer used because the main
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memory controller has a more effective address swizzling algorithm.
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Whether or not swizzling is enabled depends on the memory configuration of the
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system. Generally, systems with dual-channel RAM have swizzling enabled and
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single-channel do not. Supposedly, this swizzling allows for better balancing
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between the two memory channels and increases performance. Because it depends
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on the memory configuration which may change from one boot to the next, it
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requires a run-time check.
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The best documentation for bit-6 swizzling can be found in the Haswell PRM Vol.
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5 "Memory Views" in the section entitled "Address Swizzling for Tiled-Y
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Surfaces".
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Surfaces". It exists on older platforms but the docs get progressively worse
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the further you go back.
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ISL Representation
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------------------
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