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radv/ac: Implement Float64 SSBO stores.

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No f16 support as I'm not quite sure about alignment yet.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen 2017-01-05 01:36:26 +01:00
parent 29577b2123
commit 91074bb11b
1 changed files with 14 additions and 3 deletions
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17
src/amd/common/ac_nir_to_llvm.c
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@ -2007,7 +2007,10 @@ static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
nir_intrinsic_instr *instr)
{
const char *store_name;
LLVMValueRef src_data = get_src(ctx, instr->src[0]);
LLVMTypeRef data_type = ctx->f32;
int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
int components_32bit = elem_size_mult * instr->num_components;
unsigned writemask = nir_intrinsic_write_mask(instr);
LLVMValueRef base_data, base_offset;
LLVMValueRef params[6];
@ -2020,10 +2023,10 @@ static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
if (instr->num_components > 1)
data_type = LLVMVectorType(ctx->f32, instr->num_components);
if (components_32bit > 1)
data_type = LLVMVectorType(ctx->f32, components_32bit);
base_data = to_float(ctx, get_src(ctx, instr->src[0]));
base_data = to_float(ctx, src_data);
base_data = trim_vector(ctx, base_data, instr->num_components);
base_data = LLVMBuildBitCast(ctx->builder, base_data,
data_type, "");
@ -2042,6 +2045,14 @@ static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
count = 2;
}
start *= elem_size_mult;
count *= elem_size_mult;
if (count > 4) {
writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
count = 4;
}
if (count == 4) {
store_name = "llvm.amdgcn.buffer.store.v4f32";
data = base_data;