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r600g: rework and consolidate stencilref state setting

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Stop using the register mask.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2012-01-28 05:50:00 +01:00
parent 5345e3ea86
commit a2361946e7
4 changed files with 85 additions and 84 deletions
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48
src/gallium/drivers/r600/evergreen_state.c
View File

@ -799,20 +799,23 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
unsigned db_render_override, db_render_control;
struct r600_pipe_state *rstate;
if (dsa == NULL) {
return NULL;
}
dsa->valuemask[0] = state->stencil[0].valuemask;
dsa->valuemask[1] = state->stencil[1].valuemask;
dsa->writemask[0] = state->stencil[0].writemask;
dsa->writemask[1] = state->stencil[1].writemask;
rstate = &dsa->rstate;
rstate->id = R600_PIPE_STATE_DSA;
/* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
stencil_ref_mask = 0;
stencil_ref_mask_bf = 0;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
@ -825,17 +828,12 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
if (state->stencil[1].enabled) {
db_depth_control |= S_028800_BACKFACE_ENABLE(1);
db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
}
}
@ -858,12 +856,6 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028430_DB_STENCILREFMASK, stencil_ref_mask,
0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
/* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
@ -1298,32 +1290,6 @@ static void evergreen_set_scissor_state(struct pipe_context *ctx,
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
static void evergreen_set_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
u32 tmp;
if (rstate == NULL)
return;
rctx->stencil_ref = *state;
rstate->id = R600_PIPE_STATE_STENCIL_REF;
tmp = S_028430_STENCILREF(state->ref_value[0]);
r600_pipe_state_add_reg(rstate,
R_028430_DB_STENCILREFMASK, tmp,
~C_028430_STENCILREF, NULL, 0);
tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF, tmp,
~C_028434_STENCILREF_BF, NULL, 0);
free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
static void evergreen_set_viewport_state(struct pipe_context *ctx,
const struct pipe_viewport_state *state)
{
@ -1708,7 +1674,7 @@ void evergreen_init_state_functions(struct r600_pipe_context *rctx)
rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->context.set_sample_mask = evergreen_set_sample_mask;
rctx->context.set_scissor_state = evergreen_set_scissor_state;
rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
rctx->context.set_index_buffer = r600_set_index_buffer;
rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;

13
src/gallium/drivers/r600/r600_pipe.h
View File

@ -121,6 +121,8 @@ struct r600_pipe_blend {
struct r600_pipe_dsa {
struct r600_pipe_state rstate;
unsigned alpha_ref;
ubyte valuemask[2];
ubyte writemask[2];
};
struct r600_vertex_element
@ -183,6 +185,13 @@ struct r600_fence_block {
#define R600_CONSTANT_ARRAY_SIZE 256
#define R600_RESOURCE_ARRAY_SIZE 160
struct r600_stencil_ref
{
ubyte ref_value[2];
ubyte valuemask[2];
ubyte writemask[2];
};
struct r600_pipe_context {
struct pipe_context context;
struct blitter_context *blitter;
@ -364,8 +373,8 @@ void r600_set_so_targets(struct pipe_context *ctx,
unsigned num_targets,
struct pipe_stream_output_target **targets,
unsigned append_bitmask);
void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state);
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
/*

48
src/gallium/drivers/r600/r600_state.c
View File

@ -856,20 +856,23 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
unsigned db_render_override, db_render_control;
struct r600_pipe_state *rstate;
if (dsa == NULL) {
return NULL;
}
dsa->valuemask[0] = state->stencil[0].valuemask;
dsa->valuemask[1] = state->stencil[1].valuemask;
dsa->writemask[0] = state->stencil[0].writemask;
dsa->writemask[1] = state->stencil[1].writemask;
rstate = &dsa->rstate;
rstate->id = R600_PIPE_STATE_DSA;
/* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
stencil_ref_mask = 0;
stencil_ref_mask_bf = 0;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
@ -882,17 +885,12 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
if (state->stencil[1].enabled) {
db_depth_control |= S_028800_BACKFACE_ENABLE(1);
db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
}
}
@ -915,12 +913,6 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028430_DB_STENCILREFMASK, stencil_ref_mask,
0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
@ -1411,32 +1403,6 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
static void r600_set_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
u32 tmp;
if (rstate == NULL)
return;
rctx->stencil_ref = *state;
rstate->id = R600_PIPE_STATE_STENCIL_REF;
tmp = S_028430_STENCILREF(state->ref_value[0]);
r600_pipe_state_add_reg(rstate,
R_028430_DB_STENCILREFMASK, tmp,
~C_028430_STENCILREF, NULL, 0);
tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF, tmp,
~C_028434_STENCILREF_BF, NULL, 0);
free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
static void r600_set_viewport_state(struct pipe_context *ctx,
const struct pipe_viewport_state *state)
{
@ -1785,7 +1751,7 @@ void r600_init_state_functions(struct r600_pipe_context *rctx)
rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
rctx->context.set_sample_mask = r600_set_sample_mask;
rctx->context.set_scissor_state = r600_set_scissor_state;
rctx->context.set_stencil_ref = r600_set_stencil_ref;
rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
rctx->context.set_index_buffer = r600_set_index_buffer;
rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;

60
src/gallium/drivers/r600/r600_state_common.c
View File

@ -76,11 +76,62 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state)
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
static void r600_set_stencil_ref(struct pipe_context *ctx,
const struct r600_stencil_ref *state)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
if (rstate == NULL)
return;
rstate->id = R600_PIPE_STATE_STENCIL_REF;
r600_pipe_state_add_reg(rstate,
R_028430_DB_STENCILREFMASK,
S_028430_STENCILREF(state->ref_value[0]) |
S_028430_STENCILMASK(state->valuemask[0]) |
S_028430_STENCILWRITEMASK(state->writemask[0]),
0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF,
S_028434_STENCILREF_BF(state->ref_value[1]) |
S_028434_STENCILMASK_BF(state->valuemask[1]) |
S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
0xFFFFFFFF, NULL, 0);
free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
const struct pipe_stencil_ref *state)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
struct r600_stencil_ref ref;
rctx->stencil_ref = *state;
if (!dsa)
return;
ref.ref_value[0] = state->ref_value[0];
ref.ref_value[1] = state->ref_value[1];
ref.valuemask[0] = dsa->valuemask[0];
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
}
void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_dsa *dsa = state;
struct r600_pipe_state *rstate;
struct r600_stencil_ref ref;
if (state == NULL)
return;
@ -89,6 +140,15 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
rctx->alpha_ref = dsa->alpha_ref;
rctx->alpha_ref_dirty = true;
r600_context_pipe_state_set(&rctx->ctx, rstate);
ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
ref.valuemask[0] = dsa->valuemask[0];
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
}
void r600_bind_rs_state(struct pipe_context *ctx, void *state)