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https://gitee.com/openharmony/third_party_mesa3d
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ac/surface: cache DCC retile maps (v2)
This reduces overhead when resizing windows or when allocating similar image sizes over and over again. v2: optimize the memory footprint of the cache Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
This commit is contained in:
Marek Olšák
Marge Bot
parent
4cf674c8f7
commit
bd553f0546
@ -29,9 +29,12 @@
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#include "amd_family.h"
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#include "addrlib/src/amdgpu_asic_addr.h"
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#include "ac_gpu_info.h"
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#include "util/hash_table.h"
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#include "util/macros.h"
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#include "util/simple_mtx.h"
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#include "util/u_atomic.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include "sid.h"
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#include <errno.h>
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@ -52,8 +55,143 @@
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struct ac_addrlib {
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ADDR_HANDLE handle;
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/* The cache of DCC retile maps for reuse when allocating images of
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* similar sizes.
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*/
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simple_mtx_t dcc_retile_map_lock;
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struct hash_table *dcc_retile_maps;
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};
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struct dcc_retile_map_key {
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enum radeon_family family;
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unsigned retile_width;
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unsigned retile_height;
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bool rb_aligned;
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bool pipe_aligned;
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unsigned dcc_retile_num_elements;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT input;
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};
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static uint32_t dcc_retile_map_hash_key(const void *key)
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{
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return _mesa_hash_data(key, sizeof(struct dcc_retile_map_key));
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}
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static bool dcc_retile_map_keys_equal(const void *a, const void *b)
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{
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return memcmp(a, b, sizeof(struct dcc_retile_map_key)) == 0;
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}
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static void dcc_retile_map_free(struct hash_entry *entry)
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{
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free((void*)entry->key);
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free(entry->data);
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}
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static uint32_t *ac_compute_dcc_retile_map(struct ac_addrlib *addrlib,
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const struct radeon_info *info,
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unsigned retile_width, unsigned retile_height,
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bool rb_aligned, bool pipe_aligned, bool use_uint16,
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unsigned dcc_retile_num_elements,
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const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT *in)
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{
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unsigned dcc_retile_map_size = dcc_retile_num_elements * (use_uint16 ? 2 : 4);
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struct dcc_retile_map_key key;
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assert(in->numFrags == 1 && in->numSlices == 1 && in->numMipLevels == 1);
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memset(&key, 0, sizeof(key));
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key.family = info->family;
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key.retile_width = retile_width;
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key.retile_height = retile_height;
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key.rb_aligned = rb_aligned;
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key.pipe_aligned = pipe_aligned;
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key.dcc_retile_num_elements = dcc_retile_num_elements;
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memcpy(&key.input, in, sizeof(*in));
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simple_mtx_lock(&addrlib->dcc_retile_map_lock);
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/* If we have already computed this retile map, get it from the hash table. */
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struct hash_entry *entry = _mesa_hash_table_search(addrlib->dcc_retile_maps, &key);
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if (entry) {
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uint32_t *map = entry->data;
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return map;
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}
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin;
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memcpy(&addrin, in, sizeof(*in));
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
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addrout.size = sizeof(addrout);
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void *dcc_retile_map = malloc(dcc_retile_map_size);
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if (!dcc_retile_map) {
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return NULL;
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}
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unsigned index = 0;
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for (unsigned y = 0; y < retile_height; y += in->compressBlkHeight) {
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addrin.y = y;
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for (unsigned x = 0; x < retile_width; x += in->compressBlkWidth) {
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addrin.x = x;
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/* Compute src DCC address */
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addrin.dccKeyFlags.pipeAligned = pipe_aligned;
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addrin.dccKeyFlags.rbAligned = rb_aligned;
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addrout.addr = 0;
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if (Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout) != ADDR_OK) {
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return NULL;
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}
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if (use_uint16)
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((uint16_t*)dcc_retile_map)[index * 2] = addrout.addr;
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else
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((uint32_t*)dcc_retile_map)[index * 2] = addrout.addr;
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/* Compute dst DCC address */
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addrin.dccKeyFlags.pipeAligned = 0;
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addrin.dccKeyFlags.rbAligned = 0;
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addrout.addr = 0;
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if (Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout) != ADDR_OK) {
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return NULL;
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}
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if (use_uint16)
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((uint16_t*)dcc_retile_map)[index * 2 + 1] = addrout.addr;
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else
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((uint32_t*)dcc_retile_map)[index * 2 + 1] = addrout.addr;
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assert(index * 2 + 1 < dcc_retile_num_elements);
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index++;
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}
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}
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/* Fill the remaining pairs with the last one (for the compute shader). */
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for (unsigned i = index * 2; i < dcc_retile_num_elements; i++) {
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if (use_uint16)
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((uint16_t*)dcc_retile_map)[i] = ((uint16_t*)dcc_retile_map)[i - 2];
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else
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((uint32_t*)dcc_retile_map)[i] = ((uint32_t*)dcc_retile_map)[i - 2];
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}
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/* Insert the retile map into the hash table, so that it can be reused and
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* the computation can be skipped for similar image sizes.
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*/
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_mesa_hash_table_insert(addrlib->dcc_retile_maps,
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mem_dup(&key, sizeof(key)), dcc_retile_map);
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return dcc_retile_map;
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}
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static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
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{
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return malloc(pInput->sizeInBytes);
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@ -135,12 +273,17 @@ struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info,
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}
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addrlib->handle = addrCreateOutput.hLib;
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simple_mtx_init(&addrlib->dcc_retile_map_lock, mtx_plain);
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addrlib->dcc_retile_maps = _mesa_hash_table_create(NULL, dcc_retile_map_hash_key,
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dcc_retile_map_keys_equal);
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return addrlib;
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}
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void ac_addrlib_destroy(struct ac_addrlib *addrlib)
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{
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AddrDestroy(addrlib->handle);
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simple_mtx_destroy(&addrlib->dcc_retile_map_lock);
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_mesa_hash_table_destroy(addrlib->dcc_retile_maps, dcc_retile_map_free);
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free(addrlib);
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}
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@ -1376,16 +1519,60 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
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surf->u.gfx9.dcc_retile_use_uint16 =
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surf->u.gfx9.display_dcc_size <= UINT16_MAX + 1 &&
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surf->dcc_size <= UINT16_MAX + 1;
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/* Align the retile map size to get more hash table hits and
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* decrease the maximum memory footprint when all retile maps
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* are cached in the hash table.
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*/
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unsigned retile_dim[2] = {in->width, in->height};
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for (unsigned i = 0; i < 2; i++) {
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/* Increase the alignment as the size increases.
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* Greater alignment increases retile compute work,
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* but decreases maximum memory footprint for the cache.
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*
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* With this alignment, the worst case memory footprint of
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* the cache is:
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* 1920x1080: 55 MB
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* 2560x1440: 99 MB
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* 3840x2160: 305 MB
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*
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* The worst case size in MB can be computed in Haskell as follows:
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* (sum (map get_retile_size (map get_dcc_size (deduplicate (map align_pair
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* [(i*16,j*16) | i <- [1..maxwidth`div`16], j <- [1..maxheight`div`16]]))))) `div` 1024^2
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* where
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* alignment x = if x <= 512 then 16 else if x <= 1024 then 32 else if x <= 2048 then 64 else 128
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* align x = (x + (alignment x) - 1) `div` (alignment x) * (alignment x)
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* align_pair e = (align (fst e), align (snd e))
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* deduplicate = map head . groupBy (\ a b -> ((fst a) == (fst b)) && ((snd a) == (snd b))) . sortBy compare
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* get_dcc_size e = ((fst e) * (snd e) * bpp) `div` 256
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* get_retile_size dcc_size = dcc_size * 2 * (if dcc_size <= 2^16 then 2 else 4)
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* bpp = 4; maxwidth = 3840; maxheight = 2160
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*/
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if (retile_dim[i] <= 512)
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retile_dim[i] = align(retile_dim[i], 16);
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else if (retile_dim[i] <= 1024)
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retile_dim[i] = align(retile_dim[i], 32);
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else if (retile_dim[i] <= 2048)
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retile_dim[i] = align(retile_dim[i], 64);
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else
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retile_dim[i] = align(retile_dim[i], 128);
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/* Don't align more than the DCC pixel alignment. */
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assert(dout.metaBlkWidth >= 128 && dout.metaBlkHeight >= 128);
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}
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surf->u.gfx9.dcc_retile_num_elements =
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DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
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DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
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DIV_ROUND_UP(retile_dim[0], dout.compressBlkWidth) *
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DIV_ROUND_UP(retile_dim[1], dout.compressBlkHeight) * 2;
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/* Align the size to 4 (for the compute shader). */
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surf->u.gfx9.dcc_retile_num_elements =
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align(surf->u.gfx9.dcc_retile_num_elements, 4);
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if (!(surf->flags & RADEON_SURF_IMPORTED)) {
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/* Compute address mapping from non-displayable to displayable DCC. */
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin;
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memset(&addrin, 0, sizeof(addrin));
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addrin.size = sizeof(addrin);
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addrin.swizzleMode = din.swizzleMode;
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addrin.resourceType = din.resourceType;
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@ -1401,53 +1588,18 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
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addrin.metaBlkWidth = dout.metaBlkWidth;
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addrin.metaBlkHeight = dout.metaBlkHeight;
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addrin.metaBlkDepth = dout.metaBlkDepth;
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addrin.dccRamSliceSize = dout.dccRamSliceSize;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
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addrout.size = sizeof(addrout);
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addrin.dccRamSliceSize = 0; /* Don't care for non-layered images. */
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surf->u.gfx9.dcc_retile_map =
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malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
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ac_compute_dcc_retile_map(addrlib, info,
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retile_dim[0], retile_dim[1],
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surf->u.gfx9.dcc.rb_aligned,
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surf->u.gfx9.dcc.pipe_aligned,
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surf->u.gfx9.dcc_retile_use_uint16,
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surf->u.gfx9.dcc_retile_num_elements,
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&addrin);
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if (!surf->u.gfx9.dcc_retile_map)
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return ADDR_OUTOFMEMORY;
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unsigned index = 0;
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for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
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addrin.y = y;
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for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
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addrin.x = x;
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/* Compute src DCC address */
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addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
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addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
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addrout.addr = 0;
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ret = Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout);
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if (ret != ADDR_OK)
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return ret;
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surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
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/* Compute dst DCC address */
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addrin.dccKeyFlags.pipeAligned = 0;
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addrin.dccKeyFlags.rbAligned = 0;
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addrout.addr = 0;
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ret = Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout);
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if (ret != ADDR_OK)
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return ret;
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surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
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assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
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index++;
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}
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}
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/* Fill the remaining pairs with the last one (for the compute shader). */
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for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
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surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
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}
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}
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}
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@ -179,7 +179,7 @@ struct gfx9_surf_layout {
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uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */
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bool dcc_retile_use_uint16; /* if all values fit into uint16_t */
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uint32_t dcc_retile_num_elements;
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uint32_t *dcc_retile_map;
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void *dcc_retile_map;
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};
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struct radeon_surf {
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@ -802,13 +802,9 @@ static bool si_texture_get_handle(struct pipe_screen *screen, struct pipe_contex
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static void si_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex)
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{
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struct si_screen *sscreen = (struct si_screen *)screen;
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struct si_texture *tex = (struct si_texture *)ptex;
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struct si_resource *resource = &tex->buffer;
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if (sscreen->info.chip_class >= GFX9)
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free(tex->surface.u.gfx9.dcc_retile_map);
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si_texture_reference(&tex->flushed_depth_texture, NULL);
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if (tex->cmask_buffer != &tex->buffer) {
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@ -1163,20 +1159,14 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
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*/
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bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16;
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unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements;
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unsigned dcc_retile_map_size = num_elements * (use_uint16 ? 2 : 4);
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struct si_resource *buf = si_aligned_buffer_create(screen, 0, PIPE_USAGE_STREAM,
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num_elements * (use_uint16 ? 2 : 4),
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dcc_retile_map_size,
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sscreen->info.tcc_cache_line_size);
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uint32_t *ui = (uint32_t *)sscreen->ws->buffer_map(buf->buf, NULL, PIPE_TRANSFER_WRITE);
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uint16_t *us = (uint16_t *)ui;
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void *map = sscreen->ws->buffer_map(buf->buf, NULL, PIPE_TRANSFER_WRITE);
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/* Upload the retile map into a staging buffer. */
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if (use_uint16) {
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for (unsigned i = 0; i < num_elements; i++)
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us[i] = tex->surface.u.gfx9.dcc_retile_map[i];
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} else {
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for (unsigned i = 0; i < num_elements; i++)
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ui[i] = tex->surface.u.gfx9.dcc_retile_map[i];
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}
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/* Upload the retile map into the staging buffer. */
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memcpy(map, tex->surface.u.gfx9.dcc_retile_map, dcc_retile_map_size);
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/* Copy the staging buffer to the buffer backing the texture. */
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struct si_context *sctx = (struct si_context *)sscreen->aux_context;
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@ -1218,8 +1208,6 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
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error:
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FREE(tex);
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if (sscreen->info.chip_class >= GFX9)
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free(surface->u.gfx9.dcc_retile_map);
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return NULL;
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}
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