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nir: Rename nir_address_format_vk_index_offset to not be vk
It's just a 32-bit index and offset. We're going to want to use it in GL as well so stop talking about Vulkan. Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
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@ -3021,9 +3021,9 @@ typedef enum {
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/**
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* An address format which is comprised of a vec2 where the first
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* component is a vulkan descriptor index and the second is an offset.
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* component is a buffer index and the second is an offset.
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*/
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nir_address_format_vk_index_offset,
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nir_address_format_32bit_index_offset,
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} nir_address_format;
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bool nir_lower_explicit_io(nir_shader *shader,
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nir_variable_mode modes,
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@ -599,7 +599,7 @@ build_addr_iadd(nir_builder *b, nir_ssa_def *addr,
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assert(addr->num_components == 1);
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return nir_iadd(b, addr, offset);
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case nir_address_format_vk_index_offset:
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case nir_address_format_32bit_index_offset:
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assert(addr->num_components == 2);
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return nir_vec2(b, nir_channel(b, addr, 0),
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nir_iadd(b, nir_channel(b, addr, 1), offset));
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@ -619,7 +619,7 @@ static nir_ssa_def *
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addr_to_index(nir_builder *b, nir_ssa_def *addr,
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nir_address_format addr_format)
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{
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assert(addr_format == nir_address_format_vk_index_offset);
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assert(addr_format == nir_address_format_32bit_index_offset);
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assert(addr->num_components == 2);
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return nir_channel(b, addr, 0);
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}
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@ -628,7 +628,7 @@ static nir_ssa_def *
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addr_to_offset(nir_builder *b, nir_ssa_def *addr,
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nir_address_format addr_format)
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{
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assert(addr_format == nir_address_format_vk_index_offset);
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assert(addr_format == nir_address_format_32bit_index_offset);
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assert(addr->num_components == 2);
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return nir_channel(b, addr, 1);
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}
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@ -651,7 +651,7 @@ addr_to_global(nir_builder *b, nir_ssa_def *addr,
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assert(addr->num_components == 1);
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return addr;
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case nir_address_format_vk_index_offset:
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case nir_address_format_32bit_index_offset:
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unreachable("Cannot get a 64-bit address with this address format");
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}
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@ -168,7 +168,7 @@ lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
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index = nir_imm_ivec2(b, state->set[set].desc_offset,
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bind_layout->descriptor_offset);
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} else {
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/* We're using nir_address_format_vk_index_offset */
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/* We're using nir_address_format_32bit_index_offset */
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index = nir_vec2(b, nir_iadd_imm(b, array_index, surface_index),
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nir_imm_int(b, 0));
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}
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@ -211,7 +211,7 @@ lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin,
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b->cursor = nir_before_instr(&intrin->instr);
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/* We follow the nir_address_format_vk_index_offset model */
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/* We follow the nir_address_format_32bit_index_offset model */
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assert(intrin->src[0].is_ssa);
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nir_ssa_def *index = intrin->src[0].ssa;
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@ -231,7 +231,7 @@ lower_get_buffer_size(nir_intrinsic_instr *intrin,
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assert(intrin->src[0].is_ssa);
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nir_ssa_def *index = intrin->src[0].ssa;
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/* We're following the nir_address_format_vk_index_offset model so the
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/* We're following the nir_address_format_32bit_index_offset model so the
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* binding table index is the first component of the address. The
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* back-end wants a scalar binding table index source.
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*/
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@ -600,7 +600,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
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NIR_PASS_V(nir, nir_lower_explicit_io,
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nir_var_mem_ubo | nir_var_mem_ssbo,
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nir_address_format_vk_index_offset);
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nir_address_format_32bit_index_offset);
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NIR_PASS_V(nir, nir_opt_constant_folding);
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}
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