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intel/dev: fix HSW GT3 number of subslices in slice1

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10015>
This commit is contained in:
Lionel Landwerlin 2021-04-03 13:22:50 +03:00 committed by Marge Bot
parent 12294026d5
commit d1db5d562a
1 changed files with 1 additions and 1 deletions
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2
src/intel/dev/intel_device_info.c
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@ -373,7 +373,7 @@ static const struct intel_device_info intel_device_info_hsw_gt2 = {
static const struct intel_device_info intel_device_info_hsw_gt3 = {
HSW_FEATURES, .gt = 3,
.num_slices = 2,
.num_subslices = { 2, },
.num_subslices = { 2, 2, },
.num_eu_per_subslice = 10,
.num_thread_per_eu = 7,
.l3_banks = 8,