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i965/skl: Add fast color clear infrastructure
Patch was originally called:
i965/skl: Enable fast color clears on SKL
Skylake introduces some differences in the way that fast clears are programmed
and in the restrictions for using fast clears. Since some of these are
non-obvious, and fast clears are currently disabled globally, we can enable the
simple stuff here and leave the weirder stuff and separately reviewable work.
Based on a patch originally from Kristian.
Note that within this patch the change in scaling factors could be achieved with
this hunk instead. I've opted to keep things more like how the docs describe it
however.
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -150,9 +150,13 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
/* In release builds, fall through */
case I915_TILING_Y:
*width_px = 32 / mt->cpp;
- *height = 4;
+ if (brw->gen >= 9)
+ *height = 2;
+ else
+ *height = 4;
v2: Add braces for the multiline (Matt + Chad)
Comment updates (requested by Chad)
Modified commit message
Commit message from Chad explaining the MCS height change (Chad)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Ben Widawsky
parent
2f7d2fd997
commit
d23aa634e0
@ -204,7 +204,7 @@ brw_draw_rectlist(struct gl_context *ctx, struct rect *rect, int num_instances)
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}
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static void
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get_fast_clear_rect(struct gl_framebuffer *fb,
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get_fast_clear_rect(struct brw_context *brw, struct gl_framebuffer *fb,
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struct intel_renderbuffer *irb, struct rect *rect)
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{
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unsigned int x_align, y_align;
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@ -228,7 +228,14 @@ get_fast_clear_rect(struct gl_framebuffer *fb,
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*/
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intel_get_non_msrt_mcs_alignment(irb->mt, &x_align, &y_align);
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x_align *= 16;
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y_align *= 32;
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/* SKL+ line alignment requirement for Y-tiled are half those of the prior
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* generations.
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*/
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if (brw->gen >= 9)
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y_align *= 16;
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else
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y_align *= 32;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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@ -265,8 +272,10 @@ get_fast_clear_rect(struct gl_framebuffer *fb,
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* terms of (width,height) of the RT.
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*
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* MSAA Width of Clear Rect Height of Clear Rect
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* 2X Ceil(1/8*width) Ceil(1/2*height)
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* 4X Ceil(1/8*width) Ceil(1/2*height)
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* 8X Ceil(1/2*width) Ceil(1/2*height)
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* 16X width Ceil(1/2*height)
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*
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* The text "with upper left co-ordinate to coincide with actual
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* rectangle being cleared" is a little confusing--it seems to imply
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@ -289,6 +298,9 @@ get_fast_clear_rect(struct gl_framebuffer *fb,
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case 8:
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x_scaledown = 2;
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break;
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case 16:
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x_scaledown = 1;
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break;
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default:
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unreachable("Unexpected sample count for fast clear");
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}
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@ -357,18 +369,25 @@ is_color_fast_clear_compatible(struct brw_context *brw,
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/**
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* Convert the given color to a bitfield suitable for ORing into DWORD 7 of
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* SURFACE_STATE.
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* SURFACE_STATE (DWORD 12-15 on SKL+).
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*/
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static uint32_t
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compute_fast_clear_color_bits(const union gl_color_union *color)
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static void
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set_fast_clear_color(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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const union gl_color_union *color)
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{
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uint32_t bits = 0;
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for (int i = 0; i < 4; i++) {
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/* Testing for non-0 works for integer and float colors */
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if (color->f[i] != 0.0f)
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bits |= 1 << (GEN7_SURFACE_CLEAR_COLOR_SHIFT + (3 - i));
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if (brw->gen >= 9) {
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mt->gen9_fast_clear_color = *color;
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} else {
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mt->fast_clear_color_value = 0;
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for (int i = 0; i < 4; i++) {
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/* Testing for non-0 works for integer and float colors */
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if (color->f[i] != 0.0f) {
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mt->fast_clear_color_value |=
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1 << (GEN7_SURFACE_CLEAR_COLOR_SHIFT + (3 - i));
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}
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}
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}
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return bits;
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}
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static const uint32_t fast_clear_color[4] = { ~0, ~0, ~0, ~0 };
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@ -510,8 +529,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
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switch (clear_type) {
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case FAST_CLEAR:
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irb->mt->fast_clear_color_value =
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compute_fast_clear_color_bits(&ctx->Color.ClearColor);
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set_fast_clear_color(brw, irb->mt, &ctx->Color.ClearColor);
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irb->need_downsample = true;
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/* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the
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@ -527,7 +545,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
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irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
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irb->need_downsample = true;
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fast_clear_buffers |= 1 << index;
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get_fast_clear_rect(fb, irb, &fast_clear_rect);
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get_fast_clear_rect(brw, fb, irb, &fast_clear_rect);
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break;
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case REP_CLEAR:
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@ -662,8 +680,9 @@ get_resolve_rect(struct brw_context *brw,
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*
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* The scaledown factors in the table that follows are related to the
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* alignment size returned by intel_get_non_msrt_mcs_alignment() by a
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* multiplier. For IVB and HSW, we divide by two, for BDW we multiply
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* by 8 and 16 and 8 and 8 for SKL.
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* multiplier. For IVB and HSW, we divide by two, for BDW we multiply
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* by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical scaling
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* by a factor of 2.
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*/
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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@ -709,6 +728,10 @@ brw_meta_resolve_color(struct brw_context *brw,
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brw_bind_rep_write_shader(brw, (float *) fast_clear_color);
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/* SKL+ also has a resolve mode for compressed render targets and thus more
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* bits to let us select the type of resolve. For fast clear resolves, it
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* turns out we can use the same value as pre-SKL though.
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*/
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set_fast_clear_op(brw, GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE);
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mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
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@ -187,7 +187,21 @@ gen8_emit_fast_clear_color(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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uint32_t *surf)
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{
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surf[7] |= mt->fast_clear_color_value;
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if (brw->gen >= 9) {
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#define check_fast_clear_val(x) \
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assert(mt->gen9_fast_clear_color.f[x] == 0.0 || \
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mt->gen9_fast_clear_color.f[x] == 1.0)
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check_fast_clear_val(0);
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check_fast_clear_val(1);
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check_fast_clear_val(2);
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check_fast_clear_val(3);
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#undef check_fast_clear_val
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surf[12] = mt->gen9_fast_clear_color.ui[0];
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surf[13] = mt->gen9_fast_clear_color.ui[1];
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surf[14] = mt->gen9_fast_clear_color.ui[2];
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surf[15] = mt->gen9_fast_clear_color.ui[3];
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} else
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surf[7] |= mt->fast_clear_color_value;
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}
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static void
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@ -192,6 +192,12 @@ intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling)
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*
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* - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
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* 64bpp, and 128bpp.
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*
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* From the Skylake documentation, it is made clear that X-tiling is no longer
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* supported:
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*
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* - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
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* non-MSRTs only.
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*/
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static bool
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intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
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@ -1495,6 +1501,17 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
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intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height);
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unsigned width_divisor = block_width_px * 4;
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unsigned height_divisor = block_height * 8;
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/* The Skylake MCS is twice as tall as the Broadwell MCS.
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*
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* In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
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* in the main surface. In Skylake, it's two bits. The extra bit
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* doubles the MCS height, not width, because in Skylake the MCS is always
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* Y-tiled.
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*/
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if (brw->gen >= 9)
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height_divisor /= 2;
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unsigned mcs_width =
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ALIGN(mt->logical_width0, width_divisor) / width_divisor;
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unsigned mcs_height =
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@ -633,15 +633,22 @@ struct intel_mipmap_tree
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* The SURFACE_STATE bits associated with the last fast color clear to this
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* color mipmap tree, if any.
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*
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* This value will only ever contain ones in bits 28-31, so it is safe to
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* OR into dword 7 of SURFACE_STATE.
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* Prior to GEN9 there is a single bit for RGBA clear values which gives you
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* the option of 2^4 clear colors. Each bit determines if the color channel
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* is fully saturated or unsaturated (Cherryview does add a 32b value per
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* channel, but it is globally applied instead of being part of the render
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* surface state). Starting with GEN9, the surface state accepts a 32b value
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* for each color channel.
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*
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* @see RENDER_SURFACE_STATE.RedClearColor
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* @see RENDER_SURFACE_STATE.GreenClearColor
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* @see RENDER_SURFACE_STATE.BlueClearColor
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* @see RENDER_SURFACE_STATE.AlphaClearColor
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*/
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uint32_t fast_clear_color_value;
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union {
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uint32_t fast_clear_color_value;
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union gl_color_union gen9_fast_clear_color;
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};
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/**
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* Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
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